SM501: Clock updates and checks

Ensure that the M1XCLK and MCLK are sourced from the same PLL (and refuse to
bind the driver if they are not).

Update the PCI to safe initialisation values, as 72MHz is the maximum clock
for 33MHz PCI bus mastering.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 5 insertions, 0 deletions

diff --git a/include/linux/sm501-regs.h b/include/linux/sm501-regs.h
index cc9be4a11861..8b4ecf02f9dc 100644
--- a/include/linux/sm501-regs.h
+++ b/include/linux/sm501-regs.h
@@ -64,6 +64,11 @@
 #define SM501_DEBUG_CONTROL             (0x000034)
 
 /* power management */
+#define SM501_POWERMODE_P2X_SRC         (1<<29)
+#define SM501_POWERMODE_V2X_SRC         (1<<20)
+#define SM501_POWERMODE_M_SRC           (1<<12)
+#define SM501_POWERMODE_M1_SRC          (1<<4)
+
 #define SM501_CURRENT_GATE              (0x000038)
 #define SM501_CURRENT_CLOCK             (0x00003C)
 #define SM501_POWER_MODE_0_GATE         (0x000040)