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authorThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 05:37:03 -0400
committerThomas Gleixner <tglx@cruncher.tec.linutronix.de>2006-05-23 05:37:03 -0400
commita36ed2995c56d4f858ecb524a78837473e7115ae (patch)
tree510f31485713ae5be63a20fe29b3809f0fafbbb8 /include
parent819d6a32c397534c819d3c72a3947b7e7e4bec4b (diff)
[MTD] Simplify NAND locking
Replace the chip lock by a the controller lock. For simple drivers a dummy controller structure is created by the scan code. This simplifies the locking algorithm in nand_get/release_chip(). Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mtd/nand.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index da5e67b3fc70..b8792be3c4e0 100644
--- a/include/linux/mtd/nand.h
+++ b/include/linux/mtd/nand.h
@@ -227,6 +227,8 @@ extern int nand_read_raw (struct mtd_info *mtd, uint8_t *buf, loff_t from, size_
227#define NAND_SKIP_BBTSCAN 0x00040000 227#define NAND_SKIP_BBTSCAN 0x00040000
228 228
229/* Options set by nand scan */ 229/* Options set by nand scan */
230/* Nand scan has allocated controller struct */
231#define NAND_CONTROLLER_ALLOC 0x20000000
230/* Nand scan has allocated oob_buf */ 232/* Nand scan has allocated oob_buf */
231#define NAND_OOBBUF_ALLOC 0x40000000 233#define NAND_OOBBUF_ALLOC 0x40000000
232/* Nand scan has allocated data_buf */ 234/* Nand scan has allocated data_buf */
@@ -294,7 +296,6 @@ struct nand_hw_control {
294 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step 296 * @eccbytes: [INTERN] number of ecc bytes per ecc-calculation step
295 * @eccsteps: [INTERN] number of ecc calculation steps per page 297 * @eccsteps: [INTERN] number of ecc calculation steps per page
296 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR) 298 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
297 * @chip_lock: [INTERN] spinlock used to protect access to this structure and the chip
298 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress 299 * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
299 * @state: [INTERN] the current state of the NAND device 300 * @state: [INTERN] the current state of the NAND device
300 * @page_shift: [INTERN] number of address bits in a page (column address bits) 301 * @page_shift: [INTERN] number of address bits in a page (column address bits)
@@ -317,7 +318,8 @@ struct nand_hw_control {
317 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup 318 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
318 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor 319 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
319 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan 320 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
320 * @controller: [OPTIONAL] a pointer to a hardware controller structure which is shared among multiple independend devices 321 * @controller: [REPLACEABLE] a pointer to a hardware controller structure
322 * which is shared among multiple independend devices
321 * @priv: [OPTIONAL] pointer to private chip date 323 * @priv: [OPTIONAL] pointer to private chip date
322 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks 324 * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
323 * (determine if errors are correctable) 325 * (determine if errors are correctable)
@@ -352,7 +354,6 @@ struct nand_chip {
352 int eccbytes; 354 int eccbytes;
353 int eccsteps; 355 int eccsteps;
354 int chip_delay; 356 int chip_delay;
355 spinlock_t chip_lock;
356 wait_queue_head_t wq; 357 wait_queue_head_t wq;
357 nand_state_t state; 358 nand_state_t state;
358 int page_shift; 359 int page_shift;