diff options
author | Anton Blanchard <anton@samba.org> | 2006-06-10 06:18:39 -0400 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-06-15 05:31:25 -0400 |
commit | 3a2c48cfc97f9046abbd810f1efb1aa824bcfaf1 (patch) | |
tree | afcd54f2ad36353abcf2282fdf15a05e77fcba4a /include | |
parent | 30d8caf7c625203b295a78f143820cdc3124830b (diff) |
[POWERPC] 64bit FPSCR support
Forthcoming machines will extend the FPSCR to 64 bits. We already
had a 64-bit save area for the FPSCR, but we need to use a new form
of the mtfsf instruction. Fortunately this new form is decoded as
an ordinary mtfsf by existing 64-bit processors.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-powerpc/reg.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index 3779b21a7c71..bfc7dc14ffcc 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h | |||
@@ -499,6 +499,19 @@ | |||
499 | #define MMCR0_PMC2_LOADMISSTIME 0x5 | 499 | #define MMCR0_PMC2_LOADMISSTIME 0x5 |
500 | #endif | 500 | #endif |
501 | 501 | ||
502 | /* | ||
503 | * An mtfsf instruction with the L bit set. On CPUs that support this a | ||
504 | * full 64bits of FPSCR is restored and on other CPUs it is ignored. | ||
505 | * | ||
506 | * Until binutils gets the new form of mtfsf, hardwire the instruction. | ||
507 | */ | ||
508 | #ifdef CONFIG_PPC64 | ||
509 | #define MTFSF_L(REG) \ | ||
510 | .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25)) | ||
511 | #else | ||
512 | #define MTFSF_L(REG) mtfsf 0xff, (REG) | ||
513 | #endif | ||
514 | |||
502 | /* Processor Version Register (PVR) field extraction */ | 515 | /* Processor Version Register (PVR) field extraction */ |
503 | 516 | ||
504 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ | 517 | #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ |