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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-27 13:05:42 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-27 13:05:42 -0400
commitfc67b16ecaf6ebde04096030c268adddade023f1 (patch)
tree1cce42cdca1fc9e4ec41b9f7f72c60e343cebca7 /include
parente8108c98dd6d65613fa0ec9d2300f89c48d554bf (diff)
parent2d29306b231a1a0e7a70166c10e4c0f917b21334 (diff)
Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/aegl/linux-2.6.git
Diffstat (limited to 'include')
-rw-r--r--include/asm-ia64/hw_irq.h1
-rw-r--r--include/asm-ia64/pal.h68
-rw-r--r--include/asm-ia64/perfmon.h12
-rw-r--r--include/asm-ia64/pgalloc.h148
-rw-r--r--include/asm-ia64/processor.h10
-rw-r--r--include/asm-ia64/sal.h12
-rw-r--r--include/asm-ia64/smp.h5
-rw-r--r--include/asm-ia64/sn/addrs.h6
-rw-r--r--include/asm-ia64/sn/bte.h53
-rw-r--r--include/asm-ia64/sn/geo.h45
-rw-r--r--include/asm-ia64/sn/nodepda.h4
-rw-r--r--include/asm-ia64/sn/pcibus_provider_defs.h52
-rw-r--r--include/asm-ia64/sn/pcidev.h58
-rw-r--r--include/asm-ia64/sn/pda.h3
-rw-r--r--include/asm-ia64/sn/shub_mmr.h37
-rw-r--r--include/asm-ia64/sn/sn_sal.h46
-rw-r--r--include/asm-ia64/sn/tioca.h596
-rw-r--r--include/asm-ia64/sn/tioca_provider.h206
-rw-r--r--include/asm-ia64/sn/tiocx.h71
-rw-r--r--include/asm-ia64/sn/types.h3
20 files changed, 1314 insertions, 122 deletions
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
index 041ab8c51a64..cd4e06b74ab6 100644
--- a/include/asm-ia64/hw_irq.h
+++ b/include/asm-ia64/hw_irq.h
@@ -81,6 +81,7 @@ extern __u8 isa_irq_to_vector_map[16];
81 81
82extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */ 82extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
83 83
84extern int assign_irq_vector_nopanic (int irq); /* allocate a free vector without panic */
84extern int assign_irq_vector (int irq); /* allocate a free vector */ 85extern int assign_irq_vector (int irq); /* allocate a free vector */
85extern void free_irq_vector (int vector); 86extern void free_irq_vector (int vector);
86extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect); 87extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 5dd477ffb88e..2303a10ee595 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -67,6 +67,7 @@
67#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/ 67#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
68#define PAL_SHUTDOWN 40 /* enter processor shutdown state */ 68#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
69#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */ 69#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
70#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
70 71
71#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */ 72#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
72#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */ 73#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
@@ -1559,6 +1560,73 @@ ia64_pal_prefetch_visibility (s64 trans_type)
1559 return iprv.status; 1560 return iprv.status;
1560} 1561}
1561 1562
1563/* data structure for getting information on logical to physical mappings */
1564typedef union pal_log_overview_u {
1565 struct {
1566 u64 num_log :16, /* Total number of logical
1567 * processors on this die
1568 */
1569 tpc :8, /* Threads per core */
1570 reserved3 :8, /* Reserved */
1571 cpp :8, /* Cores per processor */
1572 reserved2 :8, /* Reserved */
1573 ppid :8, /* Physical processor ID */
1574 reserved1 :8; /* Reserved */
1575 } overview_bits;
1576 u64 overview_data;
1577} pal_log_overview_t;
1578
1579typedef union pal_proc_n_log_info1_u{
1580 struct {
1581 u64 tid :16, /* Thread id */
1582 reserved2 :16, /* Reserved */
1583 cid :16, /* Core id */
1584 reserved1 :16; /* Reserved */
1585 } ppli1_bits;
1586 u64 ppli1_data;
1587} pal_proc_n_log_info1_t;
1588
1589typedef union pal_proc_n_log_info2_u {
1590 struct {
1591 u64 la :16, /* Logical address */
1592 reserved :48; /* Reserved */
1593 } ppli2_bits;
1594 u64 ppli2_data;
1595} pal_proc_n_log_info2_t;
1596
1597typedef struct pal_logical_to_physical_s
1598{
1599 pal_log_overview_t overview;
1600 pal_proc_n_log_info1_t ppli1;
1601 pal_proc_n_log_info2_t ppli2;
1602} pal_logical_to_physical_t;
1603
1604#define overview_num_log overview.overview_bits.num_log
1605#define overview_tpc overview.overview_bits.tpc
1606#define overview_cpp overview.overview_bits.cpp
1607#define overview_ppid overview.overview_bits.ppid
1608#define log1_tid ppli1.ppli1_bits.tid
1609#define log1_cid ppli1.ppli1_bits.cid
1610#define log2_la ppli2.ppli2_bits.la
1611
1612/* Get information on logical to physical processor mappings. */
1613static inline s64
1614ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1615{
1616 struct ia64_pal_retval iprv;
1617
1618 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1619
1620 if (iprv.status == PAL_STATUS_SUCCESS)
1621 {
1622 if (proc_number == 0)
1623 mapping->overview.overview_data = iprv.v0;
1624 mapping->ppli1.ppli1_data = iprv.v1;
1625 mapping->ppli2.ppli2_data = iprv.v2;
1626 }
1627
1628 return iprv.status;
1629}
1562#endif /* __ASSEMBLY__ */ 1630#endif /* __ASSEMBLY__ */
1563 1631
1564#endif /* _ASM_IA64_PAL_H */ 1632#endif /* _ASM_IA64_PAL_H */
diff --git a/include/asm-ia64/perfmon.h b/include/asm-ia64/perfmon.h
index 136c60e6bfcc..ed5416c5b1ac 100644
--- a/include/asm-ia64/perfmon.h
+++ b/include/asm-ia64/perfmon.h
@@ -254,6 +254,18 @@ extern int pfm_mod_write_dbrs(struct task_struct *task, void *req, unsigned int
254#define PFM_CPUINFO_DCR_PP 0x2 /* if set the system wide session has started */ 254#define PFM_CPUINFO_DCR_PP 0x2 /* if set the system wide session has started */
255#define PFM_CPUINFO_EXCL_IDLE 0x4 /* the system wide session excludes the idle task */ 255#define PFM_CPUINFO_EXCL_IDLE 0x4 /* the system wide session excludes the idle task */
256 256
257/*
258 * sysctl control structure. visible to sampling formats
259 */
260typedef struct {
261 int debug; /* turn on/off debugging via syslog */
262 int debug_ovfl; /* turn on/off debug printk in overflow handler */
263 int fastctxsw; /* turn on/off fast (unsecure) ctxsw */
264 int expert_mode; /* turn on/off value checking */
265} pfm_sysctl_t;
266extern pfm_sysctl_t pfm_sysctl;
267
268
257#endif /* __KERNEL__ */ 269#endif /* __KERNEL__ */
258 270
259#endif /* _ASM_IA64_PERFMON_H */ 271#endif /* _ASM_IA64_PERFMON_H */
diff --git a/include/asm-ia64/pgalloc.h b/include/asm-ia64/pgalloc.h
index 0f05dc8bd460..a5f214554afd 100644
--- a/include/asm-ia64/pgalloc.h
+++ b/include/asm-ia64/pgalloc.h
@@ -22,146 +22,124 @@
22 22
23#include <asm/mmu_context.h> 23#include <asm/mmu_context.h>
24 24
25/* 25DECLARE_PER_CPU(unsigned long *, __pgtable_quicklist);
26 * Very stupidly, we used to get new pgd's and pmd's, init their contents 26#define pgtable_quicklist __ia64_per_cpu_var(__pgtable_quicklist)
27 * to point to the NULL versions of the next level page table, later on 27DECLARE_PER_CPU(long, __pgtable_quicklist_size);
28 * completely re-init them the same way, then free them up. This wasted 28#define pgtable_quicklist_size __ia64_per_cpu_var(__pgtable_quicklist_size)
29 * a lot of work and caused unnecessary memory traffic. How broken...
30 * We fix this by caching them.
31 */
32#define pgd_quicklist (local_cpu_data->pgd_quick)
33#define pmd_quicklist (local_cpu_data->pmd_quick)
34#define pgtable_cache_size (local_cpu_data->pgtable_cache_sz)
35 29
36static inline pgd_t* 30static inline long pgtable_quicklist_total_size(void)
37pgd_alloc_one_fast (struct mm_struct *mm) 31{
32 long ql_size = 0;
33 int cpuid;
34
35 for_each_online_cpu(cpuid) {
36 ql_size += per_cpu(__pgtable_quicklist_size, cpuid);
37 }
38 return ql_size;
39}
40
41static inline void *pgtable_quicklist_alloc(void)
38{ 42{
39 unsigned long *ret = NULL; 43 unsigned long *ret = NULL;
40 44
41 preempt_disable(); 45 preempt_disable();
42 46
43 ret = pgd_quicklist; 47 ret = pgtable_quicklist;
44 if (likely(ret != NULL)) { 48 if (likely(ret != NULL)) {
45 pgd_quicklist = (unsigned long *)(*ret); 49 pgtable_quicklist = (unsigned long *)(*ret);
46 ret[0] = 0; 50 ret[0] = 0;
47 --pgtable_cache_size; 51 --pgtable_quicklist_size;
48 } else 52 preempt_enable();
49 ret = NULL; 53 } else {
50 54 preempt_enable();
51 preempt_enable(); 55 ret = (unsigned long *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
56 }
52 57
53 return (pgd_t *) ret; 58 return ret;
54} 59}
55 60
56static inline pgd_t* 61static inline void pgtable_quicklist_free(void *pgtable_entry)
57pgd_alloc (struct mm_struct *mm)
58{ 62{
59 /* the VM system never calls pgd_alloc_one_fast(), so we do it here. */ 63#ifdef CONFIG_NUMA
60 pgd_t *pgd = pgd_alloc_one_fast(mm); 64 unsigned long nid = page_to_nid(virt_to_page(pgtable_entry));
61 65
62 if (unlikely(pgd == NULL)) { 66 if (unlikely(nid != numa_node_id())) {
63 pgd = (pgd_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO); 67 free_page((unsigned long)pgtable_entry);
68 return;
64 } 69 }
65 return pgd; 70#endif
66}
67 71
68static inline void
69pgd_free (pgd_t *pgd)
70{
71 preempt_disable(); 72 preempt_disable();
72 *(unsigned long *)pgd = (unsigned long) pgd_quicklist; 73 *(unsigned long *)pgtable_entry = (unsigned long)pgtable_quicklist;
73 pgd_quicklist = (unsigned long *) pgd; 74 pgtable_quicklist = (unsigned long *)pgtable_entry;
74 ++pgtable_cache_size; 75 ++pgtable_quicklist_size;
75 preempt_enable(); 76 preempt_enable();
76} 77}
77 78
78static inline void 79static inline pgd_t *pgd_alloc(struct mm_struct *mm)
79pud_populate (struct mm_struct *mm, pud_t *pud_entry, pmd_t *pmd)
80{ 80{
81 pud_val(*pud_entry) = __pa(pmd); 81 return pgtable_quicklist_alloc();
82} 82}
83 83
84static inline pmd_t* 84static inline void pgd_free(pgd_t * pgd)
85pmd_alloc_one_fast (struct mm_struct *mm, unsigned long addr)
86{ 85{
87 unsigned long *ret = NULL; 86 pgtable_quicklist_free(pgd);
88
89 preempt_disable();
90
91 ret = (unsigned long *)pmd_quicklist;
92 if (likely(ret != NULL)) {
93 pmd_quicklist = (unsigned long *)(*ret);
94 ret[0] = 0;
95 --pgtable_cache_size;
96 }
97
98 preempt_enable();
99
100 return (pmd_t *)ret;
101} 87}
102 88
103static inline pmd_t* 89static inline void
104pmd_alloc_one (struct mm_struct *mm, unsigned long addr) 90pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
105{ 91{
106 pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); 92 pud_val(*pud_entry) = __pa(pmd);
93}
107 94
108 return pmd; 95static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
96{
97 return pgtable_quicklist_alloc();
109} 98}
110 99
111static inline void 100static inline void pmd_free(pmd_t * pmd)
112pmd_free (pmd_t *pmd)
113{ 101{
114 preempt_disable(); 102 pgtable_quicklist_free(pmd);
115 *(unsigned long *)pmd = (unsigned long) pmd_quicklist;
116 pmd_quicklist = (unsigned long *) pmd;
117 ++pgtable_cache_size;
118 preempt_enable();
119} 103}
120 104
121#define __pmd_free_tlb(tlb, pmd) pmd_free(pmd) 105#define __pmd_free_tlb(tlb, pmd) pmd_free(pmd)
122 106
123static inline void 107static inline void
124pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, struct page *pte) 108pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, struct page *pte)
125{ 109{
126 pmd_val(*pmd_entry) = page_to_phys(pte); 110 pmd_val(*pmd_entry) = page_to_phys(pte);
127} 111}
128 112
129static inline void 113static inline void
130pmd_populate_kernel (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte) 114pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte)
131{ 115{
132 pmd_val(*pmd_entry) = __pa(pte); 116 pmd_val(*pmd_entry) = __pa(pte);
133} 117}
134 118
135static inline struct page * 119static inline struct page *pte_alloc_one(struct mm_struct *mm,
136pte_alloc_one (struct mm_struct *mm, unsigned long addr) 120 unsigned long addr)
137{ 121{
138 struct page *pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); 122 return virt_to_page(pgtable_quicklist_alloc());
139
140 return pte;
141} 123}
142 124
143static inline pte_t * 125static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
144pte_alloc_one_kernel (struct mm_struct *mm, unsigned long addr) 126 unsigned long addr)
145{ 127{
146 pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO); 128 return pgtable_quicklist_alloc();
147
148 return pte;
149} 129}
150 130
151static inline void 131static inline void pte_free(struct page *pte)
152pte_free (struct page *pte)
153{ 132{
154 __free_page(pte); 133 pgtable_quicklist_free(page_address(pte));
155} 134}
156 135
157static inline void 136static inline void pte_free_kernel(pte_t * pte)
158pte_free_kernel (pte_t *pte)
159{ 137{
160 free_page((unsigned long) pte); 138 pgtable_quicklist_free(pte);
161} 139}
162 140
163#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte)) 141#define __pte_free_tlb(tlb, pte) pte_free(pte)
164 142
165extern void check_pgt_cache (void); 143extern void check_pgt_cache(void);
166 144
167#endif /* _ASM_IA64_PGALLOC_H */ 145#endif /* _ASM_IA64_PGALLOC_H */
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 2807f8d766d4..9e1ba8b7fb68 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -137,9 +137,6 @@ struct cpuinfo_ia64 {
137 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */ 137 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
138 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */ 138 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
139 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */ 139 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
140 __u64 *pgd_quick;
141 __u64 *pmd_quick;
142 __u64 pgtable_cache_sz;
143 __u64 itc_freq; /* frequency of ITC counter */ 140 __u64 itc_freq; /* frequency of ITC counter */
144 __u64 proc_freq; /* frequency of processor */ 141 __u64 proc_freq; /* frequency of processor */
145 __u64 cyc_per_usec; /* itc_freq/1000000 */ 142 __u64 cyc_per_usec; /* itc_freq/1000000 */
@@ -151,6 +148,13 @@ struct cpuinfo_ia64 {
151#ifdef CONFIG_SMP 148#ifdef CONFIG_SMP
152 __u64 loops_per_jiffy; 149 __u64 loops_per_jiffy;
153 int cpu; 150 int cpu;
151 __u32 socket_id; /* physical processor socket id */
152 __u16 core_id; /* core id */
153 __u16 thread_id; /* thread id */
154 __u16 num_log; /* Total number of logical processors on
155 * this socket that were successfully booted */
156 __u8 cores_per_socket; /* Cores per processor socket */
157 __u8 threads_per_core; /* Threads per core */
154#endif 158#endif
155 159
156 /* CPUID-derived information: */ 160 /* CPUID-derived information: */
diff --git a/include/asm-ia64/sal.h b/include/asm-ia64/sal.h
index 240676f75390..29df88bdd2bc 100644
--- a/include/asm-ia64/sal.h
+++ b/include/asm-ia64/sal.h
@@ -91,6 +91,7 @@ extern spinlock_t sal_lock;
91#define SAL_PCI_CONFIG_READ 0x01000010 91#define SAL_PCI_CONFIG_READ 0x01000010
92#define SAL_PCI_CONFIG_WRITE 0x01000011 92#define SAL_PCI_CONFIG_WRITE 0x01000011
93#define SAL_FREQ_BASE 0x01000012 93#define SAL_FREQ_BASE 0x01000012
94#define SAL_PHYSICAL_ID_INFO 0x01000013
94 95
95#define SAL_UPDATE_PAL 0x01000020 96#define SAL_UPDATE_PAL 0x01000020
96 97
@@ -815,6 +816,17 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
815 return isrv.status; 816 return isrv.status;
816} 817}
817 818
819/* Get physical processor die mapping in the platform. */
820static inline s64
821ia64_sal_physical_id_info(u16 *splid)
822{
823 struct ia64_sal_retval isrv;
824 SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
825 if (splid)
826 *splid = isrv.v0;
827 return isrv.status;
828}
829
818extern unsigned long sal_platform_features; 830extern unsigned long sal_platform_features;
819 831
820extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *); 832extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
index c4a227acfeb0..3ba1a061e4ae 100644
--- a/include/asm-ia64/smp.h
+++ b/include/asm-ia64/smp.h
@@ -56,6 +56,10 @@ extern struct smp_boot_data {
56extern char no_int_routing __devinitdata; 56extern char no_int_routing __devinitdata;
57 57
58extern cpumask_t cpu_online_map; 58extern cpumask_t cpu_online_map;
59extern cpumask_t cpu_core_map[NR_CPUS];
60extern cpumask_t cpu_sibling_map[NR_CPUS];
61extern int smp_num_siblings;
62extern int smp_num_cpucores;
59extern void __iomem *ipi_base_addr; 63extern void __iomem *ipi_base_addr;
60extern unsigned char smp_int_redirect; 64extern unsigned char smp_int_redirect;
61 65
@@ -124,6 +128,7 @@ extern int smp_call_function_single (int cpuid, void (*func) (void *info), void
124extern void smp_send_reschedule (int cpu); 128extern void smp_send_reschedule (int cpu);
125extern void lock_ipi_calllock(void); 129extern void lock_ipi_calllock(void);
126extern void unlock_ipi_calllock(void); 130extern void unlock_ipi_calllock(void);
131extern void identify_siblings (struct cpuinfo_ia64 *);
127 132
128#else 133#else
129 134
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index c916bd22767a..960d626ee589 100644
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -154,8 +154,9 @@
154 * the chiplet id is zero. If we implement TIO-TIO dma, we might need 154 * the chiplet id is zero. If we implement TIO-TIO dma, we might need
155 * to insert a chiplet id into this macro. However, it is our belief 155 * to insert a chiplet id into this macro. However, it is our belief
156 * right now that this chiplet id will be ICE, which is also zero. 156 * right now that this chiplet id will be ICE, which is also zero.
157 * Nasid starts on bit 40.
157 */ 158 */
158#define PHYS_TO_TIODMA(x) ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x)) 159#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
159#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) 160#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
160 161
161 162
@@ -168,7 +169,10 @@
168#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */ 169#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
169#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \ 170#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
170 : RAW_NODE_SWIN_BASE(n, w)) 171 : RAW_NODE_SWIN_BASE(n, w))
172#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
173 ((u64) (w) << TIO_SWIN_SIZE_BITS))
171#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n)) 174#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
175#define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n))
172#define BWIN_SIZE (1UL << BWIN_SIZE_BITS) 176#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
173#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE) 177#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
174#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS)) 178#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
diff --git a/include/asm-ia64/sn/bte.h b/include/asm-ia64/sn/bte.h
index 0ec27f99c181..f50da3d91d07 100644
--- a/include/asm-ia64/sn/bte.h
+++ b/include/asm-ia64/sn/bte.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (c) 2000-2004 Silicon Graphics, Inc. All Rights Reserved. 6 * Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
7 */ 7 */
8 8
9 9
@@ -13,8 +13,12 @@
13#include <linux/timer.h> 13#include <linux/timer.h>
14#include <linux/spinlock.h> 14#include <linux/spinlock.h>
15#include <linux/cache.h> 15#include <linux/cache.h>
16#include <asm/sn/pda.h>
16#include <asm/sn/types.h> 17#include <asm/sn/types.h>
18#include <asm/sn/shub_mmr.h>
17 19
20#define IBCT_NOTIFY (0x1UL << 4)
21#define IBCT_ZFIL_MODE (0x1UL << 0)
18 22
19/* #define BTE_DEBUG */ 23/* #define BTE_DEBUG */
20/* #define BTE_DEBUG_VERBOSE */ 24/* #define BTE_DEBUG_VERBOSE */
@@ -39,8 +43,36 @@
39 43
40 44
41/* Define hardware */ 45/* Define hardware */
42#define BTES_PER_NODE 2 46#define BTES_PER_NODE (is_shub2() ? 4 : 2)
47#define MAX_BTES_PER_NODE 4
43 48
49#define BTE2OFF_CTRL (0)
50#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
51#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
52#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
53
54#define BTE_BASE_ADDR(interface) \
55 (is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
56 (interface == 1) ? SH2_BT_ENG_CSR_1 : \
57 (interface == 2) ? SH2_BT_ENG_CSR_2 : \
58 SH2_BT_ENG_CSR_3 \
59 : (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
60
61#define BTE_SOURCE_ADDR(base) \
62 (is_shub2() ? base + (BTE2OFF_SRC/8) \
63 : base + (BTEOFF_SRC/8))
64
65#define BTE_DEST_ADDR(base) \
66 (is_shub2() ? base + (BTE2OFF_DEST/8) \
67 : base + (BTEOFF_DEST/8))
68
69#define BTE_CTRL_ADDR(base) \
70 (is_shub2() ? base + (BTE2OFF_CTRL/8) \
71 : base + (BTEOFF_CTRL/8))
72
73#define BTE_NOTIF_ADDR(base) \
74 (is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
75 : base + (BTEOFF_NOTIFY/8))
44 76
45/* Define hardware modes */ 77/* Define hardware modes */
46#define BTE_NOTIFY (IBCT_NOTIFY) 78#define BTE_NOTIFY (IBCT_NOTIFY)
@@ -68,14 +100,18 @@
68#define BTE_LNSTAT_STORE(_bte, _x) \ 100#define BTE_LNSTAT_STORE(_bte, _x) \
69 HUB_S(_bte->bte_base_addr, (_x)) 101 HUB_S(_bte->bte_base_addr, (_x))
70#define BTE_SRC_STORE(_bte, _x) \ 102#define BTE_SRC_STORE(_bte, _x) \
71 HUB_S(_bte->bte_base_addr + (BTEOFF_SRC/8), (_x)) 103 HUB_S(_bte->bte_source_addr, (_x))
72#define BTE_DEST_STORE(_bte, _x) \ 104#define BTE_DEST_STORE(_bte, _x) \
73 HUB_S(_bte->bte_base_addr + (BTEOFF_DEST/8), (_x)) 105 HUB_S(_bte->bte_destination_addr, (_x))
74#define BTE_CTRL_STORE(_bte, _x) \ 106#define BTE_CTRL_STORE(_bte, _x) \
75 HUB_S(_bte->bte_base_addr + (BTEOFF_CTRL/8), (_x)) 107 HUB_S(_bte->bte_control_addr, (_x))
76#define BTE_NOTIF_STORE(_bte, _x) \ 108#define BTE_NOTIF_STORE(_bte, _x) \
77 HUB_S(_bte->bte_base_addr + (BTEOFF_NOTIFY/8), (_x)) 109 HUB_S(_bte->bte_notify_addr, (_x))
78 110
111#define BTE_START_TRANSFER(_bte, _len, _mode) \
112 is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
113 : BTE_LNSTAT_STORE(_bte, _len); \
114 BTE_CTRL_STORE(_bte, _mode)
79 115
80/* Possible results from bte_copy and bte_unaligned_copy */ 116/* Possible results from bte_copy and bte_unaligned_copy */
81/* The following error codes map into the BTE hardware codes 117/* The following error codes map into the BTE hardware codes
@@ -110,6 +146,10 @@ typedef enum {
110struct bteinfo_s { 146struct bteinfo_s {
111 volatile u64 notify ____cacheline_aligned; 147 volatile u64 notify ____cacheline_aligned;
112 u64 *bte_base_addr ____cacheline_aligned; 148 u64 *bte_base_addr ____cacheline_aligned;
149 u64 *bte_source_addr;
150 u64 *bte_destination_addr;
151 u64 *bte_control_addr;
152 u64 *bte_notify_addr;
113 spinlock_t spinlock; 153 spinlock_t spinlock;
114 cnodeid_t bte_cnode; /* cnode */ 154 cnodeid_t bte_cnode; /* cnode */
115 int bte_error_count; /* Number of errors encountered */ 155 int bte_error_count; /* Number of errors encountered */
@@ -117,6 +157,7 @@ struct bteinfo_s {
117 int cleanup_active; /* Interface is locked for cleanup */ 157 int cleanup_active; /* Interface is locked for cleanup */
118 volatile bte_result_t bh_error; /* error while processing */ 158 volatile bte_result_t bh_error; /* error while processing */
119 volatile u64 *most_rcnt_na; 159 volatile u64 *most_rcnt_na;
160 struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
120}; 161};
121 162
122 163
diff --git a/include/asm-ia64/sn/geo.h b/include/asm-ia64/sn/geo.h
index f566343d25f8..84b254603b8d 100644
--- a/include/asm-ia64/sn/geo.h
+++ b/include/asm-ia64/sn/geo.h
@@ -18,32 +18,34 @@
18#define GEOID_SIZE 8 /* Would 16 be better? The size can 18#define GEOID_SIZE 8 /* Would 16 be better? The size can
19 be different on different platforms. */ 19 be different on different platforms. */
20 20
21#define MAX_SLABS 0xe /* slabs per module */ 21#define MAX_SLOTS 0xf /* slots per module */
22#define MAX_SLABS 0xf /* slabs per slot */
22 23
23typedef unsigned char geo_type_t; 24typedef unsigned char geo_type_t;
24 25
25/* Fields common to all substructures */ 26/* Fields common to all substructures */
26typedef struct geo_any_s { 27typedef struct geo_common_s {
27 moduleid_t module; /* The module (box) this h/w lives in */ 28 moduleid_t module; /* The module (box) this h/w lives in */
28 geo_type_t type; /* What type of h/w is named by this geoid_t */ 29 geo_type_t type; /* What type of h/w is named by this geoid_t */
29 slabid_t slab; /* The logical assembly within the module */ 30 slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */
30} geo_any_t; 31 slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */
32} geo_common_t;
31 33
32/* Additional fields for particular types of hardware */ 34/* Additional fields for particular types of hardware */
33typedef struct geo_node_s { 35typedef struct geo_node_s {
34 geo_any_t any; /* No additional fields needed */ 36 geo_common_t common; /* No additional fields needed */
35} geo_node_t; 37} geo_node_t;
36 38
37typedef struct geo_rtr_s { 39typedef struct geo_rtr_s {
38 geo_any_t any; /* No additional fields needed */ 40 geo_common_t common; /* No additional fields needed */
39} geo_rtr_t; 41} geo_rtr_t;
40 42
41typedef struct geo_iocntl_s { 43typedef struct geo_iocntl_s {
42 geo_any_t any; /* No additional fields needed */ 44 geo_common_t common; /* No additional fields needed */
43} geo_iocntl_t; 45} geo_iocntl_t;
44 46
45typedef struct geo_pcicard_s { 47typedef struct geo_pcicard_s {
46 geo_iocntl_t any; 48 geo_iocntl_t common;
47 char bus; /* Bus/widget number */ 49 char bus; /* Bus/widget number */
48 char slot; /* PCI slot number */ 50 char slot; /* PCI slot number */
49} geo_pcicard_t; 51} geo_pcicard_t;
@@ -62,14 +64,14 @@ typedef struct geo_mem_s {
62 64
63 65
64typedef union geoid_u { 66typedef union geoid_u {
65 geo_any_t any; 67 geo_common_t common;
66 geo_node_t node; 68 geo_node_t node;
67 geo_iocntl_t iocntl; 69 geo_iocntl_t iocntl;
68 geo_pcicard_t pcicard; 70 geo_pcicard_t pcicard;
69 geo_rtr_t rtr; 71 geo_rtr_t rtr;
70 geo_cpu_t cpu; 72 geo_cpu_t cpu;
71 geo_mem_t mem; 73 geo_mem_t mem;
72 char padsize[GEOID_SIZE]; 74 char padsize[GEOID_SIZE];
73} geoid_t; 75} geoid_t;
74 76
75 77
@@ -104,19 +106,26 @@ typedef union geoid_u {
104#define INVALID_CNODEID ((cnodeid_t)-1) 106#define INVALID_CNODEID ((cnodeid_t)-1)
105#define INVALID_PNODEID ((pnodeid_t)-1) 107#define INVALID_PNODEID ((pnodeid_t)-1)
106#define INVALID_SLAB (slabid_t)-1 108#define INVALID_SLAB (slabid_t)-1
109#define INVALID_SLOT (slotid_t)-1
107#define INVALID_MODULE ((moduleid_t)-1) 110#define INVALID_MODULE ((moduleid_t)-1)
108#define INVALID_PARTID ((partid_t)-1) 111#define INVALID_PARTID ((partid_t)-1)
109 112
110static inline slabid_t geo_slab(geoid_t g) 113static inline slabid_t geo_slab(geoid_t g)
111{ 114{
112 return (g.any.type == GEO_TYPE_INVALID) ? 115 return (g.common.type == GEO_TYPE_INVALID) ?
113 INVALID_SLAB : g.any.slab; 116 INVALID_SLAB : g.common.slab;
117}
118
119static inline slotid_t geo_slot(geoid_t g)
120{
121 return (g.common.type == GEO_TYPE_INVALID) ?
122 INVALID_SLOT : g.common.slot;
114} 123}
115 124
116static inline moduleid_t geo_module(geoid_t g) 125static inline moduleid_t geo_module(geoid_t g)
117{ 126{
118 return (g.any.type == GEO_TYPE_INVALID) ? 127 return (g.common.type == GEO_TYPE_INVALID) ?
119 INVALID_MODULE : g.any.module; 128 INVALID_MODULE : g.common.module;
120} 129}
121 130
122extern geoid_t cnodeid_get_geoid(cnodeid_t cnode); 131extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
diff --git a/include/asm-ia64/sn/nodepda.h b/include/asm-ia64/sn/nodepda.h
index 2fbde33656e6..13cc1002b294 100644
--- a/include/asm-ia64/sn/nodepda.h
+++ b/include/asm-ia64/sn/nodepda.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8#ifndef _ASM_IA64_SN_NODEPDA_H 8#ifndef _ASM_IA64_SN_NODEPDA_H
9#define _ASM_IA64_SN_NODEPDA_H 9#define _ASM_IA64_SN_NODEPDA_H
@@ -43,7 +43,7 @@ struct nodepda_s {
43 /* 43 /*
44 * The BTEs on this node are shared by the local cpus 44 * The BTEs on this node are shared by the local cpus
45 */ 45 */
46 struct bteinfo_s bte_if[BTES_PER_NODE]; /* Virtual Interface */ 46 struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */
47 struct timer_list bte_recovery_timer; 47 struct timer_list bte_recovery_timer;
48 spinlock_t bte_recovery_lock; 48 spinlock_t bte_recovery_lock;
49 49
diff --git a/include/asm-ia64/sn/pcibus_provider_defs.h b/include/asm-ia64/sn/pcibus_provider_defs.h
new file mode 100644
index 000000000000..04e27d5b3820
--- /dev/null
+++ b/include/asm-ia64/sn/pcibus_provider_defs.h
@@ -0,0 +1,52 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
9#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
10
11/*
12 * SN pci asic types. Do not ever renumber these or reuse values. The
13 * values must agree with what prom thinks they are.
14 */
15
16#define PCIIO_ASIC_TYPE_UNKNOWN 0
17#define PCIIO_ASIC_TYPE_PPB 1
18#define PCIIO_ASIC_TYPE_PIC 2
19#define PCIIO_ASIC_TYPE_TIOCP 3
20#define PCIIO_ASIC_TYPE_TIOCA 4
21
22#define PCIIO_ASIC_MAX_TYPES 5
23
24/*
25 * Common pciio bus provider data. There should be one of these as the
26 * first field in any pciio based provider soft structure (e.g. pcibr_soft
27 * tioca_soft, etc).
28 */
29
30struct pcibus_bussoft {
31 uint32_t bs_asic_type; /* chipset type */
32 uint32_t bs_xid; /* xwidget id */
33 uint64_t bs_persist_busnum; /* Persistent Bus Number */
34 uint64_t bs_legacy_io; /* legacy io pio addr */
35 uint64_t bs_legacy_mem; /* legacy mem pio addr */
36 uint64_t bs_base; /* widget base */
37 struct xwidget_info *bs_xwidget_info;
38};
39
40/*
41 * SN pci bus indirection
42 */
43
44struct sn_pcibus_provider {
45 dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t);
46 dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
47 void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
48 void * (*bus_fixup)(struct pcibus_bussoft *);
49};
50
51extern struct sn_pcibus_provider *sn_pci_provider[];
52#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
diff --git a/include/asm-ia64/sn/pcidev.h b/include/asm-ia64/sn/pcidev.h
new file mode 100644
index 000000000000..ed4031d80811
--- /dev/null
+++ b/include/asm-ia64/sn/pcidev.h
@@ -0,0 +1,58 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
7 */
8#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
9#define _ASM_IA64_SN_PCI_PCIDEV_H
10
11#include <linux/pci.h>
12
13extern struct sn_irq_info **sn_irq;
14
15#define SN_PCIDEV_INFO(pci_dev) \
16 ((struct pcidev_info *)(pci_dev)->sysdata)
17
18/*
19 * Given a pci_bus, return the sn pcibus_bussoft struct. Note that
20 * this only works for root busses, not for busses represented by PPB's.
21 */
22
23#define SN_PCIBUS_BUSSOFT(pci_bus) \
24 ((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
25
26/*
27 * Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
28 * that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
29 * due to possible PPB's in the path.
30 */
31
32#define SN_PCIDEV_BUSSOFT(pci_dev) \
33 (SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
34
35#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
36 (SN_PCIDEV_INFO(pci_dev)->pdi_provider)
37
38#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
39#define PCIIO_SLOT_NONE 255
40#define PCIIO_FUNC_NONE 255
41#define PCIIO_VENDOR_ID_NONE (-1)
42
43struct pcidev_info {
44 uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
45 uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
46
47 struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
48 struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
49 struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
50
51 struct sn_irq_info *pdi_sn_irq_info;
52 struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
53};
54
55extern void sn_irq_fixup(struct pci_dev *pci_dev,
56 struct sn_irq_info *sn_irq_info);
57
58#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
diff --git a/include/asm-ia64/sn/pda.h b/include/asm-ia64/sn/pda.h
index e940d3647c80..cd19f17bf91a 100644
--- a/include/asm-ia64/sn/pda.h
+++ b/include/asm-ia64/sn/pda.h
@@ -3,7 +3,7 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved. 6 * Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
7 */ 7 */
8#ifndef _ASM_IA64_SN_PDA_H 8#ifndef _ASM_IA64_SN_PDA_H
9#define _ASM_IA64_SN_PDA_H 9#define _ASM_IA64_SN_PDA_H
@@ -11,7 +11,6 @@
11#include <linux/cache.h> 11#include <linux/cache.h>
12#include <asm/percpu.h> 12#include <asm/percpu.h>
13#include <asm/system.h> 13#include <asm/system.h>
14#include <asm/sn/bte.h>
15 14
16 15
17/* 16/*
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h
index 5c2fcf13d5ce..2f885088e095 100644
--- a/include/asm-ia64/sn/shub_mmr.h
+++ b/include/asm-ia64/sn/shub_mmr.h
@@ -4,7 +4,7 @@
4 * License. See the file "COPYING" in the main directory of this archive 4 * License. See the file "COPYING" in the main directory of this archive
5 * for more details. 5 * for more details.
6 * 6 *
7 * Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved. 7 * Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved.
8 */ 8 */
9 9
10#ifndef _ASM_IA64_SN_SHUB_MMR_H 10#ifndef _ASM_IA64_SN_SHUB_MMR_H
@@ -129,6 +129,23 @@
129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30 129#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000 130#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000
131 131
132/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
133/* Description: Pending SHUB 2 EXT IO INT2 */
134#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
135#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000
136
137/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
138/* Description: Pending SHUB 2 EXT IO INT3 */
139#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
140#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000
141
142#define SH_ALL_INT_MASK \
143 (SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
144 SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
145 SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
146 SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
147
148
132/* ==================================================================== */ 149/* ==================================================================== */
133/* LEDS */ 150/* LEDS */
134/* ==================================================================== */ 151/* ==================================================================== */
@@ -438,4 +455,22 @@
438#define SH_INT_CMPC shubmmr(SH, INT_CMPC) 455#define SH_INT_CMPC shubmmr(SH, INT_CMPC)
439#define SH_INT_CMPD shubmmr(SH, INT_CMPD) 456#define SH_INT_CMPD shubmmr(SH, INT_CMPD)
440 457
458/* ========================================================================== */
459/* Register "SH2_BT_ENG_CSR_0" */
460/* Engine 0 Control and Status Register */
461/* ========================================================================== */
462
463#define SH2_BT_ENG_CSR_0 0x0000000030040000
464#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080
465#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100
466#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180
467
468/* ========================================================================== */
469/* BTE interfaces 1-3 */
470/* ========================================================================== */
471
472#define SH2_BT_ENG_CSR_1 0x0000000030050000
473#define SH2_BT_ENG_CSR_2 0x0000000030060000
474#define SH2_BT_ENG_CSR_3 0x0000000030070000
475
441#endif /* _ASM_IA64_SN_SHUB_MMR_H */ 476#endif /* _ASM_IA64_SN_SHUB_MMR_H */
diff --git a/include/asm-ia64/sn/sn_sal.h b/include/asm-ia64/sn/sn_sal.h
index 88c31b53dc09..f914f6da077c 100644
--- a/include/asm-ia64/sn/sn_sal.h
+++ b/include/asm-ia64/sn/sn_sal.h
@@ -8,7 +8,7 @@
8 * License. See the file "COPYING" in the main directory of this archive 8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details. 9 * for more details.
10 * 10 *
11 * Copyright (c) 2000-2004 Silicon Graphics, Inc. All rights reserved. 11 * Copyright (c) 2000-2005 Silicon Graphics, Inc. All rights reserved.
12 */ 12 */
13 13
14 14
@@ -35,8 +35,8 @@
35#define SN_SAL_PRINT_ERROR 0x02000012 35#define SN_SAL_PRINT_ERROR 0x02000012
36#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant 36#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
37#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant 37#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
38#define SN_SAL_GET_SN_INFO 0x0200001c
39#define SN_SAL_GET_SAPIC_INFO 0x0200001d 38#define SN_SAL_GET_SAPIC_INFO 0x0200001d
39#define SN_SAL_GET_SN_INFO 0x0200001e
40#define SN_SAL_CONSOLE_PUTC 0x02000021 40#define SN_SAL_CONSOLE_PUTC 0x02000021
41#define SN_SAL_CONSOLE_GETC 0x02000022 41#define SN_SAL_CONSOLE_GETC 0x02000022
42#define SN_SAL_CONSOLE_PUTS 0x02000023 42#define SN_SAL_CONSOLE_PUTS 0x02000023
@@ -64,6 +64,7 @@
64 64
65#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant 65#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
66#define SN_SAL_IROUTER_OP 0x02000043 66#define SN_SAL_IROUTER_OP 0x02000043
67#define SN_SAL_SYSCTL_EVENT 0x02000044
67#define SN_SAL_IOIF_INTERRUPT 0x0200004a 68#define SN_SAL_IOIF_INTERRUPT 0x0200004a
68#define SN_SAL_HWPERF_OP 0x02000050 // lock 69#define SN_SAL_HWPERF_OP 0x02000050 // lock
69#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051 70#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
@@ -76,7 +77,8 @@
76#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058 77#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058
77 78
78#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060 79#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
79 80#define SN_SAL_BTE_RECOVER 0x02000061
81#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000062
80 82
81/* 83/*
82 * Service-specific constants 84 * Service-specific constants
@@ -849,6 +851,19 @@ ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
849 return (int) rv.v0; 851 return (int) rv.v0;
850} 852}
851 853
854/*
855 * Set up a node as the point of contact for system controller
856 * environmental event delivery.
857 */
858static inline int
859ia64_sn_sysctl_event_init(nasid_t nasid)
860{
861 struct ia64_sal_retval rv;
862 SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
863 0, 0, 0, 0, 0, 0);
864 return (int) rv.v0;
865}
866
852/** 867/**
853 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header 868 * ia64_sn_get_fit_compt - read a FIT entry from the PROM header
854 * @nasid: NASID of node to read 869 * @nasid: NASID of node to read
@@ -1012,4 +1027,29 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
1012 return (int) rv.status; 1027 return (int) rv.status;
1013} 1028}
1014 1029
1030static inline int
1031ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab,
1032 u64 buf, u64 len)
1033{
1034 struct ia64_sal_retval rv;
1035 SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY,
1036 rack, bay, slot, slab, buf, len, 0);
1037 return (int) rv.status;
1038}
1039
1040/*
1041 * BTE error recovery is implemented in SAL
1042 */
1043static inline int
1044ia64_sn_bte_recovery(nasid_t nasid)
1045{
1046 struct ia64_sal_retval rv;
1047
1048 rv.status = 0;
1049 SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, 0, 0, 0, 0, 0, 0, 0);
1050 if (rv.status == SALRET_NOT_IMPLEMENTED)
1051 return 0;
1052 return (int) rv.status;
1053}
1054
1015#endif /* _ASM_IA64_SN_SN_SAL_H */ 1055#endif /* _ASM_IA64_SN_SN_SAL_H */
diff --git a/include/asm-ia64/sn/tioca.h b/include/asm-ia64/sn/tioca.h
new file mode 100644
index 000000000000..bc1aacfb9483
--- /dev/null
+++ b/include/asm-ia64/sn/tioca.h
@@ -0,0 +1,596 @@
1#ifndef _ASM_IA64_SN_TIO_TIOCA_H
2#define _ASM_IA64_SN_TIO_TIOCA_H
3
4/*
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 *
9 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
10 */
11
12
13#define TIOCA_PART_NUM 0xE020
14#define TIOCA_MFGR_NUM 0x24
15#define TIOCA_REV_A 0x1
16
17/*
18 * Register layout for TIO:CA. See below for bitmasks for each register.
19 */
20
21struct tioca {
22 uint64_t ca_id; /* 0x000000 */
23 uint64_t ca_control1; /* 0x000008 */
24 uint64_t ca_control2; /* 0x000010 */
25 uint64_t ca_status1; /* 0x000018 */
26 uint64_t ca_status2; /* 0x000020 */
27 uint64_t ca_gart_aperature; /* 0x000028 */
28 uint64_t ca_gfx_detach; /* 0x000030 */
29 uint64_t ca_inta_dest_addr; /* 0x000038 */
30 uint64_t ca_intb_dest_addr; /* 0x000040 */
31 uint64_t ca_err_int_dest_addr; /* 0x000048 */
32 uint64_t ca_int_status; /* 0x000050 */
33 uint64_t ca_int_status_alias; /* 0x000058 */
34 uint64_t ca_mult_error; /* 0x000060 */
35 uint64_t ca_mult_error_alias; /* 0x000068 */
36 uint64_t ca_first_error; /* 0x000070 */
37 uint64_t ca_int_mask; /* 0x000078 */
38 uint64_t ca_crm_pkterr_type; /* 0x000080 */
39 uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */
40 uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */
41 uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */
42 uint64_t ca_crm_tnumto; /* 0x0000A0 */
43 uint64_t ca_gart_err; /* 0x0000A8 */
44 uint64_t ca_pcierr_type; /* 0x0000B0 */
45 uint64_t ca_pcierr_addr; /* 0x0000B8 */
46
47 uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
48
49 uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */
50 uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */
51 uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */
52 uint64_t ca_force_inta; /* 0x0000F0 */
53 uint64_t ca_force_intb; /* 0x0000F8 */
54 uint64_t ca_debug_vector_sel; /* 0x000100 */
55 uint64_t ca_debug_mux_core_sel; /* 0x000108 */
56 uint64_t ca_debug_mux_pci_sel; /* 0x000110 */
57 uint64_t ca_debug_domain_sel; /* 0x000118 */
58
59 uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */
60
61 uint64_t ca_gart_ptr_table; /* 0x200 */
62 uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */
63};
64
65/*
66 * Mask/shift definitions for TIO:CA registers. The convention here is
67 * to mainly use the names as they appear in the "TIO AEGIS Programmers'
68 * Reference" with a CA_ prefix added. Some exceptions were made to fix
69 * duplicate field names or to generalize fields that are common to
70 * different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
71 * example).
72 *
73 * Fields consisting of a single bit have a single #define have a single
74 * macro declaration to mask the bit. Fields consisting of multiple bits
75 * have two declarations: one to mask the proper bits in a register, and
76 * a second with the suffix "_SHFT" to identify how far the mask needs to
77 * be shifted right to get its base value.
78 */
79
80/* ==== ca_control1 */
81#define CA_SYS_BIG_END (1ull << 0)
82#define CA_DMA_AGP_SWAP (1ull << 1)
83#define CA_DMA_PCI_SWAP (1ull << 2)
84#define CA_PIO_IO_SWAP (1ull << 3)
85#define CA_PIO_MEM_SWAP (1ull << 4)
86#define CA_GFX_WR_SWAP (1ull << 5)
87#define CA_AGP_FW_ENABLE (1ull << 6)
88#define CA_AGP_CAL_CYCLE (0x7ull << 7)
89#define CA_AGP_CAL_CYCLE_SHFT 7
90#define CA_AGP_CAL_PRSCL_BYP (1ull << 10)
91#define CA_AGP_INIT_CAL_ENB (1ull << 11)
92#define CA_INJ_ADDR_PERR (1ull << 12)
93#define CA_INJ_DATA_PERR (1ull << 13)
94 /* bits 15:14 unused */
95#define CA_PCIM_IO_NBE_AD (0x7ull << 16)
96#define CA_PCIM_IO_NBE_AD_SHFT 16
97#define CA_PCIM_FAST_BTB_ENB (1ull << 19)
98 /* bits 23:20 unused */
99#define CA_PIO_ADDR_OFFSET (0xffull << 24)
100#define CA_PIO_ADDR_OFFSET_SHFT 24
101 /* bits 35:32 unused */
102#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36)
103#define CA_AGPDMA_OP_COMBDELAY_SHFT 36
104 /* bit 41 unused */
105#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42)
106#define CA_PCI_INT_LPCNT (0xffull << 44)
107#define CA_PCI_INT_LPCNT_SHFT 44
108 /* bits 63:52 unused */
109
110/* ==== ca_control2 */
111#define CA_AGP_LATENCY_TO (0xffull << 0)
112#define CA_AGP_LATENCY_TO_SHFT 0
113#define CA_PCI_LATENCY_TO (0xffull << 8)
114#define CA_PCI_LATENCY_TO_SHFT 8
115#define CA_PCI_MAX_RETRY (0x3ffull << 16)
116#define CA_PCI_MAX_RETRY_SHFT 16
117 /* bits 27:26 unused */
118#define CA_RT_INT_EN (0x3ull << 28)
119#define CA_RT_INT_EN_SHFT 28
120#define CA_MSI_INT_ENB (1ull << 30)
121#define CA_PCI_ARB_ERR_ENB (1ull << 31)
122#define CA_GART_MEM_PARAM (0x3ull << 32)
123#define CA_GART_MEM_PARAM_SHFT 32
124#define CA_GART_RD_PREFETCH_ENB (1ull << 34)
125#define CA_GART_WR_PREFETCH_ENB (1ull << 35)
126#define CA_GART_FLUSH_TLB (1ull << 36)
127 /* bits 39:37 unused */
128#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
129#define CA_CRM_TNUMTO_PERIOD_SHFT 40
130 /* bits 55:53 unused */
131#define CA_CRM_TNUMTO_ENB (1ull << 56)
132#define CA_CRM_PRESCALER_BYP (1ull << 57)
133 /* bits 59:58 unused */
134#define CA_CRM_MAX_CREDIT (0x7ull << 60)
135#define CA_CRM_MAX_CREDIT_SHFT 60
136 /* bit 63 unused */
137
138/* ==== ca_status1 */
139#define CA_CORELET_ID (0x3ull << 0)
140#define CA_CORELET_ID_SHFT 0
141#define CA_INTA_N (1ull << 2)
142#define CA_INTB_N (1ull << 3)
143#define CA_CRM_CREDIT_AVAIL (0x7ull << 4)
144#define CA_CRM_CREDIT_AVAIL_SHFT 4
145 /* bit 7 unused */
146#define CA_CRM_SPACE_AVAIL (0x7full << 8)
147#define CA_CRM_SPACE_AVAIL_SHFT 8
148 /* bit 15 unused */
149#define CA_GART_TLB_VAL (0xffull << 16)
150#define CA_GART_TLB_VAL_SHFT 16
151 /* bits 63:24 unused */
152
153/* ==== ca_status2 */
154#define CA_GFX_CREDIT_AVAIL (0xffull << 0)
155#define CA_GFX_CREDIT_AVAIL_SHFT 0
156#define CA_GFX_OPQ_AVAIL (0xffull << 8)
157#define CA_GFX_OPQ_AVAIL_SHFT 8
158#define CA_GFX_WRBUFF_AVAIL (0xffull << 16)
159#define CA_GFX_WRBUFF_AVAIL_SHFT 16
160#define CA_ADMA_OPQ_AVAIL (0xffull << 24)
161#define CA_ADMA_OPQ_AVAIL_SHFT 24
162#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32)
163#define CA_ADMA_WRBUFF_AVAIL_SHFT 32
164#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40)
165#define CA_ADMA_RDBUFF_AVAIL_SHFT 40
166#define CA_PCI_PIO_OP_STAT (1ull << 47)
167#define CA_PDMA_OPQ_AVAIL (0xfull << 48)
168#define CA_PDMA_OPQ_AVAIL_SHFT 48
169#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52)
170#define CA_PDMA_WRBUFF_AVAIL_SHFT 52
171#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56)
172#define CA_PDMA_RDBUFF_AVAIL_SHFT 56
173 /* bits 63:58 unused */
174
175/* ==== ca_gart_aperature */
176#define CA_GART_AP_ENB_AGP (1ull << 0)
177#define CA_GART_PAGE_SIZE (1ull << 1)
178#define CA_GART_AP_ENB_PCI (1ull << 2)
179 /* bits 11:3 unused */
180#define CA_GART_AP_SIZE (0x3ffull << 12)
181#define CA_GART_AP_SIZE_SHFT 12
182#define CA_GART_AP_BASE (0x3ffffffffffull << 22)
183#define CA_GART_AP_BASE_SHFT 22
184
185/* ==== ca_inta_dest_addr
186 ==== ca_intb_dest_addr
187 ==== ca_err_int_dest_addr */
188 /* bits 2:0 unused */
189#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3)
190#define CA_INT_DEST_ADDR_SHFT 3
191 /* bits 55:54 unused */
192#define CA_INT_DEST_VECT (0xffull << 56)
193#define CA_INT_DEST_VECT_SHFT 56
194
195/* ==== ca_int_status */
196/* ==== ca_int_status_alias */
197/* ==== ca_mult_error */
198/* ==== ca_mult_error_alias */
199/* ==== ca_first_error */
200/* ==== ca_int_mask */
201#define CA_PCI_ERR (1ull << 0)
202 /* bits 3:1 unused */
203#define CA_GART_FETCH_ERR (1ull << 4)
204#define CA_GFX_WR_OVFLW (1ull << 5)
205#define CA_PIO_REQ_OVFLW (1ull << 6)
206#define CA_CRM_PKTERR (1ull << 7)
207#define CA_CRM_DVERR (1ull << 8)
208#define CA_TNUMTO (1ull << 9)
209#define CA_CXM_RSP_CRED_OVFLW (1ull << 10)
210#define CA_CXM_REQ_CRED_OVFLW (1ull << 11)
211#define CA_PIO_INVALID_ADDR (1ull << 12)
212#define CA_PCI_ARB_TO (1ull << 13)
213#define CA_AGP_REQ_OFLOW (1ull << 14)
214#define CA_SBA_TYPE1_ERR (1ull << 15)
215 /* bit 16 unused */
216#define CA_INTA (1ull << 17)
217#define CA_INTB (1ull << 18)
218#define CA_MULT_INTA (1ull << 19)
219#define CA_MULT_INTB (1ull << 20)
220#define CA_GFX_CREDIT_OVFLW (1ull << 21)
221 /* bits 63:22 unused */
222
223/* ==== ca_crm_pkterr_type */
224/* ==== ca_crm_pkterr_type_alias */
225#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0)
226#define CA_CRM_PKTERR_DIDN (1ull << 1)
227#define CA_CRM_PKTERR_PACTYPE (1ull << 2)
228#define CA_CRM_PKTERR_INV_TNUM (1ull << 3)
229#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4)
230#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5)
231#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6)
232#define CA_CRM_PKTERR_CW_ERR (1ull << 7)
233#define CA_CRM_PKTERR_SBERR_NH (1ull << 8)
234#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9)
235#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10)
236#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11)
237#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12)
238 /* bits 15:13 unused */
239#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16)
240#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17)
241#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18)
242#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19)
243#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20)
244#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21)
245#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22)
246#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23)
247#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24)
248#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25)
249#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26)
250#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27)
251#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28)
252 /* bits 63:29 unused */
253
254/* ==== ca_crm_ct_error_detail_1 */
255#define CA_PKT_TYPE (0xfull << 0)
256#define CA_PKT_TYPE_SHFT 0
257#define CA_SRC_ID (0x3ull << 4)
258#define CA_SRC_ID_SHFT 4
259#define CA_DATA_SZ (0x3ull << 6)
260#define CA_DATA_SZ_SHFT 6
261#define CA_TNUM (0xffull << 8)
262#define CA_TNUM_SHFT 8
263#define CA_DW_DATA_EN (0xffull << 16)
264#define CA_DW_DATA_EN_SHFT 16
265#define CA_GFX_CRED (0xffull << 24)
266#define CA_GFX_CRED_SHFT 24
267#define CA_MEM_RD_PARAM (0x3ull << 32)
268#define CA_MEM_RD_PARAM_SHFT 32
269#define CA_PIO_OP (1ull << 34)
270#define CA_CW_ERR (1ull << 35)
271 /* bits 62:36 unused */
272#define CA_VALID (1ull << 63)
273
274/* ==== ca_crm_ct_error_detail_2 */
275 /* bits 2:0 unused */
276#define CA_PKT_ADDR (0x1fffffffffffffull << 3)
277#define CA_PKT_ADDR_SHFT 3
278 /* bits 63:56 unused */
279
280/* ==== ca_crm_tnumto */
281#define CA_CRM_TNUMTO_VAL (0xffull << 0)
282#define CA_CRM_TNUMTO_VAL_SHFT 0
283#define CA_CRM_TNUMTO_WR (1ull << 8)
284 /* bits 63:9 unused */
285
286/* ==== ca_gart_err */
287#define CA_GART_ERR_SOURCE (0x3ull << 0)
288#define CA_GART_ERR_SOURCE_SHFT 0
289 /* bits 3:2 unused */
290#define CA_GART_ERR_ADDR (0xfffffffffull << 4)
291#define CA_GART_ERR_ADDR_SHFT 4
292 /* bits 63:40 unused */
293
294/* ==== ca_pcierr_type */
295#define CA_PCIERR_DATA (0xffffffffull << 0)
296#define CA_PCIERR_DATA_SHFT 0
297#define CA_PCIERR_ENB (0xfull << 32)
298#define CA_PCIERR_ENB_SHFT 32
299#define CA_PCIERR_CMD (0xfull << 36)
300#define CA_PCIERR_CMD_SHFT 36
301#define CA_PCIERR_A64 (1ull << 40)
302#define CA_PCIERR_SLV_SERR (1ull << 41)
303#define CA_PCIERR_SLV_WR_PERR (1ull << 42)
304#define CA_PCIERR_SLV_RD_PERR (1ull << 43)
305#define CA_PCIERR_MST_SERR (1ull << 44)
306#define CA_PCIERR_MST_WR_PERR (1ull << 45)
307#define CA_PCIERR_MST_RD_PERR (1ull << 46)
308#define CA_PCIERR_MST_MABT (1ull << 47)
309#define CA_PCIERR_MST_TABT (1ull << 48)
310#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49)
311
312#define CA_PCIERR_TYPES \
313 (CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
314 CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
315 CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
316 CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
317
318 /* bits 63:50 unused */
319
320/* ==== ca_pci_dma_addr_extn */
321#define CA_UPPER_NODE_OFFSET (0x3full << 0)
322#define CA_UPPER_NODE_OFFSET_SHFT 0
323 /* bits 7:6 unused */
324#define CA_CHIPLET_ID (0x3ull << 8)
325#define CA_CHIPLET_ID_SHFT 8
326 /* bits 11:10 unused */
327#define CA_PCI_DMA_NODE_ID (0xffffull << 12)
328#define CA_PCI_DMA_NODE_ID_SHFT 12
329 /* bits 27:26 unused */
330#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28)
331 /* bits 63:29 unused */
332
333
334/* ==== ca_agp_dma_addr_extn */
335 /* bits 19:0 unused */
336#define CA_AGP_DMA_NODE_ID (0xffffull << 20)
337#define CA_AGP_DMA_NODE_ID_SHFT 20
338 /* bits 27:26 unused */
339#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28)
340 /* bits 63:29 unused */
341
342/* ==== ca_debug_vector_sel */
343#define CA_DEBUG_MN_VSEL (0xfull << 0)
344#define CA_DEBUG_MN_VSEL_SHFT 0
345#define CA_DEBUG_PP_VSEL (0xfull << 4)
346#define CA_DEBUG_PP_VSEL_SHFT 4
347#define CA_DEBUG_GW_VSEL (0xfull << 8)
348#define CA_DEBUG_GW_VSEL_SHFT 8
349#define CA_DEBUG_GT_VSEL (0xfull << 12)
350#define CA_DEBUG_GT_VSEL_SHFT 12
351#define CA_DEBUG_PD_VSEL (0xfull << 16)
352#define CA_DEBUG_PD_VSEL_SHFT 16
353#define CA_DEBUG_AD_VSEL (0xfull << 20)
354#define CA_DEBUG_AD_VSEL_SHFT 20
355#define CA_DEBUG_CX_VSEL (0xfull << 24)
356#define CA_DEBUG_CX_VSEL_SHFT 24
357#define CA_DEBUG_CR_VSEL (0xfull << 28)
358#define CA_DEBUG_CR_VSEL_SHFT 28
359#define CA_DEBUG_BA_VSEL (0xfull << 32)
360#define CA_DEBUG_BA_VSEL_SHFT 32
361#define CA_DEBUG_PE_VSEL (0xfull << 36)
362#define CA_DEBUG_PE_VSEL_SHFT 36
363#define CA_DEBUG_BO_VSEL (0xfull << 40)
364#define CA_DEBUG_BO_VSEL_SHFT 40
365#define CA_DEBUG_BI_VSEL (0xfull << 44)
366#define CA_DEBUG_BI_VSEL_SHFT 44
367#define CA_DEBUG_AS_VSEL (0xfull << 48)
368#define CA_DEBUG_AS_VSEL_SHFT 48
369#define CA_DEBUG_PS_VSEL (0xfull << 52)
370#define CA_DEBUG_PS_VSEL_SHFT 52
371#define CA_DEBUG_PM_VSEL (0xfull << 56)
372#define CA_DEBUG_PM_VSEL_SHFT 56
373 /* bits 63:60 unused */
374
375/* ==== ca_debug_mux_core_sel */
376/* ==== ca_debug_mux_pci_sel */
377#define CA_DEBUG_MSEL0 (0x7ull << 0)
378#define CA_DEBUG_MSEL0_SHFT 0
379 /* bit 3 unused */
380#define CA_DEBUG_NSEL0 (0x7ull << 4)
381#define CA_DEBUG_NSEL0_SHFT 4
382 /* bit 7 unused */
383#define CA_DEBUG_MSEL1 (0x7ull << 8)
384#define CA_DEBUG_MSEL1_SHFT 8
385 /* bit 11 unused */
386#define CA_DEBUG_NSEL1 (0x7ull << 12)
387#define CA_DEBUG_NSEL1_SHFT 12
388 /* bit 15 unused */
389#define CA_DEBUG_MSEL2 (0x7ull << 16)
390#define CA_DEBUG_MSEL2_SHFT 16
391 /* bit 19 unused */
392#define CA_DEBUG_NSEL2 (0x7ull << 20)
393#define CA_DEBUG_NSEL2_SHFT 20
394 /* bit 23 unused */
395#define CA_DEBUG_MSEL3 (0x7ull << 24)
396#define CA_DEBUG_MSEL3_SHFT 24
397 /* bit 27 unused */
398#define CA_DEBUG_NSEL3 (0x7ull << 28)
399#define CA_DEBUG_NSEL3_SHFT 28
400 /* bit 31 unused */
401#define CA_DEBUG_MSEL4 (0x7ull << 32)
402#define CA_DEBUG_MSEL4_SHFT 32
403 /* bit 35 unused */
404#define CA_DEBUG_NSEL4 (0x7ull << 36)
405#define CA_DEBUG_NSEL4_SHFT 36
406 /* bit 39 unused */
407#define CA_DEBUG_MSEL5 (0x7ull << 40)
408#define CA_DEBUG_MSEL5_SHFT 40
409 /* bit 43 unused */
410#define CA_DEBUG_NSEL5 (0x7ull << 44)
411#define CA_DEBUG_NSEL5_SHFT 44
412 /* bit 47 unused */
413#define CA_DEBUG_MSEL6 (0x7ull << 48)
414#define CA_DEBUG_MSEL6_SHFT 48
415 /* bit 51 unused */
416#define CA_DEBUG_NSEL6 (0x7ull << 52)
417#define CA_DEBUG_NSEL6_SHFT 52
418 /* bit 55 unused */
419#define CA_DEBUG_MSEL7 (0x7ull << 56)
420#define CA_DEBUG_MSEL7_SHFT 56
421 /* bit 59 unused */
422#define CA_DEBUG_NSEL7 (0x7ull << 60)
423#define CA_DEBUG_NSEL7_SHFT 60
424 /* bit 63 unused */
425
426
427/* ==== ca_debug_domain_sel */
428#define CA_DEBUG_DOMAIN_L (1ull << 0)
429#define CA_DEBUG_DOMAIN_H (1ull << 1)
430 /* bits 63:2 unused */
431
432/* ==== ca_gart_ptr_table */
433#define CA_GART_PTR_VAL (1ull << 0)
434 /* bits 11:1 unused */
435#define CA_GART_PTR_ADDR (0xfffffffffffull << 12)
436#define CA_GART_PTR_ADDR_SHFT 12
437 /* bits 63:56 unused */
438
439/* ==== ca_gart_tlb_addr[0-7] */
440#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0)
441#define CA_GART_TLB_ADDR_SHFT 0
442 /* bits 62:56 unused */
443#define CA_GART_TLB_ENTRY_VAL (1ull << 63)
444
445/*
446 * PIO address space ranges for TIO:CA
447 */
448
449/* CA internal registers */
450#define CA_PIO_ADMIN 0x00000000
451#define CA_PIO_ADMIN_LEN 0x00010000
452
453/* GFX Write Buffer - Diagnostics */
454#define CA_PIO_GFX 0x00010000
455#define CA_PIO_GFX_LEN 0x00010000
456
457/* AGP DMA Write Buffer - Diagnostics */
458#define CA_PIO_AGP_DMAWRITE 0x00020000
459#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000
460
461/* AGP DMA READ Buffer - Diagnostics */
462#define CA_PIO_AGP_DMAREAD 0x00030000
463#define CA_PIO_AGP_DMAREAD_LEN 0x00010000
464
465/* PCI Config Type 0 */
466#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000
467#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000
468
469/* PCI Config Type 1 */
470#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000
471#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000
472
473/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
474#define CA_PIO_PCI_IO 0x03000000
475#define CA_PIO_PCI_IO_LEN 0x05000000
476
477/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
478/* use Fast Write if enabled and coretalk packet type is a GFX request */
479#define CA_PIO_PCI_MEM_OFFSET 0x08000000
480#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000
481
482/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
483/* use Fast Write if enabled and coretalk packet type is a GFX request */
484#define CA_PIO_PCI_MEM 0x40000000
485#define CA_PIO_PCI_MEM_LEN 0xc0000000
486
487/*
488 * DMA space
489 *
490 * The CA aperature (ie. bus address range) mapped by the GART is segmented into
491 * two parts. The lower portion of the aperature is used for mapping 32 bit
492 * PCI addresses which are managed by the dma interfaces in this file. The
493 * upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
494 * The AGP portion of the aperature is managed by the agpgart_be.c driver
495 * in drivers/linux/agp. There are ca-specific hooks in that driver to
496 * manipulate the gart, but management of the AGP portion of the aperature
497 * is the responsibility of that driver.
498 *
499 * CA allows three main types of DMA mapping:
500 *
501 * PCI 64-bit Managed by this driver
502 * PCI 32-bit Managed by this driver
503 * AGP 48-bit Managed by hooks in the /dev/agpgart driver
504 *
505 * All of the above can optionally be remapped through the GART. The following
506 * table lists the combinations of addressing types and GART remapping that
507 * is currently supported by the driver (h/w supports all, s/w limits this):
508 *
509 * PCI64 PCI32 AGP48
510 * GART no yes yes
511 * Direct yes yes no
512 *
513 * GART remapping of PCI64 is not done because there is no need to. The
514 * 64 bit PCI address holds all of the information necessary to target any
515 * memory in the system.
516 *
517 * AGP48 is always mapped through the GART. Management of the AGP48 portion
518 * of the aperature is the responsibility of code in the agpgart_be driver.
519 *
520 * The non-64 bit bus address space will currently be partitioned like this:
521 *
522 * 0xffff_ffff_ffff +--------
523 * | AGP48 direct
524 * | Space managed by this driver
525 * CA_AGP_DIRECT_BASE +--------
526 * | AGP GART mapped (gfx aperature)
527 * | Space managed by /dev/agpgart driver
528 * | This range is exposed to the agpgart
529 * | driver as the "graphics aperature"
530 * CA_AGP_MAPPED_BASE +-----
531 * | PCI GART mapped
532 * | Space managed by this driver
533 * CA_PCI32_MAPPED_BASE +----
534 * | PCI32 direct
535 * | Space managed by this driver
536 * 0xC000_0000 +--------
537 * (CA_PCI32_DIRECT_BASE)
538 *
539 * The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
540 * is what we call the CA aperature. Addresses falling in this range will
541 * be remapped using the GART.
542 *
543 * The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
544 * is what we call the graphics aperature. This is a subset of the CA
545 * aperature and is under the control of the agpgart_be driver.
546 *
547 * CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
548 * somewhat arbitrary values. The known constraints on choosing these is:
549 *
550 * 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
551 * must be one of the values supported by the ca_gart_aperature register.
552 * Currently valid values are: 4MB through 4096MB in powers of 2 increments
553 *
554 * 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
555 * must be in MB units since that's what the agpgart driver assumes.
556 */
557
558/*
559 * Define Bus DMA ranges. These are configurable (see constraints above)
560 * and will probably need tuning based on experience.
561 */
562
563
564/*
565 * 11/24/03
566 * CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
567 * generally unusable. The problem is that for PCI direct 32
568 * DMA's, all 32 bits of the bus address are used to form the lower 32 bits
569 * of the coretalk address, and coretalk bits 38:32 come from a register.
570 * Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
571 * for DMA (the rest is allocated to PIO), host node addresses need to be
572 * such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
573 * as well. So there can be no PCI32 direct DMA below 3GB!! For this
574 * reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
575 * tioca_dma_direct32() a noop but preserves the code flow should this issue
576 * be fixed in a respin.
577 *
578 * For now, all PCI32 DMA's must be mapped through the GART.
579 */
580
581#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
582#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */
583
584#define CA_PCI32_MAPPED_BASE 0xC0000000UL
585#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */
586
587#define CA_AGP_MAPPED_BASE 0x80000000UL
588#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */
589
590#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */
591#define CA_AGP_DIRECT_SIZE 0x40000000UL
592
593#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE)
594#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
595
596#endif /* _ASM_IA64_SN_TIO_TIOCA_H */
diff --git a/include/asm-ia64/sn/tioca_provider.h b/include/asm-ia64/sn/tioca_provider.h
new file mode 100644
index 000000000000..b6acc22ab239
--- /dev/null
+++ b/include/asm-ia64/sn/tioca_provider.h
@@ -0,0 +1,206 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
10#define _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H
11
12#include <asm/sn/tioca.h>
13
14/*
15 * WAR enables
16 * Defines for individual WARs. Each is a bitmask of applicable
17 * part revision numbers. (1 << 1) == rev A, (1 << 2) == rev B,
18 * (3 << 1) == (rev A or rev B), etc
19 */
20
21#define TIOCA_WAR_ENABLED(pv, tioca_common) \
22 ((1 << tioca_common->ca_rev) & pv)
23
24 /* TIO:ICE:FRZ:Freezer loses a PIO data ucred on PIO RD RSP with CW error */
25#define PV907908 (1 << 1)
26 /* ATI config space problems after BIOS execution starts */
27#define PV908234 (1 << 1)
28 /* CA:AGPDMA write request data mismatch with ABC1CL merge */
29#define PV895469 (1 << 1)
30 /* TIO:CA TLB invalidate of written GART entries possibly not occuring in CA*/
31#define PV910244 (1 << 1)
32
33struct tioca_dmamap{
34 struct list_head cad_list; /* headed by ca_list */
35
36 dma_addr_t cad_dma_addr; /* Linux dma handle */
37 uint cad_gart_entry; /* start entry in ca_gart_pagemap */
38 uint cad_gart_size; /* #entries for this map */
39};
40
41/*
42 * Kernel only fields. Prom may look at this stuff for debugging only.
43 * Access this structure through the ca_kernel_private ptr.
44 */
45
46struct tioca_common ;
47
48struct tioca_kernel {
49 struct tioca_common *ca_common; /* tioca this belongs to */
50 struct list_head ca_list; /* list of all ca's */
51 struct list_head ca_dmamaps;
52 spinlock_t ca_lock; /* Kernel lock */
53 cnodeid_t ca_closest_node;
54 struct list_head *ca_devices; /* bus->devices */
55
56 /*
57 * General GART stuff
58 */
59 uint64_t ca_ap_size; /* size of aperature in bytes */
60 uint32_t ca_gart_entries; /* # uint64_t entries in gart */
61 uint32_t ca_ap_pagesize; /* aperature page size in bytes */
62 uint64_t ca_ap_bus_base; /* bus address of CA aperature */
63 uint64_t ca_gart_size; /* gart size in bytes */
64 uint64_t *ca_gart; /* gart table vaddr */
65 uint64_t ca_gart_coretalk_addr; /* gart coretalk addr */
66 uint8_t ca_gart_iscoherent; /* used in tioca_tlbflush */
67
68 /* PCI GART convenience values */
69 uint64_t ca_pciap_base; /* pci aperature bus base address */
70 uint64_t ca_pciap_size; /* pci aperature size (bytes) */
71 uint64_t ca_pcigart_base; /* gfx GART bus base address */
72 uint64_t *ca_pcigart; /* gfx GART vm address */
73 uint32_t ca_pcigart_entries;
74 uint32_t ca_pcigart_start; /* PCI start index in ca_gart */
75 void *ca_pcigart_pagemap;
76
77 /* AGP GART convenience values */
78 uint64_t ca_gfxap_base; /* gfx aperature bus base address */
79 uint64_t ca_gfxap_size; /* gfx aperature size (bytes) */
80 uint64_t ca_gfxgart_base; /* gfx GART bus base address */
81 uint64_t *ca_gfxgart; /* gfx GART vm address */
82 uint32_t ca_gfxgart_entries;
83 uint32_t ca_gfxgart_start; /* agpgart start index in ca_gart */
84};
85
86/*
87 * Common tioca info shared between kernel and prom
88 *
89 * DO NOT CHANGE THIS STRUCT WITHOUT MAKING CORRESPONDING CHANGES
90 * TO THE PROM VERSION.
91 */
92
93struct tioca_common {
94 struct pcibus_bussoft ca_common; /* common pciio header */
95
96 uint32_t ca_rev;
97 uint32_t ca_closest_nasid;
98
99 uint64_t ca_prom_private;
100 uint64_t ca_kernel_private;
101};
102
103/**
104 * tioca_paddr_to_gart - Convert an SGI coretalk address to a CA GART entry
105 * @paddr: page address to convert
106 *
107 * Convert a system [coretalk] address to a GART entry. GART entries are
108 * formed using the following:
109 *
110 * data = ( (1<<63) | ( (REMAP_NODE_ID << 40) | (MD_CHIPLET_ID << 38) |
111 * (REMAP_SYS_ADDR) ) >> 12 )
112 *
113 * DATA written to 1 GART TABLE Entry in system memory is remapped system
114 * addr for 1 page
115 *
116 * The data is for coretalk address format right shifted 12 bits with a
117 * valid bit.
118 *
119 * GART_TABLE_ENTRY [ 25:0 ] -- REMAP_SYS_ADDRESS[37:12].
120 * GART_TABLE_ENTRY [ 27:26 ] -- SHUB MD chiplet id.
121 * GART_TABLE_ENTRY [ 41:28 ] -- REMAP_NODE_ID.
122 * GART_TABLE_ENTRY [ 63 ] -- Valid Bit
123 */
124static inline u64
125tioca_paddr_to_gart(unsigned long paddr)
126{
127 /*
128 * We are assuming right now that paddr already has the correct
129 * format since the address from xtalk_dmaXXX should already have
130 * NODE_ID, CHIPLET_ID, and SYS_ADDR in the correct locations.
131 */
132
133 return ((paddr) >> 12) | (1UL << 63);
134}
135
136/**
137 * tioca_physpage_to_gart - Map a host physical page for SGI CA based DMA
138 * @page_addr: system page address to map
139 */
140
141static inline unsigned long
142tioca_physpage_to_gart(uint64_t page_addr)
143{
144 uint64_t coretalk_addr;
145
146 coretalk_addr = PHYS_TO_TIODMA(page_addr);
147 if (!coretalk_addr) {
148 return 0;
149 }
150
151 return tioca_paddr_to_gart(coretalk_addr);
152}
153
154/**
155 * tioca_tlbflush - invalidate cached SGI CA GART TLB entries
156 * @tioca_kernel: CA context
157 *
158 * Invalidate tlb entries for a given CA GART. Main complexity is to account
159 * for revA bug.
160 */
161static inline void
162tioca_tlbflush(struct tioca_kernel *tioca_kernel)
163{
164 volatile uint64_t tmp;
165 volatile struct tioca *ca_base;
166 struct tioca_common *tioca_common;
167
168 tioca_common = tioca_kernel->ca_common;
169 ca_base = (struct tioca *)tioca_common->ca_common.bs_base;
170
171 /*
172 * Explicit flushes not needed if GART is in cached mode
173 */
174 if (tioca_kernel->ca_gart_iscoherent) {
175 if (TIOCA_WAR_ENABLED(PV910244, tioca_common)) {
176 /*
177 * PV910244: RevA CA needs explicit flushes.
178 * Need to put GART into uncached mode before
179 * flushing otherwise the explicit flush is ignored.
180 *
181 * Alternate WAR would be to leave GART cached and
182 * touch every CL aligned GART entry.
183 */
184
185 ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
186 ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
187 ca_base->ca_control2 |=
188 (0x2ull << CA_GART_MEM_PARAM_SHFT);
189 tmp = ca_base->ca_control2;
190 }
191
192 return;
193 }
194
195 /*
196 * Gart in uncached mode ... need an explicit flush.
197 */
198
199 ca_base->ca_control2 |= CA_GART_FLUSH_TLB;
200 tmp = ca_base->ca_control2;
201}
202
203extern uint32_t tioca_gart_found;
204extern int tioca_init_provider(void);
205extern void tioca_fastwrite_enable(struct tioca_kernel *tioca_kern);
206#endif /* _ASM_IA64_SN_TIO_CA_AGP_PROVIDER_H */
diff --git a/include/asm-ia64/sn/tiocx.h b/include/asm-ia64/sn/tiocx.h
new file mode 100644
index 000000000000..c5447a504509
--- /dev/null
+++ b/include/asm-ia64/sn/tiocx.h
@@ -0,0 +1,71 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (c) 2005 Silicon Graphics, Inc. All rights reserved.
7 */
8
9#ifndef _ASM_IA64_SN_TIO_TIOCX_H
10#define _ASM_IA64_SN_TIO_TIOCX_H
11
12#ifdef __KERNEL__
13
14struct cx_id_s {
15 unsigned int part_num;
16 unsigned int mfg_num;
17 int nasid;
18};
19
20struct cx_dev {
21 struct cx_id_s cx_id;
22 void *soft; /* driver specific */
23 struct hubdev_info *hubdev;
24 struct device dev;
25 struct cx_drv *driver;
26};
27
28struct cx_device_id {
29 unsigned int part_num;
30 unsigned int mfg_num;
31};
32
33struct cx_drv {
34 char *name;
35 const struct cx_device_id *id_table;
36 struct device_driver driver;
37 int (*probe) (struct cx_dev * dev, const struct cx_device_id * id);
38 int (*remove) (struct cx_dev * dev);
39};
40
41/* create DMA address by stripping AS bits */
42#define TIOCX_DMA_ADDR(a) (uint64_t)((uint64_t)(a) & 0xffffcfffffffffUL)
43
44#define TIOCX_TO_TIOCX_DMA_ADDR(a) (uint64_t)(((uint64_t)(a) & 0xfffffffff) | \
45 ((((uint64_t)(a)) & 0xffffc000000000UL) <<2))
46
47#define TIO_CE_ASIC_PARTNUM 0xce00
48#define TIOCX_CORELET 3
49
50/* These are taken from tio_mmr_as.h */
51#define TIO_ICE_FRZ_CFG TIO_MMR_ADDR_MOD(0x00000000b0008100UL)
52#define TIO_ICE_PMI_TX_CFG TIO_MMR_ADDR_MOD(0x00000000b000b100UL)
53#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3 TIO_MMR_ADDR_MOD(0x00000000b000be18UL)
54#define TIO_ICE_PMI_TX_DYN_CREDIT_STAT_CB3_CREDIT_CNT_MASK 0x000000000000000fUL
55
56#define to_cx_dev(n) container_of(n, struct cx_dev, dev)
57#define to_cx_driver(drv) container_of(drv, struct cx_drv, driver)
58
59extern struct sn_irq_info *tiocx_irq_alloc(nasid_t, int, int, nasid_t, int);
60extern void tiocx_irq_free(struct sn_irq_info *);
61extern int cx_device_unregister(struct cx_dev *);
62extern int cx_device_register(nasid_t, int, int, struct hubdev_info *);
63extern int cx_driver_unregister(struct cx_drv *);
64extern int cx_driver_register(struct cx_drv *);
65extern uint64_t tiocx_dma_addr(uint64_t addr);
66extern uint64_t tiocx_swin_base(int nasid);
67extern void tiocx_mmr_store(int nasid, uint64_t offset, uint64_t value);
68extern uint64_t tiocx_mmr_load(int nasid, uint64_t offset);
69
70#endif // __KERNEL__
71#endif // _ASM_IA64_SN_TIO_TIOCX__
diff --git a/include/asm-ia64/sn/types.h b/include/asm-ia64/sn/types.h
index 586ed47cae9c..8e04ee211e59 100644
--- a/include/asm-ia64/sn/types.h
+++ b/include/asm-ia64/sn/types.h
@@ -16,7 +16,8 @@ typedef signed short nasid_t; /* node id in numa-as-id space */
16typedef signed char partid_t; /* partition ID type */ 16typedef signed char partid_t; /* partition ID type */
17typedef unsigned int moduleid_t; /* user-visible module number type */ 17typedef unsigned int moduleid_t; /* user-visible module number type */
18typedef unsigned int cmoduleid_t; /* kernel compact module id type */ 18typedef unsigned int cmoduleid_t; /* kernel compact module id type */
19typedef signed char slabid_t; 19typedef unsigned char slotid_t; /* slot (blade) within module */
20typedef unsigned char slabid_t; /* slab (asic) within slot */
20typedef u64 nic_t; 21typedef u64 nic_t;
21typedef unsigned long iopaddr_t; 22typedef unsigned long iopaddr_t;
22typedef unsigned long paddr_t; 23typedef unsigned long paddr_t;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-20 11:04:41 -0500