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authorLinus Torvalds <torvalds@linux-foundation.org>2008-08-28 15:30:59 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-08-28 15:30:59 -0400
commite52c8857e0ca3214aa7e2a746000ac0f3016b345 (patch)
tree9fdc6bbe990a8d8dd5fc74c2145e990ae8f2f916 /include
parent9c2bdac40eba639c438690b1245a020e7c2530df (diff)
parentc1b362e3b4d331a63915b268a33207311a439d60 (diff)
Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: update defconfigs x86: msr: fix bogus return values from rdmsr_safe/wrmsr_safe x86: cpuid: correct return value on partial operations x86: msr: correct return value on partial operations x86: cpuid: propagate error from smp_call_function_single() x86: msr: propagate errors from smp_call_function_single() smp: have smp_call_function_single() detect invalid CPUs
Diffstat (limited to 'include')
-rw-r--r--include/asm-x86/msr.h27
1 files changed, 14 insertions, 13 deletions
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index ca110ee73f07..2362cfda1fbc 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -52,14 +52,14 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
52{ 52{
53 DECLARE_ARGS(val, low, high); 53 DECLARE_ARGS(val, low, high);
54 54
55 asm volatile("2: rdmsr ; xor %0,%0\n" 55 asm volatile("2: rdmsr ; xor %[err],%[err]\n"
56 "1:\n\t" 56 "1:\n\t"
57 ".section .fixup,\"ax\"\n\t" 57 ".section .fixup,\"ax\"\n\t"
58 "3: mov %3,%0 ; jmp 1b\n\t" 58 "3: mov %[fault],%[err] ; jmp 1b\n\t"
59 ".previous\n\t" 59 ".previous\n\t"
60 _ASM_EXTABLE(2b, 3b) 60 _ASM_EXTABLE(2b, 3b)
61 : "=r" (*err), EAX_EDX_RET(val, low, high) 61 : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
62 : "c" (msr), "i" (-EFAULT)); 62 : "c" (msr), [fault] "i" (-EFAULT));
63 return EAX_EDX_VAL(val, low, high); 63 return EAX_EDX_VAL(val, low, high);
64} 64}
65 65
@@ -73,15 +73,15 @@ static inline int native_write_msr_safe(unsigned int msr,
73 unsigned low, unsigned high) 73 unsigned low, unsigned high)
74{ 74{
75 int err; 75 int err;
76 asm volatile("2: wrmsr ; xor %0,%0\n" 76 asm volatile("2: wrmsr ; xor %[err],%[err]\n"
77 "1:\n\t" 77 "1:\n\t"
78 ".section .fixup,\"ax\"\n\t" 78 ".section .fixup,\"ax\"\n\t"
79 "3: mov %4,%0 ; jmp 1b\n\t" 79 "3: mov %[fault],%[err] ; jmp 1b\n\t"
80 ".previous\n\t" 80 ".previous\n\t"
81 _ASM_EXTABLE(2b, 3b) 81 _ASM_EXTABLE(2b, 3b)
82 : "=a" (err) 82 : [err] "=a" (err)
83 : "c" (msr), "0" (low), "d" (high), 83 : "c" (msr), "0" (low), "d" (high),
84 "i" (-EFAULT) 84 [fault] "i" (-EFAULT)
85 : "memory"); 85 : "memory");
86 return err; 86 return err;
87} 87}
@@ -192,19 +192,20 @@ do { \
192#define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0) 192#define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
193 193
194#ifdef CONFIG_SMP 194#ifdef CONFIG_SMP
195void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 195int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
196void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 196int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
197int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); 197int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
198
199int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); 198int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
200#else /* CONFIG_SMP */ 199#else /* CONFIG_SMP */
201static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) 200static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
202{ 201{
203 rdmsr(msr_no, *l, *h); 202 rdmsr(msr_no, *l, *h);
203 return 0;
204} 204}
205static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) 205static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
206{ 206{
207 wrmsr(msr_no, l, h); 207 wrmsr(msr_no, l, h);
208 return 0;
208} 209}
209static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, 210static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
210 u32 *l, u32 *h) 211 u32 *l, u32 *h)