diff options
author | Anton Blanchard <anton@samba.org> | 2005-07-07 20:56:11 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2005-07-07 21:23:37 -0400 |
commit | a2f7a9ce2a5c3d21cc0eb37a03da603b44ba4b09 (patch) | |
tree | 20d782192f849d9f8f1eabd465246e8fd292324a /include | |
parent | 315a699851722a6bc31e35f91562f31f55d4c4a2 (diff) |
[PATCH] ppc64: Fix runlatch code to work on pseries machines
Not all ppc64 CPUs have the CTRL SPR, so we need a cputable feature for it.
Signed-off-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-ppc64/cputable.h | 3 | ||||
-rw-r--r-- | include/asm-ppc64/processor.h | 17 |
2 files changed, 13 insertions, 7 deletions
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h index cbbfbec78b6b..d67fa9e26079 100644 --- a/include/asm-ppc64/cputable.h +++ b/include/asm-ppc64/cputable.h | |||
@@ -138,6 +138,7 @@ extern firmware_feature_t firmware_features_table[]; | |||
138 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) | 138 | #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000) |
139 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) | 139 | #define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000) |
140 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) | 140 | #define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000) |
141 | #define CPU_FTR_CTRL ASM_CONST(0x0000100000000000) | ||
141 | 142 | ||
142 | /* Platform firmware features */ | 143 | /* Platform firmware features */ |
143 | #define FW_FTR_ ASM_CONST(0x0000000000000001) | 144 | #define FW_FTR_ ASM_CONST(0x0000000000000001) |
@@ -148,7 +149,7 @@ extern firmware_feature_t firmware_features_table[]; | |||
148 | 149 | ||
149 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ | 150 | #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ |
150 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ | 151 | CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \ |
151 | CPU_FTR_NODSISRALIGN) | 152 | CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL) |
152 | 153 | ||
153 | /* iSeries doesn't support large pages */ | 154 | /* iSeries doesn't support large pages */ |
154 | #ifdef CONFIG_PPC_ISERIES | 155 | #ifdef CONFIG_PPC_ISERIES |
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h index af28aa55d8c1..06aa07c2c71d 100644 --- a/include/asm-ppc64/processor.h +++ b/include/asm-ppc64/processor.h | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <asm/ptrace.h> | 20 | #include <asm/ptrace.h> |
21 | #include <asm/types.h> | 21 | #include <asm/types.h> |
22 | #include <asm/systemcfg.h> | 22 | #include <asm/systemcfg.h> |
23 | #include <asm/cputable.h> | ||
23 | 24 | ||
24 | /* Machine State Register (MSR) Fields */ | 25 | /* Machine State Register (MSR) Fields */ |
25 | #define MSR_SF_LG 63 /* Enable 64 bit mode */ | 26 | #define MSR_SF_LG 63 /* Enable 64 bit mode */ |
@@ -501,18 +502,22 @@ static inline void ppc64_runlatch_on(void) | |||
501 | { | 502 | { |
502 | unsigned long ctrl; | 503 | unsigned long ctrl; |
503 | 504 | ||
504 | ctrl = mfspr(SPRN_CTRLF); | 505 | if (cpu_has_feature(CPU_FTR_CTRL)) { |
505 | ctrl |= CTRL_RUNLATCH; | 506 | ctrl = mfspr(SPRN_CTRLF); |
506 | mtspr(SPRN_CTRLT, ctrl); | 507 | ctrl |= CTRL_RUNLATCH; |
508 | mtspr(SPRN_CTRLT, ctrl); | ||
509 | } | ||
507 | } | 510 | } |
508 | 511 | ||
509 | static inline void ppc64_runlatch_off(void) | 512 | static inline void ppc64_runlatch_off(void) |
510 | { | 513 | { |
511 | unsigned long ctrl; | 514 | unsigned long ctrl; |
512 | 515 | ||
513 | ctrl = mfspr(SPRN_CTRLF); | 516 | if (cpu_has_feature(CPU_FTR_CTRL)) { |
514 | ctrl &= ~CTRL_RUNLATCH; | 517 | ctrl = mfspr(SPRN_CTRLF); |
515 | mtspr(SPRN_CTRLT, ctrl); | 518 | ctrl &= ~CTRL_RUNLATCH; |
519 | mtspr(SPRN_CTRLT, ctrl); | ||
520 | } | ||
516 | } | 521 | } |
517 | 522 | ||
518 | #endif /* __KERNEL__ */ | 523 | #endif /* __KERNEL__ */ |