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authorDmitry Torokhov <dtor_core@ameritech.net>2005-06-06 03:21:03 -0400
committerDmitry Torokhov <dtor_core@ameritech.net>2005-06-06 03:21:03 -0400
commit3c241f8337542655ee013a661b7f1770f561d3ef (patch)
tree79dd9a5dd12d305e1be7b926d414855377d2e192 /include
parentdbf4ccd6043e58ed32fbf253fb3f0a9991e4c13a (diff)
parenteae936e21bd726f9d9555f2262d439fbcd61dccf (diff)
Automatic merge of rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include')
-rw-r--r--include/asm-ppc64/processor.h186
-rw-r--r--include/asm-ppc64/prom.h13
-rw-r--r--include/asm-ppc64/thread_info.h4
-rw-r--r--include/asm-s390/user.h2
-rw-r--r--include/asm-sparc64/iommu.h2
-rw-r--r--include/asm-sparc64/pbm.h8
-rw-r--r--include/linux/if_shaper.h3
-rw-r--r--include/linux/libata.h58
-rw-r--r--include/linux/netdevice.h2
-rw-r--r--include/linux/pci_ids.h6
-rw-r--r--include/linux/usb.h6
11 files changed, 104 insertions, 186 deletions
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 0035efe2db2b..809c634ba1df 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -120,103 +120,18 @@
120 120
121/* Special Purpose Registers (SPRNs)*/ 121/* Special Purpose Registers (SPRNs)*/
122 122
123#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
124#define SPRN_CTR 0x009 /* Count Register */ 123#define SPRN_CTR 0x009 /* Count Register */
125#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ 124#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
126#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ 125#define DABR_TRANSLATION (1UL << 2)
127#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
128#define SPRN_DAR 0x013 /* Data Address Register */ 126#define SPRN_DAR 0x013 /* Data Address Register */
129#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
130#define DBCR_EDM 0x80000000
131#define DBCR_IDM 0x40000000
132#define DBCR_RST(x) (((x) & 0x3) << 28)
133#define DBCR_RST_NONE 0
134#define DBCR_RST_CORE 1
135#define DBCR_RST_CHIP 2
136#define DBCR_RST_SYSTEM 3
137#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
138#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
139#define DBCR_EDE 0x02000000 /* Exception Debug Event */
140#define DBCR_TDE 0x01000000 /* TRAP Debug Event */
141#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
142#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
143#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
144#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
145#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
146#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
147#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
148#define DAC_BYTE 0
149#define DAC_HALF 1
150#define DAC_WORD 2
151#define DAC_QUAD 3
152#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
153#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
154#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
155#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
156#define DBCR_SED 0x00000020 /* Second Exception Debug Event */
157#define DBCR_STD 0x00000010 /* Second Trap Debug Event */
158#define DBCR_SIA 0x00000008 /* Second IAC Enable */
159#define DBCR_SDA 0x00000004 /* Second DAC Enable */
160#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
161#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
162#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
163#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
164#define SPRN_DBSR 0x3F0 /* Debug Status Register */
165#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
166#define DCCR_NOCACHE 0 /* Noncacheable */
167#define DCCR_CACHE 1 /* Cacheable */
168#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
169#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
170#define DCWR_COPY 0 /* Copy-back */
171#define DCWR_WRITE 1 /* Write-through */
172#define SPRN_DEAR 0x3D5 /* Data Error Address Register */
173#define SPRN_DEC 0x016 /* Decrement Register */ 127#define SPRN_DEC 0x016 /* Decrement Register */
174#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
175#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ 128#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
176#define DSISR_NOHPTE 0x40000000 /* no translation found */ 129#define DSISR_NOHPTE 0x40000000 /* no translation found */
177#define DSISR_PROTFAULT 0x08000000 /* protection fault */ 130#define DSISR_PROTFAULT 0x08000000 /* protection fault */
178#define DSISR_ISSTORE 0x02000000 /* access was a store */ 131#define DSISR_ISSTORE 0x02000000 /* access was a store */
179#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */ 132#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
180#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */ 133#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
181#define SPRN_EAR 0x11A /* External Address Register */
182#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
183#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
184#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
185#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
186#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
187#define ESR_PIL 0x08000000 /* Program Exception - Illegal */
188#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
189#define ESR_PTR 0x02000000 /* Program Exception - Trap */
190#define ESR_DST 0x00800000 /* Storage Exception - Data miss */
191#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
192#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
193#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
194#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
195#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ 134#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
196#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
197#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
198#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
199#define HID0_SBCLK (1<<27)
200#define HID0_EICE (1<<26)
201#define HID0_ECLK (1<<25)
202#define HID0_PAR (1<<24)
203#define HID0_DOZE (1<<23)
204#define HID0_NAP (1<<22)
205#define HID0_SLEEP (1<<21)
206#define HID0_DPM (1<<20)
207#define HID0_ICE (1<<15) /* Instruction Cache Enable */
208#define HID0_DCE (1<<14) /* Data Cache Enable */
209#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
210#define HID0_DLOCK (1<<12) /* Data Cache Lock */
211#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
212#define HID0_DCI (1<<10) /* Data Cache Invalidate */
213#define HID0_SPD (1<<9) /* Speculative disable */
214#define HID0_SGE (1<<7) /* Store Gathering Enable */
215#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
216#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */
217#define HID0_ABE (1<<3) /* Address Broadcast Enable */
218#define HID0_BHTE (1<<2) /* Branch History Table Enable */
219#define HID0_BTCD (1<<1) /* Branch target cache disable */
220#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */ 135#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */
221#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ 136#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
222#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ 137#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
@@ -225,23 +140,8 @@
225#define SPRN_HID5 0x3F6 /* 970 HID5 */ 140#define SPRN_HID5 0x3F6 /* 970 HID5 */
226#define SPRN_TSC 0x3FD /* Thread switch control */ 141#define SPRN_TSC 0x3FD /* Thread switch control */
227#define SPRN_TST 0x3FC /* Thread switch timeout */ 142#define SPRN_TST 0x3FC /* Thread switch timeout */
228#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
229#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
230#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
231#define ICCR_NOCACHE 0 /* Noncacheable */
232#define ICCR_CACHE 1 /* Cacheable */
233#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
234#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
235#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
236#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
237#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
238#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ 143#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
239#define SPRN_LR 0x008 /* Link Register */ 144#define SPRN_LR 0x008 /* Link Register */
240#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
241#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
242#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
243#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
244#define SPRN_PID 0x3B1 /* Process ID */
245#define SPRN_PIR 0x3FF /* Processor Identification Register */ 145#define SPRN_PIR 0x3FF /* Processor Identification Register */
246#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 146#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
247#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */ 147#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */
@@ -249,9 +149,6 @@
249#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 149#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
250#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 150#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
251#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 151#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
252#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
253#define SGR_NORMAL 0
254#define SGR_GUARDED 1
255#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 152#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
256#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 153#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
257#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 154#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
@@ -264,50 +161,12 @@
264#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */ 161#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */
265#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */ 162#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */
266#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */ 163#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
267#define SPRN_TCR 0x3DA /* Timer Control Register */
268#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
269#define WP_2_17 0 /* 2^17 clocks */
270#define WP_2_21 1 /* 2^21 clocks */
271#define WP_2_25 2 /* 2^25 clocks */
272#define WP_2_29 3 /* 2^29 clocks */
273#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
274#define WRC_NONE 0 /* No reset will occur */
275#define WRC_CORE 1 /* Core reset will occur */
276#define WRC_CHIP 2 /* Chip reset will occur */
277#define WRC_SYSTEM 3 /* System reset will occur */
278#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
279#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
280#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
281#define FP_2_9 0 /* 2^9 clocks */
282#define FP_2_13 1 /* 2^13 clocks */
283#define FP_2_17 2 /* 2^17 clocks */
284#define FP_2_21 3 /* 2^21 clocks */
285#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
286#define TCR_ARE 0x00400000 /* Auto Reload Enable */
287#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
288#define THRM1_TIN (1<<0)
289#define THRM1_TIV (1<<1)
290#define THRM1_THRES (0x7f<<2)
291#define THRM1_TID (1<<29)
292#define THRM1_TIE (1<<30)
293#define THRM1_V (1<<31)
294#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
295#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
296#define THRM3_E (1<<31)
297#define SPRN_TSR 0x3D8 /* Timer Status Register */
298#define TSR_ENW 0x80000000 /* Enable Next Watchdog */
299#define TSR_WIS 0x40000000 /* WDT Interrupt Status */
300#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
301#define WRS_NONE 0 /* No WDT reset occurred */
302#define WRS_CORE 1 /* WDT forced core reset */
303#define WRS_CHIP 2 /* WDT forced chip reset */
304#define WRS_SYSTEM 3 /* WDT forced system reset */
305#define TSR_PIS 0x08000000 /* PIT Interrupt Status */
306#define TSR_FIS 0x04000000 /* FIT Interrupt Status */
307#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ 164#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
308#define SPRN_XER 0x001 /* Fixed Point Exception Register */ 165#define SPRN_XER 0x001 /* Fixed Point Exception Register */
309#define SPRN_ZPR 0x3B0 /* Zone Protection Register */
310#define SPRN_VRSAVE 0x100 /* Vector save */ 166#define SPRN_VRSAVE 0x100 /* Vector save */
167#define SPRN_CTRLF 0x088
168#define SPRN_CTRLT 0x098
169#define CTRL_RUNLATCH 0x1
311 170
312/* Performance monitor SPRs */ 171/* Performance monitor SPRs */
313#define SPRN_SIAR 780 172#define SPRN_SIAR 780
@@ -352,28 +211,19 @@
352#define CTR SPRN_CTR /* Counter Register */ 211#define CTR SPRN_CTR /* Counter Register */
353#define DAR SPRN_DAR /* Data Address Register */ 212#define DAR SPRN_DAR /* Data Address Register */
354#define DABR SPRN_DABR /* Data Address Breakpoint Register */ 213#define DABR SPRN_DABR /* Data Address Breakpoint Register */
355#define DCMP SPRN_DCMP /* Data TLB Compare Register */
356#define DEC SPRN_DEC /* Decrement Register */ 214#define DEC SPRN_DEC /* Decrement Register */
357#define DMISS SPRN_DMISS /* Data TLB Miss Register */
358#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ 215#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
359#define EAR SPRN_EAR /* External Address Register */
360#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
361#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
362#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ 216#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
363#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */ 217#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */
364#define NIADORM SPRN_NIADORM /* NIA Dormant Register */ 218#define NIADORM SPRN_NIADORM /* NIA Dormant Register */
365#define TSC SPRN_TSC /* Thread switch control */ 219#define TSC SPRN_TSC /* Thread switch control */
366#define TST SPRN_TST /* Thread switch timeout */ 220#define TST SPRN_TST /* Thread switch timeout */
367#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ 221#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
368#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
369#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
370#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
371#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ 222#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
372#define __LR SPRN_LR 223#define __LR SPRN_LR
373#define PVR SPRN_PVR /* Processor Version */ 224#define PVR SPRN_PVR /* Processor Version */
374#define PIR SPRN_PIR /* Processor ID */ 225#define PIR SPRN_PIR /* Processor ID */
375#define PURR SPRN_PURR /* Processor Utilization of Resource Register */ 226#define PURR SPRN_PURR /* Processor Utilization of Resource Register */
376//#define RPA SPRN_RPA /* Required Physical Address Register */
377#define SDR1 SPRN_SDR1 /* MMU hash base register */ 227#define SDR1 SPRN_SDR1 /* MMU hash base register */
378#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ 228#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
379#define SPR1 SPRN_SPRG1 229#define SPR1 SPRN_SPRG1
@@ -389,10 +239,6 @@
389#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ 239#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
390#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ 240#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
391#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ 241#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
392#define ICTC 1019
393#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
394#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
395#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
396#define XER SPRN_XER 242#define XER SPRN_XER
397 243
398/* Processor Version Register (PVR) field extraction */ 244/* Processor Version Register (PVR) field extraction */
@@ -436,12 +282,6 @@
436#define XGLUE(a,b) a##b 282#define XGLUE(a,b) a##b
437#define GLUE(a,b) XGLUE(a,b) 283#define GLUE(a,b) XGLUE(a,b)
438 284
439/* iSeries CTRL register (for runlatch) */
440
441#define CTRLT 0x098
442#define CTRLF 0x088
443#define RUNLATCH 0x0001
444
445#ifdef __ASSEMBLY__ 285#ifdef __ASSEMBLY__
446 286
447#define _GLOBAL(name) \ 287#define _GLOBAL(name) \
@@ -656,6 +496,24 @@ static inline void prefetchw(const void *x)
656 496
657#define HAVE_ARCH_PICK_MMAP_LAYOUT 497#define HAVE_ARCH_PICK_MMAP_LAYOUT
658 498
499static inline void ppc64_runlatch_on(void)
500{
501 unsigned long ctrl;
502
503 ctrl = mfspr(SPRN_CTRLF);
504 ctrl |= CTRL_RUNLATCH;
505 mtspr(SPRN_CTRLT, ctrl);
506}
507
508static inline void ppc64_runlatch_off(void)
509{
510 unsigned long ctrl;
511
512 ctrl = mfspr(SPRN_CTRLF);
513 ctrl &= ~CTRL_RUNLATCH;
514 mtspr(SPRN_CTRLT, ctrl);
515}
516
659#endif /* __KERNEL__ */ 517#endif /* __KERNEL__ */
660 518
661#endif /* __ASSEMBLY__ */ 519#endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index 2440a2c90ae9..04b1a84f7ca3 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -147,9 +147,7 @@ struct device_node {
147 struct device_node *sibling; 147 struct device_node *sibling;
148 struct device_node *next; /* next device of same type */ 148 struct device_node *next; /* next device of same type */
149 struct device_node *allnext; /* next in list of all nodes */ 149 struct device_node *allnext; /* next in list of all nodes */
150 struct proc_dir_entry *pde; /* this node's proc directory */ 150 struct proc_dir_entry *pde; /* this node's proc directory */
151 struct proc_dir_entry *name_link; /* name symlink */
152 struct proc_dir_entry *addr_link; /* addr symlink */
153 struct kref kref; 151 struct kref kref;
154 unsigned long _flags; 152 unsigned long _flags;
155}; 153};
@@ -174,15 +172,6 @@ static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_e
174 dn->pde = de; 172 dn->pde = de;
175} 173}
176 174
177static void inline set_node_name_link(struct device_node *dn, struct proc_dir_entry *de)
178{
179 dn->name_link = de;
180}
181
182static void inline set_node_addr_link(struct device_node *dn, struct proc_dir_entry *de)
183{
184 dn->addr_link = de;
185}
186 175
187/* OBSOLETE: Old stlye node lookup */ 176/* OBSOLETE: Old stlye node lookup */
188extern struct device_node *find_devices(const char *name); 177extern struct device_node *find_devices(const char *name);
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-ppc64/thread_info.h
index 037b5e06083c..48b7900e90ec 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-ppc64/thread_info.h
@@ -96,7 +96,7 @@ static inline struct thread_info *current_thread_info(void)
96#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling 96#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
97 TIF_NEED_RESCHED */ 97 TIF_NEED_RESCHED */
98#define TIF_32BIT 5 /* 32 bit binary */ 98#define TIF_32BIT 5 /* 32 bit binary */
99#define TIF_RUN_LIGHT 6 /* iSeries run light */ 99/* #define SPARE 6 */
100#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */ 100#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */
101#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */ 101#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */
102#define TIF_SINGLESTEP 9 /* singlestepping active */ 102#define TIF_SINGLESTEP 9 /* singlestepping active */
@@ -110,7 +110,7 @@ static inline struct thread_info *current_thread_info(void)
110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 110#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 111#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
112#define _TIF_32BIT (1<<TIF_32BIT) 112#define _TIF_32BIT (1<<TIF_32BIT)
113#define _TIF_RUN_LIGHT (1<<TIF_RUN_LIGHT) 113/* #define _SPARE (1<<SPARE) */
114#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING) 114#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
115#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT) 115#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
116#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP) 116#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
diff --git a/include/asm-s390/user.h b/include/asm-s390/user.h
index c64f8c181df3..1dc74baf03c4 100644
--- a/include/asm-s390/user.h
+++ b/include/asm-s390/user.h
@@ -10,7 +10,7 @@
10#define _S390_USER_H 10#define _S390_USER_H
11 11
12#include <asm/page.h> 12#include <asm/page.h>
13#include <linux/ptrace.h> 13#include <asm/ptrace.h>
14/* Core file format: The core file is written in such a way that gdb 14/* Core file format: The core file is written in such a way that gdb
15 can understand it and provide useful information to the user (under 15 can understand it and provide useful information to the user (under
16 linux we use the 'trad-core' bfd). There are quite a number of 16 linux we use the 'trad-core' bfd). There are quite a number of
diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
index 5fd16e42a045..0de7a3da79cd 100644
--- a/include/asm-sparc64/iommu.h
+++ b/include/asm-sparc64/iommu.h
@@ -16,4 +16,6 @@
16#define IOPTE_CACHE 0x0000000000000010UL /* Cached (in UPA E-cache) */ 16#define IOPTE_CACHE 0x0000000000000010UL /* Cached (in UPA E-cache) */
17#define IOPTE_WRITE 0x0000000000000002UL /* Writeable */ 17#define IOPTE_WRITE 0x0000000000000002UL /* Writeable */
18 18
19#define IOMMU_NUM_CTXS 4096
20
19#endif /* !(_SPARC_IOMMU_H) */ 21#endif /* !(_SPARC_IOMMU_H) */
diff --git a/include/asm-sparc64/pbm.h b/include/asm-sparc64/pbm.h
index 92999631c819..4c15610a2bac 100644
--- a/include/asm-sparc64/pbm.h
+++ b/include/asm-sparc64/pbm.h
@@ -15,6 +15,7 @@
15#include <asm/io.h> 15#include <asm/io.h>
16#include <asm/page.h> 16#include <asm/page.h>
17#include <asm/oplib.h> 17#include <asm/oplib.h>
18#include <asm/iommu.h>
18 19
19/* The abstraction used here is that there are PCI controllers, 20/* The abstraction used here is that there are PCI controllers,
20 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules 21 * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
@@ -40,9 +41,6 @@ struct pci_iommu {
40 */ 41 */
41 spinlock_t lock; 42 spinlock_t lock;
42 43
43 /* Context allocator. */
44 unsigned int iommu_cur_ctx;
45
46 /* IOMMU page table, a linear array of ioptes. */ 44 /* IOMMU page table, a linear array of ioptes. */
47 iopte_t *page_table; /* The page table itself. */ 45 iopte_t *page_table; /* The page table itself. */
48 int page_table_sz_bits; /* log2 of ow many pages does it map? */ 46 int page_table_sz_bits; /* log2 of ow many pages does it map? */
@@ -87,6 +85,10 @@ struct pci_iommu {
87 u16 flush; 85 u16 flush;
88 } alloc_info[PBM_NCLUSTERS]; 86 } alloc_info[PBM_NCLUSTERS];
89 87
88 /* CTX allocation. */
89 unsigned long ctx_lowest_free;
90 unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
91
90 /* Here a PCI controller driver describes the areas of 92 /* Here a PCI controller driver describes the areas of
91 * PCI memory space where DMA to/from physical memory 93 * PCI memory space where DMA to/from physical memory
92 * are addressed. Drivers interrogate the PCI layer 94 * are addressed. Drivers interrogate the PCI layer
diff --git a/include/linux/if_shaper.h b/include/linux/if_shaper.h
index 0485b256d043..004e6f09a6e2 100644
--- a/include/linux/if_shaper.h
+++ b/include/linux/if_shaper.h
@@ -23,7 +23,7 @@ struct shaper
23 __u32 shapeclock; 23 __u32 shapeclock;
24 unsigned long recovery; /* Time we can next clock a packet out on 24 unsigned long recovery; /* Time we can next clock a packet out on
25 an empty queue */ 25 an empty queue */
26 unsigned long locked; 26 struct semaphore sem;
27 struct net_device_stats stats; 27 struct net_device_stats stats;
28 struct net_device *dev; 28 struct net_device *dev;
29 int (*hard_start_xmit) (struct sk_buff *skb, 29 int (*hard_start_xmit) (struct sk_buff *skb,
@@ -38,7 +38,6 @@ struct shaper
38 int (*hard_header_cache)(struct neighbour *neigh, struct hh_cache *hh); 38 int (*hard_header_cache)(struct neighbour *neigh, struct hh_cache *hh);
39 void (*header_cache_update)(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr); 39 void (*header_cache_update)(struct hh_cache *hh, struct net_device *dev, unsigned char * haddr);
40 struct net_device_stats* (*get_stats)(struct net_device *dev); 40 struct net_device_stats* (*get_stats)(struct net_device *dev);
41 wait_queue_head_t wait_queue;
42 struct timer_list timer; 41 struct timer_list timer;
43}; 42};
44 43
diff --git a/include/linux/libata.h b/include/linux/libata.h
index e74f301e9bae..b009f801e7c5 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -467,12 +467,34 @@ static inline u8 ata_chk_status(struct ata_port *ap)
467 return ap->ops->check_status(ap); 467 return ap->ops->check_status(ap);
468} 468}
469 469
470
471/**
472 * ata_pause - Flush writes and pause 400 nanoseconds.
473 * @ap: Port to wait for.
474 *
475 * LOCKING:
476 * Inherited from caller.
477 */
478
470static inline void ata_pause(struct ata_port *ap) 479static inline void ata_pause(struct ata_port *ap)
471{ 480{
472 ata_altstatus(ap); 481 ata_altstatus(ap);
473 ndelay(400); 482 ndelay(400);
474} 483}
475 484
485
486/**
487 * ata_busy_wait - Wait for a port status register
488 * @ap: Port to wait for.
489 *
490 * Waits up to max*10 microseconds for the selected bits in the port's
491 * status register to be cleared.
492 * Returns final value of status register.
493 *
494 * LOCKING:
495 * Inherited from caller.
496 */
497
476static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits, 498static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits,
477 unsigned int max) 499 unsigned int max)
478{ 500{
@@ -487,6 +509,18 @@ static inline u8 ata_busy_wait(struct ata_port *ap, unsigned int bits,
487 return status; 509 return status;
488} 510}
489 511
512
513/**
514 * ata_wait_idle - Wait for a port to be idle.
515 * @ap: Port to wait for.
516 *
517 * Waits up to 10ms for port's BUSY and DRQ signals to clear.
518 * Returns final value of status register.
519 *
520 * LOCKING:
521 * Inherited from caller.
522 */
523
490static inline u8 ata_wait_idle(struct ata_port *ap) 524static inline u8 ata_wait_idle(struct ata_port *ap)
491{ 525{
492 u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000); 526 u8 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
@@ -525,6 +559,18 @@ static inline void ata_tf_init(struct ata_port *ap, struct ata_taskfile *tf, uns
525 tf->device = ATA_DEVICE_OBS | ATA_DEV1; 559 tf->device = ATA_DEVICE_OBS | ATA_DEV1;
526} 560}
527 561
562
563/**
564 * ata_irq_on - Enable interrupts on a port.
565 * @ap: Port on which interrupts are enabled.
566 *
567 * Enable interrupts on a legacy IDE device using MMIO or PIO,
568 * wait for idle, clear any pending interrupts.
569 *
570 * LOCKING:
571 * Inherited from caller.
572 */
573
528static inline u8 ata_irq_on(struct ata_port *ap) 574static inline u8 ata_irq_on(struct ata_port *ap)
529{ 575{
530 struct ata_ioports *ioaddr = &ap->ioaddr; 576 struct ata_ioports *ioaddr = &ap->ioaddr;
@@ -544,6 +590,18 @@ static inline u8 ata_irq_on(struct ata_port *ap)
544 return tmp; 590 return tmp;
545} 591}
546 592
593
594/**
595 * ata_irq_ack - Acknowledge a device interrupt.
596 * @ap: Port on which interrupts are enabled.
597 *
598 * Wait up to 10 ms for legacy IDE device to become idle (BUSY
599 * or BUSY+DRQ clear). Obtain dma status and port status from
600 * device. Clear the interrupt. Return port status.
601 *
602 * LOCKING:
603 */
604
547static inline u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq) 605static inline u8 ata_irq_ack(struct ata_port *ap, unsigned int chk_drq)
548{ 606{
549 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY; 607 unsigned int bits = chk_drq ? ATA_BUSY | ATA_DRQ : ATA_BUSY;
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 470af8c1a4a0..ba5d1236aa17 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -204,7 +204,7 @@ struct hh_cache
204 /* cached hardware header; allow for machine alignment needs. */ 204 /* cached hardware header; allow for machine alignment needs. */
205#define HH_DATA_MOD 16 205#define HH_DATA_MOD 16
206#define HH_DATA_OFF(__len) \ 206#define HH_DATA_OFF(__len) \
207 (HH_DATA_MOD - ((__len) & (HH_DATA_MOD - 1))) 207 (HH_DATA_MOD - (((__len - 1) & (HH_DATA_MOD - 1)) + 1))
208#define HH_DATA_ALIGN(__len) \ 208#define HH_DATA_ALIGN(__len) \
209 (((__len)+(HH_DATA_MOD-1))&~(HH_DATA_MOD - 1)) 209 (((__len)+(HH_DATA_MOD-1))&~(HH_DATA_MOD - 1))
210 unsigned long hh_data[HH_DATA_ALIGN(LL_MAX_HEADER) / sizeof(long)]; 210 unsigned long hh_data[HH_DATA_ALIGN(LL_MAX_HEADER) / sizeof(long)];
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 7ccbc2e4272c..b0d6134e1ee6 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -1230,6 +1230,12 @@
1230#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258 1230#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL 0x0258
1231#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259 1231#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL 0x0259
1232#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B 1232#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL 0x025B
1233#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE 0x0265
1234#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA 0x0266
1235#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2 0x0267
1236#define PCI_DEVICE_ID_NVIDIA_NVENET_12 0x0268
1237#define PCI_DEVICE_ID_NVIDIA_NVENET_13 0x0269
1238#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO 0x026B
1233#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280 1239#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800 0x0280
1234#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281 1240#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X 0x0281
1235#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282 1241#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE 0x0282
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 41d1a644c9d4..2d1ac5058534 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -796,6 +796,10 @@ typedef void (*usb_complete_t)(struct urb *, struct pt_regs *);
796 * of the iso_frame_desc array, and the number of errors is reported in 796 * of the iso_frame_desc array, and the number of errors is reported in
797 * error_count. Completion callbacks for ISO transfers will normally 797 * error_count. Completion callbacks for ISO transfers will normally
798 * (re)submit URBs to ensure a constant transfer rate. 798 * (re)submit URBs to ensure a constant transfer rate.
799 *
800 * Note that even fields marked "public" should not be touched by the driver
801 * when the urb is owned by the hcd, that is, since the call to
802 * usb_submit_urb() till the entry into the completion routine.
799 */ 803 */
800struct urb 804struct urb
801{ 805{
@@ -803,12 +807,12 @@ struct urb
803 struct kref kref; /* reference count of the URB */ 807 struct kref kref; /* reference count of the URB */
804 spinlock_t lock; /* lock for the URB */ 808 spinlock_t lock; /* lock for the URB */
805 void *hcpriv; /* private data for host controller */ 809 void *hcpriv; /* private data for host controller */
806 struct list_head urb_list; /* list pointer to all active urbs */
807 int bandwidth; /* bandwidth for INT/ISO request */ 810 int bandwidth; /* bandwidth for INT/ISO request */
808 atomic_t use_count; /* concurrent submissions counter */ 811 atomic_t use_count; /* concurrent submissions counter */
809 u8 reject; /* submissions will fail */ 812 u8 reject; /* submissions will fail */
810 813
811 /* public, documented fields in the urb that can be used by drivers */ 814 /* public, documented fields in the urb that can be used by drivers */
815 struct list_head urb_list; /* list head for use by the urb owner */
812 struct usb_device *dev; /* (in) pointer to associated device */ 816 struct usb_device *dev; /* (in) pointer to associated device */
813 unsigned int pipe; /* (in) pipe information */ 817 unsigned int pipe; /* (in) pipe information */
814 int status; /* (return) non-ISO status */ 818 int status; /* (return) non-ISO status */