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authorYinghai Lu <Yinghai.Lu@Sun.COM>2008-02-25 00:36:28 -0500
committerIngo Molnar <mingo@elte.hu>2008-04-17 11:40:50 -0400
commitf8fffa458368ed3d57385698f775880db629bd1a (patch)
tree845bce35fea17284414d973a0fd0ea199d0947a6 /include
parent34048c9e927d5ae29c6ba802c826370de2a046d2 (diff)
x86: apic_is_clustered_box for vsmp
quad core 8 socket system will have apic id lifting.the apic id range could be [4, 0x23]. and apic_is_clustered_box will think that need to three clusters and that is larger than 2. So it is treated as a clustered_box. and will get: Marking TSC unstable due to TSCs unsynchronized even if the CPUs have X86_FEATURE_CONSTANT_TSC set. this quick fix will check if the cpu is from AMD. but vsmp still needs that checking... this patch is fix to make sure that vsmp not to be passed. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
-rw-r--r--include/asm-x86/apic.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
index bcfc07fd3661..f0321a427e16 100644
--- a/include/asm-x86/apic.h
+++ b/include/asm-x86/apic.h
@@ -51,12 +51,17 @@ extern unsigned boot_cpu_id;
51 */ 51 */
52#ifdef CONFIG_PARAVIRT 52#ifdef CONFIG_PARAVIRT
53#include <asm/paravirt.h> 53#include <asm/paravirt.h>
54extern int is_vsmp_box(void);
54#else 55#else
55#define apic_write native_apic_write 56#define apic_write native_apic_write
56#define apic_write_atomic native_apic_write_atomic 57#define apic_write_atomic native_apic_write_atomic
57#define apic_read native_apic_read 58#define apic_read native_apic_read
58#define setup_boot_clock setup_boot_APIC_clock 59#define setup_boot_clock setup_boot_APIC_clock
59#define setup_secondary_clock setup_secondary_APIC_clock 60#define setup_secondary_clock setup_secondary_APIC_clock
61static int inline is_vsmp_box(void)
62{
63 return 0;
64}
60#endif 65#endif
61 66
62static inline void native_apic_write(unsigned long reg, u32 v) 67static inline void native_apic_write(unsigned long reg, u32 v)