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authorAnand Gadiyar <adiyar@ti.com>2007-12-01 15:14:11 -0500
committerTony Lindgren <tony@atomide.com>2008-02-08 13:37:59 -0500
commitf8151e5c327bfc41f0993a45fb61ea121bebfee4 (patch)
tree78b7558e18a07eca2c477b7dfdb576392cd5c699 /include
parent5eb3bb9c0d123ad84ed5127fbc62731896d87181 (diff)
ARM: OMAP: Add DMA support for chaining and 3430
Add DMA support for chaining and 3430. Also remove old DEBUG_PRINTS as noted by Russell King. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-omap/dma.h135
1 files changed, 101 insertions, 34 deletions
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index f33b467fddb7..24acf090030d 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -45,22 +45,28 @@
45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
46 46
47/* Hardware registers for omap2 */ 47/* Hardware registers for omap2 */
48#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000) 48#if defined(CONFIG_ARCH_OMAP3)
49#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00) 49#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000)
50#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78) 50#else /* CONFIG_ARCH_OMAP2 */
51#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08) 51#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000)
52#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c) 52#endif
53#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10) 53
54#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14) 54#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00)
55#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18) 55#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78)
56#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c) 56#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08)
57#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20) 57#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c)
58#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24) 58#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10)
59#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28) 59#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14)
60#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64) 60#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18)
61#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c) 61#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c)
62#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70) 62#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20)
63#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74) 63#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24)
64#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28)
65#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c)
66#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64)
67#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c)
68#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70)
69#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74)
64 70
65#ifdef CONFIG_ARCH_OMAP1 71#ifdef CONFIG_ARCH_OMAP1
66 72
@@ -86,19 +92,19 @@
86#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ 92#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
87 93
88/* Common channel specific registers for omap2 */ 94/* Common channel specific registers for omap2 */
89#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80) 95#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
90#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84) 96#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
91#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88) 97#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
92#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c) 98#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
93#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90) 99#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
94#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94) 100#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
95#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98) 101#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
96#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4) 102#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
97#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8) 103#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
98#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac) 104#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
99#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0) 105#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
100#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4) 106#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
101#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8) 107#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
102 108
103#endif 109#endif
104 110
@@ -113,11 +119,11 @@
113#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 119#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
114 120
115/* Channel specific registers only on omap2 */ 121/* Channel specific registers only on omap2 */
116#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c) 122#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
117#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0) 123#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
118#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc) 124#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
119#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0) 125#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
120#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4) 126#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
121 127
122/*----------------------------------------------------------------------------*/ 128/*----------------------------------------------------------------------------*/
123 129
@@ -297,6 +303,10 @@
297#define OMAP_DMA_SYNC_ELEMENT 0x00 303#define OMAP_DMA_SYNC_ELEMENT 0x00
298#define OMAP_DMA_SYNC_FRAME 0x01 304#define OMAP_DMA_SYNC_FRAME 0x01
299#define OMAP_DMA_SYNC_BLOCK 0x02 305#define OMAP_DMA_SYNC_BLOCK 0x02
306#define OMAP_DMA_SYNC_PACKET 0x03
307
308#define OMAP_DMA_SRC_SYNC 0x01
309#define OMAP_DMA_DST_SYNC 0x00
300 310
301#define OMAP_DMA_PORT_EMIFF 0x00 311#define OMAP_DMA_PORT_EMIFF 0x00
302#define OMAP_DMA_PORT_EMIFS 0x01 312#define OMAP_DMA_PORT_EMIFS 0x01
@@ -310,6 +320,29 @@
310#define OMAP_DMA_AMODE_SINGLE_IDX 0x02 320#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
311#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03 321#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
312 322
323#define DMA_DEFAULT_FIFO_DEPTH 0x10
324#define DMA_DEFAULT_ARB_RATE 0x01
325/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
326#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
327#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
328#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
329#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
330#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
331#define DMA_THREAD_FIFO_75 (0x01 << 14)
332#define DMA_THREAD_FIFO_25 (0x02 << 14)
333#define DMA_THREAD_FIFO_50 (0x03 << 14)
334
335/* Chaining modes*/
336#ifndef CONFIG_ARCH_OMAP1
337#define OMAP_DMA_STATIC_CHAIN 0x1
338#define OMAP_DMA_DYNAMIC_CHAIN 0x2
339#define OMAP_DMA_CHAIN_ACTIVE 0x1
340#define OMAP_DMA_CHAIN_INACTIVE 0x0
341#endif
342
343#define DMA_CH_PRIO_HIGH 0x1
344#define DMA_CH_PRIO_LOW 0x0 /* Def */
345
313/* LCD DMA block numbers */ 346/* LCD DMA block numbers */
314enum { 347enum {
315 OMAP_LCD_DMA_B1_TOP, 348 OMAP_LCD_DMA_B1_TOP,
@@ -359,6 +392,13 @@ struct omap_dma_channel_params {
359 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 392 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
360 393
361 int ie; /* interrupt enabled */ 394 int ie; /* interrupt enabled */
395
396 unsigned char read_prio;/* read priority */
397 unsigned char write_prio;/* write priority */
398
399#ifndef CONFIG_ARCH_OMAP1
400 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
401#endif
362}; 402};
363 403
364 404
@@ -409,6 +449,33 @@ extern dma_addr_t omap_get_dma_dst_pos(int lch);
409extern int omap_get_dma_src_addr_counter(int lch); 449extern int omap_get_dma_src_addr_counter(int lch);
410extern void omap_clear_dma(int lch); 450extern void omap_clear_dma(int lch);
411extern int omap_dma_running(void); 451extern int omap_dma_running(void);
452extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
453 int tparams);
454extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
455 unsigned char write_prio);
456
457/* Chaining APIs */
458#ifndef CONFIG_ARCH_OMAP1
459extern int omap_request_dma_chain(int dev_id, const char *dev_name,
460 void (*callback) (int chain_id, u16 ch_status,
461 void *data),
462 int *chain_id, int no_of_chans,
463 int chain_mode,
464 struct omap_dma_channel_params params);
465extern int omap_free_dma_chain(int chain_id);
466extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
467 int dest_start, int elem_count,
468 int frame_count, void *callbk_data);
469extern int omap_start_dma_chain_transfers(int chain_id);
470extern int omap_stop_dma_chain_transfers(int chain_id);
471extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
472extern int omap_get_dma_chain_dst_pos(int chain_id);
473extern int omap_get_dma_chain_src_pos(int chain_id);
474
475extern int omap_modify_dma_chain_params(int chain_id,
476 struct omap_dma_channel_params params);
477extern int omap_dma_chain_status(int chain_id);
478#endif
412 479
413/* LCD DMA functions */ 480/* LCD DMA functions */
414extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 481extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),