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authorDan Williams <dan.j.williams@intel.com>2007-02-16 16:16:32 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-02-17 10:04:29 -0500
commitf80dff9da07d81da16e3b842118d47b9febf9c01 (patch)
treeea2da17c5af516c241b3ea3b4dd4fa47d9d86769 /include
parent588ef7693574cfbcb228f48d5478c2b39a9b0c9f (diff)
[ARM] 4185/2: entry: introduce get_irqnr_preamble and arch_ret_to_user
get_irqnr_preamble allows machines to take some action before entering the get_irqnr_and_base loop. On iop we enable cp6 access. arch_ret_to_user is added to the userspace return path to allow individual architectures to take actions, like disabling coprocessor access, before the final return to userspace. Per Nicolas Pitre's note, there is no need to cp_wait on the return to user as the latency to return is sufficient. Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-aaec2000/entry-macro.S6
-rw-r--r--include/asm-arm/arch-at91rm9200/entry-macro.S6
-rw-r--r--include/asm-arm/arch-cl7500/entry-macro.S5
-rw-r--r--include/asm-arm/arch-clps711x/entry-macro.S6
-rw-r--r--include/asm-arm/arch-ebsa110/entry-macro.S6
-rw-r--r--include/asm-arm/arch-ebsa285/entry-macro.S6
-rw-r--r--include/asm-arm/arch-ep93xx/entry-macro.S6
-rw-r--r--include/asm-arm/arch-h720x/entry-macro.S6
-rw-r--r--include/asm-arm/arch-imx/entry-macro.S7
-rw-r--r--include/asm-arm/arch-integrator/entry-macro.S6
-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S18
-rw-r--r--include/asm-arm/arch-iop32x/entry-macro.S33
-rw-r--r--include/asm-arm/arch-iop33x/entry-macro.S35
-rw-r--r--include/asm-arm/arch-ixp2000/entry-macro.S6
-rw-r--r--include/asm-arm/arch-ixp23xx/entry-macro.S6
-rw-r--r--include/asm-arm/arch-ixp4xx/entry-macro.S6
-rw-r--r--include/asm-arm/arch-l7200/entry-macro.S6
-rw-r--r--include/asm-arm/arch-lh7a40x/entry-macro.S6
-rw-r--r--include/asm-arm/arch-netx/entry-macro.S6
-rw-r--r--include/asm-arm/arch-omap/entry-macro.S6
-rw-r--r--include/asm-arm/arch-pnx4008/entry-macro.S6
-rw-r--r--include/asm-arm/arch-pxa/entry-macro.S6
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S6
-rw-r--r--include/asm-arm/arch-rpc/entry-macro.S5
-rw-r--r--include/asm-arm/arch-s3c2410/entry-macro.S6
-rw-r--r--include/asm-arm/arch-sa1100/entry-macro.S6
-rw-r--r--include/asm-arm/arch-shark/entry-macro.S6
-rw-r--r--include/asm-arm/arch-versatile/entry-macro.S6
28 files changed, 210 insertions, 25 deletions
diff --git a/include/asm-arm/arch-aaec2000/entry-macro.S b/include/asm-arm/arch-aaec2000/entry-macro.S
index 1eb3503bd16e..83fdf68f6b7c 100644
--- a/include/asm-arm/arch-aaec2000/entry-macro.S
+++ b/include/asm-arm/arch-aaec2000/entry-macro.S
@@ -15,6 +15,12 @@
15 .macro disable_fiq 15 .macro disable_fiq
16 .endm 16 .endm
17 17
18 .macro get_irqnr_preamble, base, tmp
19 .endm
20
21 .macro arch_ret_to_user, tmp1, tmp2
22 .endm
23
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 mov r4, #0xf8000000 25 mov r4, #0xf8000000
20 add r4, r4, #0x00000500 26 add r4, r4, #0x00000500
diff --git a/include/asm-arm/arch-at91rm9200/entry-macro.S b/include/asm-arm/arch-at91rm9200/entry-macro.S
index 57248a796472..0e0aadf2a175 100644
--- a/include/asm-arm/arch-at91rm9200/entry-macro.S
+++ b/include/asm-arm/arch-at91rm9200/entry-macro.S
@@ -16,6 +16,12 @@
16 .macro disable_fiq 16 .macro disable_fiq
17 .endm 17 .endm
18 18
19 .macro get_irqnr_preamble, base, tmp
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2
23 .endm
24
19 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
20 ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals 26 ldr \base, =(AT91_VA_BASE_SYS) @ base virtual address of SYS peripherals
21 ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) 27 ldr \irqnr, [\base, #AT91_AIC_IVR] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S
index c9e5395e5106..0cfb89b229d1 100644
--- a/include/asm-arm/arch-cl7500/entry-macro.S
+++ b/include/asm-arm/arch-cl7500/entry-macro.S
@@ -1,3 +1,8 @@
1#include <asm/hardware.h> 1#include <asm/hardware.h>
2#include <asm/hardware/entry-macro-iomd.S> 2#include <asm/hardware/entry-macro-iomd.S>
3 .macro get_irqnr_preamble, base, tmp
4 .endm
5
6 .macro arch_ret_to_user, tmp1, tmp2
7 .endm
3 8
diff --git a/include/asm-arm/arch-clps711x/entry-macro.S b/include/asm-arm/arch-clps711x/entry-macro.S
index de4481dd8ba0..cd8c5a0bc7bc 100644
--- a/include/asm-arm/arch-clps711x/entry-macro.S
+++ b/include/asm-arm/arch-clps711x/entry-macro.S
@@ -13,6 +13,12 @@
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1) 22#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
17#error INTSR stride != INTMR stride 23#error INTSR stride != INTMR stride
18#endif 24#endif
diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S
index b12ca04f998c..aa23c5d6c69e 100644
--- a/include/asm-arm/arch-ebsa110/entry-macro.S
+++ b/include/asm-arm/arch-ebsa110/entry-macro.S
@@ -15,6 +15,12 @@
15 .macro disable_fiq 15 .macro disable_fiq
16 .endm 16 .endm
17 17
18 .macro get_irqnr_preamble, base, tmp
19 .endm
20
21 .macro arch_ret_to_user, tmp1, tmp2
22 .endm
23
18 .macro get_irqnr_and_base, irqnr, stat, base, tmp 24 .macro get_irqnr_and_base, irqnr, stat, base, tmp
19 mov \base, #IRQ_STAT 25 mov \base, #IRQ_STAT
20 ldrb \stat, [\base] @ get interrupts 26 ldrb \stat, [\base] @ get interrupts
diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S
index ce812d4f4a33..4203dbf10662 100644
--- a/include/asm-arm/arch-ebsa285/entry-macro.S
+++ b/include/asm-arm/arch-ebsa285/entry-macro.S
@@ -14,6 +14,12 @@
14 .macro disable_fiq 14 .macro disable_fiq
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
17 .equ dc21285_high, ARMCSR_BASE & 0xff000000 23 .equ dc21285_high, ARMCSR_BASE & 0xff000000
18 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff 24 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
19 25
diff --git a/include/asm-arm/arch-ep93xx/entry-macro.S b/include/asm-arm/arch-ep93xx/entry-macro.S
index 84140a28dfcf..241ec221a047 100644
--- a/include/asm-arm/arch-ep93xx/entry-macro.S
+++ b/include/asm-arm/arch-ep93xx/entry-macro.S
@@ -14,6 +14,12 @@
14 .macro disable_fiq 14 .macro disable_fiq
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
17 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
18 ldr \base, =(EP93XX_AHB_VIRT_BASE) 24 ldr \base, =(EP93XX_AHB_VIRT_BASE)
19 orr \base, \base, #0x000b0000 25 orr \base, \base, #0x000b0000
diff --git a/include/asm-arm/arch-h720x/entry-macro.S b/include/asm-arm/arch-h720x/entry-macro.S
index 8f165648e2af..38dd63ae104e 100644
--- a/include/asm-arm/arch-h720x/entry-macro.S
+++ b/include/asm-arm/arch-h720x/entry-macro.S
@@ -11,6 +11,12 @@
11 .macro disable_fiq 11 .macro disable_fiq
12 .endm 12 .endm
13 13
14 .macro get_irqnr_preamble, base, tmp
15 .endm
16
17 .macro arch_ret_to_user, tmp1, tmp2
18 .endm
19
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 20 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202) 21#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
16 @ we could use the id register on H7202, but this is not 22 @ we could use the id register on H7202, but this is not
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
index 3b9ef6914627..d8cbafa6cc49 100644
--- a/include/asm-arm/arch-imx/entry-macro.S
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@ -11,6 +11,13 @@
11 11
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
14#define AITC_NIVECSR 0x40 21#define AITC_NIVECSR 0x40
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE) 23 ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S
index 69838d04f90b..491af1a23de5 100644
--- a/include/asm-arm/arch-integrator/entry-macro.S
+++ b/include/asm-arm/arch-integrator/entry-macro.S
@@ -13,6 +13,12 @@
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
17/* FIXME: should not be using soo many LDRs here */ 23/* FIXME: should not be using soo many LDRs here */
18 ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE) 24 ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
index 94c50283dc56..a624a7870c64 100644
--- a/include/asm-arm/arch-iop13xx/entry-macro.S
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -19,21 +19,27 @@
19 .macro disable_fiq 19 .macro disable_fiq
20 .endm 20 .endm
21 21
22 .macro get_irqnr_preamble, base, tmp
23 mrc p15, 0, \tmp, c15, c1, 0
24 orr \tmp, \tmp, #(1 << 6)
25 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
26 .endm
27
22 /* 28 /*
23 * Note: a 1-cycle window exists where iintvec will return the value 29 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros" 30 * of iintbase, so we explicitly check for "bad zeros"
25 */ 31 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 32 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC 33 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0 34 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero 35 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff 36 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr 37 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
38 .endm
36 39
37 biceq \tmp, \tmp, #(1 << 6) 40 .macro arch_ret_to_user, tmp1, tmp2
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts 41 mrc p15, 0, \tmp1, c15, c1, 0
42 ands \tmp2, \tmp1, #(1 << 6)
43 bicne \tmp1, \tmp1, #(1 << 6)
44 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
39 .endm 45 .endm
diff --git a/include/asm-arm/arch-iop32x/entry-macro.S b/include/asm-arm/arch-iop32x/entry-macro.S
index 1500cbbd2295..207db99dfbd2 100644
--- a/include/asm-arm/arch-iop32x/entry-macro.S
+++ b/include/asm-arm/arch-iop32x/entry-macro.S
@@ -9,13 +9,28 @@
9 */ 9 */
10#include <asm/arch/iop32x.h> 10#include <asm/arch/iop32x.h>
11 11
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 15 .macro get_irqnr_preamble, base, tmp
16 ldr \base, =IOP3XX_REG_ADDR(0x07D8) 16 mrc p15, 0, \tmp, c15, c1, 0
17 ldr \irqstat, [\base] @ Read IINTSRC 17 orr \tmp, \tmp, #(1 << 6)
18 cmp \irqstat, #0 18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
19 clzne \irqnr, \irqstat 19 mrc p15, 0, \tmp, c15, c1, 0
20 rsbne \irqnr, \irqnr, #31 20 mov \tmp, \tmp
21 .endm 21 sub pc, pc, #4 @ cp_wait
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
26 cmp \irqstat, #0
27 clzne \irqnr, \irqstat
28 rsbne \irqnr, \irqnr, #31
29 .endm
30
31 .macro arch_ret_to_user, tmp1, tmp2
32 mrc p15, 0, \tmp1, c15, c1, 0
33 ands \tmp2, \tmp1, #(1 << 6)
34 bicne \tmp1, \tmp1, #(1 << 6)
35 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
36 .endm
diff --git a/include/asm-arm/arch-iop33x/entry-macro.S b/include/asm-arm/arch-iop33x/entry-macro.S
index 92b791702e34..b8e3d449e882 100644
--- a/include/asm-arm/arch-iop33x/entry-macro.S
+++ b/include/asm-arm/arch-iop33x/entry-macro.S
@@ -9,14 +9,29 @@
9 */ 9 */
10#include <asm/arch/iop33x.h> 10#include <asm/arch/iop33x.h>
11 11
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 15 .macro get_irqnr_preamble, base, tmp
16 ldr \base, =IOP3XX_REG_ADDR(0x07C8) 16 mrc p15, 0, \tmp, c15, c1, 0
17 ldr \irqstat, [\base] @ Read IINTVEC 17 orr \tmp, \tmp, #(1 << 6)
18 cmp \irqstat, #0 18 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
19 ldreq \irqstat, [\base] @ erratum 63 workaround 19 mrc p15, 0, \tmp, c15, c1, 0
20 adds \irqnr, \irqstat, #1 20 mov \tmp, \tmp
21 movne \irqnr, \irqstat, lsr #2 21 sub pc, pc, #4 @ cp_wait
22 .endm 22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 mrc p6, 0, \irqstat, c14, c0, 0 @ Read IINTVEC
26 cmp \irqstat, #0
27 mrceq p6, 0, \irqstat, c14, c0, 0 @ erratum 63 workaround
28 adds \irqnr, \irqstat, #1
29 movne \irqnr, \irqstat, lsr #2
30 .endm
31
32 .macro arch_ret_to_user, tmp1, tmp2
33 mrc p15, 0, \tmp1, c15, c1, 0
34 ands \tmp2, \tmp1, #(1 << 6)
35 bicne \tmp1, \tmp1, #(1 << 6)
36 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
37 .endm
diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S
index 16e1e6124b31..11d512ad5945 100644
--- a/include/asm-arm/arch-ixp2000/entry-macro.S
+++ b/include/asm-arm/arch-ixp2000/entry-macro.S
@@ -12,6 +12,12 @@
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 22
17 mov \irqnr, #0x0 @clear out irqnr as default 23 mov \irqnr, #0x0 @clear out irqnr as default
diff --git a/include/asm-arm/arch-ixp23xx/entry-macro.S b/include/asm-arm/arch-ixp23xx/entry-macro.S
index 867761677b57..ec9dd6fc2d0f 100644
--- a/include/asm-arm/arch-ixp23xx/entry-macro.S
+++ b/include/asm-arm/arch-ixp23xx/entry-macro.S
@@ -5,6 +5,12 @@
5 .macro disable_fiq 5 .macro disable_fiq
6 .endm 6 .endm
7 7
8 .macro get_irqnr_preamble, base, tmp
9 .endm
10
11 .macro arch_ret_to_user, tmp1, tmp2
12 .endm
13
8 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
9 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET) 15 ldr \irqnr, =(IXP23XX_INTC_VIRT + IXP23XX_INTR_IRQ_ENC_ST_OFFSET)
10 ldr \irqnr, [\irqnr] @ get interrupt number 16 ldr \irqnr, [\irqnr] @ get interrupt number
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
index 27e124132e4c..dadb568b7ef0 100644
--- a/include/asm-arm/arch-ixp4xx/entry-macro.S
+++ b/include/asm-arm/arch-ixp4xx/entry-macro.S
@@ -12,6 +12,12 @@
12 .macro disable_fiq 12 .macro disable_fiq
13 .endm 13 .endm
14 14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro arch_ret_to_user, tmp1, tmp2
19 .endm
20
15 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 21 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
16 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) 22 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
17 ldr \irqstat, [\irqstat] @ get interrupts 23 ldr \irqstat, [\irqstat] @ get interrupts
diff --git a/include/asm-arm/arch-l7200/entry-macro.S b/include/asm-arm/arch-l7200/entry-macro.S
index 8b6342dc4be2..63411d3e9df4 100644
--- a/include/asm-arm/arch-l7200/entry-macro.S
+++ b/include/asm-arm/arch-l7200/entry-macro.S
@@ -14,6 +14,12 @@
14 .macro disable_fiq 14 .macro disable_fiq
15 .endm 15 .endm
16 16
17 .macro get_irqnr_preamble, base, tmp
18 .endm
19
20 .macro arch_ret_to_user, tmp1, tmp2
21 .endm
22
17 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
18 mov \irqstat, #irq_base_addr @ Virt addr IRQ regs 24 mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
19 add \irqstat, \irqstat, #0x00001000 @ Status reg 25 add \irqstat, \irqstat, #0x00001000 @ Status reg
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
index 9fc7f4988124..502700604e00 100644
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -26,6 +26,12 @@
26 .macro disable_fiq 26 .macro disable_fiq
27 .endm 27 .endm
28 28
29 .macro get_irqnr_preamble, base, tmp
30 .endm
31
32 .macro arch_ret_to_user, tmp1, tmp2
33 .endm
34
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 35 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30 36
31branch_irq_lh7a400: b 1000f 37branch_irq_lh7a400: b 1000f
diff --git a/include/asm-arm/arch-netx/entry-macro.S b/include/asm-arm/arch-netx/entry-macro.S
index 658df4d60ff3..83ad188a0847 100644
--- a/include/asm-arm/arch-netx/entry-macro.S
+++ b/include/asm-arm/arch-netx/entry-macro.S
@@ -23,6 +23,12 @@
23 .macro disable_fiq 23 .macro disable_fiq
24 .endm 24 .endm
25 25
26 .macro get_irqnr_preamble, base, tmp
27 .endm
28
29 .macro arch_ret_to_user, tmp1, tmp2
30 .endm
31
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 32 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mov \base, #io_p2v(0x00100000) 33 mov \base, #io_p2v(0x00100000)
28 add \base, \base, #0x000ff000 34 add \base, \base, #0x000ff000
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
index 0ffb1185f1ac..c90dff4828f7 100644
--- a/include/asm-arm/arch-omap/entry-macro.S
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -29,6 +29,12 @@
29 .macro disable_fiq 29 .macro disable_fiq
30 .endm 30 .endm
31 31
32 .macro get_irqnr_preamble, base, tmp
33 .endm
34
35 .macro arch_ret_to_user, tmp1, tmp2
36 .endm
37
32 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 38 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
33 ldr \base, =IO_ADDRESS(OMAP_IH1_BASE) 39 ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
34 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET] 40 ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S
index c1c198e3680b..f11731974e5d 100644
--- a/include/asm-arm/arch-pnx4008/entry-macro.S
+++ b/include/asm-arm/arch-pnx4008/entry-macro.S
@@ -28,6 +28,12 @@
28 .macro disable_fiq 28 .macro disable_fiq
29 .endm 29 .endm
30 30
31 .macro get_irqnr_preamble, base, tmp
32 .endm
33
34 .macro arch_ret_to_user, tmp1, tmp2
35 .endm
36
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 37 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32/* decode the MIC interrupt numbers */ 38/* decode the MIC interrupt numbers */
33 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE) 39 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
index 4985e33afc12..1d5fbb9b379a 100644
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ b/include/asm-arm/arch-pxa/entry-macro.S
@@ -13,6 +13,12 @@
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
17#ifdef CONFIG_PXA27x 23#ifdef CONFIG_PXA27x
18 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP 24 mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 1a6eec86bd47..138838d4ad75 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -13,6 +13,12 @@
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16 /* 22 /*
17 * The interrupt numbering scheme is defined in the 23 * The interrupt numbering scheme is defined in the
18 * interrupt controller spec. To wit: 24 * interrupt controller spec. To wit:
diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S
index c9e5395e5106..0cfb89b229d1 100644
--- a/include/asm-arm/arch-rpc/entry-macro.S
+++ b/include/asm-arm/arch-rpc/entry-macro.S
@@ -1,3 +1,8 @@
1#include <asm/hardware.h> 1#include <asm/hardware.h>
2#include <asm/hardware/entry-macro-iomd.S> 2#include <asm/hardware/entry-macro-iomd.S>
3 .macro get_irqnr_preamble, base, tmp
4 .endm
5
6 .macro arch_ret_to_user, tmp1, tmp2
7 .endm
3 8
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
index 1eb4e6b8d249..bbec0a8ff158 100644
--- a/include/asm-arm/arch-s3c2410/entry-macro.S
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -22,6 +22,12 @@
22#include <asm/hardware.h> 22#include <asm/hardware.h>
23#include <asm/irq.h> 23#include <asm/irq.h>
24 24
25 .macro get_irqnr_preamble, base, tmp
26 .endm
27
28 .macro arch_ret_to_user, tmp1, tmp2
29 .endm
30
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26 32
27 mov \base, #S3C24XX_VA_IRQ 33 mov \base, #S3C24XX_VA_IRQ
diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S
index 51fb50ce1169..028967629340 100644
--- a/include/asm-arm/arch-sa1100/entry-macro.S
+++ b/include/asm-arm/arch-sa1100/entry-macro.S
@@ -11,6 +11,12 @@
11 .macro disable_fiq 11 .macro disable_fiq
12 .endm 12 .endm
13 13
14 .macro get_irqnr_preamble, base, tmp
15 .endm
16
17 .macro arch_ret_to_user, tmp1, tmp2
18 .endm
19
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 20 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15 mov r4, #0xfa000000 @ ICIP = 0xfa050000 21 mov r4, #0xfa000000 @ ICIP = 0xfa050000
16 add r4, r4, #0x00050000 22 add r4, r4, #0x00050000
diff --git a/include/asm-arm/arch-shark/entry-macro.S b/include/asm-arm/arch-shark/entry-macro.S
index a924f27fb8d9..82463f30f3df 100644
--- a/include/asm-arm/arch-shark/entry-macro.S
+++ b/include/asm-arm/arch-shark/entry-macro.S
@@ -10,6 +10,12 @@
10 .macro disable_fiq 10 .macro disable_fiq
11 .endm 11 .endm
12 12
13 .macro get_irqnr_preamble, base, tmp
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
13 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 19 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
14 mov r4, #0xe0000000 20 mov r4, #0xe0000000
15 21
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S
index feff771c0a0a..0fae002637a0 100644
--- a/include/asm-arm/arch-versatile/entry-macro.S
+++ b/include/asm-arm/arch-versatile/entry-macro.S
@@ -13,6 +13,12 @@
13 .macro disable_fiq 13 .macro disable_fiq
14 .endm 14 .endm
15 15
16 .macro get_irqnr_preamble, base, tmp
17 .endm
18
19 .macro arch_ret_to_user, tmp1, tmp2
20 .endm
21
16 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
17 ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) 23 ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
18 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status 24 ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status