diff options
author | John Bowler <jbowler@acm.org> | 2005-11-02 06:55:12 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-11-02 06:55:12 -0500 |
commit | bfca94590bfd3dcd958c542d2fb6406518150fee (patch) | |
tree | 00e947e6abd3ec64ac025112121440160a783cf3 /include | |
parent | 9dc2d0f55fb693ae6d50c8dd3d934fe3133ca183 (diff) |
[ARM] 3083/1: include/asm-arm/arch-ixp4xx/io.h: eliminate warnings for pointer passed to integral function argument
Patch from John Bowler
Fix for a compiler warning, this wasn't apparent in 2.6.12, I
believe the compiler options have been changed (somewhere) so
that passing a (void*) to a (u32) argument is now warned.
This accounts for the majority of the warnings in my builds of
the 2.6.14 kernel for NSLU2.
The patch changes pointer parameters declared as u32 to be
declared as either, for read parameters:
const volatile void __iomem *
and for write parameters:
volatile void __iomem *
Signed-off-by: John Bowler <jbowler@acm.org>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-arm/arch-ixp4xx/io.h | 74 |
1 files changed, 40 insertions, 34 deletions
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h index 80d05ecad2f0..688f7f90d93e 100644 --- a/include/asm-arm/arch-ixp4xx/io.h +++ b/include/asm-arm/arch-ixp4xx/io.h | |||
@@ -80,9 +80,9 @@ __ixp4xx_iounmap(void __iomem *addr) | |||
80 | #define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x) | 80 | #define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x) |
81 | #define __arch_iounmap(a) __ixp4xx_iounmap(a) | 81 | #define __arch_iounmap(a) __ixp4xx_iounmap(a) |
82 | 82 | ||
83 | #define writeb(p, v) __ixp4xx_writeb(p, v) | 83 | #define writeb(v, p) __ixp4xx_writeb(v, p) |
84 | #define writew(p, v) __ixp4xx_writew(p, v) | 84 | #define writew(v, p) __ixp4xx_writew(v, p) |
85 | #define writel(p, v) __ixp4xx_writel(p, v) | 85 | #define writel(v, p) __ixp4xx_writel(v, p) |
86 | 86 | ||
87 | #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) | 87 | #define writesb(p, v, l) __ixp4xx_writesb(p, v, l) |
88 | #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) | 88 | #define writesw(p, v, l) __ixp4xx_writesw(p, v, l) |
@@ -97,8 +97,9 @@ __ixp4xx_iounmap(void __iomem *addr) | |||
97 | #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) | 97 | #define readsl(p, v, l) __ixp4xx_readsl(p, v, l) |
98 | 98 | ||
99 | static inline void | 99 | static inline void |
100 | __ixp4xx_writeb(u8 value, u32 addr) | 100 | __ixp4xx_writeb(u8 value, volatile void __iomem *p) |
101 | { | 101 | { |
102 | u32 addr = (u32)p; | ||
102 | u32 n, byte_enables, data; | 103 | u32 n, byte_enables, data; |
103 | 104 | ||
104 | if (addr >= VMALLOC_START) { | 105 | if (addr >= VMALLOC_START) { |
@@ -113,15 +114,16 @@ __ixp4xx_writeb(u8 value, u32 addr) | |||
113 | } | 114 | } |
114 | 115 | ||
115 | static inline void | 116 | static inline void |
116 | __ixp4xx_writesb(u32 bus_addr, const u8 *vaddr, int count) | 117 | __ixp4xx_writesb(volatile void __iomem *bus_addr, const u8 *vaddr, int count) |
117 | { | 118 | { |
118 | while (count--) | 119 | while (count--) |
119 | writeb(*vaddr++, bus_addr); | 120 | writeb(*vaddr++, bus_addr); |
120 | } | 121 | } |
121 | 122 | ||
122 | static inline void | 123 | static inline void |
123 | __ixp4xx_writew(u16 value, u32 addr) | 124 | __ixp4xx_writew(u16 value, volatile void __iomem *p) |
124 | { | 125 | { |
126 | u32 addr = (u32)p; | ||
125 | u32 n, byte_enables, data; | 127 | u32 n, byte_enables, data; |
126 | 128 | ||
127 | if (addr >= VMALLOC_START) { | 129 | if (addr >= VMALLOC_START) { |
@@ -136,15 +138,16 @@ __ixp4xx_writew(u16 value, u32 addr) | |||
136 | } | 138 | } |
137 | 139 | ||
138 | static inline void | 140 | static inline void |
139 | __ixp4xx_writesw(u32 bus_addr, const u16 *vaddr, int count) | 141 | __ixp4xx_writesw(volatile void __iomem *bus_addr, const u16 *vaddr, int count) |
140 | { | 142 | { |
141 | while (count--) | 143 | while (count--) |
142 | writew(*vaddr++, bus_addr); | 144 | writew(*vaddr++, bus_addr); |
143 | } | 145 | } |
144 | 146 | ||
145 | static inline void | 147 | static inline void |
146 | __ixp4xx_writel(u32 value, u32 addr) | 148 | __ixp4xx_writel(u32 value, volatile void __iomem *p) |
147 | { | 149 | { |
150 | u32 addr = (u32)p; | ||
148 | if (addr >= VMALLOC_START) { | 151 | if (addr >= VMALLOC_START) { |
149 | __raw_writel(value, addr); | 152 | __raw_writel(value, addr); |
150 | return; | 153 | return; |
@@ -154,15 +157,16 @@ __ixp4xx_writel(u32 value, u32 addr) | |||
154 | } | 157 | } |
155 | 158 | ||
156 | static inline void | 159 | static inline void |
157 | __ixp4xx_writesl(u32 bus_addr, const u32 *vaddr, int count) | 160 | __ixp4xx_writesl(volatile void __iomem *bus_addr, const u32 *vaddr, int count) |
158 | { | 161 | { |
159 | while (count--) | 162 | while (count--) |
160 | writel(*vaddr++, bus_addr); | 163 | writel(*vaddr++, bus_addr); |
161 | } | 164 | } |
162 | 165 | ||
163 | static inline unsigned char | 166 | static inline unsigned char |
164 | __ixp4xx_readb(u32 addr) | 167 | __ixp4xx_readb(const volatile void __iomem *p) |
165 | { | 168 | { |
169 | u32 addr = (u32)p; | ||
166 | u32 n, byte_enables, data; | 170 | u32 n, byte_enables, data; |
167 | 171 | ||
168 | if (addr >= VMALLOC_START) | 172 | if (addr >= VMALLOC_START) |
@@ -177,15 +181,16 @@ __ixp4xx_readb(u32 addr) | |||
177 | } | 181 | } |
178 | 182 | ||
179 | static inline void | 183 | static inline void |
180 | __ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count) | 184 | __ixp4xx_readsb(const volatile void __iomem *bus_addr, u8 *vaddr, u32 count) |
181 | { | 185 | { |
182 | while (count--) | 186 | while (count--) |
183 | *vaddr++ = readb(bus_addr); | 187 | *vaddr++ = readb(bus_addr); |
184 | } | 188 | } |
185 | 189 | ||
186 | static inline unsigned short | 190 | static inline unsigned short |
187 | __ixp4xx_readw(u32 addr) | 191 | __ixp4xx_readw(const volatile void __iomem *p) |
188 | { | 192 | { |
193 | u32 addr = (u32)p; | ||
189 | u32 n, byte_enables, data; | 194 | u32 n, byte_enables, data; |
190 | 195 | ||
191 | if (addr >= VMALLOC_START) | 196 | if (addr >= VMALLOC_START) |
@@ -200,15 +205,16 @@ __ixp4xx_readw(u32 addr) | |||
200 | } | 205 | } |
201 | 206 | ||
202 | static inline void | 207 | static inline void |
203 | __ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count) | 208 | __ixp4xx_readsw(const volatile void __iomem *bus_addr, u16 *vaddr, u32 count) |
204 | { | 209 | { |
205 | while (count--) | 210 | while (count--) |
206 | *vaddr++ = readw(bus_addr); | 211 | *vaddr++ = readw(bus_addr); |
207 | } | 212 | } |
208 | 213 | ||
209 | static inline unsigned long | 214 | static inline unsigned long |
210 | __ixp4xx_readl(u32 addr) | 215 | __ixp4xx_readl(const volatile void __iomem *p) |
211 | { | 216 | { |
217 | u32 addr = (u32)p; | ||
212 | u32 data; | 218 | u32 data; |
213 | 219 | ||
214 | if (addr >= VMALLOC_START) | 220 | if (addr >= VMALLOC_START) |
@@ -221,7 +227,7 @@ __ixp4xx_readl(u32 addr) | |||
221 | } | 227 | } |
222 | 228 | ||
223 | static inline void | 229 | static inline void |
224 | __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) | 230 | __ixp4xx_readsl(const volatile void __iomem *bus_addr, u32 *vaddr, u32 count) |
225 | { | 231 | { |
226 | while (count--) | 232 | while (count--) |
227 | *vaddr++ = readl(bus_addr); | 233 | *vaddr++ = readl(bus_addr); |
@@ -239,7 +245,7 @@ __ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count) | |||
239 | eth_copy_and_sum((s),__mem_pci(c),(l),(b)) | 245 | eth_copy_and_sum((s),__mem_pci(c),(l),(b)) |
240 | 246 | ||
241 | static inline int | 247 | static inline int |
242 | check_signature(unsigned long bus_addr, const unsigned char *signature, | 248 | check_signature(const unsigned char __iomem *bus_addr, const unsigned char *signature, |
243 | int length) | 249 | int length) |
244 | { | 250 | { |
245 | int retval = 0; | 251 | int retval = 0; |
@@ -389,7 +395,7 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count) | |||
389 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ | 395 | #define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \ |
390 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) | 396 | ((unsigned long)p <= (PIO_MASK + PIO_OFFSET))) |
391 | static inline unsigned int | 397 | static inline unsigned int |
392 | __ixp4xx_ioread8(void __iomem *addr) | 398 | __ixp4xx_ioread8(const void __iomem *addr) |
393 | { | 399 | { |
394 | unsigned long port = (unsigned long __force)addr; | 400 | unsigned long port = (unsigned long __force)addr; |
395 | if (__is_io_address(port)) | 401 | if (__is_io_address(port)) |
@@ -398,12 +404,12 @@ __ixp4xx_ioread8(void __iomem *addr) | |||
398 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 404 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
399 | return (unsigned int)__raw_readb(port); | 405 | return (unsigned int)__raw_readb(port); |
400 | #else | 406 | #else |
401 | return (unsigned int)__ixp4xx_readb(port); | 407 | return (unsigned int)__ixp4xx_readb(addr); |
402 | #endif | 408 | #endif |
403 | } | 409 | } |
404 | 410 | ||
405 | static inline void | 411 | static inline void |
406 | __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) | 412 | __ixp4xx_ioread8_rep(const void __iomem *addr, void *vaddr, u32 count) |
407 | { | 413 | { |
408 | unsigned long port = (unsigned long __force)addr; | 414 | unsigned long port = (unsigned long __force)addr; |
409 | if (__is_io_address(port)) | 415 | if (__is_io_address(port)) |
@@ -412,12 +418,12 @@ __ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count) | |||
412 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 418 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
413 | __raw_readsb(addr, vaddr, count); | 419 | __raw_readsb(addr, vaddr, count); |
414 | #else | 420 | #else |
415 | __ixp4xx_readsb(port, vaddr, count); | 421 | __ixp4xx_readsb(addr, vaddr, count); |
416 | #endif | 422 | #endif |
417 | } | 423 | } |
418 | 424 | ||
419 | static inline unsigned int | 425 | static inline unsigned int |
420 | __ixp4xx_ioread16(void __iomem *addr) | 426 | __ixp4xx_ioread16(const void __iomem *addr) |
421 | { | 427 | { |
422 | unsigned long port = (unsigned long __force)addr; | 428 | unsigned long port = (unsigned long __force)addr; |
423 | if (__is_io_address(port)) | 429 | if (__is_io_address(port)) |
@@ -426,12 +432,12 @@ __ixp4xx_ioread16(void __iomem *addr) | |||
426 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 432 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
427 | return le16_to_cpu(__raw_readw((u32)port)); | 433 | return le16_to_cpu(__raw_readw((u32)port)); |
428 | #else | 434 | #else |
429 | return (unsigned int)__ixp4xx_readw((u32)port); | 435 | return (unsigned int)__ixp4xx_readw(addr); |
430 | #endif | 436 | #endif |
431 | } | 437 | } |
432 | 438 | ||
433 | static inline void | 439 | static inline void |
434 | __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) | 440 | __ixp4xx_ioread16_rep(const void __iomem *addr, void *vaddr, u32 count) |
435 | { | 441 | { |
436 | unsigned long port = (unsigned long __force)addr; | 442 | unsigned long port = (unsigned long __force)addr; |
437 | if (__is_io_address(port)) | 443 | if (__is_io_address(port)) |
@@ -440,12 +446,12 @@ __ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count) | |||
440 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 446 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
441 | __raw_readsw(addr, vaddr, count); | 447 | __raw_readsw(addr, vaddr, count); |
442 | #else | 448 | #else |
443 | __ixp4xx_readsw(port, vaddr, count); | 449 | __ixp4xx_readsw(addr, vaddr, count); |
444 | #endif | 450 | #endif |
445 | } | 451 | } |
446 | 452 | ||
447 | static inline unsigned int | 453 | static inline unsigned int |
448 | __ixp4xx_ioread32(void __iomem *addr) | 454 | __ixp4xx_ioread32(const void __iomem *addr) |
449 | { | 455 | { |
450 | unsigned long port = (unsigned long __force)addr; | 456 | unsigned long port = (unsigned long __force)addr; |
451 | if (__is_io_address(port)) | 457 | if (__is_io_address(port)) |
@@ -454,13 +460,13 @@ __ixp4xx_ioread32(void __iomem *addr) | |||
454 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 460 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
455 | return le32_to_cpu(__raw_readl((u32)port)); | 461 | return le32_to_cpu(__raw_readl((u32)port)); |
456 | #else | 462 | #else |
457 | return (unsigned int)__ixp4xx_readl((u32)port); | 463 | return (unsigned int)__ixp4xx_readl(addr); |
458 | #endif | 464 | #endif |
459 | } | 465 | } |
460 | } | 466 | } |
461 | 467 | ||
462 | static inline void | 468 | static inline void |
463 | __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) | 469 | __ixp4xx_ioread32_rep(const void __iomem *addr, void *vaddr, u32 count) |
464 | { | 470 | { |
465 | unsigned long port = (unsigned long __force)addr; | 471 | unsigned long port = (unsigned long __force)addr; |
466 | if (__is_io_address(port)) | 472 | if (__is_io_address(port)) |
@@ -469,7 +475,7 @@ __ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count) | |||
469 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 475 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
470 | __raw_readsl(addr, vaddr, count); | 476 | __raw_readsl(addr, vaddr, count); |
471 | #else | 477 | #else |
472 | __ixp4xx_readsl(port, vaddr, count); | 478 | __ixp4xx_readsl(addr, vaddr, count); |
473 | #endif | 479 | #endif |
474 | } | 480 | } |
475 | 481 | ||
@@ -483,7 +489,7 @@ __ixp4xx_iowrite8(u8 value, void __iomem *addr) | |||
483 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 489 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
484 | __raw_writeb(value, port); | 490 | __raw_writeb(value, port); |
485 | #else | 491 | #else |
486 | __ixp4xx_writeb(value, port); | 492 | __ixp4xx_writeb(value, addr); |
487 | #endif | 493 | #endif |
488 | } | 494 | } |
489 | 495 | ||
@@ -497,7 +503,7 @@ __ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count) | |||
497 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 503 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
498 | __raw_writesb(addr, vaddr, count); | 504 | __raw_writesb(addr, vaddr, count); |
499 | #else | 505 | #else |
500 | __ixp4xx_writesb(port, vaddr, count); | 506 | __ixp4xx_writesb(addr, vaddr, count); |
501 | #endif | 507 | #endif |
502 | } | 508 | } |
503 | 509 | ||
@@ -511,7 +517,7 @@ __ixp4xx_iowrite16(u16 value, void __iomem *addr) | |||
511 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 517 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
512 | __raw_writew(cpu_to_le16(value), addr); | 518 | __raw_writew(cpu_to_le16(value), addr); |
513 | #else | 519 | #else |
514 | __ixp4xx_writew(value, port); | 520 | __ixp4xx_writew(value, addr); |
515 | #endif | 521 | #endif |
516 | } | 522 | } |
517 | 523 | ||
@@ -525,7 +531,7 @@ __ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count) | |||
525 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 531 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
526 | __raw_writesw(addr, vaddr, count); | 532 | __raw_writesw(addr, vaddr, count); |
527 | #else | 533 | #else |
528 | __ixp4xx_writesw(port, vaddr, count); | 534 | __ixp4xx_writesw(addr, vaddr, count); |
529 | #endif | 535 | #endif |
530 | } | 536 | } |
531 | 537 | ||
@@ -539,7 +545,7 @@ __ixp4xx_iowrite32(u32 value, void __iomem *addr) | |||
539 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 545 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
540 | __raw_writel(cpu_to_le32(value), port); | 546 | __raw_writel(cpu_to_le32(value), port); |
541 | #else | 547 | #else |
542 | __ixp4xx_writel(value, port); | 548 | __ixp4xx_writel(value, addr); |
543 | #endif | 549 | #endif |
544 | } | 550 | } |
545 | 551 | ||
@@ -553,7 +559,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count) | |||
553 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI | 559 | #ifndef CONFIG_IXP4XX_INDIRECT_PCI |
554 | __raw_writesl(addr, vaddr, count); | 560 | __raw_writesl(addr, vaddr, count); |
555 | #else | 561 | #else |
556 | __ixp4xx_writesl(port, vaddr, count); | 562 | __ixp4xx_writesl(addr, vaddr, count); |
557 | #endif | 563 | #endif |
558 | } | 564 | } |
559 | 565 | ||