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authorMichael Chan <mchan@broadcom.com>2005-05-26 16:03:09 -0400
committerDavid S. Miller <davem@davemloft.net>2005-05-26 16:03:09 -0400
commitb6016b767397258b58163494a869f8f1199e6897 (patch)
treecd0bc87ff25ceaa1dd55860c9f212e18bb5a9f08 /include
parentc8b35d2a29ec3c93e3b9c1e70d649a77a214b1c1 (diff)
[BNX2]: New Broadcom gigabit network driver.
A new driver bnx2 for Broadcom bcm5706 is available. The patch also includes new 1000BASE-X advertisement bit definitions in mii.h Thanks to David Miller and Jeff Garzik for reviewing and their valuable feedback. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mii.h8
-rw-r--r--include/linux/pci_ids.h2
2 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/mii.h b/include/linux/mii.h
index 20971fe78a8d..374b615ea9ea 100644
--- a/include/linux/mii.h
+++ b/include/linux/mii.h
@@ -65,9 +65,13 @@
65#define ADVERTISE_SLCT 0x001f /* Selector bits */ 65#define ADVERTISE_SLCT 0x001f /* Selector bits */
66#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ 66#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
67#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ 67#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
68#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
68#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ 69#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
70#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
69#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ 71#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
72#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
70#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ 73#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
74#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
71#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ 75#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
72#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ 76#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
73#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ 77#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
@@ -84,9 +88,13 @@
84/* Link partner ability register. */ 88/* Link partner ability register. */
85#define LPA_SLCT 0x001f /* Same as advertise selector */ 89#define LPA_SLCT 0x001f /* Same as advertise selector */
86#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 90#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
91#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
87#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 92#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
93#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
88#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 94#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
95#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
89#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 96#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
97#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
90#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ 98#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
91#define LPA_PAUSE_CAP 0x0400 /* Can pause */ 99#define LPA_PAUSE_CAP 0x0400 /* Can pause */
92#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ 100#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 7b9720e35361..7ccbc2e4272c 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2071,6 +2071,7 @@
2071#define PCI_DEVICE_ID_TIGON3_5703 0x1647 2071#define PCI_DEVICE_ID_TIGON3_5703 0x1647
2072#define PCI_DEVICE_ID_TIGON3_5704 0x1648 2072#define PCI_DEVICE_ID_TIGON3_5704 0x1648
2073#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649 2073#define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
2074#define PCI_DEVICE_ID_NX2_5706 0x164a
2074#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d 2075#define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
2075#define PCI_DEVICE_ID_TIGON3_5705 0x1653 2076#define PCI_DEVICE_ID_TIGON3_5705 0x1653
2076#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654 2077#define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
@@ -2090,6 +2091,7 @@
2090#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6 2091#define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
2091#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7 2092#define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
2092#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8 2093#define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
2094#define PCI_DEVICE_ID_NX2_5706S 0x16aa
2093#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6 2095#define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
2094#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7 2096#define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
2095#define PCI_DEVICE_ID_TIGON3_5781 0x16dd 2097#define PCI_DEVICE_ID_TIGON3_5781 0x16dd