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authorRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:05 -0400
committerRalf Baechle <ralf@linux-mips.org>2007-10-11 18:46:05 -0400
commit641e97f318870921d048154af6807e46e43c307a (patch)
tree6e0984a1bc8932db848be3fdb104a92c97fe341a /include
parent424b28ba4d25fc41abdb7e6fa90e132f0d9558fb (diff)
[MIPS] Sibyte: Replace SB1 cachecode with standard R4000 class cache code.
It may not be perfect yet but the SB1 code is badly borken and has horrible performance issues. Downside: This seriously breaks support for pass 1 parts of the BCM1250 where indexed cacheops don't work quite reliable but I seem to be the last one on the planet with a pass 1 part anyway. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/cpu-features.h3
-rw-r--r--include/asm-mips/cpu.h35
-rw-r--r--include/asm-mips/linkage.h2
-rw-r--r--include/asm-mips/mach-cobalt/cpu-feature-overrides.h1
4 files changed, 19 insertions, 22 deletions
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
index d95a83e3e1d7..81f19aebc0db 100644
--- a/include/asm-mips/cpu-features.h
+++ b/include/asm-mips/cpu-features.h
@@ -35,9 +35,6 @@
35#ifndef cpu_has_tx39_cache 35#ifndef cpu_has_tx39_cache
36#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 36#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
37#endif 37#endif
38#ifndef cpu_has_sb1_cache
39#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
40#endif
41#ifndef cpu_has_fpu 38#ifndef cpu_has_fpu
42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 39#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 40#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index d67f43b09964..107ccbeee294 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -255,24 +255,23 @@
255#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */ 255#define MIPS_CPU_3K_CACHE 0x00000004 /* R3000-style caches */
256#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */ 256#define MIPS_CPU_4K_CACHE 0x00000008 /* R4000-style caches */
257#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */ 257#define MIPS_CPU_TX39_CACHE 0x00000010 /* TX3900-style caches */
258#define MIPS_CPU_SB1_CACHE 0x00000020 /* SB1-style caches */ 258#define MIPS_CPU_FPU 0x00000020 /* CPU has FPU */
259#define MIPS_CPU_FPU 0x00000040 /* CPU has FPU */ 259#define MIPS_CPU_32FPR 0x00000040 /* 32 dbl. prec. FP registers */
260#define MIPS_CPU_32FPR 0x00000080 /* 32 dbl. prec. FP registers */ 260#define MIPS_CPU_COUNTER 0x00000080 /* Cycle count/compare */
261#define MIPS_CPU_COUNTER 0x00000100 /* Cycle count/compare */ 261#define MIPS_CPU_WATCH 0x00000100 /* watchpoint registers */
262#define MIPS_CPU_WATCH 0x00000200 /* watchpoint registers */ 262#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
263#define MIPS_CPU_DIVEC 0x00000400 /* dedicated interrupt vector */ 263#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
264#define MIPS_CPU_VCE 0x00000800 /* virt. coherence conflict possible */ 264#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
265#define MIPS_CPU_CACHE_CDEX_P 0x00001000 /* Create_Dirty_Exclusive CACHE op */ 265#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
266#define MIPS_CPU_CACHE_CDEX_S 0x00002000 /* ... same for seconary cache ... */ 266#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
267#define MIPS_CPU_MCHECK 0x00004000 /* Machine check exception */ 267#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
268#define MIPS_CPU_EJTAG 0x00008000 /* EJTAG exception */ 268#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
269#define MIPS_CPU_NOFPUEX 0x00010000 /* no FPU exception */ 269#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
270#define MIPS_CPU_LLSC 0x00020000 /* CPU has ll/sc instructions */ 270#define MIPS_CPU_INCLUSIVE_CACHES 0x00020000 /* P-cache subset enforced */
271#define MIPS_CPU_INCLUSIVE_CACHES 0x00040000 /* P-cache subset enforced */ 271#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
272#define MIPS_CPU_PREFETCH 0x00080000 /* CPU has usable prefetch */ 272#define MIPS_CPU_VINT 0x00080000 /* CPU supports MIPSR2 vectored interrupts */
273#define MIPS_CPU_VINT 0x00100000 /* CPU supports MIPSR2 vectored interrupts */ 273#define MIPS_CPU_VEIC 0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
274#define MIPS_CPU_VEIC 0x00200000 /* CPU supports MIPSR2 external interrupt controller mode */ 274#define MIPS_CPU_ULRI 0x00200000 /* CPU has ULRI feature */
275#define MIPS_CPU_ULRI 0x00400000 /* CPU has ULRI feature */
276 275
277/* 276/*
278 * CPU ASE encodings 277 * CPU ASE encodings
diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h
index b6185d3cfe68..e9a940d1b0c6 100644
--- a/include/asm-mips/linkage.h
+++ b/include/asm-mips/linkage.h
@@ -5,4 +5,6 @@
5#include <asm/asm.h> 5#include <asm/asm.h>
6#endif 6#endif
7 7
8#define __weak __attribute__((weak))
9
8#endif 10#endif
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
index d38f069d9e95..b3314cf53194 100644
--- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
+++ b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
@@ -14,7 +14,6 @@
14#define cpu_has_3k_cache 0 14#define cpu_has_3k_cache 0
15#define cpu_has_4k_cache 1 15#define cpu_has_4k_cache 1
16#define cpu_has_tx39_cache 0 16#define cpu_has_tx39_cache 0
17#define cpu_has_sb1_cache 0
18#define cpu_has_fpu 1 17#define cpu_has_fpu 1
19#define cpu_has_32fpr 1 18#define cpu_has_32fpr 1
20#define cpu_has_counter 1 19#define cpu_has_counter 1