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authorPaul Mackerras <paulus@samba.org>2007-08-28 01:56:11 -0400
committerPaul Mackerras <paulus@samba.org>2007-08-28 01:56:11 -0400
commit35438c4327df18dbf5e7f597b69299119f4a14de (patch)
treea4589d731015db93f2eba8f84ffb1f48a8084020 /include
parent2f6c9d961081dc7b109eb19166244bcb2a5dfc28 (diff)
parentb07d68b5ca4d55a16fab223d63d5fb36f89ff42f (diff)
Merge branch 'linux-2.6' into for-2.6.24
Diffstat (limited to 'include')
-rw-r--r--include/acpi/acpi_bus.h10
-rw-r--r--include/acpi/acpixf.h2
-rw-r--r--include/acpi/acstruct.h2
-rw-r--r--include/asm-avr32/io.h2
-rw-r--r--include/asm-avr32/pgalloc.h30
-rw-r--r--include/asm-avr32/pgtable.h4
-rw-r--r--include/asm-i386/io.h3
-rw-r--r--include/asm-i386/io_apic.h1
-rw-r--r--include/asm-i386/mach-default/mach_wakecpu.h3
-rw-r--r--include/asm-i386/mach-es7000/mach_wakecpu.h3
-rw-r--r--include/asm-i386/nmi.h3
-rw-r--r--include/asm-ia64/atomic.h4
-rw-r--r--include/asm-ia64/hw_irq.h7
-rw-r--r--include/asm-ia64/machvec.h7
-rw-r--r--include/asm-ia64/machvec_init.h1
-rw-r--r--include/asm-ia64/machvec_sn2.h2
-rw-r--r--include/asm-m68k/ioctls.h4
-rw-r--r--include/asm-m68k/page.h10
-rw-r--r--include/asm-m68k/processor.h4
-rw-r--r--include/asm-m68k/termbits.h5
-rw-r--r--include/asm-m68k/termios.h6
-rw-r--r--include/asm-m68knommu/pgtable.h2
-rw-r--r--include/asm-mips/bcache.h1
-rw-r--r--include/asm-mips/edac.h17
-rw-r--r--include/asm-mips/gt64240.h1235
-rw-r--r--include/asm-mips/jmr3927/jmr3927.h3
-rw-r--r--include/asm-mips/jmr3927/tx3927.h36
-rw-r--r--include/asm-mips/mach-generic/ide.h76
-rw-r--r--include/asm-mips/marvell.h59
-rw-r--r--include/asm-mips/pgtable-32.h16
-rw-r--r--include/asm-mips/pgtable.h12
-rw-r--r--include/asm-mips/smtc.h10
-rw-r--r--include/asm-mips/stacktrace.h6
-rw-r--r--include/asm-mips/tx4927/toshiba_rbtx4927.h2
-rw-r--r--include/asm-mips/tx4927/tx4927.h49
-rw-r--r--include/asm-mips/tx4927/tx4927_pci.h23
-rw-r--r--include/asm-mips/tx4938/rbtx4938.h25
-rw-r--r--include/asm-mips/tx4938/tx4938.h41
-rw-r--r--include/asm-mips/txx9irq.h30
-rw-r--r--include/asm-parisc/io.h10
-rw-r--r--include/asm-parisc/vga.h6
-rw-r--r--include/asm-powerpc/reg_booke.h12
-rw-r--r--include/asm-s390/atomic.h26
-rw-r--r--include/asm-s390/cio.h15
-rw-r--r--include/asm-s390/diag.h39
-rw-r--r--include/asm-s390/pgalloc.h2
-rw-r--r--include/asm-sh/dma-mapping.h19
-rw-r--r--include/asm-sh64/dma-mapping.h18
-rw-r--r--include/asm-sparc/sbus.h1
-rw-r--r--include/asm-sparc/sfp-machine.h6
-rw-r--r--include/asm-sparc/tlbflush.h6
-rw-r--r--include/asm-sparc64/elf.h10
-rw-r--r--include/asm-sparc64/percpu.h4
-rw-r--r--include/asm-sparc64/sfp-machine.h2
-rw-r--r--include/asm-sparc64/system.h26
-rw-r--r--include/asm-x86_64/io_apic.h6
-rw-r--r--include/asm-x86_64/nmi.h3
-rw-r--r--include/linux/Kbuild1
-rw-r--r--include/linux/audit.h4
-rw-r--r--include/linux/ide.h4
-rw-r--r--include/linux/if_pppol2tp.h4
-rw-r--r--include/linux/input.h6
-rw-r--r--include/linux/kbd_kern.h3
-rw-r--r--include/linux/mempolicy.h2
-rw-r--r--include/linux/mm.h2
-rw-r--r--include/linux/mmzone.h18
-rw-r--r--include/linux/mod_devicetable.h3
-rw-r--r--include/linux/pci.h4
-rw-r--r--include/linux/pci_ids.h10
-rw-r--r--include/linux/pmu.h2
-rw-r--r--include/linux/sched.h8
-rw-r--r--include/linux/security.h20
-rw-r--r--include/linux/selection.h2
-rw-r--r--include/linux/serial_reg.h1
-rw-r--r--include/linux/videodev2.h2
-rw-r--r--include/math-emu/op-common.h5
-rw-r--r--include/math-emu/soft-fp.h7
-rw-r--r--include/rdma/ib_mad.h2
-rw-r--r--include/rdma/ib_verbs.h7
79 files changed, 422 insertions, 1662 deletions
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index 3d0fea235bf3..86aea44ce6d4 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -321,8 +321,7 @@ struct acpi_bus_event {
321}; 321};
322 322
323extern struct kset acpi_subsys; 323extern struct kset acpi_subsys;
324extern int acpi_bus_generate_genetlink_event(struct acpi_device *device, 324extern int acpi_bus_generate_netlink_event(const char*, const char*, u8, int);
325 u8 type, int data);
326/* 325/*
327 * External Functions 326 * External Functions
328 */ 327 */
@@ -332,8 +331,13 @@ void acpi_bus_data_handler(acpi_handle handle, u32 function, void *context);
332int acpi_bus_get_status(struct acpi_device *device); 331int acpi_bus_get_status(struct acpi_device *device);
333int acpi_bus_get_power(acpi_handle handle, int *state); 332int acpi_bus_get_power(acpi_handle handle, int *state);
334int acpi_bus_set_power(acpi_handle handle, int state); 333int acpi_bus_set_power(acpi_handle handle, int state);
335int acpi_bus_generate_event(struct acpi_device *device, u8 type, int data); 334#ifdef CONFIG_ACPI_PROC_EVENT
335int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data);
336int acpi_bus_receive_event(struct acpi_bus_event *event); 336int acpi_bus_receive_event(struct acpi_bus_event *event);
337#else
338static inline int acpi_bus_generate_proc_event(struct acpi_device *device, u8 type, int data)
339 { return 0; }
340#endif
337int acpi_bus_register_driver(struct acpi_driver *driver); 341int acpi_bus_register_driver(struct acpi_driver *driver);
338void acpi_bus_unregister_driver(struct acpi_driver *driver); 342void acpi_bus_unregister_driver(struct acpi_driver *driver);
339int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent, 343int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent,
diff --git a/include/acpi/acpixf.h b/include/acpi/acpixf.h
index b5cca5daa348..3d7ab9e0c9fe 100644
--- a/include/acpi/acpixf.h
+++ b/include/acpi/acpixf.h
@@ -130,7 +130,7 @@ acpi_walk_namespace(acpi_object_type type,
130 void *context, void **return_value); 130 void *context, void **return_value);
131 131
132acpi_status 132acpi_status
133acpi_get_devices(char *HID, 133acpi_get_devices(const char *HID,
134 acpi_walk_callback user_function, 134 acpi_walk_callback user_function,
135 void *context, void **return_value); 135 void *context, void **return_value);
136 136
diff --git a/include/acpi/acstruct.h b/include/acpi/acstruct.h
index aeb4498e5e06..88482655407f 100644
--- a/include/acpi/acstruct.h
+++ b/include/acpi/acstruct.h
@@ -146,7 +146,7 @@ struct acpi_init_walk_info {
146struct acpi_get_devices_info { 146struct acpi_get_devices_info {
147 acpi_walk_callback user_function; 147 acpi_walk_callback user_function;
148 void *context; 148 void *context;
149 char *hid; 149 const char *hid;
150}; 150};
151 151
152union acpi_aml_operands { 152union acpi_aml_operands {
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index e30d4b3bd836..64bb92bb6773 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -255,6 +255,8 @@ static inline void memset_io(volatile void __iomem *addr, unsigned char val,
255 memset((void __force *)addr, val, count); 255 memset((void __force *)addr, val, count);
256} 256}
257 257
258#define mmiowb()
259
258#define IO_SPACE_LIMIT 0xffffffff 260#define IO_SPACE_LIMIT 0xffffffff
259 261
260extern void __iomem *__ioremap(unsigned long offset, size_t size, 262extern void __iomem *__ioremap(unsigned long offset, size_t size,
diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h
index bb82e70cde8d..0e680f47209f 100644
--- a/include/asm-avr32/pgalloc.h
+++ b/include/asm-avr32/pgalloc.h
@@ -27,13 +27,7 @@ static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
27 */ 27 */
28static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm) 28static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm)
29{ 29{
30 unsigned int pgd_size = (USER_PTRS_PER_PGD * sizeof(pgd_t)); 30 return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL);
31 pgd_t *pgd = kmalloc(pgd_size, GFP_KERNEL);
32
33 if (pgd)
34 memset(pgd, 0, pgd_size);
35
36 return pgd;
37} 31}
38 32
39static inline void pgd_free(pgd_t *pgd) 33static inline void pgd_free(pgd_t *pgd)
@@ -44,18 +38,9 @@ static inline void pgd_free(pgd_t *pgd)
44static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 38static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
45 unsigned long address) 39 unsigned long address)
46{ 40{
47 int count = 0;
48 pte_t *pte; 41 pte_t *pte;
49 42
50 do { 43 pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
51 pte = (pte_t *) __get_free_page(GFP_KERNEL | __GFP_REPEAT);
52 if (pte)
53 clear_page(pte);
54 else {
55 current->state = TASK_UNINTERRUPTIBLE;
56 schedule_timeout(HZ);
57 }
58 } while (!pte && (count++ < 10));
59 44
60 return pte; 45 return pte;
61} 46}
@@ -63,18 +48,9 @@ static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
63static inline struct page *pte_alloc_one(struct mm_struct *mm, 48static inline struct page *pte_alloc_one(struct mm_struct *mm,
64 unsigned long address) 49 unsigned long address)
65{ 50{
66 int count = 0;
67 struct page *pte; 51 struct page *pte;
68 52
69 do { 53 pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO);
70 pte = alloc_pages(GFP_KERNEL, 0);
71 if (pte)
72 clear_page(page_address(pte));
73 else {
74 current->state = TASK_UNINTERRUPTIBLE;
75 schedule_timeout(HZ);
76 }
77 } while (!pte && (count++ < 10));
78 54
79 return pte; 55 return pte;
80} 56}
diff --git a/include/asm-avr32/pgtable.h b/include/asm-avr32/pgtable.h
index c07bdd10b891..018f6e2a0242 100644
--- a/include/asm-avr32/pgtable.h
+++ b/include/asm-avr32/pgtable.h
@@ -32,8 +32,6 @@
32#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) 32#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
33#define FIRST_USER_ADDRESS 0 33#define FIRST_USER_ADDRESS 0
34 34
35#define PTE_PHYS_MASK 0x1ffff000
36
37#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
38extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 36extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
39extern void paging_init(void); 37extern void paging_init(void);
@@ -265,7 +263,7 @@ static inline pte_t pte_mkyoung(pte_t pte)
265 * trivial. 263 * trivial.
266 */ 264 */
267#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) 265#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
268#define pte_page(x) phys_to_page(pte_val(x) & PTE_PHYS_MASK) 266#define pte_page(x) (pfn_to_page(pte_pfn(x)))
269 267
270/* 268/*
271 * Mark the prot value as uncacheable and unbufferable 269 * Mark the prot value as uncacheable and unbufferable
diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h
index 7b65b5b00034..e8e0bd641120 100644
--- a/include/asm-i386/io.h
+++ b/include/asm-i386/io.h
@@ -112,6 +112,9 @@ extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsign
112 * writew/writel functions and the other mmio helpers. The returned 112 * writew/writel functions and the other mmio helpers. The returned
113 * address is not guaranteed to be usable directly as a virtual 113 * address is not guaranteed to be usable directly as a virtual
114 * address. 114 * address.
115 *
116 * If the area you are trying to map is a PCI BAR you should have a
117 * look at pci_iomap().
115 */ 118 */
116 119
117static inline void __iomem * ioremap(unsigned long offset, unsigned long size) 120static inline void __iomem * ioremap(unsigned long offset, unsigned long size)
diff --git a/include/asm-i386/io_apic.h b/include/asm-i386/io_apic.h
index 340764076d5f..dbe734ddf2af 100644
--- a/include/asm-i386/io_apic.h
+++ b/include/asm-i386/io_apic.h
@@ -150,7 +150,6 @@ extern int (*ioapic_renumber_irq)(int ioapic, int irq);
150 150
151#else /* !CONFIG_X86_IO_APIC */ 151#else /* !CONFIG_X86_IO_APIC */
152#define io_apic_assign_pci_irqs 0 152#define io_apic_assign_pci_irqs 0
153static inline void disable_ioapic_setup(void) { }
154#endif 153#endif
155 154
156#endif 155#endif
diff --git a/include/asm-i386/mach-default/mach_wakecpu.h b/include/asm-i386/mach-default/mach_wakecpu.h
index 673b85c9b273..3ebb17893aa5 100644
--- a/include/asm-i386/mach-default/mach_wakecpu.h
+++ b/include/asm-i386/mach-default/mach_wakecpu.h
@@ -15,7 +15,8 @@
15 15
16static inline void wait_for_init_deassert(atomic_t *deassert) 16static inline void wait_for_init_deassert(atomic_t *deassert)
17{ 17{
18 while (!atomic_read(deassert)); 18 while (!atomic_read(deassert))
19 cpu_relax();
19 return; 20 return;
20} 21}
21 22
diff --git a/include/asm-i386/mach-es7000/mach_wakecpu.h b/include/asm-i386/mach-es7000/mach_wakecpu.h
index efc903b73486..84ff58314501 100644
--- a/include/asm-i386/mach-es7000/mach_wakecpu.h
+++ b/include/asm-i386/mach-es7000/mach_wakecpu.h
@@ -31,7 +31,8 @@ wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip)
31static inline void wait_for_init_deassert(atomic_t *deassert) 31static inline void wait_for_init_deassert(atomic_t *deassert)
32{ 32{
33#ifdef WAKE_SECONDARY_VIA_INIT 33#ifdef WAKE_SECONDARY_VIA_INIT
34 while (!atomic_read(deassert)); 34 while (!atomic_read(deassert))
35 cpu_relax();
35#endif 36#endif
36 return; 37 return;
37} 38}
diff --git a/include/asm-i386/nmi.h b/include/asm-i386/nmi.h
index ff30c98f87b0..70a958a8e381 100644
--- a/include/asm-i386/nmi.h
+++ b/include/asm-i386/nmi.h
@@ -33,11 +33,12 @@ extern int nmi_watchdog_tick (struct pt_regs * regs, unsigned reason);
33 33
34extern atomic_t nmi_active; 34extern atomic_t nmi_active;
35extern unsigned int nmi_watchdog; 35extern unsigned int nmi_watchdog;
36#define NMI_DEFAULT -1 36#define NMI_DISABLED -1
37#define NMI_NONE 0 37#define NMI_NONE 0
38#define NMI_IO_APIC 1 38#define NMI_IO_APIC 1
39#define NMI_LOCAL_APIC 2 39#define NMI_LOCAL_APIC 2
40#define NMI_INVALID 3 40#define NMI_INVALID 3
41#define NMI_DEFAULT NMI_DISABLED
41 42
42struct ctl_table; 43struct ctl_table;
43struct file; 44struct file;
diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h
index 1fc3b83325da..50c2b83fd5a0 100644
--- a/include/asm-ia64/atomic.h
+++ b/include/asm-ia64/atomic.h
@@ -55,7 +55,7 @@ ia64_atomic64_add (__s64 i, atomic64_t *v)
55 55
56 do { 56 do {
57 CMPXCHG_BUGCHECK(v); 57 CMPXCHG_BUGCHECK(v);
58 old = atomic_read(v); 58 old = atomic64_read(v);
59 new = old + i; 59 new = old + i;
60 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); 60 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
61 return new; 61 return new;
@@ -83,7 +83,7 @@ ia64_atomic64_sub (__s64 i, atomic64_t *v)
83 83
84 do { 84 do {
85 CMPXCHG_BUGCHECK(v); 85 CMPXCHG_BUGCHECK(v);
86 old = atomic_read(v); 86 old = atomic64_read(v);
87 new = old - i; 87 new = old - i;
88 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old); 88 } while (ia64_cmpxchg(acq, v, old, new, sizeof(atomic64_t)) != old);
89 return new; 89 return new;
diff --git a/include/asm-ia64/hw_irq.h b/include/asm-ia64/hw_irq.h
index efa1b8f7251d..bba5baa3c7fc 100644
--- a/include/asm-ia64/hw_irq.h
+++ b/include/asm-ia64/hw_irq.h
@@ -124,6 +124,11 @@ static inline void ia64_resend_irq(unsigned int vector)
124extern irq_desc_t irq_desc[NR_IRQS]; 124extern irq_desc_t irq_desc[NR_IRQS];
125 125
126#ifndef CONFIG_IA64_GENERIC 126#ifndef CONFIG_IA64_GENERIC
127static inline ia64_vector __ia64_irq_to_vector(int irq)
128{
129 return irq_cfg[irq].vector;
130}
131
127static inline unsigned int 132static inline unsigned int
128__ia64_local_vector_to_irq (ia64_vector vec) 133__ia64_local_vector_to_irq (ia64_vector vec)
129{ 134{
@@ -145,7 +150,7 @@ __ia64_local_vector_to_irq (ia64_vector vec)
145static inline ia64_vector 150static inline ia64_vector
146irq_to_vector (int irq) 151irq_to_vector (int irq)
147{ 152{
148 return irq_cfg[irq].vector; 153 return platform_irq_to_vector(irq);
149} 154}
150 155
151/* 156/*
diff --git a/include/asm-ia64/machvec.h b/include/asm-ia64/machvec.h
index 5cf8bf1e805e..c201a2020aa4 100644
--- a/include/asm-ia64/machvec.h
+++ b/include/asm-ia64/machvec.h
@@ -30,6 +30,7 @@ typedef void ia64_mv_send_ipi_t (int, int, int, int);
30typedef void ia64_mv_timer_interrupt_t (int, void *); 30typedef void ia64_mv_timer_interrupt_t (int, void *);
31typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long); 31typedef void ia64_mv_global_tlb_purge_t (struct mm_struct *, unsigned long, unsigned long, unsigned long);
32typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *); 32typedef void ia64_mv_tlb_migrate_finish_t (struct mm_struct *);
33typedef u8 ia64_mv_irq_to_vector (int);
33typedef unsigned int ia64_mv_local_vector_to_irq (u8); 34typedef unsigned int ia64_mv_local_vector_to_irq (u8);
34typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *); 35typedef char *ia64_mv_pci_get_legacy_mem_t (struct pci_bus *);
35typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val, 36typedef int ia64_mv_pci_legacy_read_t (struct pci_bus *, u16 port, u32 *val,
@@ -145,6 +146,7 @@ extern void machvec_tlb_migrate_finish (struct mm_struct *);
145# define platform_dma_sync_sg_for_device ia64_mv.dma_sync_sg_for_device 146# define platform_dma_sync_sg_for_device ia64_mv.dma_sync_sg_for_device
146# define platform_dma_mapping_error ia64_mv.dma_mapping_error 147# define platform_dma_mapping_error ia64_mv.dma_mapping_error
147# define platform_dma_supported ia64_mv.dma_supported 148# define platform_dma_supported ia64_mv.dma_supported
149# define platform_irq_to_vector ia64_mv.irq_to_vector
148# define platform_local_vector_to_irq ia64_mv.local_vector_to_irq 150# define platform_local_vector_to_irq ia64_mv.local_vector_to_irq
149# define platform_pci_get_legacy_mem ia64_mv.pci_get_legacy_mem 151# define platform_pci_get_legacy_mem ia64_mv.pci_get_legacy_mem
150# define platform_pci_legacy_read ia64_mv.pci_legacy_read 152# define platform_pci_legacy_read ia64_mv.pci_legacy_read
@@ -198,6 +200,7 @@ struct ia64_machine_vector {
198 ia64_mv_dma_sync_sg_for_device *dma_sync_sg_for_device; 200 ia64_mv_dma_sync_sg_for_device *dma_sync_sg_for_device;
199 ia64_mv_dma_mapping_error *dma_mapping_error; 201 ia64_mv_dma_mapping_error *dma_mapping_error;
200 ia64_mv_dma_supported *dma_supported; 202 ia64_mv_dma_supported *dma_supported;
203 ia64_mv_irq_to_vector *irq_to_vector;
201 ia64_mv_local_vector_to_irq *local_vector_to_irq; 204 ia64_mv_local_vector_to_irq *local_vector_to_irq;
202 ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem; 205 ia64_mv_pci_get_legacy_mem_t *pci_get_legacy_mem;
203 ia64_mv_pci_legacy_read_t *pci_legacy_read; 206 ia64_mv_pci_legacy_read_t *pci_legacy_read;
@@ -247,6 +250,7 @@ struct ia64_machine_vector {
247 platform_dma_sync_sg_for_device, \ 250 platform_dma_sync_sg_for_device, \
248 platform_dma_mapping_error, \ 251 platform_dma_mapping_error, \
249 platform_dma_supported, \ 252 platform_dma_supported, \
253 platform_irq_to_vector, \
250 platform_local_vector_to_irq, \ 254 platform_local_vector_to_irq, \
251 platform_pci_get_legacy_mem, \ 255 platform_pci_get_legacy_mem, \
252 platform_pci_legacy_read, \ 256 platform_pci_legacy_read, \
@@ -366,6 +370,9 @@ extern ia64_mv_dma_supported swiotlb_dma_supported;
366#ifndef platform_dma_supported 370#ifndef platform_dma_supported
367# define platform_dma_supported swiotlb_dma_supported 371# define platform_dma_supported swiotlb_dma_supported
368#endif 372#endif
373#ifndef platform_irq_to_vector
374# define platform_irq_to_vector __ia64_irq_to_vector
375#endif
369#ifndef platform_local_vector_to_irq 376#ifndef platform_local_vector_to_irq
370# define platform_local_vector_to_irq __ia64_local_vector_to_irq 377# define platform_local_vector_to_irq __ia64_local_vector_to_irq
371#endif 378#endif
diff --git a/include/asm-ia64/machvec_init.h b/include/asm-ia64/machvec_init.h
index 2d36f6840f0b..7f21249fba3f 100644
--- a/include/asm-ia64/machvec_init.h
+++ b/include/asm-ia64/machvec_init.h
@@ -2,6 +2,7 @@
2 2
3extern ia64_mv_send_ipi_t ia64_send_ipi; 3extern ia64_mv_send_ipi_t ia64_send_ipi;
4extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge; 4extern ia64_mv_global_tlb_purge_t ia64_global_tlb_purge;
5extern ia64_mv_irq_to_vector __ia64_irq_to_vector;
5extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq; 6extern ia64_mv_local_vector_to_irq __ia64_local_vector_to_irq;
6extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem; 7extern ia64_mv_pci_get_legacy_mem_t ia64_pci_get_legacy_mem;
7extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read; 8extern ia64_mv_pci_legacy_read_t ia64_pci_legacy_read;
diff --git a/include/asm-ia64/machvec_sn2.h b/include/asm-ia64/machvec_sn2.h
index eaa2fce0fecd..61439a7f5b08 100644
--- a/include/asm-ia64/machvec_sn2.h
+++ b/include/asm-ia64/machvec_sn2.h
@@ -35,6 +35,7 @@ extern ia64_mv_send_ipi_t sn2_send_IPI;
35extern ia64_mv_timer_interrupt_t sn_timer_interrupt; 35extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
36extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge; 36extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
37extern ia64_mv_tlb_migrate_finish_t sn_tlb_migrate_finish; 37extern ia64_mv_tlb_migrate_finish_t sn_tlb_migrate_finish;
38extern ia64_mv_irq_to_vector sn_irq_to_vector;
38extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq; 39extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
39extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem; 40extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
40extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read; 41extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
@@ -104,6 +105,7 @@ extern ia64_mv_pci_fixup_bus_t sn_pci_fixup_bus;
104#define platform_readw_relaxed __sn_readw_relaxed 105#define platform_readw_relaxed __sn_readw_relaxed
105#define platform_readl_relaxed __sn_readl_relaxed 106#define platform_readl_relaxed __sn_readl_relaxed
106#define platform_readq_relaxed __sn_readq_relaxed 107#define platform_readq_relaxed __sn_readq_relaxed
108#define platform_irq_to_vector sn_irq_to_vector
107#define platform_local_vector_to_irq sn_local_vector_to_irq 109#define platform_local_vector_to_irq sn_local_vector_to_irq
108#define platform_pci_get_legacy_mem sn_pci_get_legacy_mem 110#define platform_pci_get_legacy_mem sn_pci_get_legacy_mem
109#define platform_pci_legacy_read sn_pci_legacy_read 111#define platform_pci_legacy_read sn_pci_legacy_read
diff --git a/include/asm-m68k/ioctls.h b/include/asm-m68k/ioctls.h
index 0c48929ab444..b8d2f4be7fd7 100644
--- a/include/asm-m68k/ioctls.h
+++ b/include/asm-m68k/ioctls.h
@@ -46,6 +46,10 @@
46#define TIOCSBRK 0x5427 /* BSD compatibility */ 46#define TIOCSBRK 0x5427 /* BSD compatibility */
47#define TIOCCBRK 0x5428 /* BSD compatibility */ 47#define TIOCCBRK 0x5428 /* BSD compatibility */
48#define TIOCGSID 0x5429 /* Return the session ID of FD */ 48#define TIOCGSID 0x5429 /* Return the session ID of FD */
49#define TCGETS2 _IOR('T',0x2A, struct termios2)
50#define TCSETS2 _IOW('T',0x2B, struct termios2)
51#define TCSETSW2 _IOW('T',0x2C, struct termios2)
52#define TCSETSF2 _IOW('T',0x2D, struct termios2)
49#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ 53#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
50#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ 54#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
51 55
diff --git a/include/asm-m68k/page.h b/include/asm-m68k/page.h
index 9e6d0d6debdb..1431ea0b59e0 100644
--- a/include/asm-m68k/page.h
+++ b/include/asm-m68k/page.h
@@ -4,17 +4,15 @@
4 4
5#ifdef __KERNEL__ 5#ifdef __KERNEL__
6 6
7#include <linux/const.h>
8
7/* PAGE_SHIFT determines the page size */ 9/* PAGE_SHIFT determines the page size */
8#ifndef CONFIG_SUN3 10#ifndef CONFIG_SUN3
9#define PAGE_SHIFT (12) 11#define PAGE_SHIFT (12)
10#else 12#else
11#define PAGE_SHIFT (13) 13#define PAGE_SHIFT (13)
12#endif 14#endif
13#ifdef __ASSEMBLY__ 15#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
14#define PAGE_SIZE (1 << PAGE_SHIFT)
15#else
16#define PAGE_SIZE (1UL << PAGE_SHIFT)
17#endif
18#define PAGE_MASK (~(PAGE_SIZE-1)) 16#define PAGE_MASK (~(PAGE_SIZE-1))
19 17
20#include <asm/setup.h> 18#include <asm/setup.h>
@@ -27,6 +25,8 @@
27 25
28#ifndef __ASSEMBLY__ 26#ifndef __ASSEMBLY__
29 27
28#include <linux/compiler.h>
29
30#include <asm/module.h> 30#include <asm/module.h>
31 31
32#define get_user_page(vaddr) __get_free_page(GFP_KERNEL) 32#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
diff --git a/include/asm-m68k/processor.h b/include/asm-m68k/processor.h
index 8455f778b601..4453ec379c5d 100644
--- a/include/asm-m68k/processor.h
+++ b/include/asm-m68k/processor.h
@@ -38,12 +38,8 @@ static inline void wrusp(unsigned long usp)
38#ifndef CONFIG_SUN3 38#ifndef CONFIG_SUN3
39#define TASK_SIZE (0xF0000000UL) 39#define TASK_SIZE (0xF0000000UL)
40#else 40#else
41#ifdef __ASSEMBLY__
42#define TASK_SIZE (0x0E000000)
43#else
44#define TASK_SIZE (0x0E000000UL) 41#define TASK_SIZE (0x0E000000UL)
45#endif 42#endif
46#endif
47 43
48/* This decides where the kernel will search for a free chunk of vm 44/* This decides where the kernel will search for a free chunk of vm
49 * space during mmap's. 45 * space during mmap's.
diff --git a/include/asm-m68k/termbits.h b/include/asm-m68k/termbits.h
index 0e520f328f53..8c14170996bb 100644
--- a/include/asm-m68k/termbits.h
+++ b/include/asm-m68k/termbits.h
@@ -141,6 +141,7 @@ struct ktermios {
141#define HUPCL 0002000 141#define HUPCL 0002000
142#define CLOCAL 0004000 142#define CLOCAL 0004000
143#define CBAUDEX 0010000 143#define CBAUDEX 0010000
144#define BOTHER 0010000
144#define B57600 0010001 145#define B57600 0010001
145#define B115200 0010002 146#define B115200 0010002
146#define B230400 0010003 147#define B230400 0010003
@@ -156,10 +157,12 @@ struct ktermios {
156#define B3000000 0010015 157#define B3000000 0010015
157#define B3500000 0010016 158#define B3500000 0010016
158#define B4000000 0010017 159#define B4000000 0010017
159#define CIBAUD 002003600000 /* input baud rate (not used) */ 160#define CIBAUD 002003600000 /* input baud rate */
160#define CMSPAR 010000000000 /* mark or space (stick) parity */ 161#define CMSPAR 010000000000 /* mark or space (stick) parity */
161#define CRTSCTS 020000000000 /* flow control */ 162#define CRTSCTS 020000000000 /* flow control */
162 163
164#define IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
165
163/* c_lflag bits */ 166/* c_lflag bits */
164#define ISIG 0000001 167#define ISIG 0000001
165#define ICANON 0000002 168#define ICANON 0000002
diff --git a/include/asm-m68k/termios.h b/include/asm-m68k/termios.h
index 00edabd76168..0823032e4045 100644
--- a/include/asm-m68k/termios.h
+++ b/include/asm-m68k/termios.h
@@ -82,8 +82,10 @@ struct termio {
82 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ 82 copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
83}) 83})
84 84
85#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) 85#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
86#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) 86#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
87#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
88#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
87 89
88#endif /* __KERNEL__ */ 90#endif /* __KERNEL__ */
89 91
diff --git a/include/asm-m68knommu/pgtable.h b/include/asm-m68knommu/pgtable.h
index e1e6a1d2333a..46251016e821 100644
--- a/include/asm-m68knommu/pgtable.h
+++ b/include/asm-m68knommu/pgtable.h
@@ -65,4 +65,6 @@ extern unsigned int kobjsize(const void *objp);
65#define VMALLOC_START 0 65#define VMALLOC_START 0
66#define VMALLOC_END 0xffffffff 66#define VMALLOC_END 0xffffffff
67 67
68#include <asm-generic/pgtable.h>
69
68#endif /* _M68KNOMMU_PGTABLE_H */ 70#endif /* _M68KNOMMU_PGTABLE_H */
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
index 3646a3f2ed38..0ba9d6ef76a7 100644
--- a/include/asm-mips/bcache.h
+++ b/include/asm-mips/bcache.h
@@ -21,7 +21,6 @@ struct bcache_ops {
21}; 21};
22 22
23extern void indy_sc_init(void); 23extern void indy_sc_init(void);
24extern void sni_pcimt_sc_init(void);
25 24
26#ifdef CONFIG_BOARD_SCACHE 25#ifdef CONFIG_BOARD_SCACHE
27 26
diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h
index 83719eee2d13..4da0c1fe30d9 100644
--- a/include/asm-mips/edac.h
+++ b/include/asm-mips/edac.h
@@ -9,8 +9,7 @@ static inline void atomic_scrub(void *va, u32 size)
9 unsigned long temp; 9 unsigned long temp;
10 u32 i; 10 u32 i;
11 11
12 for (i = 0; i < size / sizeof(unsigned long); i++, virt_addr++) { 12 for (i = 0; i < size / sizeof(unsigned long); i++) {
13
14 /* 13 /*
15 * Very carefully read and write to memory atomically 14 * Very carefully read and write to memory atomically
16 * so we are interrupt, DMA and SMP safe. 15 * so we are interrupt, DMA and SMP safe.
@@ -19,16 +18,16 @@ static inline void atomic_scrub(void *va, u32 size)
19 */ 18 */
20 19
21 __asm__ __volatile__ ( 20 __asm__ __volatile__ (
22 " .set mips3 \n" 21 " .set mips2 \n"
23 "1: ll %0, %1 # atomic_add \n" 22 "1: ll %0, %1 # atomic_scrub \n"
24 " ll %0, %1 # atomic_add \n" 23 " addu %0, $0 \n"
25 " addu %0, $0 \n" 24 " sc %0, %1 \n"
26 " sc %0, %1 \n" 25 " beqz %0, 1b \n"
27 " beqz %0, 1b \n" 26 " .set mips0 \n"
28 " .set mips0 \n"
29 : "=&r" (temp), "=m" (*virt_addr) 27 : "=&r" (temp), "=m" (*virt_addr)
30 : "m" (*virt_addr)); 28 : "m" (*virt_addr));
31 29
30 virt_addr++;
32 } 31 }
33} 32}
34 33
diff --git a/include/asm-mips/gt64240.h b/include/asm-mips/gt64240.h
deleted file mode 100644
index 8f9bd341ed49..000000000000
--- a/include/asm-mips/gt64240.h
+++ /dev/null
@@ -1,1235 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright - Galileo technology.
7 * Copyright (C) 2004 by Ralf Baechle
8 */
9#ifndef __ASM_MIPS_MV64240_H
10#define __ASM_MIPS_MV64240_H
11
12#include <asm/addrspace.h>
13#include <asm/marvell.h>
14
15/*
16 * CPU Control Registers
17 */
18
19#define CPU_CONFIGURATION 0x000
20#define CPU_MODE 0x120
21#define CPU_READ_RESPONSE_CROSSBAR_LOW 0x170
22#define CPU_READ_RESPONSE_CROSSBAR_HIGH 0x178
23
24/*
25 * Processor Address Space
26 */
27
28/* Sdram's BAR'S */
29#define SCS_0_LOW_DECODE_ADDRESS 0x008
30#define SCS_0_HIGH_DECODE_ADDRESS 0x010
31#define SCS_1_LOW_DECODE_ADDRESS 0x208
32#define SCS_1_HIGH_DECODE_ADDRESS 0x210
33#define SCS_2_LOW_DECODE_ADDRESS 0x018
34#define SCS_2_HIGH_DECODE_ADDRESS 0x020
35#define SCS_3_LOW_DECODE_ADDRESS 0x218
36#define SCS_3_HIGH_DECODE_ADDRESS 0x220
37/* Devices BAR'S */
38#define CS_0_LOW_DECODE_ADDRESS 0x028
39#define CS_0_HIGH_DECODE_ADDRESS 0x030
40#define CS_1_LOW_DECODE_ADDRESS 0x228
41#define CS_1_HIGH_DECODE_ADDRESS 0x230
42#define CS_2_LOW_DECODE_ADDRESS 0x248
43#define CS_2_HIGH_DECODE_ADDRESS 0x250
44#define CS_3_LOW_DECODE_ADDRESS 0x038
45#define CS_3_HIGH_DECODE_ADDRESS 0x040
46#define BOOTCS_LOW_DECODE_ADDRESS 0x238
47#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
48
49#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
50#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
51#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
52#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
53#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
54#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
55#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
56#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
57#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
58#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
59
60#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
61#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
62#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
63#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
64#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
65#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
66#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
67#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
68#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
69#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
70
71#define INTERNAL_SPACE_DECODE 0x068
72
73#define CPU_0_LOW_DECODE_ADDRESS 0x290
74#define CPU_0_HIGH_DECODE_ADDRESS 0x298
75#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
76#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
77
78#define PCI_0I_O_ADDRESS_REMAP 0x0f0
79#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
80#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
81#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
82#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
83#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
84#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
85#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
86#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
87
88#define PCI_1I_O_ADDRESS_REMAP 0x108
89#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
90#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
91#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
92#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
93#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
94#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
95#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
96#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
97
98/*
99 * CPU Sync Barrier
100 */
101
102#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
103#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
104
105
106/*
107 * CPU Access Protect
108 */
109
110#define CPU_LOW_PROTECT_ADDRESS_0 0X180
111#define CPU_HIGH_PROTECT_ADDRESS_0 0X188
112#define CPU_LOW_PROTECT_ADDRESS_1 0X190
113#define CPU_HIGH_PROTECT_ADDRESS_1 0X198
114#define CPU_LOW_PROTECT_ADDRESS_2 0X1a0
115#define CPU_HIGH_PROTECT_ADDRESS_2 0X1a8
116#define CPU_LOW_PROTECT_ADDRESS_3 0X1b0
117#define CPU_HIGH_PROTECT_ADDRESS_3 0X1b8
118#define CPU_LOW_PROTECT_ADDRESS_4 0X1c0
119#define CPU_HIGH_PROTECT_ADDRESS_4 0X1c8
120#define CPU_LOW_PROTECT_ADDRESS_5 0X1d0
121#define CPU_HIGH_PROTECT_ADDRESS_5 0X1d8
122#define CPU_LOW_PROTECT_ADDRESS_6 0X1e0
123#define CPU_HIGH_PROTECT_ADDRESS_6 0X1e8
124#define CPU_LOW_PROTECT_ADDRESS_7 0X1f0
125#define CPU_HIGH_PROTECT_ADDRESS_7 0X1f8
126
127
128/*
129 * Snoop Control
130 */
131
132#define SNOOP_BASE_ADDRESS_0 0x380
133#define SNOOP_TOP_ADDRESS_0 0x388
134#define SNOOP_BASE_ADDRESS_1 0x390
135#define SNOOP_TOP_ADDRESS_1 0x398
136#define SNOOP_BASE_ADDRESS_2 0x3a0
137#define SNOOP_TOP_ADDRESS_2 0x3a8
138#define SNOOP_BASE_ADDRESS_3 0x3b0
139#define SNOOP_TOP_ADDRESS_3 0x3b8
140
141/*
142 * CPU Error Report
143 */
144
145#define CPU_ERROR_ADDRESS_LOW 0x070
146#define CPU_ERROR_ADDRESS_HIGH 0x078
147#define CPU_ERROR_DATA_LOW 0x128
148#define CPU_ERROR_DATA_HIGH 0x130
149#define CPU_ERROR_PARITY 0x138
150#define CPU_ERROR_CAUSE 0x140
151#define CPU_ERROR_MASK 0x148
152
153/*
154 * Pslave Debug
155 */
156
157#define X_0_ADDRESS 0x360
158#define X_0_COMMAND_ID 0x368
159#define X_1_ADDRESS 0x370
160#define X_1_COMMAND_ID 0x378
161#define WRITE_DATA_LOW 0x3c0
162#define WRITE_DATA_HIGH 0x3c8
163#define WRITE_BYTE_ENABLE 0X3e0
164#define READ_DATA_LOW 0x3d0
165#define READ_DATA_HIGH 0x3d8
166#define READ_ID 0x3e8
167
168
169/*
170 * SDRAM and Device Address Space
171 */
172
173
174/*
175 * SDRAM Configuration
176 */
177
178#define SDRAM_CONFIGURATION 0x448
179#define SDRAM_OPERATION_MODE 0x474
180#define SDRAM_ADDRESS_DECODE 0x47C
181#define SDRAM_TIMING_PARAMETERS 0x4b4
182#define SDRAM_UMA_CONTROL 0x4a4
183#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
184#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
185#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
186
187
188/*
189 * SDRAM Parameters
190 */
191
192#define SDRAM_BANK0PARAMETERS 0x44C
193#define SDRAM_BANK1PARAMETERS 0x450
194#define SDRAM_BANK2PARAMETERS 0x454
195#define SDRAM_BANK3PARAMETERS 0x458
196
197
198/*
199 * SDRAM Error Report
200 */
201
202#define SDRAM_ERROR_DATA_LOW 0x484
203#define SDRAM_ERROR_DATA_HIGH 0x480
204#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
205#define SDRAM_RECEIVED_ECC 0x488
206#define SDRAM_CALCULATED_ECC 0x48c
207#define SDRAM_ECC_CONTROL 0x494
208#define SDRAM_ECC_ERROR_COUNTER 0x498
209
210
211/*
212 * SDunit Debug (for internal use)
213 */
214
215#define X0_ADDRESS 0x500
216#define X0_COMMAND_AND_ID 0x504
217#define X0_WRITE_DATA_LOW 0x508
218#define X0_WRITE_DATA_HIGH 0x50c
219#define X0_WRITE_BYTE_ENABLE 0x518
220#define X0_READ_DATA_LOW 0x510
221#define X0_READ_DATA_HIGH 0x514
222#define X0_READ_ID 0x51c
223#define X1_ADDRESS 0x520
224#define X1_COMMAND_AND_ID 0x524
225#define X1_WRITE_DATA_LOW 0x528
226#define X1_WRITE_DATA_HIGH 0x52c
227#define X1_WRITE_BYTE_ENABLE 0x538
228#define X1_READ_DATA_LOW 0x530
229#define X1_READ_DATA_HIGH 0x534
230#define X1_READ_ID 0x53c
231#define X0_SNOOP_ADDRESS 0x540
232#define X0_SNOOP_COMMAND 0x544
233#define X1_SNOOP_ADDRESS 0x548
234#define X1_SNOOP_COMMAND 0x54c
235
236
237/*
238 * Device Parameters
239 */
240
241#define DEVICE_BANK0PARAMETERS 0x45c
242#define DEVICE_BANK1PARAMETERS 0x460
243#define DEVICE_BANK2PARAMETERS 0x464
244#define DEVICE_BANK3PARAMETERS 0x468
245#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
246#define DEVICE_CONTROL 0x4c0
247#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
248#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
249#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
250
251
252/*
253 * Device Interrupt
254 */
255
256#define DEVICE_INTERRUPT_CAUSE 0x4d0
257#define DEVICE_INTERRUPT_MASK 0x4d4
258#define DEVICE_ERROR_ADDRESS 0x4d8
259
260/*
261 * DMA Record
262 */
263
264#define CHANNEL0_DMA_BYTE_COUNT 0x800
265#define CHANNEL1_DMA_BYTE_COUNT 0x804
266#define CHANNEL2_DMA_BYTE_COUNT 0x808
267#define CHANNEL3_DMA_BYTE_COUNT 0x80C
268#define CHANNEL4_DMA_BYTE_COUNT 0x900
269#define CHANNEL5_DMA_BYTE_COUNT 0x904
270#define CHANNEL6_DMA_BYTE_COUNT 0x908
271#define CHANNEL7_DMA_BYTE_COUNT 0x90C
272#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
273#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
274#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
275#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
276#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
277#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
278#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
279#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
280#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
281#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
282#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
283#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
284#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
285#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
286#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
287#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
288#define CHANNEL0NEXT_RECORD_POINTER 0x830
289#define CHANNEL1NEXT_RECORD_POINTER 0x834
290#define CHANNEL2NEXT_RECORD_POINTER 0x838
291#define CHANNEL3NEXT_RECORD_POINTER 0x83C
292#define CHANNEL4NEXT_RECORD_POINTER 0x930
293#define CHANNEL5NEXT_RECORD_POINTER 0x934
294#define CHANNEL6NEXT_RECORD_POINTER 0x938
295#define CHANNEL7NEXT_RECORD_POINTER 0x93C
296#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
297#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
298#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
299#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
300#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
301#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
302#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
303#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
304#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
305#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
306#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
307#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
308#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
309#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
310#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
311#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
312#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
313#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
314#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
315#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
316#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
317#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
318#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
319#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
320#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
321#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
322#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
323#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
324#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
325#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
326#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
327#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
328
329/*
330 * DMA Channel Control
331 */
332
333#define CHANNEL0CONTROL 0x840
334#define CHANNEL0CONTROL_HIGH 0x880
335
336#define CHANNEL1CONTROL 0x844
337#define CHANNEL1CONTROL_HIGH 0x884
338
339#define CHANNEL2CONTROL 0x848
340#define CHANNEL2CONTROL_HIGH 0x888
341
342#define CHANNEL3CONTROL 0x84C
343#define CHANNEL3CONTROL_HIGH 0x88C
344
345#define CHANNEL4CONTROL 0x940
346#define CHANNEL4CONTROL_HIGH 0x980
347
348#define CHANNEL5CONTROL 0x944
349#define CHANNEL5CONTROL_HIGH 0x984
350
351#define CHANNEL6CONTROL 0x948
352#define CHANNEL6CONTROL_HIGH 0x988
353
354#define CHANNEL7CONTROL 0x94C
355#define CHANNEL7CONTROL_HIGH 0x98C
356
357
358/*
359 * DMA Arbiter
360 */
361
362#define ARBITER_CONTROL_0_3 0x860
363#define ARBITER_CONTROL_4_7 0x960
364
365
366/*
367 * DMA Interrupt
368 */
369
370#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
371#define CHANELS0_3_INTERRUPT_MASK 0x8c4
372#define CHANELS0_3_ERROR_ADDRESS 0x8c8
373#define CHANELS0_3_ERROR_SELECT 0x8cc
374#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
375#define CHANELS4_7_INTERRUPT_MASK 0x9c4
376#define CHANELS4_7_ERROR_ADDRESS 0x9c8
377#define CHANELS4_7_ERROR_SELECT 0x9cc
378
379
380/*
381 * DMA Debug (for internal use)
382 */
383
384#define DMA_X0_ADDRESS 0x8e0
385#define DMA_X0_COMMAND_AND_ID 0x8e4
386#define DMA_X0_WRITE_DATA_LOW 0x8e8
387#define DMA_X0_WRITE_DATA_HIGH 0x8ec
388#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
389#define DMA_X0_READ_DATA_LOW 0x8f0
390#define DMA_X0_READ_DATA_HIGH 0x8f4
391#define DMA_X0_READ_ID 0x8fc
392#define DMA_X1_ADDRESS 0x9e0
393#define DMA_X1_COMMAND_AND_ID 0x9e4
394#define DMA_X1_WRITE_DATA_LOW 0x9e8
395#define DMA_X1_WRITE_DATA_HIGH 0x9ec
396#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
397#define DMA_X1_READ_DATA_LOW 0x9f0
398#define DMA_X1_READ_DATA_HIGH 0x9f4
399#define DMA_X1_READ_ID 0x9fc
400
401/*
402 * Timer_Counter
403 */
404
405#define TIMER_COUNTER0 0x850
406#define TIMER_COUNTER1 0x854
407#define TIMER_COUNTER2 0x858
408#define TIMER_COUNTER3 0x85C
409#define TIMER_COUNTER_0_3_CONTROL 0x864
410#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
411#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
412#define TIMER_COUNTER4 0x950
413#define TIMER_COUNTER5 0x954
414#define TIMER_COUNTER6 0x958
415#define TIMER_COUNTER7 0x95C
416#define TIMER_COUNTER_4_7_CONTROL 0x964
417#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
418#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
419
420/*
421 * PCI Slave Address Decoding
422 */
423
424#define PCI_0SCS_0_BANK_SIZE 0xc08
425#define PCI_1SCS_0_BANK_SIZE 0xc88
426#define PCI_0SCS_1_BANK_SIZE 0xd08
427#define PCI_1SCS_1_BANK_SIZE 0xd88
428#define PCI_0SCS_2_BANK_SIZE 0xc0c
429#define PCI_1SCS_2_BANK_SIZE 0xc8c
430#define PCI_0SCS_3_BANK_SIZE 0xd0c
431#define PCI_1SCS_3_BANK_SIZE 0xd8c
432#define PCI_0CS_0_BANK_SIZE 0xc10
433#define PCI_1CS_0_BANK_SIZE 0xc90
434#define PCI_0CS_1_BANK_SIZE 0xd10
435#define PCI_1CS_1_BANK_SIZE 0xd90
436#define PCI_0CS_2_BANK_SIZE 0xd18
437#define PCI_1CS_2_BANK_SIZE 0xd98
438#define PCI_0CS_3_BANK_SIZE 0xc14
439#define PCI_1CS_3_BANK_SIZE 0xc94
440#define PCI_0CS_BOOT_BANK_SIZE 0xd14
441#define PCI_1CS_BOOT_BANK_SIZE 0xd94
442#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
443#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
444#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
445#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
446#define PCI_0P2P_I_O_BAR_SIZE 0xd24
447#define PCI_1P2P_I_O_BAR_SIZE 0xda4
448#define PCI_0CPU_BAR_SIZE 0xd28
449#define PCI_1CPU_BAR_SIZE 0xda8
450#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
451#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
452#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
453#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
454#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
455#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
456#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
457#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
458#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
459#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
460#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
461#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
462#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
463#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
464#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
465#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
466#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
467#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
468#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
469#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
470#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
471#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
472#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
473#define PCI_1DAC_CPU_BAR_SIZE 0xeac
474#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
475#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
476#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
477#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
478#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
479#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
480#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
481#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
482#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
483#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
484#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
485#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
486#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
487#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
488#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
489#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
490#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
491#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
492#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
493#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
494#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
495#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
496#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
497#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
498#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
499#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
500#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
501#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
502#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
503#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
504#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
505#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
506#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
507#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
508#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
509#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
510#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
511#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
512#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
513#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
514#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
515#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
516#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
517#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
518#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
519#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
520#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
521#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
522#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
523#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
524#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
525#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
526#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
527#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
528#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
529#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
530#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
531#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
532#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
533#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
534#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
535#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
536#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
537#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
538#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
539#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
540
541/*
542 * PCI Control
543 */
544
545#define PCI_0COMMAND 0xc00
546#define PCI_1COMMAND 0xc80
547#define PCI_0MODE 0xd00
548#define PCI_1MODE 0xd80
549#define PCI_0TIMEOUT_RETRY 0xc04
550#define PCI_1TIMEOUT_RETRY 0xc84
551#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
552#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
553#define MSI_0TRIGGER_TIMER 0xc38
554#define MSI_1TRIGGER_TIMER 0xcb8
555#define PCI_0ARBITER_CONTROL 0x1d00
556#define PCI_1ARBITER_CONTROL 0x1d80
557/* changing untill here */
558#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
559#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
560#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
561#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
562#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
563#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
564#define PCI_0P2P_CONFIGURATION 0x1d14
565#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
566#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
567#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
568#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0c1e10
569#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
570#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
571#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0c1e20
572#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
573#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
574#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0c1e30
575#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
576#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
577#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0c1e40
578#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
579#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
580#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0c1e50
581#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
582#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
583#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0c1e60
584#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
585#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
586#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0c1e70
587#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
588#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
589#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
590#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
591#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
592#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
593#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
594#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
595#define PCI_1P2P_CONFIGURATION 0x1d94
596#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
597#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
598#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
599#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0c1e90
600#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
601#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
602#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0c1ea0
603#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
604#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
605#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0c1eb0
606#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
607#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
608#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0c1ec0
609#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
610#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
611#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0c1ed0
612#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
613#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
614#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0c1ee0
615#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
616#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
617#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0c1ef0
618#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
619#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
620
621/*
622 * PCI Snoop Control
623 */
624
625#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
626#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
627#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
628#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
629#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
630#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
631#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
632#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
633#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
634#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
635#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
636#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
637#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
638#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
639#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
640#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
641#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
642#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
643#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
644#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
645#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
646#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
647#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
648#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
649
650/*
651 * PCI Configuration Address
652 */
653
654#define PCI_0CONFIGURATION_ADDRESS 0xcf8
655#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
656#define PCI_1CONFIGURATION_ADDRESS 0xc78
657#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
658#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
659#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
660
661/*
662 * PCI Error Report
663 */
664
665#define PCI_0SERR_MASK 0xc28
666#define PCI_0ERROR_ADDRESS_LOW 0x1d40
667#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
668#define PCI_0ERROR_DATA_LOW 0x1d48
669#define PCI_0ERROR_DATA_HIGH 0x1d4c
670#define PCI_0ERROR_COMMAND 0x1d50
671#define PCI_0ERROR_CAUSE 0x1d58
672#define PCI_0ERROR_MASK 0x1d5c
673
674#define PCI_1SERR_MASK 0xca8
675#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
676#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
677#define PCI_1ERROR_DATA_LOW 0x1dc8
678#define PCI_1ERROR_DATA_HIGH 0x1dcc
679#define PCI_1ERROR_COMMAND 0x1dd0
680#define PCI_1ERROR_CAUSE 0x1dd8
681#define PCI_1ERROR_MASK 0x1ddc
682
683
684/*
685 * Lslave Debug (for internal use)
686 */
687
688#define L_SLAVE_X0_ADDRESS 0x1d20
689#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
690#define L_SLAVE_X1_ADDRESS 0x1d28
691#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
692#define L_SLAVE_WRITE_DATA_LOW 0x1d30
693#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
694#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
695#define L_SLAVE_READ_DATA_LOW 0x1d38
696#define L_SLAVE_READ_DATA_HIGH 0x1d3c
697#define L_SLAVE_READ_ID 0x1d64
698
699#if 0 /* Disabled because PCI_* namespace belongs to PCI subsystem ... */
700
701/*
702 * PCI Configuration Function 0
703 */
704
705#define PCI_DEVICE_AND_VENDOR_ID 0x000
706#define PCI_STATUS_AND_COMMAND 0x004
707#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
708#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
709#define PCI_SCS_0_BASE_ADDRESS 0x010
710#define PCI_SCS_1_BASE_ADDRESS 0x014
711#define PCI_SCS_2_BASE_ADDRESS 0x018
712#define PCI_SCS_3_BASE_ADDRESS 0x01C
713#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
714#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
715#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
716#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
717#define PCI_CAPABILTY_LIST_POINTER 0x034
718#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
719#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
720#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
721#define PCI_VPD_ADDRESS 0x048
722#define PCI_VPD_DATA 0X04c
723#define PCI_MSI_MESSAGE_CONTROL 0x050
724#define PCI_MSI_MESSAGE_ADDRESS 0x054
725#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
726#define PCI_MSI_MESSAGE_DATA 0x05c
727#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
728
729/*
730 * PCI Configuration Function 1
731 */
732
733#define PCI_CS_0_BASE_ADDRESS 0x110
734#define PCI_CS_1_BASE_ADDRESS 0x114
735#define PCI_CS_2_BASE_ADDRESS 0x118
736#define PCI_CS_3_BASE_ADDRESS 0x11c
737#define PCI_BOOTCS_BASE_ADDRESS 0x120
738
739/*
740 * PCI Configuration Function 2
741 */
742
743#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
744#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
745#define PCI_P2P_I_O_BASE_ADDRESS 0x218
746#define PCI_CPU_BASE_ADDRESS 0x21c
747
748/*
749 * PCI Configuration Function 4
750 */
751
752#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
753#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
754#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
755#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
756#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
757#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
758
759
760/*
761 * PCI Configuration Function 5
762 */
763
764#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
765#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
766#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
767#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
768#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
769#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
770
771
772/*
773 * PCI Configuration Function 6
774 */
775
776#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
777#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
778#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
779#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
780#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
781#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
782
783/*
784 * PCI Configuration Function 7
785 */
786
787#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
788#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
789#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
790#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
791#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
792#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
793#endif
794
795/*
796 * Interrupts
797 */
798
799#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
800#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
801#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
802#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
803#define CPU_SELECT_CAUSE_REGISTER 0xc70
804#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
805#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
806#define PCI_0SELECT_CAUSE 0xc74
807#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
808#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
809#define PCI_1SELECT_CAUSE 0xcf4
810#define CPU_INT_0_MASK 0xe60
811#define CPU_INT_1_MASK 0xe64
812#define CPU_INT_2_MASK 0xe68
813#define CPU_INT_3_MASK 0xe6c
814
815/*
816 * I20 Support registers
817 */
818
819#define INBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x010
820#define INBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x014
821#define OUTBOUND_MESSAGE_REGISTER0_PCI0_SIDE 0x018
822#define OUTBOUND_MESSAGE_REGISTER1_PCI0_SIDE 0x01C
823#define INBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x020
824#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x024
825#define INBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x028
826#define OUTBOUND_DOORBELL_REGISTER_PCI0_SIDE 0x02C
827#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI0_SIDE 0x030
828#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI0_SIDE 0x034
829#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x040
830#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI0_SIDE 0x044
831#define QUEUE_CONTROL_REGISTER_PCI0_SIDE 0x050
832#define QUEUE_BASE_ADDRESS_REGISTER_PCI0_SIDE 0x054
833#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x060
834#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x064
835#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x068
836#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x06C
837#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI0_SIDE 0x070
838#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI0_SIDE 0x074
839#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI0_SIDE 0x0F8
840#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI0_SIDE 0x0FC
841
842#define INBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x090
843#define INBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x094
844#define OUTBOUND_MESSAGE_REGISTER0_PCI1_SIDE 0x098
845#define OUTBOUND_MESSAGE_REGISTER1_PCI1_SIDE 0x09C
846#define INBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0A0
847#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0A4
848#define INBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0A8
849#define OUTBOUND_DOORBELL_REGISTER_PCI1_SIDE 0x0AC
850#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI1_SIDE 0x0B0
851#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI1_SIDE 0x0B4
852#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C0
853#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI1_SIDE 0x0C4
854#define QUEUE_CONTROL_REGISTER_PCI1_SIDE 0x0D0
855#define QUEUE_BASE_ADDRESS_REGISTER_PCI1_SIDE 0x0D4
856#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E0
857#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0E4
858#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0E8
859#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0EC
860#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI1_SIDE 0x0F0
861#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI1_SIDE 0x0F4
862#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI1_SIDE 0x078
863#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI1_SIDE 0x07C
864
865#define INBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C10
866#define INBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C14
867#define OUTBOUND_MESSAGE_REGISTER0_CPU0_SIDE 0X1C18
868#define OUTBOUND_MESSAGE_REGISTER1_CPU0_SIDE 0X1C1C
869#define INBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C20
870#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C24
871#define INBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C28
872#define OUTBOUND_DOORBELL_REGISTER_CPU0_SIDE 0X1C2C
873#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU0_SIDE 0X1C30
874#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU0_SIDE 0X1C34
875#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C40
876#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU0_SIDE 0X1C44
877#define QUEUE_CONTROL_REGISTER_CPU0_SIDE 0X1C50
878#define QUEUE_BASE_ADDRESS_REGISTER_CPU0_SIDE 0X1C54
879#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C60
880#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C64
881#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C68
882#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C6C
883#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1C70
884#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1C74
885#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU0_SIDE 0X1CF8
886#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU0_SIDE 0X1CFC
887
888#define INBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C90
889#define INBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C94
890#define OUTBOUND_MESSAGE_REGISTER0_CPU1_SIDE 0X1C98
891#define OUTBOUND_MESSAGE_REGISTER1_CPU1_SIDE 0X1C9C
892#define INBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CA0
893#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CA4
894#define INBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CA8
895#define OUTBOUND_DOORBELL_REGISTER_CPU1_SIDE 0X1CAC
896#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU1_SIDE 0X1CB0
897#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU1_SIDE 0X1CB4
898#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC0
899#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU1_SIDE 0X1CC4
900#define QUEUE_CONTROL_REGISTER_CPU1_SIDE 0X1CD0
901#define QUEUE_BASE_ADDRESS_REGISTER_CPU1_SIDE 0X1CD4
902#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE0
903#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CE4
904#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CE8
905#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CEC
906#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1CF0
907#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1CF4
908#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU1_SIDE 0X1C78
909#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU1_SIDE 0X1C7C
910
911/*
912 * Communication Unit Registers
913 */
914
915#define ETHERNET_0_ADDRESS_CONTROL_LOW
916#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
917#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
918#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
919#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
920#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
921#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
922#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
923#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
924#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
925#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
926#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
927#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
928#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
929#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
930#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
931#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
932#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
933#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
934#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
935#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
936#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
937#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
938#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
939#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
940#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
941#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
942#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2a0
943#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2a4
944#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2a8
945#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2ac
946#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b0
947#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2b4
948#define MPSC_2_ADDRESS_CONTROL_LOW 0xf2c0
949#define MPSC_2_ADDRESS_CONTROL_HIGH 0xf2c4
950#define MPSC_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
951#define MPSC_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
952#define MPSC_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
953#define MPSC_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
954#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
955#define SERIAL_INIT_LAST_DATA 0xf324
956#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
957#define COMM_UNIT_ARBITER_CONTROL 0xf300
958#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
959#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
960#define COMM_UNIT_INTERRUPT_MASK 0xf314
961#define COMM_UNIT_ERROR_ADDRESS 0xf314
962
963/*
964 * Cunit Debug (for internal use)
965 */
966
967#define CUNIT_ADDRESS 0xf340
968#define CUNIT_COMMAND_AND_ID 0xf344
969#define CUNIT_WRITE_DATA_LOW 0xf348
970#define CUNIT_WRITE_DATA_HIGH 0xf34c
971#define CUNIT_WRITE_BYTE_ENABLE 0xf358
972#define CUNIT_READ_DATA_LOW 0xf350
973#define CUNIT_READ_DATA_HIGH 0xf354
974#define CUNIT_READ_ID 0xf35c
975
976/*
977 * Fast Ethernet Unit Registers
978 */
979
980/* Ethernet */
981
982#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
983#define ETHERNET_SMI_REGISTER 0x2010
984
985/* Ethernet 0 */
986
987#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
988#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
989#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
990#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
991#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
992#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
993#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
994#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
995#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
996#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
997#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
998#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
999#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
1000#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
1001#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
1002#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
1003#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
1004#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
1005#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
1006#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
1007#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
1008#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
1009#define ETHERNET0_MIB_COUNTER_BASE 0x2500
1010
1011/* Ethernet 1 */
1012
1013#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
1014#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
1015#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
1016#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
1017#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
1018#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
1019#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
1020#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
1021#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
1022#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
1023#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
1024#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
1025#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
1026#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
1027#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
1028#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
1029#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
1030#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
1031#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
1032#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
1033#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
1034#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
1035#define ETHERNET1_MIB_COUNTER_BASE 0x2900
1036
1037/* Ethernet 2 */
1038
1039#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
1040#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
1041#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
1042#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
1043#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
1044#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
1045#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
1046#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
1047#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
1048#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
1049#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
1050#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
1051#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
1052#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
1053#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
1054#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
1055#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
1056#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
1057#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
1058#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
1059#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
1060#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
1061#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
1062
1063/*
1064 * SDMA Registers
1065 */
1066
1067#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
1068#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
1069#define CHANNEL0_COMMAND_REGISTER 0x4008
1070#define CHANNEL0_RX_CMD_STATUS 0x4800
1071#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
1072#define CHANNEL0_RX_BUFFER_POINTER 0x4808
1073#define CHANNEL0_RX_NEXT_POINTER 0x480c
1074#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
1075#define CHANNEL0_TX_CMD_STATUS 0x4C00
1076#define CHANNEL0_TX_PACKET_SIZE 0x4C04
1077#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
1078#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
1079#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
1080#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
1081#define CHANNEL1_CONFIGURATION_REGISTER 0x6000
1082#define CHANNEL1_COMMAND_REGISTER 0x6008
1083#define CHANNEL1_RX_CMD_STATUS 0x6800
1084#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x6804
1085#define CHANNEL1_RX_BUFFER_POINTER 0x6808
1086#define CHANNEL1_RX_NEXT_POINTER 0x680c
1087#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1088#define CHANNEL1_TX_CMD_STATUS 0x6C00
1089#define CHANNEL1_TX_PACKET_SIZE 0x6C04
1090#define CHANNEL1_TX_BUFFER_POINTER 0x6C08
1091#define CHANNEL1_TX_NEXT_POINTER 0x6C0c
1092#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
1093#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
1094#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
1095
1096/* SDMA Interrupt */
1097
1098#define SDMA_CAUSE 0xb820
1099#define SDMA_MASK 0xb8a0
1100
1101
1102/*
1103 * Baude Rate Generators Registers
1104 */
1105
1106/* BRG 0 */
1107
1108#define BRG0_CONFIGURATION_REGISTER 0xb200
1109#define BRG0_BAUDE_TUNING_REGISTER 0xb204
1110
1111/* BRG 1 */
1112
1113#define BRG1_CONFIGURATION_REGISTER 0xb208
1114#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
1115
1116/* BRG 2 */
1117
1118#define BRG2_CONFIGURATION_REGISTER 0xb210
1119#define BRG2_BAUDE_TUNING_REGISTER 0xb214
1120
1121/* BRG Interrupts */
1122
1123#define BRG_CAUSE_REGISTER 0xb834
1124#define BRG_MASK_REGISTER 0xb8b4
1125
1126/* MISC */
1127
1128#define MAIN_ROUTING_REGISTER 0xb400
1129#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
1130#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
1131#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
1132#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
1133#define WATCHDOG_VALUE_REGISTER 0xb414
1134
1135
1136/*
1137 * Flex TDM Registers
1138 */
1139
1140/* FTDM Port */
1141
1142#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
1143#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
1144#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
1145#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
1146#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
1147#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
1148#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
1149
1150/* FTDM Interrupts */
1151
1152#define FTDM_CAUSE_REGISTER 0xb830
1153#define FTDM_MASK_REGISTER 0xb8b0
1154
1155
1156/*
1157 * GPP Interface Registers
1158 */
1159
1160#define GPP_IO_CONTROL 0xf100
1161#define GPP_LEVEL_CONTROL 0xf110
1162#define GPP_VALUE 0xf104
1163#define GPP_INTERRUPT_CAUSE 0xf108
1164#define GPP_INTERRUPT_MASK 0xf10c
1165
1166#define MPP_CONTROL0 0xf000
1167#define MPP_CONTROL1 0xf004
1168#define MPP_CONTROL2 0xf008
1169#define MPP_CONTROL3 0xf00c
1170#define DEBUG_PORT_MULTIPLEX 0xf014
1171#define SERIAL_PORT_MULTIPLEX 0xf010
1172
1173/*
1174 * I2C Registers
1175 */
1176
1177#define I2C_SLAVE_ADDRESS 0xc000
1178#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
1179#define I2C_DATA 0xc004
1180#define I2C_CONTROL 0xc008
1181#define I2C_STATUS_BAUDE_RATE 0xc00C
1182#define I2C_SOFT_RESET 0xc01c
1183
1184/*
1185 * MPSC Registers
1186 */
1187
1188/*
1189 * MPSC0
1190 */
1191
1192#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
1193#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
1194#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
1195#define CHANNEL0_REGISTER1 0x800c
1196#define CHANNEL0_REGISTER2 0x8010
1197#define CHANNEL0_REGISTER3 0x8014
1198#define CHANNEL0_REGISTER4 0x8018
1199#define CHANNEL0_REGISTER5 0x801c
1200#define CHANNEL0_REGISTER6 0x8020
1201#define CHANNEL0_REGISTER7 0x8024
1202#define CHANNEL0_REGISTER8 0x8028
1203#define CHANNEL0_REGISTER9 0x802c
1204#define CHANNEL0_REGISTER10 0x8030
1205#define CHANNEL0_REGISTER11 0x8034
1206
1207/*
1208 * MPSC1
1209 */
1210
1211#define MPSC1_MAIN_CONFIGURATION_LOW 0x9000
1212#define MPSC1_MAIN_CONFIGURATION_HIGH 0x9004
1213#define MPSC1_PROTOCOL_CONFIGURATION 0x9008
1214#define CHANNEL1_REGISTER1 0x900c
1215#define CHANNEL1_REGISTER2 0x9010
1216#define CHANNEL1_REGISTER3 0x9014
1217#define CHANNEL1_REGISTER4 0x9018
1218#define CHANNEL1_REGISTER5 0x901c
1219#define CHANNEL1_REGISTER6 0x9020
1220#define CHANNEL1_REGISTER7 0x9024
1221#define CHANNEL1_REGISTER8 0x9028
1222#define CHANNEL1_REGISTER9 0x902c
1223#define CHANNEL1_REGISTER10 0x9030
1224#define CHANNEL1_REGISTER11 0x9034
1225
1226/*
1227 * MPSCs Interupts
1228 */
1229
1230#define MPSC0_CAUSE 0xb804
1231#define MPSC0_MASK 0xb884
1232#define MPSC1_CAUSE 0xb80c
1233#define MPSC1_MASK 0xb88c
1234
1235#endif /* __ASM_MIPS_MV64240_H */
diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 958e29706e2d..b2dc35f56181 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -13,6 +13,7 @@
13#include <asm/jmr3927/tx3927.h> 13#include <asm/jmr3927/tx3927.h>
14#include <asm/addrspace.h> 14#include <asm/addrspace.h>
15#include <asm/system.h> 15#include <asm/system.h>
16#include <asm/txx9irq.h>
16 17
17/* CS */ 18/* CS */
18#define JMR3927_ROMCE0 0x1fc00000 /* 4M */ 19#define JMR3927_ROMCE0 0x1fc00000 /* 4M */
@@ -115,7 +116,7 @@
115#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */ 116#define JMR3927_NR_IRQ_IRC 16 /* On-Chip IRC */
116#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */ 117#define JMR3927_NR_IRQ_IOC 8 /* PCI/MODEM/INT[6:7] */
117 118
118#define JMR3927_IRQ_IRC 16 119#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
119#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC) 120#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
120#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC) 121#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
121 122
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 0b9073bfb759..4be2f25f70dd 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -50,21 +50,6 @@ struct tx3927_dma_reg {
50 volatile unsigned long unused0; 50 volatile unsigned long unused0;
51}; 51};
52 52
53struct tx3927_irc_reg {
54 volatile unsigned long cer;
55 volatile unsigned long cr[2];
56 volatile unsigned long unused0;
57 volatile unsigned long ilr[8];
58 volatile unsigned long unused1[4];
59 volatile unsigned long imr;
60 volatile unsigned long unused2[7];
61 volatile unsigned long scr;
62 volatile unsigned long unused3[7];
63 volatile unsigned long ssr;
64 volatile unsigned long unused4[7];
65 volatile unsigned long csr;
66};
67
68#include <asm/byteorder.h> 53#include <asm/byteorder.h>
69 54
70#ifdef __BIG_ENDIAN 55#ifdef __BIG_ENDIAN
@@ -225,26 +210,6 @@ struct tx3927_ccfg_reg {
225/* 210/*
226 * IRC 211 * IRC
227 */ 212 */
228#define TX3927_IR_MAX_LEVEL 7
229
230/* IRCER : Int. Control Enable */
231#define TX3927_IRCER_ICE 0x00000001
232
233/* IRCR : Int. Control */
234#define TX3927_IRCR_LOW 0x00000000
235#define TX3927_IRCR_HIGH 0x00000001
236#define TX3927_IRCR_DOWN 0x00000002
237#define TX3927_IRCR_UP 0x00000003
238
239/* IRSCR : Int. Status Control */
240#define TX3927_IRSCR_EIClrE 0x00000100
241#define TX3927_IRSCR_EIClr_MASK 0x0000000f
242
243/* IRCSR : Int. Current Status */
244#define TX3927_IRCSR_IF 0x00010000
245#define TX3927_IRCSR_ILV_MASK 0x00000700
246#define TX3927_IRCSR_IVL_MASK 0x0000001f
247
248#define TX3927_IR_INT0 0 213#define TX3927_IR_INT0 0
249#define TX3927_IR_INT1 1 214#define TX3927_IR_INT1 1
250#define TX3927_IR_INT2 2 215#define TX3927_IR_INT2 2
@@ -347,7 +312,6 @@ struct tx3927_ccfg_reg {
347#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG) 312#define tx3927_sdramcptr ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
348#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG) 313#define tx3927_romcptr ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
349#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG) 314#define tx3927_dmaptr ((struct tx3927_dma_reg *)TX3927_DMA_REG)
350#define tx3927_ircptr ((struct tx3927_irc_reg *)TX3927_IRC_REG)
351#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG) 315#define tx3927_pcicptr ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
352#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG) 316#define tx3927_ccfgptr ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
353#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch)) 317#define tx3927_tmrptr(ch) ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
index 6eba2e576aaa..2b928577be5d 100644
--- a/include/asm-mips/mach-generic/ide.h
+++ b/include/asm-mips/mach-generic/ide.h
@@ -29,68 +29,42 @@
29 29
30#define IDE_ARCH_OBSOLETE_DEFAULTS 30#define IDE_ARCH_OBSOLETE_DEFAULTS
31 31
32static __inline__ int ide_probe_legacy(void)
33{
34#ifdef CONFIG_PCI
35 struct pci_dev *dev;
36 if ((dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL)) != NULL ||
37 (dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL)) != NULL) {
38 pci_dev_put(dev);
39
40 return 1;
41 }
42 return 0;
43#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
44 return 1;
45#else
46 return 0;
47#endif
48}
49
50static __inline__ int ide_default_irq(unsigned long base) 32static __inline__ int ide_default_irq(unsigned long base)
51{ 33{
52 if (ide_probe_legacy()) 34 switch (base) {
53 switch (base) { 35 case 0x1f0: return 14;
54 case 0x1f0: 36 case 0x170: return 15;
55 return 14; 37 case 0x1e8: return 11;
56 case 0x170: 38 case 0x168: return 10;
57 return 15; 39 case 0x1e0: return 8;
58 case 0x1e8: 40 case 0x160: return 12;
59 return 11;
60 case 0x168:
61 return 10;
62 case 0x1e0:
63 return 8;
64 case 0x160:
65 return 12;
66 default: 41 default:
67 return 0; 42 return 0;
68 } 43 }
69 else
70 return 0;
71} 44}
72 45
73static __inline__ unsigned long ide_default_io_base(int index) 46static __inline__ unsigned long ide_default_io_base(int index)
74{ 47{
75 if (ide_probe_legacy()) 48 /*
49 * If PCI is present then it is not safe to poke around
50 * the other legacy IDE ports. Only 0x1f0 and 0x170 are
51 * defined compatibility mode ports for PCI. A user can
52 * override this using ide= but we must default safe.
53 */
54 if (no_pci_devices()) {
76 switch (index) { 55 switch (index) {
77 case 0: 56 case 2: return 0x1e8;
78 return 0x1f0; 57 case 3: return 0x168;
79 case 1: 58 case 4: return 0x1e0;
80 return 0x170; 59 case 5: return 0x160;
81 case 2:
82 return 0x1e8;
83 case 3:
84 return 0x168;
85 case 4:
86 return 0x1e0;
87 case 5:
88 return 0x160;
89 default:
90 return 0;
91 } 60 }
92 else 61 }
62 switch (index) {
63 case 0: return 0x1f0;
64 case 1: return 0x170;
65 default:
93 return 0; 66 return 0;
67 }
94} 68}
95 69
96#define IDE_ARCH_OBSOLETE_INIT 70#define IDE_ARCH_OBSOLETE_INIT
diff --git a/include/asm-mips/marvell.h b/include/asm-mips/marvell.h
deleted file mode 100644
index b6144bafc565..000000000000
--- a/include/asm-mips/marvell.h
+++ /dev/null
@@ -1,59 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 by Ralf Baechle
7 */
8#ifndef __ASM_MIPS_MARVELL_H
9#define __ASM_MIPS_MARVELL_H
10
11#include <linux/pci.h>
12
13#include <asm/byteorder.h>
14
15extern unsigned long marvell_base;
16
17/*
18 * Because of an error/peculiarity in the Galileo chip, we need to swap the
19 * bytes when running bigendian.
20 */
21#define __MV_READ(ofs) \
22 (*(volatile u32 *)(marvell_base+(ofs)))
23#define __MV_WRITE(ofs, data) \
24 do { *(volatile u32 *)(marvell_base+(ofs)) = (data); } while (0)
25
26#define MV_READ(ofs) le32_to_cpu(__MV_READ(ofs))
27#define MV_WRITE(ofs, data) __MV_WRITE(ofs, cpu_to_le32(data))
28
29#define MV_READ_16(ofs) \
30 le16_to_cpu(*(volatile u16 *)(marvell_base+(ofs)))
31#define MV_WRITE_16(ofs, data) \
32 *(volatile u16 *)(marvell_base+(ofs)) = cpu_to_le16(data)
33
34#define MV_READ_8(ofs) \
35 *(volatile u8 *)(marvell_base+(ofs))
36#define MV_WRITE_8(ofs, data) \
37 *(volatile u8 *)(marvell_base+(ofs)) = data
38
39#define MV_SET_REG_BITS(ofs, bits) \
40 (*((volatile u32 *)(marvell_base + (ofs)))) |= ((u32)cpu_to_le32(bits))
41#define MV_RESET_REG_BITS(ofs, bits) \
42 (*((volatile u32 *)(marvell_base + (ofs)))) &= ~((u32)cpu_to_le32(bits))
43
44extern struct pci_ops mv_pci_ops;
45
46struct mv_pci_controller {
47 struct pci_controller pcic;
48
49 /*
50 * GT-64240/MV-64340 specific, per host bus information
51 */
52 unsigned long config_addr;
53 unsigned long config_vreg;
54};
55
56extern void ll_mv64340_irq(void);
57extern void mv64340_irq_init(unsigned int base);
58
59#endif /* __ASM_MIPS_MARVELL_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
index 2fbd47eba32d..59c865deb0c7 100644
--- a/include/asm-mips/pgtable-32.h
+++ b/include/asm-mips/pgtable-32.h
@@ -43,11 +43,7 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
43 */ 43 */
44 44
45/* PGDIR_SHIFT determines what a third-level page table entry can map */ 45/* PGDIR_SHIFT determines what a third-level page table entry can map */
46#ifdef CONFIG_64BIT_PHYS_ADDR 46#define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
47#define PGDIR_SHIFT 21
48#else
49#define PGDIR_SHIFT 22
50#endif
51#define PGDIR_SIZE (1UL << PGDIR_SHIFT) 47#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
52#define PGDIR_MASK (~(PGDIR_SIZE-1)) 48#define PGDIR_MASK (~(PGDIR_SIZE-1))
53 49
@@ -55,17 +51,11 @@ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
55 * Entries per page directory level: we use two-level, so 51 * Entries per page directory level: we use two-level, so
56 * we don't really have any PUD/PMD directory physically. 52 * we don't really have any PUD/PMD directory physically.
57 */ 53 */
58#ifdef CONFIG_64BIT_PHYS_ADDR 54#define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
59#define PGD_ORDER 1 55#define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
60#define PUD_ORDER aieeee_attempt_to_allocate_pud 56#define PUD_ORDER aieeee_attempt_to_allocate_pud
61#define PMD_ORDER 1 57#define PMD_ORDER 1
62#define PTE_ORDER 0 58#define PTE_ORDER 0
63#else
64#define PGD_ORDER 0
65#define PUD_ORDER aieeee_attempt_to_allocate_pud
66#define PMD_ORDER 1
67#define PTE_ORDER 0
68#endif
69 59
70#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t)) 60#define PTRS_PER_PGD ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
71#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) 61#define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 2e2d70d13ff6..d2ee28156743 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -168,11 +168,15 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
168#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0) 168#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
169#endif 169#endif
170 170
171#define PGD_T_LOG2 ffz(~sizeof(pgd_t)) 171#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
172#define PMD_T_LOG2 ffz(~sizeof(pmd_t)) 172#define PMD_T_LOG2 (__builtin_ffs(sizeof(pmd_t)) - 1)
173#define PTE_T_LOG2 ffz(~sizeof(pte_t)) 173#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
174 174
175extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; 175/*
176 * We used to declare this array with size but gcc 3.3 and older are not able
177 * to find that this expression is a constant, so the size is dropped.
178 */
179extern pgd_t swapper_pg_dir[];
176 180
177/* 181/*
178 * The following only work if pte_present() is true. 182 * The following only work if pte_present() is true.
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 44dfa4adecf3..ff3e8936b493 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t);
55 55
56#define PARKED_INDEX ((unsigned int)0x80000000) 56#define PARKED_INDEX ((unsigned int)0x80000000)
57 57
58/*
59 * Define low-level interrupt mask for IPIs, if necessary.
60 * By default, use SW interrupt 1, which requires no external
61 * hardware support, but which works only for single-core
62 * MIPS MT systems.
63 */
64#ifndef MIPS_CPU_IPI_IRQ
65#define MIPS_CPU_IPI_IRQ 1
66#endif
67
58#endif /* _ASM_SMTC_MT_H */ 68#endif /* _ASM_SMTC_MT_H */
diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
index 07f873351a86..0bf82818aa53 100644
--- a/include/asm-mips/stacktrace.h
+++ b/include/asm-mips/stacktrace.h
@@ -9,7 +9,11 @@ extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
9 unsigned long pc, unsigned long *ra); 9 unsigned long pc, unsigned long *ra);
10#else 10#else
11#define raw_show_trace 1 11#define raw_show_trace 1
12#define unwind_stack(task, sp, pc, ra) 0 12static inline unsigned long unwind_stack(struct task_struct *task,
13 unsigned long *sp, unsigned long pc, unsigned long *ra)
14{
15 return 0;
16}
13#endif 17#endif
14 18
15static __always_inline void prepare_frametrace(struct pt_regs *regs) 19static __always_inline void prepare_frametrace(struct pt_regs *regs)
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a867774..a60649569c2c 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
50 50
51 51
52#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET) 52#define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
53#define RBTX4927_RTL_8019_IRQ (29) 53#define RBTX4927_RTL_8019_IRQ (TX4927_IRQ_PIC_BEG + 5)
54 54
55int toshiba_rbtx4927_irq_nested(int sw_irq); 55int toshiba_rbtx4927_irq_nested(int sw_irq);
56 56
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
28#define __ASM_TX4927_TX4927_H 28#define __ASM_TX4927_TX4927_H
29 29
30#include <asm/tx4927/tx4927_mips.h> 30#include <asm/tx4927/tx4927_mips.h>
31#include <asm/txx9irq.h>
31 32
32/* 33/*
33 This register naming came from the integrated CPU/controller name TX4927 34 This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
421#define TX4927_PIO_LIMIT 0xf50f 422#define TX4927_PIO_LIMIT 0xf50f
422 423
423 424
424/* TX4927 Interrupt Controller (32-bit registers) */
425#define TX4927_IRC_BASE 0xf510
426#define TX4927_IRC_IRFLAG0 0xf510
427#define TX4927_IRC_IRFLAG1 0xf514
428#define TX4927_IRC_IRPOL 0xf518
429#define TX4927_IRC_IRRCNT 0xf51c
430#define TX4927_IRC_IRMASKINT 0xf520
431#define TX4927_IRC_IRMASKEXT 0xf524
432#define TX4927_IRC_IRDEN 0xf600
433#define TX4927_IRC_IRDM0 0xf604
434#define TX4927_IRC_IRDM1 0xf608
435#define TX4927_IRC_IRLVL0 0xf610
436#define TX4927_IRC_IRLVL1 0xf614
437#define TX4927_IRC_IRLVL2 0xf618
438#define TX4927_IRC_IRLVL3 0xf61c
439#define TX4927_IRC_IRLVL4 0xf620
440#define TX4927_IRC_IRLVL5 0xf624
441#define TX4927_IRC_IRLVL6 0xf628
442#define TX4927_IRC_IRLVL7 0xf62c
443#define TX4927_IRC_IRMSK 0xf640
444#define TX4927_IRC_IREDC 0xf660
445#define TX4927_IRC_IRPND 0xf680
446#define TX4927_IRC_IRCS 0xf6a0
447#define TX4927_IRC_LIMIT 0xf6ff
448
449
450/* TX4927 AC-link controller (32-bit registers) */ 425/* TX4927 AC-link controller (32-bit registers) */
451#define TX4927_ACLC_BASE 0xf700 426#define TX4927_ACLC_BASE 0xf700
452#define TX4927_ACLC_ACCTLEN 0xf700 427#define TX4927_ACLC_ACCTLEN 0xf700
@@ -493,25 +468,11 @@
493#define TX4927_WR( reg, val ) TX4927_WR32( reg, val ) 468#define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
494 469
495 470
471#define TX4927_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
472#define TX4927_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
496 473
497 474#define TX4927_IRQ_PIC_BEG TXX9_IRQ_BASE
498 475#define TX4927_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
499#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */
500#define MI8259_IRQ_ISA_RAW_END 15
501#define TX4927_IRQ_CP0_RAW_BEG 0 /* tx4927 cpu built-in cp0 */
502#define TX4927_IRQ_CP0_RAW_END 7
503#define TX4927_IRQ_PIC_RAW_BEG 0 /* tx4927 cpu build-in pic */
504#define TX4927_IRQ_PIC_RAW_END 31
505
506
507#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */
508#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */
509
510#define TX4927_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG) /* 16 */
511#define TX4927_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END) /* 23 */
512
513#define TX4927_IRQ_PIC_BEG ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG) /* 24 */
514#define TX4927_IRQ_PIC_END ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END) /* 55 */
515 476
516 477
517#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0) 478#define TX4927_IRQ_USER0 (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f41..f98b2bb719d5 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
48#define TX4927_PCI_CLK_ACK 0x04 48#define TX4927_PCI_CLK_ACK 0x04
49#define TX4927_PCI_CLK_ACE 0x02 49#define TX4927_PCI_CLK_ACE 0x02
50#define TX4927_PCI_CLK_ENDIAN 0x01 50#define TX4927_PCI_CLK_ENDIAN 0x01
51#define TX4927_NR_IRQ_LOCAL (8+16) 51#define TX4927_NR_IRQ_LOCAL TX4927_IRQ_PIC_BEG
52#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */ 52#define TX4927_NR_IRQ_IRC 32 /* On-Chip IRC */
53 53
54#define TX4927_IR_PCIC 16 54#define TX4927_IR_PCIC 16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
99 volatile unsigned long long ramp; 99 volatile unsigned long long ramp;
100}; 100};
101 101
102struct tx4927_irc_reg {
103 volatile unsigned long cer;
104 volatile unsigned long cr[2];
105 volatile unsigned long unused0;
106 volatile unsigned long ilr[8];
107 volatile unsigned long unused1[4];
108 volatile unsigned long imr;
109 volatile unsigned long unused2[7];
110 volatile unsigned long scr;
111 volatile unsigned long unused3[7];
112 volatile unsigned long ssr;
113 volatile unsigned long unused4[7];
114 volatile unsigned long csr;
115};
116
117struct tx4927_pcic_reg { 102struct tx4927_pcic_reg {
118 volatile unsigned long pciid; 103 volatile unsigned long pciid;
119 volatile unsigned long pcistatus; 104 volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
182 167
183#endif /* _LANGUAGE_ASSEMBLY */ 168#endif /* _LANGUAGE_ASSEMBLY */
184 169
185/* IRCSR : Int. Current Status */
186#define TX4927_IRCSR_IF 0x00010000
187#define TX4927_IRCSR_ILV_MASK 0x00000700
188#define TX4927_IRCSR_IVL_MASK 0x0000001f
189
190/* 170/*
191 * PCIC 171 * PCIC
192 */ 172 */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
278#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG) 258#define tx4927_pcicptr ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
279#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG) 259#define tx4927_ccfgptr ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
280#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG) 260#define tx4927_ebuscptr ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
281#define tx4927_ircptr ((struct tx4927_irc_reg *)TX4927_IRC_REG)
282 261
283#endif /* _LANGUAGE_ASSEMBLY */ 262#endif /* _LANGUAGE_ASSEMBLY */
284 263
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 74e7d8061e58..b14acb575be2 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -14,6 +14,7 @@
14 14
15#include <asm/addrspace.h> 15#include <asm/addrspace.h>
16#include <asm/tx4938/tx4938.h> 16#include <asm/tx4938/tx4938.h>
17#include <asm/txx9irq.h>
17 18
18/* CS */ 19/* CS */
19#define RBTX4938_CE0 0x1c000000 /* 64M */ 20#define RBTX4938_CE0 0x1c000000 /* 64M */
@@ -123,21 +124,11 @@
123#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */ 124#define RBTX4938_NR_IRQ_IRC 32 /* On-Chip IRC */
124#define RBTX4938_NR_IRQ_IOC 8 125#define RBTX4938_NR_IRQ_IOC 8
125 126
126#define MI8259_IRQ_ISA_RAW_BEG 0 /* optional backplane i8259 */ 127#define TX4938_IRQ_CP0_BEG MIPS_CPU_IRQ_BASE
127#define MI8259_IRQ_ISA_RAW_END 15 128#define TX4938_IRQ_CP0_END (MIPS_CPU_IRQ_BASE + 8 - 1)
128#define TX4938_IRQ_CP0_RAW_BEG 0 /* tx4938 cpu built-in cp0 */
129#define TX4938_IRQ_CP0_RAW_END 7
130#define TX4938_IRQ_PIC_RAW_BEG 0 /* tx4938 cpu build-in pic */
131#define TX4938_IRQ_PIC_RAW_END 31
132 129
133#define MI8259_IRQ_ISA_BEG MI8259_IRQ_ISA_RAW_BEG /* 0 */ 130#define TX4938_IRQ_PIC_BEG TXX9_IRQ_BASE
134#define MI8259_IRQ_ISA_END MI8259_IRQ_ISA_RAW_END /* 15 */ 131#define TX4938_IRQ_PIC_END (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
135
136#define TX4938_IRQ_CP0_BEG ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG) /* 16 */
137#define TX4938_IRQ_CP0_END ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END) /* 23 */
138
139#define TX4938_IRQ_PIC_BEG ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG) /* 24 */
140#define TX4938_IRQ_PIC_END ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END) /* 55 */
141#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2) 132#define TX4938_IRQ_NEST_EXT_ON_PIC (TX4938_IRQ_PIC_BEG+2)
142#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2) 133#define TX4938_IRQ_NEST_PIC_ON_CP0 (TX4938_IRQ_CP0_BEG+2)
143#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0) 134#define TX4938_IRQ_USER0 (TX4938_IRQ_CP0_BEG+0)
@@ -192,10 +183,4 @@
192#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base) 183#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
193#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER) 184#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
194 185
195/* IRCR : Int. Control */
196#define TX4938_IRCR_LOW 0x00000000
197#define TX4938_IRCR_HIGH 0x00000001
198#define TX4938_IRCR_DOWN 0x00000002
199#define TX4938_IRCR_UP 0x00000003
200
201#endif /* __ASM_TX_BOARDS_RBTX4938_H */ 186#endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index e25b1a0975cb..afdb19813ca1 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -272,20 +272,6 @@ struct tx4938_pio_reg {
272 volatile unsigned long maskcpu; 272 volatile unsigned long maskcpu;
273 volatile unsigned long maskext; 273 volatile unsigned long maskext;
274}; 274};
275struct tx4938_irc_reg {
276 volatile unsigned long cer;
277 volatile unsigned long cr[2];
278 volatile unsigned long unused0;
279 volatile unsigned long ilr[8];
280 volatile unsigned long unused1[4];
281 volatile unsigned long imr;
282 volatile unsigned long unused2[7];
283 volatile unsigned long scr;
284 volatile unsigned long unused3[7];
285 volatile unsigned long ssr;
286 volatile unsigned long unused4[7];
287 volatile unsigned long csr;
288};
289 275
290struct tx4938_ndfmc_reg { 276struct tx4938_ndfmc_reg {
291 endian_def_l2(unused0, dtr); 277 endian_def_l2(unused0, dtr);
@@ -646,39 +632,12 @@ struct tx4938_ccfg_reg {
646#define TX4938_DMA_CSR_DESERR 0x00000002 632#define TX4938_DMA_CSR_DESERR 0x00000002
647#define TX4938_DMA_CSR_SORERR 0x00000001 633#define TX4938_DMA_CSR_SORERR 0x00000001
648 634
649/* TX4938 Interrupt Controller (32-bit registers) */
650#define TX4938_IRC_BASE 0xf510
651#define TX4938_IRC_IRFLAG0 0xf510
652#define TX4938_IRC_IRFLAG1 0xf514
653#define TX4938_IRC_IRPOL 0xf518
654#define TX4938_IRC_IRRCNT 0xf51c
655#define TX4938_IRC_IRMASKINT 0xf520
656#define TX4938_IRC_IRMASKEXT 0xf524
657#define TX4938_IRC_IRDEN 0xf600
658#define TX4938_IRC_IRDM0 0xf604
659#define TX4938_IRC_IRDM1 0xf608
660#define TX4938_IRC_IRLVL0 0xf610
661#define TX4938_IRC_IRLVL1 0xf614
662#define TX4938_IRC_IRLVL2 0xf618
663#define TX4938_IRC_IRLVL3 0xf61c
664#define TX4938_IRC_IRLVL4 0xf620
665#define TX4938_IRC_IRLVL5 0xf624
666#define TX4938_IRC_IRLVL6 0xf628
667#define TX4938_IRC_IRLVL7 0xf62c
668#define TX4938_IRC_IRMSK 0xf640
669#define TX4938_IRC_IREDC 0xf660
670#define TX4938_IRC_IRPND 0xf680
671#define TX4938_IRC_IRCS 0xf6a0
672#define TX4938_IRC_LIMIT 0xf6ff
673
674
675#ifndef __ASSEMBLY__ 635#ifndef __ASSEMBLY__
676 636
677#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG) 637#define tx4938_sdramcptr ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
678#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG) 638#define tx4938_ebuscptr ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
679#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch)) 639#define tx4938_dmaptr(ch) ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
680#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG) 640#define tx4938_ndfmcptr ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
681#define tx4938_ircptr ((struct tx4938_irc_reg *)TX4938_IRC_REG)
682#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) 641#define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
683#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) 642#define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
684#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) 643#define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
new file mode 100644
index 000000000000..1c439e51b875
--- /dev/null
+++ b/include/asm-mips/txx9irq.h
@@ -0,0 +1,30 @@
1/*
2 * include/asm-mips/txx9irq.h
3 * TX39/TX49 interrupt controller definitions.
4 *
5 * This file is subject to the terms and conditions of the GNU General Public
6 * License. See the file "COPYING" in the main directory of this archive
7 * for more details.
8 */
9#ifndef __ASM_TXX9IRQ_H
10#define __ASM_TXX9IRQ_H
11
12#include <irq.h>
13
14#ifdef CONFIG_IRQ_CPU
15#define TXX9_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
16#else
17#define TXX9_IRQ_BASE 0
18#endif
19
20#ifdef CONFIG_CPU_TX39XX
21#define TXx9_MAX_IR 16
22#else
23#define TXx9_MAX_IR 32
24#endif
25
26void txx9_irq_init(unsigned long baseaddr);
27int txx9_irq(void);
28int txx9_irq_set_pri(int irc_irq, int new_pri);
29
30#endif /* __ASM_TXX9IRQ_H */
diff --git a/include/asm-parisc/io.h b/include/asm-parisc/io.h
index c0fed91da3a2..4cc9bcec0564 100644
--- a/include/asm-parisc/io.h
+++ b/include/asm-parisc/io.h
@@ -15,6 +15,16 @@ extern unsigned long parisc_vmerge_max_size;
15#define virt_to_bus virt_to_phys 15#define virt_to_bus virt_to_phys
16#define bus_to_virt phys_to_virt 16#define bus_to_virt phys_to_virt
17 17
18static inline unsigned long isa_bus_to_virt(unsigned long addr) {
19 BUG();
20 return 0;
21}
22
23static inline unsigned long isa_virt_to_bus(void *addr) {
24 BUG();
25 return 0;
26}
27
18/* 28/*
19 * Memory mapped I/O 29 * Memory mapped I/O
20 * 30 *
diff --git a/include/asm-parisc/vga.h b/include/asm-parisc/vga.h
new file mode 100644
index 000000000000..154a84c843a7
--- /dev/null
+++ b/include/asm-parisc/vga.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_PARISC_VGA_H__
2#define __ASM_PARISC_VGA_H__
3
4/* nothing */
5
6#endif __ASM_PARISC_VGA_H__
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 064405c207bf..8fdc2b47afb9 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -223,7 +223,6 @@
223#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ 223#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
224#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ 224#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
225#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ 225#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
226#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
227#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ 226#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
228#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ 227#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
229#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ 228#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
@@ -232,6 +231,12 @@
232#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ 231#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
233#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 232#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
234#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 233#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
234
235/* e500 parts may set unused bits in MCSR; mask these off */
236#define MCSR_MASK (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
237 MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
238 MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
239 MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
235#endif 240#endif
236#ifdef CONFIG_E200 241#ifdef CONFIG_E200
237#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ 242#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
@@ -243,6 +248,11 @@
243#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ 248#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
244#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered 249#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
245 store or cache line push */ 250 store or cache line push */
251
252/* e200 parts may set unused bits in MCSR; mask these off */
253#define MCSR_MASK (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
254 MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
255 MCSR_BUS_WRERR)
246#endif 256#endif
247 257
248/* Bit definitions for the DBSR. */ 258/* Bit definitions for the DBSR. */
diff --git a/include/asm-s390/atomic.h b/include/asm-s390/atomic.h
index ea486952f778..2d184655bc5d 100644
--- a/include/asm-s390/atomic.h
+++ b/include/asm-s390/atomic.h
@@ -67,8 +67,17 @@ typedef struct {
67 67
68#endif /* __GNUC__ */ 68#endif /* __GNUC__ */
69 69
70#define atomic_read(v) ((v)->counter) 70static inline int atomic_read(const atomic_t *v)
71#define atomic_set(v,i) (((v)->counter) = (i)) 71{
72 barrier();
73 return v->counter;
74}
75
76static inline void atomic_set(atomic_t *v, int i)
77{
78 v->counter = i;
79 barrier();
80}
72 81
73static __inline__ int atomic_add_return(int i, atomic_t * v) 82static __inline__ int atomic_add_return(int i, atomic_t * v)
74{ 83{
@@ -182,8 +191,17 @@ typedef struct {
182 191
183#endif /* __GNUC__ */ 192#endif /* __GNUC__ */
184 193
185#define atomic64_read(v) ((v)->counter) 194static inline long long atomic64_read(const atomic64_t *v)
186#define atomic64_set(v,i) (((v)->counter) = (i)) 195{
196 barrier();
197 return v->counter;
198}
199
200static inline void atomic64_set(atomic64_t *v, long long i)
201{
202 v->counter = i;
203 barrier();
204}
187 205
188static __inline__ long long atomic64_add_return(long long i, atomic64_t * v) 206static __inline__ long long atomic64_add_return(long long i, atomic64_t * v)
189{ 207{
diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h
index f738d2827582..1982fb344164 100644
--- a/include/asm-s390/cio.h
+++ b/include/asm-s390/cio.h
@@ -258,19 +258,6 @@ struct ciw {
258/* Sick revalidation of device. */ 258/* Sick revalidation of device. */
259#define CIO_REVALIDATE 0x0008 259#define CIO_REVALIDATE 0x0008
260 260
261struct diag210 {
262 __u16 vrdcdvno : 16; /* device number (input) */
263 __u16 vrdclen : 16; /* data block length (input) */
264 __u32 vrdcvcla : 8; /* virtual device class (output) */
265 __u32 vrdcvtyp : 8; /* virtual device type (output) */
266 __u32 vrdcvsta : 8; /* virtual device status (output) */
267 __u32 vrdcvfla : 8; /* virtual device flags (output) */
268 __u32 vrdcrccl : 8; /* real device class (output) */
269 __u32 vrdccrty : 8; /* real device type (output) */
270 __u32 vrdccrmd : 8; /* real device model (output) */
271 __u32 vrdccrft : 8; /* real device feature (output) */
272} __attribute__ ((packed,aligned(4)));
273
274struct ccw_dev_id { 261struct ccw_dev_id {
275 u8 ssid; 262 u8 ssid;
276 u16 devno; 263 u16 devno;
@@ -285,8 +272,6 @@ static inline int ccw_dev_id_is_equal(struct ccw_dev_id *dev_id1,
285 return 0; 272 return 0;
286} 273}
287 274
288extern int diag210(struct diag210 *addr);
289
290extern void wait_cons_dev(void); 275extern void wait_cons_dev(void);
291 276
292extern void css_schedule_reprobe(void); 277extern void css_schedule_reprobe(void);
diff --git a/include/asm-s390/diag.h b/include/asm-s390/diag.h
new file mode 100644
index 000000000000..72b2e2f2d32d
--- /dev/null
+++ b/include/asm-s390/diag.h
@@ -0,0 +1,39 @@
1/*
2 * s390 diagnose functions
3 *
4 * Copyright IBM Corp. 2007
5 * Author(s): Michael Holzheu <holzheu@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_DIAG_H
9#define _ASM_S390_DIAG_H
10
11/*
12 * Diagnose 10: Release pages
13 */
14extern void diag10(unsigned long addr);
15
16/*
17 * Diagnose 14: Input spool file manipulation
18 */
19extern int diag14(unsigned long rx, unsigned long ry1, unsigned long subcode);
20
21/*
22 * Diagnose 210: Get information about a virtual device
23 */
24struct diag210 {
25 u16 vrdcdvno; /* device number (input) */
26 u16 vrdclen; /* data block length (input) */
27 u8 vrdcvcla; /* virtual device class (output) */
28 u8 vrdcvtyp; /* virtual device type (output) */
29 u8 vrdcvsta; /* virtual device status (output) */
30 u8 vrdcvfla; /* virtual device flags (output) */
31 u8 vrdcrccl; /* real device class (output) */
32 u8 vrdccrty; /* real device type (output) */
33 u8 vrdccrmd; /* real device model (output) */
34 u8 vrdccrft; /* real device feature (output) */
35} __attribute__((packed, aligned(4)));
36
37extern int diag210(struct diag210 *addr);
38
39#endif /* _ASM_S390_DIAG_H */
diff --git a/include/asm-s390/pgalloc.h b/include/asm-s390/pgalloc.h
index 56c8a6c80e2e..e45d3c9a4b7e 100644
--- a/include/asm-s390/pgalloc.h
+++ b/include/asm-s390/pgalloc.h
@@ -19,8 +19,6 @@
19 19
20#define check_pgt_cache() do {} while (0) 20#define check_pgt_cache() do {} while (0)
21 21
22extern void diag10(unsigned long addr);
23
24/* 22/*
25 * Page allocation orders. 23 * Page allocation orders.
26 */ 24 */
diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h
index 6f492ac3fa13..84fefdaa01a5 100644
--- a/include/asm-sh/dma-mapping.h
+++ b/include/asm-sh/dma-mapping.h
@@ -160,6 +160,25 @@ static inline void dma_sync_single_for_device(struct device *dev,
160 dma_sync_single(dev, dma_handle, size, dir); 160 dma_sync_single(dev, dma_handle, size, dir);
161} 161}
162 162
163static inline void dma_sync_single_range_for_cpu(struct device *dev,
164 dma_addr_t dma_handle,
165 unsigned long offset,
166 size_t size,
167 enum dma_data_direction direction)
168{
169 dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
170}
171
172static inline void dma_sync_single_range_for_device(struct device *dev,
173 dma_addr_t dma_handle,
174 unsigned long offset,
175 size_t size,
176 enum dma_data_direction direction)
177{
178 dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
179}
180
181
163static inline void dma_sync_sg_for_cpu(struct device *dev, 182static inline void dma_sync_sg_for_cpu(struct device *dev,
164 struct scatterlist *sg, int nelems, 183 struct scatterlist *sg, int nelems,
165 enum dma_data_direction dir) 184 enum dma_data_direction dir)
diff --git a/include/asm-sh64/dma-mapping.h b/include/asm-sh64/dma-mapping.h
index d505f357f819..de4309960207 100644
--- a/include/asm-sh64/dma-mapping.h
+++ b/include/asm-sh64/dma-mapping.h
@@ -141,6 +141,24 @@ static inline void dma_sync_single_for_device(struct device *dev,
141 dma_sync_single(dev, dma_handle, size, dir); 141 dma_sync_single(dev, dma_handle, size, dir);
142} 142}
143 143
144static inline void dma_sync_single_range_for_cpu(struct device *dev,
145 dma_addr_t dma_handle,
146 unsigned long offset,
147 size_t size,
148 enum dma_data_direction direction)
149{
150 dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
151}
152
153static inline void dma_sync_single_range_for_device(struct device *dev,
154 dma_addr_t dma_handle,
155 unsigned long offset,
156 size_t size,
157 enum dma_data_direction direction)
158{
159 dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
160}
161
144static inline void dma_sync_sg_for_cpu(struct device *dev, 162static inline void dma_sync_sg_for_cpu(struct device *dev,
145 struct scatterlist *sg, int nelems, 163 struct scatterlist *sg, int nelems,
146 enum dma_data_direction dir) 164 enum dma_data_direction dir)
diff --git a/include/asm-sparc/sbus.h b/include/asm-sparc/sbus.h
index d036e4419d79..27d076c46964 100644
--- a/include/asm-sparc/sbus.h
+++ b/include/asm-sparc/sbus.h
@@ -68,7 +68,6 @@ struct sbus_dev {
68/* This struct describes the SBus(s) found on this machine. */ 68/* This struct describes the SBus(s) found on this machine. */
69struct sbus_bus { 69struct sbus_bus {
70 struct of_device ofdev; 70 struct of_device ofdev;
71 void *iommu; /* Opaque IOMMU cookie */
72 struct sbus_dev *devices; /* Link to devices on this SBus */ 71 struct sbus_dev *devices; /* Link to devices on this SBus */
73 struct sbus_bus *next; /* next SBus, if more than one SBus */ 72 struct sbus_bus *next; /* next SBus, if more than one SBus */
74 int prom_node; /* PROM device tree node for this SBus */ 73 int prom_node; /* PROM device tree node for this SBus */
diff --git a/include/asm-sparc/sfp-machine.h b/include/asm-sparc/sfp-machine.h
index ecfc86a4a725..266a42b8f99f 100644
--- a/include/asm-sparc/sfp-machine.h
+++ b/include/asm-sparc/sfp-machine.h
@@ -203,4 +203,10 @@ extern struct task_struct *last_task_used_math;
203#define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex) 203#define FP_INHIBIT_RESULTS ((last_task_used_math->thread.fsr >> 23) & _fex)
204#endif 204#endif
205 205
206#ifdef CONFIG_SMP
207#define FP_TRAPPING_EXCEPTIONS ((current->thread.fsr >> 23) & 0x1f)
208#else
209#define FP_TRAPPING_EXCEPTIONS ((last_task_used_math->thread.fsr >> 23) & 0x1f)
210#endif
211
206#endif 212#endif
diff --git a/include/asm-sparc/tlbflush.h b/include/asm-sparc/tlbflush.h
index 4a3b66618e75..a619da5cfaa9 100644
--- a/include/asm-sparc/tlbflush.h
+++ b/include/asm-sparc/tlbflush.h
@@ -57,6 +57,10 @@ BTFIXUPDEF_CALL(void, flush_tlb_page, struct vm_area_struct *, unsigned long)
57/* 57/*
58 * This is a kludge, until I know better. --zaitcev XXX 58 * This is a kludge, until I know better. --zaitcev XXX
59 */ 59 */
60#define flush_tlb_kernel_range(start, end) flush_tlb_all() 60static inline void flush_tlb_kernel_range(unsigned long start,
61 unsigned long end)
62{
63 flush_tlb_all();
64}
61 65
62#endif /* _SPARC_TLBFLUSH_H */ 66#endif /* _SPARC_TLBFLUSH_H */
diff --git a/include/asm-sparc64/elf.h b/include/asm-sparc64/elf.h
index 303d85e2f82e..8653e8665009 100644
--- a/include/asm-sparc64/elf.h
+++ b/include/asm-sparc64/elf.h
@@ -70,6 +70,7 @@
70#define HWCAP_SPARC_V9 16 70#define HWCAP_SPARC_V9 16
71#define HWCAP_SPARC_ULTRA3 32 71#define HWCAP_SPARC_ULTRA3 32
72#define HWCAP_SPARC_BLKINIT 64 72#define HWCAP_SPARC_BLKINIT 64
73#define HWCAP_SPARC_N2 128
73 74
74/* 75/*
75 * These are used to set parameters in the core dumps. 76 * These are used to set parameters in the core dumps.
@@ -155,8 +156,13 @@ static inline unsigned int sparc64_elf_hwcap(void)
155 156
156 if (tlb_type == cheetah || tlb_type == cheetah_plus) 157 if (tlb_type == cheetah || tlb_type == cheetah_plus)
157 cap |= HWCAP_SPARC_ULTRA3; 158 cap |= HWCAP_SPARC_ULTRA3;
158 else if (tlb_type == hypervisor) 159 else if (tlb_type == hypervisor) {
159 cap |= HWCAP_SPARC_BLKINIT; 160 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
161 sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
162 cap |= HWCAP_SPARC_BLKINIT;
163 if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2)
164 cap |= HWCAP_SPARC_N2;
165 }
160 166
161 return cap; 167 return cap;
162} 168}
diff --git a/include/asm-sparc64/percpu.h b/include/asm-sparc64/percpu.h
index caf8750792ff..a1f53a4da405 100644
--- a/include/asm-sparc64/percpu.h
+++ b/include/asm-sparc64/percpu.h
@@ -3,6 +3,8 @@
3 3
4#include <linux/compiler.h> 4#include <linux/compiler.h>
5 5
6register unsigned long __local_per_cpu_offset asm("g5");
7
6#ifdef CONFIG_SMP 8#ifdef CONFIG_SMP
7 9
8#define setup_per_cpu_areas() do { } while (0) 10#define setup_per_cpu_areas() do { } while (0)
@@ -23,8 +25,6 @@ extern unsigned long __per_cpu_shift;
23 __typeof__(type) per_cpu__##name \ 25 __typeof__(type) per_cpu__##name \
24 ____cacheline_aligned_in_smp 26 ____cacheline_aligned_in_smp
25 27
26register unsigned long __local_per_cpu_offset asm("g5");
27
28/* var is in discarded region: offset to particular copy we want */ 28/* var is in discarded region: offset to particular copy we want */
29#define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu))) 29#define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu)))
30#define __get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __local_per_cpu_offset)) 30#define __get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __local_per_cpu_offset))
diff --git a/include/asm-sparc64/sfp-machine.h b/include/asm-sparc64/sfp-machine.h
index 89d42431efb5..c9331b02d9c8 100644
--- a/include/asm-sparc64/sfp-machine.h
+++ b/include/asm-sparc64/sfp-machine.h
@@ -88,4 +88,6 @@
88 88
89#define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex) 89#define FP_INHIBIT_RESULTS ((current_thread_info()->xfsr[0] >> 23) & _fex)
90 90
91#define FP_TRAPPING_EXCEPTIONS ((current_thread_info()->xfsr[0] >> 23) & 0x1f)
92
91#endif 93#endif
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index 64891cb10f05..3f175fa7e6d2 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -141,7 +141,6 @@ do { \
141 * not preserve it's value. Hairy, but it lets us remove 2 loads 141 * not preserve it's value. Hairy, but it lets us remove 2 loads
142 * and 2 stores in this critical code path. -DaveM 142 * and 2 stores in this critical code path. -DaveM
143 */ 143 */
144#define EXTRA_CLOBBER ,"%l1"
145#define switch_to(prev, next, last) \ 144#define switch_to(prev, next, last) \
146do { if (test_thread_flag(TIF_PERFCTR)) { \ 145do { if (test_thread_flag(TIF_PERFCTR)) { \
147 unsigned long __tmp; \ 146 unsigned long __tmp; \
@@ -164,33 +163,34 @@ do { if (test_thread_flag(TIF_PERFCTR)) { \
164 "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \ 163 "stx %%i6, [%%sp + 2047 + 0x70]\n\t" \
165 "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \ 164 "stx %%i7, [%%sp + 2047 + 0x78]\n\t" \
166 "rdpr %%wstate, %%o5\n\t" \ 165 "rdpr %%wstate, %%o5\n\t" \
167 "stx %%o6, [%%g6 + %3]\n\t" \ 166 "stx %%o6, [%%g6 + %6]\n\t" \
168 "stb %%o5, [%%g6 + %2]\n\t" \
169 "rdpr %%cwp, %%o5\n\t" \
170 "stb %%o5, [%%g6 + %5]\n\t" \ 167 "stb %%o5, [%%g6 + %5]\n\t" \
171 "mov %1, %%g6\n\t" \ 168 "rdpr %%cwp, %%o5\n\t" \
172 "ldub [%1 + %5], %%g1\n\t" \ 169 "stb %%o5, [%%g6 + %8]\n\t" \
170 "mov %4, %%g6\n\t" \
171 "ldub [%4 + %8], %%g1\n\t" \
173 "wrpr %%g1, %%cwp\n\t" \ 172 "wrpr %%g1, %%cwp\n\t" \
174 "ldx [%%g6 + %3], %%o6\n\t" \ 173 "ldx [%%g6 + %6], %%o6\n\t" \
175 "ldub [%%g6 + %2], %%o5\n\t" \ 174 "ldub [%%g6 + %5], %%o5\n\t" \
176 "ldub [%%g6 + %4], %%o7\n\t" \ 175 "ldub [%%g6 + %7], %%o7\n\t" \
177 "wrpr %%o5, 0x0, %%wstate\n\t" \ 176 "wrpr %%o5, 0x0, %%wstate\n\t" \
178 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \ 177 "ldx [%%sp + 2047 + 0x70], %%i6\n\t" \
179 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \ 178 "ldx [%%sp + 2047 + 0x78], %%i7\n\t" \
180 "ldx [%%g6 + %6], %%g4\n\t" \ 179 "ldx [%%g6 + %9], %%g4\n\t" \
181 "brz,pt %%o7, 1f\n\t" \ 180 "brz,pt %%o7, 1f\n\t" \
182 " mov %%g7, %0\n\t" \ 181 " mov %%g7, %0\n\t" \
183 "b,a ret_from_syscall\n\t" \ 182 "b,a ret_from_syscall\n\t" \
184 "1:\n\t" \ 183 "1:\n\t" \
185 : "=&r" (last) \ 184 : "=&r" (last), "=r" (current), "=r" (current_thread_info_reg), \
185 "=r" (__local_per_cpu_offset) \
186 : "0" (task_thread_info(next)), \ 186 : "0" (task_thread_info(next)), \
187 "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \ 187 "i" (TI_WSTATE), "i" (TI_KSP), "i" (TI_NEW_CHILD), \
188 "i" (TI_CWP), "i" (TI_TASK) \ 188 "i" (TI_CWP), "i" (TI_TASK) \
189 : "cc", \ 189 : "cc", \
190 "g1", "g2", "g3", "g7", \ 190 "g1", "g2", "g3", "g7", \
191 "l2", "l3", "l4", "l5", "l6", "l7", \ 191 "l1", "l2", "l3", "l4", "l5", "l6", "l7", \
192 "i0", "i1", "i2", "i3", "i4", "i5", \ 192 "i0", "i1", "i2", "i3", "i4", "i5", \
193 "o0", "o1", "o2", "o3", "o4", "o5", "o7" EXTRA_CLOBBER);\ 193 "o0", "o1", "o2", "o3", "o4", "o5", "o7"); \
194 /* If you fuck with this, update ret_from_syscall code too. */ \ 194 /* If you fuck with this, update ret_from_syscall code too. */ \
195 if (test_thread_flag(TIF_PERFCTR)) { \ 195 if (test_thread_flag(TIF_PERFCTR)) { \
196 write_pcr(current_thread_info()->pcr_reg); \ 196 write_pcr(current_thread_info()->pcr_reg); \
diff --git a/include/asm-x86_64/io_apic.h b/include/asm-x86_64/io_apic.h
index 969d225a9350..d9f2e54324d5 100644
--- a/include/asm-x86_64/io_apic.h
+++ b/include/asm-x86_64/io_apic.h
@@ -109,6 +109,12 @@ extern int mpc_default_type;
109/* 1 if "noapic" boot option passed */ 109/* 1 if "noapic" boot option passed */
110extern int skip_ioapic_setup; 110extern int skip_ioapic_setup;
111 111
112static inline void disable_ioapic_setup(void)
113{
114 skip_ioapic_setup = 1;
115}
116
117
112/* 118/*
113 * If we use the IO-APIC for IRQ routing, disable automatic 119 * If we use the IO-APIC for IRQ routing, disable automatic
114 * assignment of PCI IRQ's. 120 * assignment of PCI IRQ's.
diff --git a/include/asm-x86_64/nmi.h b/include/asm-x86_64/nmi.h
index 5fb3c0de5ccc..65b6acf3bb59 100644
--- a/include/asm-x86_64/nmi.h
+++ b/include/asm-x86_64/nmi.h
@@ -64,11 +64,12 @@ extern int setup_nmi_watchdog(char *);
64 64
65extern atomic_t nmi_active; 65extern atomic_t nmi_active;
66extern unsigned int nmi_watchdog; 66extern unsigned int nmi_watchdog;
67#define NMI_DEFAULT -1 67#define NMI_DISABLED -1
68#define NMI_NONE 0 68#define NMI_NONE 0
69#define NMI_IO_APIC 1 69#define NMI_IO_APIC 1
70#define NMI_LOCAL_APIC 2 70#define NMI_LOCAL_APIC 2
71#define NMI_INVALID 3 71#define NMI_INVALID 3
72#define NMI_DEFAULT NMI_DISABLED
72 73
73struct ctl_table; 74struct ctl_table;
74struct file; 75struct file;
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index ad7f71a81b0a..818cc3a50e6b 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -7,6 +7,7 @@ header-y += raid/
7header-y += spi/ 7header-y += spi/
8header-y += sunrpc/ 8header-y += sunrpc/
9header-y += tc_act/ 9header-y += tc_act/
10header-y += tc_ematch/
10header-y += netfilter/ 11header-y += netfilter/
11header-y += netfilter_arp/ 12header-y += netfilter_arp/
12header-y += netfilter_bridge/ 13header-y += netfilter_bridge/
diff --git a/include/linux/audit.h b/include/linux/audit.h
index 4bbd8601b8f0..d6579df8dadf 100644
--- a/include/linux/audit.h
+++ b/include/linux/audit.h
@@ -63,8 +63,8 @@
63#define AUDIT_ADD_RULE 1011 /* Add syscall filtering rule */ 63#define AUDIT_ADD_RULE 1011 /* Add syscall filtering rule */
64#define AUDIT_DEL_RULE 1012 /* Delete syscall filtering rule */ 64#define AUDIT_DEL_RULE 1012 /* Delete syscall filtering rule */
65#define AUDIT_LIST_RULES 1013 /* List syscall filtering rules */ 65#define AUDIT_LIST_RULES 1013 /* List syscall filtering rules */
66#define AUDIT_TTY_GET 1014 /* Get TTY auditing status */ 66#define AUDIT_TTY_GET 1016 /* Get TTY auditing status */
67#define AUDIT_TTY_SET 1015 /* Set TTY auditing status */ 67#define AUDIT_TTY_SET 1017 /* Set TTY auditing status */
68 68
69#define AUDIT_FIRST_USER_MSG 1100 /* Userspace messages mostly uninteresting to kernel */ 69#define AUDIT_FIRST_USER_MSG 1100 /* Userspace messages mostly uninteresting to kernel */
70#define AUDIT_USER_AVC 1107 /* We filter this differently */ 70#define AUDIT_USER_AVC 1107 /* We filter this differently */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index d71d0121b7f9..c792b4fd1588 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -1285,13 +1285,14 @@ void ide_init_sg_cmd(ide_drive_t *, struct request *);
1285#define BAD_DMA_DRIVE 0 1285#define BAD_DMA_DRIVE 0
1286#define GOOD_DMA_DRIVE 1 1286#define GOOD_DMA_DRIVE 1
1287 1287
1288#ifdef CONFIG_BLK_DEV_IDEDMA
1289struct drive_list_entry { 1288struct drive_list_entry {
1290 const char *id_model; 1289 const char *id_model;
1291 const char *id_firmware; 1290 const char *id_firmware;
1292}; 1291};
1293 1292
1294int ide_in_drive_list(struct hd_driveid *, const struct drive_list_entry *); 1293int ide_in_drive_list(struct hd_driveid *, const struct drive_list_entry *);
1294
1295#ifdef CONFIG_BLK_DEV_IDEDMA
1295int __ide_dma_bad_drive(ide_drive_t *); 1296int __ide_dma_bad_drive(ide_drive_t *);
1296int __ide_dma_good_drive(ide_drive_t *); 1297int __ide_dma_good_drive(ide_drive_t *);
1297u8 ide_max_dma_mode(ide_drive_t *); 1298u8 ide_max_dma_mode(ide_drive_t *);
@@ -1312,7 +1313,6 @@ void ide_dma_host_off(ide_drive_t *);
1312void ide_dma_off_quietly(ide_drive_t *); 1313void ide_dma_off_quietly(ide_drive_t *);
1313void ide_dma_host_on(ide_drive_t *); 1314void ide_dma_host_on(ide_drive_t *);
1314extern int __ide_dma_on(ide_drive_t *); 1315extern int __ide_dma_on(ide_drive_t *);
1315extern int __ide_dma_check(ide_drive_t *);
1316extern int ide_dma_setup(ide_drive_t *); 1316extern int ide_dma_setup(ide_drive_t *);
1317extern void ide_dma_start(ide_drive_t *); 1317extern void ide_dma_start(ide_drive_t *);
1318extern int __ide_dma_end(ide_drive_t *); 1318extern int __ide_dma_end(ide_drive_t *);
diff --git a/include/linux/if_pppol2tp.h b/include/linux/if_pppol2tp.h
index 516203b6fdeb..a7d6a2234b31 100644
--- a/include/linux/if_pppol2tp.h
+++ b/include/linux/if_pppol2tp.h
@@ -32,8 +32,8 @@ struct pppol2tp_addr
32 32
33 struct sockaddr_in addr; /* IP address and port to send to */ 33 struct sockaddr_in addr; /* IP address and port to send to */
34 34
35 __be16 s_tunnel, s_session; /* For matching incoming packets */ 35 __u16 s_tunnel, s_session; /* For matching incoming packets */
36 __be16 d_tunnel, d_session; /* For sending outgoing packets */ 36 __u16 d_tunnel, d_session; /* For sending outgoing packets */
37}; 37};
38 38
39/* Socket options: 39/* Socket options:
diff --git a/include/linux/input.h b/include/linux/input.h
index e02c6a66b2ba..cf2b5619aa13 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -363,6 +363,12 @@ struct input_absinfo {
363 363
364#define KEY_UNKNOWN 240 364#define KEY_UNKNOWN 240
365 365
366#define KEY_VIDEO_NEXT 241 /* drive next video source */
367#define KEY_VIDEO_PREV 242 /* drive previous video source */
368#define KEY_BRIGHTNESS_CYCLE 243 /* brightness up, after max is min */
369#define KEY_BRIGHTNESS_ZERO 244 /* brightness off, use ambient */
370#define KEY_DISPLAY_OFF 245 /* display device to off state */
371
366#define BTN_MISC 0x100 372#define BTN_MISC 0x100
367#define BTN_0 0x100 373#define BTN_0 0x100
368#define BTN_1 0x101 374#define BTN_1 0x101
diff --git a/include/linux/kbd_kern.h b/include/linux/kbd_kern.h
index 506ad20c18f8..8bdb16bfe5fb 100644
--- a/include/linux/kbd_kern.h
+++ b/include/linux/kbd_kern.h
@@ -161,4 +161,7 @@ static inline void con_schedule_flip(struct tty_struct *t)
161 schedule_delayed_work(&t->buf.work, 0); 161 schedule_delayed_work(&t->buf.work, 0);
162} 162}
163 163
164/* mac_hid.c */
165extern int mac_hid_mouse_emulate_buttons(int, unsigned int, int);
166
164#endif 167#endif
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index e147cf50529f..5bdd656e88cf 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -166,7 +166,7 @@ extern enum zone_type policy_zone;
166 166
167static inline void check_highest_zone(enum zone_type k) 167static inline void check_highest_zone(enum zone_type k)
168{ 168{
169 if (k > policy_zone) 169 if (k > policy_zone && k != ZONE_MOVABLE)
170 policy_zone = k; 170 policy_zone = k;
171} 171}
172 172
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 655094dc9440..1692dd6cb915 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -1042,7 +1042,7 @@ static inline void vma_nonlinear_insert(struct vm_area_struct *vma,
1042} 1042}
1043 1043
1044/* mmap.c */ 1044/* mmap.c */
1045extern int __vm_enough_memory(long pages, int cap_sys_admin); 1045extern int __vm_enough_memory(struct mm_struct *mm, long pages, int cap_sys_admin);
1046extern void vma_adjust(struct vm_area_struct *vma, unsigned long start, 1046extern void vma_adjust(struct vm_area_struct *vma, unsigned long start,
1047 unsigned long end, pgoff_t pgoff, struct vm_area_struct *insert); 1047 unsigned long end, pgoff_t pgoff, struct vm_area_struct *insert);
1048extern struct vm_area_struct *vma_merge(struct mm_struct *, 1048extern struct vm_area_struct *vma_merge(struct mm_struct *,
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 3ea68cd3b61f..4e5627379b09 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -410,6 +410,24 @@ struct zonelist {
410#endif 410#endif
411}; 411};
412 412
413#ifdef CONFIG_NUMA
414/*
415 * Only custom zonelists like MPOL_BIND need to be filtered as part of
416 * policies. As described in the comment for struct zonelist_cache, these
417 * zonelists will not have a zlcache so zlcache_ptr will not be set. Use
418 * that to determine if the zonelists needs to be filtered or not.
419 */
420static inline int alloc_should_filter_zonelist(struct zonelist *zonelist)
421{
422 return !zonelist->zlcache_ptr;
423}
424#else
425static inline int alloc_should_filter_zonelist(struct zonelist *zonelist)
426{
427 return 0;
428}
429#endif /* CONFIG_NUMA */
430
413#ifdef CONFIG_ARCH_POPULATES_NODE_MAP 431#ifdef CONFIG_ARCH_POPULATES_NODE_MAP
414struct node_active_region { 432struct node_active_region {
415 unsigned long start_pfn; 433 unsigned long start_pfn;
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 2ada8ee316b3..4dc5fa8be781 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -159,7 +159,8 @@ struct ap_device_id {
159 159
160#define AP_DEVICE_ID_MATCH_DEVICE_TYPE 0x01 160#define AP_DEVICE_ID_MATCH_DEVICE_TYPE 0x01
161 161
162#define ACPI_ID_LEN 9 162#define ACPI_ID_LEN 16 /* only 9 bytes needed here, 16 bytes are used */
163 /* to workaround crosscompile issues */
163 164
164struct acpi_device_id { 165struct acpi_device_id {
165 __u8 id[ACPI_ID_LEN]; 166 __u8 id[ACPI_ID_LEN];
diff --git a/include/linux/pci.h b/include/linux/pci.h
index e7d8d4e19a53..038a0dc7273a 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -557,6 +557,7 @@ int pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask);
557int pcix_get_max_mmrbc(struct pci_dev *dev); 557int pcix_get_max_mmrbc(struct pci_dev *dev);
558int pcix_get_mmrbc(struct pci_dev *dev); 558int pcix_get_mmrbc(struct pci_dev *dev);
559int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc); 559int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
560int pcie_get_readrq(struct pci_dev *dev);
560int pcie_set_readrq(struct pci_dev *dev, int rq); 561int pcie_set_readrq(struct pci_dev *dev, int rq);
561void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno); 562void pci_update_resource(struct pci_dev *dev, struct resource *res, int resno);
562int __must_check pci_assign_resource(struct pci_dev *dev, int i); 563int __must_check pci_assign_resource(struct pci_dev *dev, int i);
@@ -578,6 +579,9 @@ int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
578pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state); 579pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
579int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable); 580int pci_enable_wake(struct pci_dev *dev, pci_power_t state, int enable);
580 581
582/* Functions for PCI Hotplug drivers to use */
583int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
584
581/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */ 585/* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
582void pci_bus_assign_resources(struct pci_bus *bus); 586void pci_bus_assign_resources(struct pci_bus *bus);
583void pci_bus_size_bridges(struct pci_bus *bus); 587void pci_bus_size_bridges(struct pci_bus *bus);
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 07fc57429b58..06d23e10a16d 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -360,6 +360,9 @@
360#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32 360#define PCI_DEVICE_ID_ATI_RS400_166 0x5a32
361#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33 361#define PCI_DEVICE_ID_ATI_RS400_200 0x5a33
362#define PCI_DEVICE_ID_ATI_RS480 0x5950 362#define PCI_DEVICE_ID_ATI_RS480 0x5950
363#define PCI_DEVICE_ID_ATI_RD580 0x5952
364#define PCI_DEVICE_ID_ATI_RX790 0x5957
365#define PCI_DEVICE_ID_ATI_RS690 0x7910
363/* ATI IXP Chipset */ 366/* ATI IXP Chipset */
364#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349 367#define PCI_DEVICE_ID_ATI_IXP200_IDE 0x4349
365#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353 368#define PCI_DEVICE_ID_ATI_IXP200_SMBUS 0x4353
@@ -1287,6 +1290,7 @@
1287#define PCI_DEVICE_ID_VIA_VT3324 0x0324 1290#define PCI_DEVICE_ID_VIA_VT3324 0x0324
1288#define PCI_DEVICE_ID_VIA_VT3336 0x0336 1291#define PCI_DEVICE_ID_VIA_VT3336 0x0336
1289#define PCI_DEVICE_ID_VIA_VT3351 0x0351 1292#define PCI_DEVICE_ID_VIA_VT3351 0x0351
1293#define PCI_DEVICE_ID_VIA_VT3364 0x0364
1290#define PCI_DEVICE_ID_VIA_8371_0 0x0391 1294#define PCI_DEVICE_ID_VIA_8371_0 0x0391
1291#define PCI_DEVICE_ID_VIA_8501_0 0x0501 1295#define PCI_DEVICE_ID_VIA_8501_0 0x0501
1292#define PCI_DEVICE_ID_VIA_82C561 0x0561 1296#define PCI_DEVICE_ID_VIA_82C561 0x0561
@@ -2092,8 +2096,10 @@
2092#define PCI_DEVICE_ID_MPC8568 0x0021 2096#define PCI_DEVICE_ID_MPC8568 0x0021
2093#define PCI_DEVICE_ID_MPC8567E 0x0022 2097#define PCI_DEVICE_ID_MPC8567E 0x0022
2094#define PCI_DEVICE_ID_MPC8567 0x0023 2098#define PCI_DEVICE_ID_MPC8567 0x0023
2095#define PCI_DEVICE_ID_MPC8544E 0x0030 2099#define PCI_DEVICE_ID_MPC8533E 0x0030
2096#define PCI_DEVICE_ID_MPC8544 0x0031 2100#define PCI_DEVICE_ID_MPC8533 0x0031
2101#define PCI_DEVICE_ID_MPC8544E 0x0032
2102#define PCI_DEVICE_ID_MPC8544 0x0033
2097#define PCI_DEVICE_ID_MPC8641 0x7010 2103#define PCI_DEVICE_ID_MPC8641 0x7010
2098#define PCI_DEVICE_ID_MPC8641D 0x7011 2104#define PCI_DEVICE_ID_MPC8641D 0x7011
2099 2105
diff --git a/include/linux/pmu.h b/include/linux/pmu.h
index 5ad913ff02b2..b7824c215354 100644
--- a/include/linux/pmu.h
+++ b/include/linux/pmu.h
@@ -226,7 +226,7 @@ extern unsigned int pmu_power_flags;
226extern void pmu_backlight_init(void); 226extern void pmu_backlight_init(void);
227 227
228/* some code needs to know if the PMU was suspended for hibernation */ 228/* some code needs to know if the PMU was suspended for hibernation */
229#if defined(CONFIG_PM) && defined(CONFIG_PPC32) 229#if defined(CONFIG_PM_SLEEP) && defined(CONFIG_PPC32)
230extern int pmu_sys_suspended; 230extern int pmu_sys_suspended;
231#else 231#else
232/* if power management is not configured it can't be suspended */ 232/* if power management is not configured it can't be suspended */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 682ef87da6eb..bd6a0320a770 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -681,7 +681,7 @@ enum cpu_idle_type {
681#define SCHED_LOAD_SHIFT 10 681#define SCHED_LOAD_SHIFT 10
682#define SCHED_LOAD_SCALE (1L << SCHED_LOAD_SHIFT) 682#define SCHED_LOAD_SCALE (1L << SCHED_LOAD_SHIFT)
683 683
684#define SCHED_LOAD_SCALE_FUZZ (SCHED_LOAD_SCALE >> 1) 684#define SCHED_LOAD_SCALE_FUZZ SCHED_LOAD_SCALE
685 685
686#ifdef CONFIG_SMP 686#ifdef CONFIG_SMP
687#define SD_LOAD_BALANCE 1 /* Do load balancing on this domain. */ 687#define SD_LOAD_BALANCE 1 /* Do load balancing on this domain. */
@@ -1388,7 +1388,8 @@ extern void sched_exec(void);
1388#define sched_exec() {} 1388#define sched_exec() {}
1389#endif 1389#endif
1390 1390
1391extern void sched_clock_unstable_event(void); 1391extern void sched_clock_idle_sleep_event(void);
1392extern void sched_clock_idle_wakeup_event(u64 delta_ns);
1392 1393
1393#ifdef CONFIG_HOTPLUG_CPU 1394#ifdef CONFIG_HOTPLUG_CPU
1394extern void idle_task_exit(void); 1395extern void idle_task_exit(void);
@@ -1398,7 +1399,8 @@ static inline void idle_task_exit(void) {}
1398 1399
1399extern void sched_idle_next(void); 1400extern void sched_idle_next(void);
1400 1401
1401extern unsigned int sysctl_sched_granularity; 1402extern unsigned int sysctl_sched_latency;
1403extern unsigned int sysctl_sched_min_granularity;
1402extern unsigned int sysctl_sched_wakeup_granularity; 1404extern unsigned int sysctl_sched_wakeup_granularity;
1403extern unsigned int sysctl_sched_batch_wakeup_granularity; 1405extern unsigned int sysctl_sched_batch_wakeup_granularity;
1404extern unsigned int sysctl_sched_stat_granularity; 1406extern unsigned int sysctl_sched_stat_granularity;
diff --git a/include/linux/security.h b/include/linux/security.h
index c11dc8aa0351..1a15526e9f67 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -54,7 +54,7 @@ extern int cap_inode_removexattr(struct dentry *dentry, char *name);
54extern int cap_task_post_setuid (uid_t old_ruid, uid_t old_euid, uid_t old_suid, int flags); 54extern int cap_task_post_setuid (uid_t old_ruid, uid_t old_euid, uid_t old_suid, int flags);
55extern void cap_task_reparent_to_init (struct task_struct *p); 55extern void cap_task_reparent_to_init (struct task_struct *p);
56extern int cap_syslog (int type); 56extern int cap_syslog (int type);
57extern int cap_vm_enough_memory (long pages); 57extern int cap_vm_enough_memory (struct mm_struct *mm, long pages);
58 58
59struct msghdr; 59struct msghdr;
60struct sk_buff; 60struct sk_buff;
@@ -1125,6 +1125,7 @@ struct request_sock;
1125 * Return 0 if permission is granted. 1125 * Return 0 if permission is granted.
1126 * @vm_enough_memory: 1126 * @vm_enough_memory:
1127 * Check permissions for allocating a new virtual mapping. 1127 * Check permissions for allocating a new virtual mapping.
1128 * @mm contains the mm struct it is being added to.
1128 * @pages contains the number of pages. 1129 * @pages contains the number of pages.
1129 * Return 0 if permission is granted. 1130 * Return 0 if permission is granted.
1130 * 1131 *
@@ -1169,7 +1170,7 @@ struct security_operations {
1169 int (*quota_on) (struct dentry * dentry); 1170 int (*quota_on) (struct dentry * dentry);
1170 int (*syslog) (int type); 1171 int (*syslog) (int type);
1171 int (*settime) (struct timespec *ts, struct timezone *tz); 1172 int (*settime) (struct timespec *ts, struct timezone *tz);
1172 int (*vm_enough_memory) (long pages); 1173 int (*vm_enough_memory) (struct mm_struct *mm, long pages);
1173 1174
1174 int (*bprm_alloc_security) (struct linux_binprm * bprm); 1175 int (*bprm_alloc_security) (struct linux_binprm * bprm);
1175 void (*bprm_free_security) (struct linux_binprm * bprm); 1176 void (*bprm_free_security) (struct linux_binprm * bprm);
@@ -1469,10 +1470,14 @@ static inline int security_settime(struct timespec *ts, struct timezone *tz)
1469 return security_ops->settime(ts, tz); 1470 return security_ops->settime(ts, tz);
1470} 1471}
1471 1472
1472
1473static inline int security_vm_enough_memory(long pages) 1473static inline int security_vm_enough_memory(long pages)
1474{ 1474{
1475 return security_ops->vm_enough_memory(pages); 1475 return security_ops->vm_enough_memory(current->mm, pages);
1476}
1477
1478static inline int security_vm_enough_memory_mm(struct mm_struct *mm, long pages)
1479{
1480 return security_ops->vm_enough_memory(mm, pages);
1476} 1481}
1477 1482
1478static inline int security_bprm_alloc (struct linux_binprm *bprm) 1483static inline int security_bprm_alloc (struct linux_binprm *bprm)
@@ -2219,7 +2224,12 @@ static inline int security_settime(struct timespec *ts, struct timezone *tz)
2219 2224
2220static inline int security_vm_enough_memory(long pages) 2225static inline int security_vm_enough_memory(long pages)
2221{ 2226{
2222 return cap_vm_enough_memory(pages); 2227 return cap_vm_enough_memory(current->mm, pages);
2228}
2229
2230static inline int security_vm_enough_memory_mm(struct mm_struct *mm, long pages)
2231{
2232 return cap_vm_enough_memory(mm, pages);
2223} 2233}
2224 2234
2225static inline int security_bprm_alloc (struct linux_binprm *bprm) 2235static inline int security_bprm_alloc (struct linux_binprm *bprm)
diff --git a/include/linux/selection.h b/include/linux/selection.h
index ed3408b400f1..f9457861937c 100644
--- a/include/linux/selection.h
+++ b/include/linux/selection.h
@@ -10,6 +10,8 @@
10#include <linux/tiocl.h> 10#include <linux/tiocl.h>
11#include <linux/vt_buffer.h> 11#include <linux/vt_buffer.h>
12 12
13struct tty_struct;
14
13extern struct vc_data *sel_cons; 15extern struct vc_data *sel_cons;
14 16
15extern void clear_selection(void); 17extern void clear_selection(void);
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 1c5ed7d92b0f..96c0d93fc2ca 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -118,6 +118,7 @@
118#define UART_LSR_PE 0x04 /* Parity error indicator */ 118#define UART_LSR_PE 0x04 /* Parity error indicator */
119#define UART_LSR_OE 0x02 /* Overrun error indicator */ 119#define UART_LSR_OE 0x02 /* Overrun error indicator */
120#define UART_LSR_DR 0x01 /* Receiver data ready */ 120#define UART_LSR_DR 0x01 /* Receiver data ready */
121#define UART_LSR_BRK_ERROR_BITS 0x1E /* BI, FE, PE, OE bits */
121 122
122#define UART_MSR 6 /* In: Modem Status Register */ 123#define UART_MSR 6 /* In: Modem Status Register */
123#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ 124#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index c66c8a3410b9..ae9b24c12f6a 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -617,7 +617,6 @@ struct v4l2_framebuffer
617#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010 617#define V4L2_FBUF_CAP_LOCAL_ALPHA 0x0010
618#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020 618#define V4L2_FBUF_CAP_GLOBAL_ALPHA 0x0020
619#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040 619#define V4L2_FBUF_CAP_LOCAL_INV_ALPHA 0x0040
620#define V4L2_FBUF_CAP_GLOBAL_INV_ALPHA 0x0080
621/* Flags for the 'flags' field. */ 620/* Flags for the 'flags' field. */
622#define V4L2_FBUF_FLAG_PRIMARY 0x0001 621#define V4L2_FBUF_FLAG_PRIMARY 0x0001
623#define V4L2_FBUF_FLAG_OVERLAY 0x0002 622#define V4L2_FBUF_FLAG_OVERLAY 0x0002
@@ -625,7 +624,6 @@ struct v4l2_framebuffer
625#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008 624#define V4L2_FBUF_FLAG_LOCAL_ALPHA 0x0008
626#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010 625#define V4L2_FBUF_FLAG_GLOBAL_ALPHA 0x0010
627#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020 626#define V4L2_FBUF_FLAG_LOCAL_INV_ALPHA 0x0020
628#define V4L2_FBUF_FLAG_GLOBAL_INV_ALPHA 0x0040
629 627
630struct v4l2_clip 628struct v4l2_clip
631{ 629{
diff --git a/include/math-emu/op-common.h b/include/math-emu/op-common.h
index 93780abd01bc..bb46e7645d53 100644
--- a/include/math-emu/op-common.h
+++ b/include/math-emu/op-common.h
@@ -145,13 +145,16 @@ do { \
145 { \ 145 { \
146 X##_e = 1; \ 146 X##_e = 1; \
147 _FP_FRAC_SET_##wc(X, _FP_ZEROFRAC_##wc); \ 147 _FP_FRAC_SET_##wc(X, _FP_ZEROFRAC_##wc); \
148 FP_SET_EXCEPTION(FP_EX_INEXACT); \
148 } \ 149 } \
149 else \ 150 else \
150 { \ 151 { \
151 X##_e = 0; \ 152 X##_e = 0; \
152 _FP_FRAC_SRL_##wc(X, _FP_WORKBITS); \ 153 _FP_FRAC_SRL_##wc(X, _FP_WORKBITS); \
153 FP_SET_EXCEPTION(FP_EX_UNDERFLOW); \
154 } \ 154 } \
155 if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT) || \
156 (FP_TRAPPING_EXCEPTIONS & FP_EX_UNDERFLOW)) \
157 FP_SET_EXCEPTION(FP_EX_UNDERFLOW); \
155 } \ 158 } \
156 else \ 159 else \
157 { \ 160 { \
diff --git a/include/math-emu/soft-fp.h b/include/math-emu/soft-fp.h
index d02eb64a865b..a6f873b45f98 100644
--- a/include/math-emu/soft-fp.h
+++ b/include/math-emu/soft-fp.h
@@ -97,12 +97,19 @@
97#define FP_INHIBIT_RESULTS 0 97#define FP_INHIBIT_RESULTS 0
98#endif 98#endif
99 99
100#ifndef FP_TRAPPING_EXCEPTIONS
101#define FP_TRAPPING_EXCEPTIONS 0
102#endif
103
100#define FP_SET_EXCEPTION(ex) \ 104#define FP_SET_EXCEPTION(ex) \
101 _fex |= (ex) 105 _fex |= (ex)
102 106
103#define FP_UNSET_EXCEPTION(ex) \ 107#define FP_UNSET_EXCEPTION(ex) \
104 _fex &= ~(ex) 108 _fex &= ~(ex)
105 109
110#define FP_CUR_EXCEPTIONS \
111 (_fex)
112
106#define FP_CLEAR_EXCEPTIONS \ 113#define FP_CLEAR_EXCEPTIONS \
107 _fex = 0 114 _fex = 0
108 115
diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h
index 30712ddd8a5e..8ec3799e42e1 100644
--- a/include/rdma/ib_mad.h
+++ b/include/rdma/ib_mad.h
@@ -39,6 +39,8 @@
39#if !defined( IB_MAD_H ) 39#if !defined( IB_MAD_H )
40#define IB_MAD_H 40#define IB_MAD_H
41 41
42#include <linux/list.h>
43
42#include <rdma/ib_verbs.h> 44#include <rdma/ib_verbs.h>
43 45
44/* Management base version */ 46/* Management base version */
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index 0627a6aa282a..4bea182d7116 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -46,6 +46,8 @@
46#include <linux/mm.h> 46#include <linux/mm.h>
47#include <linux/dma-mapping.h> 47#include <linux/dma-mapping.h>
48#include <linux/kref.h> 48#include <linux/kref.h>
49#include <linux/list.h>
50#include <linux/rwsem.h>
49 51
50#include <asm/atomic.h> 52#include <asm/atomic.h>
51#include <asm/scatterlist.h> 53#include <asm/scatterlist.h>
@@ -731,11 +733,6 @@ struct ib_udata {
731 size_t outlen; 733 size_t outlen;
732}; 734};
733 735
734#define IB_UMEM_MAX_PAGE_CHUNK \
735 ((PAGE_SIZE - offsetof(struct ib_umem_chunk, page_list)) / \
736 ((void *) &((struct ib_umem_chunk *) 0)->page_list[1] - \
737 (void *) &((struct ib_umem_chunk *) 0)->page_list[0]))
738
739struct ib_pd { 736struct ib_pd {
740 struct ib_device *device; 737 struct ib_device *device;
741 struct ib_uobject *uobject; 738 struct ib_uobject *uobject;
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 16:32:23 -0500