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authorIsaku Yamahata <yamahata@valinux.co.jp>2008-05-19 09:13:30 -0400
committerTony Luck <tony.luck@intel.com>2008-05-27 17:38:44 -0400
commit0e1a77ccdbc4ca59ccaf84168a0c3c1df4fadfc0 (patch)
treeceee49874e01183a1871778744c4033864853585 /include
parent8311d21c35092aa4c4a12e0140e1ef3443489d77 (diff)
[IA64] pvops: preparation: introduce ia64_set_rr0_to_rr4() to make kernel paravirtualization friendly.
make kernel paravirtualization friendly by introducing ia64_set_rr0_to_rr4(). ia64/Xen will replace setting rr[0-4] with single hypercall later. Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp> Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-ia64/intrinsics.h9
-rw-r--r--include/asm-ia64/mmu_context.h6
2 files changed, 10 insertions, 5 deletions
diff --git a/include/asm-ia64/intrinsics.h b/include/asm-ia64/intrinsics.h
index f1135b5b94c3..9b83f8f01678 100644
--- a/include/asm-ia64/intrinsics.h
+++ b/include/asm-ia64/intrinsics.h
@@ -18,6 +18,15 @@
18# include <asm/gcc_intrin.h> 18# include <asm/gcc_intrin.h>
19#endif 19#endif
20 20
21#define ia64_set_rr0_to_rr4(val0, val1, val2, val3, val4) \
22do { \
23 ia64_set_rr(0x0000000000000000UL, (val0)); \
24 ia64_set_rr(0x2000000000000000UL, (val1)); \
25 ia64_set_rr(0x4000000000000000UL, (val2)); \
26 ia64_set_rr(0x6000000000000000UL, (val3)); \
27 ia64_set_rr(0x8000000000000000UL, (val4)); \
28} while (0)
29
21/* 30/*
22 * Force an unresolved reference if someone tries to use 31 * Force an unresolved reference if someone tries to use
23 * ia64_fetch_and_add() with a bad value. 32 * ia64_fetch_and_add() with a bad value.
diff --git a/include/asm-ia64/mmu_context.h b/include/asm-ia64/mmu_context.h
index cef2400983fa..040bc87db930 100644
--- a/include/asm-ia64/mmu_context.h
+++ b/include/asm-ia64/mmu_context.h
@@ -152,11 +152,7 @@ reload_context (nv_mm_context_t context)
152# endif 152# endif
153#endif 153#endif
154 154
155 ia64_set_rr(0x0000000000000000UL, rr0); 155 ia64_set_rr0_to_rr4(rr0, rr1, rr2, rr3, rr4);
156 ia64_set_rr(0x2000000000000000UL, rr1);
157 ia64_set_rr(0x4000000000000000UL, rr2);
158 ia64_set_rr(0x6000000000000000UL, rr3);
159 ia64_set_rr(0x8000000000000000UL, rr4);
160 ia64_srlz_i(); /* srlz.i implies srlz.d */ 156 ia64_srlz_i(); /* srlz.i implies srlz.d */
161} 157}
162 158