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authorAdam Jackson <ajax@redhat.com>2012-09-18 10:58:48 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-26 08:13:48 -0400
commite89861dfa3ed0d8e9d184becf25aebea14e98372 (patch)
treeb97b45fce35239645424576a33d6da42a4f5ede4 /include
parent015b85a067bd9949756e49b01b70c820d31316d7 (diff)
drm/dp: Update DPCD defines
Sources: DP, eDP, and DP interop specs, and a VESA slideshow about DP 1.2 for the MST bits. Tested-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Adam Jackson <ajax@redhat.com> Acked-by: Dave Airlie <airlied@gmail.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'include')
-rw-r--r--include/drm/drm_dp_helper.h60
1 files changed, 56 insertions, 4 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 1744b18c06b3..f9888c3cb955 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -69,16 +69,30 @@
69/* 10b = TMDS or HDMI */ 69/* 10b = TMDS or HDMI */
70/* 11b = Other */ 70/* 11b = Other */
71# define DP_FORMAT_CONVERSION (1 << 3) 71# define DP_FORMAT_CONVERSION (1 << 3)
72# define DP_DETAILED_CAP_INFO_AVAILABLE (1 << 4)
72 73
73#define DP_MAIN_LINK_CHANNEL_CODING 0x006 74#define DP_MAIN_LINK_CHANNEL_CODING 0x006
74 75
75#define DP_DOWN_STREAM_PORT_COUNT 0x007 76#define DP_DOWN_STREAM_PORT_COUNT 0x007
76#define DP_PORT_COUNT_MASK 0x0f 77# define DP_PORT_COUNT_MASK 0x0f
77#define DP_OUI_SUPPORT (1 << 7) 78# define DP_MSA_TIMING_PAR_IGNORED (1 << 6)
79# define DP_OUI_SUPPORT (1 << 7)
80
81#define DP_I2C_SPEED_CAP 0x00c
82# define DP_I2C_SPEED_1K 0x01
83# define DP_I2C_SPEED_5K 0x02
84# define DP_I2C_SPEED_10K 0x04
85# define DP_I2C_SPEED_100K 0x08
86# define DP_I2C_SPEED_400K 0x10
87# define DP_I2C_SPEED_1M 0x20
78 88
79#define DP_EDP_CONFIGURATION_CAP 0x00d 89#define DP_EDP_CONFIGURATION_CAP 0x00d
80#define DP_TRAINING_AUX_RD_INTERVAL 0x00e 90#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
81 91
92/* Multiple stream transport */
93#define DP_MSTM_CAP 0x021
94# define DP_MST_CAP (1 << 0)
95
82#define DP_PSR_SUPPORT 0x070 96#define DP_PSR_SUPPORT 0x070
83# define DP_PSR_IS_SUPPORTED 1 97# define DP_PSR_IS_SUPPORTED 1
84#define DP_PSR_CAPS 0x071 98#define DP_PSR_CAPS 0x071
@@ -93,6 +107,31 @@
93# define DP_PSR_SETUP_TIME_MASK (7 << 1) 107# define DP_PSR_SETUP_TIME_MASK (7 << 1)
94# define DP_PSR_SETUP_TIME_SHIFT 1 108# define DP_PSR_SETUP_TIME_SHIFT 1
95 109
110/*
111 * 0x80-0x8f describe downstream port capabilities, but there are two layouts
112 * based on whether DP_DETAILED_CAP_INFO_AVAILABLE was set. If it was not,
113 * each port's descriptor is one byte wide. If it was set, each port's is
114 * four bytes wide, starting with the one byte from the base info. As of
115 * DP interop v1.1a only VGA defines additional detail.
116 */
117
118/* offset 0 */
119#define DP_DOWNSTREAM_PORT_0 0x80
120# define DP_DS_PORT_TYPE_MASK (7 << 0)
121# define DP_DS_PORT_TYPE_DP 0
122# define DP_DS_PORT_TYPE_VGA 1
123# define DP_DS_PORT_TYPE_DVI 2
124# define DP_DS_PORT_TYPE_HDMI 3
125# define DP_DS_PORT_TYPE_NON_EDID 4
126# define DP_DS_PORT_HPD (1 << 3)
127/* offset 1 for VGA is maximum megapixels per second / 8 */
128/* offset 2 */
129# define DP_DS_VGA_MAX_BPC_MASK (3 << 0)
130# define DP_DS_VGA_8BPC 0
131# define DP_DS_VGA_10BPC 1
132# define DP_DS_VGA_12BPC 2
133# define DP_DS_VGA_16BPC 3
134
96/* link configuration */ 135/* link configuration */
97#define DP_LINK_BW_SET 0x100 136#define DP_LINK_BW_SET 0x100
98# define DP_LINK_BW_1_62 0x06 137# define DP_LINK_BW_1_62 0x06
@@ -148,24 +187,37 @@
148 187
149#define DP_DOWNSPREAD_CTRL 0x107 188#define DP_DOWNSPREAD_CTRL 0x107
150# define DP_SPREAD_AMP_0_5 (1 << 4) 189# define DP_SPREAD_AMP_0_5 (1 << 4)
190# define DP_MSA_TIMING_PAR_IGNORE_EN (1 << 7)
151 191
152#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 192#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108
153# define DP_SET_ANSI_8B10B (1 << 0) 193# define DP_SET_ANSI_8B10B (1 << 0)
154 194
195#define DP_I2C_SPEED_CONTROL_STATUS 0x109
196/* bitmask as for DP_I2C_SPEED_CAP */
197
198#define DP_EDP_CONFIGURATION_SET 0x10a
199
200#define DP_MSTM_CTRL 0x111
201# define DP_MST_EN (1 << 0)
202# define DP_UP_REQ_EN (1 << 1)
203# define DP_UPSTREAM_IS_SRC (1 << 2)
204
155#define DP_PSR_EN_CFG 0x170 205#define DP_PSR_EN_CFG 0x170
156# define DP_PSR_ENABLE (1 << 0) 206# define DP_PSR_ENABLE (1 << 0)
157# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1) 207# define DP_PSR_MAIN_LINK_ACTIVE (1 << 1)
158# define DP_PSR_CRC_VERIFICATION (1 << 2) 208# define DP_PSR_CRC_VERIFICATION (1 << 2)
159# define DP_PSR_FRAME_CAPTURE (1 << 3) 209# define DP_PSR_FRAME_CAPTURE (1 << 3)
160 210
211#define DP_SINK_COUNT 0x200
212# define DP_SINK_COUNT_MASK (31 << 0)
213# define DP_SINK_CP_READY (1 << 6)
214
161#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201 215#define DP_DEVICE_SERVICE_IRQ_VECTOR 0x201
162# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0) 216# define DP_REMOTE_CONTROL_COMMAND_PENDING (1 << 0)
163# define DP_AUTOMATED_TEST_REQUEST (1 << 1) 217# define DP_AUTOMATED_TEST_REQUEST (1 << 1)
164# define DP_CP_IRQ (1 << 2) 218# define DP_CP_IRQ (1 << 2)
165# define DP_SINK_SPECIFIC_IRQ (1 << 6) 219# define DP_SINK_SPECIFIC_IRQ (1 << 6)
166 220
167#define DP_EDP_CONFIGURATION_SET 0x10a
168
169#define DP_LANE0_1_STATUS 0x202 221#define DP_LANE0_1_STATUS 0x202
170#define DP_LANE2_3_STATUS 0x203 222#define DP_LANE2_3_STATUS 0x203
171# define DP_LANE_CR_DONE (1 << 0) 223# define DP_LANE_CR_DONE (1 << 0)