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authorMark Brown <broonie@linaro.org>2014-01-16 07:42:54 -0500
committerMark Brown <broonie@linaro.org>2014-01-16 07:42:54 -0500
commit7cfa7b547337faf5890c8c5f091e081fb79caf73 (patch)
treeb7a701162c0f6eb422417bf16f63b1ca7cc69e44 /include
parent99896f714a0a940d84476bc6208319f70af30789 (diff)
parentd70e861a3154833467023123e218e9b1ba558809 (diff)
Merge remote-tracking branch 'asoc/topic/dma' into for-tiwai
Diffstat (limited to 'include')
-rw-r--r--include/linux/dmaengine.h28
1 files changed, 28 insertions, 0 deletions
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index ed92b30a02fd..ba5f96db0754 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -364,6 +364,32 @@ struct dma_slave_config {
364 unsigned int slave_id; 364 unsigned int slave_id;
365}; 365};
366 366
367/**
368 * enum dma_residue_granularity - Granularity of the reported transfer residue
369 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
370 * DMA channel is only able to tell whether a descriptor has been completed or
371 * not, which means residue reporting is not supported by this channel. The
372 * residue field of the dma_tx_state field will always be 0.
373 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
374 * completed segment of the transfer (For cyclic transfers this is after each
375 * period). This is typically implemented by having the hardware generate an
376 * interrupt after each transferred segment and then the drivers updates the
377 * outstanding residue by the size of the segment. Another possibility is if
378 * the hardware supports scatter-gather and the segment descriptor has a field
379 * which gets set after the segment has been completed. The driver then counts
380 * the number of segments without the flag set to compute the residue.
381 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
382 * burst. This is typically only supported if the hardware has a progress
383 * register of some sort (E.g. a register with the current read/write address
384 * or a register with the amount of bursts/beats/bytes that have been
385 * transferred or still need to be transferred).
386 */
387enum dma_residue_granularity {
388 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
389 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
390 DMA_RESIDUE_GRANULARITY_BURST = 2,
391};
392
367/* struct dma_slave_caps - expose capabilities of a slave channel only 393/* struct dma_slave_caps - expose capabilities of a slave channel only
368 * 394 *
369 * @src_addr_widths: bit mask of src addr widths the channel supports 395 * @src_addr_widths: bit mask of src addr widths the channel supports
@@ -374,6 +400,7 @@ struct dma_slave_config {
374 * should be checked by controller as well 400 * should be checked by controller as well
375 * @cmd_pause: true, if pause and thereby resume is supported 401 * @cmd_pause: true, if pause and thereby resume is supported
376 * @cmd_terminate: true, if terminate cmd is supported 402 * @cmd_terminate: true, if terminate cmd is supported
403 * @residue_granularity: granularity of the reported transfer residue
377 */ 404 */
378struct dma_slave_caps { 405struct dma_slave_caps {
379 u32 src_addr_widths; 406 u32 src_addr_widths;
@@ -381,6 +408,7 @@ struct dma_slave_caps {
381 u32 directions; 408 u32 directions;
382 bool cmd_pause; 409 bool cmd_pause;
383 bool cmd_terminate; 410 bool cmd_terminate;
411 enum dma_residue_granularity residue_granularity;
384}; 412};
385 413
386static inline const char *dma_chan_name(struct dma_chan *chan) 414static inline const char *dma_chan_name(struct dma_chan *chan)