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authorDave Airlie <airlied@redhat.com>2009-12-07 23:29:15 -0500
committerDave Airlie <airlied@redhat.com>2009-12-07 23:29:15 -0500
commit7b0a9e8302522d5f7bb7fab6b8a3c8ce8181609c (patch)
treec958236a2397b3e5be77d99a494673764341e737 /include
parent3f838fc50c0dcdc993c24f6f5da0cda1228fc276 (diff)
parentd4877cf2293f5463f531769fd12300cb3417c778 (diff)
Merge remote branch 'korg/drm-radeon-dp' into drm-linus
This merges the radeon KMS DisplayPort and hotplug detect support. Tested on RV635 DP card with a Dell 2408 monitor. Conflicts: drivers/gpu/drm/drm_fb_helper.c
Diffstat (limited to 'include')
-rw-r--r--include/drm/drm_dp_helper.h59
1 files changed, 45 insertions, 14 deletions
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index e49879ce95f9..a49e791db0b0 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -43,16 +43,41 @@
43#define AUX_I2C_REPLY_MASK (0x3 << 6) 43#define AUX_I2C_REPLY_MASK (0x3 << 6)
44 44
45/* AUX CH addresses */ 45/* AUX CH addresses */
46#define DP_LINK_BW_SET 0x100 46/* DPCD */
47#define DP_DPCD_REV 0x000
48
49#define DP_MAX_LINK_RATE 0x001
50
51#define DP_MAX_LANE_COUNT 0x002
52# define DP_MAX_LANE_COUNT_MASK 0x1f
53# define DP_ENHANCED_FRAME_CAP (1 << 7)
54
55#define DP_MAX_DOWNSPREAD 0x003
56# define DP_NO_AUX_HANDSHAKE_LINK_TRAINING (1 << 6)
57
58#define DP_NORP 0x004
59
60#define DP_DOWNSTREAMPORT_PRESENT 0x005
61# define DP_DWN_STRM_PORT_PRESENT (1 << 0)
62# define DP_DWN_STRM_PORT_TYPE_MASK 0x06
63/* 00b = DisplayPort */
64/* 01b = Analog */
65/* 10b = TMDS or HDMI */
66/* 11b = Other */
67# define DP_FORMAT_CONVERSION (1 << 3)
68
69#define DP_MAIN_LINK_CHANNEL_CODING 0x006
70
71/* link configuration */
72#define DP_LINK_BW_SET 0x100
47# define DP_LINK_BW_1_62 0x06 73# define DP_LINK_BW_1_62 0x06
48# define DP_LINK_BW_2_7 0x0a 74# define DP_LINK_BW_2_7 0x0a
49 75
50#define DP_LANE_COUNT_SET 0x101 76#define DP_LANE_COUNT_SET 0x101
51# define DP_LANE_COUNT_MASK 0x0f 77# define DP_LANE_COUNT_MASK 0x0f
52# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7) 78# define DP_LANE_COUNT_ENHANCED_FRAME_EN (1 << 7)
53 79
54#define DP_TRAINING_PATTERN_SET 0x102 80#define DP_TRAINING_PATTERN_SET 0x102
55
56# define DP_TRAINING_PATTERN_DISABLE 0 81# define DP_TRAINING_PATTERN_DISABLE 0
57# define DP_TRAINING_PATTERN_1 1 82# define DP_TRAINING_PATTERN_1 1
58# define DP_TRAINING_PATTERN_2 2 83# define DP_TRAINING_PATTERN_2 2
@@ -102,11 +127,14 @@
102 127
103#define DP_LANE0_1_STATUS 0x202 128#define DP_LANE0_1_STATUS 0x202
104#define DP_LANE2_3_STATUS 0x203 129#define DP_LANE2_3_STATUS 0x203
105
106# define DP_LANE_CR_DONE (1 << 0) 130# define DP_LANE_CR_DONE (1 << 0)
107# define DP_LANE_CHANNEL_EQ_DONE (1 << 1) 131# define DP_LANE_CHANNEL_EQ_DONE (1 << 1)
108# define DP_LANE_SYMBOL_LOCKED (1 << 2) 132# define DP_LANE_SYMBOL_LOCKED (1 << 2)
109 133
134#define DP_CHANNEL_EQ_BITS (DP_LANE_CR_DONE | \
135 DP_LANE_CHANNEL_EQ_DONE | \
136 DP_LANE_SYMBOL_LOCKED)
137
110#define DP_LANE_ALIGN_STATUS_UPDATED 0x204 138#define DP_LANE_ALIGN_STATUS_UPDATED 0x204
111 139
112#define DP_INTERLANE_ALIGN_DONE (1 << 0) 140#define DP_INTERLANE_ALIGN_DONE (1 << 0)
@@ -120,15 +148,18 @@
120 148
121#define DP_ADJUST_REQUEST_LANE0_1 0x206 149#define DP_ADJUST_REQUEST_LANE0_1 0x206
122#define DP_ADJUST_REQUEST_LANE2_3 0x207 150#define DP_ADJUST_REQUEST_LANE2_3 0x207
123 151# define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03
124#define DP_ADJUST_VOLTAGE_SWING_LANE0_MASK 0x03 152# define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0
125#define DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT 0 153# define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c
126#define DP_ADJUST_PRE_EMPHASIS_LANE0_MASK 0x0c 154# define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2
127#define DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT 2 155# define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30
128#define DP_ADJUST_VOLTAGE_SWING_LANE1_MASK 0x30 156# define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4
129#define DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT 4 157# define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0
130#define DP_ADJUST_PRE_EMPHASIS_LANE1_MASK 0xc0 158# define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6
131#define DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT 6 159
160#define DP_SET_POWER 0x600
161# define DP_SET_POWER_D0 0x1
162# define DP_SET_POWER_D3 0x2
132 163
133#define MODE_I2C_START 1 164#define MODE_I2C_START 1
134#define MODE_I2C_WRITE 2 165#define MODE_I2C_WRITE 2