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authorRalf Baechle <ralf@linux-mips.org>2006-08-12 11:40:08 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-09-27 08:37:34 -0400
commit585fa72493edd7d5acb308806e7bb609412c6228 (patch)
tree5ba44983f09c477a35381b1171f58596b7d1110e /include
parent13fdd31abec5f48cf97693bd14d2e11e0779b4ca (diff)
[MIPS] Retire flush_icache_page from mm use.
On the 34K the redundant cache operations were causing excessive stalls resulting in realtime code running on the second VPE missing its deadline. For all other platforms this patch is just a significant performance improvment as illustrated by below benchmark numbers. Processor, Processes - times in microseconds - smaller is better ------------------------------------------------------------------------------ Host OS Mhz null null open slct sig sig fork exec sh call I/O stat clos TCP inst hndl proc proc proc --------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 25Kf 2.6.18-rc4 533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K 25Kf 2.6.18-rc4-p 533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K 4Kc 2.6.18-rc4 80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K 4Kc 2.6.18-rc4-p 80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K 34Kc 2.6.18-rc4 40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K 34Kc 2.6.18-rc4-p 40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K BCM1480 2.6.18-rc4 700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K BCM1480 2.6.18-rc4-p 700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385 TX49-16K 2.6.18-rc3 197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K TX49-16K 2.6.18-rc3-p 197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K TX49-32K 2.6.18-rc3 396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K TX49-32K 2.6.18-rc3-p 396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K Original patch by me with enhancements by Atsushi Nemoto. Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Diffstat (limited to 'include')
-rw-r--r--include/asm-mips/cacheflush.h12
-rw-r--r--include/asm-mips/page.h7
2 files changed, 13 insertions, 6 deletions
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
index 47bc8f6c20d2..36416fdfcf68 100644
--- a/include/asm-mips/cacheflush.h
+++ b/include/asm-mips/cacheflush.h
@@ -21,7 +21,6 @@
21 * - flush_cache_range(vma, start, end) flushes a range of pages 21 * - flush_cache_range(vma, start, end) flushes a range of pages
22 * - flush_icache_range(start, end) flush a range of instructions 22 * - flush_icache_range(start, end) flush a range of instructions
23 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache 23 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 * 24 *
26 * MIPS specific flush operations: 25 * MIPS specific flush operations:
27 * 26 *
@@ -39,7 +38,7 @@ extern void __flush_dcache_page(struct page *page);
39 38
40static inline void flush_dcache_page(struct page *page) 39static inline void flush_dcache_page(struct page *page)
41{ 40{
42 if (cpu_has_dc_aliases) 41 if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
43 __flush_dcache_page(page); 42 __flush_dcache_page(page);
44 43
45} 44}
@@ -47,8 +46,13 @@ static inline void flush_dcache_page(struct page *page)
47#define flush_dcache_mmap_lock(mapping) do { } while (0) 46#define flush_dcache_mmap_lock(mapping) do { } while (0)
48#define flush_dcache_mmap_unlock(mapping) do { } while (0) 47#define flush_dcache_mmap_unlock(mapping) do { } while (0)
49 48
50extern void (*flush_icache_page)(struct vm_area_struct *vma, 49extern void (*__flush_icache_page)(struct vm_area_struct *vma,
51 struct page *page); 50 struct page *page);
51static inline void flush_icache_page(struct vm_area_struct *vma,
52 struct page *page)
53{
54}
55
52extern void (*flush_icache_range)(unsigned long start, unsigned long end); 56extern void (*flush_icache_range)(unsigned long start, unsigned long end);
53#define flush_cache_vmap(start, end) flush_cache_all() 57#define flush_cache_vmap(start, end) flush_cache_all()
54#define flush_cache_vunmap(start, end) flush_cache_all() 58#define flush_cache_vunmap(start, end) flush_cache_all()
@@ -60,7 +64,7 @@ static inline void copy_to_user_page(struct vm_area_struct *vma,
60 if (cpu_has_dc_aliases) 64 if (cpu_has_dc_aliases)
61 flush_cache_page(vma, vaddr, page_to_pfn(page)); 65 flush_cache_page(vma, vaddr, page_to_pfn(page));
62 memcpy(dst, src, len); 66 memcpy(dst, src, len);
63 flush_icache_page(vma, page); 67 __flush_icache_page(vma, page);
64} 68}
65 69
66static inline void copy_from_user_page(struct vm_area_struct *vma, 70static inline void copy_from_user_page(struct vm_area_struct *vma,
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
index 219d359861f3..c3b872b047d7 100644
--- a/include/asm-mips/page.h
+++ b/include/asm-mips/page.h
@@ -34,6 +34,8 @@
34 34
35#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
36 36
37#include <asm/cpu-features.h>
38
37extern void clear_page(void * page); 39extern void clear_page(void * page);
38extern void copy_page(void * to, void * from); 40extern void copy_page(void * to, void * from);
39 41
@@ -53,7 +55,7 @@ static inline void clear_user_page(void *addr, unsigned long vaddr,
53 extern void (*flush_data_cache_page)(unsigned long addr); 55 extern void (*flush_data_cache_page)(unsigned long addr);
54 56
55 clear_page(addr); 57 clear_page(addr);
56 if (pages_do_alias((unsigned long) addr, vaddr)) 58 if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
57 flush_data_cache_page((unsigned long)addr); 59 flush_data_cache_page((unsigned long)addr);
58} 60}
59 61
@@ -63,7 +65,8 @@ static inline void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
63 extern void (*flush_data_cache_page)(unsigned long addr); 65 extern void (*flush_data_cache_page)(unsigned long addr);
64 66
65 copy_page(vto, vfrom); 67 copy_page(vto, vfrom);
66 if (pages_do_alias((unsigned long)vto, vaddr)) 68 if (!cpu_has_ic_fills_f_dc ||
69 pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK))
67 flush_data_cache_page((unsigned long)vto); 70 flush_data_cache_page((unsigned long)vto);
68} 71}
69 72