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authorJuergen Beisert <j.beisert@pengutronix.de>2008-07-05 04:02:50 -0400
committerRobert Schwebel <r.schwebel@pengutronix.de>2008-07-05 04:02:50 -0400
commitd0f349fbce2905607e0473d2358f97f48866e52c (patch)
tree7b6892554648c4ab2eae4b29a054787399a49094 /include
parent90292ea60f1c730efb9fea02b2e12676da89ebef (diff)
i.MXC family: Adding timer support
This patch adds timer support for the i.MX machine family. This code can be used on the following machs: - i.MX1 (tested) - i.MX2 (i.MX21 (to be tested), i.MX27 (tested)) - i.MX3 (i.MX31 (tested)) TODO: It seems impossible to build a kernel for more than one CPU because the timer do not follow the platform device rules. So it does only work if timer 1 can be accessed on all CPUs at the same address. Signed-off-by: Juergen Beisert <j.beisert@pengutronix.de> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-mxc/common.h4
-rw-r--r--include/asm-arm/arch-mxc/mxc.h112
-rw-r--r--include/asm-arm/arch-mxc/mxc_timer.h158
3 files changed, 174 insertions, 100 deletions
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 8774783ed984..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,11 +11,9 @@
11#ifndef __ASM_ARCH_MXC_COMMON_H__ 11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct sys_timer;
15
16extern void mxc_map_io(void); 14extern void mxc_map_io(void);
17extern void mxc_init_irq(void); 15extern void mxc_init_irq(void);
18extern struct sys_timer mxc_timer; 16extern void mxc_timer_init(const char *clk_timer);
19extern int mxc_clocks_init(unsigned long fref); 17extern int mxc_clocks_init(unsigned long fref);
20extern int mxc_register_gpios(void); 18extern int mxc_register_gpios(void);
21 19
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..1df4e2f24920 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_H__ 20#ifndef __ASM_ARCH_MXC_H__
@@ -22,97 +31,6 @@
22 31
23/* 32/*
24 ***************************************** 33 *****************************************
25 * GPT Register definitions *
26 *****************************************
27 */
28#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
29#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
30#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
31#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
32#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
33#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
34#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
35#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
36#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
37#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
38
39/* GPT Control register bit definitions */
40#define GPTCR_FO3 (1 << 31)
41#define GPTCR_FO2 (1 << 30)
42#define GPTCR_FO1 (1 << 29)
43
44#define GPTCR_OM3_SHIFT 26
45#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
48#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
49#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
50#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
51
52#define GPTCR_OM2_SHIFT 23
53#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
56#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
57#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
58#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
59
60#define GPTCR_OM1_SHIFT 20
61#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
64#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
65#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
66#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
67
68#define GPTCR_IM2_SHIFT 18
69#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
71#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
72#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
73#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
74
75#define GPTCR_IM1_SHIFT 16
76#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
78#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
79#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
80#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
81
82#define GPTCR_SWR (1 << 15)
83#define GPTCR_FRR (1 << 9)
84
85#define GPTCR_CLKSRC_SHIFT 6
86#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
88#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
89#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
90#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
91
92#define GPTCR_STOPEN (1 << 5)
93#define GPTCR_DOZEN (1 << 4)
94#define GPTCR_WAITEN (1 << 3)
95#define GPTCR_DBGEN (1 << 2)
96
97#define GPTCR_ENMOD (1 << 1)
98#define GPTCR_ENABLE (1 << 0)
99
100#define GPTSR_OF1 (1 << 0)
101#define GPTSR_OF2 (1 << 1)
102#define GPTSR_OF3 (1 << 2)
103#define GPTSR_IF1 (1 << 3)
104#define GPTSR_IF2 (1 << 4)
105#define GPTSR_ROV (1 << 5)
106
107#define GPTIR_OF1IE GPTSR_OF1
108#define GPTIR_OF2IE GPTSR_OF2
109#define GPTIR_OF3IE GPTSR_OF3
110#define GPTIR_IF1IE GPTSR_IF1
111#define GPTIR_IF2IE GPTSR_IF2
112#define GPTIR_ROVIE GPTSR_ROV
113
114/*
115 *****************************************
116 * AVIC Registers * 34 * AVIC Registers *
117 ***************************************** 35 *****************************************
118 */ 36 */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
1/*
2 * mxc_timer.h
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 * Boston, MA 02110-1301, USA.
21 */
22
23#ifndef __PLAT_MXC_TIMER_H
24#define __PLAT_MXC_TIMER_H
25
26#include <linux/clk.h>
27#include <asm/hardware.h>
28
29#ifdef CONFIG_ARCH_IMX
30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
31#define TIMER_INTERRUPT TIM1_INT
32
33#define TCTL_VAL TCTL_CLK_PCLK1
34#define TCTL_IRQEN (1<<4)
35#define TCTL_FRR (1<<8)
36#define TCTL_CLK_PCLK1 (1<<1)
37#define TCTL_CLK_PCLK1_4 (2<<1)
38#define TCTL_CLK_TIN (3<<1)
39#define TCTL_CLK_32 (4<<1)
40
41#define MXC_TCTL 0x00
42#define MXC_TPRER 0x04
43#define MXC_TCMP 0x08
44#define MXC_TCR 0x0c
45#define MXC_TCN 0x10
46#define MXC_TSTAT 0x14
47#define TSTAT_CAPT (1<<1)
48#define TSTAT_COMP (1<<0)
49
50static inline void gpt_irq_disable(void)
51{
52 unsigned int tmp;
53
54 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
55 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
56}
57
58static inline void gpt_irq_enable(void)
59{
60 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
61 TIMER_BASE + MXC_TCTL);
62}
63
64static void gpt_irq_acknowledge(void)
65{
66 __raw_writel(0, TIMER_BASE + MXC_TSTAT);
67}
68#endif /* CONFIG_ARCH_IMX */
69
70#ifdef CONFIG_ARCH_MX2
71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
72#define TIMER_INTERRUPT MXC_INT_GPT1
73
74#define MXC_TCTL 0x00
75#define TCTL_VAL TCTL_CLK_PCLK1
76#define TCTL_CLK_PCLK1 (1<<1)
77#define TCTL_CLK_PCLK1_4 (2<<1)
78#define TCTL_IRQEN (1<<4)
79#define TCTL_FRR (1<<8)
80#define MXC_TPRER 0x04
81#define MXC_TCMP 0x08
82#define MXC_TCR 0x0c
83#define MXC_TCN 0x10
84#define MXC_TSTAT 0x14
85#define TSTAT_CAPT (1<<1)
86#define TSTAT_COMP (1<<0)
87
88static inline void gpt_irq_disable(void)
89{
90 unsigned int tmp;
91
92 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
93 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
94}
95
96static inline void gpt_irq_enable(void)
97{
98 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
99 TIMER_BASE + MXC_TCTL);
100}
101
102static void gpt_irq_acknowledge(void)
103{
104 __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
105}
106#endif /* CONFIG_ARCH_MX2 */
107
108#ifdef CONFIG_ARCH_MX3
109#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
110#define TIMER_INTERRUPT MXC_INT_GPT
111
112#define MXC_TCTL 0x00
113#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
114#define TCTL_CLK_IPG (1<<6)
115#define TCTL_FRR (1<<9)
116#define TCTL_WAITEN (1<<3)
117
118#define MXC_TPRER 0x04
119#define MXC_TSTAT 0x08
120#define TSTAT_OF1 (1<<0)
121#define TSTAT_OF2 (1<<1)
122#define TSTAT_OF3 (1<<2)
123#define TSTAT_IF1 (1<<3)
124#define TSTAT_IF2 (1<<4)
125#define TSTAT_ROV (1<<5)
126#define MXC_IR 0x0c
127#define MXC_TCMP 0x10
128#define MXC_TCMP2 0x14
129#define MXC_TCMP3 0x18
130#define MXC_TCR 0x1c
131#define MXC_TCN 0x24
132
133static inline void gpt_irq_disable(void)
134{
135 __raw_writel(0, TIMER_BASE + MXC_IR);
136}
137
138static inline void gpt_irq_enable(void)
139{
140 __raw_writel(1<<0, TIMER_BASE + MXC_IR);
141}
142
143static inline void gpt_irq_acknowledge(void)
144{
145 __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
146}
147#endif /* CONFIG_ARCH_MX3 */
148
149#define TCTL_SWR (1<<15)
150#define TCTL_CC (1<<10)
151#define TCTL_OM (1<<9)
152#define TCTL_CAP_RIS (1<<6)
153#define TCTL_CAP_FAL (2<<6)
154#define TCTL_CAP_RIS_FAL (3<<6)
155#define TCTL_CAP_ENA (1<<5)
156#define TCTL_TEN (1<<0)
157
158#endif
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