diff options
author | H. Peter Anvin <hpa@zytor.com> | 2008-08-18 20:39:32 -0400 |
---|---|---|
committer | H. Peter Anvin <hpa@zytor.com> | 2008-09-05 19:13:52 -0400 |
commit | b6734c35af028f06772c0b2c836c7d579e6d4dad (patch) | |
tree | ecdfc0dc851f440b0f5861b8c3fe6b582d516d1b /include | |
parent | b74b06c5f6612a72298f37baa65460a59c26ca67 (diff) |
x86: add NOPL as a synthetic CPU feature bit
The long noops ("NOPL") are supposed to be detected by family >= 6.
Unfortunately, several non-Intel x86 implementations, both hardware
and software, don't obey this dictum. Instead, probe for NOPL
directly by executing a NOPL instruction and see if we get #UD.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-x86/cpufeature.h | 11 | ||||
-rw-r--r-- | include/asm-x86/required-features.h | 8 |
2 files changed, 13 insertions, 6 deletions
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h index 762f6a6bc707..9489283a4bcf 100644 --- a/include/asm-x86/cpufeature.h +++ b/include/asm-x86/cpufeature.h | |||
@@ -72,14 +72,15 @@ | |||
72 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ | 72 | #define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */ |
73 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ | 73 | #define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */ |
74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ | 74 | #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ |
75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ | 75 | #define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ |
76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ | 76 | #define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ |
77 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ | 77 | #define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */ |
78 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ | 78 | #define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */ |
79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ | 79 | #define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ |
80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ | 80 | #define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ |
81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ | 81 | #define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ |
82 | #define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ | 82 | #define X86_FEATURE_11AP (3*32+19) /* Bad local APIC aka 11AP */ |
83 | #define X86_FEATURE_NOPL (3*32+20) /* The NOPL (0F 1F) instructions */ | ||
83 | 84 | ||
84 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ | 85 | /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */ |
85 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ | 86 | #define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */ |
diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h index adec887dd7cd..5c2ff4bc2980 100644 --- a/include/asm-x86/required-features.h +++ b/include/asm-x86/required-features.h | |||
@@ -41,6 +41,12 @@ | |||
41 | # define NEED_3DNOW 0 | 41 | # define NEED_3DNOW 0 |
42 | #endif | 42 | #endif |
43 | 43 | ||
44 | #if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64) | ||
45 | # define NEED_NOPL (1<<(X86_FEATURE_NOPL & 31)) | ||
46 | #else | ||
47 | # define NEED_NOPL 0 | ||
48 | #endif | ||
49 | |||
44 | #ifdef CONFIG_X86_64 | 50 | #ifdef CONFIG_X86_64 |
45 | #define NEED_PSE 0 | 51 | #define NEED_PSE 0 |
46 | #define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) | 52 | #define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) |
@@ -67,7 +73,7 @@ | |||
67 | #define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) | 73 | #define REQUIRED_MASK1 (NEED_LM|NEED_3DNOW) |
68 | 74 | ||
69 | #define REQUIRED_MASK2 0 | 75 | #define REQUIRED_MASK2 0 |
70 | #define REQUIRED_MASK3 0 | 76 | #define REQUIRED_MASK3 (NEED_NOPL) |
71 | #define REQUIRED_MASK4 0 | 77 | #define REQUIRED_MASK4 0 |
72 | #define REQUIRED_MASK5 0 | 78 | #define REQUIRED_MASK5 0 |
73 | #define REQUIRED_MASK6 0 | 79 | #define REQUIRED_MASK6 0 |