[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support

Patch from Ben Dooks

Add support for the Samsung S3C2412 and S3C2413 range
of SoCs. This patch contains the core identification,
debug macros, and basic register updates to get these
to build.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

5 files changed, 92 insertions, 5 deletions

diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 5f8223e700d3..b7d15d125458 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -33,7 +33,7 @@
                 .endm
 
                 .macro  senduart,rd,rx
-                str     \rd, [\rx, # S3C2410_UTXH ]
+                strb    \rd, [\rx, # S3C2410_UTXH ]
                 .endm
 
                 .macro  busyuart, rd, rx
@@ -42,6 +42,12 @@
                 beq     1001f                           @
                 @ FIFO enabled...
 1003:
+                @ check for arm920 vs arm926. currently assume all arm926
+                @ devices have an 64 byte FIFO identical to the s3c2440
+                mrc     p15, 0, \rd, c0, c0
+                and     \rd, \rd, #0xff0
+                teq     \rd, #0x260
+                beq     1004f
                 mrc     p15, 0, \rd, c1, c0
                 tst     \rd, #1
                 addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -50,7 +56,7 @@
                 ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
                 and     \rd, \rd, #0x00ff0000
                 teq     \rd, #0x00440000                @ is it 2440?
-
+1004:
                 ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
                 moveq   \rd, \rd, lsr #SHIFT_2440TXF
                 tst     \rd, #S3C2410_UFSTAT_TXFULL
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 5e4c8c37bc66..fae2766ff32b 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -236,4 +236,20 @@
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
 #endif
 
+/* deal with the registers that move under the 2412/2413 */
+
+#if defined(CONFIG_CPU_S3C2412) || defined(CONFIG_CPU_S3C2413)
+#ifndef __ASSEMBLY__
+extern void __iomem *s3c24xx_va_gpio2;
+#endif
+#ifdef CONFIG_CPU_S3C2412_ONLY
+#define S3C24XX_VA_GPIO2 (S3C24XX_VA_GPIO + 0x10)
+#else
+#define S3C24XX_VA_GPIO2 s3c24xx_va_gpio2
+#endif
+#else
+#define s3c24xx_va_gpio2 S3C24XX_VA_GPIO
+#define S3C24XX_VA_GPIO2 S3C24XX_VA_GPIO
+#endif
+
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
index ba13a2c9e547..84aca61cbaa3 100644
--- a/include/asm-arm/arch-s3c2410/regs-dsc.h
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -23,6 +23,9 @@
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
 
+#define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
+#define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
+
 #define S3C2440_SELECT_DSC0 (0)
 #define S3C2440_SELECT_DSC1 (1<<31)
 
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 5f10334f06bf..6dd17f0f84e0 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -45,7 +45,7 @@
 #define S3C24XX_MISCCR        S3C2400_MISCCR
 #else
 #define S3C24XX_GPIO_BASE(x)  S3C2410_GPIO_BASE(x)
-#define S3C24XX_MISCCR        S3C2410_MISCCR
+#define S3C24XX_MISCCR        S3C24XX_GPIOREG2(0x80)
 #endif /* CONFIG_CPU_S3C2400 */
 
 
@@ -73,9 +73,15 @@
 #define S3C2410_GPIO_SFN2    (0xFFFFFFF2)       /* not available on A */
 #define S3C2410_GPIO_SFN3    (0xFFFFFFF3)       /* not available on A */
 
-/* configure GPIO ports A..G */
+/* register address for the GPIO registers.
+ * S3C24XX_GPIOREG2 is for the second set of registers in the
+ * GPIO which move between s3c2410 and s3c2412 type systems */
 
 #define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
+#define S3C24XX_GPIOREG2(x) ((x) + S3C24XX_VA_GPIO2)
+
+
+/* configure GPIO ports A..G */
 
 /* port A - S3C2410: 22bits, zero in bit X makes pin X output
  *          S3C2400: 18bits, zero in bit X makes pin X output
@@ -953,11 +959,18 @@
 #define S3C2410_GPH10_OUTP    (0x01 << 20)
 #define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
 
+/* The S3C2412 and S3C2413 move the GPJ register set to after
+ * GPH, which means all registers after 0x80 are now offset by 0x10
+ * for the 2412/2413 from the 2410/2440/2442
+*/
+
 /* miscellaneous control */
 #define S3C2400_MISCCR     S3C2410_GPIOREG(0x54)
 #define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
 #define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
 
+#define S3C24XX_DCLKCON    S3C24XX_GPIOREG2(0x84)
+
 /* see clock.h for dclk definitions */
 
 /* pullup control on databus */
@@ -985,6 +998,8 @@
 #define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
 #define S3C2410_MISCCR_CLK0_MASK    (7<<4)
 
+#define S3C2412_MISCCR_CLK0_RTC     (2<<4)
+
 #define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
 #define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
 #define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
@@ -993,6 +1008,8 @@
 #define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
 #define S3C2410_MISCCR_CLK1_MASK    (7<<8)
 
+#define S3C2412_MISCCR_CLK1_CLKsrc  (0<<8)
+
 #define S3C2410_MISCCR_USBSUSPND0   (1<<12)
 #define S3C2410_MISCCR_USBSUSPND1   (1<<13)
 
@@ -1000,7 +1017,7 @@
 
 #define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
 #define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
-#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)
+#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)     /* not 2412 */
 #define S3C2410_MISCCR_SDSLEEP      (7<<17)
 
 /* external interrupt control... */
@@ -1017,6 +1034,10 @@
 #define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
 #define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
 
+#define S3C24XX_EXTINT0    S3C24XX_GPIOREG2(0x88)
+#define S3C24XX_EXTINT1    S3C24XX_GPIOREG2(0x8C)
+#define S3C24XX_EXTINT2    S3C24XX_GPIOREG2(0x90)
+
 /* values for S3C2410_EXTINT0/1/2 */
 #define S3C2410_EXTINT_LOWLEV    (0x00)
 #define S3C2410_EXTINT_HILEV     (0x01)
@@ -1030,6 +1051,11 @@
 #define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
 #define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
 
+#define S3C24XX_EINFLT0    S3C24XX_GPIOREG2(0x94)
+#define S3C24XX_EINFLT1    S3C24XX_GPIOREG2(0x98)
+#define S3C24XX_EINFLT2    S3C24XX_GPIOREG2(0x9C)
+#define S3C24XX_EINFLT3    S3C24XX_GPIOREG2(0xA0)
+
 /* values for interrupt filtering */
 #define S3C2410_EINTFLT_PCLK            (0x00)
 #define S3C2410_EINTFLT_EXTCLK          (1<<7)
@@ -1039,6 +1065,7 @@
 
 /* GSTATUS have miscellaneous information in them
  *
+ * These move between s3c2410 and s3c2412 style systems.
  */
 
 #define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
@@ -1047,6 +1074,18 @@
 #define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
 #define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
 
+#define S3C2412_GSTATUS0   S3C2410_GPIOREG(0x0BC)
+#define S3C2412_GSTATUS1   S3C2410_GPIOREG(0x0C0)
+#define S3C2412_GSTATUS2   S3C2410_GPIOREG(0x0C4)
+#define S3C2412_GSTATUS3   S3C2410_GPIOREG(0x0C8)
+#define S3C2412_GSTATUS4   S3C2410_GPIOREG(0x0CC)
+
+#define S3C24XX_GSTATUS0   S3C24XX_GPIOREG2(0x0AC)
+#define S3C24XX_GSTATUS1   S3C24XX_GPIOREG2(0x0B0)
+#define S3C24XX_GSTATUS2   S3C24XX_GPIOREG2(0x0B4)
+#define S3C24XX_GSTATUS3   S3C24XX_GPIOREG2(0x0B8)
+#define S3C24XX_GSTATUS4   S3C24XX_GPIOREG2(0x0BC)
+
 #define S3C2410_GSTATUS0_nWAIT     (1<<3)
 #define S3C2410_GSTATUS0_NCON      (1<<2)
 #define S3C2410_GSTATUS0_RnB       (1<<1)
@@ -1054,6 +1093,7 @@
 
 #define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
 #define S3C2410_GSTATUS1_2410      (0x32410000)
+#define S3C2410_GSTATUS1_2412      (0x32412001)
 #define S3C2410_GSTATUS1_2440      (0x32440000)
 #define S3C2410_GSTATUS1_2442      (0x32440aaa)
 
@@ -1077,5 +1117,22 @@
 #define S3C2400_OPENCR_OPC_MOSIDIS  (0<<5)
 #define S3C2400_OPENCR_OPC_MOSIEN   (1<<5)
 
+/* 2412/2413 sleep configuration registers */
+
+#define S3C2412_GPBSLPCON       S3C2410_GPIOREG(0x1C)
+#define S3C2412_GPCSLPCON       S3C2410_GPIOREG(0x2C)
+#define S3C2412_GPDSLPCON       S3C2410_GPIOREG(0x3C)
+#define S3C2412_GPESLPCON       S3C2410_GPIOREG(0x4C)
+#define S3C2412_GPFSLPCON       S3C2410_GPIOREG(0x5C)
+#define S3C2412_GPGSLPCON       S3C2410_GPIOREG(0x6C)
+#define S3C2412_GPHSLPCON       S3C2410_GPIOREG(0x7C)
+
+/* definitions for each pin bit */
+#define S3C2412_SLPCON_LOW(x)   ( 0x00 << ((x) * 2))
+#define S3C2412_SLPCON_HI(x)    ( 0x01 << ((x) * 2))
+#define S3C2412_SLPCON_IN(x)    ( 0x02 << ((x) * 2))
+#define S3C2412_SLPCON_PDWN(x)  ( 0x03 << ((x) * 2))
+#define S3C2412_SLPCON_MASK(x)  ( 0x03 << ((x) * 2))
+
 #endif  /* __ASM_ARCH_REGS_GPIO_H */
 
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
index 3ad2324acc39..18edae50d0b8 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpioj.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -32,6 +32,11 @@
 #define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
 #define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
 
+#define S3C2413_GPJCON          S3C2410_GPIOREG(0x80)
+#define S3C2413_GPJDAT          S3C2410_GPIOREG(0x84)
+#define S3C2413_GPJUP           S3C2410_GPIOREG(0x88)
+#define S3C2413_GPJSLPCON       S3C2410_GPIOREG(0x8C)
+
 #define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
 #define S3C2440_GPJ0_INP        (0x00 << 0)
 #define S3C2440_GPJ0_OUTP       (0x01 << 0)