[MIPS] Cleanup TX39/TX49 irq code

Cleanup jmr3927, tx4927 and tx4938 irq codes, using common IRQ_CPU,
I8259 and IRQ_TXX9 irq routines.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

7 files changed, 14 insertions, 165 deletions

diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h
index 958e29706e2d..b2dc35f56181 100644
--- a/include/asm-mips/jmr3927/jmr3927.h
+++ b/include/asm-mips/jmr3927/jmr3927.h
@@ -13,6 +13,7 @@
 #include <asm/jmr3927/tx3927.h>
 #include <asm/addrspace.h>
 #include <asm/system.h>
+#include <asm/txx9irq.h>
 
 /* CS */
 #define JMR3927_ROMCE0  0x1fc00000      /* 4M */
@@ -115,7 +116,7 @@
 #define JMR3927_NR_IRQ_IRC      16      /* On-Chip IRC */
 #define JMR3927_NR_IRQ_IOC      8       /* PCI/MODEM/INT[6:7] */
 
-#define JMR3927_IRQ_IRC 16
+#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
 #define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
 #define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
 
diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h
index 0b9073bfb759..4be2f25f70dd 100644
--- a/include/asm-mips/jmr3927/tx3927.h
+++ b/include/asm-mips/jmr3927/tx3927.h
@@ -50,21 +50,6 @@ struct tx3927_dma_reg {
         volatile unsigned long unused0;
 };
 
-struct tx3927_irc_reg {
-        volatile unsigned long cer;
-        volatile unsigned long cr[2];
-        volatile unsigned long unused0;
-        volatile unsigned long ilr[8];
-        volatile unsigned long unused1[4];
-        volatile unsigned long imr;
-        volatile unsigned long unused2[7];
-        volatile unsigned long scr;
-        volatile unsigned long unused3[7];
-        volatile unsigned long ssr;
-        volatile unsigned long unused4[7];
-        volatile unsigned long csr;
-};
-
 #include <asm/byteorder.h>
 
 #ifdef __BIG_ENDIAN
@@ -225,26 +210,6 @@ struct tx3927_ccfg_reg {
 /*
  * IRC
  */
-#define TX3927_IR_MAX_LEVEL     7
-
-/* IRCER : Int. Control Enable */
-#define TX3927_IRCER_ICE        0x00000001
-
-/* IRCR : Int. Control */
-#define TX3927_IRCR_LOW 0x00000000
-#define TX3927_IRCR_HIGH        0x00000001
-#define TX3927_IRCR_DOWN        0x00000002
-#define TX3927_IRCR_UP  0x00000003
-
-/* IRSCR : Int. Status Control */
-#define TX3927_IRSCR_EIClrE     0x00000100
-#define TX3927_IRSCR_EIClr_MASK 0x0000000f
-
-/* IRCSR : Int. Current Status */
-#define TX3927_IRCSR_IF 0x00010000
-#define TX3927_IRCSR_ILV_MASK   0x00000700
-#define TX3927_IRCSR_IVL_MASK   0x0000001f
-
 #define TX3927_IR_INT0  0
 #define TX3927_IR_INT1  1
 #define TX3927_IR_INT2  2
@@ -347,7 +312,6 @@ struct tx3927_ccfg_reg {
 #define tx3927_sdramcptr        ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
 #define tx3927_romcptr          ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
 #define tx3927_dmaptr           ((struct tx3927_dma_reg *)TX3927_DMA_REG)
-#define tx3927_ircptr           ((struct tx3927_irc_reg *)TX3927_IRC_REG)
 #define tx3927_pcicptr          ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
 #define tx3927_ccfgptr          ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
 #define tx3927_tmrptr(ch)       ((struct txx927_tmr_reg *)TX3927_TMR_REG(ch))
diff --git a/include/asm-mips/tx4927/toshiba_rbtx4927.h b/include/asm-mips/tx4927/toshiba_rbtx4927.h
index 5dc40a867774..a60649569c2c 100644
--- a/include/asm-mips/tx4927/toshiba_rbtx4927.h
+++ b/include/asm-mips/tx4927/toshiba_rbtx4927.h
@@ -50,7 +50,7 @@
 
 
 #define RBTX4927_RTL_8019_BASE (0x1c020280-TBTX4927_ISA_IO_OFFSET)
-#define RBTX4927_RTL_8019_IRQ  (29)
+#define RBTX4927_RTL_8019_IRQ  (TX4927_IRQ_PIC_BEG + 5)
 
 int toshiba_rbtx4927_irq_nested(int sw_irq);
 
diff --git a/include/asm-mips/tx4927/tx4927.h b/include/asm-mips/tx4927/tx4927.h
index de85bd2245f7..4bd4368e188c 100644
--- a/include/asm-mips/tx4927/tx4927.h
+++ b/include/asm-mips/tx4927/tx4927.h
@@ -28,6 +28,7 @@
 #define __ASM_TX4927_TX4927_H
 
 #include <asm/tx4927/tx4927_mips.h>
+#include <asm/txx9irq.h>
 
 /*
  This register naming came from the integrated CPU/controller name TX4927
@@ -421,32 +422,6 @@
 #define TX4927_PIO_LIMIT                0xf50f
 
 
-/* TX4927 Interrupt Controller (32-bit registers) */
-#define TX4927_IRC_BASE                 0xf510
-#define TX4927_IRC_IRFLAG0              0xf510
-#define TX4927_IRC_IRFLAG1              0xf514
-#define TX4927_IRC_IRPOL                0xf518
-#define TX4927_IRC_IRRCNT               0xf51c
-#define TX4927_IRC_IRMASKINT            0xf520
-#define TX4927_IRC_IRMASKEXT            0xf524
-#define TX4927_IRC_IRDEN                0xf600
-#define TX4927_IRC_IRDM0                0xf604
-#define TX4927_IRC_IRDM1                0xf608
-#define TX4927_IRC_IRLVL0               0xf610
-#define TX4927_IRC_IRLVL1               0xf614
-#define TX4927_IRC_IRLVL2               0xf618
-#define TX4927_IRC_IRLVL3               0xf61c
-#define TX4927_IRC_IRLVL4               0xf620
-#define TX4927_IRC_IRLVL5               0xf624
-#define TX4927_IRC_IRLVL6               0xf628
-#define TX4927_IRC_IRLVL7               0xf62c
-#define TX4927_IRC_IRMSK                0xf640
-#define TX4927_IRC_IREDC                0xf660
-#define TX4927_IRC_IRPND                0xf680
-#define TX4927_IRC_IRCS                 0xf6a0
-#define TX4927_IRC_LIMIT                0xf6ff
-
-
 /* TX4927 AC-link controller (32-bit registers) */
 #define TX4927_ACLC_BASE                0xf700
 #define TX4927_ACLC_ACCTLEN             0xf700
@@ -493,25 +468,11 @@
 #define TX4927_WR( reg, val ) TX4927_WR32( reg, val )
 
 
+#define TX4927_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4927_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-
-
-#define MI8259_IRQ_ISA_RAW_BEG   0    /* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4927_IRQ_CP0_RAW_BEG   0    /* tx4927 cpu built-in cp0 */
-#define TX4927_IRQ_CP0_RAW_END   7
-#define TX4927_IRQ_PIC_RAW_BEG   0    /* tx4927 cpu build-in pic */
-#define TX4927_IRQ_PIC_RAW_END  31
-
-
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG   /*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END   /* 15 */
-
-#define TX4927_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_BEG)  /* 16 */
-#define TX4927_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4927_IRQ_CP0_RAW_END)  /* 23 */
-
-#define TX4927_IRQ_PIC_BEG  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_BEG)  /* 24 */
-#define TX4927_IRQ_PIC_END  ((TX4927_IRQ_CP0_END+1)+TX4927_IRQ_PIC_RAW_END)  /* 55 */
+#define TX4927_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4927_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 
 
 #define TX4927_IRQ_USER0            (TX4927_IRQ_CP0_BEG+0)
diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h
index 66c064690f41..f98b2bb719d5 100644
--- a/include/asm-mips/tx4927/tx4927_pci.h
+++ b/include/asm-mips/tx4927/tx4927_pci.h
@@ -48,7 +48,7 @@
 #define TX4927_PCI_CLK_ACK      0x04
 #define TX4927_PCI_CLK_ACE      0x02
 #define TX4927_PCI_CLK_ENDIAN   0x01
-#define TX4927_NR_IRQ_LOCAL     (8+16)
+#define TX4927_NR_IRQ_LOCAL     TX4927_IRQ_PIC_BEG
 #define TX4927_NR_IRQ_IRC       32      /* On-Chip IRC */
 
 #define TX4927_IR_PCIC          16
@@ -99,21 +99,6 @@ struct tx4927_ccfg_reg {
         volatile unsigned long long ramp;
 };
 
-struct tx4927_irc_reg {
-        volatile unsigned long cer;
-        volatile unsigned long cr[2];
-        volatile unsigned long unused0;
-        volatile unsigned long ilr[8];
-        volatile unsigned long unused1[4];
-        volatile unsigned long imr;
-        volatile unsigned long unused2[7];
-        volatile unsigned long scr;
-        volatile unsigned long unused3[7];
-        volatile unsigned long ssr;
-        volatile unsigned long unused4[7];
-        volatile unsigned long csr;
-};
-
 struct tx4927_pcic_reg {
         volatile unsigned long pciid;
         volatile unsigned long pcistatus;
@@ -182,11 +167,6 @@ struct tx4927_pcic_reg {
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
-/* IRCSR : Int. Current Status */
-#define TX4927_IRCSR_IF         0x00010000
-#define TX4927_IRCSR_ILV_MASK   0x00000700
-#define TX4927_IRCSR_IVL_MASK   0x0000001f
-
 /*
  * PCIC
  */
@@ -278,7 +258,6 @@ struct tx4927_pcic_reg {
 #define tx4927_pcicptr          ((struct tx4927_pcic_reg *)TX4927_PCIC_REG)
 #define tx4927_ccfgptr          ((struct tx4927_ccfg_reg *)TX4927_CCFG_REG)
 #define tx4927_ebuscptr         ((struct tx4927_ebusc_reg *)TX4927_EBUSC_REG)
-#define tx4927_ircptr           ((struct tx4927_irc_reg *)TX4927_IRC_REG)
 
 #endif /* _LANGUAGE_ASSEMBLY */
 
diff --git a/include/asm-mips/tx4938/rbtx4938.h b/include/asm-mips/tx4938/rbtx4938.h
index 74e7d8061e58..b14acb575be2 100644
--- a/include/asm-mips/tx4938/rbtx4938.h
+++ b/include/asm-mips/tx4938/rbtx4938.h
@@ -14,6 +14,7 @@
 
 #include <asm/addrspace.h>
 #include <asm/tx4938/tx4938.h>
+#include <asm/txx9irq.h>
 
 /* CS */
 #define RBTX4938_CE0    0x1c000000      /* 64M */
@@ -123,21 +124,11 @@
 #define RBTX4938_NR_IRQ_IRC     32      /* On-Chip IRC */
 #define RBTX4938_NR_IRQ_IOC     8
 
-#define MI8259_IRQ_ISA_RAW_BEG   0      /* optional backplane i8259 */
-#define MI8259_IRQ_ISA_RAW_END  15
-#define TX4938_IRQ_CP0_RAW_BEG   0      /* tx4938 cpu built-in cp0 */
-#define TX4938_IRQ_CP0_RAW_END   7
-#define TX4938_IRQ_PIC_RAW_BEG   0      /* tx4938 cpu build-in pic */
-#define TX4938_IRQ_PIC_RAW_END  31
+#define TX4938_IRQ_CP0_BEG  MIPS_CPU_IRQ_BASE
+#define TX4938_IRQ_CP0_END  (MIPS_CPU_IRQ_BASE + 8 - 1)
 
-#define MI8259_IRQ_ISA_BEG                          MI8259_IRQ_ISA_RAW_BEG      /*  0 */
-#define MI8259_IRQ_ISA_END                          MI8259_IRQ_ISA_RAW_END      /* 15 */
-
-#define TX4938_IRQ_CP0_BEG  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_BEG)     /* 16 */
-#define TX4938_IRQ_CP0_END  ((MI8259_IRQ_ISA_END+1)+TX4938_IRQ_CP0_RAW_END)     /* 23 */
-
-#define TX4938_IRQ_PIC_BEG  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_BEG)     /* 24 */
-#define TX4938_IRQ_PIC_END  ((TX4938_IRQ_CP0_END+1)+TX4938_IRQ_PIC_RAW_END)     /* 55 */
+#define TX4938_IRQ_PIC_BEG  TXX9_IRQ_BASE
+#define TX4938_IRQ_PIC_END  (TXX9_IRQ_BASE + TXx9_MAX_IR - 1)
 #define TX4938_IRQ_NEST_EXT_ON_PIC  (TX4938_IRQ_PIC_BEG+2)
 #define TX4938_IRQ_NEST_PIC_ON_CP0  (TX4938_IRQ_CP0_BEG+2)
 #define TX4938_IRQ_USER0            (TX4938_IRQ_CP0_BEG+0)
@@ -192,10 +183,4 @@
 #define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
 #define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
 
-/* IRCR : Int. Control */
-#define TX4938_IRCR_LOW  0x00000000
-#define TX4938_IRCR_HIGH 0x00000001
-#define TX4938_IRCR_DOWN 0x00000002
-#define TX4938_IRCR_UP   0x00000003
-
 #endif /* __ASM_TX_BOARDS_RBTX4938_H */
diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h
index e25b1a0975cb..afdb19813ca1 100644
--- a/include/asm-mips/tx4938/tx4938.h
+++ b/include/asm-mips/tx4938/tx4938.h
@@ -272,20 +272,6 @@ struct tx4938_pio_reg {
         volatile unsigned long maskcpu;
         volatile unsigned long maskext;
 };
-struct tx4938_irc_reg {
-        volatile unsigned long cer;
-        volatile unsigned long cr[2];
-        volatile unsigned long unused0;
-        volatile unsigned long ilr[8];
-        volatile unsigned long unused1[4];
-        volatile unsigned long imr;
-        volatile unsigned long unused2[7];
-        volatile unsigned long scr;
-        volatile unsigned long unused3[7];
-        volatile unsigned long ssr;
-        volatile unsigned long unused4[7];
-        volatile unsigned long csr;
-};
 
 struct tx4938_ndfmc_reg {
         endian_def_l2(unused0, dtr);
@@ -646,39 +632,12 @@ struct tx4938_ccfg_reg {
 #define TX4938_DMA_CSR_DESERR   0x00000002
 #define TX4938_DMA_CSR_SORERR   0x00000001
 
-/* TX4938 Interrupt Controller (32-bit registers) */
-#define TX4938_IRC_BASE                 0xf510
-#define TX4938_IRC_IRFLAG0              0xf510
-#define TX4938_IRC_IRFLAG1              0xf514
-#define TX4938_IRC_IRPOL                0xf518
-#define TX4938_IRC_IRRCNT               0xf51c
-#define TX4938_IRC_IRMASKINT            0xf520
-#define TX4938_IRC_IRMASKEXT            0xf524
-#define TX4938_IRC_IRDEN                0xf600
-#define TX4938_IRC_IRDM0                0xf604
-#define TX4938_IRC_IRDM1                0xf608
-#define TX4938_IRC_IRLVL0               0xf610
-#define TX4938_IRC_IRLVL1               0xf614
-#define TX4938_IRC_IRLVL2               0xf618
-#define TX4938_IRC_IRLVL3               0xf61c
-#define TX4938_IRC_IRLVL4               0xf620
-#define TX4938_IRC_IRLVL5               0xf624
-#define TX4938_IRC_IRLVL6               0xf628
-#define TX4938_IRC_IRLVL7               0xf62c
-#define TX4938_IRC_IRMSK                0xf640
-#define TX4938_IRC_IREDC                0xf660
-#define TX4938_IRC_IRPND                0xf680
-#define TX4938_IRC_IRCS                 0xf6a0
-#define TX4938_IRC_LIMIT                0xf6ff
-
-
 #ifndef __ASSEMBLY__
 
 #define tx4938_sdramcptr        ((struct tx4938_sdramc_reg *)TX4938_SDRAMC_REG)
 #define tx4938_ebuscptr         ((struct tx4938_ebusc_reg *)TX4938_EBUSC_REG)
 #define tx4938_dmaptr(ch)       ((struct tx4938_dma_reg *)TX4938_DMA_REG(ch))
 #define tx4938_ndfmcptr         ((struct tx4938_ndfmc_reg *)TX4938_NDFMC_REG)
-#define tx4938_ircptr           ((struct tx4938_irc_reg *)TX4938_IRC_REG)
 #define tx4938_pcicptr          ((struct tx4938_pcic_reg *)TX4938_PCIC_REG)
 #define tx4938_pcic1ptr         ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG)
 #define tx4938_ccfgptr          ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG)