Merge commit master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6 of HEAD

* HEAD:
  [PATCH] PCI: PCIE power management quirk
  [PATCH] PCI: add PCI Express AER register definitions to pci_regs.h
  [PATCH] PCI: Clear abnormal poweroff flag on VIA southbridges, fix resume
  [PATCH] PCI: poper prototype for arch/i386/pci/pcbios.c:pcibios_sort()

2 files changed, 17 insertions, 0 deletions

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 983fca251b25..8565b81d7fbc 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -161,6 +161,7 @@ struct pci_dev {
         unsigned int    is_enabled:1;   /* pci_enable_device has been called */
         unsigned int    is_busmaster:1; /* device is busmaster */
         unsigned int    no_msi:1;       /* device may not use msi */
+        unsigned int    no_d1d2:1;   /* only allow d0 or d3 */
         unsigned int    block_ucfg_access:1;    /* userspace config space access is blocked */
         unsigned int    broken_parity_status:1; /* Device generates false positive parity */
         unsigned int    msi_enabled:1;
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index 6bce4a240364..96930cb5927c 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -422,7 +422,23 @@
 #define  PCI_ERR_CAP_ECRC_CHKE  0x00000100      /* ECRC Check Enable */
 #define PCI_ERR_HEADER_LOG      28      /* Header Log Register (16 bytes) */
 #define PCI_ERR_ROOT_COMMAND    44      /* Root Error Command */
+/* Correctable Err Reporting Enable */
+#define PCI_ERR_ROOT_CMD_COR_EN         0x00000001
+/* Non-fatal Err Reporting Enable */
+#define PCI_ERR_ROOT_CMD_NONFATAL_EN    0x00000002
+/* Fatal Err Reporting Enable */
+#define PCI_ERR_ROOT_CMD_FATAL_EN       0x00000004
 #define PCI_ERR_ROOT_STATUS     48
+#define PCI_ERR_ROOT_COR_RCV            0x00000001      /* ERR_COR Received */
+/* Multi ERR_COR Received */
+#define PCI_ERR_ROOT_MULTI_COR_RCV      0x00000002
+/* ERR_FATAL/NONFATAL Recevied */
+#define PCI_ERR_ROOT_UNCOR_RCV          0x00000004
+/* Multi ERR_FATAL/NONFATAL Recevied */
+#define PCI_ERR_ROOT_MULTI_UNCOR_RCV    0x00000008
+#define PCI_ERR_ROOT_FIRST_FATAL        0x00000010      /* First Fatal */
+#define PCI_ERR_ROOT_NONFATAL_RCV       0x00000020      /* Non-Fatal Received */
+#define PCI_ERR_ROOT_FATAL_RCV          0x00000040      /* Fatal Received */
 #define PCI_ERR_ROOT_COR_SRC    52
 #define PCI_ERR_ROOT_SRC        54