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authorKumar Gala <galak@freescale.com>2005-09-09 16:02:25 -0400
committerPaul Mackerras <paulus@samba.org>2005-09-18 19:38:49 -0400
commit5f7c690728ace1404f72d74972dcc261674c0dd4 (patch)
treed2fea77e39c2103be9ae41b9b849dce949cd9efd /include
parent0a1e1222b77b9b02457d8126f598e3713559d5c7 (diff)
[PATCH] powerpc: Merged ppc_asm.h
Merged ppc_asm.h between ppc32 & ppc64. The majority of the file is common between the two architectures excluding how a single GPR is saved/restored and which GPRs are non-volatile. Additionally, moved the ASM_CONST macro used on ppc64 into ppc_asm.h. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-powerpc/ppc_asm.h (renamed from include/asm-ppc/ppc_asm.h)205
-rw-r--r--include/asm-ppc64/cputable.h2
-rw-r--r--include/asm-ppc64/mmu.h1
-rw-r--r--include/asm-ppc64/page.h8
-rw-r--r--include/asm-ppc64/ppc_asm.h242
5 files changed, 149 insertions, 309 deletions
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index bb53e2def363..553035cda00e 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -1,38 +1,40 @@
1/* 1/*
2 * include/asm-ppc/ppc_asm.h
3 *
4 * Definitions used by various bits of low-level assembly code on PowerPC.
5 *
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. 2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */ 3 */
13 4
14#include <linux/config.h> 5#ifndef _ASM_POWERPC_PPC_ASM_H
6#define _ASM_POWERPC_PPC_ASM_H
7
8#ifdef __ASSEMBLY__
15 9
16/* 10/*
17 * Macros for storing registers into and loading registers from 11 * Macros for storing registers into and loading registers from
18 * exception frames. 12 * exception frames.
19 */ 13 */
14#ifdef __powerpc64__
15#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
16#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
17#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
18#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
19#else
20#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 20#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
21#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
22#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
23 SAVE_10GPRS(22, base)
24#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
25 REST_10GPRS(22, base)
26#endif
27
28
21#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 29#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
22#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 30#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
23#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 31#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
24#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 32#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
25#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
26#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 33#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
27#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 34#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
28#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 35#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
29#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 36#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
30 37
31#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
32 SAVE_10GPRS(22, base)
33#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
34 REST_10GPRS(22, base)
35
36#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) 38#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
37#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) 39#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
38#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) 40#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
@@ -47,32 +49,80 @@
47#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) 49#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
48 50
49#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base 51#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
50#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) 52#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
51#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base) 53#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
52#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base) 54#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
53#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base) 55#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
54#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base) 56#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
55#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base 57#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
56#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) 58#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
57#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base) 59#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
58#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base) 60#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
59#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base) 61#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
60#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base) 62#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
61 63
62#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base) 64#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
63#define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base) 65#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
64#define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base) 66#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
65#define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base) 67#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
66#define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base) 68#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
67#define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base) 69#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
68
69#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n 70#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
70#define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base) 71#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
71#define REST_4EVR(n,s,base) REST_2EVR(n,s,base); REST_2EVR(n+2,s,base) 72#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
72#define REST_8EVR(n,s,base) REST_4EVR(n,s,base); REST_4EVR(n+4,s,base) 73#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
73#define REST_16EVR(n,s,base) REST_8EVR(n,s,base); REST_8EVR(n+8,s,base) 74#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
74#define REST_32EVR(n,s,base) REST_16EVR(n,s,base); REST_16EVR(n+16,s,base) 75#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
76
77/* Macros to adjust thread priority for Iseries hardware multithreading */
78#define HMT_LOW or 1,1,1
79#define HMT_MEDIUM or 2,2,2
80#define HMT_HIGH or 3,3,3
81
82/* handle instructions that older assemblers may not know */
83#define RFCI .long 0x4c000066 /* rfci instruction */
84#define RFDI .long 0x4c00004e /* rfdi instruction */
85#define RFMCI .long 0x4c00004c /* rfmci instruction */
86
87/*
88 * LOADADDR( rn, name )
89 * loads the address of 'name' into 'rn'
90 *
91 * LOADBASE( rn, name )
92 * loads the address (less the low 16 bits) of 'name' into 'rn'
93 * suitable for base+disp addressing
94 */
95#ifdef __powerpc64__
96#define LOADADDR(rn,name) \
97 lis rn,name##@highest; \
98 ori rn,rn,name##@higher; \
99 rldicr rn,rn,32,31; \
100 oris rn,rn,name##@h; \
101 ori rn,rn,name##@l
102
103#define LOADBASE(rn,name) \
104 lis rn,name@highest; \
105 ori rn,rn,name@higher; \
106 rldicr rn,rn,32,31; \
107 oris rn,rn,name@ha
108
109
110#define SET_REG_TO_CONST(reg, value) \
111 lis reg,(((value)>>48)&0xFFFF); \
112 ori reg,reg,(((value)>>32)&0xFFFF); \
113 rldicr reg,reg,32,31; \
114 oris reg,reg,(((value)>>16)&0xFFFF); \
115 ori reg,reg,((value)&0xFFFF);
116
117#define SET_REG_TO_LABEL(reg, label) \
118 lis reg,(label)@highest; \
119 ori reg,reg,(label)@higher; \
120 rldicr reg,reg,32,31; \
121 oris reg,reg,(label)@h; \
122 ori reg,reg,(label)@l;
123#endif
75 124
125/* various errata or part fixups */
76#ifdef CONFIG_PPC601_SYNC_FIX 126#ifdef CONFIG_PPC601_SYNC_FIX
77#define SYNC \ 127#define SYNC \
78BEGIN_FTR_SECTION \ 128BEGIN_FTR_SECTION \
@@ -93,6 +143,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_601)
93#define ISYNC_601 143#define ISYNC_601
94#endif 144#endif
95 145
146
96#ifndef CONFIG_SMP 147#ifndef CONFIG_SMP
97#define TLBSYNC 148#define TLBSYNC
98#else /* CONFIG_SMP */ 149#else /* CONFIG_SMP */
@@ -104,6 +155,7 @@ BEGIN_FTR_SECTION \
104END_FTR_SECTION_IFCLR(CPU_FTR_601) 155END_FTR_SECTION_IFCLR(CPU_FTR_601)
105#endif 156#endif
106 157
158
107/* 159/*
108 * This instruction is not implemented on the PPC 603 or 601; however, on 160 * This instruction is not implemented on the PPC 603 or 601; however, on
109 * the 403GCX and 405GP tlbia IS defined and tlbie is not. 161 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
@@ -121,14 +173,44 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
121 bdnz 0b 173 bdnz 0b
122#endif 174#endif
123 175
124#ifdef CONFIG_BOOKE 176
177#ifdef CONFIG_IBM405_ERR77
178#define PPC405_ERR77(ra,rb) dcbt ra, rb;
179#define PPC405_ERR77_SYNC sync;
180#else
181#define PPC405_ERR77(ra,rb)
182#define PPC405_ERR77_SYNC
183#endif
184
185
186#ifdef CONFIG_IBM440EP_ERR42
187#define PPC440EP_ERR42 isync
188#else
189#define PPC440EP_ERR42
190#endif
191
192
193#if defined(CONFIG_BOOKE)
125#define tophys(rd,rs) \ 194#define tophys(rd,rs) \
126 addis rd,rs,0 195 addis rd,rs,0
127 196
128#define tovirt(rd,rs) \ 197#define tovirt(rd,rs) \
129 addis rd,rs,0 198 addis rd,rs,0
130 199
131#else /* CONFIG_BOOKE */ 200#elif defined(CONFIG_PPC64)
201/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
202 * Then we can easily do this with one asm insn. -Peter
203 */
204#define tophys(rd,rs) \
205 lis rd,((KERNELBASE>>48)&0xFFFF); \
206 rldicr rd,rd,32,31; \
207 sub rd,rs,rd
208
209#define tovirt(rd,rs) \
210 lis rd,((KERNELBASE>>48)&0xFFFF); \
211 rldicr rd,rd,32,31; \
212 add rd,rs,rd
213#else
132/* 214/*
133 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the 215 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
134 * physical base address of RAM at compile time. 216 * physical base address of RAM at compile time.
@@ -146,14 +228,14 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
146 .align 1; \ 228 .align 1; \
147 .long 0b; \ 229 .long 0b; \
148 .previous 230 .previous
149#endif /* CONFIG_BOOKE */ 231#endif
150 232
151/* 233/*
152 * On 64-bit cpus, we use the rfid instruction instead of rfi, but 234 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
153 * we then have to make sure we preserve the top 32 bits except for 235 * we then have to make sure we preserve the top 32 bits except for
154 * the 64-bit mode bit, which we clear. 236 * the 64-bit mode bit, which we clear.
155 */ 237 */
156#ifdef CONFIG_PPC64BRIDGE 238#if defined(CONFIG_PPC64BRIDGE)
157#define FIX_SRR1(ra, rb) \ 239#define FIX_SRR1(ra, rb) \
158 mr rb,ra; \ 240 mr rb,ra; \
159 mfmsr ra; \ 241 mfmsr ra; \
@@ -162,6 +244,17 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
162#define RFI .long 0x4c000024 /* rfid instruction */ 244#define RFI .long 0x4c000024 /* rfid instruction */
163#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */ 245#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
164#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */ 246#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
247#elif defined(CONFIG_PPC64)
248/* Insert the high 32 bits of the MSR into what will be the new
249 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
250 bits. */
251
252#define FIX_SRR1(ra, rb) \
253 mr rb,ra; \
254 mfmsr ra; \
255 rldimi ra,rb,0,32
256
257#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
165 258
166#else 259#else
167#define FIX_SRR1(ra, rb) 260#define FIX_SRR1(ra, rb)
@@ -172,24 +265,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
172#endif 265#endif
173#define MTMSRD(r) mtmsr r 266#define MTMSRD(r) mtmsr r
174#define CLR_TOP32(r) 267#define CLR_TOP32(r)
175#endif /* CONFIG_PPC64BRIDGE */
176
177#define RFCI .long 0x4c000066 /* rfci instruction */
178#define RFDI .long 0x4c00004e /* rfdi instruction */
179#define RFMCI .long 0x4c00004c /* rfmci instruction */
180
181#ifdef CONFIG_IBM405_ERR77
182#define PPC405_ERR77(ra,rb) dcbt ra, rb;
183#define PPC405_ERR77_SYNC sync;
184#else
185#define PPC405_ERR77(ra,rb)
186#define PPC405_ERR77_SYNC
187#endif
188
189#ifdef CONFIG_IBM440EP_ERR42
190#define PPC440EP_ERR42 isync
191#else
192#define PPC440EP_ERR42
193#endif 268#endif
194 269
195/* The boring bits... */ 270/* The boring bits... */
@@ -277,6 +352,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
277#define fr30 30 352#define fr30 30
278#define fr31 31 353#define fr31 31
279 354
355/* AltiVec Registers (VPRs) */
356
280#define vr0 0 357#define vr0 0
281#define vr1 1 358#define vr1 1
282#define vr2 2 359#define vr2 2
@@ -310,6 +387,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
310#define vr30 30 387#define vr30 30
311#define vr31 31 388#define vr31 31
312 389
390/* SPE Registers (EVPRs) */
391
313#define evr0 0 392#define evr0 0
314#define evr1 1 393#define evr1 1
315#define evr2 2 394#define evr2 2
@@ -348,3 +427,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
348#define N_RSYM 64 427#define N_RSYM 64
349#define N_SLINE 68 428#define N_SLINE 68
350#define N_SO 100 429#define N_SO 100
430
431#define ASM_CONST(x) x
432#else
433 #define __ASM_CONST(x) x##UL
434 #define ASM_CONST(x) __ASM_CONST(x)
435#endif /* __ASSEMBLY__ */
436
437#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
index acc9b4d6c168..35121408ed1c 100644
--- a/include/asm-ppc64/cputable.h
+++ b/include/asm-ppc64/cputable.h
@@ -16,7 +16,7 @@
16#define __ASM_PPC_CPUTABLE_H 16#define __ASM_PPC_CPUTABLE_H
17 17
18#include <linux/config.h> 18#include <linux/config.h>
19#include <asm/page.h> /* for ASM_CONST */ 19#include <asm/ppc_asm.h> /* for ASM_CONST */
20 20
21/* Exposed to userland CPU features - Must match ppc32 definitions */ 21/* Exposed to userland CPU features - Must match ppc32 definitions */
22#define PPC_FEATURE_32 0x80000000 22#define PPC_FEATURE_32 0x80000000
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 7bc42eb087ad..737e85a5ce3c 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -14,6 +14,7 @@
14#define _PPC64_MMU_H_ 14#define _PPC64_MMU_H_
15 15
16#include <linux/config.h> 16#include <linux/config.h>
17#include <asm/ppc_asm.h> /* for ASM_CONST */
17#include <asm/page.h> 18#include <asm/page.h>
18 19
19/* 20/*
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
index a15422bcf30d..d404431f0a9a 100644
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -11,13 +11,7 @@
11 */ 11 */
12 12
13#include <linux/config.h> 13#include <linux/config.h>
14 14#include <asm/ppc_asm.h> /* for ASM_CONST */
15#ifdef __ASSEMBLY__
16 #define ASM_CONST(x) x
17#else
18 #define __ASM_CONST(x) x##UL
19 #define ASM_CONST(x) __ASM_CONST(x)
20#endif
21 15
22/* PAGE_SHIFT determines the page size */ 16/* PAGE_SHIFT determines the page size */
23#define PAGE_SHIFT 12 17#define PAGE_SHIFT 12
diff --git a/include/asm-ppc64/ppc_asm.h b/include/asm-ppc64/ppc_asm.h
deleted file mode 100644
index 9031d8a29aca..000000000000
--- a/include/asm-ppc64/ppc_asm.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * arch/ppc64/kernel/ppc_asm.h
3 *
4 * Definitions used by various bits of low-level assembly code on PowerPC.
5 *
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#ifndef _PPC64_PPC_ASM_H
15#define _PPC64_PPC_ASM_H
16/*
17 * Macros for storing registers into and loading registers from
18 * exception frames.
19 */
20#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
21#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
22#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
23#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
24#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
25#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
26#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
27#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
28#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
29#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
30
31#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
32#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
33
34#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
35#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
36#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
37#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
38#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
39#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
40#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
41#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
42#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
43#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
44#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
45#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
46
47#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
48#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
49#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
50#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
51#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
52#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
53#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
54#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
55#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
56#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
57#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
58#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
59
60/* Macros to adjust thread priority for Iseries hardware multithreading */
61#define HMT_LOW or 1,1,1
62#define HMT_MEDIUM or 2,2,2
63#define HMT_HIGH or 3,3,3
64
65/* Insert the high 32 bits of the MSR into what will be the new
66 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
67 bits. */
68
69#define FIX_SRR1(ra, rb) \
70 mr rb,ra; \
71 mfmsr ra; \
72 rldimi ra,rb,0,32
73
74#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
75
76/*
77 * LOADADDR( rn, name )
78 * loads the address of 'name' into 'rn'
79 *
80 * LOADBASE( rn, name )
81 * loads the address (less the low 16 bits) of 'name' into 'rn'
82 * suitable for base+disp addressing
83 */
84#define LOADADDR(rn,name) \
85 lis rn,name##@highest; \
86 ori rn,rn,name##@higher; \
87 rldicr rn,rn,32,31; \
88 oris rn,rn,name##@h; \
89 ori rn,rn,name##@l
90
91#define LOADBASE(rn,name) \
92 lis rn,name@highest; \
93 ori rn,rn,name@higher; \
94 rldicr rn,rn,32,31; \
95 oris rn,rn,name@ha
96
97
98#define SET_REG_TO_CONST(reg, value) \
99 lis reg,(((value)>>48)&0xFFFF); \
100 ori reg,reg,(((value)>>32)&0xFFFF); \
101 rldicr reg,reg,32,31; \
102 oris reg,reg,(((value)>>16)&0xFFFF); \
103 ori reg,reg,((value)&0xFFFF);
104
105#define SET_REG_TO_LABEL(reg, label) \
106 lis reg,(label)@highest; \
107 ori reg,reg,(label)@higher; \
108 rldicr reg,reg,32,31; \
109 oris reg,reg,(label)@h; \
110 ori reg,reg,(label)@l;
111
112
113/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
114 * Then we can easily do this with one asm insn. -Peter
115 */
116#define tophys(rd,rs) \
117 lis rd,((KERNELBASE>>48)&0xFFFF); \
118 rldicr rd,rd,32,31; \
119 sub rd,rs,rd
120
121#define tovirt(rd,rs) \
122 lis rd,((KERNELBASE>>48)&0xFFFF); \
123 rldicr rd,rd,32,31; \
124 add rd,rs,rd
125
126/* Condition Register Bit Fields */
127
128#define cr0 0
129#define cr1 1
130#define cr2 2
131#define cr3 3
132#define cr4 4
133#define cr5 5
134#define cr6 6
135#define cr7 7
136
137
138/* General Purpose Registers (GPRs) */
139
140#define r0 0
141#define r1 1
142#define r2 2
143#define r3 3
144#define r4 4
145#define r5 5
146#define r6 6
147#define r7 7
148#define r8 8
149#define r9 9
150#define r10 10
151#define r11 11
152#define r12 12
153#define r13 13
154#define r14 14
155#define r15 15
156#define r16 16
157#define r17 17
158#define r18 18
159#define r19 19
160#define r20 20
161#define r21 21
162#define r22 22
163#define r23 23
164#define r24 24
165#define r25 25
166#define r26 26
167#define r27 27
168#define r28 28
169#define r29 29
170#define r30 30
171#define r31 31
172
173
174/* Floating Point Registers (FPRs) */
175
176#define fr0 0
177#define fr1 1
178#define fr2 2
179#define fr3 3
180#define fr4 4
181#define fr5 5
182#define fr6 6
183#define fr7 7
184#define fr8 8
185#define fr9 9
186#define fr10 10
187#define fr11 11
188#define fr12 12
189#define fr13 13
190#define fr14 14
191#define fr15 15
192#define fr16 16
193#define fr17 17
194#define fr18 18
195#define fr19 19
196#define fr20 20
197#define fr21 21
198#define fr22 22
199#define fr23 23
200#define fr24 24
201#define fr25 25
202#define fr26 26
203#define fr27 27
204#define fr28 28
205#define fr29 29
206#define fr30 30
207#define fr31 31
208
209#define vr0 0
210#define vr1 1
211#define vr2 2
212#define vr3 3
213#define vr4 4
214#define vr5 5
215#define vr6 6
216#define vr7 7
217#define vr8 8
218#define vr9 9
219#define vr10 10
220#define vr11 11
221#define vr12 12
222#define vr13 13
223#define vr14 14
224#define vr15 15
225#define vr16 16
226#define vr17 17
227#define vr18 18
228#define vr19 19
229#define vr20 20
230#define vr21 21
231#define vr22 22
232#define vr23 23
233#define vr24 24
234#define vr25 25
235#define vr26 26
236#define vr27 27
237#define vr28 28
238#define vr29 29
239#define vr30 30
240#define vr31 31
241
242#endif /* _PPC64_PPC_ASM_H */
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