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authorLinus Torvalds <torvalds@linux-foundation.org>2009-12-14 13:02:35 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-12-14 13:02:35 -0500
commit76b8f82cde2d9c13ef0c9a9aa2581b9b30b68e8c (patch)
treef94b370b95051b4a7b3c272b4b2ee20091e1b746 /include
parentaf853e631db12a97363c8c3b727d153bd2cb346b (diff)
parent9da66539281b5e15afc4a4739014c8923059d894 (diff)
Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (58 commits) mfd: Add twl6030 regulator subdevices regulator: Add support for twl6030 regulators rtc: Add twl6030 RTC support mfd: Add support for twl6030 irq framework mfd: Rename twl4030_ routines in twl-regulator.c mfd: Rename twl4030_ routines in rtc-twl.c mfd: Rename all twl4030_i2c* mfd: Rename twl4030* driver files to enable re-use mfd: Clarify twl4030 return value for read and write mfd: Add all twl4030 regulators to the twl4030 mfd driver mfd: Don't set mc13783 ADREFMODE for touch conversions mfd: Remove ezx-pcap defines for custom led gpio encoding mfd: Near complete mc13783 rewrite mfd: Remove build time warning for WM835x register default tables mfd: Force I2C to be built in when building WM831x mfd: Don't allow wm831x to be built as a module mfd: Fix incorrect error check for wm8350-core mfd: Fix twl4030 warning gpiolib: Implement gpio_to_irq() for wm831x mfd: Remove default selection of AB4500 ...
Diffstat (limited to 'include')
-rw-r--r--include/linux/i2c/tps65010.h19
-rw-r--r--include/linux/i2c/twl.h (renamed from include/linux/i2c/twl4030.h)209
-rw-r--r--include/linux/mfd/88pm8607.h217
-rw-r--r--include/linux/mfd/ab4500.h262
-rw-r--r--include/linux/mfd/adp5520.h299
-rw-r--r--include/linux/mfd/ezx-pcap.h3
-rw-r--r--include/linux/mfd/mc13783-private.h208
-rw-r--r--include/linux/mfd/mc13783.h120
-rw-r--r--include/linux/mfd/pcf50633/core.h10
-rw-r--r--include/linux/mfd/wm831x/core.h43
-rw-r--r--include/linux/mfd/wm831x/pdata.h1
-rw-r--r--include/linux/mfd/wm8350/core.h14
-rw-r--r--include/linux/mfd/wm8350/gpio.h18
13 files changed, 1163 insertions, 260 deletions
diff --git a/include/linux/i2c/tps65010.h b/include/linux/i2c/tps65010.h
index 918c5354d9b8..08aa92278d71 100644
--- a/include/linux/i2c/tps65010.h
+++ b/include/linux/i2c/tps65010.h
@@ -72,6 +72,21 @@
72#define TPS_VDCDC1 0x0c 72#define TPS_VDCDC1 0x0c
73# define TPS_ENABLE_LP (1 << 3) 73# define TPS_ENABLE_LP (1 << 3)
74#define TPS_VDCDC2 0x0d 74#define TPS_VDCDC2 0x0d
75# define TPS_LP_COREOFF (1 << 7)
76# define TPS_VCORE_1_8V (7<<4)
77# define TPS_VCORE_1_5V (6 << 4)
78# define TPS_VCORE_1_4V (5 << 4)
79# define TPS_VCORE_1_3V (4 << 4)
80# define TPS_VCORE_1_2V (3 << 4)
81# define TPS_VCORE_1_1V (2 << 4)
82# define TPS_VCORE_1_0V (1 << 4)
83# define TPS_VCORE_0_85V (0 << 4)
84# define TPS_VCORE_LP_1_2V (3 << 2)
85# define TPS_VCORE_LP_1_1V (2 << 2)
86# define TPS_VCORE_LP_1_0V (1 << 2)
87# define TPS_VCORE_LP_0_85V (0 << 2)
88# define TPS_VIB (1 << 1)
89# define TPS_VCORE_DISCH (1 << 0)
75#define TPS_VREGS1 0x0e 90#define TPS_VREGS1 0x0e
76# define TPS_LDO2_ENABLE (1 << 7) 91# define TPS_LDO2_ENABLE (1 << 7)
77# define TPS_LDO2_OFF (1 << 6) 92# define TPS_LDO2_OFF (1 << 6)
@@ -152,6 +167,10 @@ extern int tps65010_config_vregs1(unsigned value);
152 */ 167 */
153extern int tps65013_set_low_pwr(unsigned mode); 168extern int tps65013_set_low_pwr(unsigned mode);
154 169
170/* tps65010_set_vdcdc2
171 * value to be written to VDCDC2
172 */
173extern int tps65010_config_vdcdc2(unsigned value);
155 174
156struct i2c_client; 175struct i2c_client;
157 176
diff --git a/include/linux/i2c/twl4030.h b/include/linux/i2c/twl.h
index 5306a759cbde..bf1c5be1f5b6 100644
--- a/include/linux/i2c/twl4030.h
+++ b/include/linux/i2c/twl.h
@@ -22,8 +22,8 @@
22 * 22 *
23 */ 23 */
24 24
25#ifndef __TWL4030_H_ 25#ifndef __TWL_H_
26#define __TWL4030_H_ 26#define __TWL_H_
27 27
28#include <linux/types.h> 28#include <linux/types.h>
29#include <linux/input/matrix_keypad.h> 29#include <linux/input/matrix_keypad.h>
@@ -61,28 +61,112 @@
61#define TWL4030_MODULE_PWMA 0x0E 61#define TWL4030_MODULE_PWMA 0x0E
62#define TWL4030_MODULE_PWMB 0x0F 62#define TWL4030_MODULE_PWMB 0x0F
63 63
64#define TWL5031_MODULE_ACCESSORY 0x10
65#define TWL5031_MODULE_INTERRUPTS 0x11
66
64/* Slave 3 (i2c address 0x4b) */ 67/* Slave 3 (i2c address 0x4b) */
65#define TWL4030_MODULE_BACKUP 0x10 68#define TWL4030_MODULE_BACKUP 0x12
66#define TWL4030_MODULE_INT 0x11 69#define TWL4030_MODULE_INT 0x13
67#define TWL4030_MODULE_PM_MASTER 0x12 70#define TWL4030_MODULE_PM_MASTER 0x14
68#define TWL4030_MODULE_PM_RECEIVER 0x13 71#define TWL4030_MODULE_PM_RECEIVER 0x15
69#define TWL4030_MODULE_RTC 0x14 72#define TWL4030_MODULE_RTC 0x16
70#define TWL4030_MODULE_SECURED_REG 0x15 73#define TWL4030_MODULE_SECURED_REG 0x17
74
75#define TWL_MODULE_USB TWL4030_MODULE_USB
76#define TWL_MODULE_AUDIO_VOICE TWL4030_MODULE_AUDIO_VOICE
77#define TWL_MODULE_PIH TWL4030_MODULE_PIH
78#define TWL_MODULE_MADC TWL4030_MODULE_MADC
79#define TWL_MODULE_MAIN_CHARGE TWL4030_MODULE_MAIN_CHARGE
80#define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
81#define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
82#define TWL_MODULE_RTC TWL4030_MODULE_RTC
83
84#define GPIO_INTR_OFFSET 0
85#define KEYPAD_INTR_OFFSET 1
86#define BCI_INTR_OFFSET 2
87#define MADC_INTR_OFFSET 3
88#define USB_INTR_OFFSET 4
89#define BCI_PRES_INTR_OFFSET 9
90#define USB_PRES_INTR_OFFSET 10
91#define RTC_INTR_OFFSET 11
92
93/*
94 * Offset from TWL6030_IRQ_BASE / pdata->irq_base
95 */
96#define PWR_INTR_OFFSET 0
97#define HOTDIE_INTR_OFFSET 12
98#define SMPSLDO_INTR_OFFSET 13
99#define BATDETECT_INTR_OFFSET 14
100#define SIMDETECT_INTR_OFFSET 15
101#define MMCDETECT_INTR_OFFSET 16
102#define GASGAUGE_INTR_OFFSET 17
103#define USBOTG_INTR_OFFSET 4
104#define CHARGER_INTR_OFFSET 2
105#define RSV_INTR_OFFSET 0
106
107/* INT register offsets */
108#define REG_INT_STS_A 0x00
109#define REG_INT_STS_B 0x01
110#define REG_INT_STS_C 0x02
111
112#define REG_INT_MSK_LINE_A 0x03
113#define REG_INT_MSK_LINE_B 0x04
114#define REG_INT_MSK_LINE_C 0x05
115
116#define REG_INT_MSK_STS_A 0x06
117#define REG_INT_MSK_STS_B 0x07
118#define REG_INT_MSK_STS_C 0x08
119
120/* MASK INT REG GROUP A */
121#define TWL6030_PWR_INT_MASK 0x07
122#define TWL6030_RTC_INT_MASK 0x18
123#define TWL6030_HOTDIE_INT_MASK 0x20
124#define TWL6030_SMPSLDOA_INT_MASK 0xC0
125
126/* MASK INT REG GROUP B */
127#define TWL6030_SMPSLDOB_INT_MASK 0x01
128#define TWL6030_BATDETECT_INT_MASK 0x02
129#define TWL6030_SIMDETECT_INT_MASK 0x04
130#define TWL6030_MMCDETECT_INT_MASK 0x08
131#define TWL6030_GPADC_INT_MASK 0x60
132#define TWL6030_GASGAUGE_INT_MASK 0x80
133
134/* MASK INT REG GROUP C */
135#define TWL6030_USBOTG_INT_MASK 0x0F
136#define TWL6030_CHARGER_CTRL_INT_MASK 0x10
137#define TWL6030_CHARGER_FAULT_INT_MASK 0x60
138
139
140#define TWL4030_CLASS_ID 0x4030
141#define TWL6030_CLASS_ID 0x6030
142unsigned int twl_rev(void);
143#define GET_TWL_REV (twl_rev())
144#define TWL_CLASS_IS(class, id) \
145static inline int twl_class_is_ ##class(void) \
146{ \
147 return ((id) == (GET_TWL_REV)) ? 1 : 0; \
148}
149
150TWL_CLASS_IS(4030, TWL4030_CLASS_ID)
151TWL_CLASS_IS(6030, TWL6030_CLASS_ID)
71 152
72/* 153/*
73 * Read and write single 8-bit registers 154 * Read and write single 8-bit registers
74 */ 155 */
75int twl4030_i2c_write_u8(u8 mod_no, u8 val, u8 reg); 156int twl_i2c_write_u8(u8 mod_no, u8 val, u8 reg);
76int twl4030_i2c_read_u8(u8 mod_no, u8 *val, u8 reg); 157int twl_i2c_read_u8(u8 mod_no, u8 *val, u8 reg);
77 158
78/* 159/*
79 * Read and write several 8-bit registers at once. 160 * Read and write several 8-bit registers at once.
80 * 161 *
81 * IMPORTANT: For twl4030_i2c_write(), allocate num_bytes + 1 162 * IMPORTANT: For twl_i2c_write(), allocate num_bytes + 1
82 * for the value, and populate your data starting at offset 1. 163 * for the value, and populate your data starting at offset 1.
83 */ 164 */
84int twl4030_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 165int twl_i2c_write(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
85int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes); 166int twl_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
167
168int twl6030_interrupt_unmask(u8 bit_mask, u8 offset);
169int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
86 170
87/*----------------------------------------------------------------------*/ 171/*----------------------------------------------------------------------*/
88 172
@@ -221,6 +305,38 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
221 305
222/*----------------------------------------------------------------------*/ 306/*----------------------------------------------------------------------*/
223 307
308/*
309 * Accessory Interrupts
310 */
311#define TWL5031_ACIIMR_LSB 0x05
312#define TWL5031_ACIIMR_MSB 0x06
313#define TWL5031_ACIIDR_LSB 0x07
314#define TWL5031_ACIIDR_MSB 0x08
315#define TWL5031_ACCISR1 0x0F
316#define TWL5031_ACCIMR1 0x10
317#define TWL5031_ACCISR2 0x11
318#define TWL5031_ACCIMR2 0x12
319#define TWL5031_ACCSIR 0x13
320#define TWL5031_ACCEDR1 0x14
321#define TWL5031_ACCSIHCTRL 0x15
322
323/*----------------------------------------------------------------------*/
324
325/*
326 * Battery Charger Controller
327 */
328
329#define TWL5031_INTERRUPTS_BCIISR1 0x0
330#define TWL5031_INTERRUPTS_BCIIMR1 0x1
331#define TWL5031_INTERRUPTS_BCIISR2 0x2
332#define TWL5031_INTERRUPTS_BCIIMR2 0x3
333#define TWL5031_INTERRUPTS_BCISIR 0x4
334#define TWL5031_INTERRUPTS_BCIEDR1 0x5
335#define TWL5031_INTERRUPTS_BCIEDR2 0x6
336#define TWL5031_INTERRUPTS_BCISIHCTRL 0x7
337
338/*----------------------------------------------------------------------*/
339
224/* Power bus message definitions */ 340/* Power bus message definitions */
225 341
226/* The TWL4030/5030 splits its power-management resources (the various 342/* The TWL4030/5030 splits its power-management resources (the various
@@ -250,6 +366,7 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
250 366
251#define RES_TYPE_ALL 0x7 367#define RES_TYPE_ALL 0x7
252 368
369/* Resource states */
253#define RES_STATE_WRST 0xF 370#define RES_STATE_WRST 0xF
254#define RES_STATE_ACTIVE 0xE 371#define RES_STATE_ACTIVE 0xE
255#define RES_STATE_SLEEP 0x8 372#define RES_STATE_SLEEP 0x8
@@ -310,8 +427,18 @@ int twl4030_i2c_read(u8 mod_no, u8 *value, u8 reg, unsigned num_bytes);
310#define MSG_SINGULAR(devgrp, id, state) \ 427#define MSG_SINGULAR(devgrp, id, state) \
311 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state)) 428 ((devgrp) << 13 | 0 << 12 | (id) << 4 | (state))
312 429
430#define MSG_BROADCAST_ALL(devgrp, state) \
431 ((devgrp) << 5 | (state))
432
433#define MSG_BROADCAST_REF MSG_BROADCAST_ALL
434#define MSG_BROADCAST_PROV MSG_BROADCAST_ALL
435#define MSG_BROADCAST__CLK_RST MSG_BROADCAST_ALL
313/*----------------------------------------------------------------------*/ 436/*----------------------------------------------------------------------*/
314 437
438struct twl4030_clock_init_data {
439 bool ck32k_lowpwr_enable;
440};
441
315struct twl4030_bci_platform_data { 442struct twl4030_bci_platform_data {
316 int *battery_tmp_tbl; 443 int *battery_tmp_tbl;
317 unsigned int tblsize; 444 unsigned int tblsize;
@@ -391,12 +518,15 @@ struct twl4030_resconfig {
391 u8 devgroup; /* Processor group that Power resource belongs to */ 518 u8 devgroup; /* Processor group that Power resource belongs to */
392 u8 type; /* Power resource addressed, 6 / broadcast message */ 519 u8 type; /* Power resource addressed, 6 / broadcast message */
393 u8 type2; /* Power resource addressed, 3 / broadcast message */ 520 u8 type2; /* Power resource addressed, 3 / broadcast message */
521 u8 remap_off; /* off state remapping */
522 u8 remap_sleep; /* sleep state remapping */
394}; 523};
395 524
396struct twl4030_power_data { 525struct twl4030_power_data {
397 struct twl4030_script **scripts; 526 struct twl4030_script **scripts;
398 unsigned num; 527 unsigned num;
399 struct twl4030_resconfig *resource_config; 528 struct twl4030_resconfig *resource_config;
529#define TWL4030_RESCONFIG_UNDEF ((u8)-1)
400}; 530};
401 531
402extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts); 532extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
@@ -421,6 +551,7 @@ struct twl4030_codec_data {
421 551
422struct twl4030_platform_data { 552struct twl4030_platform_data {
423 unsigned irq_base, irq_end; 553 unsigned irq_base, irq_end;
554 struct twl4030_clock_init_data *clock;
424 struct twl4030_bci_platform_data *bci; 555 struct twl4030_bci_platform_data *bci;
425 struct twl4030_gpio_platform_data *gpio; 556 struct twl4030_gpio_platform_data *gpio;
426 struct twl4030_madc_platform_data *madc; 557 struct twl4030_madc_platform_data *madc;
@@ -429,19 +560,31 @@ struct twl4030_platform_data {
429 struct twl4030_power_data *power; 560 struct twl4030_power_data *power;
430 struct twl4030_codec_data *codec; 561 struct twl4030_codec_data *codec;
431 562
432 /* LDO regulators */ 563 /* Common LDO regulators for TWL4030/TWL6030 */
433 struct regulator_init_data *vdac; 564 struct regulator_init_data *vdac;
565 struct regulator_init_data *vaux1;
566 struct regulator_init_data *vaux2;
567 struct regulator_init_data *vaux3;
568 /* TWL4030 LDO regulators */
434 struct regulator_init_data *vpll1; 569 struct regulator_init_data *vpll1;
435 struct regulator_init_data *vpll2; 570 struct regulator_init_data *vpll2;
436 struct regulator_init_data *vmmc1; 571 struct regulator_init_data *vmmc1;
437 struct regulator_init_data *vmmc2; 572 struct regulator_init_data *vmmc2;
438 struct regulator_init_data *vsim; 573 struct regulator_init_data *vsim;
439 struct regulator_init_data *vaux1;
440 struct regulator_init_data *vaux2;
441 struct regulator_init_data *vaux3;
442 struct regulator_init_data *vaux4; 574 struct regulator_init_data *vaux4;
443 575 struct regulator_init_data *vio;
444 /* REVISIT more to come ... _nothing_ should be hard-wired */ 576 struct regulator_init_data *vdd1;
577 struct regulator_init_data *vdd2;
578 struct regulator_init_data *vintana1;
579 struct regulator_init_data *vintana2;
580 struct regulator_init_data *vintdig;
581 /* TWL6030 LDO regulators */
582 struct regulator_init_data *vmmc;
583 struct regulator_init_data *vpp;
584 struct regulator_init_data *vusim;
585 struct regulator_init_data *vana;
586 struct regulator_init_data *vcxio;
587 struct regulator_init_data *vusb;
445}; 588};
446 589
447/*----------------------------------------------------------------------*/ 590/*----------------------------------------------------------------------*/
@@ -473,6 +616,7 @@ int twl4030_sih_setup(int module);
473 * VIO is generally fixed. 616 * VIO is generally fixed.
474 */ 617 */
475 618
619/* TWL4030 SMPS/LDO's */
476/* EXTERNAL dc-to-dc buck converters */ 620/* EXTERNAL dc-to-dc buck converters */
477#define TWL4030_REG_VDD1 0 621#define TWL4030_REG_VDD1 0
478#define TWL4030_REG_VDD2 1 622#define TWL4030_REG_VDD2 1
@@ -499,4 +643,31 @@ int twl4030_sih_setup(int module);
499#define TWL4030_REG_VUSB1V8 18 643#define TWL4030_REG_VUSB1V8 18
500#define TWL4030_REG_VUSB3V1 19 644#define TWL4030_REG_VUSB3V1 19
501 645
646/* TWL6030 SMPS/LDO's */
647/* EXTERNAL dc-to-dc buck convertor contollable via SR */
648#define TWL6030_REG_VDD1 30
649#define TWL6030_REG_VDD2 31
650#define TWL6030_REG_VDD3 32
651
652/* Non SR compliant dc-to-dc buck convertors */
653#define TWL6030_REG_VMEM 33
654#define TWL6030_REG_V2V1 34
655#define TWL6030_REG_V1V29 35
656#define TWL6030_REG_V1V8 36
657
658/* EXTERNAL LDOs */
659#define TWL6030_REG_VAUX1_6030 37
660#define TWL6030_REG_VAUX2_6030 38
661#define TWL6030_REG_VAUX3_6030 39
662#define TWL6030_REG_VMMC 40
663#define TWL6030_REG_VPP 41
664#define TWL6030_REG_VUSIM 42
665#define TWL6030_REG_VANA 43
666#define TWL6030_REG_VCXIO 44
667#define TWL6030_REG_VDAC 45
668#define TWL6030_REG_VUSB 46
669
670/* INTERNAL LDOs */
671#define TWL6030_REG_VRTC 47
672
502#endif /* End of __TWL4030_H */ 673#endif /* End of __TWL4030_H */
diff --git a/include/linux/mfd/88pm8607.h b/include/linux/mfd/88pm8607.h
new file mode 100644
index 000000000000..f41b428d2cec
--- /dev/null
+++ b/include/linux/mfd/88pm8607.h
@@ -0,0 +1,217 @@
1/*
2 * Marvell 88PM8607 Interface
3 *
4 * Copyright (C) 2009 Marvell International Ltd.
5 * Haojian Zhuang <haojian.zhuang@marvell.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __LINUX_MFD_88PM8607_H
13#define __LINUX_MFD_88PM8607_H
14
15enum {
16 PM8607_ID_BUCK1 = 0,
17 PM8607_ID_BUCK2,
18 PM8607_ID_BUCK3,
19
20 PM8607_ID_LDO1,
21 PM8607_ID_LDO2,
22 PM8607_ID_LDO3,
23 PM8607_ID_LDO4,
24 PM8607_ID_LDO5,
25 PM8607_ID_LDO6,
26 PM8607_ID_LDO7,
27 PM8607_ID_LDO8,
28 PM8607_ID_LDO9,
29 PM8607_ID_LDO10,
30 PM8607_ID_LDO12,
31 PM8607_ID_LDO14,
32
33 PM8607_ID_RG_MAX,
34};
35
36#define CHIP_ID (0x40)
37#define CHIP_ID_MASK (0xF8)
38
39/* Interrupt Registers */
40#define PM8607_STATUS_1 (0x01)
41#define PM8607_STATUS_2 (0x02)
42#define PM8607_INT_STATUS1 (0x03)
43#define PM8607_INT_STATUS2 (0x04)
44#define PM8607_INT_STATUS3 (0x05)
45#define PM8607_INT_MASK_1 (0x06)
46#define PM8607_INT_MASK_2 (0x07)
47#define PM8607_INT_MASK_3 (0x08)
48
49/* Regulator Control Registers */
50#define PM8607_LDO1 (0x10)
51#define PM8607_LDO2 (0x11)
52#define PM8607_LDO3 (0x12)
53#define PM8607_LDO4 (0x13)
54#define PM8607_LDO5 (0x14)
55#define PM8607_LDO6 (0x15)
56#define PM8607_LDO7 (0x16)
57#define PM8607_LDO8 (0x17)
58#define PM8607_LDO9 (0x18)
59#define PM8607_LDO10 (0x19)
60#define PM8607_LDO12 (0x1A)
61#define PM8607_LDO14 (0x1B)
62#define PM8607_SLEEP_MODE1 (0x1C)
63#define PM8607_SLEEP_MODE2 (0x1D)
64#define PM8607_SLEEP_MODE3 (0x1E)
65#define PM8607_SLEEP_MODE4 (0x1F)
66#define PM8607_GO (0x20)
67#define PM8607_SLEEP_BUCK1 (0x21)
68#define PM8607_SLEEP_BUCK2 (0x22)
69#define PM8607_SLEEP_BUCK3 (0x23)
70#define PM8607_BUCK1 (0x24)
71#define PM8607_BUCK2 (0x25)
72#define PM8607_BUCK3 (0x26)
73#define PM8607_BUCK_CONTROLS (0x27)
74#define PM8607_SUPPLIES_EN11 (0x2B)
75#define PM8607_SUPPLIES_EN12 (0x2C)
76#define PM8607_GROUP1 (0x2D)
77#define PM8607_GROUP2 (0x2E)
78#define PM8607_GROUP3 (0x2F)
79#define PM8607_GROUP4 (0x30)
80#define PM8607_GROUP5 (0x31)
81#define PM8607_GROUP6 (0x32)
82#define PM8607_SUPPLIES_EN21 (0x33)
83#define PM8607_SUPPLIES_EN22 (0x34)
84
85/* RTC Control Registers */
86#define PM8607_RTC1 (0xA0)
87#define PM8607_RTC_COUNTER1 (0xA1)
88#define PM8607_RTC_COUNTER2 (0xA2)
89#define PM8607_RTC_COUNTER3 (0xA3)
90#define PM8607_RTC_COUNTER4 (0xA4)
91#define PM8607_RTC_EXPIRE1 (0xA5)
92#define PM8607_RTC_EXPIRE2 (0xA6)
93#define PM8607_RTC_EXPIRE3 (0xA7)
94#define PM8607_RTC_EXPIRE4 (0xA8)
95#define PM8607_RTC_TRIM1 (0xA9)
96#define PM8607_RTC_TRIM2 (0xAA)
97#define PM8607_RTC_TRIM3 (0xAB)
98#define PM8607_RTC_TRIM4 (0xAC)
99#define PM8607_RTC_MISC1 (0xAD)
100#define PM8607_RTC_MISC2 (0xAE)
101#define PM8607_RTC_MISC3 (0xAF)
102
103/* Misc Registers */
104#define PM8607_CHIP_ID (0x00)
105#define PM8607_LDO1 (0x10)
106#define PM8607_DVC3 (0x26)
107#define PM8607_MISC1 (0x40)
108
109/* bit definitions for PM8607 events */
110#define PM8607_EVENT_ONKEY (1 << 0)
111#define PM8607_EVENT_EXTON (1 << 1)
112#define PM8607_EVENT_CHG (1 << 2)
113#define PM8607_EVENT_BAT (1 << 3)
114#define PM8607_EVENT_RTC (1 << 4)
115#define PM8607_EVENT_CC (1 << 5)
116#define PM8607_EVENT_VBAT (1 << 8)
117#define PM8607_EVENT_VCHG (1 << 9)
118#define PM8607_EVENT_VSYS (1 << 10)
119#define PM8607_EVENT_TINT (1 << 11)
120#define PM8607_EVENT_GPADC0 (1 << 12)
121#define PM8607_EVENT_GPADC1 (1 << 13)
122#define PM8607_EVENT_GPADC2 (1 << 14)
123#define PM8607_EVENT_GPADC3 (1 << 15)
124#define PM8607_EVENT_AUDIO_SHORT (1 << 16)
125#define PM8607_EVENT_PEN (1 << 17)
126#define PM8607_EVENT_HEADSET (1 << 18)
127#define PM8607_EVENT_HOOK (1 << 19)
128#define PM8607_EVENT_MICIN (1 << 20)
129#define PM8607_EVENT_CHG_TIMEOUT (1 << 21)
130#define PM8607_EVENT_CHG_DONE (1 << 22)
131#define PM8607_EVENT_CHG_FAULT (1 << 23)
132
133/* bit definitions of Status Query Interface */
134#define PM8607_STATUS_CC (1 << 3)
135#define PM8607_STATUS_PEN (1 << 4)
136#define PM8607_STATUS_HEADSET (1 << 5)
137#define PM8607_STATUS_HOOK (1 << 6)
138#define PM8607_STATUS_MICIN (1 << 7)
139#define PM8607_STATUS_ONKEY (1 << 8)
140#define PM8607_STATUS_EXTON (1 << 9)
141#define PM8607_STATUS_CHG (1 << 10)
142#define PM8607_STATUS_BAT (1 << 11)
143#define PM8607_STATUS_VBUS (1 << 12)
144#define PM8607_STATUS_OV (1 << 13)
145
146/* bit definitions of BUCK3 */
147#define PM8607_BUCK3_DOUBLE (1 << 6)
148
149/* bit definitions of Misc1 */
150#define PM8607_MISC1_PI2C (1 << 0)
151
152/* Interrupt Number in 88PM8607 */
153enum {
154 PM8607_IRQ_ONKEY = 0,
155 PM8607_IRQ_EXTON,
156 PM8607_IRQ_CHG,
157 PM8607_IRQ_BAT,
158 PM8607_IRQ_RTC,
159 PM8607_IRQ_VBAT = 8,
160 PM8607_IRQ_VCHG,
161 PM8607_IRQ_VSYS,
162 PM8607_IRQ_TINT,
163 PM8607_IRQ_GPADC0,
164 PM8607_IRQ_GPADC1,
165 PM8607_IRQ_GPADC2,
166 PM8607_IRQ_GPADC3,
167 PM8607_IRQ_AUDIO_SHORT = 16,
168 PM8607_IRQ_PEN,
169 PM8607_IRQ_HEADSET,
170 PM8607_IRQ_HOOK,
171 PM8607_IRQ_MICIN,
172 PM8607_IRQ_CHG_FAIL,
173 PM8607_IRQ_CHG_DONE,
174 PM8607_IRQ_CHG_FAULT,
175};
176
177enum {
178 PM8607_CHIP_A0 = 0x40,
179 PM8607_CHIP_A1 = 0x41,
180 PM8607_CHIP_B0 = 0x48,
181};
182
183
184struct pm8607_chip {
185 struct device *dev;
186 struct mutex io_lock;
187 struct i2c_client *client;
188
189 int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest);
190 int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src);
191
192 int buck3_double; /* DVC ramp slope double */
193 unsigned char chip_id;
194
195};
196
197#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */
198
199enum {
200 GI2C_PORT = 0,
201 PI2C_PORT,
202};
203
204struct pm8607_platform_data {
205 int i2c_port; /* Controlled by GI2C or PI2C */
206 struct regulator_init_data *regulator[PM8607_MAX_REGULATOR];
207};
208
209extern int pm8607_reg_read(struct pm8607_chip *, int);
210extern int pm8607_reg_write(struct pm8607_chip *, int, unsigned char);
211extern int pm8607_bulk_read(struct pm8607_chip *, int, int,
212 unsigned char *);
213extern int pm8607_bulk_write(struct pm8607_chip *, int, int,
214 unsigned char *);
215extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char,
216 unsigned char);
217#endif /* __LINUX_MFD_88PM8607_H */
diff --git a/include/linux/mfd/ab4500.h b/include/linux/mfd/ab4500.h
new file mode 100644
index 000000000000..a42a7033ae53
--- /dev/null
+++ b/include/linux/mfd/ab4500.h
@@ -0,0 +1,262 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 * AB4500 device core funtions, for client access
11 */
12#ifndef MFD_AB4500_H
13#define MFD_AB4500_H
14
15#include <linux/device.h>
16
17/*
18 * AB4500 bank addresses
19 */
20#define AB4500_SYS_CTRL1_BLOCK 0x1
21#define AB4500_SYS_CTRL2_BLOCK 0x2
22#define AB4500_REGU_CTRL1 0x3
23#define AB4500_REGU_CTRL2 0x4
24#define AB4500_USB 0x5
25#define AB4500_TVOUT 0x6
26#define AB4500_DBI 0x7
27#define AB4500_ECI_AV_ACC 0x8
28#define AB4500_RESERVED 0x9
29#define AB4500_GPADC 0xA
30#define AB4500_CHARGER 0xB
31#define AB4500_GAS_GAUGE 0xC
32#define AB4500_AUDIO 0xD
33#define AB4500_INTERRUPT 0xE
34#define AB4500_RTC 0xF
35#define AB4500_MISC 0x10
36#define AB4500_DEBUG 0x12
37#define AB4500_PROD_TEST 0x13
38#define AB4500_OTP_EMUL 0x15
39
40/*
41 * System control 1 register offsets.
42 * Bank = 0x01
43 */
44#define AB4500_TURNON_STAT_REG 0x0100
45#define AB4500_RESET_STAT_REG 0x0101
46#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102
47
48#define AB4500_FSM_STAT1_REG 0x0140
49#define AB4500_FSM_STAT2_REG 0x0141
50#define AB4500_SYSCLK_REQ_STAT_REG 0x0142
51#define AB4500_USB_STAT1_REG 0x0143
52#define AB4500_USB_STAT2_REG 0x0144
53#define AB4500_STATUS_SPARE1_REG 0x0145
54#define AB4500_STATUS_SPARE2_REG 0x0146
55
56#define AB4500_CTRL1_REG 0x0180
57#define AB4500_CTRL2_REG 0x0181
58
59/*
60 * System control 2 register offsets.
61 * bank = 0x02
62 */
63#define AB4500_CTRL3_REG 0x0200
64#define AB4500_MAIN_WDOG_CTRL_REG 0x0201
65#define AB4500_MAIN_WDOG_TIMER_REG 0x0202
66#define AB4500_LOW_BAT_REG 0x0203
67#define AB4500_BATT_OK_REG 0x0204
68#define AB4500_SYSCLK_TIMER_REG 0x0205
69#define AB4500_SMPSCLK_CTRL_REG 0x0206
70#define AB4500_SMPSCLK_SEL1_REG 0x0207
71#define AB4500_SMPSCLK_SEL2_REG 0x0208
72#define AB4500_SMPSCLK_SEL3_REG 0x0209
73#define AB4500_SYSULPCLK_CONF_REG 0x020A
74#define AB4500_SYSULPCLK_CTRL1_REG 0x020B
75#define AB4500_SYSCLK_CTRL_REG 0x020C
76#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D
77#define AB4500_SYSCLK_REQ_VALID_REG 0x020E
78#define AB4500_SYSCTRL_SPARE_REG 0x020F
79#define AB4500_PAD_CONF_REG 0x0210
80
81/*
82 * Regu control1 register offsets
83 * Bank = 0x03
84 */
85#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300
86#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301
87#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302
88#define AB4500_REGU_REQ_CTRL1_REG 0x0303
89#define AB4500_REGU_REQ_CTRL2_REG 0x0304
90#define AB4500_REGU_REQ_CTRL3_REG 0x0305
91#define AB4500_REGU_REQ_CTRL4_REG 0x0306
92#define AB4500_REGU_MISC1_REG 0x0380
93#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381
94#define AB4500_REGU_VUSB_CTRL_REG 0x0382
95#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383
96#define AB4500_REGU_CTRL1_SPARE_REG 0x0384
97
98/*
99 * Regu control2 Vmod register offsets
100 */
101#define AB4500_REGU_VMOD_REGU_REG 0x0440
102#define AB4500_REGU_VMOD_SEL1_REG 0x0441
103#define AB4500_REGU_VMOD_SEL2_REG 0x0442
104#define AB4500_REGU_CTRL_DISCH_REG 0x0443
105#define AB4500_REGU_CTRL_DISCH2_REG 0x0444
106
107/*
108 * USB/ULPI register offsets
109 * Bank : 0x5
110 */
111#define AB4500_USB_LINE_STAT_REG 0x0580
112#define AB4500_USB_LINE_CTRL1_REG 0x0581
113#define AB4500_USB_LINE_CTRL2_REG 0x0582
114#define AB4500_USB_LINE_CTRL3_REG 0x0583
115#define AB4500_USB_LINE_CTRL4_REG 0x0584
116#define AB4500_USB_LINE_CTRL5_REG 0x0585
117#define AB4500_USB_OTG_CTRL_REG 0x0587
118#define AB4500_USB_OTG_STAT_REG 0x0588
119#define AB4500_USB_OTG_STAT_REG 0x0588
120#define AB4500_USB_CTRL_SPARE_REG 0x0589
121#define AB4500_USB_PHY_CTRL_REG 0x058A
122
123/*
124 * TVOUT / CTRL register offsets
125 * Bank : 0x06
126 */
127#define AB4500_TVOUT_CTRL_REG 0x0680
128
129/*
130 * DBI register offsets
131 * Bank : 0x07
132 */
133#define AB4500_DBI_REG1_REG 0x0700
134#define AB4500_DBI_REG2_REG 0x0701
135
136/*
137 * ECI regsiter offsets
138 * Bank : 0x08
139 */
140#define AB4500_ECI_CTRL_REG 0x0800
141#define AB4500_ECI_HOOKLEVEL_REG 0x0801
142#define AB4500_ECI_DATAOUT_REG 0x0802
143#define AB4500_ECI_DATAIN_REG 0x0803
144
145/*
146 * AV Connector register offsets
147 * Bank : 0x08
148 */
149#define AB4500_AV_CONN_REG 0x0840
150
151/*
152 * Accessory detection register offsets
153 * Bank : 0x08
154 */
155#define AB4500_ACC_DET_DB1_REG 0x0880
156#define AB4500_ACC_DET_DB2_REG 0x0881
157
158/*
159 * GPADC register offsets
160 * Bank : 0x0A
161 */
162#define AB4500_GPADC_CTRL1_REG 0x0A00
163#define AB4500_GPADC_CTRL2_REG 0x0A01
164#define AB4500_GPADC_CTRL3_REG 0x0A02
165#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03
166#define AB4500_GPADC_STAT_REG 0x0A04
167#define AB4500_GPADC_MANDATAL_REG 0x0A05
168#define AB4500_GPADC_MANDATAH_REG 0x0A06
169#define AB4500_GPADC_AUTODATAL_REG 0x0A07
170#define AB4500_GPADC_AUTODATAH_REG 0x0A08
171#define AB4500_GPADC_MUX_CTRL_REG 0x0A09
172
173/*
174 * Charger / status register offfsets
175 * Bank : 0x0B
176 */
177#define AB4500_CH_STATUS1_REG 0x0B00
178#define AB4500_CH_STATUS2_REG 0x0B01
179#define AB4500_CH_USBCH_STAT1_REG 0x0B02
180#define AB4500_CH_USBCH_STAT2_REG 0x0B03
181#define AB4500_CH_FSM_STAT_REG 0x0B04
182#define AB4500_CH_STAT_REG 0x0B05
183
184/*
185 * Charger / control register offfsets
186 * Bank : 0x0B
187 */
188#define AB4500_CH_VOLT_LVL_REG 0x0B40
189
190/*
191 * Charger / main control register offfsets
192 * Bank : 0x0B
193 */
194#define AB4500_MCH_CTRL1 0x0B80
195#define AB4500_MCH_CTRL2 0x0B81
196#define AB4500_MCH_IPT_CURLVL_REG 0x0B82
197#define AB4500_CH_WD_REG 0x0B83
198
199/*
200 * Charger / USB control register offsets
201 * Bank : 0x0B
202 */
203#define AB4500_USBCH_CTRL1_REG 0x0BC0
204#define AB4500_USBCH_CTRL2_REG 0x0BC1
205#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2
206
207/*
208 * RTC bank register offsets
209 * Bank : 0xF
210 */
211#define AB4500_RTC_SOFF_STAT_REG 0x0F00
212#define AB4500_RTC_CC_CONF_REG 0x0F01
213#define AB4500_RTC_READ_REQ_REG 0x0F02
214#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03
215#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04
216#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05
217#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06
218#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07
219#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08
220#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09
221#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A
222#define AB4500_RTC_STAT_REG 0x0F0B
223#define AB4500_RTC_BKUP_CHG_REG 0x0F0C
224#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D
225#define AB4500_RTC_CALIB_REG 0x0F0E
226#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F
227
228/*
229 * PWM Out generators
230 * Bank: 0x10
231 */
232#define AB4500_PWM_OUT_CTRL1_REG 0x1060
233#define AB4500_PWM_OUT_CTRL2_REG 0x1061
234#define AB4500_PWM_OUT_CTRL3_REG 0x1062
235#define AB4500_PWM_OUT_CTRL4_REG 0x1063
236#define AB4500_PWM_OUT_CTRL5_REG 0x1064
237#define AB4500_PWM_OUT_CTRL6_REG 0x1065
238#define AB4500_PWM_OUT_CTRL7_REG 0x1066
239
240#define AB4500_I2C_PAD_CTRL_REG 0x1067
241#define AB4500_REV_REG 0x1080
242
243/**
244 * struct ab4500
245 * @spi: spi device structure
246 * @tx_buf: transmit buffer
247 * @rx_buf: receive buffer
248 * @lock: sync primitive
249 */
250struct ab4500 {
251 struct spi_device *spi;
252 unsigned long tx_buf[4];
253 unsigned long rx_buf[4];
254 struct mutex lock;
255};
256
257int ab4500_write(struct ab4500 *ab4500, unsigned char block,
258 unsigned long addr, unsigned char data);
259int ab4500_read(struct ab4500 *ab4500, unsigned char block,
260 unsigned long addr);
261
262#endif /* MFD_AB4500_H */
diff --git a/include/linux/mfd/adp5520.h b/include/linux/mfd/adp5520.h
new file mode 100644
index 000000000000..ac37558a4673
--- /dev/null
+++ b/include/linux/mfd/adp5520.h
@@ -0,0 +1,299 @@
1/*
2 * Definitions and platform data for Analog Devices
3 * ADP5520/ADP5501 MFD PMICs (Backlight, LED, GPIO and Keys)
4 *
5 * Copyright 2009 Analog Devices Inc.
6 *
7 * Licensed under the GPL-2 or later.
8 */
9
10
11#ifndef __LINUX_MFD_ADP5520_H
12#define __LINUX_MFD_ADP5520_H
13
14#define ID_ADP5520 5520
15#define ID_ADP5501 5501
16
17/*
18 * ADP5520/ADP5501 Register Map
19 */
20
21#define ADP5520_MODE_STATUS 0x00
22#define ADP5520_INTERRUPT_ENABLE 0x01
23#define ADP5520_BL_CONTROL 0x02
24#define ADP5520_BL_TIME 0x03
25#define ADP5520_BL_FADE 0x04
26#define ADP5520_DAYLIGHT_MAX 0x05
27#define ADP5520_DAYLIGHT_DIM 0x06
28#define ADP5520_OFFICE_MAX 0x07
29#define ADP5520_OFFICE_DIM 0x08
30#define ADP5520_DARK_MAX 0x09
31#define ADP5520_DARK_DIM 0x0A
32#define ADP5520_BL_VALUE 0x0B
33#define ADP5520_ALS_CMPR_CFG 0x0C
34#define ADP5520_L2_TRIP 0x0D
35#define ADP5520_L2_HYS 0x0E
36#define ADP5520_L3_TRIP 0x0F
37#define ADP5520_L3_HYS 0x10
38#define ADP5520_LED_CONTROL 0x11
39#define ADP5520_LED_TIME 0x12
40#define ADP5520_LED_FADE 0x13
41#define ADP5520_LED1_CURRENT 0x14
42#define ADP5520_LED2_CURRENT 0x15
43#define ADP5520_LED3_CURRENT 0x16
44
45/*
46 * ADP5520 Register Map
47 */
48
49#define ADP5520_GPIO_CFG_1 0x17
50#define ADP5520_GPIO_CFG_2 0x18
51#define ADP5520_GPIO_IN 0x19
52#define ADP5520_GPIO_OUT 0x1A
53#define ADP5520_GPIO_INT_EN 0x1B
54#define ADP5520_GPIO_INT_STAT 0x1C
55#define ADP5520_GPIO_INT_LVL 0x1D
56#define ADP5520_GPIO_DEBOUNCE 0x1E
57#define ADP5520_GPIO_PULLUP 0x1F
58#define ADP5520_KP_INT_STAT_1 0x20
59#define ADP5520_KP_INT_STAT_2 0x21
60#define ADP5520_KR_INT_STAT_1 0x22
61#define ADP5520_KR_INT_STAT_2 0x23
62#define ADP5520_KEY_STAT_1 0x24
63#define ADP5520_KEY_STAT_2 0x25
64
65/*
66 * MODE_STATUS bits
67 */
68
69#define ADP5520_nSTNBY (1 << 7)
70#define ADP5520_BL_EN (1 << 6)
71#define ADP5520_DIM_EN (1 << 5)
72#define ADP5520_OVP_INT (1 << 4)
73#define ADP5520_CMPR_INT (1 << 3)
74#define ADP5520_GPI_INT (1 << 2)
75#define ADP5520_KR_INT (1 << 1)
76#define ADP5520_KP_INT (1 << 0)
77
78/*
79 * INTERRUPT_ENABLE bits
80 */
81
82#define ADP5520_AUTO_LD_EN (1 << 4)
83#define ADP5520_CMPR_IEN (1 << 3)
84#define ADP5520_OVP_IEN (1 << 2)
85#define ADP5520_KR_IEN (1 << 1)
86#define ADP5520_KP_IEN (1 << 0)
87
88/*
89 * BL_CONTROL bits
90 */
91
92#define ADP5520_BL_LVL ((x) << 5)
93#define ADP5520_BL_LAW ((x) << 4)
94#define ADP5520_BL_AUTO_ADJ (1 << 3)
95#define ADP5520_OVP_EN (1 << 2)
96#define ADP5520_FOVR (1 << 1)
97#define ADP5520_KP_BL_EN (1 << 0)
98
99/*
100 * ALS_CMPR_CFG bits
101 */
102
103#define ADP5520_L3_OUT (1 << 3)
104#define ADP5520_L2_OUT (1 << 2)
105#define ADP5520_L3_EN (1 << 1)
106
107#define ADP5020_MAX_BRIGHTNESS 0x7F
108
109#define FADE_VAL(in, out) ((0xF & (in)) | ((0xF & (out)) << 4))
110#define BL_CTRL_VAL(law, auto) (((1 & (auto)) << 3) | ((0x3 & (law)) << 4))
111#define ALS_CMPR_CFG_VAL(filt, l3_en) (((0x7 & filt) << 5) | l3_en)
112
113/*
114 * LEDs subdevice bits and masks
115 */
116
117#define ADP5520_01_MAXLEDS 3
118
119#define ADP5520_FLAG_LED_MASK 0x3
120#define ADP5520_FLAG_OFFT_SHIFT 8
121#define ADP5520_FLAG_OFFT_MASK 0x3
122
123#define ADP5520_R3_MODE (1 << 5)
124#define ADP5520_C3_MODE (1 << 4)
125#define ADP5520_LED_LAW (1 << 3)
126#define ADP5520_LED3_EN (1 << 2)
127#define ADP5520_LED2_EN (1 << 1)
128#define ADP5520_LED1_EN (1 << 0)
129
130/*
131 * GPIO subdevice bits and masks
132 */
133
134#define ADP5520_MAXGPIOS 8
135
136#define ADP5520_GPIO_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
137#define ADP5520_GPIO_C2 (1 << 6)
138#define ADP5520_GPIO_C1 (1 << 5)
139#define ADP5520_GPIO_C0 (1 << 4)
140#define ADP5520_GPIO_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
141#define ADP5520_GPIO_R2 (1 << 2)
142#define ADP5520_GPIO_R1 (1 << 1)
143#define ADP5520_GPIO_R0 (1 << 0)
144
145struct adp5520_gpio_platform_data {
146 unsigned gpio_start;
147 u8 gpio_en_mask;
148 u8 gpio_pullup_mask;
149};
150
151/*
152 * Keypad subdevice bits and masks
153 */
154
155#define ADP5520_MAXKEYS 16
156
157#define ADP5520_COL_C3 (1 << 7) /* LED2 or GPIO7 aka C3 */
158#define ADP5520_COL_C2 (1 << 6)
159#define ADP5520_COL_C1 (1 << 5)
160#define ADP5520_COL_C0 (1 << 4)
161#define ADP5520_ROW_R3 (1 << 3) /* LED3 or GPIO3 aka R3 */
162#define ADP5520_ROW_R2 (1 << 2)
163#define ADP5520_ROW_R1 (1 << 1)
164#define ADP5520_ROW_R0 (1 << 0)
165
166#define ADP5520_KEY(row, col) (col + row * 4)
167#define ADP5520_KEYMAPSIZE ADP5520_MAXKEYS
168
169struct adp5520_keys_platform_data {
170 int rows_en_mask; /* Number of rows */
171 int cols_en_mask; /* Number of columns */
172 const unsigned short *keymap; /* Pointer to keymap */
173 unsigned short keymapsize; /* Keymap size */
174 unsigned repeat:1; /* Enable key repeat */
175};
176
177
178/*
179 * LEDs subdevice platform data
180 */
181
182#define FLAG_ID_ADP5520_LED1_ADP5501_LED0 1 /* ADP5520 PIN ILED */
183#define FLAG_ID_ADP5520_LED2_ADP5501_LED1 2 /* ADP5520 PIN C3 */
184#define FLAG_ID_ADP5520_LED3_ADP5501_LED2 3 /* ADP5520 PIN R3 */
185
186#define ADP5520_LED_DIS_BLINK (0 << ADP5520_FLAG_OFFT_SHIFT)
187#define ADP5520_LED_OFFT_600ms (1 << ADP5520_FLAG_OFFT_SHIFT)
188#define ADP5520_LED_OFFT_800ms (2 << ADP5520_FLAG_OFFT_SHIFT)
189#define ADP5520_LED_OFFT_1200ms (3 << ADP5520_FLAG_OFFT_SHIFT)
190
191#define ADP5520_LED_ONT_200ms 0
192#define ADP5520_LED_ONT_600ms 1
193#define ADP5520_LED_ONT_800ms 2
194#define ADP5520_LED_ONT_1200ms 3
195
196struct adp5520_leds_platform_data {
197 int num_leds;
198 struct led_info *leds;
199 u8 fade_in; /* Backlight Fade-In Timer */
200 u8 fade_out; /* Backlight Fade-Out Timer */
201 u8 led_on_time;
202};
203
204/*
205 * Backlight subdevice platform data
206 */
207
208#define ADP5520_FADE_T_DIS 0 /* Fade Timer Disabled */
209#define ADP5520_FADE_T_300ms 1 /* 0.3 Sec */
210#define ADP5520_FADE_T_600ms 2
211#define ADP5520_FADE_T_900ms 3
212#define ADP5520_FADE_T_1200ms 4
213#define ADP5520_FADE_T_1500ms 5
214#define ADP5520_FADE_T_1800ms 6
215#define ADP5520_FADE_T_2100ms 7
216#define ADP5520_FADE_T_2400ms 8
217#define ADP5520_FADE_T_2700ms 9
218#define ADP5520_FADE_T_3000ms 10
219#define ADP5520_FADE_T_3500ms 11
220#define ADP5520_FADE_T_4000ms 12
221#define ADP5520_FADE_T_4500ms 13
222#define ADP5520_FADE_T_5000ms 14
223#define ADP5520_FADE_T_5500ms 15 /* 5.5 Sec */
224
225#define ADP5520_BL_LAW_LINEAR 0
226#define ADP5520_BL_LAW_SQUARE 1
227#define ADP5520_BL_LAW_CUBIC1 2
228#define ADP5520_BL_LAW_CUBIC2 3
229
230#define ADP5520_BL_AMBL_FILT_80ms 0 /* Light sensor filter time */
231#define ADP5520_BL_AMBL_FILT_160ms 1
232#define ADP5520_BL_AMBL_FILT_320ms 2
233#define ADP5520_BL_AMBL_FILT_640ms 3
234#define ADP5520_BL_AMBL_FILT_1280ms 4
235#define ADP5520_BL_AMBL_FILT_2560ms 5
236#define ADP5520_BL_AMBL_FILT_5120ms 6
237#define ADP5520_BL_AMBL_FILT_10240ms 7 /* 10.24 sec */
238
239 /*
240 * Blacklight current 0..30mA
241 */
242#define ADP5520_BL_CUR_mA(I) ((I * 127) / 30)
243
244 /*
245 * L2 comparator current 0..1000uA
246 */
247#define ADP5520_L2_COMP_CURR_uA(I) ((I * 255) / 1000)
248
249 /*
250 * L3 comparator current 0..127uA
251 */
252#define ADP5520_L3_COMP_CURR_uA(I) ((I * 255) / 127)
253
254struct adp5520_backlight_platform_data {
255 u8 fade_in; /* Backlight Fade-In Timer */
256 u8 fade_out; /* Backlight Fade-Out Timer */
257 u8 fade_led_law; /* fade-on/fade-off transfer characteristic */
258
259 u8 en_ambl_sens; /* 1 = enable ambient light sensor */
260 u8 abml_filt; /* Light sensor filter time */
261 u8 l1_daylight_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
262 u8 l1_daylight_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
263 u8 l2_office_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
264 u8 l2_office_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
265 u8 l3_dark_max; /* use BL_CUR_mA(I) 0 <= I <= 30 mA */
266 u8 l3_dark_dim; /* typ = 0, use BL_CUR_mA(I) 0 <= I <= 30 mA */
267 u8 l2_trip; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
268 u8 l2_hyst; /* use L2_COMP_CURR_uA(I) 0 <= I <= 1000 uA */
269 u8 l3_trip; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
270 u8 l3_hyst; /* use L3_COMP_CURR_uA(I) 0 <= I <= 127 uA */
271};
272
273/*
274 * MFD chip platform data
275 */
276
277struct adp5520_platform_data {
278 struct adp5520_keys_platform_data *keys;
279 struct adp5520_gpio_platform_data *gpio;
280 struct adp5520_leds_platform_data *leds;
281 struct adp5520_backlight_platform_data *backlight;
282};
283
284/*
285 * MFD chip functions
286 */
287
288extern int adp5520_read(struct device *dev, int reg, uint8_t *val);
289extern int adp5520_write(struct device *dev, int reg, u8 val);
290extern int adp5520_clr_bits(struct device *dev, int reg, uint8_t bit_mask);
291extern int adp5520_set_bits(struct device *dev, int reg, uint8_t bit_mask);
292
293extern int adp5520_register_notifier(struct device *dev,
294 struct notifier_block *nb, unsigned int events);
295
296extern int adp5520_unregister_notifier(struct device *dev,
297 struct notifier_block *nb, unsigned int events);
298
299#endif /* __LINUX_MFD_ADP5520_H */
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
index 3402042ddc31..40c372165f3e 100644
--- a/include/linux/mfd/ezx-pcap.h
+++ b/include/linux/mfd/ezx-pcap.h
@@ -231,9 +231,6 @@ void pcap_set_ts_bits(struct pcap_chip *, u32);
231#define PCAP_LED_4MA 1 231#define PCAP_LED_4MA 1
232#define PCAP_LED_5MA 2 232#define PCAP_LED_5MA 2
233#define PCAP_LED_9MA 3 233#define PCAP_LED_9MA 3
234#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
235#define PCAP_LED_GPIO_EN 0x01000000
236#define PCAP_LED_GPIO_INVERT 0x02000000
237#define PCAP_LED_T_MASK 0xf 234#define PCAP_LED_T_MASK 0xf
238#define PCAP_LED_C_MASK 0x3 235#define PCAP_LED_C_MASK 0x3
239#define PCAP_BL_MASK 0x1f 236#define PCAP_BL_MASK 0x1f
diff --git a/include/linux/mfd/mc13783-private.h b/include/linux/mfd/mc13783-private.h
index 47e698cb0f16..95cf9360553f 100644
--- a/include/linux/mfd/mc13783-private.h
+++ b/include/linux/mfd/mc13783-private.h
@@ -24,52 +24,23 @@
24 24
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/mfd/mc13783.h> 26#include <linux/mfd/mc13783.h>
27#include <linux/workqueue.h>
28#include <linux/mutex.h> 27#include <linux/mutex.h>
29 28#include <linux/interrupt.h>
30struct mc13783_irq {
31 void (*handler)(int, void *);
32 void *data;
33};
34
35#define MC13783_NUM_IRQ 2
36#define MC13783_IRQ_TS 0
37#define MC13783_IRQ_REGULATOR 1
38
39#define MC13783_ADC_MODE_TS 1
40#define MC13783_ADC_MODE_SINGLE_CHAN 2
41#define MC13783_ADC_MODE_MULT_CHAN 3
42 29
43struct mc13783 { 30struct mc13783 {
44 int revision; 31 struct spi_device *spidev;
45 struct device *dev; 32 struct mutex lock;
46 struct spi_device *spi_device;
47
48 int (*read_dev)(void *data, char reg, int count, u32 *dst);
49 int (*write_dev)(void *data, char reg, int count, const u32 *src);
50
51 struct mutex io_lock;
52 void *io_data;
53 int irq; 33 int irq;
54 unsigned int flags; 34 int flags;
55 35
56 struct mc13783_irq irq_handler[MC13783_NUM_IRQ]; 36 irq_handler_t irqhandler[MC13783_NUM_IRQ];
57 struct work_struct work; 37 void *irqdata[MC13783_NUM_IRQ];
58 struct completion adc_done;
59 unsigned int ts_active;
60 struct mutex adc_conv_lock;
61 38
39 /* XXX these should go as platformdata to the regulator subdevice */
62 struct mc13783_regulator_init_data *regulators; 40 struct mc13783_regulator_init_data *regulators;
63 int num_regulators; 41 int num_regulators;
64}; 42};
65 43
66int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
67int mc13783_reg_write(struct mc13783 *, int, u32);
68int mc13783_set_bits(struct mc13783 *, int, u32, u32);
69int mc13783_free_irq(struct mc13783 *mc13783, int irq);
70int mc13783_register_irq(struct mc13783 *mc13783, int irq,
71 void (*handler) (int, void *), void *data);
72
73#define MC13783_REG_INTERRUPT_STATUS_0 0 44#define MC13783_REG_INTERRUPT_STATUS_0 0
74#define MC13783_REG_INTERRUPT_MASK_0 1 45#define MC13783_REG_INTERRUPT_MASK_0 1
75#define MC13783_REG_INTERRUPT_SENSE_0 2 46#define MC13783_REG_INTERRUPT_SENSE_0 2
@@ -136,55 +107,6 @@ int mc13783_register_irq(struct mc13783 *mc13783, int irq,
136#define MC13783_REG_TEST_3 63 107#define MC13783_REG_TEST_3 63
137#define MC13783_REG_NB 64 108#define MC13783_REG_NB 64
138 109
139
140/*
141 * Interrupt Status
142 */
143#define MC13783_INT_STAT_ADCDONEI (1 << 0)
144#define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
145#define MC13783_INT_STAT_TSI (1 << 2)
146#define MC13783_INT_STAT_WHIGHI (1 << 3)
147#define MC13783_INT_STAT_WLOWI (1 << 4)
148#define MC13783_INT_STAT_CHGDETI (1 << 6)
149#define MC13783_INT_STAT_CHGOVI (1 << 7)
150#define MC13783_INT_STAT_CHGREVI (1 << 8)
151#define MC13783_INT_STAT_CHGSHORTI (1 << 9)
152#define MC13783_INT_STAT_CCCVI (1 << 10)
153#define MC13783_INT_STAT_CHGCURRI (1 << 11)
154#define MC13783_INT_STAT_BPONI (1 << 12)
155#define MC13783_INT_STAT_LOBATLI (1 << 13)
156#define MC13783_INT_STAT_LOBATHI (1 << 14)
157#define MC13783_INT_STAT_UDPI (1 << 15)
158#define MC13783_INT_STAT_USBI (1 << 16)
159#define MC13783_INT_STAT_IDI (1 << 19)
160#define MC13783_INT_STAT_Unused (1 << 20)
161#define MC13783_INT_STAT_SE1I (1 << 21)
162#define MC13783_INT_STAT_CKDETI (1 << 22)
163#define MC13783_INT_STAT_UDMI (1 << 23)
164
165/*
166 * Interrupt Mask
167 */
168#define MC13783_INT_MASK_ADCDONEM (1 << 0)
169#define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
170#define MC13783_INT_MASK_TSM (1 << 2)
171#define MC13783_INT_MASK_WHIGHM (1 << 3)
172#define MC13783_INT_MASK_WLOWM (1 << 4)
173#define MC13783_INT_MASK_CHGDETM (1 << 6)
174#define MC13783_INT_MASK_CHGOVM (1 << 7)
175#define MC13783_INT_MASK_CHGREVM (1 << 8)
176#define MC13783_INT_MASK_CHGSHORTM (1 << 9)
177#define MC13783_INT_MASK_CCCVM (1 << 10)
178#define MC13783_INT_MASK_CHGCURRM (1 << 11)
179#define MC13783_INT_MASK_BPONM (1 << 12)
180#define MC13783_INT_MASK_LOBATLM (1 << 13)
181#define MC13783_INT_MASK_LOBATHM (1 << 14)
182#define MC13783_INT_MASK_UDPM (1 << 15)
183#define MC13783_INT_MASK_USBM (1 << 16)
184#define MC13783_INT_MASK_IDM (1 << 19)
185#define MC13783_INT_MASK_SE1M (1 << 21)
186#define MC13783_INT_MASK_CKDETM (1 << 22)
187
188/* 110/*
189 * Reg Regulator Mode 0 111 * Reg Regulator Mode 0
190 */ 112 */
@@ -284,113 +206,15 @@ int mc13783_register_irq(struct mc13783 *mc13783, int irq,
284#define MC13783_SWCTRL_SW3_STBY (1 << 21) 206#define MC13783_SWCTRL_SW3_STBY (1 << 21)
285#define MC13783_SWCTRL_SW3_MODE (1 << 22) 207#define MC13783_SWCTRL_SW3_MODE (1 << 22)
286 208
287/* 209static inline int mc13783_set_bits(struct mc13783 *mc13783, unsigned int offset,
288 * ADC/Touch 210 u32 mask, u32 val)
289 */ 211{
290#define MC13783_ADC0_LICELLCON (1 << 0) 212 int ret;
291#define MC13783_ADC0_CHRGICON (1 << 1) 213 mc13783_lock(mc13783);
292#define MC13783_ADC0_BATICON (1 << 2) 214 ret = mc13783_reg_rmw(mc13783, offset, mask, val);
293#define MC13783_ADC0_RTHEN (1 << 3) 215 mc13783_unlock(mc13783);
294#define MC13783_ADC0_DTHEN (1 << 4)
295#define MC13783_ADC0_UIDEN (1 << 5)
296#define MC13783_ADC0_ADOUTEN (1 << 6)
297#define MC13783_ADC0_ADOUTPER (1 << 7)
298#define MC13783_ADC0_ADREFEN (1 << 10)
299#define MC13783_ADC0_ADREFMODE (1 << 11)
300#define MC13783_ADC0_TSMOD0 (1 << 12)
301#define MC13783_ADC0_TSMOD1 (1 << 13)
302#define MC13783_ADC0_TSMOD2 (1 << 14)
303#define MC13783_ADC0_CHRGRAWDIV (1 << 15)
304#define MC13783_ADC0_ADINC1 (1 << 16)
305#define MC13783_ADC0_ADINC2 (1 << 17)
306#define MC13783_ADC0_WCOMP (1 << 18)
307#define MC13783_ADC0_ADCBIS0 (1 << 23)
308
309#define MC13783_ADC1_ADEN (1 << 0)
310#define MC13783_ADC1_RAND (1 << 1)
311#define MC13783_ADC1_ADSEL (1 << 3)
312#define MC13783_ADC1_TRIGMASK (1 << 4)
313#define MC13783_ADC1_ADA10 (1 << 5)
314#define MC13783_ADC1_ADA11 (1 << 6)
315#define MC13783_ADC1_ADA12 (1 << 7)
316#define MC13783_ADC1_ADA20 (1 << 8)
317#define MC13783_ADC1_ADA21 (1 << 9)
318#define MC13783_ADC1_ADA22 (1 << 10)
319#define MC13783_ADC1_ATO0 (1 << 11)
320#define MC13783_ADC1_ATO1 (1 << 12)
321#define MC13783_ADC1_ATO2 (1 << 13)
322#define MC13783_ADC1_ATO3 (1 << 14)
323#define MC13783_ADC1_ATO4 (1 << 15)
324#define MC13783_ADC1_ATO5 (1 << 16)
325#define MC13783_ADC1_ATO6 (1 << 17)
326#define MC13783_ADC1_ATO7 (1 << 18)
327#define MC13783_ADC1_ATOX (1 << 19)
328#define MC13783_ADC1_ASC (1 << 20)
329#define MC13783_ADC1_ADTRIGIGN (1 << 21)
330#define MC13783_ADC1_ADONESHOT (1 << 22)
331#define MC13783_ADC1_ADCBIS1 (1 << 23)
332
333#define MC13783_ADC1_CHAN0_SHIFT 5
334#define MC13783_ADC1_CHAN1_SHIFT 8
335
336#define MC13783_ADC2_ADD10 (1 << 2)
337#define MC13783_ADC2_ADD11 (1 << 3)
338#define MC13783_ADC2_ADD12 (1 << 4)
339#define MC13783_ADC2_ADD13 (1 << 5)
340#define MC13783_ADC2_ADD14 (1 << 6)
341#define MC13783_ADC2_ADD15 (1 << 7)
342#define MC13783_ADC2_ADD16 (1 << 8)
343#define MC13783_ADC2_ADD17 (1 << 9)
344#define MC13783_ADC2_ADD18 (1 << 10)
345#define MC13783_ADC2_ADD19 (1 << 11)
346#define MC13783_ADC2_ADD20 (1 << 14)
347#define MC13783_ADC2_ADD21 (1 << 15)
348#define MC13783_ADC2_ADD22 (1 << 16)
349#define MC13783_ADC2_ADD23 (1 << 17)
350#define MC13783_ADC2_ADD24 (1 << 18)
351#define MC13783_ADC2_ADD25 (1 << 19)
352#define MC13783_ADC2_ADD26 (1 << 20)
353#define MC13783_ADC2_ADD27 (1 << 21)
354#define MC13783_ADC2_ADD28 (1 << 22)
355#define MC13783_ADC2_ADD29 (1 << 23)
356 216
357#define MC13783_ADC3_WHIGH0 (1 << 0) 217 return ret;
358#define MC13783_ADC3_WHIGH1 (1 << 1) 218}
359#define MC13783_ADC3_WHIGH2 (1 << 2)
360#define MC13783_ADC3_WHIGH3 (1 << 3)
361#define MC13783_ADC3_WHIGH4 (1 << 4)
362#define MC13783_ADC3_WHIGH5 (1 << 5)
363#define MC13783_ADC3_ICID0 (1 << 6)
364#define MC13783_ADC3_ICID1 (1 << 7)
365#define MC13783_ADC3_ICID2 (1 << 8)
366#define MC13783_ADC3_WLOW0 (1 << 9)
367#define MC13783_ADC3_WLOW1 (1 << 10)
368#define MC13783_ADC3_WLOW2 (1 << 11)
369#define MC13783_ADC3_WLOW3 (1 << 12)
370#define MC13783_ADC3_WLOW4 (1 << 13)
371#define MC13783_ADC3_WLOW5 (1 << 14)
372#define MC13783_ADC3_ADCBIS2 (1 << 23)
373
374#define MC13783_ADC4_ADDBIS10 (1 << 2)
375#define MC13783_ADC4_ADDBIS11 (1 << 3)
376#define MC13783_ADC4_ADDBIS12 (1 << 4)
377#define MC13783_ADC4_ADDBIS13 (1 << 5)
378#define MC13783_ADC4_ADDBIS14 (1 << 6)
379#define MC13783_ADC4_ADDBIS15 (1 << 7)
380#define MC13783_ADC4_ADDBIS16 (1 << 8)
381#define MC13783_ADC4_ADDBIS17 (1 << 9)
382#define MC13783_ADC4_ADDBIS18 (1 << 10)
383#define MC13783_ADC4_ADDBIS19 (1 << 11)
384#define MC13783_ADC4_ADDBIS20 (1 << 14)
385#define MC13783_ADC4_ADDBIS21 (1 << 15)
386#define MC13783_ADC4_ADDBIS22 (1 << 16)
387#define MC13783_ADC4_ADDBIS23 (1 << 17)
388#define MC13783_ADC4_ADDBIS24 (1 << 18)
389#define MC13783_ADC4_ADDBIS25 (1 << 19)
390#define MC13783_ADC4_ADDBIS26 (1 << 20)
391#define MC13783_ADC4_ADDBIS27 (1 << 21)
392#define MC13783_ADC4_ADDBIS28 (1 << 22)
393#define MC13783_ADC4_ADDBIS29 (1 << 23)
394 219
395#endif /* __LINUX_MFD_MC13783_PRIV_H */ 220#endif /* __LINUX_MFD_MC13783_PRIV_H */
396
diff --git a/include/linux/mfd/mc13783.h b/include/linux/mfd/mc13783.h
index b3a2a7243573..35680409b8cf 100644
--- a/include/linux/mfd/mc13783.h
+++ b/include/linux/mfd/mc13783.h
@@ -1,28 +1,50 @@
1/* 1/*
2 * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 2 * Copyright 2009 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
3 * 4 *
4 * Initial development of this code was funded by 5 * This program is free software; you can redistribute it and/or modify it under
5 * Phytec Messtechnik GmbH, http://www.phytec.de 6 * the terms of the GNU General Public License version 2 as published by the
6 * 7 * Free Software Foundation.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 */ 8 */
9#ifndef __LINUX_MFD_MC13783_H
10#define __LINUX_MFD_MC13783_H
21 11
22#ifndef __INCLUDE_LINUX_MFD_MC13783_H 12#include <linux/interrupt.h>
23#define __INCLUDE_LINUX_MFD_MC13783_H
24 13
25struct mc13783; 14struct mc13783;
15
16void mc13783_lock(struct mc13783 *mc13783);
17void mc13783_unlock(struct mc13783 *mc13783);
18
19int mc13783_reg_read(struct mc13783 *mc13783, unsigned int offset, u32 *val);
20int mc13783_reg_write(struct mc13783 *mc13783, unsigned int offset, u32 val);
21int mc13783_reg_rmw(struct mc13783 *mc13783, unsigned int offset,
22 u32 mask, u32 val);
23
24int mc13783_irq_request(struct mc13783 *mc13783, int irq,
25 irq_handler_t handler, const char *name, void *dev);
26int mc13783_irq_request_nounmask(struct mc13783 *mc13783, int irq,
27 irq_handler_t handler, const char *name, void *dev);
28int mc13783_irq_free(struct mc13783 *mc13783, int irq, void *dev);
29int mc13783_ackirq(struct mc13783 *mc13783, int irq);
30
31int mc13783_mask(struct mc13783 *mc13783, int irq);
32int mc13783_unmask(struct mc13783 *mc13783, int irq);
33
34#define MC13783_ADC0 43
35#define MC13783_ADC0_ADREFEN (1 << 10)
36#define MC13783_ADC0_ADREFMODE (1 << 11)
37#define MC13783_ADC0_TSMOD0 (1 << 12)
38#define MC13783_ADC0_TSMOD1 (1 << 13)
39#define MC13783_ADC0_TSMOD2 (1 << 14)
40#define MC13783_ADC0_ADINC1 (1 << 16)
41#define MC13783_ADC0_ADINC2 (1 << 17)
42
43#define MC13783_ADC0_TSMOD_MASK (MC13783_ADC0_TSMOD0 | \
44 MC13783_ADC0_TSMOD1 | \
45 MC13783_ADC0_TSMOD2)
46
47/* to be cleaned up */
26struct regulator_init_data; 48struct regulator_init_data;
27 49
28struct mc13783_regulator_init_data { 50struct mc13783_regulator_init_data {
@@ -30,23 +52,30 @@ struct mc13783_regulator_init_data {
30 struct regulator_init_data *init_data; 52 struct regulator_init_data *init_data;
31}; 53};
32 54
33struct mc13783_platform_data { 55struct mc13783_regulator_platform_data {
34 struct mc13783_regulator_init_data *regulators;
35 int num_regulators; 56 int num_regulators;
36 unsigned int flags; 57 struct mc13783_regulator_init_data *regulators;
37}; 58};
38 59
39/* mc13783_platform_data flags */ 60struct mc13783_platform_data {
61 int num_regulators;
62 struct mc13783_regulator_init_data *regulators;
63
40#define MC13783_USE_TOUCHSCREEN (1 << 0) 64#define MC13783_USE_TOUCHSCREEN (1 << 0)
41#define MC13783_USE_CODEC (1 << 1) 65#define MC13783_USE_CODEC (1 << 1)
42#define MC13783_USE_ADC (1 << 2) 66#define MC13783_USE_ADC (1 << 2)
43#define MC13783_USE_RTC (1 << 3) 67#define MC13783_USE_RTC (1 << 3)
44#define MC13783_USE_REGULATOR (1 << 4) 68#define MC13783_USE_REGULATOR (1 << 4)
69 unsigned int flags;
70};
71
72#define MC13783_ADC_MODE_TS 1
73#define MC13783_ADC_MODE_SINGLE_CHAN 2
74#define MC13783_ADC_MODE_MULT_CHAN 3
45 75
46int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode, 76int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
47 unsigned int channel, unsigned int *sample); 77 unsigned int channel, unsigned int *sample);
48 78
49void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
50 79
51#define MC13783_SW_SW1A 0 80#define MC13783_SW_SW1A 0
52#define MC13783_SW_SW1B 1 81#define MC13783_SW_SW1B 1
@@ -80,5 +109,46 @@ void mc13783_adc_set_ts_status(struct mc13783 *mc13783, unsigned int status);
80#define MC13783_REGU_V3 29 109#define MC13783_REGU_V3 29
81#define MC13783_REGU_V4 30 110#define MC13783_REGU_V4 30
82 111
83#endif /* __INCLUDE_LINUX_MFD_MC13783_H */ 112#define MC13783_IRQ_ADCDONE 0
113#define MC13783_IRQ_ADCBISDONE 1
114#define MC13783_IRQ_TS 2
115#define MC13783_IRQ_WHIGH 3
116#define MC13783_IRQ_WLOW 4
117#define MC13783_IRQ_CHGDET 6
118#define MC13783_IRQ_CHGOV 7
119#define MC13783_IRQ_CHGREV 8
120#define MC13783_IRQ_CHGSHORT 9
121#define MC13783_IRQ_CCCV 10
122#define MC13783_IRQ_CHGCURR 11
123#define MC13783_IRQ_BPON 12
124#define MC13783_IRQ_LOBATL 13
125#define MC13783_IRQ_LOBATH 14
126#define MC13783_IRQ_UDP 15
127#define MC13783_IRQ_USB 16
128#define MC13783_IRQ_ID 19
129#define MC13783_IRQ_SE1 21
130#define MC13783_IRQ_CKDET 22
131#define MC13783_IRQ_UDM 23
132#define MC13783_IRQ_1HZ 24
133#define MC13783_IRQ_TODA 25
134#define MC13783_IRQ_ONOFD1 27
135#define MC13783_IRQ_ONOFD2 28
136#define MC13783_IRQ_ONOFD3 29
137#define MC13783_IRQ_SYSRST 30
138#define MC13783_IRQ_RTCRST 31
139#define MC13783_IRQ_PC 32
140#define MC13783_IRQ_WARM 33
141#define MC13783_IRQ_MEMHLD 34
142#define MC13783_IRQ_PWRRDY 35
143#define MC13783_IRQ_THWARNL 36
144#define MC13783_IRQ_THWARNH 37
145#define MC13783_IRQ_CLK 38
146#define MC13783_IRQ_SEMAF 39
147#define MC13783_IRQ_MC2B 41
148#define MC13783_IRQ_HSDET 42
149#define MC13783_IRQ_HSL 43
150#define MC13783_IRQ_ALSPTH 44
151#define MC13783_IRQ_AHSSHORT 45
152#define MC13783_NUM_IRQ 46
84 153
154#endif /* __LINUX_MFD_MC13783_H */
diff --git a/include/linux/mfd/pcf50633/core.h b/include/linux/mfd/pcf50633/core.h
index 9aba7b779fbc..d9034cc87f18 100644
--- a/include/linux/mfd/pcf50633/core.h
+++ b/include/linux/mfd/pcf50633/core.h
@@ -40,10 +40,6 @@ struct pcf50633_platform_data {
40 u8 resumers[5]; 40 u8 resumers[5];
41}; 41};
42 42
43struct pcf50633_subdev_pdata {
44 struct pcf50633 *pcf;
45};
46
47struct pcf50633_irq { 43struct pcf50633_irq {
48 void (*handler) (int, void *); 44 void (*handler) (int, void *);
49 void *data; 45 void *data;
@@ -217,5 +213,9 @@ enum pcf50633_reg_int5 {
217#define PCF50633_REG_LEDCTL 0x2a 213#define PCF50633_REG_LEDCTL 0x2a
218#define PCF50633_REG_LEDDIM 0x2b 214#define PCF50633_REG_LEDDIM 0x2b
219 215
220#endif 216static inline struct pcf50633 *dev_to_pcf50633(struct device *dev)
217{
218 return dev_get_drvdata(dev);
219}
221 220
221#endif
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 91eb493bf14c..5184b79c700b 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -16,7 +16,6 @@
16#define __MFD_WM831X_CORE_H__ 16#define __MFD_WM831X_CORE_H__
17 17
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/workqueue.h>
20 19
21/* 20/*
22 * Register values. 21 * Register values.
@@ -117,6 +116,7 @@
117#define WM831X_DC3_SLEEP_CONTROL 0x4063 116#define WM831X_DC3_SLEEP_CONTROL 0x4063
118#define WM831X_DC4_CONTROL 0x4064 117#define WM831X_DC4_CONTROL 0x4064
119#define WM831X_DC4_SLEEP_CONTROL 0x4065 118#define WM831X_DC4_SLEEP_CONTROL 0x4065
119#define WM832X_DC4_SLEEP_CONTROL 0x4067
120#define WM831X_EPE1_CONTROL 0x4066 120#define WM831X_EPE1_CONTROL 0x4066
121#define WM831X_EPE2_CONTROL 0x4067 121#define WM831X_EPE2_CONTROL 0x4067
122#define WM831X_LDO1_CONTROL 0x4068 122#define WM831X_LDO1_CONTROL 0x4068
@@ -235,6 +235,8 @@
235 235
236struct regulator_dev; 236struct regulator_dev;
237 237
238#define WM831X_NUM_IRQ_REGS 5
239
238struct wm831x { 240struct wm831x {
239 struct mutex io_lock; 241 struct mutex io_lock;
240 242
@@ -248,10 +250,11 @@ struct wm831x {
248 250
249 int irq; /* Our chip IRQ */ 251 int irq; /* Our chip IRQ */
250 struct mutex irq_lock; 252 struct mutex irq_lock;
251 struct workqueue_struct *irq_wq;
252 struct work_struct irq_work;
253 unsigned int irq_base; 253 unsigned int irq_base;
254 int irq_masks[5]; 254 int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
255 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
256
257 int num_gpio;
255 258
256 struct mutex auxadc_lock; 259 struct mutex auxadc_lock;
257 260
@@ -278,12 +281,30 @@ int wm831x_bulk_read(struct wm831x *wm831x, unsigned short reg,
278int wm831x_irq_init(struct wm831x *wm831x, int irq); 281int wm831x_irq_init(struct wm831x *wm831x, int irq);
279void wm831x_irq_exit(struct wm831x *wm831x); 282void wm831x_irq_exit(struct wm831x *wm831x);
280 283
281int __must_check wm831x_request_irq(struct wm831x *wm831x, 284static inline int __must_check wm831x_request_irq(struct wm831x *wm831x,
282 unsigned int irq, irq_handler_t handler, 285 unsigned int irq,
283 unsigned long flags, const char *name, 286 irq_handler_t handler,
284 void *dev); 287 unsigned long flags,
285void wm831x_free_irq(struct wm831x *wm831x, unsigned int, void *); 288 const char *name,
286void wm831x_disable_irq(struct wm831x *wm831x, int irq); 289 void *dev)
287void wm831x_enable_irq(struct wm831x *wm831x, int irq); 290{
291 return request_threaded_irq(irq, NULL, handler, flags, name, dev);
292}
293
294static inline void wm831x_free_irq(struct wm831x *wm831x,
295 unsigned int irq, void *dev)
296{
297 free_irq(irq, dev);
298}
299
300static inline void wm831x_disable_irq(struct wm831x *wm831x, int irq)
301{
302 disable_irq(irq);
303}
304
305static inline void wm831x_enable_irq(struct wm831x *wm831x, int irq)
306{
307 enable_irq(irq);
308}
288 309
289#endif 310#endif
diff --git a/include/linux/mfd/wm831x/pdata.h b/include/linux/mfd/wm831x/pdata.h
index 90d820260aad..415c228743d5 100644
--- a/include/linux/mfd/wm831x/pdata.h
+++ b/include/linux/mfd/wm831x/pdata.h
@@ -91,6 +91,7 @@ struct wm831x_pdata {
91 /** Called after subdevices are set up */ 91 /** Called after subdevices are set up */
92 int (*post_init)(struct wm831x *wm831x); 92 int (*post_init)(struct wm831x *wm831x);
93 93
94 int irq_base;
94 int gpio_base; 95 int gpio_base;
95 struct wm831x_backlight_pdata *backlight; 96 struct wm831x_backlight_pdata *backlight;
96 struct wm831x_backup_pdata *backup; 97 struct wm831x_backup_pdata *backup;
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
index 1d595de6a055..43868899bf49 100644
--- a/include/linux/mfd/wm8350/core.h
+++ b/include/linux/mfd/wm8350/core.h
@@ -15,7 +15,7 @@
15 15
16#include <linux/kernel.h> 16#include <linux/kernel.h>
17#include <linux/mutex.h> 17#include <linux/mutex.h>
18#include <linux/workqueue.h> 18#include <linux/interrupt.h>
19 19
20#include <linux/mfd/wm8350/audio.h> 20#include <linux/mfd/wm8350/audio.h>
21#include <linux/mfd/wm8350/gpio.h> 21#include <linux/mfd/wm8350/gpio.h>
@@ -601,7 +601,7 @@ extern const u16 wm8352_mode3_defaults[];
601struct wm8350; 601struct wm8350;
602 602
603struct wm8350_irq { 603struct wm8350_irq {
604 void (*handler) (struct wm8350 *, int, void *); 604 irq_handler_t handler;
605 void *data; 605 void *data;
606}; 606};
607 607
@@ -646,10 +646,12 @@ struct wm8350 {
646 * @init: Function called during driver initialisation. Should be 646 * @init: Function called during driver initialisation. Should be
647 * used by the platform to configure GPIO functions and similar. 647 * used by the platform to configure GPIO functions and similar.
648 * @irq_high: Set if WM8350 IRQ is active high. 648 * @irq_high: Set if WM8350 IRQ is active high.
649 * @irq_base: Base IRQ for genirq (not currently used).
649 */ 650 */
650struct wm8350_platform_data { 651struct wm8350_platform_data {
651 int (*init)(struct wm8350 *wm8350); 652 int (*init)(struct wm8350 *wm8350);
652 int irq_high; 653 int irq_high;
654 int irq_base;
653}; 655};
654 656
655 657
@@ -676,11 +678,13 @@ int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
676 * WM8350 internal interrupts 678 * WM8350 internal interrupts
677 */ 679 */
678int wm8350_register_irq(struct wm8350 *wm8350, int irq, 680int wm8350_register_irq(struct wm8350 *wm8350, int irq,
679 void (*handler) (struct wm8350 *, int, void *), 681 irq_handler_t handler, unsigned long flags,
680 void *data); 682 const char *name, void *data);
681int wm8350_free_irq(struct wm8350 *wm8350, int irq); 683int wm8350_free_irq(struct wm8350 *wm8350, int irq);
682int wm8350_mask_irq(struct wm8350 *wm8350, int irq); 684int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
683int wm8350_unmask_irq(struct wm8350 *wm8350, int irq); 685int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
684 686int wm8350_irq_init(struct wm8350 *wm8350, int irq,
687 struct wm8350_platform_data *pdata);
688int wm8350_irq_exit(struct wm8350 *wm8350);
685 689
686#endif 690#endif
diff --git a/include/linux/mfd/wm8350/gpio.h b/include/linux/mfd/wm8350/gpio.h
index ed91e8f5d298..71af3d6ebe9d 100644
--- a/include/linux/mfd/wm8350/gpio.h
+++ b/include/linux/mfd/wm8350/gpio.h
@@ -173,6 +173,24 @@
173#define WM8350_GPIO_DEBOUNCE_ON 1 173#define WM8350_GPIO_DEBOUNCE_ON 1
174 174
175/* 175/*
176 * R30 (0x1E) - GPIO Interrupt Status
177 */
178#define WM8350_GP12_EINT 0x1000
179#define WM8350_GP11_EINT 0x0800
180#define WM8350_GP10_EINT 0x0400
181#define WM8350_GP9_EINT 0x0200
182#define WM8350_GP8_EINT 0x0100
183#define WM8350_GP7_EINT 0x0080
184#define WM8350_GP6_EINT 0x0040
185#define WM8350_GP5_EINT 0x0020
186#define WM8350_GP4_EINT 0x0010
187#define WM8350_GP3_EINT 0x0008
188#define WM8350_GP2_EINT 0x0004
189#define WM8350_GP1_EINT 0x0002
190#define WM8350_GP0_EINT 0x0001
191
192
193/*
176 * R128 (0x80) - GPIO Debounce 194 * R128 (0x80) - GPIO Debounce
177 */ 195 */
178#define WM8350_GP12_DB 0x1000 196#define WM8350_GP12_DB 0x1000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 14:26:38 -0500