[PATCH] ppc32: Added support for new MPC8548 family of PowerQUICC III processors

Added descriptions of the new MPC8548 family processors, e500 core and
peripherals.

Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

3 files changed, 19 insertions, 2 deletions

diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
index 06b86be61ed1..434fc515ba64 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-ppc/irq.h
@@ -223,9 +223,15 @@ static __inline__ int irq_canonicalize(int irq)
 #define MPC85xx_IRQ_RIO_RX      (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_TX    (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_RX    (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_TX    (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_RX    (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_TX    (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_RX    (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_TX    (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_RX    (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
+#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_FEC         (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
 #define MPC85xx_IRQ_DUART       (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 22713e331585..51b61d3305f7 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -74,7 +74,7 @@ extern unsigned char __res[];
 #define MPC85xx_GUTS_OFFSET     (0xe0000)
 #define MPC85xx_GUTS_SIZE       (0x01000)
 #define MPC85xx_IIC1_OFFSET     (0x03000)
-#define MPC85xx_IIC1_SIZE       (0x01000)
+#define MPC85xx_IIC1_SIZE       (0x00100)
 #define MPC85xx_OPENPIC_OFFSET  (0x40000)
 #define MPC85xx_OPENPIC_SIZE    (0x40000)
 #define MPC85xx_PCI1_OFFSET     (0x08000)
@@ -127,6 +127,11 @@ enum ppc_sys_devices {
         MPC85xx_CPM_MCC2,
         MPC85xx_CPM_SMC1,
         MPC85xx_CPM_SMC2,
+        MPC85xx_eTSEC1,
+        MPC85xx_eTSEC2,
+        MPC85xx_eTSEC3,
+        MPC85xx_eTSEC4,
+        MPC85xx_IIC2,
 };
 
 #endif /* CONFIG_85xx */
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index faaff4c64559..70f54af87b9f 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -51,6 +51,7 @@ struct gianfar_platform_data {
 
         /* board specific information */
         u32 board_flags;
+        u32 phy_flags;
         u32 phyid;
         u32 interruptPHY;
         u8 mac_addr[6];
@@ -61,9 +62,14 @@ struct gianfar_platform_data {
 #define FSL_GIANFAR_DEV_HAS_COALESCE            0x00000002
 #define FSL_GIANFAR_DEV_HAS_RMON                0x00000004
 #define FSL_GIANFAR_DEV_HAS_MULTI_INTR          0x00000008
+#define FSL_GIANFAR_DEV_HAS_CSUM                0x00000010
+#define FSL_GIANFAR_DEV_HAS_VLAN                0x00000020
+#define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH       0x00000040
+#define FSL_GIANFAR_DEV_HAS_PADDING             0x00000080
 
 /* Flags in gianfar_platform_data */
-#define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001      /* if not set use a timer */
+#define FSL_GIANFAR_BRD_HAS_PHY_INTR    0x00000001 /* set or use a timer */
+#define FSL_GIANFAR_BRD_IS_REDUCED      0x00000002 /* Set if RGMII, RMII */
 
 struct fsl_i2c_platform_data {
         /* device specific information */