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authorDave Jiang <dave.jiang@intel.com>2011-07-22 17:04:56 -0400
committerDan Williams <dan.j.williams@intel.com>2011-07-22 17:17:31 -0400
commit3baef940f289f08e4aada1fd481ab9ee3f070144 (patch)
tree9cccce957f0697d2d2e449fc380dc697bb6e92b6 /include
parent02f8c6aee8df3cdc935e9bdd4f2d020306035dbe (diff)
ioat: Adding PCI IDs for IOAT devices on SandyBridge platforms
Adding to pci_id.h and the device table for ioat. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/pci_ids.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index f8910e155566..a8571b36ae97 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2699,6 +2699,16 @@
2699#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60 2699#define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60
2700#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00 2700#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN 0x3b00
2701#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f 2701#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX 0x3b1f
2702#define PCI_DEVICE_ID_INTEL_IOAT_SNB0 0x3c20
2703#define PCI_DEVICE_ID_INTEL_IOAT_SNB1 0x3c21
2704#define PCI_DEVICE_ID_INTEL_IOAT_SNB2 0x3c22
2705#define PCI_DEVICE_ID_INTEL_IOAT_SNB3 0x3c23
2706#define PCI_DEVICE_ID_INTEL_IOAT_SNB4 0x3c24
2707#define PCI_DEVICE_ID_INTEL_IOAT_SNB5 0x3c25
2708#define PCI_DEVICE_ID_INTEL_IOAT_SNB6 0x3c26
2709#define PCI_DEVICE_ID_INTEL_IOAT_SNB7 0x3c27
2710#define PCI_DEVICE_ID_INTEL_IOAT_SNB8 0x3c2e
2711#define PCI_DEVICE_ID_INTEL_IOAT_SNB9 0x3c2f
2702#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f 2712#define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
2703#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0 2713#define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
2704#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5 2714#define PCI_DEVICE_ID_INTEL_5100_21 0x65f5