[PATCH] ppc32: Support for 82xx PQII on-chip PCI bridge

This patch adds on-chip PCI bridge support for the PQ2 family.  The
incomplete existent code is updated with interrupt handling stuff and
board-specific bits for 8272ADS and PQ2FADS; the related files were renamed
(from m8260_pci to m82xx_pci) to be of more generic fashion.  This is
tested with 8266ADS and 8272ADS, should work on PQ2FADS as well.

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

3 files changed, 48 insertions, 1 deletions

diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 42fd1068cf2a..c5883dbed63f 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1039,6 +1039,52 @@ typedef struct im_idma {
 #define CMXSCR_TS4CS_CLK7  0x00000006   /* SCC4 Tx Clock Source is CLK7 */
 #define CMXSCR_TS4CS_CLK8  0x00000007   /* SCC4 Tx Clock Source is CLK8 */
 
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration Register                            4-31
+ */
+#define SIUMCR_BBD      0x80000000      /* Bus Busy Disable             */
+#define SIUMCR_ESE      0x40000000      /* External Snoop Enable        */
+#define SIUMCR_PBSE     0x20000000      /* Parity Byte Select Enable    */
+#define SIUMCR_CDIS     0x10000000      /* Core Disable                 */
+#define SIUMCR_DPPC00   0x00000000      /* Data Parity Pins Configuration*/
+#define SIUMCR_DPPC01   0x04000000      /* - " -                        */
+#define SIUMCR_DPPC10   0x08000000      /* - " -                        */
+#define SIUMCR_DPPC11   0x0c000000      /* - " -                        */
+#define SIUMCR_L2CPC00  0x00000000      /* L2 Cache Pins Configuration  */
+#define SIUMCR_L2CPC01  0x01000000      /* - " -                        */
+#define SIUMCR_L2CPC10  0x02000000      /* - " -                        */
+#define SIUMCR_L2CPC11  0x03000000      /* - " -                        */
+#define SIUMCR_LBPC00   0x00000000      /* Local Bus Pins Configuration */
+#define SIUMCR_LBPC01   0x00400000      /* - " -                        */
+#define SIUMCR_LBPC10   0x00800000      /* - " -                        */
+#define SIUMCR_LBPC11   0x00c00000      /* - " -                        */
+#define SIUMCR_APPC00   0x00000000      /* Address Parity Pins Configuration*/
+#define SIUMCR_APPC01   0x00100000      /* - " -                        */
+#define SIUMCR_APPC10   0x00200000      /* - " -                        */
+#define SIUMCR_APPC11   0x00300000      /* - " -                        */
+#define SIUMCR_CS10PC00 0x00000000      /* CS10 Pin Configuration       */
+#define SIUMCR_CS10PC01 0x00040000      /* - " -                        */
+#define SIUMCR_CS10PC10 0x00080000      /* - " -                        */
+#define SIUMCR_CS10PC11 0x000c0000      /* - " -                        */
+#define SIUMCR_BCTLC00  0x00000000      /* Buffer Control Configuration */
+#define SIUMCR_BCTLC01  0x00010000      /* - " -                        */
+#define SIUMCR_BCTLC10  0x00020000      /* - " -                        */
+#define SIUMCR_BCTLC11  0x00030000      /* - " -                        */
+#define SIUMCR_MMR00    0x00000000      /* Mask Masters Requests        */
+#define SIUMCR_MMR01    0x00004000      /* - " -                        */
+#define SIUMCR_MMR10    0x00008000      /* - " -                        */
+#define SIUMCR_MMR11    0x0000c000      /* - " -                        */
+#define SIUMCR_LPBSE    0x00002000      /* LocalBus Parity Byte Select Enable*/
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock Control Register                                  9-8
+*/
+#define SCCR_PCI_MODE   0x00000100      /* PCI Mode     */
+#define SCCR_PCI_MODCK  0x00000080      /* Value of PCI_MODCK pin       */
+#define SCCR_PCIDF_MSK  0x00000078      /* PCI division factor  */
+#define SCCR_PCIDF_SHIFT 3
+
+
 #endif /* __CPM2__ */
 #endif /* __KERNEL__ */
 
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
index 163a6b91d5b2..bf9e05dd54b5 100644
--- a/include/asm-ppc/m8260_pci.h
+++ b/include/asm-ppc/m8260_pci.h
@@ -19,6 +19,7 @@
  * Define the vendor/device ID for the MPC8265.
  */
 #define PCI_DEVICE_ID_MPC8265   ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
+#define PCI_DEVICE_ID_MPC8272   ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
 
 #define M8265_PCIBR0    0x101ac
 #define M8265_PCIBR1    0x101b0
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index d820894e5991..89eb8a2ac693 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -41,7 +41,7 @@
 #endif
 
 #ifdef CONFIG_PCI_8260
-#include <syslib/m8260_pci.h>
+#include <syslib/m82xx_pci.h>
 #endif
 
 /* Make sure the memory translation stuff is there if PCI not used.