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authorIngo Molnar <mingo@elte.hu>2008-07-15 18:29:07 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-15 18:29:07 -0400
commit82638844d9a8581bbf33201cc209a14876eca167 (patch)
tree961d7f9360194421a71aa644a9d0c176a960ce49 /include
parent9982fbface82893e77d211fbabfbd229da6bdde6 (diff)
parent63cf13b77ab785e87c867defa8545e6d4a989774 (diff)
Merge branch 'linus' into cpus4096
Conflicts: arch/x86/xen/smp.c kernel/sched_rt.c net/iucv/iucv.c Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'include')
-rw-r--r--include/Kbuild1
-rw-r--r--include/asm-alpha/smp.h5
-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h7
-rw-r--r--include/asm-arm/arch-at91/at91cap9.h2
-rw-r--r--include/asm-arm/arch-at91/at91cap9_matrix.h5
-rw-r--r--include/asm-arm/arch-at91/at91sam9260.h11
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl.h2
-rw-r--r--include/asm-arm/arch-at91/board.h6
-rw-r--r--include/asm-arm/arch-at91/cpu.h7
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h22
-rw-r--r--include/asm-arm/arch-ebsa285/hardware.h26
-rw-r--r--include/asm-arm/arch-ebsa285/memory.h19
-rw-r--r--include/asm-arm/arch-ebsa285/vmalloc.h4
-rw-r--r--include/asm-arm/arch-imx/hardware.h8
-rw-r--r--include/asm-arm/arch-imx/imx-dma.h2
-rw-r--r--include/asm-arm/arch-imx/imx-uart.h2
-rw-r--r--include/asm-arm/arch-iop13xx/dma.h2
-rw-r--r--include/asm-arm/arch-iop32x/gpio.h6
-rw-r--r--include/asm-arm/arch-iop33x/gpio.h6
-rw-r--r--include/asm-arm/arch-ixp4xx/fsg.h50
-rw-r--r--include/asm-arm/arch-ixp4xx/hardware.h1
-rw-r--r--include/asm-arm/arch-ixp4xx/irqs.h7
-rw-r--r--include/asm-arm/arch-kirkwood/debug-macro.S20
-rw-r--r--include/asm-arm/arch-kirkwood/dma.h1
-rw-r--r--include/asm-arm/arch-kirkwood/entry-macro.S40
-rw-r--r--include/asm-arm/arch-kirkwood/hardware.h21
-rw-r--r--include/asm-arm/arch-kirkwood/io.h26
-rw-r--r--include/asm-arm/arch-kirkwood/irqs.h63
-rw-r--r--include/asm-arm/arch-kirkwood/kirkwood.h100
-rw-r--r--include/asm-arm/arch-kirkwood/memory.h14
-rw-r--r--include/asm-arm/arch-kirkwood/system.h37
-rw-r--r--include/asm-arm/arch-kirkwood/timex.h11
-rw-r--r--include/asm-arm/arch-kirkwood/uncompress.h47
-rw-r--r--include/asm-arm/arch-kirkwood/vmalloc.h5
-rw-r--r--include/asm-arm/arch-loki/debug-macro.S20
-rw-r--r--include/asm-arm/arch-loki/dma.h1
-rw-r--r--include/asm-arm/arch-loki/entry-macro.S30
-rw-r--r--include/asm-arm/arch-loki/hardware.h15
-rw-r--r--include/asm-arm/arch-loki/io.h26
-rw-r--r--include/asm-arm/arch-loki/irqs.h58
-rw-r--r--include/asm-arm/arch-loki/loki.h97
-rw-r--r--include/asm-arm/arch-loki/memory.h14
-rw-r--r--include/asm-arm/arch-loki/system.h37
-rw-r--r--include/asm-arm/arch-loki/timex.h11
-rw-r--r--include/asm-arm/arch-loki/uncompress.h47
-rw-r--r--include/asm-arm/arch-loki/vmalloc.h5
-rw-r--r--include/asm-arm/arch-msm/irqs.h1
-rw-r--r--include/asm-arm/arch-msm/timex.h1
-rw-r--r--include/asm-arm/arch-mv78xx0/debug-macro.S20
-rw-r--r--include/asm-arm/arch-mv78xx0/dma.h1
-rw-r--r--include/asm-arm/arch-mv78xx0/entry-macro.S39
-rw-r--r--include/asm-arm/arch-mv78xx0/hardware.h21
-rw-r--r--include/asm-arm/arch-mv78xx0/io.h26
-rw-r--r--include/asm-arm/arch-mv78xx0/irqs.h91
-rw-r--r--include/asm-arm/arch-mv78xx0/memory.h14
-rw-r--r--include/asm-arm/arch-mv78xx0/mv78xx0.h126
-rw-r--r--include/asm-arm/arch-mv78xx0/system.h37
-rw-r--r--include/asm-arm/arch-mv78xx0/timex.h9
-rw-r--r--include/asm-arm/arch-mv78xx0/uncompress.h47
-rw-r--r--include/asm-arm/arch-mv78xx0/vmalloc.h5
-rw-r--r--include/asm-arm/arch-mxc/board-mx27ads.h354
-rw-r--r--include/asm-arm/arch-mxc/board-mx31ads.h5
-rw-r--r--include/asm-arm/arch-mxc/board-mx31lite.h38
-rw-r--r--include/asm-arm/arch-mxc/board-pcm037.h27
-rw-r--r--include/asm-arm/arch-mxc/board-pcm038.h41
-rw-r--r--include/asm-arm/arch-mxc/clock.h67
-rw-r--r--include/asm-arm/arch-mxc/common.h6
-rw-r--r--include/asm-arm/arch-mxc/debug-macro.S49
-rw-r--r--include/asm-arm/arch-mxc/gpio.h42
-rw-r--r--include/asm-arm/arch-mxc/hardware.h38
-rw-r--r--include/asm-arm/arch-mxc/iim.h77
-rw-r--r--include/asm-arm/arch-mxc/imx-uart.h32
-rw-r--r--include/asm-arm/arch-mxc/iomux-mx1-mx2.h372
-rw-r--r--include/asm-arm/arch-mxc/iomux-mx3.h501
-rw-r--r--include/asm-arm/arch-mxc/irqs.h13
-rw-r--r--include/asm-arm/arch-mxc/mx27.h302
-rw-r--r--include/asm-arm/arch-mxc/mx31.h21
-rw-r--r--include/asm-arm/arch-mxc/mxc.h152
-rw-r--r--include/asm-arm/arch-mxc/mxc_timer.h158
-rw-r--r--include/asm-arm/arch-ns9xxx/hardware.h4
-rw-r--r--include/asm-arm/arch-omap/board-2430sdp.h5
-rw-r--r--include/asm-arm/arch-omap/board-h3.h6
-rw-r--r--include/asm-arm/arch-omap/board-innovator.h3
-rw-r--r--include/asm-arm/arch-omap/board-perseus2.h6
-rw-r--r--include/asm-arm/arch-omap/clock.h17
-rw-r--r--include/asm-arm/arch-omap/common.h15
-rw-r--r--include/asm-arm/arch-omap/control.h4
-rw-r--r--include/asm-arm/arch-omap/cpu.h39
-rw-r--r--include/asm-arm/arch-omap/dma.h378
-rw-r--r--include/asm-arm/arch-omap/dmtimer.h1
-rw-r--r--include/asm-arm/arch-omap/fpga.h49
-rw-r--r--include/asm-arm/arch-omap/hardware.h1
-rw-r--r--include/asm-arm/arch-omap/io.h26
-rw-r--r--include/asm-arm/arch-omap/irqs.h44
-rw-r--r--include/asm-arm/arch-omap/mcbsp.h62
-rw-r--r--include/asm-arm/arch-omap/omap34xx.h72
-rw-r--r--include/asm-arm/arch-omap/sram.h37
-rw-r--r--include/asm-arm/arch-omap/tc.h10
-rw-r--r--include/asm-arm/arch-omap/usb.h23
-rw-r--r--include/asm-arm/arch-orion5x/io.h8
-rw-r--r--include/asm-arm/arch-orion5x/orion5x.h7
-rw-r--r--include/asm-arm/arch-orion5x/uncompress.h29
-rw-r--r--include/asm-arm/arch-pxa/audio.h2
-rw-r--r--include/asm-arm/arch-pxa/hardware.h9
-rw-r--r--include/asm-arm/arch-pxa/irda.h4
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h570
-rw-r--r--include/asm-arm/arch-pxa/pxa25x-udc.h163
-rw-r--r--include/asm-arm/arch-pxa/pxa27x-udc.h257
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-gpio.h2
-rw-r--r--include/asm-arm/arch-pxa/pxa2xx-regs.h162
-rw-r--r--include/asm-arm/arch-pxa/system.h1
-rw-r--r--include/asm-arm/arch-pxa/zylonite.h1
-rw-r--r--include/asm-arm/arch-rpc/io.h5
-rw-r--r--include/asm-arm/arch-s3c2410/gpio.h74
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h2
-rw-r--r--include/asm-arm/assembler.h15
-rw-r--r--include/asm-arm/cacheflush.h13
-rw-r--r--include/asm-arm/dyntick.h6
-rw-r--r--include/asm-arm/ecard.h35
-rw-r--r--include/asm-arm/ftrace.h14
-rw-r--r--include/asm-arm/hardware/iop3xx-gpio.h73
-rw-r--r--include/asm-arm/hw_irq.h11
-rw-r--r--include/asm-arm/kexec.h2
-rw-r--r--include/asm-arm/kprobes.h1
-rw-r--r--include/asm-arm/mach/time.h22
-rw-r--r--include/asm-arm/mmu_context.h5
-rw-r--r--include/asm-arm/plat-orion/cache-feroceon-l2.h11
-rw-r--r--include/asm-arm/plat-orion/orion_nand.h1
-rw-r--r--include/asm-arm/plat-orion/pcie.h1
-rw-r--r--include/asm-arm/plat-s3c/regs-timer.h9
-rw-r--r--include/asm-arm/plat-s3c24xx/devs.h7
-rw-r--r--include/asm-arm/rtc.h43
-rw-r--r--include/asm-arm/smp.h3
-rw-r--r--include/asm-arm/tlbflush.h30
-rw-r--r--include/asm-avr32/arch-at32ap/board.h10
-rw-r--r--include/asm-avr32/arch-at32ap/init.h4
-rw-r--r--include/asm-avr32/arch-at32ap/pm.h3
-rw-r--r--include/asm-avr32/arch-at32ap/sram.h30
-rw-r--r--include/asm-avr32/mmu_context.h1
-rw-r--r--include/asm-avr32/pci.h2
-rw-r--r--include/asm-avr32/pgalloc.h68
-rw-r--r--include/asm-avr32/pgtable.h34
-rw-r--r--include/asm-avr32/setup.h2
-rw-r--r--include/asm-avr32/thread_info.h1
-rw-r--r--include/asm-avr32/tlbflush.h1
-rw-r--r--include/asm-frv/system.h2
-rw-r--r--include/asm-generic/pgtable.h57
-rw-r--r--include/asm-generic/topology.h3
-rw-r--r--include/asm-generic/vmlinux.lds.h27
-rw-r--r--include/asm-ia64/smp.h8
-rw-r--r--include/asm-m32r/smp.h4
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_psc.h8
-rw-r--r--include/asm-mips/smp.h13
-rw-r--r--include/asm-parisc/smp.h3
-rw-r--r--include/asm-powerpc/ftrace.h14
-rw-r--r--include/asm-powerpc/hugetlb.h6
-rw-r--r--include/asm-powerpc/hw_irq.h10
-rw-r--r--include/asm-powerpc/pgtable-ppc64.h10
-rw-r--r--include/asm-powerpc/smp.h8
-rw-r--r--include/asm-s390/Kbuild3
-rw-r--r--include/asm-s390/airq.h4
-rw-r--r--include/asm-s390/ccwdev.h12
-rw-r--r--include/asm-s390/chpid.h5
-rw-r--r--include/asm-s390/chsc.h127
-rw-r--r--include/asm-s390/cio.h114
-rw-r--r--include/asm-s390/elf.h51
-rw-r--r--include/asm-s390/etr.h45
-rw-r--r--include/asm-s390/fcx.h311
-rw-r--r--include/asm-s390/ipl.h17
-rw-r--r--include/asm-s390/isc.h25
-rw-r--r--include/asm-s390/itcw.h30
-rw-r--r--include/asm-s390/pgtable.h6
-rw-r--r--include/asm-s390/processor.h24
-rw-r--r--include/asm-s390/ptrace.h15
-rw-r--r--include/asm-s390/schid.h28
-rw-r--r--include/asm-s390/sclp.h4
-rw-r--r--include/asm-s390/setup.h12
-rw-r--r--include/asm-s390/sparsemem.h4
-rw-r--r--include/asm-s390/timer.h12
-rw-r--r--include/asm-s390/zcrypt.h2
-rw-r--r--include/asm-sh/smp.h14
-rw-r--r--include/asm-sparc/smp.h2
-rw-r--r--include/asm-sparc64/ftrace.h14
-rw-r--r--include/asm-x86/acpi.h5
-rw-r--r--include/asm-x86/alternative.h2
-rw-r--r--include/asm-x86/amd_iommu.h32
-rw-r--r--include/asm-x86/amd_iommu_types.h244
-rw-r--r--include/asm-x86/apic.h14
-rw-r--r--include/asm-x86/asm.h55
-rw-r--r--include/asm-x86/atomic_64.h32
-rw-r--r--include/asm-x86/bios_ebda.h2
-rw-r--r--include/asm-x86/bitops.h68
-rw-r--r--include/asm-x86/bootparam.h2
-rw-r--r--include/asm-x86/cmpxchg_64.h37
-rw-r--r--include/asm-x86/cpufeature.h9
-rw-r--r--include/asm-x86/current.h42
-rw-r--r--include/asm-x86/current_32.h17
-rw-r--r--include/asm-x86/current_64.h27
-rw-r--r--include/asm-x86/desc.h50
-rw-r--r--include/asm-x86/desc_defs.h4
-rw-r--r--include/asm-x86/dmi.h8
-rw-r--r--include/asm-x86/dwarf2.h62
-rw-r--r--include/asm-x86/dwarf2_32.h61
-rw-r--r--include/asm-x86/dwarf2_64.h56
-rw-r--r--include/asm-x86/e820.h107
-rw-r--r--include/asm-x86/e820_32.h50
-rw-r--r--include/asm-x86/e820_64.h56
-rw-r--r--include/asm-x86/efi.h2
-rw-r--r--include/asm-x86/elf.h2
-rw-r--r--include/asm-x86/fixmap.h55
-rw-r--r--include/asm-x86/fixmap_32.h50
-rw-r--r--include/asm-x86/fixmap_64.h59
-rw-r--r--include/asm-x86/ftrace.h14
-rw-r--r--include/asm-x86/gart.h84
-rw-r--r--include/asm-x86/genapic_64.h2
-rw-r--r--include/asm-x86/hardirq.h6
-rw-r--r--include/asm-x86/highmem.h3
-rw-r--r--include/asm-x86/hpet.h2
-rw-r--r--include/asm-x86/hw_irq.h106
-rw-r--r--include/asm-x86/hw_irq_32.h66
-rw-r--r--include/asm-x86/hw_irq_64.h173
-rw-r--r--include/asm-x86/i8259.h2
-rw-r--r--include/asm-x86/io.h83
-rw-r--r--include/asm-x86/io_32.h61
-rw-r--r--include/asm-x86/io_64.h71
-rw-r--r--include/asm-x86/io_apic.h39
-rw-r--r--include/asm-x86/iommu.h31
-rw-r--r--include/asm-x86/ipi.h1
-rw-r--r--include/asm-x86/irq.h51
-rw-r--r--include/asm-x86/irq_32.h51
-rw-r--r--include/asm-x86/irq_64.h51
-rw-r--r--include/asm-x86/irq_vectors.h173
-rw-r--r--include/asm-x86/irqflags.h65
-rw-r--r--include/asm-x86/kvm_para.h15
-rw-r--r--include/asm-x86/mach-bigsmp/mach_apic.h2
-rw-r--r--include/asm-x86/mach-bigsmp/mach_mpspec.h8
-rw-r--r--include/asm-x86/mach-default/entry_arch.h1
-rw-r--r--include/asm-x86/mach-default/irq_vectors.h96
-rw-r--r--include/asm-x86/mach-default/irq_vectors_limits.h16
-rw-r--r--include/asm-x86/mach-default/mach_apic.h4
-rw-r--r--include/asm-x86/mach-default/setup_arch.h4
-rw-r--r--include/asm-x86/mach-default/smpboot_hooks.h10
-rw-r--r--include/asm-x86/mach-es7000/mach_mpspec.h8
-rw-r--r--include/asm-x86/mach-generic/mach_mpparse.h7
-rw-r--r--include/asm-x86/mach-numaq/mach_apic.h39
-rw-r--r--include/asm-x86/mach-numaq/mach_mpparse.h11
-rw-r--r--include/asm-x86/mach-numaq/mach_mpspec.h8
-rw-r--r--include/asm-x86/mach-summit/mach_mpspec.h9
-rw-r--r--include/asm-x86/mach-visws/entry_arch.h22
-rw-r--r--include/asm-x86/mach-visws/irq_vectors.h62
-rw-r--r--include/asm-x86/mach-visws/mach_apic.h104
-rw-r--r--include/asm-x86/mach-visws/mach_apicdef.h13
-rw-r--r--include/asm-x86/mach-visws/setup_arch.h9
-rw-r--r--include/asm-x86/mach-visws/smpboot_hooks.h29
-rw-r--r--include/asm-x86/mach-voyager/entry_arch.h2
-rw-r--r--include/asm-x86/mach-voyager/irq_vectors.h79
-rw-r--r--include/asm-x86/mmconfig.h12
-rw-r--r--include/asm-x86/mmu_context.h32
-rw-r--r--include/asm-x86/mmu_context_32.h28
-rw-r--r--include/asm-x86/mmu_context_64.h18
-rw-r--r--include/asm-x86/mmzone_32.h26
-rw-r--r--include/asm-x86/mpspec.h36
-rw-r--r--include/asm-x86/mpspec_def.h9
-rw-r--r--include/asm-x86/msr-index.h4
-rw-r--r--include/asm-x86/msr.h5
-rw-r--r--include/asm-x86/nmi.h47
-rw-r--r--include/asm-x86/numa_32.h8
-rw-r--r--include/asm-x86/numa_64.h20
-rw-r--r--include/asm-x86/numaq.h8
-rw-r--r--include/asm-x86/page.h12
-rw-r--r--include/asm-x86/page_32.h15
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-rw-r--r--include/asm-x86/paravirt.h197
-rw-r--r--include/asm-x86/pat.h8
-rw-r--r--include/asm-x86/pci.h2
-rw-r--r--include/asm-x86/pci_32.h14
-rw-r--r--include/asm-x86/pda.h5
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-rw-r--r--include/asm-x86/thread_info.h248
-rw-r--r--include/asm-x86/thread_info_32.h205
-rw-r--r--include/asm-x86/thread_info_64.h195
-rw-r--r--include/asm-x86/time.h2
-rw-r--r--include/asm-x86/timer.h4
-rw-r--r--include/asm-x86/topology.h157
-rw-r--r--include/asm-x86/tsc.h2
-rw-r--r--include/asm-x86/uaccess.h448
-rw-r--r--include/asm-x86/uaccess_32.h422
-rw-r--r--include/asm-x86/uaccess_64.h263
-rw-r--r--include/asm-x86/unistd_64.h2
-rw-r--r--include/asm-x86/uv/uv_bau.h337
-rw-r--r--include/asm-x86/uv/uv_hub.h190
-rw-r--r--include/asm-x86/uv/uv_mmrs.h954
-rw-r--r--include/asm-x86/visws/cobalt.h (renamed from include/asm-x86/mach-visws/cobalt.h)0
-rw-r--r--include/asm-x86/visws/lithium.h (renamed from include/asm-x86/mach-visws/lithium.h)0
-rw-r--r--include/asm-x86/visws/piix4.h (renamed from include/asm-x86/mach-visws/piix4.h)0
-rw-r--r--include/asm-x86/visws/sgivw.h5
-rw-r--r--include/asm-x86/vm86.h11
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-rw-r--r--include/asm-x86/xor_64.h5
-rw-r--r--include/crypto/hash.h154
-rw-r--r--include/crypto/internal/hash.h78
-rw-r--r--include/drm/Kbuild10
-rw-r--r--include/drm/drm.h694
-rw-r--r--include/drm/drmP.h1154
-rw-r--r--include/drm/drm_core.h34
-rw-r--r--include/drm/drm_hashtab.h67
-rw-r--r--include/drm/drm_memory.h61
-rw-r--r--include/drm/drm_memory_debug.h309
-rw-r--r--include/drm/drm_os_linux.h108
-rw-r--r--include/drm/drm_pciids.h415
-rw-r--r--include/drm/drm_sarea.h84
-rw-r--r--include/drm/drm_sman.h176
-rw-r--r--include/drm/i810_drm.h281
-rw-r--r--include/drm/i830_drm.h342
-rw-r--r--include/drm/i915_drm.h270
-rw-r--r--include/drm/mga_drm.h417
-rw-r--r--include/drm/r128_drm.h326
-rw-r--r--include/drm/radeon_drm.h749
-rw-r--r--include/drm/savage_drm.h210
-rw-r--r--include/drm/sis_drm.h67
-rw-r--r--include/drm/via_drm.h275
-rw-r--r--include/linux/acpi.h6
-rw-r--r--include/linux/bio.h130
-rw-r--r--include/linux/blkdev.h164
-rw-r--r--include/linux/blktrace_api.h1
-rw-r--r--include/linux/bootmem.h2
-rw-r--r--include/linux/console.h2
-rw-r--r--include/linux/crypto.h48
-rw-r--r--include/linux/dcache.h1
-rw-r--r--include/linux/delay.h1
-rw-r--r--include/linux/efi.h4
-rw-r--r--include/linux/firmware-map.h74
-rw-r--r--include/linux/firmware.h23
-rw-r--r--include/linux/fs.h5
-rw-r--r--include/linux/ftrace.h144
-rw-r--r--include/linux/genhd.h12
-rw-r--r--include/linux/i2c-algo-pcf.h8
-rw-r--r--include/linux/i2c-id.h3
-rw-r--r--include/linux/i2c.h46
-rw-r--r--include/linux/i2c/at24.h28
-rw-r--r--include/linux/ide.h70
-rw-r--r--include/linux/ihex.h74
-rw-r--r--include/linux/interrupt.h8
-rw-r--r--include/linux/iocontext.h18
-rw-r--r--include/linux/irq.h9
-rw-r--r--include/linux/irqflags.h13
-rw-r--r--include/linux/jbd2.h73
-rw-r--r--include/linux/kernel.h8
-rw-r--r--include/linux/kernel_stat.h2
-rw-r--r--include/linux/kprobes.h4
-rw-r--r--include/linux/libata.h55
-rw-r--r--include/linux/linkage.h6
-rw-r--r--include/linux/list.h367
-rw-r--r--include/linux/lm_interface.h6
-rw-r--r--include/linux/lockdep.h11
-rw-r--r--include/linux/marker.h40
-rw-r--r--include/linux/mlx4/device.h3
-rw-r--r--include/linux/mm.h7
-rw-r--r--include/linux/mmiotrace.h85
-rw-r--r--include/linux/mod_devicetable.h9
-rw-r--r--include/linux/mpage.h10
-rw-r--r--include/linux/page-flags.h1
-rw-r--r--include/linux/pageblock-flags.h8
-rw-r--r--include/linux/percpu_counter.h12
-rw-r--r--include/linux/preempt.h34
-rw-r--r--include/linux/ptrace.h8
-rw-r--r--include/linux/pwm.h31
-rw-r--r--include/linux/pwm_backlight.h17
-rw-r--r--include/linux/rcuclassic.h3
-rw-r--r--include/linux/rculist.h369
-rw-r--r--include/linux/rcupdate.h26
-rw-r--r--include/linux/rcupreempt.h42
-rw-r--r--include/linux/resume-trace.h2
-rw-r--r--include/linux/sched.h77
-rw-r--r--include/linux/security.h49
-rw-r--r--include/linux/smp.h46
-rw-r--r--include/linux/smp_lock.h13
-rw-r--r--include/linux/topology.h13
-rw-r--r--include/linux/writeback.h3
-rw-r--r--include/linux/xfrm.h1
-rw-r--r--include/pcmcia/bulkmem.h41
-rw-r--r--include/pcmcia/cistpl.h2
-rw-r--r--include/pcmcia/cs.h3
-rw-r--r--include/pcmcia/cs_types.h6
-rw-r--r--include/pcmcia/ds.h19
-rw-r--r--include/pcmcia/ss.h12
-rw-r--r--include/pcmcia/version.h3
-rw-r--r--include/rdma/ib_addr.h43
-rw-r--r--include/rdma/ib_cache.h2
-rw-r--r--include/rdma/ib_cm.h2
-rw-r--r--include/rdma/ib_fmr_pool.h4
-rw-r--r--include/rdma/ib_mad.h17
-rw-r--r--include/rdma/ib_pack.h2
-rw-r--r--include/rdma/ib_sa.h2
-rw-r--r--include/rdma/ib_smi.h4
-rw-r--r--include/rdma/ib_user_cm.h2
-rw-r--r--include/rdma/ib_user_mad.h2
-rw-r--r--include/rdma/ib_user_verbs.h7
-rw-r--r--include/rdma/ib_verbs.h149
-rw-r--r--include/rdma/iw_cm.h2
-rw-r--r--include/rdma/rdma_cm.h52
-rw-r--r--include/rdma/rdma_cm_ib.h50
-rw-r--r--include/scsi/scsi_device.h1
-rw-r--r--include/sound/ad1843.h46
-rw-r--r--include/sound/control.h3
-rw-r--r--include/sound/core.h8
-rw-r--r--include/sound/cs4231-regs.h8
-rw-r--r--include/sound/cs4231.h3
-rw-r--r--include/sound/emu10k1.h1
-rw-r--r--include/sound/seq_kernel.h2
-rw-r--r--include/sound/soc-dapm.h42
-rw-r--r--include/sound/soc.h175
-rw-r--r--include/sound/uda1341.h2
-rw-r--r--include/sound/version.h4
-rw-r--r--include/xen/events.h4
-rw-r--r--include/xen/grant_table.h3
-rw-r--r--include/xen/hvc-console.h9
-rw-r--r--include/xen/interface/elfnote.h20
-rw-r--r--include/xen/interface/features.h3
-rw-r--r--include/xen/interface/io/fbif.h29
-rw-r--r--include/xen/interface/io/kbdif.h2
-rw-r--r--include/xen/interface/memory.h12
-rw-r--r--include/xen/interface/xen.h9
-rw-r--r--include/xen/xen-ops.h6
450 files changed, 18791 insertions, 5575 deletions
diff --git a/include/Kbuild b/include/Kbuild
index b52288774345..bdca155028ec 100644
--- a/include/Kbuild
+++ b/include/Kbuild
@@ -4,5 +4,6 @@ header-y += sound/
4header-y += mtd/ 4header-y += mtd/
5header-y += rdma/ 5header-y += rdma/
6header-y += video/ 6header-y += video/
7header-y += drm/
7 8
8header-y += asm-$(ARCH)/ 9header-y += asm-$(ARCH)/
diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h
index 286e1d844f63..544c69af8168 100644
--- a/include/asm-alpha/smp.h
+++ b/include/asm-alpha/smp.h
@@ -47,12 +47,13 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS];
47extern int smp_num_cpus; 47extern int smp_num_cpus;
48#define cpu_possible_map cpu_present_map 48#define cpu_possible_map cpu_present_map
49 49
50int smp_call_function_on_cpu(void (*func) (void *info), void *info,int retry, int wait, cpumask_t cpu); 50extern void arch_send_call_function_single_ipi(int cpu);
51extern void arch_send_call_function_ipi(cpumask_t mask);
51 52
52#else /* CONFIG_SMP */ 53#else /* CONFIG_SMP */
53 54
54#define hard_smp_processor_id() 0 55#define hard_smp_processor_id() 0
55#define smp_call_function_on_cpu(func,info,retry,wait,cpu) ({ 0; }) 56#define smp_call_function_on_cpu(func,info,wait,cpu) ({ 0; })
56 57
57#endif /* CONFIG_SMP */ 58#endif /* CONFIG_SMP */
58 59
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index c2b13c280155..2001e81f2267 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -39,10 +39,14 @@
39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
40 40
41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */ 41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
42#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
43#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
44#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
45#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
42 46
43#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */ 47#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
44#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 48#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
45#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ 49#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
46#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 50#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
47 51
48#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */ 52#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
@@ -97,6 +101,7 @@
97#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 101#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
98#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 102#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
99#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 103#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
104#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
100#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 105#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
101#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 106#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
102#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 107#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
index bac83adb5050..6f14d9053ac7 100644
--- a/include/asm-arm/arch-at91/at91cap9.h
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -118,7 +118,7 @@
118#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */ 118#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
119 119
120#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */ 120#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
121#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */ 121#define AT91CAP9_UDPHS_FIFO 0x00600000 /* USB High Speed Device Port */
122#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */ 122#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
123 123
124#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6 124#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
index a641686b6c3d..ddbd4873c842 100644
--- a/include/asm-arm/arch-at91/at91cap9_matrix.h
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -106,6 +106,11 @@
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */ 106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */ 107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108 108
109#define AT91_MATRIX_UDPHS (AT91_MATRIX + 0x118) /* USBHS Special Function Register [AT91CAP9 only] */
110#define AT91_MATRIX_SELECT_UDPHS (0 << 31) /* select High Speed UDP */
111#define AT91_MATRIX_SELECT_UDP (1 << 31) /* select standard UDP */
112#define AT91_MATRIX_UDPHS_BYPASS_LOCK (1 << 30) /* bypass lock bit */
113
109#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */ 114#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
110#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */ 115#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
111#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1) 116#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index c8934fe34dc5..889872a3f2a9 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -6,6 +6,8 @@
6 * Common definitions. 6 * Common definitions.
7 * Based on AT91SAM9260 datasheet revision A (Preliminary). 7 * Based on AT91SAM9260 datasheet revision A (Preliminary).
8 * 8 *
9 * Includes also definitions for AT91SAM9XE and AT91SAM9G families
10 *
9 * This program is free software; you can redistribute it and/or modify 11 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by 12 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or 13 * the Free Software Foundation; either version 2 of the License, or
@@ -123,5 +125,14 @@
123#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */ 125#define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
124#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 126#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
125 127
128#define AT91SAM9G20_ROM_BASE 0x00100000 /* Internal ROM base address */
129#define AT91SAM9G20_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
130
131#define AT91SAM9G20_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
132#define AT91SAM9G20_SRAM0_SIZE SZ_16K /* Internal SRAM 0 size (16Kb) */
133#define AT91SAM9G20_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
134#define AT91SAM9G20_SRAM1_SIZE SZ_16K /* Internal SRAM 1 size (16Kb) */
135
136#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
126 137
127#endif 138#endif
diff --git a/include/asm-arm/arch-at91/at91sam9rl.h b/include/asm-arm/arch-at91/at91sam9rl.h
index 16d2832f6c0a..622e56f81d42 100644
--- a/include/asm-arm/arch-at91/at91sam9rl.h
+++ b/include/asm-arm/arch-at91/at91sam9rl.h
@@ -110,6 +110,6 @@
110#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */ 110#define AT91SAM9RL_ROM_SIZE (2 * SZ_16K) /* Internal ROM size (32Kb) */
111 111
112#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */ 112#define AT91SAM9RL_LCDC_BASE 0x00500000 /* LCD Controller */
113#define AT91SAM9RL_UDPHS_BASE 0x00600000 /* USB Device HS controller */ 113#define AT91SAM9RL_UDPHS_FIFO 0x00600000 /* USB Device HS controller */
114 114
115#endif 115#endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index dc189f01c5b3..94de788da76e 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -36,6 +36,7 @@
36#include <linux/i2c.h> 36#include <linux/i2c.h>
37#include <linux/leds.h> 37#include <linux/leds.h>
38#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
39#include <linux/usb/atmel_usba_udc.h>
39 40
40 /* USB Device */ 41 /* USB Device */
41struct at91_udc_data { 42struct at91_udc_data {
@@ -45,6 +46,9 @@ struct at91_udc_data {
45}; 46};
46extern void __init at91_add_device_udc(struct at91_udc_data *data); 47extern void __init at91_add_device_udc(struct at91_udc_data *data);
47 48
49 /* USB High Speed Device */
50extern void __init at91_add_device_usba(struct usba_platform_data *data);
51
48 /* Compact Flash */ 52 /* Compact Flash */
49struct at91_cf_data { 53struct at91_cf_data {
50 u8 irq_pin; /* I/O IRQ */ 54 u8 irq_pin; /* I/O IRQ */
@@ -73,7 +77,7 @@ struct at91_eth_data {
73}; 77};
74extern void __init at91_add_device_eth(struct at91_eth_data *data); 78extern void __init at91_add_device_eth(struct at91_eth_data *data);
75 79
76#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9) 80#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91SAM9G20) || defined(CONFIG_ARCH_AT91CAP9)
77#define eth_platform_data at91_eth_data 81#define eth_platform_data at91_eth_data
78#endif 82#endif
79 83
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 7145166826a2..52df794205cb 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,6 +21,7 @@
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0 23#define ARCH_ID_AT91SAM9263 0x019607a0
24#define ARCH_ID_AT91SAM9G20 0x019905a0
24#define ARCH_ID_AT91SAM9RL64 0x019b03a0 25#define ARCH_ID_AT91SAM9RL64 0x019b03a0
25#define ARCH_ID_AT91CAP9 0x039A03A0 26#define ARCH_ID_AT91CAP9 0x039A03A0
26 27
@@ -63,6 +64,12 @@ static inline unsigned long at91_arch_identify(void)
63#define cpu_is_at91sam9260() (0) 64#define cpu_is_at91sam9260() (0)
64#endif 65#endif
65 66
67#ifdef CONFIG_ARCH_AT91SAM9G20
68#define cpu_is_at91sam9g20() (at91_cpu_identify() == ARCH_ID_AT91SAM9G20)
69#else
70#define cpu_is_at91sam9g20() (0)
71#endif
72
66#ifdef CONFIG_ARCH_AT91SAM9261 73#ifdef CONFIG_ARCH_AT91SAM9261
67#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261) 74#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
68#else 75#else
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 2c826d8247a3..016a3a3f6633 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -18,7 +18,7 @@
18 18
19#if defined(CONFIG_ARCH_AT91RM9200) 19#if defined(CONFIG_ARCH_AT91RM9200)
20#include <asm/arch/at91rm9200.h> 20#include <asm/arch/at91rm9200.h>
21#elif defined(CONFIG_ARCH_AT91SAM9260) 21#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
22#include <asm/arch/at91sam9260.h> 22#include <asm/arch/at91sam9260.h>
23#elif defined(CONFIG_ARCH_AT91SAM9261) 23#elif defined(CONFIG_ARCH_AT91SAM9261)
24#include <asm/arch/at91sam9261.h> 24#include <asm/arch/at91sam9261.h>
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index f1933b0fa43f..298d8313cdac 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -27,14 +27,29 @@
27 27
28#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK) 28#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
29 29
30#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261) 30#elif defined(CONFIG_ARCH_AT91SAM9260)
31
32#if defined(CONFIG_MACH_USB_A9260) || defined(CONFIG_MACH_QIL_A9260)
33#define AT91SAM9_MASTER_CLOCK 90000000
34#else
35#define AT91SAM9_MASTER_CLOCK 99300000
36#endif
37
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39
40#elif defined(CONFIG_ARCH_AT91SAM9261)
31 41
32#define AT91SAM9_MASTER_CLOCK 99300000 42#define AT91SAM9_MASTER_CLOCK 99300000
33#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
34 44
35#elif defined(CONFIG_ARCH_AT91SAM9263) 45#elif defined(CONFIG_ARCH_AT91SAM9263)
36 46
47#if defined(CONFIG_MACH_USB_A9263)
48#define AT91SAM9_MASTER_CLOCK 90000000
49#else
37#define AT91SAM9_MASTER_CLOCK 99959500 50#define AT91SAM9_MASTER_CLOCK 99959500
51#endif
52
38#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 53#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
39 54
40#elif defined(CONFIG_ARCH_AT91SAM9RL) 55#elif defined(CONFIG_ARCH_AT91SAM9RL)
@@ -42,6 +57,11 @@
42#define AT91SAM9_MASTER_CLOCK 100000000 57#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 58#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44 59
60#elif defined(CONFIG_ARCH_AT91SAM9G20)
61
62#define AT91SAM9_MASTER_CLOCK 132096000
63#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
64
45#elif defined(CONFIG_ARCH_AT91CAP9) 65#elif defined(CONFIG_ARCH_AT91CAP9)
46 66
47#define AT91CAP9_MASTER_CLOCK 100000000 67#define AT91CAP9_MASTER_CLOCK 100000000
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
index daad8ee2d194..74610c2c63d4 100644
--- a/include/asm-arm/arch-ebsa285/hardware.h
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -14,7 +14,6 @@
14 14
15#include <asm/arch/memory.h> 15#include <asm/arch/memory.h>
16 16
17#ifdef CONFIG_ARCH_FOOTBRIDGE
18/* Virtual Physical Size 17/* Virtual Physical Size
19 * 0xff800000 0x40000000 1MB X-Bus 18 * 0xff800000 0x40000000 1MB X-Bus
20 * 0xff000000 0x7c000000 1MB PCI I/O space 19 * 0xff000000 0x7c000000 1MB PCI I/O space
@@ -50,31 +49,6 @@
50#define PCIMEM_SIZE 0x01000000 49#define PCIMEM_SIZE 0x01000000
51#define PCIMEM_BASE 0xf0000000 50#define PCIMEM_BASE 0xf0000000
52 51
53#elif defined(CONFIG_ARCH_CO285)
54/*
55 * This is the COEBSA285 cut-down mapping
56 */
57#define PCIMEM_SIZE 0x80000000
58#define PCIMEM_BASE 0x80000000
59
60#define WFLUSH_SIZE 0x01000000
61#define WFLUSH_BASE 0x7d000000
62
63#define ARMCSR_SIZE 0x00100000
64#define ARMCSR_BASE 0x7cf00000
65
66#define XBUS_SIZE 0x00020000
67#define XBUS_BASE 0x7cee0000
68
69#define PCIO_SIZE 0x00010000
70#define PCIO_BASE 0x7ced0000
71
72#else
73
74#error "Undefined footbridge architecture"
75
76#endif
77
78#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000)) 52#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000))
79#define XBUS_LED_AMBER (1 << 0) 53#define XBUS_LED_AMBER (1 << 0)
80#define XBUS_LED_GREEN (1 << 1) 54#define XBUS_LED_GREEN (1 << 1)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
index cbd7ae64bcc9..9019a3bf5ab9 100644
--- a/include/asm-arm/arch-ebsa285/memory.h
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -42,8 +42,6 @@ extern unsigned long __bus_to_virt(unsigned long);
42 42
43#endif 43#endif
44 44
45#if defined(CONFIG_ARCH_FOOTBRIDGE)
46
47/* Task size and page offset at 3GB */ 45/* Task size and page offset at 3GB */
48#define TASK_SIZE UL(0xbf000000) 46#define TASK_SIZE UL(0xbf000000)
49#define PAGE_OFFSET UL(0xc0000000) 47#define PAGE_OFFSET UL(0xc0000000)
@@ -53,23 +51,6 @@ extern unsigned long __bus_to_virt(unsigned long);
53 */ 51 */
54#define FLUSH_BASE 0xf9000000 52#define FLUSH_BASE 0xf9000000
55 53
56#elif defined(CONFIG_ARCH_CO285)
57
58/* Task size and page offset at 1.5GB */
59#define TASK_SIZE UL(0x5f000000)
60#define PAGE_OFFSET UL(0x60000000)
61
62/*
63 * Cache flushing area.
64 */
65#define FLUSH_BASE 0x7e000000
66
67#else
68
69#error "Undefined footbridge architecture"
70
71#endif
72
73/* 54/*
74 * Physical DRAM offset. 55 * Physical DRAM offset.
75 */ 56 */
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
index 02598200997d..e487d7e8c8a6 100644
--- a/include/asm-arm/arch-ebsa285/vmalloc.h
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -7,8 +7,4 @@
7 */ 7 */
8 8
9 9
10#ifdef CONFIG_ARCH_FOOTBRIDGE
11#define VMALLOC_END (PAGE_OFFSET + 0x30000000) 10#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
12#else
13#define VMALLOC_END (PAGE_OFFSET + 0x20000000)
14#endif
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
index adffb6acf42a..6542ca5e8c33 100644
--- a/include/asm-arm/arch-imx/hardware.h
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -73,14 +73,6 @@
73 */ 73 */
74extern void imx_gpio_mode( int gpio_mode ); 74extern void imx_gpio_mode( int gpio_mode );
75 75
76/* get frequencies in Hz */
77extern unsigned int imx_get_system_clk(void);
78extern unsigned int imx_get_mcu_clk(void);
79extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
80extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12] */
81extern unsigned int imx_get_perclk3(void); /* SSI */
82extern unsigned int imx_get_hclk(void); /* SDRAM, CSI, Memory Stick,*/
83 /* I2C, DMA */
84#endif 76#endif
85 77
86#define MAXIRQNUM 62 78#define MAXIRQNUM 62
diff --git a/include/asm-arm/arch-imx/imx-dma.h b/include/asm-arm/arch-imx/imx-dma.h
index 5b1066da4e1f..44d89c35539a 100644
--- a/include/asm-arm/arch-imx/imx-dma.h
+++ b/include/asm-arm/arch-imx/imx-dma.h
@@ -88,7 +88,7 @@ int imx_dma_request(imx_dmach_t dma_ch, const char *name);
88 88
89void imx_dma_free(imx_dmach_t dma_ch); 89void imx_dma_free(imx_dmach_t dma_ch);
90 90
91int imx_dma_request_by_prio(imx_dmach_t *pdma_ch, const char *name, imx_dma_prio prio); 91imx_dmach_t imx_dma_request_by_prio(const char *name, imx_dma_prio prio);
92 92
93 93
94#endif /* _ASM_ARCH_IMX_DMA_H */ 94#endif /* _ASM_ARCH_IMX_DMA_H */
diff --git a/include/asm-arm/arch-imx/imx-uart.h b/include/asm-arm/arch-imx/imx-uart.h
index 3a685e1780ea..d54eb1d48026 100644
--- a/include/asm-arm/arch-imx/imx-uart.h
+++ b/include/asm-arm/arch-imx/imx-uart.h
@@ -4,6 +4,8 @@
4#define IMXUART_HAVE_RTSCTS (1<<0) 4#define IMXUART_HAVE_RTSCTS (1<<0)
5 5
6struct imxuart_platform_data { 6struct imxuart_platform_data {
7 int (*init)(struct platform_device *pdev);
8 void (*exit)(struct platform_device *pdev);
7 unsigned int flags; 9 unsigned int flags;
8}; 10};
9 11
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
index 2e15da53ff79..d79846fbb394 100644
--- a/include/asm-arm/arch-iop13xx/dma.h
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -1,3 +1,3 @@
1#ifndef _IOP13XX_DMA_H 1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H_ 2#define _IOP13XX_DMA_H
3#endif 3#endif
diff --git a/include/asm-arm/arch-iop32x/gpio.h b/include/asm-arm/arch-iop32x/gpio.h
new file mode 100644
index 000000000000..708f4ec9db1d
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/gpio.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_IOP32X_GPIO_H
2#define __ASM_ARCH_IOP32X_GPIO_H
3
4#include <asm/hardware/iop3xx-gpio.h>
5
6#endif
diff --git a/include/asm-arm/arch-iop33x/gpio.h b/include/asm-arm/arch-iop33x/gpio.h
new file mode 100644
index 000000000000..ddd55bba9bb9
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/gpio.h
@@ -0,0 +1,6 @@
1#ifndef __ASM_ARCH_IOP33X_GPIO_H
2#define __ASM_ARCH_IOP33X_GPIO_H
3
4#include <asm/hardware/iop3xx-gpio.h>
5
6#endif
diff --git a/include/asm-arm/arch-ixp4xx/fsg.h b/include/asm-arm/arch-ixp4xx/fsg.h
new file mode 100644
index 000000000000..c0100cc7981c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/fsg.h
@@ -0,0 +1,50 @@
1/*
2 * include/asm-arm/arch-ixp4xx/fsg.h
3 *
4 * Freecom FSG-3 platform specific definitions
5 *
6 * Author: Rod Whitby <rod@whitby.id.au>
7 * Author: Tomasz Chmielewski <mangoo@wpkg.org>
8 * Maintainers: http://www.nslu2-linux.org
9 *
10 * Based on coyote.h by
11 * Copyright 2004 (c) MontaVista, Software, Inc.
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#define FSG_SDA_PIN 12
23#define FSG_SCL_PIN 13
24
25/*
26 * FSG PCI IRQs
27 */
28#define FSG_PCI_MAX_DEV 3
29#define FSG_PCI_IRQ_LINES 3
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define FSG_PCI_INTA_PIN 6
34#define FSG_PCI_INTB_PIN 7
35#define FSG_PCI_INTC_PIN 5
36
37/* Buttons */
38
39#define FSG_SB_GPIO 4 /* sync button */
40#define FSG_RB_GPIO 9 /* reset button */
41#define FSG_UB_GPIO 10 /* usb button */
42
43/* LEDs */
44
45#define FSG_LED_WLAN_BIT 0
46#define FSG_LED_WAN_BIT 1
47#define FSG_LED_SATA_BIT 2
48#define FSG_LED_USB_BIT 4
49#define FSG_LED_RING_BIT 5
50#define FSG_LED_SYNC_BIT 7
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 73e8dc36f6a4..fa723a627854 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -45,5 +45,6 @@
45#include "nslu2.h" 45#include "nslu2.h"
46#include "nas100d.h" 46#include "nas100d.h"
47#include "dsmg600.h" 47#include "dsmg600.h"
48#include "fsg.h"
48 49
49#endif /* _ASM_ARCH_HARDWARE_H */ 50#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index 11801605047b..674af4a84147 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -128,4 +128,11 @@
128#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7 128#define IRQ_DSMG600_PCI_INTE IRQ_IXP4XX_GPIO7
129#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6 129#define IRQ_DSMG600_PCI_INTF IRQ_IXP4XX_GPIO6
130 130
131/*
132 * Freecom FSG-3 Board IRQs
133 */
134#define IRQ_FSG_PCI_INTA IRQ_IXP4XX_GPIO6
135#define IRQ_FSG_PCI_INTB IRQ_IXP4XX_GPIO7
136#define IRQ_FSG_PCI_INTC IRQ_IXP4XX_GPIO5
137
131#endif 138#endif
diff --git a/include/asm-arm/arch-kirkwood/debug-macro.S b/include/asm-arm/arch-kirkwood/debug-macro.S
new file mode 100644
index 000000000000..f55fb8ad9ee4
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-kirkwood/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/kirkwood.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =KIRKWOOD_REGS_PHYS_BASE
15 ldrne \rx, =KIRKWOOD_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-kirkwood/dma.h b/include/asm-arm/arch-kirkwood/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-kirkwood/entry-macro.S b/include/asm-arm/arch-kirkwood/entry-macro.S
new file mode 100644
index 000000000000..fc6a43d9355c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/entry-macro.S
@@ -0,0 +1,40 @@
1/*
2 * include/asm-arm/arch-kirkwood/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Kirkwood platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/kirkwood.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29 bne 1001f
30
31 @ if no low interrupts set, check high interrupts
32 ldr \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
33 ldr \tmp, [\base, #IRQ_MASK_HIGH_OFF]
34 mov \irqnr, #63
35 ands \irqstat, \irqstat, \tmp
36
37 @ find first active interrupt source
381001: clzne \irqstat, \irqstat
39 subne \irqnr, \irqnr, \irqstat
40 .endm
diff --git a/include/asm-arm/arch-kirkwood/hardware.h b/include/asm-arm/arch-kirkwood/hardware.h
new file mode 100644
index 000000000000..e695719771a5
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/hardware.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-kirkwood/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "kirkwood.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
19
20
21#endif
diff --git a/include/asm-arm/arch-kirkwood/io.h b/include/asm-arm/arch-kirkwood/io.h
new file mode 100644
index 000000000000..0ef6e95f5d5b
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-kirkwood/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "kirkwood.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - KIRKWOOD_PCIE_IO_PHYS_BASE)
19 + KIRKWOOD_PCIE_IO_VIRT_BASE);
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-kirkwood/irqs.h b/include/asm-arm/arch-kirkwood/irqs.h
new file mode 100644
index 000000000000..2e7b5da6335c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/irqs.h
@@ -0,0 +1,63 @@
1/*
2 * include/asm-arm/arch-kirkwood/irqs.h
3 *
4 * IRQ definitions for Marvell Kirkwood SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "kirkwood.h" /* need GPIO_MAX */
15
16/*
17 * Low Interrupt Controller
18 */
19#define IRQ_KIRKWOOD_HIGH_SUM 0
20#define IRQ_KIRKWOOD_BRIDGE 1
21#define IRQ_KIRKWOOD_HOST2CPU 2
22#define IRQ_KIRKWOOD_CPU2HOST 3
23#define IRQ_KIRKWOOD_XOR_00 5
24#define IRQ_KIRKWOOD_XOR_01 6
25#define IRQ_KIRKWOOD_XOR_10 7
26#define IRQ_KIRKWOOD_XOR_11 8
27#define IRQ_KIRKWOOD_PCIE 9
28#define IRQ_KIRKWOOD_GE00_SUM 11
29#define IRQ_KIRKWOOD_GE01_SUM 15
30#define IRQ_KIRKWOOD_USB 19
31#define IRQ_KIRKWOOD_SATA 21
32#define IRQ_KIRKWOOD_CRYPTO 22
33#define IRQ_KIRKWOOD_SPI 23
34#define IRQ_KIRKWOOD_I2S 24
35#define IRQ_KIRKWOOD_TS_0 26
36#define IRQ_KIRKWOOD_SDIO 28
37#define IRQ_KIRKWOOD_TWSI 29
38#define IRQ_KIRKWOOD_AVB 30
39#define IRQ_KIRKWOOD_TDMI 31
40
41/*
42 * High Interrupt Controller
43 */
44#define IRQ_KIRKWOOD_UART_0 33
45#define IRQ_KIRKWOOD_UART_1 34
46#define IRQ_KIRKWOOD_GPIO_LOW_0_7 35
47#define IRQ_KIRKWOOD_GPIO_LOW_8_15 36
48#define IRQ_KIRKWOOD_GPIO_LOW_16_23 37
49#define IRQ_KIRKWOOD_GPIO_LOW_24_31 38
50#define IRQ_KIRKWOOD_GPIO_HIGH_0_7 39
51#define IRQ_KIRKWOOD_GPIO_HIGH_8_15 40
52#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
53
54/*
55 * KIRKWOOD General Purpose Pins
56 */
57#define IRQ_KIRKWOOD_GPIO_START 64
58#define NR_GPIO_IRQS GPIO_MAX
59
60#define NR_IRQS (IRQ_KIRKWOOD_GPIO_START + NR_GPIO_IRQS)
61
62
63#endif
diff --git a/include/asm-arm/arch-kirkwood/kirkwood.h b/include/asm-arm/arch-kirkwood/kirkwood.h
new file mode 100644
index 000000000000..bb31b315c350
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/kirkwood.h
@@ -0,0 +1,100 @@
1/*
2 * include/asm-arm/arch-kirkwood/kirkwood.h
3 *
4 * Generic definitions for Marvell Kirkwood SoC flavors:
5 * 88F6180, 88F6192 and 88F6281.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_KIRKWOOD_H
13#define __ASM_ARCH_KIRKWOOD_H
14
15/*
16 * Marvell Kirkwood address maps.
17 *
18 * phys
19 * e0000000 PCIe Memory space
20 * f1000000 on-chip peripheral registers
21 * f2000000 PCIe I/O space
22 * f3000000 NAND controller address window
23 *
24 * virt phys size
25 * fee00000 f1000000 1M on-chip peripheral registers
26 * fef00000 f2000000 1M PCIe I/O space
27 */
28
29#define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
30#define KIRKWOOD_NAND_MEM_SIZE SZ_64K /* 1K is sufficient, but 64K
31 * is the minimal window size
32 */
33
34#define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
35#define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
36#define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
37#define KIRKWOOD_PCIE_IO_SIZE SZ_1M
38
39#define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
40#define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
41#define KIRKWOOD_REGS_SIZE SZ_1M
42
43#define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
44#define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
45
46/*
47 * MBUS bridge registers.
48 */
49#define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
50#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
51#define CPU_RESET 0x00000002
52#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
53#define SOFT_RESET_OUT_EN 0x00000004
54#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
55#define SOFT_RESET 0x00000001
56#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
57#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
58#define BRIDGE_INT_TIMER0 0x0002
59#define BRIDGE_INT_TIMER1 0x0004
60#define BRIDGE_INT_TIMER1_CLR (~0x0004)
61#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
62#define IRQ_CAUSE_LOW_OFF 0x0000
63#define IRQ_MASK_LOW_OFF 0x0004
64#define IRQ_CAUSE_HIGH_OFF 0x0010
65#define IRQ_MASK_HIGH_OFF 0x0014
66#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
67#define L2_CONFIG_REG (BRIDGE_VIRT_BASE | 0x0128)
68#define L2_WRITETHROUGH 0x00000010
69
70/*
71 * Register Map
72 */
73#define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
74#define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
75
76#define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
77#define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
78#define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
79#define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
80#define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
81#define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
82#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
83#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
84#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
85#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
86
87#define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
88
89#define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
90
91#define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
92#define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
93
94#define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
95
96
97#define GPIO_MAX 50
98
99
100#endif
diff --git a/include/asm-arm/arch-kirkwood/memory.h b/include/asm-arm/arch-kirkwood/memory.h
new file mode 100644
index 000000000000..e5108f408ce6
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-kirkwood/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-kirkwood/system.h b/include/asm-arm/arch-kirkwood/system.h
new file mode 100644
index 000000000000..8dde7e379855
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-kirkwood/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/kirkwood.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-kirkwood/timex.h b/include/asm-arm/arch-kirkwood/timex.h
new file mode 100644
index 000000000000..82122e134e3c
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/timex.h
@@ -0,0 +1,11 @@
1/*
2 * include/asm-arm/arch-kirkwood/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
10
11#define KIRKWOOD_TCLK 166666667
diff --git a/include/asm-arm/arch-kirkwood/uncompress.h b/include/asm-arm/arch-kirkwood/uncompress.h
new file mode 100644
index 000000000000..a9062b6d7680
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-kirkwood/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/kirkwood.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-kirkwood/vmalloc.h b/include/asm-arm/arch-kirkwood/vmalloc.h
new file mode 100644
index 000000000000..41852c6e77f3
--- /dev/null
+++ b/include/asm-arm/arch-kirkwood/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-kirkwood/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe800000
diff --git a/include/asm-arm/arch-loki/debug-macro.S b/include/asm-arm/arch-loki/debug-macro.S
new file mode 100644
index 000000000000..585502e96513
--- /dev/null
+++ b/include/asm-arm/arch-loki/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-loki/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/loki.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =LOKI_REGS_PHYS_BASE
15 ldrne \rx, =LOKI_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-loki/dma.h b/include/asm-arm/arch-loki/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-loki/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-loki/entry-macro.S b/include/asm-arm/arch-loki/entry-macro.S
new file mode 100644
index 000000000000..693257cdbeb8
--- /dev/null
+++ b/include/asm-arm/arch-loki/entry-macro.S
@@ -0,0 +1,30 @@
1/*
2 * include/asm-arm/arch-loki/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/loki.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
25 ldr \tmp, [\base, #IRQ_MASK_OFF]
26 mov \irqnr, #0
27 ands \irqstat, \irqstat, \tmp
28 clzne \irqnr, \irqstat
29 rsbne \irqnr, \irqnr, #31
30 .endm
diff --git a/include/asm-arm/arch-loki/hardware.h b/include/asm-arm/arch-loki/hardware.h
new file mode 100644
index 000000000000..f65b01c733b6
--- /dev/null
+++ b/include/asm-arm/arch-loki/hardware.h
@@ -0,0 +1,15 @@
1/*
2 * include/asm-arm/arch-loki/hardware.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "loki.h"
13
14
15#endif
diff --git a/include/asm-arm/arch-loki/io.h b/include/asm-arm/arch-loki/io.h
new file mode 100644
index 000000000000..e7418a915e75
--- /dev/null
+++ b/include/asm-arm/arch-loki/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-loki/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "loki.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
19 + LOKI_PCIE0_IO_VIRT_BASE);
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-loki/irqs.h b/include/asm-arm/arch-loki/irqs.h
new file mode 100644
index 000000000000..7e4971438072
--- /dev/null
+++ b/include/asm-arm/arch-loki/irqs.h
@@ -0,0 +1,58 @@
1/*
2 * include/asm-arm/arch-loki/irqs.h
3 *
4 * IRQ definitions for Marvell Loki (88RC8480) SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "loki.h" /* need GPIO_MAX */
15
16/*
17 * Interrupt Controller
18 */
19#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
20#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
21#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
22#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
23#define IRQ_LOKI_COM_A_ERR 6
24#define IRQ_LOKI_COM_A_IN 7
25#define IRQ_LOKI_COM_A_OUT 8
26#define IRQ_LOKI_COM_B_ERR 9
27#define IRQ_LOKI_COM_B_IN 10
28#define IRQ_LOKI_COM_B_OUT 11
29#define IRQ_LOKI_DMA_A 12
30#define IRQ_LOKI_DMA_B 13
31#define IRQ_LOKI_SAS_A 14
32#define IRQ_LOKI_SAS_B 15
33#define IRQ_LOKI_DDR 16
34#define IRQ_LOKI_XOR 17
35#define IRQ_LOKI_BRIDGE 18
36#define IRQ_LOKI_PCIE_A_ERR 20
37#define IRQ_LOKI_PCIE_A_INT 21
38#define IRQ_LOKI_PCIE_B_ERR 22
39#define IRQ_LOKI_PCIE_B_INT 23
40#define IRQ_LOKI_GBE_A_INT 24
41#define IRQ_LOKI_GBE_B_INT 25
42#define IRQ_LOKI_DEV_ERR 26
43#define IRQ_LOKI_UART0 27
44#define IRQ_LOKI_UART1 28
45#define IRQ_LOKI_TWSI 29
46#define IRQ_LOKI_GPIO_23_0 30
47#define IRQ_LOKI_GPIO_25_24 31
48
49/*
50 * Loki General Purpose Pins
51 */
52#define IRQ_LOKI_GPIO_START 32
53#define NR_GPIO_IRQS GPIO_MAX
54
55#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
56
57
58#endif
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
new file mode 100644
index 000000000000..5dd05ee0a4e6
--- /dev/null
+++ b/include/asm-arm/arch-loki/loki.h
@@ -0,0 +1,97 @@
1/*
2 * include/asm-arm/arch-loki/loki.h
3 *
4 * Generic definitions for Marvell Loki (88RC8480) SoC flavors
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_LOKI_H
12#define __ASM_ARCH_LOKI_H
13
14/*
15 * Marvell Loki (88RC8480) address maps.
16 *
17 * phys
18 * d0000000 on-chip peripheral registers
19 * e0000000 PCIe 0 Memory space
20 * e8000000 PCIe 1 Memory space
21 * f0000000 PCIe 0 I/O space
22 * f0100000 PCIe 1 I/O space
23 *
24 * virt phys size
25 * fed00000 d0000000 1M on-chip peripheral registers
26 * fee00000 f0000000 64K PCIe 0 I/O space
27 * fef00000 f0100000 64K PCIe 1 I/O space
28 */
29
30#define LOKI_REGS_PHYS_BASE 0xd0000000
31#define LOKI_REGS_VIRT_BASE 0xfed00000
32#define LOKI_REGS_SIZE SZ_1M
33
34#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
35#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
36#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
37#define LOKI_PCIE0_IO_SIZE SZ_64K
38
39#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
40#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
41#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
42#define LOKI_PCIE1_IO_SIZE SZ_64K
43
44#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
45#define LOKI_PCIE0_MEM_SIZE SZ_128M
46
47#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
48#define LOKI_PCIE1_MEM_SIZE SZ_128M
49
50/*
51 * Register Map
52 */
53#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
54#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
55#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
56#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
57#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
58#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
59
60#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
61#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
62#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
63#define SOFT_RESET_OUT_EN 0x00000004
64#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
65#define SOFT_RESET 0x00000001
66#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
67#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
68#define BRIDGE_INT_TIMER0 0x0002
69#define BRIDGE_INT_TIMER1 0x0004
70#define BRIDGE_INT_TIMER1_CLR 0x0004
71#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
72#define IRQ_CAUSE_OFF 0x0000
73#define IRQ_MASK_OFF 0x0004
74#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
75
76#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
77
78#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
79
80#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
81
82#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
83
84#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
85#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
86
87#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
88#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
89
90#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
91#define DDR_REG(x) (DDR_VIRT_BASE | (x))
92
93
94#define GPIO_MAX 8
95
96
97#endif
diff --git a/include/asm-arm/arch-loki/memory.h b/include/asm-arm/arch-loki/memory.h
new file mode 100644
index 000000000000..835101e49875
--- /dev/null
+++ b/include/asm-arm/arch-loki/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-loki/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-loki/system.h b/include/asm-arm/arch-loki/system.h
new file mode 100644
index 000000000000..a3568ac8ec35
--- /dev/null
+++ b/include/asm-arm/arch-loki/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-loki/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/loki.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-loki/timex.h b/include/asm-arm/arch-loki/timex.h
new file mode 100644
index 000000000000..940014f97cae
--- /dev/null
+++ b/include/asm-arm/arch-loki/timex.h
@@ -0,0 +1,11 @@
1/*
2 * include/asm-arm/arch-loki/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
10
11#define LOKI_TCLK 180000000
diff --git a/include/asm-arm/arch-loki/uncompress.h b/include/asm-arm/arch-loki/uncompress.h
new file mode 100644
index 000000000000..89a0cf88d3a5
--- /dev/null
+++ b/include/asm-arm/arch-loki/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-loki/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/loki.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-loki/vmalloc.h b/include/asm-arm/arch-loki/vmalloc.h
new file mode 100644
index 000000000000..f5be06220491
--- /dev/null
+++ b/include/asm-arm/arch-loki/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-loki/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe800000
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
index 565430cfaa7e..e62a108b1857 100644
--- a/include/asm-arm/arch-msm/irqs.h
+++ b/include/asm-arm/arch-msm/irqs.h
@@ -15,6 +15,7 @@
15 */ 15 */
16 16
17#ifndef __ASM_ARCH_MSM_IRQS_H 17#ifndef __ASM_ARCH_MSM_IRQS_H
18#define __ASM_ARCH_MSM_IRQS_H
18 19
19/* MSM ARM11 Interrupt Numbers */ 20/* MSM ARM11 Interrupt Numbers */
20/* See 80-VE113-1 A, pp219-221 */ 21/* See 80-VE113-1 A, pp219-221 */
diff --git a/include/asm-arm/arch-msm/timex.h b/include/asm-arm/arch-msm/timex.h
index 154b23fb3599..8724487ab4c9 100644
--- a/include/asm-arm/arch-msm/timex.h
+++ b/include/asm-arm/arch-msm/timex.h
@@ -14,6 +14,7 @@
14 */ 14 */
15 15
16#ifndef __ASM_ARCH_MSM_TIMEX_H 16#ifndef __ASM_ARCH_MSM_TIMEX_H
17#define __ASM_ARCH_MSM_TIMEX_H
17 18
18#define CLOCK_TICK_RATE 1000000 19#define CLOCK_TICK_RATE 1000000
19 20
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
new file mode 100644
index 000000000000..d0595bd645e5
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-mv78xx0/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/mv78xx0.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =MV78XX0_REGS_PHYS_BASE
15 ldrne \rx, =MV78XX0_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
new file mode 100644
index 000000000000..e9a606b12669
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * include/asm-arm/arch-mv78xx0/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell MV78xx0 platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/mv78xx0.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29
30 @ if no low interrupts set, check high interrupts
31 ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
32 ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
33 moveq \irqnr, #63
34 andeqs \irqstat, \irqstat, \tmp
35
36 @ find first active interrupt source
37 clzne \irqstat, \irqstat
38 subne \irqnr, \irqnr, \irqstat
39 .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
new file mode 100644
index 000000000000..8e17926086c6
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/hardware.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-mv78xx0/hardware.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "mv78xx0.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
19
20
21#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
new file mode 100644
index 000000000000..415d4c98e3d1
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-mv78xx0/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "mv78xx0.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
19 + MV78XX0_PCIE_IO_VIRT_BASE(0));
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
new file mode 100644
index 000000000000..75930450cd65
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/irqs.h
@@ -0,0 +1,91 @@
1/*
2 * include/asm-arm/arch-mv78xx0/irqs.h
3 *
4 * IRQ definitions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "mv78xx0.h" /* need GPIO_MAX */
15
16/*
17 * MV78xx0 Low Interrupt Controller
18 */
19#define IRQ_MV78XX0_ERR 0
20#define IRQ_MV78XX0_SPI 1
21#define IRQ_MV78XX0_I2C_0 2
22#define IRQ_MV78XX0_I2C_1 3
23#define IRQ_MV78XX0_IDMA_0 4
24#define IRQ_MV78XX0_IDMA_1 5
25#define IRQ_MV78XX0_IDMA_2 6
26#define IRQ_MV78XX0_IDMA_3 7
27#define IRQ_MV78XX0_TIMER_0 8
28#define IRQ_MV78XX0_TIMER_1 9
29#define IRQ_MV78XX0_TIMER_2 10
30#define IRQ_MV78XX0_TIMER_3 11
31#define IRQ_MV78XX0_UART_0 12
32#define IRQ_MV78XX0_UART_1 13
33#define IRQ_MV78XX0_UART_2 14
34#define IRQ_MV78XX0_UART_3 15
35#define IRQ_MV78XX0_USB_0 16
36#define IRQ_MV78XX0_USB_1 17
37#define IRQ_MV78XX0_USB_2 18
38#define IRQ_MV78XX0_CRYPTO 19
39#define IRQ_MV78XX0_SDIO_0 20
40#define IRQ_MV78XX0_SDIO_1 21
41#define IRQ_MV78XX0_XOR_0 22
42#define IRQ_MV78XX0_XOR_1 23
43#define IRQ_MV78XX0_I2S_0 24
44#define IRQ_MV78XX0_I2S_1 25
45#define IRQ_MV78XX0_SATA 26
46#define IRQ_MV78XX0_TDMI 27
47
48/*
49 * MV78xx0 High Interrupt Controller
50 */
51#define IRQ_MV78XX0_PCIE_00 32
52#define IRQ_MV78XX0_PCIE_01 33
53#define IRQ_MV78XX0_PCIE_02 34
54#define IRQ_MV78XX0_PCIE_03 35
55#define IRQ_MV78XX0_PCIE_10 36
56#define IRQ_MV78XX0_PCIE_11 37
57#define IRQ_MV78XX0_PCIE_12 38
58#define IRQ_MV78XX0_PCIE_13 39
59#define IRQ_MV78XX0_GE00_SUM 40
60#define IRQ_MV78XX0_GE00_RX 41
61#define IRQ_MV78XX0_GE00_TX 42
62#define IRQ_MV78XX0_GE00_MISC 43
63#define IRQ_MV78XX0_GE01_SUM 44
64#define IRQ_MV78XX0_GE01_RX 45
65#define IRQ_MV78XX0_GE01_TX 46
66#define IRQ_MV78XX0_GE01_MISC 47
67#define IRQ_MV78XX0_GE10_SUM 48
68#define IRQ_MV78XX0_GE10_RX 49
69#define IRQ_MV78XX0_GE10_TX 50
70#define IRQ_MV78XX0_GE10_MISC 51
71#define IRQ_MV78XX0_GE11_SUM 52
72#define IRQ_MV78XX0_GE11_RX 53
73#define IRQ_MV78XX0_GE11_TX 54
74#define IRQ_MV78XX0_GE11_MISC 55
75#define IRQ_MV78XX0_GPIO_0_7 56
76#define IRQ_MV78XX0_GPIO_8_15 57
77#define IRQ_MV78XX0_GPIO_16_23 58
78#define IRQ_MV78XX0_GPIO_24_31 59
79#define IRQ_MV78XX0_DB_IN 60
80#define IRQ_MV78XX0_DB_OUT 61
81
82/*
83 * MV78XX0 General Purpose Pins
84 */
85#define IRQ_MV78XX0_GPIO_START 64
86#define NR_GPIO_IRQS GPIO_MAX
87
88#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
89
90
91#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
new file mode 100644
index 000000000000..721a6b185b91
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-mv78xx0/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
new file mode 100644
index 000000000000..9f5d83c73faa
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
@@ -0,0 +1,126 @@
1/*
2 * include/asm-arm/arch-mv78xx0/mv78xx0.h
3 *
4 * Generic definitions for Marvell MV78xx0 SoC flavors:
5 * MV781x0 and MV782x0.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_MV78XX0_H
13#define __ASM_ARCH_MV78XX0_H
14
15/*
16 * Marvell MV78xx0 address maps.
17 *
18 * phys
19 * c0000000 PCIe Memory space
20 * f0800000 PCIe #0 I/O space
21 * f0900000 PCIe #1 I/O space
22 * f0a00000 PCIe #2 I/O space
23 * f0b00000 PCIe #3 I/O space
24 * f0c00000 PCIe #4 I/O space
25 * f0d00000 PCIe #5 I/O space
26 * f0e00000 PCIe #6 I/O space
27 * f0f00000 PCIe #7 I/O space
28 * f1000000 on-chip peripheral registers
29 *
30 * virt phys size
31 * fe400000 f102x000 16K core-specific peripheral registers
32 * fe700000 f0800000 1M PCIe #0 I/O space
33 * fe800000 f0900000 1M PCIe #1 I/O space
34 * fe900000 f0a00000 1M PCIe #2 I/O space
35 * fea00000 f0b00000 1M PCIe #3 I/O space
36 * feb00000 f0c00000 1M PCIe #4 I/O space
37 * fec00000 f0d00000 1M PCIe #5 I/O space
38 * fed00000 f0e00000 1M PCIe #6 I/O space
39 * fee00000 f0f00000 1M PCIe #7 I/O space
40 * fef00000 f1000000 1M on-chip peripheral registers
41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
45#define MV78XX0_CORE_REGS_SIZE SZ_16K
46
47#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
49#define MV78XX0_PCIE_IO_SIZE SZ_1M
50
51#define MV78XX0_REGS_PHYS_BASE 0xf1000000
52#define MV78XX0_REGS_VIRT_BASE 0xfef00000
53#define MV78XX0_REGS_SIZE SZ_1M
54
55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
56#define MV78XX0_PCIE_MEM_SIZE 0x30000000
57
58/*
59 * Core-specific peripheral registers.
60 */
61#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
62#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
63#define L2_WRITETHROUGH 0x00020000
64#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
65#define SOFT_RESET_OUT_EN 0x00000004
66#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
67#define SOFT_RESET 0x00000001
68#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
69#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
70#define BRIDGE_INT_TIMER0 0x0002
71#define BRIDGE_INT_TIMER1 0x0004
72#define BRIDGE_INT_TIMER1_CLR (~0x0004)
73#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
74#define IRQ_CAUSE_LOW_OFF 0x0004
75#define IRQ_CAUSE_HIGH_OFF 0x0008
76#define IRQ_MASK_LOW_OFF 0x0010
77#define IRQ_MASK_HIGH_OFF 0x0014
78#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
79
80/*
81 * Register Map
82 */
83#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
84#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
85#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
86
87#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
88#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
89#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
90#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
91#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
92#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
93#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
94#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
95#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
96#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
97#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
98#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
99
100#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
101#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
102
103#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
104#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
105#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
106#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
107
108#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
109#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
110#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
111
112#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
113#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
114
115#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
116#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
117#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
118#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
119
120#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
121
122
123#define GPIO_MAX 32
124
125
126#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
new file mode 100644
index 000000000000..7eb47d376db9
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-mv78xx0/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/mv78xx0.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
new file mode 100644
index 000000000000..a854b1ccbd01
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/timex.h
@@ -0,0 +1,9 @@
1/*
2 * include/asm-arm/arch-mv78xx0/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
new file mode 100644
index 000000000000..3bfe0a293ef7
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-mv78xx0/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/mv78xx0.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
new file mode 100644
index 000000000000..f2c512197579
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-mv78xx0/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
new file mode 100644
index 000000000000..61e66dac90ef
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx27ads.h
@@ -0,0 +1,354 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * MXC UART EVB board level configurations
30 */
31
32#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
33#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
34#define MXC_LL_EXTUART_16BIT_BUS
35
36#define MXC_LL_UART_PADDR UART1_BASE_ADDR
37#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
38
39/*
40 * @name Memory Size parameters
41 */
42
43/*
44 * Size of SDRAM memory
45 */
46#define SDRAM_MEM_SIZE SZ_128M
47
48/*
49 * PBC Controller parameters
50 */
51
52/*
53 * Base address of PBC controller, CS4
54 */
55#define PBC_BASE_ADDRESS 0xEB000000
56#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
57
58/*
59 * PBC Interupt name definitions
60 */
61#define PBC_GPIO1_0 0
62#define PBC_GPIO1_1 1
63#define PBC_GPIO1_2 2
64#define PBC_GPIO1_3 3
65#define PBC_GPIO1_4 4
66#define PBC_GPIO1_5 5
67
68#define PBC_INTR_MAX_NUM 6
69#define PBC_INTR_SHARED_MAX_NUM 8
70
71/* When the PBC address connection is fixed in h/w, defined as 1 */
72#define PBC_ADDR_SH 0
73
74/* Offsets for the PBC Controller register */
75/*
76 * PBC Board version register offset
77 */
78#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
79/*
80 * PBC Board control register 1 set address.
81 */
82#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
83/*
84 * PBC Board control register 1 clear address.
85 */
86#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
87/*
88 * PBC Board control register 2 set address.
89 */
90#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
91/*
92 * PBC Board control register 2 clear address.
93 */
94#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
95/*
96 * PBC Board control register 3 set address.
97 */
98#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
99/*
100 * PBC Board control register 3 clear address.
101 */
102#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
103/*
104 * PBC Board control register 3 set address.
105 */
106#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
107/*
108 * PBC Board control register 4 clear address.
109 */
110#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
111/*PBC_ADDR_SH
112 * PBC Board status register 1.
113 */
114#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
115/*
116 * PBC Board interrupt status register.
117 */
118#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
119/*
120 * PBC Board interrupt current status register.
121 */
122#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
123/*
124 * PBC Interrupt mask register set address.
125 */
126#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
127/*
128 * PBC Interrupt mask register clear address.
129 */
130#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
131/*
132 * External UART A.
133 */
134#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
135/*
136 * UART 4 Expanding Signal Status.
137 */
138#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
139/*
140 * UART 4 Expanding Signal Control Set.
141 */
142#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
143/*
144 * UART 4 Expanding Signal Control Clear.
145 */
146#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
147/*
148 * Ethernet Controller IO base address.
149 */
150#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
151/*
152 * Ethernet Controller Memory base address.
153 */
154#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
155/*
156 * Ethernet Controller DMA base address.
157 */
158#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
159
160/* PBC Board Version Register bit definition */
161#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
162#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
163
164/* PBC Board Control Register 1 bit definitions */
165#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
166#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
167#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
168#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
169#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
170
171/* PBC Board Control Register 2 bit definitions */
172#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
173#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
174#define PBC_BCTRL2_ATAFEC_EN 0X0010
175#define PBC_BCTRL2_ATAFEC_SEL 0X0020
176#define PBC_BCTRL2_ATA_EN 0X0040
177#define PBC_BCTRL2_IRDA_SD 0X0080
178#define PBC_BCTRL2_IRDA_EN 0X0100
179#define PBC_BCTRL2_CCTL10 0X0200
180#define PBC_BCTRL2_CCTL11 0X0400
181
182/* PBC Board Control Register 3 bit definitions */
183#define PBC_BCTRL3_HSH_EN 0X0020
184#define PBC_BCTRL3_FSH_MOD 0X0040
185#define PBC_BCTRL3_OTG_HS_EN 0X0080
186#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
187#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
188#define PBC_BCTRL3_USB_OTG_ON 0X0800
189#define PBC_BCTRL3_USB_FSH_ON 0X1000
190
191/* PBC Board Control Register 4 bit definitions */
192#define PBC_BCTRL4_REGEN_SEL 0X0001
193#define PBC_BCTRL4_USER_OFF 0X0002
194#define PBC_BCTRL4_VIB_EN 0X0004
195#define PBC_BCTRL4_PWRGT1_EN 0X0008
196#define PBC_BCTRL4_PWRGT2_EN 0X0010
197#define PBC_BCTRL4_STDBY_PRI 0X0020
198
199#ifndef __ASSEMBLY__
200/*
201 * Enumerations for SD cards and memory stick card. This corresponds to
202 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
203 */
204enum mxc_card_no {
205 MXC_CARD_SD2 = 0,
206 MXC_CARD_SD3,
207 MXC_CARD_MS,
208 MXC_CARD_SD1,
209 MXC_CARD_MIN = MXC_CARD_SD2,
210 MXC_CARD_MAX = MXC_CARD_SD1,
211};
212#endif
213
214#define MXC_CPLD_VER_1_50 0x01
215
216/*
217 * PBC BSTAT Register bit definitions
218 */
219#define PBC_BSTAT_PRI_INT 0X0001
220#define PBC_BSTAT_USB_BYP 0X0002
221#define PBC_BSTAT_ATA_IOCS16 0X0004
222#define PBC_BSTAT_ATA_CBLID 0X0008
223#define PBC_BSTAT_ATA_DASP 0X0010
224#define PBC_BSTAT_PWR_RDY 0X0020
225#define PBC_BSTAT_SD3_WP 0X0100
226#define PBC_BSTAT_SD2_WP 0X0200
227#define PBC_BSTAT_SD1_WP 0X0400
228#define PBC_BSTAT_SD3_DET 0X0800
229#define PBC_BSTAT_SD2_DET 0X1000
230#define PBC_BSTAT_SD1_DET 0X2000
231#define PBC_BSTAT_MS_DET 0X4000
232#define PBC_BSTAT_SD3_DET_BIT 11
233#define PBC_BSTAT_SD2_DET_BIT 12
234#define PBC_BSTAT_SD1_DET_BIT 13
235#define PBC_BSTAT_MS_DET_BIT 14
236#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
237 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
238 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
239 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
240 0x0))))
241
242/*
243 * PBC UART Control Register bit definitions
244 */
245#define PBC_UCTRL_DCE_DCD 0X0001
246#define PBC_UCTRL_DCE_DSR 0X0002
247#define PBC_UCTRL_DCE_RI 0X0004
248#define PBC_UCTRL_DTE_DTR 0X0100
249
250/*
251 * PBC UART Status Register bit definitions
252 */
253#define PBC_USTAT_DTE_DCD 0X0001
254#define PBC_USTAT_DTE_DSR 0X0002
255#define PBC_USTAT_DTE_RI 0X0004
256#define PBC_USTAT_DCE_DTR 0X0100
257
258/*
259 * PBC Interupt mask register bit definitions
260 */
261#define PBC_INTR_SD3_R_EN_BIT 4
262#define PBC_INTR_SD2_R_EN_BIT 0
263#define PBC_INTR_SD1_R_EN_BIT 6
264#define PBC_INTR_MS_R_EN_BIT 5
265#define PBC_INTR_SD3_EN_BIT 13
266#define PBC_INTR_SD2_EN_BIT 12
267#define PBC_INTR_MS_EN_BIT 14
268#define PBC_INTR_SD1_EN_BIT 15
269
270#define PBC_INTR_SD2_R_EN 0x0001
271#define PBC_INTR_LOW_BAT 0X0002
272#define PBC_INTR_OTG_FSOVER 0X0004
273#define PBC_INTR_FSH_OVER 0X0008
274#define PBC_INTR_SD3_R_EN 0x0010
275#define PBC_INTR_MS_R_EN 0x0020
276#define PBC_INTR_SD1_R_EN 0x0040
277#define PBC_INTR_FEC_INT 0X0080
278#define PBC_INTR_ENET_INT 0X0100
279#define PBC_INTR_OTGFS_INT 0X0200
280#define PBC_INTR_XUART_INT 0X0400
281#define PBC_INTR_CCTL12 0X0800
282#define PBC_INTR_SD2_EN 0x1000
283#define PBC_INTR_SD3_EN 0x2000
284#define PBC_INTR_MS_EN 0x4000
285#define PBC_INTR_SD1_EN 0x8000
286
287
288
289/* For interrupts like xuart, enet etc */
290#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
291#define MXC_MAX_EXP_IO_LINES 16
292
293/*
294 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
295 *
296 */
297#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
298#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
299#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
300#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
301#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
302#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
303#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
304#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
305#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
306#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
307#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
308#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
309#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
310#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
311#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
312
313/*
314 * This is System IRQ used by CS8900A for interrupt generation
315 * taken from platform.h
316 */
317#define CS8900AIRQ EXPIO_INT_ENET_INT
318/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
319#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
320
321#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
322
323/*
324* This is used to detect if the CPLD version is for mx27 evb board rev-a
325*/
326#define PBC_CPLD_VERSION_IS_REVA() \
327 ((__raw_readw(PBC_VERSION_REG) & \
328 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
329 == 0)
330
331/* This is used to active or inactive ata signal in CPLD .
332 * It is dependent with hardware
333 */
334#define PBC_ATA_SIGNAL_ACTIVE() \
335 __raw_writew( \
336 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
337 PBC_BCTRL2_CLEAR_REG)
338
339#define PBC_ATA_SIGNAL_INACTIVE() \
340 __raw_writew( \
341 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
342 PBC_BCTRL2_SET_REG)
343
344#define MXC_BD_LED1 (1 << 5)
345#define MXC_BD_LED2 (1 << 6)
346#define MXC_BD_LED_ON(led) \
347 __raw_writew(led, PBC_BCTRL1_SET_REG)
348#define MXC_BD_LED_OFF(led) \
349 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
350
351/* to determine the correct external crystal reference */
352#define CKIH_27MHZ_BIT_SET (1 << 3)
353
354#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
index 8590127760a8..1bc6fb0f9a83 100644
--- a/include/asm-arm/arch-mxc/board-mx31ads.h
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -109,4 +109,9 @@
109 109
110#define MXC_MAX_EXP_IO_LINES 16 110#define MXC_MAX_EXP_IO_LINES 16
111 111
112/* mandatory for CONFIG_LL_DEBUG */
113
114#define MXC_LL_UART_PADDR UART1_BASE_ADDR
115#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
116
112#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */ 117#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/board-mx31lite.h b/include/asm-arm/arch-mxc/board-mx31lite.h
new file mode 100644
index 000000000000..e4e5cf5ad7db
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31lite.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_BOARD_MX31LITE_H__
12#define __ASM_ARCH_MXC_BOARD_MX31LITE_H__
13
14#define MXC_MAX_EXP_IO_LINES 16
15
16
17/*
18 * Memory Size parameters
19 */
20
21/*
22 * Size of SDRAM memory
23 */
24#define SDRAM_MEM_SIZE SZ_128M
25/*
26 * Size of MBX buffer memory
27 */
28#define MXC_MBX_MEM_SIZE SZ_16M
29/*
30 * Size of memory available to kernel
31 */
32#define MEM_SIZE (SDRAM_MEM_SIZE - MXC_MBX_MEM_SIZE)
33
34#define MXC_LL_UART_PADDR UART1_BASE_ADDR
35#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
36
37#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
38
diff --git a/include/asm-arm/arch-mxc/board-pcm037.h b/include/asm-arm/arch-mxc/board-pcm037.h
new file mode 100644
index 000000000000..82232ba3c8fc
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm037.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM037_H__
20#define __ASM_ARCH_MXC_BOARD_PCM037_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
26
27#endif /* __ASM_ARCH_MXC_BOARD_PCM037_H__ */
diff --git a/include/asm-arm/arch-mxc/board-pcm038.h b/include/asm-arm/arch-mxc/board-pcm038.h
new file mode 100644
index 000000000000..750c62afd90f
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-pcm038.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_BOARD_PCM038_H__
20#define __ASM_ARCH_MXC_BOARD_PCM038_H__
21
22/* mandatory for CONFIG_LL_DEBUG */
23
24#define MXC_LL_UART_PADDR UART1_BASE_ADDR
25#define MXC_LL_UART_VADDR (AIPI_BASE_ADDR_VIRT + 0x0A000)
26
27#ifndef __ASSEMBLY__
28/*
29 * This CPU module needs a baseboard to work. After basic initializing
30 * its own devices, it calls baseboard's init function.
31 * TODO: Add your own baseboard init function and call it from
32 * inside pcm038_init().
33 *
34 * This example here is for the development board. Refer pcm970-baseboard.c
35 */
36
37extern void pcm970_baseboard_init(void);
38
39#endif
40
41#endif /* __ASM_ARCH_MXC_BOARD_PCM038_H__ */
diff --git a/include/asm-arm/arch-mxc/clock.h b/include/asm-arm/arch-mxc/clock.h
new file mode 100644
index 000000000000..24caa2b7c91d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/clock.h
@@ -0,0 +1,67 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_CLOCK_H__
21#define __ASM_ARCH_MXC_CLOCK_H__
22
23#ifndef __ASSEMBLY__
24#include <linux/list.h>
25
26struct module;
27
28struct clk {
29 struct list_head node;
30 struct module *owner;
31 const char *name;
32 int id;
33 /* Source clock this clk depends on */
34 struct clk *parent;
35 /* Secondary clock to enable/disable with this clock */
36 struct clk *secondary;
37 /* Reference count of clock enable/disable */
38 __s8 usecount;
39 /* Register bit position for clock's enable/disable control. */
40 u8 enable_shift;
41 /* Register address for clock's enable/disable control. */
42 u32 enable_reg;
43 u32 flags;
44 /* get the current clock rate (always a fresh value) */
45 unsigned long (*get_rate) (struct clk *);
46 /* Function ptr to set the clock to a new rate. The rate must match a
47 supported rate returned from round_rate. Leave blank if clock is not
48 programmable */
49 int (*set_rate) (struct clk *, unsigned long);
50 /* Function ptr to round the requested clock rate to the nearest
51 supported rate that is less than or equal to the requested rate. */
52 unsigned long (*round_rate) (struct clk *, unsigned long);
53 /* Function ptr to enable the clock. Leave blank if clock can not
54 be gated. */
55 int (*enable) (struct clk *);
56 /* Function ptr to disable the clock. Leave blank if clock can not
57 be gated. */
58 void (*disable) (struct clk *);
59 /* Function ptr to set the parent clock of the clock. */
60 int (*set_parent) (struct clk *, struct clk *);
61};
62
63int clk_register(struct clk *clk);
64void clk_unregister(struct clk *clk);
65
66#endif /* __ASSEMBLY__ */
67#endif /* __ASM_ARCH_MXC_CLOCK_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
index 23b4350edbd6..a6d2e24aab15 100644
--- a/include/asm-arm/arch-mxc/common.h
+++ b/include/asm-arm/arch-mxc/common.h
@@ -11,10 +11,10 @@
11#ifndef __ASM_ARCH_MXC_COMMON_H__ 11#ifndef __ASM_ARCH_MXC_COMMON_H__
12#define __ASM_ARCH_MXC_COMMON_H__ 12#define __ASM_ARCH_MXC_COMMON_H__
13 13
14struct sys_timer;
15
16extern void mxc_map_io(void); 14extern void mxc_map_io(void);
17extern void mxc_init_irq(void); 15extern void mxc_init_irq(void);
18extern struct sys_timer mxc_timer; 16extern void mxc_timer_init(const char *clk_timer);
17extern int mxc_clocks_init(unsigned long fref);
18extern int mxc_register_gpios(void);
19 19
20#endif 20#endif
diff --git a/include/asm-arm/arch-mxc/debug-macro.S b/include/asm-arm/arch-mxc/debug-macro.S
new file mode 100644
index 000000000000..575087f8561a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/debug-macro.S
@@ -0,0 +1,49 @@
1/* linux/include/asm-arm/arch-imx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <asm/arch/hardware.h>
15
16#ifdef CONFIG_MACH_MX31ADS
17#include <asm/arch/board-mx31ads.h>
18#endif
19#ifdef CONFIG_MACH_PCM037
20#include <asm/arch/board-pcm037.h>
21#endif
22#ifdef CONFIG_MACH_MX31LITE
23#include <asm/arch/board-mx31lite.h>
24#endif
25#ifdef CONFIG_MACH_MX27ADS
26#include <asm/arch/board-mx27ads.h>
27#endif
28#ifdef CONFIG_MACH_PCM038
29#include <asm/arch/board-pcm038.h>
30#endif
31 .macro addruart,rx
32 mrc p15, 0, \rx, c1, c0
33 tst \rx, #1 @ MMU enabled?
34 ldreq \rx, =MXC_LL_UART_PADDR @ physical
35 ldrne \rx, =MXC_LL_UART_VADDR @ virtual
36 .endm
37
38 .macro senduart,rd,rx
39 str \rd, [\rx, #0x40] @ TXDATA
40 .endm
41
42 .macro waituart,rd,rx
43 .endm
44
45 .macro busyuart,rd,rx
461002: ldr \rd, [\rx, #0x98] @ SR2
47 tst \rd, #1 << 3 @ TXDC
48 beq 1002b @ wait until transmit done
49 .endm
diff --git a/include/asm-arm/arch-mxc/gpio.h b/include/asm-arm/arch-mxc/gpio.h
new file mode 100644
index 000000000000..d393e15f5a6b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/gpio.h
@@ -0,0 +1,42 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
17 */
18
19#ifndef __ASM_ARCH_MXC_GPIO_H__
20#define __ASM_ARCH_MXC_GPIO_H__
21
22#include <asm/hardware.h>
23#include <asm-generic/gpio.h>
24
25/* use gpiolib dispatchers */
26#define gpio_get_value __gpio_get_value
27#define gpio_set_value __gpio_set_value
28#define gpio_cansleep __gpio_cansleep
29
30#define gpio_to_irq(gpio) (MXC_MAX_INT_LINES + (gpio))
31#define irq_to_gpio(irq) ((irq) - MXC_MAX_INT_LINES)
32
33struct mxc_gpio_port {
34 void __iomem *base;
35 int irq;
36 int virtual_irq_start;
37 struct gpio_chip chip;
38};
39
40int mxc_gpio_init(struct mxc_gpio_port*, int);
41
42#endif
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
index e87ff0679d5e..37cddbaaade7 100644
--- a/include/asm-arm/arch-mxc/hardware.h
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_HARDWARE_H__ 20#ifndef __ASM_ARCH_MXC_HARDWARE_H__
@@ -17,15 +26,12 @@
17# include <asm/arch/mx31.h> 26# include <asm/arch/mx31.h>
18#endif 27#endif
19 28
20#include <asm/arch/mxc.h> 29#ifdef CONFIG_ARCH_MX2
21 30# ifdef CONFIG_MACH_MX27
22/* 31# include <asm/arch/mx27.h>
23 * --------------------------------------------------------------------------- 32# endif
24 * Board specific defines
25 * ---------------------------------------------------------------------------
26 */
27#ifdef CONFIG_MACH_MX31ADS
28# include <asm/arch/board-mx31ads.h>
29#endif 33#endif
30 34
35#include <asm/arch/mxc.h>
36
31#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 37#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/iim.h b/include/asm-arm/arch-mxc/iim.h
new file mode 100644
index 000000000000..315bffadafda
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iim.h
@@ -0,0 +1,77 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_IIM_H__
21#define __ASM_ARCH_MXC_IIM_H__
22
23/* Register offsets */
24#define MXC_IIMSTAT 0x0000
25#define MXC_IIMSTATM 0x0004
26#define MXC_IIMERR 0x0008
27#define MXC_IIMEMASK 0x000C
28#define MXC_IIMFCTL 0x0010
29#define MXC_IIMUA 0x0014
30#define MXC_IIMLA 0x0018
31#define MXC_IIMSDAT 0x001C
32#define MXC_IIMPREV 0x0020
33#define MXC_IIMSREV 0x0024
34#define MXC_IIMPRG_P 0x0028
35#define MXC_IIMSCS0 0x002C
36#define MXC_IIMSCS1 0x0030
37#define MXC_IIMSCS2 0x0034
38#define MXC_IIMSCS3 0x0038
39#define MXC_IIMFBAC0 0x0800
40#define MXC_IIMJAC 0x0804
41#define MXC_IIMHWV1 0x0808
42#define MXC_IIMHWV2 0x080C
43#define MXC_IIMHAB0 0x0810
44#define MXC_IIMHAB1 0x0814
45/* Definitions for i.MX27 TO2 */
46#define MXC_IIMMAC 0x0814
47#define MXC_IIMPREV_FUSE 0x0818
48#define MXC_IIMSREV_FUSE 0x081C
49#define MXC_IIMSJC_CHALL_0 0x0820
50#define MXC_IIMSJC_CHALL_7 0x083C
51#define MXC_IIMFB0UC17 0x0840
52#define MXC_IIMFB0UC255 0x0BFC
53#define MXC_IIMFBAC1 0x0C00
54/* Definitions for i.MX27 TO2 */
55#define MXC_IIMSUID 0x0C04
56#define MXC_IIMKEY0 0x0C04
57#define MXC_IIMKEY20 0x0C54
58#define MXC_IIMSJC_RESP_0 0x0C58
59#define MXC_IIMSJC_RESP_7 0x0C74
60#define MXC_IIMFB1UC30 0x0C78
61#define MXC_IIMFB1UC255 0x0FFC
62
63/* Bit definitions */
64
65#define MXC_IIMHWV1_WLOCK (0x1 << 7)
66#define MXC_IIMHWV1_MCU_ENDIAN (0x1 << 6)
67#define MXC_IIMHWV1_DSP_ENDIAN (0x1 << 5)
68#define MXC_IIMHWV1_BOOT_INT (0x1 << 4)
69#define MXC_IIMHWV1_SCC_DISABLE (0x1 << 3)
70#define MXC_IIMHWV1_HANTRO_DISABLE (0x1 << 2)
71#define MXC_IIMHWV1_MEMSTICK_DIS (0x1 << 1)
72
73#define MXC_IIMHWV2_WLOCK (0x1 << 7)
74#define MXC_IIMHWV2_BP_SDMA (0x1 << 6)
75#define MXC_IIMHWV2_SCM_DCM (0x1 << 5)
76
77#endif /* __ASM_ARCH_MXC_IIM_H__ */
diff --git a/include/asm-arm/arch-mxc/imx-uart.h b/include/asm-arm/arch-mxc/imx-uart.h
new file mode 100644
index 000000000000..83fb72c4048a
--- /dev/null
+++ b/include/asm-arm/arch-mxc/imx-uart.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef ASMARM_ARCH_UART_H
20#define ASMARM_ARCH_UART_H
21
22#define IMXUART_HAVE_RTSCTS (1<<0)
23
24struct imxuart_platform_data {
25 int (*init)(struct platform_device *pdev);
26 int (*exit)(struct platform_device *pdev);
27 unsigned int flags;
28};
29
30int __init imx_init_uart(int uart_no, struct imxuart_platform_data *pdata);
31
32#endif
diff --git a/include/asm-arm/arch-mxc/iomux-mx1-mx2.h b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
new file mode 100644
index 000000000000..076d37b38eb2
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx1-mx2.h
@@ -0,0 +1,372 @@
1/*
2 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef _MXC_GPIO_MX1_MX2_H
20#define _MXC_GPIO_MX1_MX2_H
21
22#include <linux/io.h>
23
24#define MXC_GPIO_ALLOC_MODE_NORMAL 0
25#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1
26#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2
27#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4
28#define MXC_GPIO_ALLOC_MODE_RELEASE 8
29
30/*
31 * GPIO Module and I/O Multiplexer
32 * x = 0..3 for reg_A, reg_B, reg_C, reg_D
33 */
34#define VA_GPIO_BASE IO_ADDRESS(GPIO_BASE_ADDR)
35#define MXC_DDIR(x) (0x00 + ((x) << 8))
36#define MXC_OCR1(x) (0x04 + ((x) << 8))
37#define MXC_OCR2(x) (0x08 + ((x) << 8))
38#define MXC_ICONFA1(x) (0x0c + ((x) << 8))
39#define MXC_ICONFA2(x) (0x10 + ((x) << 8))
40#define MXC_ICONFB1(x) (0x14 + ((x) << 8))
41#define MXC_ICONFB2(x) (0x18 + ((x) << 8))
42#define MXC_DR(x) (0x1c + ((x) << 8))
43#define MXC_GIUS(x) (0x20 + ((x) << 8))
44#define MXC_SSR(x) (0x24 + ((x) << 8))
45#define MXC_ICR1(x) (0x28 + ((x) << 8))
46#define MXC_ICR2(x) (0x2c + ((x) << 8))
47#define MXC_IMR(x) (0x30 + ((x) << 8))
48#define MXC_ISR(x) (0x34 + ((x) << 8))
49#define MXC_GPR(x) (0x38 + ((x) << 8))
50#define MXC_SWR(x) (0x3c + ((x) << 8))
51#define MXC_PUEN(x) (0x40 + ((x) << 8))
52
53#ifdef CONFIG_ARCH_MX1
54# define GPIO_PORT_MAX 3
55#endif
56#ifdef CONFIG_ARCH_MX2
57# define GPIO_PORT_MAX 5
58#endif
59
60#ifndef GPIO_PORT_MAX
61# error "GPIO config port count unknown!"
62#endif
63
64#define GPIO_PIN_MASK 0x1f
65
66#define GPIO_PORT_SHIFT 5
67#define GPIO_PORT_MASK (0x7 << GPIO_PORT_SHIFT)
68
69#define GPIO_PORTA (0 << GPIO_PORT_SHIFT)
70#define GPIO_PORTB (1 << GPIO_PORT_SHIFT)
71#define GPIO_PORTC (2 << GPIO_PORT_SHIFT)
72#define GPIO_PORTD (3 << GPIO_PORT_SHIFT)
73#define GPIO_PORTE (4 << GPIO_PORT_SHIFT)
74#define GPIO_PORTF (5 << GPIO_PORT_SHIFT)
75
76#define GPIO_OUT (1 << 8)
77#define GPIO_IN (0 << 8)
78#define GPIO_PUEN (1 << 9)
79
80#define GPIO_PF (1 << 10)
81#define GPIO_AF (1 << 11)
82
83#define GPIO_OCR_SHIFT 12
84#define GPIO_OCR_MASK (3 << GPIO_OCR_SHIFT)
85#define GPIO_AIN (0 << GPIO_OCR_SHIFT)
86#define GPIO_BIN (1 << GPIO_OCR_SHIFT)
87#define GPIO_CIN (2 << GPIO_OCR_SHIFT)
88#define GPIO_GPIO (3 << GPIO_OCR_SHIFT)
89
90#define GPIO_AOUT_SHIFT 14
91#define GPIO_AOUT_MASK (3 << GPIO_AOUT_SHIFT)
92#define GPIO_AOUT (0 << GPIO_AOUT_SHIFT)
93#define GPIO_AOUT_ISR (1 << GPIO_AOUT_SHIFT)
94#define GPIO_AOUT_0 (2 << GPIO_AOUT_SHIFT)
95#define GPIO_AOUT_1 (3 << GPIO_AOUT_SHIFT)
96
97#define GPIO_BOUT_SHIFT 16
98#define GPIO_BOUT_MASK (3 << GPIO_BOUT_SHIFT)
99#define GPIO_BOUT (0 << GPIO_BOUT_SHIFT)
100#define GPIO_BOUT_ISR (1 << GPIO_BOUT_SHIFT)
101#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
102#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
103
104extern void mxc_gpio_mode(int gpio_mode);
105extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
106 int alloc_mode, const char *label);
107
108/*-------------------------------------------------------------------------*/
109
110/* assignements for GPIO alternate/primary functions */
111
112/* FIXME: This list is not completed. The correct directions are
113 * missing on some (many) pins
114 */
115#ifdef CONFIG_ARCH_MX1
116#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
117#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
118#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
119#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
120#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
121#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
122#define PA4_PF_CSI_D0 (GPIO_PORTA | GPIO_PF | 4)
123#define PA5_PF_CSI_D1 (GPIO_PORTA | GPIO_PF | 5)
124#define PA6_PF_CSI_D2 (GPIO_PORTA | GPIO_PF | 6)
125#define PA7_PF_CSI_D3 (GPIO_PORTA | GPIO_PF | 7)
126#define PA8_PF_CSI_D4 (GPIO_PORTA | GPIO_PF | 8)
127#define PA9_PF_CSI_D5 (GPIO_PORTA | GPIO_PF | 9)
128#define PA10_PF_CSI_D6 (GPIO_PORTA | GPIO_PF | 10)
129#define PA11_PF_CSI_D7 (GPIO_PORTA | GPIO_PF | 11)
130#define PA12_PF_CSI_VSYNC (GPIO_PORTA | GPIO_PF | 12)
131#define PA13_PF_CSI_HSYNC (GPIO_PORTA | GPIO_PF | 13)
132#define PA14_PF_CSI_PIXCLK (GPIO_PORTA | GPIO_PF | 14)
133#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
134#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
135#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
136#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
137#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
138#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
139#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
140#define PA21_PF_A0 (GPIO_PORTA | GPIO_PF | 21)
141#define PA22_PF_CS4 (GPIO_PORTA | GPIO_PF | 22)
142#define PA23_PF_CS5 (GPIO_PORTA | GPIO_PF | 23)
143#define PA24_PF_A16 (GPIO_PORTA | GPIO_PF | 24)
144#define PA24_AF_ETMTRACEPKT0 (GPIO_PORTA | GPIO_AF | 24)
145#define PA25_PF_A17 (GPIO_PORTA | GPIO_PF | 25)
146#define PA25_AF_ETMTRACEPKT1 (GPIO_PORTA | GPIO_AF | 25)
147#define PA26_PF_A18 (GPIO_PORTA | GPIO_PF | 26)
148#define PA26_AF_ETMTRACEPKT2 (GPIO_PORTA | GPIO_AF | 26)
149#define PA27_PF_A19 (GPIO_PORTA | GPIO_PF | 27)
150#define PA27_AF_ETMTRACEPKT3 (GPIO_PORTA | GPIO_AF | 27)
151#define PA28_PF_A20 (GPIO_PORTA | GPIO_PF | 28)
152#define PA28_AF_ETMPIPESTAT0 (GPIO_PORTA | GPIO_AF | 28)
153#define PA29_PF_A21 (GPIO_PORTA | GPIO_PF | 29)
154#define PA29_AF_ETMPIPESTAT1 (GPIO_PORTA | GPIO_AF | 29)
155#define PA30_PF_A22 (GPIO_PORTA | GPIO_PF | 30)
156#define PA30_AF_ETMPIPESTAT2 (GPIO_PORTA | GPIO_AF | 30)
157#define PA31_PF_A23 (GPIO_PORTA | GPIO_PF | 31)
158#define PA31_AF_ETMTRACECLK (GPIO_PORTA | GPIO_AF | 31)
159#define PB8_PF_SD_DAT0 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8)
160#define PB8_AF_MS_PIO (GPIO_PORTB | GPIO_AF | 8)
161#define PB9_PF_SD_DAT1 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9)
162#define PB9_AF_MS_PI1 (GPIO_PORTB | GPIO_AF | 9)
163#define PB10_PF_SD_DAT2 (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10)
164#define PB10_AF_MS_SCLKI (GPIO_PORTB | GPIO_AF | 10)
165#define PB11_PF_SD_DAT3 (GPIO_PORTB | GPIO_PF | 11)
166#define PB11_AF_MS_SDIO (GPIO_PORTB | GPIO_AF | 11)
167#define PB12_PF_SD_CLK (GPIO_PORTB | GPIO_PF | 12)
168#define PB12_AF_MS_SCLK0 (GPIO_PORTB | GPIO_AF | 12)
169#define PB13_PF_SD_CMD (GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13)
170#define PB13_AF_MS_BS (GPIO_PORTB | GPIO_AF | 13)
171#define PB14_AF_SSI_RXFS (GPIO_PORTB | GPIO_AF | 14)
172#define PB15_AF_SSI_RXCLK (GPIO_PORTB | GPIO_AF | 15)
173#define PB16_AF_SSI_RXDAT (GPIO_PORTB | GPIO_IN | GPIO_AF | 16)
174#define PB17_AF_SSI_TXDAT (GPIO_PORTB | GPIO_OUT | GPIO_AF | 17)
175#define PB18_AF_SSI_TXFS (GPIO_PORTB | GPIO_AF | 18)
176#define PB19_AF_SSI_TXCLK (GPIO_PORTB | GPIO_AF | 19)
177#define PB20_PF_USBD_AFE (GPIO_PORTB | GPIO_PF | 20)
178#define PB21_PF_USBD_OE (GPIO_PORTB | GPIO_PF | 21)
179#define PB22_PFUSBD_RCV (GPIO_PORTB | GPIO_PF | 22)
180#define PB23_PF_USBD_SUSPND (GPIO_PORTB | GPIO_PF | 23)
181#define PB24_PF_USBD_VP (GPIO_PORTB | GPIO_PF | 24)
182#define PB25_PF_USBD_VM (GPIO_PORTB | GPIO_PF | 25)
183#define PB26_PF_USBD_VPO (GPIO_PORTB | GPIO_PF | 26)
184#define PB27_PF_USBD_VMO (GPIO_PORTB | GPIO_PF | 27)
185#define PB28_PF_UART2_CTS (GPIO_PORTB | GPIO_OUT | GPIO_PF | 28)
186#define PB29_PF_UART2_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 29)
187#define PB30_PF_UART2_TXD (GPIO_PORTB | GPIO_OUT | GPIO_PF | 30)
188#define PB31_PF_UART2_RXD (GPIO_PORTB | GPIO_IN | GPIO_PF | 31)
189#define PC3_PF_SSI_RXFS (GPIO_PORTC | GPIO_PF | 3)
190#define PC4_PF_SSI_RXCLK (GPIO_PORTC | GPIO_PF | 4)
191#define PC5_PF_SSI_RXDAT (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
192#define PC6_PF_SSI_TXDAT (GPIO_PORTC | GPIO_OUT | GPIO_PF | 6)
193#define PC7_PF_SSI_TXFS (GPIO_PORTC | GPIO_PF | 7)
194#define PC8_PF_SSI_TXCLK (GPIO_PORTC | GPIO_PF | 8)
195#define PC9_PF_UART1_CTS (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
196#define PC10_PF_UART1_RTS (GPIO_PORTC | GPIO_IN | GPIO_PF | 10)
197#define PC11_PF_UART1_TXD (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
198#define PC12_PF_UART1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 12)
199#define PC13_PF_SPI1_SPI_RDY (GPIO_PORTC | GPIO_PF | 13)
200#define PC14_PF_SPI1_SCLK (GPIO_PORTC | GPIO_PF | 14)
201#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
202#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
203#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
204#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
205#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
206#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
207#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
208#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
209#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
210#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
211#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
212#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
213#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
214#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
215#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
216#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
217#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
218#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
219#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
220#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
221#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
222#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
223#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
224#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
225#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
226#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
227#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
228#define PD14_PF_FLM_VSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 14)
229#define PD15_PF_LD0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 15)
230#define PD16_PF_LD1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 16)
231#define PD17_PF_LD2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
232#define PD18_PF_LD3 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
233#define PD19_PF_LD4 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 19)
234#define PD20_PF_LD5 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 20)
235#define PD21_PF_LD6 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 21)
236#define PD22_PF_LD7 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 22)
237#define PD23_PF_LD8 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 23)
238#define PD24_PF_LD9 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 24)
239#define PD25_PF_LD10 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
240#define PD26_PF_LD11 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
241#define PD27_PF_LD12 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
242#define PD28_PF_LD13 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
243#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
244#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
245#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
246#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
247#endif
248
249#ifdef CONFIG_ARCH_MX2
250#define PA5_PF_LSCLK (GPIO_PORTA | GPIO_OUT | GPIO_PF | 5)
251#define PA6_PF_LD0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 6)
252#define PA7_PF_LD1 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 7)
253#define PA8_PF_LD2 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 8)
254#define PA9_PF_LD3 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 9)
255#define PA10_PF_LD4 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 10)
256#define PA11_PF_LD5 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 11)
257#define PA12_PF_LD6 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 12)
258#define PA13_PF_LD7 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 13)
259#define PA14_PF_LD8 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 14)
260#define PA15_PF_LD9 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
261#define PA16_PF_LD10 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
262#define PA17_PF_LD11 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 17)
263#define PA18_PF_LD12 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 18)
264#define PA19_PF_LD13 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 19)
265#define PA20_PF_LD14 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 20)
266#define PA21_PF_LD15 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 21)
267#define PA22_PF_LD16 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 22)
268#define PA23_PF_LD17 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 23)
269#define PA24_PF_REV (GPIO_PORTA | GPIO_OUT | GPIO_PF | 24)
270#define PA25_PF_CLS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 25)
271#define PA26_PF_PS (GPIO_PORTA | GPIO_OUT | GPIO_PF | 26)
272#define PA27_PF_SPL_SPR (GPIO_PORTA | GPIO_OUT | GPIO_PF | 27)
273#define PA28_PF_HSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 28)
274#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
275#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
276#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
277#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
278#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
279#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
280#define PB11_AF_UART6_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 11)
281#define PB12_PF_CSI_D2 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 12)
282#define PB12_AF_UART6_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 12)
283#define PB13_PF_CSI_D3 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 13)
284#define PB13_AF_UART6_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 13)
285#define PB14_PF_CSI_D4 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 14)
286#define PB15_PF_CSI_MCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 15)
287#define PB16_PF_CSI_PIXCLK (GPIO_PORTB | GPIO_OUT | GPIO_PF | 16)
288#define PB17_PF_CSI_D5 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 17)
289#define PB18_PF_CSI_D6 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 18)
290#define PB18_AF_UART5_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 18)
291#define PB19_PF_CSI_D7 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 19)
292#define PB19_AF_UART5_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 19)
293#define PB20_PF_CSI_VSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 20)
294#define PB20_AF_UART5_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 20)
295#define PB21_PF_CSI_HSYNC (GPIO_PORTB | GPIO_OUT | GPIO_PF | 21)
296#define PB21_AF_UART5_RTS (GPIO_PORTB | GPIO_IN | GPIO_AF | 21)
297#define PB26_AF_UART4_RTS (GPIO_PORTB | GPIO_IN | GPIO_PF | 26)
298#define PB28_AF_UART4_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 28)
299#define PB29_AF_UART4_CTS (GPIO_PORTB | GPIO_OUT | GPIO_AF | 29)
300#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
301#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
302#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
303#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
304#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
305#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
306#define PC19_PF_SSI4_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 19)
307#define PC20_PF_SSI1_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 20)
308#define PC21_PF_SSI1_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 21)
309#define PC22_PF_SSI1_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 22)
310#define PC23_PF_SSI1_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 23)
311#define PC24_PF_SSI2_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 24)
312#define PC25_PF_SSI2_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 25)
313#define PC26_PF_SSI2_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 26)
314#define PC27_PF_SSI2_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 27)
315#define PC28_PF_SSI3_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 28)
316#define PC29_PF_SSI3_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 29)
317#define PC30_PF_SSI3_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 30)
318#define PC31_PF_SSI3_CLK (GPIO_PORTC | GPIO_IN | GPIO_PF | 31)
319#define PD0_AIN_FEC_TXD0 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 0)
320#define PD1_AIN_FEC_TXD1 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 1)
321#define PD2_AIN_FEC_TXD2 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 2)
322#define PD3_AIN_FEC_TXD3 (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 3)
323#define PD4_AOUT_FEC_RX_ER (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 4)
324#define PD5_AOUT_FEC_RXD1 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 5)
325#define PD6_AOUT_FEC_RXD2 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 6)
326#define PD7_AOUT_FEC_RXD3 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 7)
327#define PD8_AF_FEC_MDIO (GPIO_PORTD | GPIO_IN | GPIO_AF | 8)
328#define PD9_AIN_FEC_MDC (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 9)
329#define PD10_AOUT_FEC_CRS (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 10)
330#define PD11_AOUT_FEC_TX_CLK (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 11)
331#define PD12_AOUT_FEC_RXD0 (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 12)
332#define PD13_AOUT_FEC_RX_DV (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 13)
333#define PD14_AOUT_FEC_CLR (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 14)
334#define PD15_AOUT_FEC_COL (GPIO_PORTD | GPIO_IN | GPIO_AOUT | 15)
335#define PD16_AIN_FEC_TX_ER (GPIO_PORTD | GPIO_OUT | GPIO_AIN | 16)
336#define PD17_PF_I2C_DATA (GPIO_PORTD | GPIO_OUT | GPIO_PF | 17)
337#define PD18_PF_I2C_CLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 18)
338#define PD25_PF_CSPI1_RDY (GPIO_PORTD | GPIO_OUT | GPIO_PF | 25)
339#define PD26_PF_CSPI1_SS2 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 26)
340#define PD27_PF_CSPI1_SS1 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 27)
341#define PD28_PF_CSPI1_SS0 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 28)
342#define PD29_PF_CSPI1_SCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
343#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
344#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
345#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
346#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
347#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
348#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
349#define PE7_PF_UART2_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 7)
350#define PE8_PF_UART3_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 8)
351#define PE9_PF_UART3_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 9)
352#define PE10_PF_UART3_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 10)
353#define PE11_PF_UART3_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 11)
354#define PE12_PF_UART1_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 12)
355#define PE13_PF_UART1_RXD (GPIO_PORTE | GPIO_IN | GPIO_PF | 13)
356#define PE14_PF_UART1_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 14)
357#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
358#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
359#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
360#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
361#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
362#endif
363
364/* decode irq number to use with IMR(x), ISR(x) and friends */
365#define IRQ_TO_REG(irq) ((irq - MXC_MAX_INT_LINES) >> 5)
366
367#define IRQ_GPIOA(x) (MXC_MAX_INT_LINES + x)
368#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
369#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
370#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
371
372#endif /* _MXC_GPIO_MX1_MX2_H */
diff --git a/include/asm-arm/arch-mxc/iomux-mx3.h b/include/asm-arm/arch-mxc/iomux-mx3.h
new file mode 100644
index 000000000000..7509e7692f08
--- /dev/null
+++ b/include/asm-arm/arch-mxc/iomux-mx3.h
@@ -0,0 +1,501 @@
1/*
2 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MX31_IOMUX_H__
21#define __MACH_MX31_IOMUX_H__
22
23#include <linux/types.h>
24
25/*
26 * various IOMUX output functions
27 */
28
29#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
30#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
31#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
32#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
33#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
34#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
35#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
36#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
37#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
38#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
39#define IOMUX_ICONFIG_FUNC 2 /* used as function */
40#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
41#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
42
43#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
44#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
45#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
46#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
47
48/*
49 * various IOMUX pad functions
50 */
51enum iomux_pad_config {
52 PAD_CTL_NOLOOPBACK = 0x0 << 9,
53 PAD_CTL_LOOPBACK = 0x1 << 9,
54 PAD_CTL_PKE_NONE = 0x0 << 8,
55 PAD_CTL_PKE_ENABLE = 0x1 << 8,
56 PAD_CTL_PUE_KEEPER = 0x0 << 7,
57 PAD_CTL_PUE_PUD = 0x1 << 7,
58 PAD_CTL_100K_PD = 0x0 << 5,
59 PAD_CTL_100K_PU = 0x1 << 5,
60 PAD_CTL_47K_PU = 0x2 << 5,
61 PAD_CTL_22K_PU = 0x3 << 5,
62 PAD_CTL_HYS_CMOS = 0x0 << 4,
63 PAD_CTL_HYS_SCHMITZ = 0x1 << 4,
64 PAD_CTL_ODE_CMOS = 0x0 << 3,
65 PAD_CTL_ODE_OpenDrain = 0x1 << 3,
66 PAD_CTL_DRV_NORMAL = 0x0 << 1,
67 PAD_CTL_DRV_HIGH = 0x1 << 1,
68 PAD_CTL_DRV_MAX = 0x2 << 1,
69 PAD_CTL_SRE_SLOW = 0x0 << 0,
70 PAD_CTL_SRE_FAST = 0x1 << 0
71};
72
73/*
74 * various IOMUX general purpose functions
75 */
76enum iomux_gp_func {
77 MUX_PGP_FIRI = 1 << 0,
78 MUX_DDR_MODE = 1 << 1,
79 MUX_PGP_CSPI_BB = 1 << 2,
80 MUX_PGP_ATA_1 = 1 << 3,
81 MUX_PGP_ATA_2 = 1 << 4,
82 MUX_PGP_ATA_3 = 1 << 5,
83 MUX_PGP_ATA_4 = 1 << 6,
84 MUX_PGP_ATA_5 = 1 << 7,
85 MUX_PGP_ATA_6 = 1 << 8,
86 MUX_PGP_ATA_7 = 1 << 9,
87 MUX_PGP_ATA_8 = 1 << 10,
88 MUX_PGP_UH2 = 1 << 11,
89 MUX_SDCTL_CSD0_SEL = 1 << 12,
90 MUX_SDCTL_CSD1_SEL = 1 << 13,
91 MUX_CSPI1_UART3 = 1 << 14,
92 MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
93 MUX_TAMPER_DETECT_EN = 1 << 16,
94 MUX_PGP_USB_4WIRE = 1 << 17,
95 MUX_PGB_USB_COMMON = 1 << 18,
96 MUX_SDHC_MEMSTICK1 = 1 << 19,
97 MUX_SDHC_MEMSTICK2 = 1 << 20,
98 MUX_PGP_SPLL_BYP = 1 << 21,
99 MUX_PGP_UPLL_BYP = 1 << 22,
100 MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
101 MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
102 MUX_CSPI3_UART5_SEL = 1 << 25,
103 MUX_PGP_ATA_9 = 1 << 26,
104 MUX_PGP_USB_SUSPEND = 1 << 27,
105 MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
106 MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
107 MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
108 MUX_CLKO_DDR_MODE = 1 << 31,
109};
110
111/*
112 * This function enables/disables the general purpose function for a particular
113 * signal.
114 */
115void iomux_config_gpr(enum iomux_gp_func , bool);
116
117/*
118 * set the mode for a IOMUX pin.
119 */
120int mxc_iomux_mode(unsigned int);
121
122/*
123 * This function enables/disables the general purpose function for a particular
124 * signal.
125 */
126void mxc_iomux_set_gpr(enum iomux_gp_func, bool);
127
128#define IOMUX_PADNUM_MASK 0x1ff
129#define IOMUX_GPIONUM_SHIFT 9
130#define IOMUX_GPIONUM_MASK (0xff << IOMUX_GPIONUM_SHIFT)
131#define IOMUX_MODE_SHIFT 17
132#define IOMUX_MODE_MASK (0xff << IOMUX_MODE_SHIFT)
133
134#define IOMUX_PIN(gpionum, padnum) \
135 (((gpionum << IOMUX_GPIONUM_SHIFT) & IOMUX_GPIONUM_MASK) | \
136 (padnum & IOMUX_PADNUM_MASK))
137
138#define IOMUX_MODE(pin, mode) (pin | mode << IOMUX_MODE_SHIFT)
139
140#define IOMUX_TO_GPIO(iomux_pin) \
141 ((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT)
142#define IOMUX_TO_IRQ(iomux_pin) \
143 (((iomux_pin & IOMUX_GPIONUM_MASK) >> IOMUX_GPIONUM_SHIFT) + \
144 MXC_GPIO_INT_BASE)
145
146/*
147 * This enumeration is constructed based on the Section
148 * "sw_pad_ctl & sw_mux_ctl details" of the MX31 IC Spec. Each enumerated
149 * value is constructed based on the rules described above.
150 */
151
152enum iomux_pins {
153 MX31_PIN_TTM_PAD = IOMUX_PIN(0xff, 0),
154 MX31_PIN_CSPI3_SPI_RDY = IOMUX_PIN(0xff, 1),
155 MX31_PIN_CSPI3_SCLK = IOMUX_PIN(0xff, 2),
156 MX31_PIN_CSPI3_MISO = IOMUX_PIN(0xff, 3),
157 MX31_PIN_CSPI3_MOSI = IOMUX_PIN(0xff, 4),
158 MX31_PIN_CLKSS = IOMUX_PIN(0xff, 5),
159 MX31_PIN_CE_CONTROL = IOMUX_PIN(0xff, 6),
160 MX31_PIN_ATA_RESET_B = IOMUX_PIN(95, 7),
161 MX31_PIN_ATA_DMACK = IOMUX_PIN(94, 8),
162 MX31_PIN_ATA_DIOW = IOMUX_PIN(93, 9),
163 MX31_PIN_ATA_DIOR = IOMUX_PIN(92, 10),
164 MX31_PIN_ATA_CS1 = IOMUX_PIN(91, 11),
165 MX31_PIN_ATA_CS0 = IOMUX_PIN(90, 12),
166 MX31_PIN_SD1_DATA3 = IOMUX_PIN(63, 13),
167 MX31_PIN_SD1_DATA2 = IOMUX_PIN(62, 14),
168 MX31_PIN_SD1_DATA1 = IOMUX_PIN(61, 15),
169 MX31_PIN_SD1_DATA0 = IOMUX_PIN(60, 16),
170 MX31_PIN_SD1_CLK = IOMUX_PIN(59, 17),
171 MX31_PIN_SD1_CMD = IOMUX_PIN(58, 18),
172 MX31_PIN_D3_SPL = IOMUX_PIN(0xff, 19),
173 MX31_PIN_D3_CLS = IOMUX_PIN(0xff, 20),
174 MX31_PIN_D3_REV = IOMUX_PIN(0xff, 21),
175 MX31_PIN_CONTRAST = IOMUX_PIN(0xff, 22),
176 MX31_PIN_VSYNC3 = IOMUX_PIN(0xff, 23),
177 MX31_PIN_READ = IOMUX_PIN(0xff, 24),
178 MX31_PIN_WRITE = IOMUX_PIN(0xff, 25),
179 MX31_PIN_PAR_RS = IOMUX_PIN(0xff, 26),
180 MX31_PIN_SER_RS = IOMUX_PIN(89, 27),
181 MX31_PIN_LCS1 = IOMUX_PIN(88, 28),
182 MX31_PIN_LCS0 = IOMUX_PIN(87, 29),
183 MX31_PIN_SD_D_CLK = IOMUX_PIN(86, 30),
184 MX31_PIN_SD_D_IO = IOMUX_PIN(85, 31),
185 MX31_PIN_SD_D_I = IOMUX_PIN(84, 32),
186 MX31_PIN_DRDY0 = IOMUX_PIN(0xff, 33),
187 MX31_PIN_FPSHIFT = IOMUX_PIN(0xff, 34),
188 MX31_PIN_HSYNC = IOMUX_PIN(0xff, 35),
189 MX31_PIN_VSYNC0 = IOMUX_PIN(0xff, 36),
190 MX31_PIN_LD17 = IOMUX_PIN(0xff, 37),
191 MX31_PIN_LD16 = IOMUX_PIN(0xff, 38),
192 MX31_PIN_LD15 = IOMUX_PIN(0xff, 39),
193 MX31_PIN_LD14 = IOMUX_PIN(0xff, 40),
194 MX31_PIN_LD13 = IOMUX_PIN(0xff, 41),
195 MX31_PIN_LD12 = IOMUX_PIN(0xff, 42),
196 MX31_PIN_LD11 = IOMUX_PIN(0xff, 43),
197 MX31_PIN_LD10 = IOMUX_PIN(0xff, 44),
198 MX31_PIN_LD9 = IOMUX_PIN(0xff, 45),
199 MX31_PIN_LD8 = IOMUX_PIN(0xff, 46),
200 MX31_PIN_LD7 = IOMUX_PIN(0xff, 47),
201 MX31_PIN_LD6 = IOMUX_PIN(0xff, 48),
202 MX31_PIN_LD5 = IOMUX_PIN(0xff, 49),
203 MX31_PIN_LD4 = IOMUX_PIN(0xff, 50),
204 MX31_PIN_LD3 = IOMUX_PIN(0xff, 51),
205 MX31_PIN_LD2 = IOMUX_PIN(0xff, 52),
206 MX31_PIN_LD1 = IOMUX_PIN(0xff, 53),
207 MX31_PIN_LD0 = IOMUX_PIN(0xff, 54),
208 MX31_PIN_USBH2_DATA1 = IOMUX_PIN(0xff, 55),
209 MX31_PIN_USBH2_DATA0 = IOMUX_PIN(0xff, 56),
210 MX31_PIN_USBH2_NXT = IOMUX_PIN(0xff, 57),
211 MX31_PIN_USBH2_STP = IOMUX_PIN(0xff, 58),
212 MX31_PIN_USBH2_DIR = IOMUX_PIN(0xff, 59),
213 MX31_PIN_USBH2_CLK = IOMUX_PIN(0xff, 60),
214 MX31_PIN_USBOTG_DATA7 = IOMUX_PIN(0xff, 61),
215 MX31_PIN_USBOTG_DATA6 = IOMUX_PIN(0xff, 62),
216 MX31_PIN_USBOTG_DATA5 = IOMUX_PIN(0xff, 63),
217 MX31_PIN_USBOTG_DATA4 = IOMUX_PIN(0xff, 64),
218 MX31_PIN_USBOTG_DATA3 = IOMUX_PIN(0xff, 65),
219 MX31_PIN_USBOTG_DATA2 = IOMUX_PIN(0xff, 66),
220 MX31_PIN_USBOTG_DATA1 = IOMUX_PIN(0xff, 67),
221 MX31_PIN_USBOTG_DATA0 = IOMUX_PIN(0xff, 68),
222 MX31_PIN_USBOTG_NXT = IOMUX_PIN(0xff, 69),
223 MX31_PIN_USBOTG_STP = IOMUX_PIN(0xff, 70),
224 MX31_PIN_USBOTG_DIR = IOMUX_PIN(0xff, 71),
225 MX31_PIN_USBOTG_CLK = IOMUX_PIN(0xff, 72),
226 MX31_PIN_USB_BYP = IOMUX_PIN(31, 73),
227 MX31_PIN_USB_OC = IOMUX_PIN(30, 74),
228 MX31_PIN_USB_PWR = IOMUX_PIN(29, 75),
229 MX31_PIN_SJC_MOD = IOMUX_PIN(0xff, 76),
230 MX31_PIN_DE_B = IOMUX_PIN(0xff, 77),
231 MX31_PIN_TRSTB = IOMUX_PIN(0xff, 78),
232 MX31_PIN_TDO = IOMUX_PIN(0xff, 79),
233 MX31_PIN_TDI = IOMUX_PIN(0xff, 80),
234 MX31_PIN_TMS = IOMUX_PIN(0xff, 81),
235 MX31_PIN_TCK = IOMUX_PIN(0xff, 82),
236 MX31_PIN_RTCK = IOMUX_PIN(0xff, 83),
237 MX31_PIN_KEY_COL7 = IOMUX_PIN(57, 84),
238 MX31_PIN_KEY_COL6 = IOMUX_PIN(56, 85),
239 MX31_PIN_KEY_COL5 = IOMUX_PIN(55, 86),
240 MX31_PIN_KEY_COL4 = IOMUX_PIN(54, 87),
241 MX31_PIN_KEY_COL3 = IOMUX_PIN(0xff, 88),
242 MX31_PIN_KEY_COL2 = IOMUX_PIN(0xff, 89),
243 MX31_PIN_KEY_COL1 = IOMUX_PIN(0xff, 90),
244 MX31_PIN_KEY_COL0 = IOMUX_PIN(0xff, 91),
245 MX31_PIN_KEY_ROW7 = IOMUX_PIN(53, 92),
246 MX31_PIN_KEY_ROW6 = IOMUX_PIN(52, 93),
247 MX31_PIN_KEY_ROW5 = IOMUX_PIN(51, 94),
248 MX31_PIN_KEY_ROW4 = IOMUX_PIN(50, 95),
249 MX31_PIN_KEY_ROW3 = IOMUX_PIN(0xff, 96),
250 MX31_PIN_KEY_ROW2 = IOMUX_PIN(0xff, 97),
251 MX31_PIN_KEY_ROW1 = IOMUX_PIN(0xff, 98),
252 MX31_PIN_KEY_ROW0 = IOMUX_PIN(0xff, 99),
253 MX31_PIN_BATT_LINE = IOMUX_PIN(49, 100),
254 MX31_PIN_CTS2 = IOMUX_PIN(0xff, 101),
255 MX31_PIN_RTS2 = IOMUX_PIN(0xff, 102),
256 MX31_PIN_TXD2 = IOMUX_PIN(28, 103),
257 MX31_PIN_RXD2 = IOMUX_PIN(27, 104),
258 MX31_PIN_DTR_DCE2 = IOMUX_PIN(48, 105),
259 MX31_PIN_DCD_DTE1 = IOMUX_PIN(47, 106),
260 MX31_PIN_RI_DTE1 = IOMUX_PIN(46, 107),
261 MX31_PIN_DSR_DTE1 = IOMUX_PIN(45, 108),
262 MX31_PIN_DTR_DTE1 = IOMUX_PIN(44, 109),
263 MX31_PIN_DCD_DCE1 = IOMUX_PIN(43, 110),
264 MX31_PIN_RI_DCE1 = IOMUX_PIN(42, 111),
265 MX31_PIN_DSR_DCE1 = IOMUX_PIN(41, 112),
266 MX31_PIN_DTR_DCE1 = IOMUX_PIN(40, 113),
267 MX31_PIN_CTS1 = IOMUX_PIN(39, 114),
268 MX31_PIN_RTS1 = IOMUX_PIN(38, 115),
269 MX31_PIN_TXD1 = IOMUX_PIN(37, 116),
270 MX31_PIN_RXD1 = IOMUX_PIN(36, 117),
271 MX31_PIN_CSPI2_SPI_RDY = IOMUX_PIN(0xff, 118),
272 MX31_PIN_CSPI2_SCLK = IOMUX_PIN(0xff, 119),
273 MX31_PIN_CSPI2_SS2 = IOMUX_PIN(0xff, 120),
274 MX31_PIN_CSPI2_SS1 = IOMUX_PIN(0xff, 121),
275 MX31_PIN_CSPI2_SS0 = IOMUX_PIN(0xff, 122),
276 MX31_PIN_CSPI2_MISO = IOMUX_PIN(0xff, 123),
277 MX31_PIN_CSPI2_MOSI = IOMUX_PIN(0xff, 124),
278 MX31_PIN_CSPI1_SPI_RDY = IOMUX_PIN(0xff, 125),
279 MX31_PIN_CSPI1_SCLK = IOMUX_PIN(0xff, 126),
280 MX31_PIN_CSPI1_SS2 = IOMUX_PIN(0xff, 127),
281 MX31_PIN_CSPI1_SS1 = IOMUX_PIN(0xff, 128),
282 MX31_PIN_CSPI1_SS0 = IOMUX_PIN(0xff, 129),
283 MX31_PIN_CSPI1_MISO = IOMUX_PIN(0xff, 130),
284 MX31_PIN_CSPI1_MOSI = IOMUX_PIN(0xff, 131),
285 MX31_PIN_SFS6 = IOMUX_PIN(26, 132),
286 MX31_PIN_SCK6 = IOMUX_PIN(25, 133),
287 MX31_PIN_SRXD6 = IOMUX_PIN(24, 134),
288 MX31_PIN_STXD6 = IOMUX_PIN(23, 135),
289 MX31_PIN_SFS5 = IOMUX_PIN(0xff, 136),
290 MX31_PIN_SCK5 = IOMUX_PIN(0xff, 137),
291 MX31_PIN_SRXD5 = IOMUX_PIN(22, 138),
292 MX31_PIN_STXD5 = IOMUX_PIN(21, 139),
293 MX31_PIN_SFS4 = IOMUX_PIN(0xff, 140),
294 MX31_PIN_SCK4 = IOMUX_PIN(0xff, 141),
295 MX31_PIN_SRXD4 = IOMUX_PIN(20, 142),
296 MX31_PIN_STXD4 = IOMUX_PIN(19, 143),
297 MX31_PIN_SFS3 = IOMUX_PIN(0xff, 144),
298 MX31_PIN_SCK3 = IOMUX_PIN(0xff, 145),
299 MX31_PIN_SRXD3 = IOMUX_PIN(18, 146),
300 MX31_PIN_STXD3 = IOMUX_PIN(17, 147),
301 MX31_PIN_I2C_DAT = IOMUX_PIN(0xff, 148),
302 MX31_PIN_I2C_CLK = IOMUX_PIN(0xff, 149),
303 MX31_PIN_CSI_PIXCLK = IOMUX_PIN(83, 150),
304 MX31_PIN_CSI_HSYNC = IOMUX_PIN(82, 151),
305 MX31_PIN_CSI_VSYNC = IOMUX_PIN(81, 152),
306 MX31_PIN_CSI_MCLK = IOMUX_PIN(80, 153),
307 MX31_PIN_CSI_D15 = IOMUX_PIN(79, 154),
308 MX31_PIN_CSI_D14 = IOMUX_PIN(78, 155),
309 MX31_PIN_CSI_D13 = IOMUX_PIN(77, 156),
310 MX31_PIN_CSI_D12 = IOMUX_PIN(76, 157),
311 MX31_PIN_CSI_D11 = IOMUX_PIN(75, 158),
312 MX31_PIN_CSI_D10 = IOMUX_PIN(74, 159),
313 MX31_PIN_CSI_D9 = IOMUX_PIN(73, 160),
314 MX31_PIN_CSI_D8 = IOMUX_PIN(72, 161),
315 MX31_PIN_CSI_D7 = IOMUX_PIN(71, 162),
316 MX31_PIN_CSI_D6 = IOMUX_PIN(70, 163),
317 MX31_PIN_CSI_D5 = IOMUX_PIN(69, 164),
318 MX31_PIN_CSI_D4 = IOMUX_PIN(68, 165),
319 MX31_PIN_M_GRANT = IOMUX_PIN(0xff, 166),
320 MX31_PIN_M_REQUEST = IOMUX_PIN(0xff, 167),
321 MX31_PIN_PC_POE = IOMUX_PIN(0xff, 168),
322 MX31_PIN_PC_RW_B = IOMUX_PIN(0xff, 169),
323 MX31_PIN_IOIS16 = IOMUX_PIN(0xff, 170),
324 MX31_PIN_PC_RST = IOMUX_PIN(0xff, 171),
325 MX31_PIN_PC_BVD2 = IOMUX_PIN(0xff, 172),
326 MX31_PIN_PC_BVD1 = IOMUX_PIN(0xff, 173),
327 MX31_PIN_PC_VS2 = IOMUX_PIN(0xff, 174),
328 MX31_PIN_PC_VS1 = IOMUX_PIN(0xff, 175),
329 MX31_PIN_PC_PWRON = IOMUX_PIN(0xff, 176),
330 MX31_PIN_PC_READY = IOMUX_PIN(0xff, 177),
331 MX31_PIN_PC_WAIT_B = IOMUX_PIN(0xff, 178),
332 MX31_PIN_PC_CD2_B = IOMUX_PIN(0xff, 179),
333 MX31_PIN_PC_CD1_B = IOMUX_PIN(0xff, 180),
334 MX31_PIN_D0 = IOMUX_PIN(0xff, 181),
335 MX31_PIN_D1 = IOMUX_PIN(0xff, 182),
336 MX31_PIN_D2 = IOMUX_PIN(0xff, 183),
337 MX31_PIN_D3 = IOMUX_PIN(0xff, 184),
338 MX31_PIN_D4 = IOMUX_PIN(0xff, 185),
339 MX31_PIN_D5 = IOMUX_PIN(0xff, 186),
340 MX31_PIN_D6 = IOMUX_PIN(0xff, 187),
341 MX31_PIN_D7 = IOMUX_PIN(0xff, 188),
342 MX31_PIN_D8 = IOMUX_PIN(0xff, 189),
343 MX31_PIN_D9 = IOMUX_PIN(0xff, 190),
344 MX31_PIN_D10 = IOMUX_PIN(0xff, 191),
345 MX31_PIN_D11 = IOMUX_PIN(0xff, 192),
346 MX31_PIN_D12 = IOMUX_PIN(0xff, 193),
347 MX31_PIN_D13 = IOMUX_PIN(0xff, 194),
348 MX31_PIN_D14 = IOMUX_PIN(0xff, 195),
349 MX31_PIN_D15 = IOMUX_PIN(0xff, 196),
350 MX31_PIN_NFRB = IOMUX_PIN(16, 197),
351 MX31_PIN_NFCE_B = IOMUX_PIN(15, 198),
352 MX31_PIN_NFWP_B = IOMUX_PIN(14, 199),
353 MX31_PIN_NFCLE = IOMUX_PIN(13, 200),
354 MX31_PIN_NFALE = IOMUX_PIN(12, 201),
355 MX31_PIN_NFRE_B = IOMUX_PIN(11, 202),
356 MX31_PIN_NFWE_B = IOMUX_PIN(10, 203),
357 MX31_PIN_SDQS3 = IOMUX_PIN(0xff, 204),
358 MX31_PIN_SDQS2 = IOMUX_PIN(0xff, 205),
359 MX31_PIN_SDQS1 = IOMUX_PIN(0xff, 206),
360 MX31_PIN_SDQS0 = IOMUX_PIN(0xff, 207),
361 MX31_PIN_SDCLK_B = IOMUX_PIN(0xff, 208),
362 MX31_PIN_SDCLK = IOMUX_PIN(0xff, 209),
363 MX31_PIN_SDCKE1 = IOMUX_PIN(0xff, 210),
364 MX31_PIN_SDCKE0 = IOMUX_PIN(0xff, 211),
365 MX31_PIN_SDWE = IOMUX_PIN(0xff, 212),
366 MX31_PIN_CAS = IOMUX_PIN(0xff, 213),
367 MX31_PIN_RAS = IOMUX_PIN(0xff, 214),
368 MX31_PIN_RW = IOMUX_PIN(0xff, 215),
369 MX31_PIN_BCLK = IOMUX_PIN(0xff, 216),
370 MX31_PIN_LBA = IOMUX_PIN(0xff, 217),
371 MX31_PIN_ECB = IOMUX_PIN(0xff, 218),
372 MX31_PIN_CS5 = IOMUX_PIN(0xff, 219),
373 MX31_PIN_CS4 = IOMUX_PIN(0xff, 220),
374 MX31_PIN_CS3 = IOMUX_PIN(0xff, 221),
375 MX31_PIN_CS2 = IOMUX_PIN(0xff, 222),
376 MX31_PIN_CS1 = IOMUX_PIN(0xff, 223),
377 MX31_PIN_CS0 = IOMUX_PIN(0xff, 224),
378 MX31_PIN_OE = IOMUX_PIN(0xff, 225),
379 MX31_PIN_EB1 = IOMUX_PIN(0xff, 226),
380 MX31_PIN_EB0 = IOMUX_PIN(0xff, 227),
381 MX31_PIN_DQM3 = IOMUX_PIN(0xff, 228),
382 MX31_PIN_DQM2 = IOMUX_PIN(0xff, 229),
383 MX31_PIN_DQM1 = IOMUX_PIN(0xff, 230),
384 MX31_PIN_DQM0 = IOMUX_PIN(0xff, 231),
385 MX31_PIN_SD31 = IOMUX_PIN(0xff, 232),
386 MX31_PIN_SD30 = IOMUX_PIN(0xff, 233),
387 MX31_PIN_SD29 = IOMUX_PIN(0xff, 234),
388 MX31_PIN_SD28 = IOMUX_PIN(0xff, 235),
389 MX31_PIN_SD27 = IOMUX_PIN(0xff, 236),
390 MX31_PIN_SD26 = IOMUX_PIN(0xff, 237),
391 MX31_PIN_SD25 = IOMUX_PIN(0xff, 238),
392 MX31_PIN_SD24 = IOMUX_PIN(0xff, 239),
393 MX31_PIN_SD23 = IOMUX_PIN(0xff, 240),
394 MX31_PIN_SD22 = IOMUX_PIN(0xff, 241),
395 MX31_PIN_SD21 = IOMUX_PIN(0xff, 242),
396 MX31_PIN_SD20 = IOMUX_PIN(0xff, 243),
397 MX31_PIN_SD19 = IOMUX_PIN(0xff, 244),
398 MX31_PIN_SD18 = IOMUX_PIN(0xff, 245),
399 MX31_PIN_SD17 = IOMUX_PIN(0xff, 246),
400 MX31_PIN_SD16 = IOMUX_PIN(0xff, 247),
401 MX31_PIN_SD15 = IOMUX_PIN(0xff, 248),
402 MX31_PIN_SD14 = IOMUX_PIN(0xff, 249),
403 MX31_PIN_SD13 = IOMUX_PIN(0xff, 250),
404 MX31_PIN_SD12 = IOMUX_PIN(0xff, 251),
405 MX31_PIN_SD11 = IOMUX_PIN(0xff, 252),
406 MX31_PIN_SD10 = IOMUX_PIN(0xff, 253),
407 MX31_PIN_SD9 = IOMUX_PIN(0xff, 254),
408 MX31_PIN_SD8 = IOMUX_PIN(0xff, 255),
409 MX31_PIN_SD7 = IOMUX_PIN(0xff, 256),
410 MX31_PIN_SD6 = IOMUX_PIN(0xff, 257),
411 MX31_PIN_SD5 = IOMUX_PIN(0xff, 258),
412 MX31_PIN_SD4 = IOMUX_PIN(0xff, 259),
413 MX31_PIN_SD3 = IOMUX_PIN(0xff, 260),
414 MX31_PIN_SD2 = IOMUX_PIN(0xff, 261),
415 MX31_PIN_SD1 = IOMUX_PIN(0xff, 262),
416 MX31_PIN_SD0 = IOMUX_PIN(0xff, 263),
417 MX31_PIN_SDBA0 = IOMUX_PIN(0xff, 264),
418 MX31_PIN_SDBA1 = IOMUX_PIN(0xff, 265),
419 MX31_PIN_A25 = IOMUX_PIN(0xff, 266),
420 MX31_PIN_A24 = IOMUX_PIN(0xff, 267),
421 MX31_PIN_A23 = IOMUX_PIN(0xff, 268),
422 MX31_PIN_A22 = IOMUX_PIN(0xff, 269),
423 MX31_PIN_A21 = IOMUX_PIN(0xff, 270),
424 MX31_PIN_A20 = IOMUX_PIN(0xff, 271),
425 MX31_PIN_A19 = IOMUX_PIN(0xff, 272),
426 MX31_PIN_A18 = IOMUX_PIN(0xff, 273),
427 MX31_PIN_A17 = IOMUX_PIN(0xff, 274),
428 MX31_PIN_A16 = IOMUX_PIN(0xff, 275),
429 MX31_PIN_A14 = IOMUX_PIN(0xff, 276),
430 MX31_PIN_A15 = IOMUX_PIN(0xff, 277),
431 MX31_PIN_A13 = IOMUX_PIN(0xff, 278),
432 MX31_PIN_A12 = IOMUX_PIN(0xff, 279),
433 MX31_PIN_A11 = IOMUX_PIN(0xff, 280),
434 MX31_PIN_MA10 = IOMUX_PIN(0xff, 281),
435 MX31_PIN_A10 = IOMUX_PIN(0xff, 282),
436 MX31_PIN_A9 = IOMUX_PIN(0xff, 283),
437 MX31_PIN_A8 = IOMUX_PIN(0xff, 284),
438 MX31_PIN_A7 = IOMUX_PIN(0xff, 285),
439 MX31_PIN_A6 = IOMUX_PIN(0xff, 286),
440 MX31_PIN_A5 = IOMUX_PIN(0xff, 287),
441 MX31_PIN_A4 = IOMUX_PIN(0xff, 288),
442 MX31_PIN_A3 = IOMUX_PIN(0xff, 289),
443 MX31_PIN_A2 = IOMUX_PIN(0xff, 290),
444 MX31_PIN_A1 = IOMUX_PIN(0xff, 291),
445 MX31_PIN_A0 = IOMUX_PIN(0xff, 292),
446 MX31_PIN_VPG1 = IOMUX_PIN(0xff, 293),
447 MX31_PIN_VPG0 = IOMUX_PIN(0xff, 294),
448 MX31_PIN_DVFS1 = IOMUX_PIN(0xff, 295),
449 MX31_PIN_DVFS0 = IOMUX_PIN(0xff, 296),
450 MX31_PIN_VSTBY = IOMUX_PIN(0xff, 297),
451 MX31_PIN_POWER_FAIL = IOMUX_PIN(0xff, 298),
452 MX31_PIN_CKIL = IOMUX_PIN(0xff, 299),
453 MX31_PIN_BOOT_MODE4 = IOMUX_PIN(0xff, 300),
454 MX31_PIN_BOOT_MODE3 = IOMUX_PIN(0xff, 301),
455 MX31_PIN_BOOT_MODE2 = IOMUX_PIN(0xff, 302),
456 MX31_PIN_BOOT_MODE1 = IOMUX_PIN(0xff, 303),
457 MX31_PIN_BOOT_MODE0 = IOMUX_PIN(0xff, 304),
458 MX31_PIN_CLKO = IOMUX_PIN(0xff, 305),
459 MX31_PIN_POR_B = IOMUX_PIN(0xff, 306),
460 MX31_PIN_RESET_IN_B = IOMUX_PIN(0xff, 307),
461 MX31_PIN_CKIH = IOMUX_PIN(0xff, 308),
462 MX31_PIN_SIMPD0 = IOMUX_PIN(35, 309),
463 MX31_PIN_SRX0 = IOMUX_PIN(34, 310),
464 MX31_PIN_STX0 = IOMUX_PIN(33, 311),
465 MX31_PIN_SVEN0 = IOMUX_PIN(32, 312),
466 MX31_PIN_SRST0 = IOMUX_PIN(67, 313),
467 MX31_PIN_SCLK0 = IOMUX_PIN(66, 314),
468 MX31_PIN_GPIO3_1 = IOMUX_PIN(65, 315),
469 MX31_PIN_GPIO3_0 = IOMUX_PIN(64, 316),
470 MX31_PIN_GPIO1_6 = IOMUX_PIN( 6, 317),
471 MX31_PIN_GPIO1_5 = IOMUX_PIN( 5, 318),
472 MX31_PIN_GPIO1_4 = IOMUX_PIN( 4, 319),
473 MX31_PIN_GPIO1_3 = IOMUX_PIN( 3, 320),
474 MX31_PIN_GPIO1_2 = IOMUX_PIN( 2, 321),
475 MX31_PIN_GPIO1_1 = IOMUX_PIN( 1, 322),
476 MX31_PIN_GPIO1_0 = IOMUX_PIN( 0, 323),
477 MX31_PIN_PWMO = IOMUX_PIN( 9, 324),
478 MX31_PIN_WATCHDOG_RST = IOMUX_PIN(0xff, 325),
479 MX31_PIN_COMPARE = IOMUX_PIN( 8, 326),
480 MX31_PIN_CAPTURE = IOMUX_PIN( 7, 327),
481};
482
483/*
484 * Convenience values for use with mxc_iomux_mode()
485 *
486 * Format here is MX31_PIN_(pin name)__(function)
487 */
488#define MX31_PIN_CSPI3_MOSI__RXD3 IOMUX_MODE(MX31_PIN_CSPI3_MOSI, IOMUX_CONFIG_ALT1)
489#define MX31_PIN_CSPI3_MISO__TXD3 IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_ALT1)
490#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
491#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
492#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
493#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
494
495/*
496 * This function configures the pad value for a IOMUX pin.
497 */
498void mxc_iomux_set_pad(enum iomux_pins, u32);
499
500#endif
501
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
index b2c5205e1962..f416130718cf 100644
--- a/include/asm-arm/arch-mxc/irqs.h
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -13,17 +13,4 @@
13 13
14#include <asm/hardware.h> 14#include <asm/hardware.h>
15 15
16#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
17
18#define MXC_IRQ_TO_GPIO(irq) ((irq) - MXC_GPIO_INT_BASE)
19#define MXC_GPIO_TO_IRQ(x) (MXC_GPIO_INT_BASE + x)
20
21/* Number of normal interrupts */
22#define NR_IRQS (MXC_MAX_INT_LINES + \
23 MXC_MAX_GPIO_LINES + \
24 MXC_MAX_VIRTUAL_INTS)
25
26/* Number of fast interrupts */
27#define NR_FIQS MXC_MAX_INTS
28
29#endif /* __ASM_ARCH_MXC_IRQS_H__ */ 16#endif /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/mx27.h b/include/asm-arm/arch-mxc/mx27.h
new file mode 100644
index 000000000000..212ecc246626
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx27.h
@@ -0,0 +1,302 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __ASM_ARCH_MXC_MX27_H__
21#define __ASM_ARCH_MXC_MX27_H__
22
23#ifndef __ASM_ARCH_MXC_HARDWARE_H__
24#error "Do not include directly."
25#endif
26
27/* IRAM */
28#define IRAM_BASE_ADDR 0xFFFF4C00 /* internal ram */
29
30/* Register offests */
31#define AIPI_BASE_ADDR 0x10000000
32#define AIPI_BASE_ADDR_VIRT 0xF4000000
33#define AIPI_SIZE SZ_1M
34
35#define DMA_BASE_ADDR (AIPI_BASE_ADDR + 0x01000)
36#define WDOG_BASE_ADDR (AIPI_BASE_ADDR + 0x02000)
37#define GPT1_BASE_ADDR (AIPI_BASE_ADDR + 0x03000)
38#define GPT2_BASE_ADDR (AIPI_BASE_ADDR + 0x04000)
39#define GPT3_BASE_ADDR (AIPI_BASE_ADDR + 0x05000)
40#define PWM_BASE_ADDR (AIPI_BASE_ADDR + 0x06000)
41#define RTC_BASE_ADDR (AIPI_BASE_ADDR + 0x07000)
42#define KPP_BASE_ADDR (AIPI_BASE_ADDR + 0x08000)
43#define OWIRE_BASE_ADDR (AIPI_BASE_ADDR + 0x09000)
44#define UART1_BASE_ADDR (AIPI_BASE_ADDR + 0x0A000)
45#define UART2_BASE_ADDR (AIPI_BASE_ADDR + 0x0B000)
46#define UART3_BASE_ADDR (AIPI_BASE_ADDR + 0x0C000)
47#define UART4_BASE_ADDR (AIPI_BASE_ADDR + 0x0D000)
48#define CSPI1_BASE_ADDR (AIPI_BASE_ADDR + 0x0E000)
49#define CSPI2_BASE_ADDR (AIPI_BASE_ADDR + 0x0F000)
50#define SSI1_BASE_ADDR (AIPI_BASE_ADDR + 0x10000)
51#define SSI2_BASE_ADDR (AIPI_BASE_ADDR + 0x11000)
52#define I2C_BASE_ADDR (AIPI_BASE_ADDR + 0x12000)
53#define SDHC1_BASE_ADDR (AIPI_BASE_ADDR + 0x13000)
54#define SDHC2_BASE_ADDR (AIPI_BASE_ADDR + 0x14000)
55#define GPIO_BASE_ADDR (AIPI_BASE_ADDR + 0x15000)
56#define AUDMUX_BASE_ADDR (AIPI_BASE_ADDR + 0x16000)
57
58#define CSPI3_BASE_ADDR (AIPI_BASE_ADDR + 0x17000)
59#define MSHC_BASE_ADDR (AIPI_BASE_ADDR + 0x18000)
60#define GPT5_BASE_ADDR (AIPI_BASE_ADDR + 0x19000)
61#define GPT4_BASE_ADDR (AIPI_BASE_ADDR + 0x1A000)
62#define UART5_BASE_ADDR (AIPI_BASE_ADDR + 0x1B000)
63#define UART6_BASE_ADDR (AIPI_BASE_ADDR + 0x1C000)
64#define I2C2_BASE_ADDR (AIPI_BASE_ADDR + 0x1D000)
65#define SDHC3_BASE_ADDR (AIPI_BASE_ADDR + 0x1E000)
66#define GPT6_BASE_ADDR (AIPI_BASE_ADDR + 0x1F000)
67
68#define LCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x21000)
69#define SLCDC_BASE_ADDR (AIPI_BASE_ADDR + 0x22000)
70#define VPU_BASE_ADDR (AIPI_BASE_ADDR + 0x23000)
71#define USBOTG_BASE_ADDR (AIPI_BASE_ADDR + 0x24000)
72/* for mx27*/
73#define OTG_BASE_ADDR USBOTG_BASE_ADDR
74#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
75#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
76#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
77#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
78#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)
79
80#define RTIC_BASE_ADDR (AIPI_BASE_ADDR + 0x2A000)
81#define FEC_BASE_ADDR (AIPI_BASE_ADDR + 0x2B000)
82#define SCC_BASE_ADDR (AIPI_BASE_ADDR + 0x2C000)
83#define ETB_BASE_ADDR (AIPI_BASE_ADDR + 0x3B000)
84#define ETB_RAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3C000)
85
86#define JAM_BASE_ADDR (AIPI_BASE_ADDR + 0x3E000)
87#define MAX_BASE_ADDR (AIPI_BASE_ADDR + 0x3F000)
88
89/* ROMP and AVIC */
90#define ROMP_BASE_ADDR 0x10041000
91
92#define AVIC_BASE_ADDR 0x10040000
93
94#define SAHB1_BASE_ADDR 0x80000000
95#define SAHB1_BASE_ADDR_VIRT 0xF4100000
96#define SAHB1_SIZE SZ_1M
97
98#define CSI_BASE_ADDR (SAHB1_BASE_ADDR + 0x0000)
99#define ATA_BASE_ADDR (SAHB1_BASE_ADDR + 0x1000)
100
101/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
102#define X_MEMC_BASE_ADDR 0xD8000000
103#define X_MEMC_BASE_ADDR_VIRT 0xF4200000
104#define X_MEMC_SIZE SZ_1M
105
106#define NFC_BASE_ADDR (X_MEMC_BASE_ADDR)
107#define SDRAMC_BASE_ADDR (X_MEMC_BASE_ADDR + 0x1000)
108#define WEIM_BASE_ADDR (X_MEMC_BASE_ADDR + 0x2000)
109#define M3IF_BASE_ADDR (X_MEMC_BASE_ADDR + 0x3000)
110#define PCMCIA_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
111
112/* Memory regions and CS */
113#define SDRAM_BASE_ADDR 0xA0000000
114#define CSD1_BASE_ADDR 0xB0000000
115
116#define CS0_BASE_ADDR 0xC0000000
117#define CS1_BASE_ADDR 0xC8000000
118#define CS2_BASE_ADDR 0xD0000000
119#define CS3_BASE_ADDR 0xD2000000
120#define CS4_BASE_ADDR 0xD4000000
121#define CS5_BASE_ADDR 0xD6000000
122#define PCMCIA_MEM_BASE_ADDR 0xDC000000
123
124/*
125 * This macro defines the physical to virtual address mapping for all the
126 * peripheral modules. It is used by passing in the physical address as x
127 * and returning the virtual address. If the physical address is not mapped,
128 * it returns 0xDEADBEEF
129 */
130#define IO_ADDRESS(x) \
131 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
132 AIPI_IO_ADDRESS(x) : \
133 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
134 SAHB1_IO_ADDRESS(x) : \
135 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
136 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
137
138/* define the address mapping macros: in physical address order */
139#define AIPI_IO_ADDRESS(x) \
140 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
141
142#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
143
144#define SAHB1_IO_ADDRESS(x) \
145 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
146
147#define CS4_IO_ADDRESS(x) \
148 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
149
150#define X_MEMC_IO_ADDRESS(x) \
151 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
152
153#define PCMCIA_IO_ADDRESS(x) \
154 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
155
156/* fixed interrput numbers */
157#define MXC_INT_CCM 63
158#define MXC_INT_IIM 62
159#define MXC_INT_LCDC 61
160#define MXC_INT_SLCDC 60
161#define MXC_INT_SAHARA 59
162#define MXC_INT_SCC_SCM 58
163#define MXC_INT_SCC_SMN 57
164#define MXC_INT_USB3 56
165#define MXC_INT_USB2 55
166#define MXC_INT_USB1 54
167#define MXC_INT_VPU 53
168#define MXC_INT_EMMAPP 52
169#define MXC_INT_EMMAPRP 51
170#define MXC_INT_FEC 50
171#define MXC_INT_UART5 49
172#define MXC_INT_UART6 48
173#define MXC_INT_DMACH15 47
174#define MXC_INT_DMACH14 46
175#define MXC_INT_DMACH13 45
176#define MXC_INT_DMACH12 44
177#define MXC_INT_DMACH11 43
178#define MXC_INT_DMACH10 42
179#define MXC_INT_DMACH9 41
180#define MXC_INT_DMACH8 40
181#define MXC_INT_DMACH7 39
182#define MXC_INT_DMACH6 38
183#define MXC_INT_DMACH5 37
184#define MXC_INT_DMACH4 36
185#define MXC_INT_DMACH3 35
186#define MXC_INT_DMACH2 34
187#define MXC_INT_DMACH1 33
188#define MXC_INT_DMACH0 32
189#define MXC_INT_CSI 31
190#define MXC_INT_ATA 30
191#define MXC_INT_NANDFC 29
192#define MXC_INT_PCMCIA 28
193#define MXC_INT_WDOG 27
194#define MXC_INT_GPT1 26
195#define MXC_INT_GPT2 25
196#define MXC_INT_GPT3 24
197#define MXC_INT_GPT INT_GPT1
198#define MXC_INT_PWM 23
199#define MXC_INT_RTC 22
200#define MXC_INT_KPP 21
201#define MXC_INT_UART1 20
202#define MXC_INT_UART2 19
203#define MXC_INT_UART3 18
204#define MXC_INT_UART4 17
205#define MXC_INT_CSPI1 16
206#define MXC_INT_CSPI2 15
207#define MXC_INT_SSI1 14
208#define MXC_INT_SSI2 13
209#define MXC_INT_I2C 12
210#define MXC_INT_SDHC1 11
211#define MXC_INT_SDHC2 10
212#define MXC_INT_SDHC3 9
213#define MXC_INT_GPIO 8
214#define MXC_INT_SDHC 7
215#define MXC_INT_CSPI3 6
216#define MXC_INT_RTIC 5
217#define MXC_INT_GPT4 4
218#define MXC_INT_GPT5 3
219#define MXC_INT_GPT6 2
220#define MXC_INT_I2C2 1
221
222/* fixed DMA request numbers */
223#define DMA_REQ_NFC 37
224#define DMA_REQ_SDHC3 36
225#define DMA_REQ_UART6_RX 35
226#define DMA_REQ_UART6_TX 34
227#define DMA_REQ_UART5_RX 33
228#define DMA_REQ_UART5_TX 32
229#define DMA_REQ_CSI_RX 31
230#define DMA_REQ_CSI_STAT 30
231#define DMA_REQ_ATA_RCV 29
232#define DMA_REQ_ATA_TX 28
233#define DMA_REQ_UART1_TX 27
234#define DMA_REQ_UART1_RX 26
235#define DMA_REQ_UART2_TX 25
236#define DMA_REQ_UART2_RX 24
237#define DMA_REQ_UART3_TX 23
238#define DMA_REQ_UART3_RX 22
239#define DMA_REQ_UART4_TX 21
240#define DMA_REQ_UART4_RX 20
241#define DMA_REQ_CSPI1_TX 19
242#define DMA_REQ_CSPI1_RX 18
243#define DMA_REQ_CSPI2_TX 17
244#define DMA_REQ_CSPI2_RX 16
245#define DMA_REQ_SSI1_TX1 15
246#define DMA_REQ_SSI1_RX1 14
247#define DMA_REQ_SSI1_TX0 13
248#define DMA_REQ_SSI1_RX0 12
249#define DMA_REQ_SSI2_TX1 11
250#define DMA_REQ_SSI2_RX1 10
251#define DMA_REQ_SSI2_TX0 9
252#define DMA_REQ_SSI2_RX0 8
253#define DMA_REQ_SDHC1 7
254#define DMA_REQ_SDHC2 6
255#define DMA_REQ_MSHC 4
256#define DMA_REQ_EXT 3
257#define DMA_REQ_CSPI3_TX 2
258#define DMA_REQ_CSPI3_RX 1
259
260/* silicon revisions specific to i.MX27 */
261#define CHIP_REV_1_0 0x00
262#define CHIP_REV_2_0 0x01
263
264#ifndef __ASSEMBLY__
265extern int mx27_revision(void);
266#endif
267
268/* gpio and gpio based interrupt handling */
269#define GPIO_DR 0x1C
270#define GPIO_GDIR 0x00
271#define GPIO_PSR 0x24
272#define GPIO_ICR1 0x28
273#define GPIO_ICR2 0x2C
274#define GPIO_IMR 0x30
275#define GPIO_ISR 0x34
276#define GPIO_INT_LOW_LEV 0x3
277#define GPIO_INT_HIGH_LEV 0x2
278#define GPIO_INT_RISE_EDGE 0x0
279#define GPIO_INT_FALL_EDGE 0x1
280#define GPIO_INT_NONE 0x4
281
282/* Mandatory defines used globally */
283
284/* this is an i.MX27 CPU */
285#define cpu_is_mx27() (1)
286
287/* this CPU supports up to 192 GPIOs (don't forget the baseboard!) */
288#define ARCH_NR_GPIOS (192 + 16)
289
290/* OS clock tick rate */
291#define CLOCK_TICK_RATE 13300000
292
293/* Start of RAM */
294#define PHYS_OFFSET SDRAM_BASE_ADDR
295
296/* max interrupt lines count */
297#define NR_IRQS 256
298
299/* count of internal interrupt sources */
300#define MXC_MAX_INT_LINES 64
301
302#endif /* __ASM_ARCH_MXC_MX27_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
index 36a1af495bb3..a7373e4a56cb 100644
--- a/include/asm-arm/arch-mxc/mx31.h
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -320,6 +320,8 @@
320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM) 320#define MXC_MAX_GPIO_LINES (GPIO_NUM_PIN * GPIO_PORT_NUM)
321#define MXC_MAX_VIRTUAL_INTS 16 321#define MXC_MAX_VIRTUAL_INTS 16
322 322
323#define NR_IRQS (MXC_MAX_INT_LINES + MXC_MAX_GPIO_LINES + MXC_MAX_VIRTUAL_INTS)
324
323/*! 325/*!
324 * Number of GPIO port as defined in the IC Spec 326 * Number of GPIO port as defined in the IC Spec
325 */ 327 */
@@ -347,6 +349,25 @@
347#define SYSTEM_REV_MIN CHIP_REV_1_0 349#define SYSTEM_REV_MIN CHIP_REV_1_0
348#define SYSTEM_REV_NUM 3 350#define SYSTEM_REV_NUM 3
349 351
352/* gpio and gpio based interrupt handling */
353#define GPIO_DR 0x00
354#define GPIO_GDIR 0x04
355#define GPIO_PSR 0x08
356#define GPIO_ICR1 0x0C
357#define GPIO_ICR2 0x10
358#define GPIO_IMR 0x14
359#define GPIO_ISR 0x18
360#define GPIO_INT_LOW_LEV 0x0
361#define GPIO_INT_HIGH_LEV 0x1
362#define GPIO_INT_RISE_EDGE 0x2
363#define GPIO_INT_FALL_EDGE 0x3
364#define GPIO_INT_NONE 0x4
365
366/* Mandatory defines used globally */
367
368/* this CPU supports up to 96 GPIOs */
369#define ARCH_NR_GPIOS 96
370
350#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 371#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
351 372
352/* this is a i.MX31 CPU */ 373/* this is a i.MX31 CPU */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_H__ 20#ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
20# define cpu_is_mx31() (0) 29# define cpu_is_mx31() (0)
21#endif 30#endif
22 31
23/* 32#ifndef CONFIG_MACH_MX27
24 ***************************************** 33# define cpu_is_mx27() (0)
25 * GPT Register definitions * 34#endif
26 *****************************************
27 */
28#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
29#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
30#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
31#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
32#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
33#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
34#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
35#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
36#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
37#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
38
39/* GPT Control register bit definitions */
40#define GPTCR_FO3 (1 << 31)
41#define GPTCR_FO2 (1 << 30)
42#define GPTCR_FO1 (1 << 29)
43
44#define GPTCR_OM3_SHIFT 26
45#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
48#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
49#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
50#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
51
52#define GPTCR_OM2_SHIFT 23
53#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
56#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
57#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
58#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
59
60#define GPTCR_OM1_SHIFT 20
61#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
64#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
65#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
66#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
67
68#define GPTCR_IM2_SHIFT 18
69#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
71#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
72#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
73#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
74
75#define GPTCR_IM1_SHIFT 16
76#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
78#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
79#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
80#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
81
82#define GPTCR_SWR (1 << 15)
83#define GPTCR_FRR (1 << 9)
84
85#define GPTCR_CLKSRC_SHIFT 6
86#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
88#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
89#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
90#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
91
92#define GPTCR_STOPEN (1 << 5)
93#define GPTCR_DOZEN (1 << 4)
94#define GPTCR_WAITEN (1 << 3)
95#define GPTCR_DBGEN (1 << 2)
96
97#define GPTCR_ENMOD (1 << 1)
98#define GPTCR_ENABLE (1 << 0)
99
100#define GPTSR_OF1 (1 << 0)
101#define GPTSR_OF2 (1 << 1)
102#define GPTSR_OF3 (1 << 2)
103#define GPTSR_IF1 (1 << 3)
104#define GPTSR_IF2 (1 << 4)
105#define GPTSR_ROV (1 << 5)
106
107#define GPTIR_OF1IE GPTSR_OF1
108#define GPTIR_OF2IE GPTSR_OF2
109#define GPTIR_OF3IE GPTSR_OF3
110#define GPTIR_IF1IE GPTSR_IF1
111#define GPTIR_IF2IE GPTSR_IF2
112#define GPTIR_ROVIE GPTSR_ROV
113
114/*
115 *****************************************
116 * AVIC Registers *
117 *****************************************
118 */
119#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
120#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
121#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
122#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
123#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
124#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
125#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
126#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
127#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
128#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
129#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
130#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
131#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
132#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
133#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
134#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
135#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
136#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
137#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
138#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
139#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
140#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
141#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
142#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
143#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
144#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
145#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
146
147#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
148#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
149#define IIM_PROD_REV_SH 3
150#define IIM_PROD_REV_LEN 5
151 35
152#endif /* __ASM_ARCH_MXC_H__ */ 36#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
1/*
2 * mxc_timer.h
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 * Boston, MA 02110-1301, USA.
21 */
22
23#ifndef __PLAT_MXC_TIMER_H
24#define __PLAT_MXC_TIMER_H
25
26#include <linux/clk.h>
27#include <asm/hardware.h>
28
29#ifdef CONFIG_ARCH_IMX
30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
31#define TIMER_INTERRUPT TIM1_INT
32
33#define TCTL_VAL TCTL_CLK_PCLK1
34#define TCTL_IRQEN (1<<4)
35#define TCTL_FRR (1<<8)
36#define TCTL_CLK_PCLK1 (1<<1)
37#define TCTL_CLK_PCLK1_4 (2<<1)
38#define TCTL_CLK_TIN (3<<1)
39#define TCTL_CLK_32 (4<<1)
40
41#define MXC_TCTL 0x00
42#define MXC_TPRER 0x04
43#define MXC_TCMP 0x08
44#define MXC_TCR 0x0c
45#define MXC_TCN 0x10
46#define MXC_TSTAT 0x14
47#define TSTAT_CAPT (1<<1)
48#define TSTAT_COMP (1<<0)
49
50static inline void gpt_irq_disable(void)
51{
52 unsigned int tmp;
53
54 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
55 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
56}
57
58static inline void gpt_irq_enable(void)
59{
60 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
61 TIMER_BASE + MXC_TCTL);
62}
63
64static void gpt_irq_acknowledge(void)
65{
66 __raw_writel(0, TIMER_BASE + MXC_TSTAT);
67}
68#endif /* CONFIG_ARCH_IMX */
69
70#ifdef CONFIG_ARCH_MX2
71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
72#define TIMER_INTERRUPT MXC_INT_GPT1
73
74#define MXC_TCTL 0x00
75#define TCTL_VAL TCTL_CLK_PCLK1
76#define TCTL_CLK_PCLK1 (1<<1)
77#define TCTL_CLK_PCLK1_4 (2<<1)
78#define TCTL_IRQEN (1<<4)
79#define TCTL_FRR (1<<8)
80#define MXC_TPRER 0x04
81#define MXC_TCMP 0x08
82#define MXC_TCR 0x0c
83#define MXC_TCN 0x10
84#define MXC_TSTAT 0x14
85#define TSTAT_CAPT (1<<1)
86#define TSTAT_COMP (1<<0)
87
88static inline void gpt_irq_disable(void)
89{
90 unsigned int tmp;
91
92 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
93 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
94}
95
96static inline void gpt_irq_enable(void)
97{
98 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
99 TIMER_BASE + MXC_TCTL);
100}
101
102static void gpt_irq_acknowledge(void)
103{
104 __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
105}
106#endif /* CONFIG_ARCH_MX2 */
107
108#ifdef CONFIG_ARCH_MX3
109#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
110#define TIMER_INTERRUPT MXC_INT_GPT
111
112#define MXC_TCTL 0x00
113#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
114#define TCTL_CLK_IPG (1<<6)
115#define TCTL_FRR (1<<9)
116#define TCTL_WAITEN (1<<3)
117
118#define MXC_TPRER 0x04
119#define MXC_TSTAT 0x08
120#define TSTAT_OF1 (1<<0)
121#define TSTAT_OF2 (1<<1)
122#define TSTAT_OF3 (1<<2)
123#define TSTAT_IF1 (1<<3)
124#define TSTAT_IF2 (1<<4)
125#define TSTAT_ROV (1<<5)
126#define MXC_IR 0x0c
127#define MXC_TCMP 0x10
128#define MXC_TCMP2 0x14
129#define MXC_TCMP3 0x18
130#define MXC_TCR 0x1c
131#define MXC_TCN 0x24
132
133static inline void gpt_irq_disable(void)
134{
135 __raw_writel(0, TIMER_BASE + MXC_IR);
136}
137
138static inline void gpt_irq_enable(void)
139{
140 __raw_writel(1<<0, TIMER_BASE + MXC_IR);
141}
142
143static inline void gpt_irq_acknowledge(void)
144{
145 __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
146}
147#endif /* CONFIG_ARCH_MX3 */
148
149#define TCTL_SWR (1<<15)
150#define TCTL_CC (1<<10)
151#define TCTL_OM (1<<9)
152#define TCTL_CAP_RIS (1<<6)
153#define TCTL_CAP_FAL (2<<6)
154#define TCTL_CAP_RIS_FAL (3<<6)
155#define TCTL_CAP_ENA (1<<5)
156#define TCTL_TEN (1<<0)
157
158#endif
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 0b7b34603f1c..0dca11ce21fc 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -66,13 +66,13 @@
66 __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) 66 __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
67 67
68# define REGGETIM_IDX(var, reg, field, idx) \ 68# define REGGETIM_IDX(var, reg, field, idx) \
69 __REGGET(var, reg ## _ ## field((idx))) / \ 69 __REGGET(var, reg ## _ ## field((idx))) / \
70 __REGSHIFT(reg ## _ ## field((idx))) 70 __REGSHIFT(reg ## _ ## field((idx)))
71 71
72#else 72#else
73 73
74# define __REG(x) io_p2v(x) 74# define __REG(x) io_p2v(x)
75# define __REG2(x, y) io_p2v((x) + (y)) 75# define __REG2(x, y) io_p2v((x) + 4 * (y))
76 76
77#endif 77#endif
78 78
diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h
index e9c65ce3cb12..c7db9004ec31 100644
--- a/include/asm-arm/arch-omap/board-2430sdp.h
+++ b/include/asm-arm/arch-omap/board-2430sdp.h
@@ -36,9 +36,4 @@
36 36
37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ 37#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ
38 38
39/* TWL4030 Primary Interrupt Handler (PIH) interrupts */
40#define IH_TWL4030_BASE IH_BOARD_BASE
41#define IH_TWL4030_END (IH_TWL4030_BASE+8)
42#define NR_IRQS (IH_TWL4030_END)
43
44#endif /* __ASM_ARCH_OMAP_2430SDP_H */ 39#endif /* __ASM_ARCH_OMAP_2430SDP_H */
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
index 0f6404435ea8..c5d0f32a40ac 100644
--- a/include/asm-arm/arch-omap/board-h3.h
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -30,12 +30,6 @@
30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */ 30/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
31#define OMAP1710_ETHR_START 0x04000300 31#define OMAP1710_ETHR_START 0x04000300
32 32
33#define MAXIRQNUM (IH_BOARD_BASE)
34#define MAXFIQNUM MAXIRQNUM
35#define MAXSWINUM MAXIRQNUM
36
37#define NR_IRQS (MAXIRQNUM + 1)
38
39extern void h3_mmc_init(void); 33extern void h3_mmc_init(void);
40extern void h3_mmc_slot_cover_handler(void *arg, int state); 34extern void h3_mmc_slot_cover_handler(void *arg, int state);
41 35
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
index 56d2c98e143c..9ca03dec9d36 100644
--- a/include/asm-arm/arch-omap/board-innovator.h
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -36,9 +36,6 @@
36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00 36#define OMAP1510P1_EMIFS_PRI_VALUE 0x00
37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00 37#define OMAP1510P1_EMIFF_PRI_VALUE 0x00
38 38
39#define NR_FPGA_IRQS 24
40#define NR_IRQS (IH_BOARD_BASE + NR_FPGA_IRQS)
41
42#ifndef __ASSEMBLY__ 39#ifndef __ASSEMBLY__
43void fpga_write(unsigned char val, int reg); 40void fpga_write(unsigned char val, int reg);
44unsigned char fpga_read(int reg); 41unsigned char fpga_read(int reg);
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
index eb74420cb439..d7429cb0f726 100644
--- a/include/asm-arm/arch-omap/board-perseus2.h
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -36,10 +36,4 @@
36#define OMAP_SDRAM_DEVICE D256M_1X16_4B 36#define OMAP_SDRAM_DEVICE D256M_1X16_4B
37#endif 37#endif
38 38
39#define MAXIRQNUM IH_BOARD_BASE
40#define MAXFIQNUM MAXIRQNUM
41#define MAXSWINUM MAXIRQNUM
42
43#define NR_IRQS (MAXIRQNUM + 1)
44
45#endif 39#endif
diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index 12a5e4de9518..4c7b3514f71a 100644
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -33,12 +33,24 @@ struct dpll_data {
33 void __iomem *mult_div1_reg; 33 void __iomem *mult_div1_reg;
34 u32 mult_mask; 34 u32 mult_mask;
35 u32 div1_mask; 35 u32 div1_mask;
36 u16 last_rounded_m;
37 u8 last_rounded_n;
38 unsigned long last_rounded_rate;
39 unsigned int rate_tolerance;
40 u16 max_multiplier;
41 u8 max_divider;
42 u32 max_tolerance;
36# if defined(CONFIG_ARCH_OMAP3) 43# if defined(CONFIG_ARCH_OMAP3)
44 u8 modes;
37 void __iomem *control_reg; 45 void __iomem *control_reg;
38 u32 enable_mask; 46 u32 enable_mask;
39 u8 auto_recal_bit; 47 u8 auto_recal_bit;
40 u8 recal_en_bit; 48 u8 recal_en_bit;
41 u8 recal_st_bit; 49 u8 recal_st_bit;
50 void __iomem *autoidle_reg;
51 u32 autoidle_mask;
52 void __iomem *idlest_reg;
53 u8 idlest_bit;
42# endif 54# endif
43}; 55};
44 56
@@ -66,11 +78,14 @@ struct clk {
66 void __iomem *clksel_reg; 78 void __iomem *clksel_reg;
67 u32 clksel_mask; 79 u32 clksel_mask;
68 const struct clksel *clksel; 80 const struct clksel *clksel;
69 const struct dpll_data *dpll_data; 81 struct dpll_data *dpll_data;
70#else 82#else
71 __u8 rate_offset; 83 __u8 rate_offset;
72 __u8 src_offset; 84 __u8 src_offset;
73#endif 85#endif
86#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
87 struct dentry *dent; /* For visible tree hierarchy */
88#endif
74}; 89};
75 90
76struct cpufreq_frequency_table; 91struct cpufreq_frequency_table;
diff --git a/include/asm-arm/arch-omap/common.h b/include/asm-arm/arch-omap/common.h
index 36a3b62d4d8d..8ac03071f60c 100644
--- a/include/asm-arm/arch-omap/common.h
+++ b/include/asm-arm/arch-omap/common.h
@@ -47,8 +47,23 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
47} 47}
48#endif 48#endif
49 49
50/* IO bases for various OMAP processors */
51struct omap_globals {
52 void __iomem *tap; /* Control module ID code */
53 void __iomem *sdrc; /* SDRAM Controller */
54 void __iomem *sms; /* SDRAM Memory Scheduler */
55 void __iomem *ctrl; /* System Control Module */
56 void __iomem *prm; /* Power and Reset Management */
57 void __iomem *cm; /* Clock Management */
58};
59
50void omap2_set_globals_242x(void); 60void omap2_set_globals_242x(void);
51void omap2_set_globals_243x(void); 61void omap2_set_globals_243x(void);
52void omap2_set_globals_343x(void); 62void omap2_set_globals_343x(void);
53 63
64/* These get called from omap2_set_globals_xxxx(), do not call these */
65void omap2_set_globals_memory(struct omap_globals *);
66void omap2_set_globals_control(struct omap_globals *);
67void omap2_set_globals_prcm(struct omap_globals *);
68
54#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */ 69#endif /* __ARCH_ARM_MACH_OMAP_COMMON_H */
diff --git a/include/asm-arm/arch-omap/control.h b/include/asm-arm/arch-omap/control.h
index 59c0686f8be7..987553e3eeb9 100644
--- a/include/asm-arm/arch-omap/control.h
+++ b/include/asm-arm/arch-omap/control.h
@@ -167,8 +167,7 @@
167 167
168#ifndef __ASSEMBLY__ 168#ifndef __ASSEMBLY__
169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 169#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
170extern void omap_ctrl_base_set(u32 base); 170extern void __iomem *omap_ctrl_base_get(void);
171extern u32 omap_ctrl_base_get(void);
172extern u8 omap_ctrl_readb(u16 offset); 171extern u8 omap_ctrl_readb(u16 offset);
173extern u16 omap_ctrl_readw(u16 offset); 172extern u16 omap_ctrl_readw(u16 offset);
174extern u32 omap_ctrl_readl(u16 offset); 173extern u32 omap_ctrl_readl(u16 offset);
@@ -176,7 +175,6 @@ extern void omap_ctrl_writeb(u8 val, u16 offset);
176extern void omap_ctrl_writew(u16 val, u16 offset); 175extern void omap_ctrl_writew(u16 val, u16 offset);
177extern void omap_ctrl_writel(u32 val, u16 offset); 176extern void omap_ctrl_writel(u32 val, u16 offset);
178#else 177#else
179#define omap_ctrl_base_set(x) WARN_ON(1)
180#define omap_ctrl_base_get() 0 178#define omap_ctrl_base_get() 0
181#define omap_ctrl_readb(x) 0 179#define omap_ctrl_readb(x) 0
182#define omap_ctrl_readw(x) 0 180#define omap_ctrl_readw(x) 0
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
index e8a4cf52778b..52db09f83281 100644
--- a/include/asm-arm/arch-omap/cpu.h
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -3,7 +3,7 @@
3 * 3 *
4 * OMAP cpu type detection 4 * OMAP cpu type detection
5 * 5 *
6 * Copyright (C) 2004 Nokia Corporation 6 * Copyright (C) 2004, 2008 Nokia Corporation
7 * 7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com> 8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 * 9 *
@@ -26,6 +26,12 @@
26#ifndef __ASM_ARCH_OMAP_CPU_H 26#ifndef __ASM_ARCH_OMAP_CPU_H
27#define __ASM_ARCH_OMAP_CPU_H 27#define __ASM_ARCH_OMAP_CPU_H
28 28
29struct omap_chip_id {
30 u8 oc;
31};
32
33#define OMAP_CHIP_INIT(x) { .oc = x }
34
29extern unsigned int system_rev; 35extern unsigned int system_rev;
30 36
31#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f) 37#define omap2_cpu_rev() ((system_rev >> 12) & 0x0f)
@@ -345,6 +351,33 @@ IS_OMAP_TYPE(3430, 0x3430)
345#define OMAP2430_REV_ES1_0 0x24300000 351#define OMAP2430_REV_ES1_0 0x24300000
346#define OMAP3430_REV_ES1_0 0x34300000 352#define OMAP3430_REV_ES1_0 0x34300000
347#define OMAP3430_REV_ES2_0 0x34301000 353#define OMAP3430_REV_ES2_0 0x34301000
354#define OMAP3430_REV_ES2_1 0x34302000
355#define OMAP3430_REV_ES2_2 0x34303000
356
357/*
358 * omap_chip bits
359 *
360 * CHIP_IS_OMAP{2420,2430,3430} indicate that a particular structure is
361 * valid on all chips of that type. CHIP_IS_OMAP3430ES{1,2} indicates
362 * something that is only valid on that particular ES revision.
363 *
364 * These bits may be ORed together to indicate structures that are
365 * available on multiple chip types.
366 *
367 * To test whether a particular structure matches the current OMAP chip type,
368 * use omap_chip_is().
369 *
370 */
371#define CHIP_IS_OMAP2420 (1 << 0)
372#define CHIP_IS_OMAP2430 (1 << 1)
373#define CHIP_IS_OMAP3430 (1 << 2)
374#define CHIP_IS_OMAP3430ES1 (1 << 3)
375#define CHIP_IS_OMAP3430ES2 (1 << 4)
376
377#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
378
379int omap_chip_is(struct omap_chip_id oci);
380
348 381
349/* 382/*
350 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD 383 * Macro to detect device type i.e. EMU/HS/TST/GP/BAD
@@ -362,6 +395,8 @@ IS_OMAP_TYPE(3430, 0x3430)
362#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP) 395#define is_device_type_gp() (get_device_type() == DEVICE_TYPE_GP)
363#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD) 396#define is_device_type_bad() (get_device_type() == DEVICE_TYPE_BAD)
364 397
365#endif 398void omap2_check_revision(void);
399
400#endif /* defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) */
366 401
367#endif 402#endif
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 24acf090030d..f4dcb9587869 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,108 +22,128 @@
22#define __ASM_ARCH_DMA_H 22#define __ASM_ARCH_DMA_H
23 23
24/* Hardware registers for omap1 */ 24/* Hardware registers for omap1 */
25#define OMAP_DMA_BASE (0xfffed800) 25#define OMAP1_DMA_BASE (0xfffed800)
26#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) 26
27#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) 27#define OMAP1_DMA_GCR 0x400
28#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) 28#define OMAP1_DMA_GSCR 0x404
29#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) 29#define OMAP1_DMA_GRST 0x408
30#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) 30#define OMAP1_DMA_HW_ID 0x442
31#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) 31#define OMAP1_DMA_PCH2_ID 0x444
32#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) 32#define OMAP1_DMA_PCH0_ID 0x446
33#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) 33#define OMAP1_DMA_PCH1_ID 0x448
34#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) 34#define OMAP1_DMA_PCHG_ID 0x44a
35#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) 35#define OMAP1_DMA_PCHD_ID 0x44c
36#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) 36#define OMAP1_DMA_CAPS_0_U 0x44e
37#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) 37#define OMAP1_DMA_CAPS_0_L 0x450
38#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) 38#define OMAP1_DMA_CAPS_1_U 0x452
39#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) 39#define OMAP1_DMA_CAPS_1_L 0x454
40#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) 40#define OMAP1_DMA_CAPS_2 0x456
41#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) 41#define OMAP1_DMA_CAPS_3 0x458
42#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) 42#define OMAP1_DMA_CAPS_4 0x45a
43#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) 43#define OMAP1_DMA_PCH2_SR 0x460
44#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) 44#define OMAP1_DMA_PCH0_SR 0x480
45#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) 45#define OMAP1_DMA_PCH1_SR 0x482
46 46#define OMAP1_DMA_PCHD_SR 0x4c0
47/* Hardware registers for omap2 */ 47
48#if defined(CONFIG_ARCH_OMAP3) 48/* Hardware registers for omap2 and omap3 */
49#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) 49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#else /* CONFIG_ARCH_OMAP2 */ 50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) 51
52#endif 52#define OMAP_DMA4_REVISION 0x00
53 53#define OMAP_DMA4_GCR 0x78
54#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) 54#define OMAP_DMA4_IRQSTATUS_L0 0x08
55#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) 55#define OMAP_DMA4_IRQSTATUS_L1 0x0c
56#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) 56#define OMAP_DMA4_IRQSTATUS_L2 0x10
57#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) 57#define OMAP_DMA4_IRQSTATUS_L3 0x14
58#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) 58#define OMAP_DMA4_IRQENABLE_L0 0x18
59#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) 59#define OMAP_DMA4_IRQENABLE_L1 0x1c
60#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) 60#define OMAP_DMA4_IRQENABLE_L2 0x20
61#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) 61#define OMAP_DMA4_IRQENABLE_L3 0x24
62#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) 62#define OMAP_DMA4_SYSSTATUS 0x28
63#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) 63#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
64#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) 64#define OMAP_DMA4_CAPS_0 0x64
65#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) 65#define OMAP_DMA4_CAPS_2 0x6c
66#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) 66#define OMAP_DMA4_CAPS_3 0x70
67#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) 67#define OMAP_DMA4_CAPS_4 0x74
68#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) 68
69#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) 69#define OMAP1_LOGICAL_DMA_CH_COUNT 17
70 70#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
71#ifdef CONFIG_ARCH_OMAP1
72
73#define OMAP_LOGICAL_DMA_CH_COUNT 17
74 71
75/* Common channel specific registers for omap1 */ 72/* Common channel specific registers for omap1 */
76#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) 73#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
77#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) 74#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
78#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) 75#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
79#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) 76#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
80#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) 77#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
81#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) 78#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
82#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) 79#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
83#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) 80#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
84#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) 81#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
85#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) 82#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
86#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) 83#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
87#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) 84#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
88#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) 85#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
89 86#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
90#else 87#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
91
92#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
93 88
94/* Common channel specific registers for omap2 */ 89/* Common channel specific registers for omap2 */
95#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) 90#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
96#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) 91#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
97#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) 92#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
98#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) 93#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
99#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) 94#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
100#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) 95#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
101#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) 96#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
102#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) 97#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
103#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) 98#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
104#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) 99#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
105#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) 100#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
106#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) 101#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
107#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) 102#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
108 103#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
109#endif
110 104
111/* Channel specific registers only on omap1 */ 105/* Channel specific registers only on omap1 */
112#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) 106#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
113#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) 107#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
114#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) 108#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
115#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) 109#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
116#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) 110#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
117#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) 111#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
118#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) 112#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
119#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) 113#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
114#define OMAP1_DMA_CCEN(n) 0
115#define OMAP1_DMA_CCFN(n) 0
120 116
121/* Channel specific registers only on omap2 */ 117/* Channel specific registers only on omap2 */
122#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) 118#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
123#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) 119#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
124#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) 120#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
125#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) 121#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
126#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) 122#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
123
124/* Dummy defines to keep multi-omap compiles happy */
125#define OMAP1_DMA_REVISION 0
126#define OMAP1_DMA_IRQSTATUS_L0 0
127#define OMAP1_DMA_IRQENABLE_L0 0
128#define OMAP1_DMA_OCP_SYSCONFIG 0
129#define OMAP_DMA4_HW_ID 0
130#define OMAP_DMA4_CAPS_0_L 0
131#define OMAP_DMA4_CAPS_0_U 0
132#define OMAP_DMA4_CAPS_1_L 0
133#define OMAP_DMA4_CAPS_1_U 0
134#define OMAP_DMA4_GSCR 0
135#define OMAP_DMA4_CPC(n) 0
136
137#define OMAP_DMA4_LCH_CTRL(n) 0
138#define OMAP_DMA4_COLOR_L(n) 0
139#define OMAP_DMA4_COLOR_U(n) 0
140#define OMAP_DMA4_CCR2(n) 0
141#define OMAP1_DMA_CSSA(n) 0
142#define OMAP1_DMA_CDSA(n) 0
143#define OMAP_DMA4_CSSA_L(n) 0
144#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0
127 147
128/*----------------------------------------------------------------------------*/ 148/*----------------------------------------------------------------------------*/
129 149
@@ -196,63 +216,98 @@
196#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ 216#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
197#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ 217#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
198#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ 218#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
199#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */ 219#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
220#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
200#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ 221#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
201#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ 222#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
202#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ 223#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
203#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ 224#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
204#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ 225#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
205#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ 226#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
206#define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ 227#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
207#define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ 228#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
208#define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ 229#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
209#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ 230#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
210#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ 231#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
211#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ 232#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
212#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ 233#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
213#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ 234#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
214#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ 235#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
215#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ 236#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
216#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ 237#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
217#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ 238#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
218#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ 239#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
240#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
241#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
242#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
243#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
244#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
245#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
246#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
247#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
248#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
249#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
250#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
251#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
252#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
253#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
254#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
255#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
219#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ 256#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
220#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ 257#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
221#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ 258#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
222#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ 259#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
223#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */ 260#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
224#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */ 261#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
225#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */ 262#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
226#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */ 263#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
227#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */ 264#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
228#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */ 265#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
229#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */ 266#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
230#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */ 267#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
231#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */ 268#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
232#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */ 269#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
233#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */ 270#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
234#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */ 271#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
235#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */ 272#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
236#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */ 273#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
237#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */ 274#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
238#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */ 275#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
239 276#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
240#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */ 277#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
241#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */ 278#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
242#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */ 279#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
243#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */ 280#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
244#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */ 281#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
245#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */ 282#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
246#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */ 283#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
247#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */ 284#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
248#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */ 285#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
249#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */ 286#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
250#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */ 287#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
251#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */ 288#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
252#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ 289#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
253#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ 290#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
254#define OMAP24XX_DMA_MS 63 /* SDMA_62 */ 291#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
255#define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ 292#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
293#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
294#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
295#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
296#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
297#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
298#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
299#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
300#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
301#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
302#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
303#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
304#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
305#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
306#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
307#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
308#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
309#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
310#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
256 311
257/*----------------------------------------------------------------------------*/ 312/*----------------------------------------------------------------------------*/
258 313
@@ -358,6 +413,11 @@ enum omap_dma_burst_mode {
358 OMAP_DMA_DATA_BURST_16, 413 OMAP_DMA_DATA_BURST_16,
359}; 414};
360 415
416enum end_type {
417 OMAP_DMA_LITTLE_ENDIAN = 0,
418 OMAP_DMA_BIG_ENDIAN
419};
420
361enum omap_dma_color_mode { 421enum omap_dma_color_mode {
362 OMAP_DMA_COLOR_DIS = 0, 422 OMAP_DMA_COLOR_DIS = 0,
363 OMAP_DMA_CONSTANT_FILL, 423 OMAP_DMA_CONSTANT_FILL,
@@ -370,24 +430,34 @@ enum omap_dma_write_mode {
370 OMAP_DMA_WRITE_LAST_NON_POSTED 430 OMAP_DMA_WRITE_LAST_NON_POSTED
371}; 431};
372 432
433enum omap_dma_channel_mode {
434 OMAP_DMA_LCH_2D = 0,
435 OMAP_DMA_LCH_G,
436 OMAP_DMA_LCH_P,
437 OMAP_DMA_LCH_PD
438};
439
373struct omap_dma_channel_params { 440struct omap_dma_channel_params {
374 int data_type; /* data type 8,16,32 */ 441 int data_type; /* data type 8,16,32 */
375 int elem_count; /* number of elements in a frame */ 442 int elem_count; /* number of elements in a frame */
376 int frame_count; /* number of frames in a element */ 443 int frame_count; /* number of frames in a element */
377 444
378 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ 445 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
379 int src_amode; /* constant , post increment, indexed , double indexed */ 446 int src_amode; /* constant, post increment, indexed,
447 double indexed */
380 unsigned long src_start; /* source address : physical */ 448 unsigned long src_start; /* source address : physical */
381 int src_ei; /* source element index */ 449 int src_ei; /* source element index */
382 int src_fi; /* source frame index */ 450 int src_fi; /* source frame index */
383 451
384 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ 452 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
385 int dst_amode; /* constant , post increment, indexed , double indexed */ 453 int dst_amode; /* constant, post increment, indexed,
454 double indexed */
386 unsigned long dst_start; /* source address : physical */ 455 unsigned long dst_start; /* source address : physical */
387 int dst_ei; /* source element index */ 456 int dst_ei; /* source element index */
388 int dst_fi; /* source frame index */ 457 int dst_fi; /* source frame index */
389 458
390 int trigger; /* trigger attached if the channel is synchronized */ 459 int trigger; /* trigger attached if the channel is
460 synchronized */
391 int sync_mode; /* sycn on element, frame , block or packet */ 461 int sync_mode; /* sycn on element, frame , block or packet */
392 int src_or_dst_synch; /* source synch(1) or destination synch(0) */ 462 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
393 463
@@ -404,8 +474,8 @@ struct omap_dma_channel_params {
404 474
405extern void omap_set_dma_priority(int lch, int dst_port, int priority); 475extern void omap_set_dma_priority(int lch, int dst_port, int priority);
406extern int omap_request_dma(int dev_id, const char *dev_name, 476extern int omap_request_dma(int dev_id, const char *dev_name,
407 void (* callback)(int lch, u16 ch_status, void *data), 477 void (*callback)(int lch, u16 ch_status, void *data),
408 void *data, int *dma_ch); 478 void *data, int *dma_ch);
409extern void omap_enable_dma_irq(int ch, u16 irq_bits); 479extern void omap_enable_dma_irq(int ch, u16 irq_bits);
410extern void omap_disable_dma_irq(int ch, u16 irq_bits); 480extern void omap_disable_dma_irq(int ch, u16 irq_bits);
411extern void omap_free_dma(int ch); 481extern void omap_free_dma(int ch);
@@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
418extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, 488extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
419 u32 color); 489 u32 color);
420extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); 490extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
491extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
421 492
422extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, 493extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
423 unsigned long src_start, 494 unsigned long src_start,
@@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch,
436 enum omap_dma_burst_mode burst_mode); 507 enum omap_dma_burst_mode burst_mode);
437 508
438extern void omap_set_dma_params(int lch, 509extern void omap_set_dma_params(int lch,
439 struct omap_dma_channel_params * params); 510 struct omap_dma_channel_params *params);
440 511
441extern void omap_dma_link_lch (int lch_head, int lch_queue); 512extern void omap_dma_link_lch(int lch_head, int lch_queue);
442extern void omap_dma_unlink_lch (int lch_head, int lch_queue); 513extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
443 514
444extern int omap_set_dma_callback(int lch, 515extern int omap_set_dma_callback(int lch,
445 void (* callback)(int lch, u16 ch_status, void *data), 516 void (*callback)(int lch, u16 ch_status, void *data),
446 void *data); 517 void *data);
447extern dma_addr_t omap_get_dma_src_pos(int lch); 518extern dma_addr_t omap_get_dma_src_pos(int lch);
448extern dma_addr_t omap_get_dma_dst_pos(int lch); 519extern dma_addr_t omap_get_dma_dst_pos(int lch);
449extern int omap_get_dma_src_addr_counter(int lch);
450extern void omap_clear_dma(int lch); 520extern void omap_clear_dma(int lch);
521extern int omap_get_dma_active_status(int lch);
451extern int omap_dma_running(void); 522extern int omap_dma_running(void);
452extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, 523extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
453 int tparams); 524 int tparams);
454extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, 525extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
455 unsigned char write_prio); 526 unsigned char write_prio);
527extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
528extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
529extern int omap_get_dma_index(int lch, int *ei, int *fi);
456 530
457/* Chaining APIs */ 531/* Chaining APIs */
458#ifndef CONFIG_ARCH_OMAP1 532#ifndef CONFIG_ARCH_OMAP1
@@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id);
478#endif 552#endif
479 553
480/* LCD DMA functions */ 554/* LCD DMA functions */
481extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), 555extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
482 void *data); 556 void *data);
483extern void omap_free_lcd_dma(void); 557extern void omap_free_lcd_dma(void);
484extern void omap_setup_lcd_dma(void); 558extern void omap_setup_lcd_dma(void);
diff --git a/include/asm-arm/arch-omap/dmtimer.h b/include/asm-arm/arch-omap/dmtimer.h
index fefb276ed402..02b29e8437ae 100644
--- a/include/asm-arm/arch-omap/dmtimer.h
+++ b/include/asm-arm/arch-omap/dmtimer.h
@@ -66,6 +66,7 @@ void omap_dm_timer_stop(struct omap_dm_timer *timer);
66 66
67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source); 67void omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value); 68void omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
69void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match); 70void omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
70void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger); 71void omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
71void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler); 72void omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
index 6a883e0bdbb8..f420881d2a3b 100644
--- a/include/asm-arm/arch-omap/fpga.h
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -169,30 +169,29 @@ struct h2p2_dbg_fpga {
169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13) 169#define OMAP1510_INT_FPGA (IH_GPIO_BASE + 13)
170 170
171/* IRQ Numbers for interrupts muxed through the FPGA */ 171/* IRQ Numbers for interrupts muxed through the FPGA */
172#define OMAP1510_IH_FPGA_BASE IH_BOARD_BASE 172#define OMAP1510_INT_FPGA_ATN (OMAP_FPGA_IRQ_BASE + 0)
173#define OMAP1510_INT_FPGA_ATN (OMAP1510_IH_FPGA_BASE + 0) 173#define OMAP1510_INT_FPGA_ACK (OMAP_FPGA_IRQ_BASE + 1)
174#define OMAP1510_INT_FPGA_ACK (OMAP1510_IH_FPGA_BASE + 1) 174#define OMAP1510_INT_FPGA2 (OMAP_FPGA_IRQ_BASE + 2)
175#define OMAP1510_INT_FPGA2 (OMAP1510_IH_FPGA_BASE + 2) 175#define OMAP1510_INT_FPGA3 (OMAP_FPGA_IRQ_BASE + 3)
176#define OMAP1510_INT_FPGA3 (OMAP1510_IH_FPGA_BASE + 3) 176#define OMAP1510_INT_FPGA4 (OMAP_FPGA_IRQ_BASE + 4)
177#define OMAP1510_INT_FPGA4 (OMAP1510_IH_FPGA_BASE + 4) 177#define OMAP1510_INT_FPGA5 (OMAP_FPGA_IRQ_BASE + 5)
178#define OMAP1510_INT_FPGA5 (OMAP1510_IH_FPGA_BASE + 5) 178#define OMAP1510_INT_FPGA6 (OMAP_FPGA_IRQ_BASE + 6)
179#define OMAP1510_INT_FPGA6 (OMAP1510_IH_FPGA_BASE + 6) 179#define OMAP1510_INT_FPGA7 (OMAP_FPGA_IRQ_BASE + 7)
180#define OMAP1510_INT_FPGA7 (OMAP1510_IH_FPGA_BASE + 7) 180#define OMAP1510_INT_FPGA8 (OMAP_FPGA_IRQ_BASE + 8)
181#define OMAP1510_INT_FPGA8 (OMAP1510_IH_FPGA_BASE + 8) 181#define OMAP1510_INT_FPGA9 (OMAP_FPGA_IRQ_BASE + 9)
182#define OMAP1510_INT_FPGA9 (OMAP1510_IH_FPGA_BASE + 9) 182#define OMAP1510_INT_FPGA10 (OMAP_FPGA_IRQ_BASE + 10)
183#define OMAP1510_INT_FPGA10 (OMAP1510_IH_FPGA_BASE + 10) 183#define OMAP1510_INT_FPGA11 (OMAP_FPGA_IRQ_BASE + 11)
184#define OMAP1510_INT_FPGA11 (OMAP1510_IH_FPGA_BASE + 11) 184#define OMAP1510_INT_FPGA12 (OMAP_FPGA_IRQ_BASE + 12)
185#define OMAP1510_INT_FPGA12 (OMAP1510_IH_FPGA_BASE + 12) 185#define OMAP1510_INT_ETHER (OMAP_FPGA_IRQ_BASE + 13)
186#define OMAP1510_INT_ETHER (OMAP1510_IH_FPGA_BASE + 13) 186#define OMAP1510_INT_FPGAUART1 (OMAP_FPGA_IRQ_BASE + 14)
187#define OMAP1510_INT_FPGAUART1 (OMAP1510_IH_FPGA_BASE + 14) 187#define OMAP1510_INT_FPGAUART2 (OMAP_FPGA_IRQ_BASE + 15)
188#define OMAP1510_INT_FPGAUART2 (OMAP1510_IH_FPGA_BASE + 15) 188#define OMAP1510_INT_FPGA_TS (OMAP_FPGA_IRQ_BASE + 16)
189#define OMAP1510_INT_FPGA_TS (OMAP1510_IH_FPGA_BASE + 16) 189#define OMAP1510_INT_FPGA17 (OMAP_FPGA_IRQ_BASE + 17)
190#define OMAP1510_INT_FPGA17 (OMAP1510_IH_FPGA_BASE + 17) 190#define OMAP1510_INT_FPGA_CAM (OMAP_FPGA_IRQ_BASE + 18)
191#define OMAP1510_INT_FPGA_CAM (OMAP1510_IH_FPGA_BASE + 18) 191#define OMAP1510_INT_FPGA_RTC_A (OMAP_FPGA_IRQ_BASE + 19)
192#define OMAP1510_INT_FPGA_RTC_A (OMAP1510_IH_FPGA_BASE + 19) 192#define OMAP1510_INT_FPGA_RTC_B (OMAP_FPGA_IRQ_BASE + 20)
193#define OMAP1510_INT_FPGA_RTC_B (OMAP1510_IH_FPGA_BASE + 20) 193#define OMAP1510_INT_FPGA_CD (OMAP_FPGA_IRQ_BASE + 21)
194#define OMAP1510_INT_FPGA_CD (OMAP1510_IH_FPGA_BASE + 21) 194#define OMAP1510_INT_FPGA22 (OMAP_FPGA_IRQ_BASE + 22)
195#define OMAP1510_INT_FPGA22 (OMAP1510_IH_FPGA_BASE + 22) 195#define OMAP1510_INT_FPGA23 (OMAP_FPGA_IRQ_BASE + 23)
196#define OMAP1510_INT_FPGA23 (OMAP1510_IH_FPGA_BASE + 23)
197 196
198#endif 197#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
index 91d85b3417b7..45fdfccbd5d4 100644
--- a/include/asm-arm/arch-omap/hardware.h
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -284,6 +284,7 @@
284#include "omap1510.h" 284#include "omap1510.h"
285#include "omap24xx.h" 285#include "omap24xx.h"
286#include "omap16xx.h" 286#include "omap16xx.h"
287#include "omap34xx.h"
287 288
288#ifndef __ASSEMBLER__ 289#ifndef __ASSEMBLER__
289 290
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
index 160578e1f557..0b13557fd30b 100644
--- a/include/asm-arm/arch-omap/io.h
+++ b/include/asm-arm/arch-omap/io.h
@@ -60,6 +60,7 @@
60#define IO_SIZE 0x40000 60#define IO_SIZE 0x40000
61#define IO_VIRT (IO_PHYS - IO_OFFSET) 61#define IO_VIRT (IO_PHYS - IO_OFFSET)
62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET) 62#define IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define OMAP1_IO_ADDRESS(pa) ((pa) - IO_OFFSET)
63#define io_p2v(pa) ((pa) - IO_OFFSET) 64#define io_p2v(pa) ((pa) - IO_OFFSET)
64#define io_v2p(va) ((va) + IO_OFFSET) 65#define io_v2p(va) ((va) + IO_OFFSET)
65 66
@@ -91,6 +92,7 @@
91 92
92#define IO_OFFSET 0x90000000 93#define IO_OFFSET 0x90000000
93#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 94#define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
94#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ 96#define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */
95#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */ 97#define io_v2p(va) ((va) - IO_OFFSET) /* Works for L3 and L4 */
96 98
@@ -148,6 +150,7 @@
148 150
149#define IO_OFFSET 0x90000000 151#define IO_OFFSET 0x90000000
150#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 152#define IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
153#define OMAP2_IO_ADDRESS(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
151#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */ 154#define io_p2v(pa) ((pa) + IO_OFFSET)/* Works for L3 and L4 */
152#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */ 155#define io_v2p(va) ((va) - IO_OFFSET)/* Works for L3 and L4 */
153 156
@@ -183,35 +186,12 @@
183#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v)) 186#define omap_writew(v,a) (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
184#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v)) 187#define omap_writel(v,a) (*(volatile unsigned int *)IO_ADDRESS(a) = (v))
185 188
186/* 16 bit uses LDRH/STRH, base +/- offset_8 */
187typedef struct { volatile u16 offset[256]; } __regbase16;
188#define __REGV16(vaddr) ((__regbase16 *)((vaddr)&~0xff)) \
189 ->offset[((vaddr)&0xff)>>1]
190#define __REG16(paddr) __REGV16(io_p2v(paddr))
191
192/* 8/32 bit uses LDR/STR, base +/- offset_12 */
193typedef struct { volatile u8 offset[4096]; } __regbase8;
194#define __REGV8(vaddr) ((__regbase8 *)((vaddr)&~4095)) \
195 ->offset[((vaddr)&4095)>>0]
196#define __REG8(paddr) __REGV8(io_p2v(paddr))
197
198typedef struct { volatile u32 offset[4096]; } __regbase32;
199#define __REGV32(vaddr) ((__regbase32 *)((vaddr)&~4095)) \
200 ->offset[((vaddr)&4095)>>2]
201#define __REG32(paddr) __REGV32(io_p2v(paddr))
202
203extern void omap1_map_common_io(void); 189extern void omap1_map_common_io(void);
204extern void omap1_init_common_hw(void); 190extern void omap1_init_common_hw(void);
205 191
206extern void omap2_map_common_io(void); 192extern void omap2_map_common_io(void);
207extern void omap2_init_common_hw(void); 193extern void omap2_init_common_hw(void);
208 194
209#else
210
211#define __REG8(paddr) io_p2v(paddr)
212#define __REG16(paddr) io_p2v(paddr)
213#define __REG32(paddr) io_p2v(paddr)
214
215#endif 195#endif
216 196
217#endif 197#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
index 87973654e625..7464c694859b 100644
--- a/include/asm-arm/arch-omap/irqs.h
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -285,7 +285,41 @@
285#define OMAP_MAX_GPIO_LINES 192 285#define OMAP_MAX_GPIO_LINES 192
286#define IH_GPIO_BASE (128 + IH2_BASE) 286#define IH_GPIO_BASE (128 + IH2_BASE)
287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE) 287#define IH_MPUIO_BASE (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
288#define IH_BOARD_BASE (16 + IH_MPUIO_BASE) 288#define OMAP_IRQ_END (IH_MPUIO_BASE + 16)
289
290/* External FPGA handles interrupts on Innovator boards */
291#define OMAP_FPGA_IRQ_BASE (OMAP_IRQ_END)
292#ifdef CONFIG_MACH_OMAP_INNOVATOR
293#define OMAP_FPGA_NR_IRQS 24
294#else
295#define OMAP_FPGA_NR_IRQS 0
296#endif
297#define OMAP_FPGA_IRQ_END (OMAP_FPGA_IRQ_BASE + OMAP_FPGA_NR_IRQS)
298
299/* External TWL4030 can handle interrupts on 2430 and 34xx boards */
300#define TWL4030_IRQ_BASE (OMAP_FPGA_IRQ_END)
301#ifdef CONFIG_TWL4030_CORE
302#define TWL4030_BASE_NR_IRQS 8
303#define TWL4030_PWR_NR_IRQS 8
304#else
305#define TWL4030_BASE_NR_IRQS 0
306#define TWL4030_PWR_NR_IRQS 0
307#endif
308#define TWL4030_IRQ_END (TWL4030_IRQ_BASE + TWL4030_BASE_NR_IRQS)
309#define TWL4030_PWR_IRQ_BASE TWL4030_IRQ_END
310#define TWL4030_PWR_IRQ_END (TWL4030_PWR_IRQ_BASE + TWL4030_PWR_NR_IRQS)
311
312/* External TWL4030 gpio interrupts are optional */
313#define TWL4030_GPIO_IRQ_BASE TWL4030_PWR_IRQ_END
314#ifdef CONFIG_TWL4030_GPIO
315#define TWL4030_GPIO_NR_IRQS 18
316#else
317#define TWL4030_GPIO_NR_IRQS 0
318#endif
319#define TWL4030_GPIO_IRQ_END (TWL4030_GPIO_IRQ_BASE + TWL4030_GPIO_NR_IRQS)
320
321/* Total number of interrupts depends on the enabled blocks above */
322#define NR_IRQS TWL4030_GPIO_IRQ_END
289 323
290#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32)) 324#define OMAP_IRQ_BIT(irq) (1 << ((irq) % 32))
291 325
@@ -293,14 +327,6 @@
293extern void omap_init_irq(void); 327extern void omap_init_irq(void);
294#endif 328#endif
295 329
296/*
297 * The definition of NR_IRQS is in board-specific header file, which is
298 * included via hardware.h
299 */
300#include <asm/hardware.h> 330#include <asm/hardware.h>
301 331
302#ifndef NR_IRQS
303#define NR_IRQS IH_BOARD_BASE
304#endif
305
306#endif 332#endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
index c7a0cc1c4e93..26c78f67dc8e 100644
--- a/include/asm-arm/arch-omap/mcbsp.h
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -24,7 +24,11 @@
24#ifndef __ASM_ARCH_OMAP_MCBSP_H 24#ifndef __ASM_ARCH_OMAP_MCBSP_H
25#define __ASM_ARCH_OMAP_MCBSP_H 25#define __ASM_ARCH_OMAP_MCBSP_H
26 26
27#include <linux/completion.h>
28#include <linux/spinlock.h>
29
27#include <asm/hardware.h> 30#include <asm/hardware.h>
31#include <asm/arch/clock.h>
28 32
29#define OMAP730_MCBSP1_BASE 0xfffb1000 33#define OMAP730_MCBSP1_BASE 0xfffb1000
30#define OMAP730_MCBSP2_BASE 0xfffb1800 34#define OMAP730_MCBSP2_BASE 0xfffb1800
@@ -40,6 +44,9 @@
40#define OMAP24XX_MCBSP1_BASE 0x48074000 44#define OMAP24XX_MCBSP1_BASE 0x48074000
41#define OMAP24XX_MCBSP2_BASE 0x48076000 45#define OMAP24XX_MCBSP2_BASE 0x48076000
42 46
47#define OMAP34XX_MCBSP1_BASE 0x48074000
48#define OMAP34XX_MCBSP2_BASE 0x49022000
49
43#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) 50#if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730)
44 51
45#define OMAP_MCBSP_REG_DRR2 0x00 52#define OMAP_MCBSP_REG_DRR2 0x00
@@ -74,7 +81,8 @@
74#define OMAP_MCBSP_REG_XCERG 0x3A 81#define OMAP_MCBSP_REG_XCERG 0x3A
75#define OMAP_MCBSP_REG_XCERH 0x3C 82#define OMAP_MCBSP_REG_XCERH 0x3C
76 83
77#define OMAP_MAX_MCBSP_COUNT 3 84#define OMAP_MAX_MCBSP_COUNT 3
85#define MAX_MCBSP_CLOCKS 3
78 86
79#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) 87#define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1)
80#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) 88#define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1)
@@ -117,7 +125,8 @@
117#define OMAP_MCBSP_REG_XCERG 0x74 125#define OMAP_MCBSP_REG_XCERG 0x74
118#define OMAP_MCBSP_REG_XCERH 0x78 126#define OMAP_MCBSP_REG_XCERH 0x78
119 127
120#define OMAP_MAX_MCBSP_COUNT 2 128#define OMAP_MAX_MCBSP_COUNT 2
129#define MAX_MCBSP_CLOCKS 2
121 130
122#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) 131#define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1)
123#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) 132#define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1)
@@ -298,6 +307,55 @@ struct omap_mcbsp_spi_cfg {
298 omap_mcbsp_word_length word_length; 307 omap_mcbsp_word_length word_length;
299}; 308};
300 309
310/* Platform specific configuration */
311struct omap_mcbsp_ops {
312 void (*request)(unsigned int);
313 void (*free)(unsigned int);
314 int (*check)(unsigned int);
315};
316
317struct omap_mcbsp_platform_data {
318 u32 virt_base;
319 u8 dma_rx_sync, dma_tx_sync;
320 u16 rx_irq, tx_irq;
321 struct omap_mcbsp_ops *ops;
322 char const *clk_name;
323};
324
325struct omap_mcbsp {
326 struct device *dev;
327 u32 io_base;
328 u8 id;
329 u8 free;
330 omap_mcbsp_word_length rx_word_length;
331 omap_mcbsp_word_length tx_word_length;
332
333 omap_mcbsp_io_type_t io_type; /* IRQ or poll */
334 /* IRQ based TX/RX */
335 int rx_irq;
336 int tx_irq;
337
338 /* DMA stuff */
339 u8 dma_rx_sync;
340 short dma_rx_lch;
341 u8 dma_tx_sync;
342 short dma_tx_lch;
343
344 /* Completion queues */
345 struct completion tx_irq_completion;
346 struct completion rx_irq_completion;
347 struct completion tx_dma_completion;
348 struct completion rx_dma_completion;
349
350 /* Protect the field .free, while checking if the mcbsp is in use */
351 spinlock_t lock;
352 struct omap_mcbsp_platform_data *pdata;
353 struct clk *clk;
354};
355
356int omap_mcbsp_init(void);
357void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config,
358 int size);
301void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); 359void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
302int omap_mcbsp_request(unsigned int id); 360int omap_mcbsp_request(unsigned int id);
303void omap_mcbsp_free(unsigned int id); 361void omap_mcbsp_free(unsigned int id);
diff --git a/include/asm-arm/arch-omap/omap34xx.h b/include/asm-arm/arch-omap/omap34xx.h
new file mode 100644
index 000000000000..aa30c6d10abd
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap34xx.h
@@ -0,0 +1,72 @@
1/*
2 * include/asm-arm/arch-omap/omap34xx.h
3 *
4 * This file contains the processor specific definitions of the TI OMAP34XX.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 * Copyright (C) 2007 Nokia Corporation.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24#ifndef __ASM_ARCH_OMAP34XX_H
25#define __ASM_ARCH_OMAP34XX_H
26
27/*
28 * Please place only base defines here and put the rest in device
29 * specific headers.
30 */
31
32#define L4_34XX_BASE 0x48000000
33#define L4_WK_34XX_BASE 0x48300000
34#define L4_WK_OMAP_BASE L4_WK_34XX_BASE
35#define L4_PER_34XX_BASE 0x49000000
36#define L4_PER_OMAP_BASE L4_PER_34XX_BASE
37#define L4_EMU_34XX_BASE 0x54000000
38#define L4_EMU_BASE L4_EMU_34XX_BASE
39#define L3_34XX_BASE 0x68000000
40#define L3_OMAP_BASE L3_34XX_BASE
41
42#define OMAP3430_32KSYNCT_BASE 0x48320000
43#define OMAP3430_CM_BASE 0x48004800
44#define OMAP3430_PRM_BASE 0x48306800
45#define OMAP343X_SMS_BASE 0x6C000000
46#define OMAP343X_SDRC_BASE 0x6D000000
47#define OMAP34XX_GPMC_BASE 0x6E000000
48#define OMAP343X_SCM_BASE 0x48002000
49#define OMAP343X_CTRL_BASE OMAP343X_SCM_BASE
50
51#define OMAP34XX_IC_BASE 0x48200000
52#define OMAP34XX_IVA_INTC_BASE 0x40000000
53#define OMAP34XX_HSUSB_OTG_BASE (L4_34XX_BASE + 0xAB000)
54#define OMAP34XX_HSUSB_HOST_BASE (L4_34XX_BASE + 0x64000)
55#define OMAP34XX_USBTLL_BASE (L4_34XX_BASE + 0x62000)
56
57
58#if defined(CONFIG_ARCH_OMAP3430)
59
60#define OMAP2_32KSYNCT_BASE OMAP3430_32KSYNCT_BASE
61#define OMAP2_CM_BASE OMAP3430_CM_BASE
62#define OMAP2_PRM_BASE OMAP3430_PRM_BASE
63#define OMAP2_VA_IC_BASE IO_ADDRESS(OMAP34XX_IC_BASE)
64
65#endif
66
67#define OMAP34XX_DSP_BASE 0x58000000
68#define OMAP34XX_DSP_MEM_BASE (OMAP34XX_DSP_BASE + 0x0)
69#define OMAP34XX_DSP_IPI_BASE (OMAP34XX_DSP_BASE + 0x1000000)
70#define OMAP34XX_DSP_MMU_BASE (OMAP34XX_DSP_BASE + 0x2000000)
71#endif /* __ASM_ARCH_OMAP34XX_H */
72
diff --git a/include/asm-arm/arch-omap/sram.h b/include/asm-arm/arch-omap/sram.h
index bb9bb3fd532f..be59f4a9828b 100644
--- a/include/asm-arm/arch-omap/sram.h
+++ b/include/asm-arm/arch-omap/sram.h
@@ -11,6 +11,7 @@
11#ifndef __ARCH_ARM_OMAP_SRAM_H 11#ifndef __ARCH_ARM_OMAP_SRAM_H
12#define __ARCH_ARM_OMAP_SRAM_H 12#define __ARCH_ARM_OMAP_SRAM_H
13 13
14extern int __init omap_sram_init(void);
14extern void * omap_sram_push(void * start, unsigned long size); 15extern void * omap_sram_push(void * start, unsigned long size);
15extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl); 16extern void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl);
16 17
@@ -21,17 +22,35 @@ extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
21extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 22extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
22 23
23/* Do not use these */ 24/* Do not use these */
24extern void sram_reprogram_clock(u32 ckctl, u32 dpllctl); 25extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
25extern unsigned long sram_reprogram_clock_sz; 26extern unsigned long omap1_sram_reprogram_clock_sz;
26 27
27extern void sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl, 28extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
28 u32 base_cs, u32 force_unlock); 29extern unsigned long omap24xx_sram_reprogram_clock_sz;
29extern unsigned long sram_ddr_init_sz;
30 30
31extern u32 sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass); 31extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
32extern unsigned long sram_set_prcm_sz; 32 u32 base_cs, u32 force_unlock);
33extern unsigned long omap242x_sram_ddr_init_sz;
33 34
34extern void sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type); 35extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
35extern unsigned long sram_reprogram_sdrc_sz; 36 int bypass);
37extern unsigned long omap242x_sram_set_prcm_sz;
38
39extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
40 u32 mem_type);
41extern unsigned long omap242x_sram_reprogram_sdrc_sz;
42
43
44extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
45 u32 base_cs, u32 force_unlock);
46extern unsigned long omap243x_sram_ddr_init_sz;
47
48extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
49 int bypass);
50extern unsigned long omap243x_sram_set_prcm_sz;
51
52extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
53 u32 mem_type);
54extern unsigned long omap243x_sram_reprogram_sdrc_sz;
36 55
37#endif 56#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
index 8ded218cbea5..65a9c82d3bf7 100644
--- a/include/asm-arm/arch-omap/tc.h
+++ b/include/asm-arm/arch-omap/tc.h
@@ -75,16 +75,14 @@
75#ifndef __ASSEMBLER__ 75#ifndef __ASSEMBLER__
76 76
77/* EMIF Slow Interface Configuration Register */ 77/* EMIF Slow Interface Configuration Register */
78#define OMAP_EMIFS_CONFIG_REG __REG32(EMIFS_CONFIG)
79
80#define OMAP_EMIFS_CONFIG_FR (1 << 4) 78#define OMAP_EMIFS_CONFIG_FR (1 << 4)
81#define OMAP_EMIFS_CONFIG_PDE (1 << 3) 79#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
82#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2) 80#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
83#define OMAP_EMIFS_CONFIG_BM (1 << 1) 81#define OMAP_EMIFS_CONFIG_BM (1 << 1)
84#define OMAP_EMIFS_CONFIG_WP (1 << 0) 82#define OMAP_EMIFS_CONFIG_WP (1 << 0)
85 83
86#define EMIFS_CCS(n) __REG32(EMIFS_CS0_CONFIG + (4 * (n))) 84#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
87#define EMIFS_ACS(n) __REG32(EMIFS_ACS0 + (4 * (n))) 85#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
88 86
89/* Almost all documentation for chip and board memory maps assumes 87/* Almost all documentation for chip and board memory maps assumes
90 * BM is clear. Most devel boards have a switch to control booting 88 * BM is clear. Most devel boards have a switch to control booting
@@ -93,13 +91,13 @@
93 */ 91 */
94static inline u32 omap_cs0_phys(void) 92static inline u32 omap_cs0_phys(void)
95{ 93{
96 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) 94 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
97 ? OMAP_CS3_PHYS : 0; 95 ? OMAP_CS3_PHYS : 0;
98} 96}
99 97
100static inline u32 omap_cs3_phys(void) 98static inline u32 omap_cs3_phys(void)
101{ 99{
102 return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM) 100 return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
103 ? 0 : OMAP_CS3_PHYS; 101 ? 0 : OMAP_CS3_PHYS;
104} 102}
105 103
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
index 2147d18aaeae..ddf1861e6df9 100644
--- a/include/asm-arm/arch-omap/usb.h
+++ b/include/asm-arm/arch-omap/usb.h
@@ -34,11 +34,8 @@
34/* 34/*
35 * OTG and transceiver registers, for OMAPs starting with ARM926 35 * OTG and transceiver registers, for OMAPs starting with ARM926
36 */ 36 */
37#define OTG_REG32(offset) __REG32(OTG_BASE + (offset)) 37#define OTG_REV (OTG_BASE + 0x00)
38#define OTG_REG16(offset) __REG16(OTG_BASE + (offset)) 38#define OTG_SYSCON_1 (OTG_BASE + 0x04)
39
40#define OTG_REV_REG OTG_REG32(0x00)
41#define OTG_SYSCON_1_REG OTG_REG32(0x04)
42# define USB2_TRX_MODE(w) (((w)>>24)&0x07) 39# define USB2_TRX_MODE(w) (((w)>>24)&0x07)
43# define USB1_TRX_MODE(w) (((w)>>20)&0x07) 40# define USB1_TRX_MODE(w) (((w)>>20)&0x07)
44# define USB0_TRX_MODE(w) (((w)>>16)&0x07) 41# define USB0_TRX_MODE(w) (((w)>>16)&0x07)
@@ -47,7 +44,7 @@
47# define DEV_IDLE_EN (1 << 13) 44# define DEV_IDLE_EN (1 << 13)
48# define OTG_RESET_DONE (1 << 2) 45# define OTG_RESET_DONE (1 << 2)
49# define OTG_SOFT_RESET (1 << 1) 46# define OTG_SOFT_RESET (1 << 1)
50#define OTG_SYSCON_2_REG OTG_REG32(0x08) 47#define OTG_SYSCON_2 (OTG_BASE + 0x08)
51# define OTG_EN (1 << 31) 48# define OTG_EN (1 << 31)
52# define USBX_SYNCHRO (1 << 30) 49# define USBX_SYNCHRO (1 << 30)
53# define OTG_MST16 (1 << 29) 50# define OTG_MST16 (1 << 29)
@@ -65,7 +62,7 @@
65# define HMC_TLLSPEED (1 << 7) 62# define HMC_TLLSPEED (1 << 7)
66# define HMC_TLLATTACH (1 << 6) 63# define HMC_TLLATTACH (1 << 6)
67# define OTG_HMC(w) (((w)>>0)&0x3f) 64# define OTG_HMC(w) (((w)>>0)&0x3f)
68#define OTG_CTRL_REG OTG_REG32(0x0c) 65#define OTG_CTRL (OTG_BASE + 0x0c)
69# define OTG_USB2_EN (1 << 29) 66# define OTG_USB2_EN (1 << 29)
70# define OTG_USB2_DP (1 << 28) 67# define OTG_USB2_DP (1 << 28)
71# define OTG_USB2_DM (1 << 27) 68# define OTG_USB2_DM (1 << 27)
@@ -92,7 +89,7 @@
92# define OTG_PD_VBUS (1 << 2) 89# define OTG_PD_VBUS (1 << 2)
93# define OTG_PU_VBUS (1 << 1) 90# define OTG_PU_VBUS (1 << 1)
94# define OTG_PU_ID (1 << 0) 91# define OTG_PU_ID (1 << 0)
95#define OTG_IRQ_EN_REG OTG_REG16(0x10) 92#define OTG_IRQ_EN (OTG_BASE + 0x10) /* 16-bit */
96# define DRIVER_SWITCH (1 << 15) 93# define DRIVER_SWITCH (1 << 15)
97# define A_VBUS_ERR (1 << 13) 94# define A_VBUS_ERR (1 << 13)
98# define A_REQ_TMROUT (1 << 12) 95# define A_REQ_TMROUT (1 << 12)
@@ -102,9 +99,9 @@
102# define B_SRP_DONE (1 << 8) 99# define B_SRP_DONE (1 << 8)
103# define B_SRP_STARTED (1 << 7) 100# define B_SRP_STARTED (1 << 7)
104# define OPRT_CHG (1 << 0) 101# define OPRT_CHG (1 << 0)
105#define OTG_IRQ_SRC_REG OTG_REG16(0x14) 102#define OTG_IRQ_SRC (OTG_BASE + 0x14) /* 16-bit */
106 // same bits as in IRQ_EN 103 // same bits as in IRQ_EN
107#define OTG_OUTCTRL_REG OTG_REG16(0x18) 104#define OTG_OUTCTRL (OTG_BASE + 0x18) /* 16-bit */
108# define OTGVPD (1 << 14) 105# define OTGVPD (1 << 14)
109# define OTGVPU (1 << 13) 106# define OTGVPU (1 << 13)
110# define OTGPUID (1 << 12) 107# define OTGPUID (1 << 12)
@@ -117,13 +114,13 @@
117# define USB0VDR (1 << 2) 114# define USB0VDR (1 << 2)
118# define USB0PDEN (1 << 1) 115# define USB0PDEN (1 << 1)
119# define USB0PUEN (1 << 0) 116# define USB0PUEN (1 << 0)
120#define OTG_TEST_REG OTG_REG16(0x20) 117#define OTG_TEST (OTG_BASE + 0x20) /* 16-bit */
121#define OTG_VENDOR_CODE_REG OTG_REG32(0xfc) 118#define OTG_VENDOR_CODE (OTG_BASE + 0xfc) /* 16-bit */
122 119
123/*-------------------------------------------------------------------------*/ 120/*-------------------------------------------------------------------------*/
124 121
125/* OMAP1 */ 122/* OMAP1 */
126#define USB_TRANSCEIVER_CTRL_REG __REG32(0xfffe1000 + 0x0064) 123#define USB_TRANSCEIVER_CTRL (0xfffe1000 + 0x0064)
127# define CONF_USB2_UNI_R (1 << 8) 124# define CONF_USB2_UNI_R (1 << 8)
128# define CONF_USB1_UNI_R (1 << 7) 125# define CONF_USB1_UNI_R (1 << 7)
129# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7) 126# define CONF_USB_PORT0_R(x) (((x)>>4)&0x7)
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
index 50f8c8802206..59f1bc96a23b 100644
--- a/include/asm-arm/arch-orion5x/io.h
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -14,7 +14,6 @@
14#include "orion5x.h" 14#include "orion5x.h"
15 15
16#define IO_SPACE_LIMIT 0xffffffff 16#define IO_SPACE_LIMIT 0xffffffff
17#define IO_SPACE_REMAP ORION5X_PCI_SYS_IO_BASE
18 17
19static inline void __iomem * 18static inline void __iomem *
20__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype) 19__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
@@ -53,15 +52,12 @@ static inline void __iomem *__io(unsigned long addr)
53/***************************************************************************** 52/*****************************************************************************
54 * Helpers to access Orion registers 53 * Helpers to access Orion registers
55 ****************************************************************************/ 54 ****************************************************************************/
56#define orion5x_read(r) __raw_readl(r)
57#define orion5x_write(r, val) __raw_writel(val, r)
58
59/* 55/*
60 * These are not preempt-safe. Locks, if needed, must be taken 56 * These are not preempt-safe. Locks, if needed, must be taken
61 * care of by the caller. 57 * care of by the caller.
62 */ 58 */
63#define orion5x_setbits(r, mask) orion5x_write((r), orion5x_read(r) | (mask)) 59#define orion5x_setbits(r, mask) writel(readl(r) | (mask), (r))
64#define orion5x_clrbits(r, mask) orion5x_write((r), orion5x_read(r) & ~(mask)) 60#define orion5x_clrbits(r, mask) writel(readl(r) & ~(mask), (r))
65 61
66 62
67#endif 63#endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
index 206ddd71e193..10257f5c5e9e 100644
--- a/include/asm-arm/arch-orion5x/orion5x.h
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -2,7 +2,7 @@
2 * include/asm-arm/arch-orion5x/orion5x.h 2 * include/asm-arm/arch-orion5x/orion5x.h
3 * 3 *
4 * Generic definitions of Orion SoC flavors: 4 * Generic definitions of Orion SoC flavors:
5 * Orion-1, Orion-NAS, Orion-VoIP, and Orion-2. 5 * Orion-1, Orion-VoIP, Orion-NAS, and Orion-2.
6 * 6 *
7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com> 7 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
8 * 8 *
@@ -63,9 +63,11 @@
63/******************************************************************************* 63/*******************************************************************************
64 * Supported Devices & Revisions 64 * Supported Devices & Revisions
65 ******************************************************************************/ 65 ******************************************************************************/
66/* Orion-1 (88F5181) */ 66/* Orion-1 (88F5181) and Orion-VoIP (88F5181L) */
67#define MV88F5181_DEV_ID 0x5181 67#define MV88F5181_DEV_ID 0x5181
68#define MV88F5181_REV_B1 3 68#define MV88F5181_REV_B1 3
69#define MV88F5181L_REV_A0 8
70#define MV88F5181L_REV_A1 9
69/* Orion-NAS (88F5182) */ 71/* Orion-NAS (88F5182) */
70#define MV88F5182_DEV_ID 0x5182 72#define MV88F5182_DEV_ID 0x5182
71#define MV88F5182_REV_A2 2 73#define MV88F5182_REV_A2 2
@@ -152,6 +154,7 @@
152#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114) 154#define BRIDGE_MASK ORION5X_BRIDGE_REG(0x114)
153#define BRIDGE_INT_TIMER0 0x0002 155#define BRIDGE_INT_TIMER0 0x0002
154#define BRIDGE_INT_TIMER1 0x0004 156#define BRIDGE_INT_TIMER1 0x0004
157#define BRIDGE_INT_TIMER1_CLR (~0x0004)
155#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200) 158#define MAIN_IRQ_CAUSE ORION5X_BRIDGE_REG(0x200)
156#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204) 159#define MAIN_IRQ_MASK ORION5X_BRIDGE_REG(0x204)
157 160
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
index 5c13d4fafb4e..7548cedf2d76 100644
--- a/include/asm-arm/arch-orion5x/uncompress.h
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -8,23 +8,38 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11#include <linux/serial_reg.h>
11#include <asm/arch/orion5x.h> 12#include <asm/arch/orion5x.h>
12 13
13#define MV_UART_THR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0)) 14#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
14#define MV_UART_LSR ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
15
16#define LSR_THRE 0x20
17 15
18static void putc(const char c) 16static void putc(const char c)
19{ 17{
20 int j = 0x1000; 18 unsigned char *base = SERIAL_BASE;
21 while (--j && !(*MV_UART_LSR & LSR_THRE)) 19 int i;
20
21 for (i = 0; i < 0x1000; i++) {
22 if (base[UART_LSR << 2] & UART_LSR_THRE)
23 break;
22 barrier(); 24 barrier();
23 *MV_UART_THR = c; 25 }
26
27 base[UART_TX << 2] = c;
24} 28}
25 29
26static void flush(void) 30static void flush(void)
27{ 31{
32 unsigned char *base = SERIAL_BASE;
33 unsigned char mask;
34 int i;
35
36 mask = UART_LSR_TEMT | UART_LSR_THRE;
37
38 for (i = 0; i < 0x1000; i++) {
39 if ((base[UART_LSR << 2] & mask) == mask)
40 break;
41 barrier();
42 }
28} 43}
29 44
30/* 45/*
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
index 52bbe3bc25e1..f82f96dd1053 100644
--- a/include/asm-arm/arch-pxa/audio.h
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -12,4 +12,6 @@ typedef struct {
12 void *priv; 12 void *priv;
13} pxa2xx_audio_ops_t; 13} pxa2xx_audio_ops_t;
14 14
15extern void pxa_set_ac97_info(pxa2xx_audio_ops_t *ops);
16
15#endif 17#endif
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e25558faa5a4..d9af6dabc899 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -192,15 +192,6 @@ extern int pxa_gpio_get_value(unsigned gpio);
192extern void pxa_gpio_set_value(unsigned gpio, int value); 192extern void pxa_gpio_set_value(unsigned gpio, int value);
193 193
194/* 194/*
195 * Routine to enable or disable CKEN
196 */
197static inline void __deprecated pxa_set_cken(int clock, int enable)
198{
199 extern void __pxa_set_cken(int clock, int enable);
200 __pxa_set_cken(clock, enable);
201}
202
203/*
204 * return current memory and LCD clock frequency in units of 10kHz 195 * return current memory and LCD clock frequency in units of 10kHz
205 */ 196 */
206extern unsigned int get_memclk_frequency_10khz(void); 197extern unsigned int get_memclk_frequency_10khz(void);
diff --git a/include/asm-arm/arch-pxa/irda.h b/include/asm-arm/arch-pxa/irda.h
index 99f4f423a8e1..0a50c3c763df 100644
--- a/include/asm-arm/arch-pxa/irda.h
+++ b/include/asm-arm/arch-pxa/irda.h
@@ -16,4 +16,8 @@ struct pxaficp_platform_data {
16 16
17extern void pxa_set_ficp_info(struct pxaficp_platform_data *info); 17extern void pxa_set_ficp_info(struct pxaficp_platform_data *info);
18 18
19#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x)
20void pxa2xx_transceiver_mode(struct device *dev, int mode);
21#endif
22
19#endif 23#endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 4b2ea1e95c57..dce9308626b7 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -600,418 +600,6 @@
600 600
601 601
602/* 602/*
603 * USB Device Controller
604 * PXA25x and PXA27x USB device controller registers are different.
605 */
606#if defined(CONFIG_PXA25x)
607
608#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
609#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
610#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
611
612#define UDCCR __REG(0x40600000) /* UDC Control Register */
613#define UDCCR_UDE (1 << 0) /* UDC enable */
614#define UDCCR_UDA (1 << 1) /* UDC active */
615#define UDCCR_RSM (1 << 2) /* Device resume */
616#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
617#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
618#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
619#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
620#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
621
622#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
623#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
624#define UDCCS0_IPR (1 << 1) /* IN packet ready */
625#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
626#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
627#define UDCCS0_SST (1 << 4) /* Sent stall */
628#define UDCCS0_FST (1 << 5) /* Force stall */
629#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
630#define UDCCS0_SA (1 << 7) /* Setup active */
631
632/* Bulk IN - Endpoint 1,6,11 */
633#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
634#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
635#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
636
637#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
638#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
639#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
640#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
641#define UDCCS_BI_SST (1 << 4) /* Sent stall */
642#define UDCCS_BI_FST (1 << 5) /* Force stall */
643#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
644
645/* Bulk OUT - Endpoint 2,7,12 */
646#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
647#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
648#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
649
650#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
651#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
652#define UDCCS_BO_DME (1 << 3) /* DMA enable */
653#define UDCCS_BO_SST (1 << 4) /* Sent stall */
654#define UDCCS_BO_FST (1 << 5) /* Force stall */
655#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
656#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
657
658/* Isochronous IN - Endpoint 3,8,13 */
659#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
660#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
661#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
662
663#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
664#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
665#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
666#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
667#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
668
669/* Isochronous OUT - Endpoint 4,9,14 */
670#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
671#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
672#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
673
674#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
675#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
676#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
677#define UDCCS_IO_DME (1 << 3) /* DMA enable */
678#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
679#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
680
681/* Interrupt IN - Endpoint 5,10,15 */
682#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
683#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
684#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
685
686#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
687#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
688#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
689#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
690#define UDCCS_INT_SST (1 << 4) /* Sent stall */
691#define UDCCS_INT_FST (1 << 5) /* Force stall */
692#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
693
694#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
695#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
696#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
697#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
698#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
699#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
700#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
701#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
702#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
703#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
704#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
705#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
706#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
707#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
708#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
709#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
710#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
711#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
712#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
713#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
714#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
715#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
716#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
717#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
718
719#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
720
721#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
722#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
723#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
724#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
725#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
726#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
727#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
728#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
729
730#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
731
732#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
733#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
734#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
735#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
736#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
737#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
738#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
739#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
740
741#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
742
743#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
744#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
745#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
746#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
747#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
748#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
749#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
750#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
751
752#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
753
754#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
755#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
756#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
757#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
758#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
759#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
760#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
761#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
762
763#elif defined(CONFIG_PXA27x)
764
765#define UDCCR __REG(0x40600000) /* UDC Control Register */
766#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
767#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
768 Protocol Port Support */
769#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
770 Support */
771#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
772 Enable */
773#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
774#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
775#define UDCCR_ACN_S 11
776#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
777#define UDCCR_AIN_S 8
778#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
779 Setting Number */
780#define UDCCR_AAISN_S 5
781#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
782 Configuration */
783#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
784 Error */
785#define UDCCR_UDR (1 << 2) /* UDC Resume */
786#define UDCCR_UDA (1 << 1) /* UDC Active */
787#define UDCCR_UDE (1 << 0) /* UDC Enable */
788
789#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
790#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
791#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
792#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
793
794#define UDC_INT_FIFOERROR (0x2)
795#define UDC_INT_PACKETCMP (0x1)
796
797#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
798#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
799#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
800#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
801#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
802#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
803
804#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
805#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
806#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
807#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
808#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
809#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
810#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
811#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
812
813#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
814#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
815#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
816#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
817 Rising Edge Interrupt Enable */
818#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
819 Falling Edge Interrupt Enable */
820#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
821 Interrupt Enable */
822#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
823 Interrupt Enable */
824#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
825 Interrupt Enable */
826#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
827 Interrupt Enable */
828#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
829 Interrupt Enable */
830#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
831 Interrupt Enable */
832#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
833 Edge Interrupt Enable */
834#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
835 Edge Interrupt Enable */
836#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
837 Interrupt Enable */
838#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
839 Interrupt Enable */
840
841#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
842
843#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
844#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
845#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
846#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
847#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
848#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
849#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
850#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
851#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
852#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
853#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
854#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
855#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
856#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
857
858#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
859#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
860#define UDCCSR0_SA (1 << 7) /* Setup Active */
861#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
862#define UDCCSR0_FST (1 << 5) /* Force Stall */
863#define UDCCSR0_SST (1 << 4) /* Sent Stall */
864#define UDCCSR0_DME (1 << 3) /* DMA Enable */
865#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
866#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
867#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
868
869#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
870#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
871#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
872#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
873#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
874#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
875#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
876#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
877#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
878#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
879#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
880#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
881#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
882#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
883#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
884#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
885#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
886#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
887#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
888#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
889#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
890#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
891#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
892
893#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
894#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
895#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
896#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
897#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
898#define UDCCSR_FST (1 << 5) /* Force STALL */
899#define UDCCSR_SST (1 << 4) /* Sent STALL */
900#define UDCCSR_DME (1 << 3) /* DMA Enable */
901#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
902#define UDCCSR_PC (1 << 1) /* Packet Complete */
903#define UDCCSR_FS (1 << 0) /* FIFO needs service */
904
905#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
906#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
907#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
908#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
909#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
910#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
911#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
912#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
913#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
914#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
915#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
916#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
917#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
918#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
919#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
920#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
921#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
922#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
923#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
924#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
925#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
926#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
927#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
928#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
929#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
930
931#define UDCDN(x) __REG2(0x40600300, (x)<<2)
932#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
933#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
934#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
935#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
936#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
937#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
938#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
939#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
940#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
941#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
942#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
943#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
944#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
945#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
946#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
947#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
948#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
949#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
950#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
951#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
952#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
953#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
954#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
955#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
956#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
957#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
958
959#define UDCCN(x) __REG2(0x40600400, (x)<<2)
960#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
961#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
962#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
963#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
964#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
965#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
966#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
967#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
968#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
969#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
970#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
971#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
972#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
973#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
974#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
975#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
976#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
977#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
978#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
979#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
980#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
981#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
982#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
983
984#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
985#define UDCCONR_CN_S (25)
986#define UDCCONR_IN (0x07 << 22) /* Interface Number */
987#define UDCCONR_IN_S (22)
988#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
989#define UDCCONR_AISN_S (19)
990#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
991#define UDCCONR_EN_S (15)
992#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
993#define UDCCONR_ET_S (13)
994#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
995#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
996#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
997#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
998#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
999#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
1000#define UDCCONR_MPS_S (2)
1001#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
1002#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
1003
1004
1005#define UDC_INT_FIFOERROR (0x2)
1006#define UDC_INT_PACKETCMP (0x1)
1007
1008#define UDC_FNR_MASK (0x7ff)
1009
1010#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
1011#define UDC_BCR_MASK (0x3ff)
1012#endif
1013
1014/*
1015 * Fast Infrared Communication Port 603 * Fast Infrared Communication Port
1016 */ 604 */
1017 605
@@ -1237,120 +825,9 @@
1237#endif 825#endif
1238 826
1239/* 827/*
1240 * Power Manager 828 * Power Manager - see pxa2xx-regs.h
1241 */ 829 */
1242 830
1243#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1244#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1245#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1246#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1247#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1248#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1249#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1250#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1251#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1252#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1253#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1254#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1255#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1256
1257#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1258#define PSTR __REG(0x40F00038) /*Power Manager Standby Config Register */
1259#define PSNR __REG(0x40F0003C) /*Power Manager Sense Config Register */
1260#define PVCR __REG(0x40F00040) /*Power Manager VoltageControl Register */
1261#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1262#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1263#define PCMD(x) __REG2(0x40F00080, (x)<<2)
1264#define PCMD0 __REG(0x40F00080 + 0 * 4)
1265#define PCMD1 __REG(0x40F00080 + 1 * 4)
1266#define PCMD2 __REG(0x40F00080 + 2 * 4)
1267#define PCMD3 __REG(0x40F00080 + 3 * 4)
1268#define PCMD4 __REG(0x40F00080 + 4 * 4)
1269#define PCMD5 __REG(0x40F00080 + 5 * 4)
1270#define PCMD6 __REG(0x40F00080 + 6 * 4)
1271#define PCMD7 __REG(0x40F00080 + 7 * 4)
1272#define PCMD8 __REG(0x40F00080 + 8 * 4)
1273#define PCMD9 __REG(0x40F00080 + 9 * 4)
1274#define PCMD10 __REG(0x40F00080 + 10 * 4)
1275#define PCMD11 __REG(0x40F00080 + 11 * 4)
1276#define PCMD12 __REG(0x40F00080 + 12 * 4)
1277#define PCMD13 __REG(0x40F00080 + 13 * 4)
1278#define PCMD14 __REG(0x40F00080 + 14 * 4)
1279#define PCMD15 __REG(0x40F00080 + 15 * 4)
1280#define PCMD16 __REG(0x40F00080 + 16 * 4)
1281#define PCMD17 __REG(0x40F00080 + 17 * 4)
1282#define PCMD18 __REG(0x40F00080 + 18 * 4)
1283#define PCMD19 __REG(0x40F00080 + 19 * 4)
1284#define PCMD20 __REG(0x40F00080 + 20 * 4)
1285#define PCMD21 __REG(0x40F00080 + 21 * 4)
1286#define PCMD22 __REG(0x40F00080 + 22 * 4)
1287#define PCMD23 __REG(0x40F00080 + 23 * 4)
1288#define PCMD24 __REG(0x40F00080 + 24 * 4)
1289#define PCMD25 __REG(0x40F00080 + 25 * 4)
1290#define PCMD26 __REG(0x40F00080 + 26 * 4)
1291#define PCMD27 __REG(0x40F00080 + 27 * 4)
1292#define PCMD28 __REG(0x40F00080 + 28 * 4)
1293#define PCMD29 __REG(0x40F00080 + 29 * 4)
1294#define PCMD30 __REG(0x40F00080 + 30 * 4)
1295#define PCMD31 __REG(0x40F00080 + 31 * 4)
1296
1297#define PCMD_MBC (1<<12)
1298#define PCMD_DCE (1<<11)
1299#define PCMD_LC (1<<10)
1300/* FIXME: PCMD_SQC need be checked. */
1301#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
1302 bit 9 should be 0 all day. */
1303#define PVCR_VCSA (0x1<<14)
1304#define PVCR_CommandDelay (0xf80)
1305#define PCFR_PI2C_EN (0x1 << 6)
1306
1307#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1308#define PSSR_RDH (1 << 5) /* Read Disable Hold */
1309#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1310#define PSSR_STS (1 << 3) /* Standby Mode Status */
1311#define PSSR_VFS (1 << 2) /* VDD Fault Status */
1312#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1313#define PSSR_SSS (1 << 0) /* Software Sleep Status */
1314
1315#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
1316
1317#define PCFR_RO (1 << 15) /* RDH Override */
1318#define PCFR_PO (1 << 14) /* PH Override */
1319#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
1320#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
1321#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1322#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1323#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1324#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
1325#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1326#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1327#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1328#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1329
1330#define RCSR_GPR (1 << 3) /* GPIO Reset */
1331#define RCSR_SMR (1 << 2) /* Sleep Mode */
1332#define RCSR_WDR (1 << 1) /* Watchdog Reset */
1333#define RCSR_HWR (1 << 0) /* Hardware Reset */
1334
1335#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
1336#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
1337#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
1338#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
1339#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
1340#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
1341#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
1342#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
1343#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
1344#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
1345#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
1346#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
1347#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
1348#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
1349#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
1350#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
1351#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
1352#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
1353
1354/* 831/*
1355 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h 832 * SSP Serial Port Registers - see include/asm-arm/arch-pxa/regs-ssp.h
1356 */ 833 */
@@ -1360,52 +837,9 @@
1360 */ 837 */
1361 838
1362/* 839/*
1363 * Core Clock 840 * Core Clock - see include/asm-arm/arch-pxa/pxa2xx-regs.h
1364 */ 841 */
1365 842
1366#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1367#define CKEN __REG(0x41300004) /* Clock Enable Register */
1368#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1369#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
1370
1371#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1372#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1373#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1374
1375#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
1376#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
1377#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
1378#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
1379#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
1380#define CKEN_IM (20) /* Internal Memory Clock Enable */
1381#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
1382#define CKEN_USIM (18) /* USIM Unit Clock Enable */
1383#define CKEN_MSL (17) /* MSL Unit Clock Enable */
1384#define CKEN_LCD (16) /* LCD Unit Clock Enable */
1385#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
1386#define CKEN_I2C (14) /* I2C Unit Clock Enable */
1387#define CKEN_FICP (13) /* FICP Unit Clock Enable */
1388#define CKEN_MMC (12) /* MMC Unit Clock Enable */
1389#define CKEN_USB (11) /* USB Unit Clock Enable */
1390#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
1391#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
1392#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
1393#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
1394#define CKEN_I2S (8) /* I2S Unit Clock Enable */
1395#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
1396#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
1397#define CKEN_STUART (5) /* STUART Unit Clock Enable */
1398#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
1399#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
1400#define CKEN_SSP (3) /* SSP Unit Clock Enable */
1401#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
1402#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
1403#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
1404#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
1405
1406#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1407#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1408
1409#ifdef CONFIG_PXA27x 843#ifdef CONFIG_PXA27x
1410 844
1411/* Camera Interface */ 845/* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxa25x-udc.h b/include/asm-arm/arch-pxa/pxa25x-udc.h
new file mode 100644
index 000000000000..840305916b6d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa25x-udc.h
@@ -0,0 +1,163 @@
1#ifndef _ASM_ARCH_PXA25X_UDC_H
2#define _ASM_ARCH_PXA25X_UDC_H
3
4#ifdef _ASM_ARCH_PXA27X_UDC_H
5#error You can't include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */
9#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */
10#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */
11
12#define UDCCR __REG(0x40600000) /* UDC Control Register */
13#define UDCCR_UDE (1 << 0) /* UDC enable */
14#define UDCCR_UDA (1 << 1) /* UDC active */
15#define UDCCR_RSM (1 << 2) /* Device resume */
16#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
17#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
18#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
19#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
20#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
21
22#define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */
23#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
24#define UDCCS0_IPR (1 << 1) /* IN packet ready */
25#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
26#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
27#define UDCCS0_SST (1 << 4) /* Sent stall */
28#define UDCCS0_FST (1 << 5) /* Force stall */
29#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
30#define UDCCS0_SA (1 << 7) /* Setup active */
31
32/* Bulk IN - Endpoint 1,6,11 */
33#define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */
34#define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
35#define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
36
37#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
38#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
39#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
40#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
41#define UDCCS_BI_SST (1 << 4) /* Sent stall */
42#define UDCCS_BI_FST (1 << 5) /* Force stall */
43#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
44
45/* Bulk OUT - Endpoint 2,7,12 */
46#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */
47#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
48#define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
49
50#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
51#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
52#define UDCCS_BO_DME (1 << 3) /* DMA enable */
53#define UDCCS_BO_SST (1 << 4) /* Sent stall */
54#define UDCCS_BO_FST (1 << 5) /* Force stall */
55#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
56#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
57
58/* Isochronous IN - Endpoint 3,8,13 */
59#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
60#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
61#define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
62
63#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
64#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
65#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
66#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
67#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
68
69/* Isochronous OUT - Endpoint 4,9,14 */
70#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
71#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
72#define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
73
74#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
75#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
76#define UDCCS_IO_ROF (1 << 2) /* Receive overflow */
77#define UDCCS_IO_DME (1 << 3) /* DMA enable */
78#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
79#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
80
81/* Interrupt IN - Endpoint 5,10,15 */
82#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
83#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
84#define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
85
86#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
87#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
88#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
89#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
90#define UDCCS_INT_SST (1 << 4) /* Sent stall */
91#define UDCCS_INT_FST (1 << 5) /* Force stall */
92#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
93
94#define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
95#define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */
96#define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */
97#define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
98#define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
99#define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
100#define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
101#define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
102#define UDDR0 __REG(0x40600080) /* UDC Endpoint 0 Data Register */
103#define UDDR1 __REG(0x40600100) /* UDC Endpoint 1 Data Register */
104#define UDDR2 __REG(0x40600180) /* UDC Endpoint 2 Data Register */
105#define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
106#define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
107#define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
108#define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
109#define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
110#define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
111#define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
112#define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
113#define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
114#define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
115#define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
116#define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
117#define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
118
119#define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */
120
121#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
122#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
123#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
124#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
125#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
126#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
127#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
128#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
129
130#define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */
131
132#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
133#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
134#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
135#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
136#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
137#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
138#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
139#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
140
141#define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */
142
143#define USIR0_IR0 (1 << 0) /* Interrupt request ep 0 */
144#define USIR0_IR1 (1 << 1) /* Interrupt request ep 1 */
145#define USIR0_IR2 (1 << 2) /* Interrupt request ep 2 */
146#define USIR0_IR3 (1 << 3) /* Interrupt request ep 3 */
147#define USIR0_IR4 (1 << 4) /* Interrupt request ep 4 */
148#define USIR0_IR5 (1 << 5) /* Interrupt request ep 5 */
149#define USIR0_IR6 (1 << 6) /* Interrupt request ep 6 */
150#define USIR0_IR7 (1 << 7) /* Interrupt request ep 7 */
151
152#define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */
153
154#define USIR1_IR8 (1 << 0) /* Interrupt request ep 8 */
155#define USIR1_IR9 (1 << 1) /* Interrupt request ep 9 */
156#define USIR1_IR10 (1 << 2) /* Interrupt request ep 10 */
157#define USIR1_IR11 (1 << 3) /* Interrupt request ep 11 */
158#define USIR1_IR12 (1 << 4) /* Interrupt request ep 12 */
159#define USIR1_IR13 (1 << 5) /* Interrupt request ep 13 */
160#define USIR1_IR14 (1 << 6) /* Interrupt request ep 14 */
161#define USIR1_IR15 (1 << 7) /* Interrupt request ep 15 */
162
163#endif
diff --git a/include/asm-arm/arch-pxa/pxa27x-udc.h b/include/asm-arm/arch-pxa/pxa27x-udc.h
new file mode 100644
index 000000000000..bc1cf7d0773a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa27x-udc.h
@@ -0,0 +1,257 @@
1#ifndef _ASM_ARCH_PXA27X_UDC_H
2#define _ASM_ARCH_PXA27X_UDC_H
3
4#ifdef _ASM_ARCH_PXA25X_UDC_H
5#error You cannot include both PXA25x and PXA27x UDC support
6#endif
7
8#define UDCCR __REG(0x40600000) /* UDC Control Register */
9#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
10#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
11 Protocol Port Support */
12#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
13 Support */
14#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
15 Enable */
16#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
17#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
18#define UDCCR_ACN_S 11
19#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
20#define UDCCR_AIN_S 8
21#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
22 Setting Number */
23#define UDCCR_AAISN_S 5
24#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
25 Configuration */
26#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
27 Error */
28#define UDCCR_UDR (1 << 2) /* UDC Resume */
29#define UDCCR_UDA (1 << 1) /* UDC Active */
30#define UDCCR_UDE (1 << 0) /* UDC Enable */
31
32#define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
33#define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
34#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
35#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
36
37#define UDC_INT_FIFOERROR (0x2)
38#define UDC_INT_PACKETCMP (0x1)
39
40#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
41#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
42#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
43#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
44#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
45#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
46
47#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
48#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
49#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
50#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
51#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
52#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
53#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
54#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
55
56#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
57#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
58#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
59#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
60 Rising Edge Interrupt Enable */
61#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
62 Falling Edge Interrupt Enable */
63#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
64 Interrupt Enable */
65#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
66 Interrupt Enable */
67#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
68 Interrupt Enable */
69#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
70 Interrupt Enable */
71#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
72 Interrupt Enable */
73#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
74 Interrupt Enable */
75#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
76 Edge Interrupt Enable */
77#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
78 Edge Interrupt Enable */
79#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
80 Interrupt Enable */
81#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
82 Interrupt Enable */
83
84#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
85#define UP3OCR __REG(0x40600024) /* USB Port 2 Output Control register */
86
87#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
88#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
89#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
90#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
91#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
92#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
93#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
94#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
95#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
96#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
97#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
98#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
99#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
100#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
101
102#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
103#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
104#define UDCCSR0_SA (1 << 7) /* Setup Active */
105#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
106#define UDCCSR0_FST (1 << 5) /* Force Stall */
107#define UDCCSR0_SST (1 << 4) /* Sent Stall */
108#define UDCCSR0_DME (1 << 3) /* DMA Enable */
109#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
110#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
111#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
112
113#define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
114#define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
115#define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
116#define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
117#define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
118#define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
119#define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
120#define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
121#define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
122#define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
123#define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
124#define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
125#define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
126#define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
127#define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
128#define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
129#define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
130#define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
131#define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
132#define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
133#define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
134#define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
135#define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
136
137#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
138#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
139#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
140#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
141#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
142#define UDCCSR_FST (1 << 5) /* Force STALL */
143#define UDCCSR_SST (1 << 4) /* Sent STALL */
144#define UDCCSR_DME (1 << 3) /* DMA Enable */
145#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
146#define UDCCSR_PC (1 << 1) /* Packet Complete */
147#define UDCCSR_FS (1 << 0) /* FIFO needs service */
148
149#define UDCBCN(x) __REG2(0x40600200, (x)<<2)
150#define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
151#define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
152#define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
153#define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
154#define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
155#define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
156#define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
157#define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
158#define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
159#define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
160#define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
161#define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
162#define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
163#define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
164#define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
165#define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
166#define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
167#define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
168#define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
169#define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
170#define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
171#define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
172#define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
173#define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
174
175#define UDCDN(x) __REG2(0x40600300, (x)<<2)
176#define PHYS_UDCDN(x) (0x40600300 + ((x)<<2))
177#define PUDCDN(x) (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
178#define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
179#define UDCDRA __REG(0x40600304) /* Data Register - EPA */
180#define UDCDRB __REG(0x40600308) /* Data Register - EPB */
181#define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
182#define UDCDRD __REG(0x40600310) /* Data Register - EPD */
183#define UDCDRE __REG(0x40600314) /* Data Register - EPE */
184#define UDCDRF __REG(0x40600318) /* Data Register - EPF */
185#define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
186#define UDCDRH __REG(0x40600320) /* Data Register - EPH */
187#define UDCDRI __REG(0x40600324) /* Data Register - EPI */
188#define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
189#define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
190#define UDCDRL __REG(0x40600330) /* Data Register - EPL */
191#define UDCDRM __REG(0x40600334) /* Data Register - EPM */
192#define UDCDRN __REG(0x40600338) /* Data Register - EPN */
193#define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
194#define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
195#define UDCDRR __REG(0x40600344) /* Data Register - EPR */
196#define UDCDRS __REG(0x40600348) /* Data Register - EPS */
197#define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
198#define UDCDRU __REG(0x40600350) /* Data Register - EPU */
199#define UDCDRV __REG(0x40600354) /* Data Register - EPV */
200#define UDCDRW __REG(0x40600358) /* Data Register - EPW */
201#define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
202
203#define UDCCN(x) __REG2(0x40600400, (x)<<2)
204#define UDCCRA __REG(0x40600404) /* Configuration register EPA */
205#define UDCCRB __REG(0x40600408) /* Configuration register EPB */
206#define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
207#define UDCCRD __REG(0x40600410) /* Configuration register EPD */
208#define UDCCRE __REG(0x40600414) /* Configuration register EPE */
209#define UDCCRF __REG(0x40600418) /* Configuration register EPF */
210#define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
211#define UDCCRH __REG(0x40600420) /* Configuration register EPH */
212#define UDCCRI __REG(0x40600424) /* Configuration register EPI */
213#define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
214#define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
215#define UDCCRL __REG(0x40600430) /* Configuration register EPL */
216#define UDCCRM __REG(0x40600434) /* Configuration register EPM */
217#define UDCCRN __REG(0x40600438) /* Configuration register EPN */
218#define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
219#define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
220#define UDCCRR __REG(0x40600444) /* Configuration register EPR */
221#define UDCCRS __REG(0x40600448) /* Configuration register EPS */
222#define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
223#define UDCCRU __REG(0x40600450) /* Configuration register EPU */
224#define UDCCRV __REG(0x40600454) /* Configuration register EPV */
225#define UDCCRW __REG(0x40600458) /* Configuration register EPW */
226#define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
227
228#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
229#define UDCCONR_CN_S (25)
230#define UDCCONR_IN (0x07 << 22) /* Interface Number */
231#define UDCCONR_IN_S (22)
232#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
233#define UDCCONR_AISN_S (19)
234#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
235#define UDCCONR_EN_S (15)
236#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
237#define UDCCONR_ET_S (13)
238#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
239#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
240#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
241#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
242#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
243#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
244#define UDCCONR_MPS_S (2)
245#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
246#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
247
248
249#define UDC_INT_FIFOERROR (0x2)
250#define UDC_INT_PACKETCMP (0x1)
251
252#define UDC_FNR_MASK (0x7ff)
253
254#define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
255#define UDC_BCR_MASK (0x3ff)
256
257#endif
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
index b81cd63cb2eb..6ef1dd09970b 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-gpio.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_ARCH_PXA2XX_GPIO_H 1#ifndef __ASM_ARCH_PXA2XX_GPIO_H
2#define __ASM_ARCH_PXA2XX_GPIO_H 2#define __ASM_ARCH_PXA2XX_GPIO_H
3 3
4#warning Please use mfp-pxa2[57]x.h instead of pxa2xx-gpio.h
5
4/* GPIO alternate function assignments */ 6/* GPIO alternate function assignments */
5 7
6#define GPIO1_RST 1 /* reset */ 8#define GPIO1_RST 1 /* reset */
diff --git a/include/asm-arm/arch-pxa/pxa2xx-regs.h b/include/asm-arm/arch-pxa/pxa2xx-regs.h
index 9553b54fa5bc..73e0a329cf7f 100644
--- a/include/asm-arm/arch-pxa/pxa2xx-regs.h
+++ b/include/asm-arm/arch-pxa/pxa2xx-regs.h
@@ -81,4 +81,166 @@
81 81
82#endif 82#endif
83 83
84
85/*
86 * Power Manager
87 */
88
89#define PMCR __REG(0x40F00000) /* Power Manager Control Register */
90#define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
91#define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
92#define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
93#define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
94#define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
95#define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
96#define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
97#define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
98#define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
99#define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
100#define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
101#define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
102
103#define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
104#define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
105#define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
106#define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
107#define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
108#define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
109#define PCMD(x) __REG2(0x40F00080, (x)<<2)
110#define PCMD0 __REG(0x40F00080 + 0 * 4)
111#define PCMD1 __REG(0x40F00080 + 1 * 4)
112#define PCMD2 __REG(0x40F00080 + 2 * 4)
113#define PCMD3 __REG(0x40F00080 + 3 * 4)
114#define PCMD4 __REG(0x40F00080 + 4 * 4)
115#define PCMD5 __REG(0x40F00080 + 5 * 4)
116#define PCMD6 __REG(0x40F00080 + 6 * 4)
117#define PCMD7 __REG(0x40F00080 + 7 * 4)
118#define PCMD8 __REG(0x40F00080 + 8 * 4)
119#define PCMD9 __REG(0x40F00080 + 9 * 4)
120#define PCMD10 __REG(0x40F00080 + 10 * 4)
121#define PCMD11 __REG(0x40F00080 + 11 * 4)
122#define PCMD12 __REG(0x40F00080 + 12 * 4)
123#define PCMD13 __REG(0x40F00080 + 13 * 4)
124#define PCMD14 __REG(0x40F00080 + 14 * 4)
125#define PCMD15 __REG(0x40F00080 + 15 * 4)
126#define PCMD16 __REG(0x40F00080 + 16 * 4)
127#define PCMD17 __REG(0x40F00080 + 17 * 4)
128#define PCMD18 __REG(0x40F00080 + 18 * 4)
129#define PCMD19 __REG(0x40F00080 + 19 * 4)
130#define PCMD20 __REG(0x40F00080 + 20 * 4)
131#define PCMD21 __REG(0x40F00080 + 21 * 4)
132#define PCMD22 __REG(0x40F00080 + 22 * 4)
133#define PCMD23 __REG(0x40F00080 + 23 * 4)
134#define PCMD24 __REG(0x40F00080 + 24 * 4)
135#define PCMD25 __REG(0x40F00080 + 25 * 4)
136#define PCMD26 __REG(0x40F00080 + 26 * 4)
137#define PCMD27 __REG(0x40F00080 + 27 * 4)
138#define PCMD28 __REG(0x40F00080 + 28 * 4)
139#define PCMD29 __REG(0x40F00080 + 29 * 4)
140#define PCMD30 __REG(0x40F00080 + 30 * 4)
141#define PCMD31 __REG(0x40F00080 + 31 * 4)
142
143#define PCMD_MBC (1<<12)
144#define PCMD_DCE (1<<11)
145#define PCMD_LC (1<<10)
146/* FIXME: PCMD_SQC need be checked. */
147#define PCMD_SQC (3<<8) /* currently only bit 8 is changeable,
148 bit 9 should be 0 all day. */
149#define PVCR_VCSA (0x1<<14)
150#define PVCR_CommandDelay (0xf80)
151#define PCFR_PI2C_EN (0x1 << 6)
152
153#define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
154#define PSSR_RDH (1 << 5) /* Read Disable Hold */
155#define PSSR_PH (1 << 4) /* Peripheral Control Hold */
156#define PSSR_STS (1 << 3) /* Standby Mode Status */
157#define PSSR_VFS (1 << 2) /* VDD Fault Status */
158#define PSSR_BFS (1 << 1) /* Battery Fault Status */
159#define PSSR_SSS (1 << 0) /* Software Sleep Status */
160
161#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
162
163#define PCFR_RO (1 << 15) /* RDH Override */
164#define PCFR_PO (1 << 14) /* PH Override */
165#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
166#define PCFR_L1_EN (1 << 11) /* Sleep Mode L1 converter Enable */
167#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
168#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
169#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
170#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
171#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
172#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
173#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
174#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
175
176#define RCSR_GPR (1 << 3) /* GPIO Reset */
177#define RCSR_SMR (1 << 2) /* Sleep Mode */
178#define RCSR_WDR (1 << 1) /* Watchdog Reset */
179#define RCSR_HWR (1 << 0) /* Hardware Reset */
180
181#define PWER_GPIO(Nb) (1 << Nb) /* GPIO [0..15] wake-up enable */
182#define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
183#define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
184#define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
185#define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
186#define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
187#define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
188#define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
189#define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
190#define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
191#define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
192#define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
193#define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
194#define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
195#define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
196#define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
197#define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
198#define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
199
200/*
201 * PXA2xx specific Core clock definitions
202 */
203#define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
204#define CCSR __REG(0x4130000C) /* Core Clock Status Register */
205#define CKEN __REG(0x41300004) /* Clock Enable Register */
206#define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
207
208#define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
209#define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
210#define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
211
212#define CKEN_AC97CONF (31) /* AC97 Controller Configuration */
213#define CKEN_CAMERA (24) /* Camera Interface Clock Enable */
214#define CKEN_SSP1 (23) /* SSP1 Unit Clock Enable */
215#define CKEN_MEMC (22) /* Memory Controller Clock Enable */
216#define CKEN_MEMSTK (21) /* Memory Stick Host Controller */
217#define CKEN_IM (20) /* Internal Memory Clock Enable */
218#define CKEN_KEYPAD (19) /* Keypad Interface Clock Enable */
219#define CKEN_USIM (18) /* USIM Unit Clock Enable */
220#define CKEN_MSL (17) /* MSL Unit Clock Enable */
221#define CKEN_LCD (16) /* LCD Unit Clock Enable */
222#define CKEN_PWRI2C (15) /* PWR I2C Unit Clock Enable */
223#define CKEN_I2C (14) /* I2C Unit Clock Enable */
224#define CKEN_FICP (13) /* FICP Unit Clock Enable */
225#define CKEN_MMC (12) /* MMC Unit Clock Enable */
226#define CKEN_USB (11) /* USB Unit Clock Enable */
227#define CKEN_ASSP (10) /* ASSP (SSP3) Clock Enable */
228#define CKEN_USBHOST (10) /* USB Host Unit Clock Enable */
229#define CKEN_OSTIMER (9) /* OS Timer Unit Clock Enable */
230#define CKEN_NSSP (9) /* NSSP (SSP2) Clock Enable */
231#define CKEN_I2S (8) /* I2S Unit Clock Enable */
232#define CKEN_BTUART (7) /* BTUART Unit Clock Enable */
233#define CKEN_FFUART (6) /* FFUART Unit Clock Enable */
234#define CKEN_STUART (5) /* STUART Unit Clock Enable */
235#define CKEN_HWUART (4) /* HWUART Unit Clock Enable */
236#define CKEN_SSP3 (4) /* SSP3 Unit Clock Enable */
237#define CKEN_SSP (3) /* SSP Unit Clock Enable */
238#define CKEN_SSP2 (3) /* SSP2 Unit Clock Enable */
239#define CKEN_AC97 (2) /* AC97 Unit Clock Enable */
240#define CKEN_PWM1 (1) /* PWM1 Clock Enable */
241#define CKEN_PWM0 (0) /* PWM0 Clock Enable */
242
243#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
244#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
245
84#endif 246#endif
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
index 9aa6c2e939e8..ba7e132de1b3 100644
--- a/include/asm-arm/arch-pxa/system.h
+++ b/include/asm-arm/arch-pxa/system.h
@@ -12,6 +12,7 @@
12 12
13#include <asm/proc-fns.h> 13#include <asm/proc-fns.h>
14#include "hardware.h" 14#include "hardware.h"
15#include "pxa2xx-regs.h"
15#include "pxa-regs.h" 16#include "pxa-regs.h"
16 17
17static inline void arch_idle(void) 18static inline void arch_idle(void)
diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h
index 4881b80f0f90..de577de8d18c 100644
--- a/include/asm-arm/arch-pxa/zylonite.h
+++ b/include/asm-arm/arch-pxa/zylonite.h
@@ -15,7 +15,6 @@ struct platform_mmc_slot {
15 15
16extern struct platform_mmc_slot zylonite_mmc_slot[]; 16extern struct platform_mmc_slot zylonite_mmc_slot[];
17 17
18extern int gpio_backlight;
19extern int gpio_eth_irq; 18extern int gpio_eth_irq;
20 19
21extern int wm9713_irq; 20extern int wm9713_irq;
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
index b4da08d7a336..6bd2295c0e01 100644
--- a/include/asm-arm/arch-rpc/io.h
+++ b/include/asm-arm/arch-rpc/io.h
@@ -126,7 +126,7 @@ static inline unsigned sz __in##fnsuffix (unsigned int port) \
126 return (unsigned sz)value; \ 126 return (unsigned sz)value; \
127} 127}
128 128
129static inline void __iomem *__ioaddr(unsigned int port) 129static inline void __iomem *__deprecated __ioaddr(unsigned int port)
130{ 130{
131 void __iomem *ret; 131 void __iomem *ret;
132 if (__PORT_PCIO(port)) 132 if (__PORT_PCIO(port))
@@ -232,8 +232,7 @@ DECLARE_IO(int,l,"")
232 result; \ 232 result; \
233}) 233})
234 234
235#define __ioaddrc(port) \ 235#define __ioaddrc(port) __ioaddr(port)
236 ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2))
237 236
238#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p)) 237#define inb(p) (__builtin_constant_p((p)) ? __inbc(p) : __inb(p))
239#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p)) 238#define inw(p) (__builtin_constant_p((p)) ? __inwc(p) : __inw(p))
diff --git a/include/asm-arm/arch-s3c2410/gpio.h b/include/asm-arm/arch-s3c2410/gpio.h
index 7583895fd336..18e10d2c35ea 100644
--- a/include/asm-arm/arch-s3c2410/gpio.h
+++ b/include/asm-arm/arch-s3c2410/gpio.h
@@ -1,68 +1,18 @@
1/* 1/* linux/include/asm-arm/arch-s3c2410/gpio.h
2 * linux/include/asm-arm/arch-s3c2410/gpio.h
3 * 2 *
4 * S3C2410 GPIO wrappers for arch-neutral GPIO calls 3 * Copyright (c) 2008 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
5 * 6 *
6 * Written by Philipp Zabel <philipp.zabel@gmail.com> 7 * S3C2410 - GPIO lib support
7 * 8 *
8 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by 10 * it under the terms of the GNU General Public License version 2 as
10 * the Free Software Foundation; either version 2 of the License, or 11 * published by the Free Software Foundation.
11 * (at your option) any later version. 12*/
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24#ifndef __ASM_ARCH_S3C2410_GPIO_H
25#define __ASM_ARCH_S3C2410_GPIO_H
26
27#include <asm/irq.h>
28#include <asm/hardware.h>
29#include <asm/arch/regs-gpio.h>
30
31static inline int gpio_request(unsigned gpio, const char *label)
32{
33 return 0;
34}
35
36static inline void gpio_free(unsigned gpio)
37{
38 return;
39}
40
41static inline int gpio_direction_input(unsigned gpio)
42{
43 s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_INPUT);
44 return 0;
45}
46
47static inline int gpio_direction_output(unsigned gpio, int value)
48{
49 s3c2410_gpio_cfgpin(gpio, S3C2410_GPIO_OUTPUT);
50 /* REVISIT can we write the value first, to avoid glitching? */
51 s3c2410_gpio_setpin(gpio, value);
52 return 0;
53}
54
55#define gpio_get_value(gpio) s3c2410_gpio_getpin(gpio)
56#define gpio_set_value(gpio,value) s3c2410_gpio_setpin(gpio, value)
57
58#include <asm-generic/gpio.h> /* cansleep wrappers */
59
60#ifdef CONFIG_CPU_S3C2400
61#define gpio_to_irq(gpio) s3c2400_gpio_getirq(gpio)
62#else
63#define gpio_to_irq(gpio) s3c2410_gpio_getirq(gpio)
64#endif
65 13
66/* FIXME implement irq_to_gpio() */ 14#define gpio_get_value __gpio_get_value
15#define gpio_set_value __gpio_set_value
16#define gpio_cansleep __gpio_cansleep
67 17
68#endif 18#include <asm-generic/gpio.h>
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index ecae9e7f5e45..37661358b42b 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -189,6 +189,8 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
189#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9) 189#define S3C2412_CLKSRC_I2SCLK_MPLL (1<<9)
190#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10) 190#define S3C2412_CLKSRC_USBCLK_HCLK (1<<10)
191#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11) 191#define S3C2412_CLKSRC_CAMCLK_HCLK (1<<11)
192#define S3C2412_CLKSRC_UREFCLK_EXTCLK (1<<12)
193#define S3C2412_CLKSRC_EREFCLK_EXTCLK (1<<14)
192 194
193#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */ 195#endif /* CONFIG_CPU_S3C2412 | CONFIG_CPU_S3C2413 */
194 196
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index fce832820825..911393b2c6f0 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -56,6 +56,21 @@
56#endif 56#endif
57 57
58/* 58/*
59 * This can be used to enable code to cacheline align the destination
60 * pointer when bulk writing to memory. Experiments on StrongARM and
61 * XScale didn't show this a worthwhile thing to do when the cache is not
62 * set to write-allocate (this would need further testing on XScale when WA
63 * is used).
64 *
65 * On Feroceon there is much to gain however, regardless of cache mode.
66 */
67#ifdef CONFIG_CPU_FEROCEON
68#define CALGN(code...) code
69#else
70#define CALGN(code...)
71#endif
72
73/*
59 * Enable and disable interrupts 74 * Enable and disable interrupts
60 */ 75 */
61#if __LINUX_ARM_ARCH__ >= 6 76#if __LINUX_ARM_ARCH__ >= 6
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 759a97b56eed..70b0fe724b62 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -95,11 +95,7 @@
95#endif 95#endif
96 96
97#if defined(CONFIG_CPU_FEROCEON) 97#if defined(CONFIG_CPU_FEROCEON)
98# ifdef _CACHE 98# define MULTI_CACHE 1
99# define MULTI_CACHE 1
100# else
101# define _CACHE feroceon
102# endif
103#endif 99#endif
104 100
105#if defined(CONFIG_CPU_V6) 101#if defined(CONFIG_CPU_V6)
@@ -410,6 +406,13 @@ extern void flush_dcache_page(struct page *);
410 406
411extern void __flush_dcache_page(struct address_space *mapping, struct page *page); 407extern void __flush_dcache_page(struct address_space *mapping, struct page *page);
412 408
409static inline void __flush_icache_all(void)
410{
411 asm("mcr p15, 0, %0, c7, c5, 0 @ invalidate I-cache\n"
412 :
413 : "r" (0));
414}
415
413#define ARCH_HAS_FLUSH_ANON_PAGE 416#define ARCH_HAS_FLUSH_ANON_PAGE
414static inline void flush_anon_page(struct vm_area_struct *vma, 417static inline void flush_anon_page(struct vm_area_struct *vma,
415 struct page *page, unsigned long vmaddr) 418 struct page *page, unsigned long vmaddr)
diff --git a/include/asm-arm/dyntick.h b/include/asm-arm/dyntick.h
deleted file mode 100644
index 19fab2d2b760..000000000000
--- a/include/asm-arm/dyntick.h
+++ /dev/null
@@ -1,6 +0,0 @@
1#ifndef _ASMARM_DYNTICK_H
2#define _ASMARM_DYNTICK_H
3
4#include <asm/mach/time.h>
5
6#endif /* _ASMARM_DYNTICK_H */
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index 684fe0645239..5e22881a630d 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -85,19 +85,6 @@
85 85
86#define MAX_ECARDS 9 86#define MAX_ECARDS 9
87 87
88typedef enum { /* Cards address space */
89 ECARD_IOC,
90 ECARD_MEMC,
91 ECARD_EASI
92} card_type_t;
93
94typedef enum { /* Speed for ECARD_IOC space */
95 ECARD_SLOW = 0,
96 ECARD_MEDIUM = 1,
97 ECARD_FAST = 2,
98 ECARD_SYNC = 3
99} card_speed_t;
100
101struct ecard_id { /* Card ID structure */ 88struct ecard_id { /* Card ID structure */
102 unsigned short manufacturer; 89 unsigned short manufacturer;
103 unsigned short product; 90 unsigned short product;
@@ -190,16 +177,6 @@ struct in_chunk_dir {
190}; 177};
191 178
192/* 179/*
193 * ecard_claim: claim an expansion card entry
194 */
195#define ecard_claim(ec) ((ec)->claimed = 1)
196
197/*
198 * ecard_release: release an expansion card entry
199 */
200#define ecard_release(ec) ((ec)->claimed = 0)
201
202/*
203 * Read a chunk from an expansion card 180 * Read a chunk from an expansion card
204 * cd : where to put read data 181 * cd : where to put read data
205 * ec : expansion card info struct 182 * ec : expansion card info struct
@@ -209,18 +186,6 @@ struct in_chunk_dir {
209extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num); 186extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
210 187
211/* 188/*
212 * Obtain the address of a card. This returns the "old style" address
213 * and should no longer be used.
214 */
215static inline unsigned int __deprecated
216ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
217{
218 extern unsigned int __ecard_address(struct expansion_card *,
219 card_type_t, card_speed_t);
220 return __ecard_address(ec, type, speed);
221}
222
223/*
224 * Request and release ecard resources 189 * Request and release ecard resources
225 */ 190 */
226extern int ecard_request_resources(struct expansion_card *ec); 191extern int ecard_request_resources(struct expansion_card *ec);
diff --git a/include/asm-arm/ftrace.h b/include/asm-arm/ftrace.h
new file mode 100644
index 000000000000..584ef9a8e5a5
--- /dev/null
+++ b/include/asm-arm/ftrace.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_ARM_FTRACE
2#define _ASM_ARM_FTRACE
3
4#ifdef CONFIG_FTRACE
5#define MCOUNT_ADDR ((long)(mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_ARM_FTRACE */
diff --git a/include/asm-arm/hardware/iop3xx-gpio.h b/include/asm-arm/hardware/iop3xx-gpio.h
new file mode 100644
index 000000000000..0c9331f9ac24
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx-gpio.h
@@ -0,0 +1,73 @@
1/*
2 * linux/include/asm-arm/hardware/iop3xx-gpio.h
3 *
4 * IOP3xx GPIO wrappers
5 *
6 * Copyright (c) 2008 Arnaud Patard <arnaud.patard@rtp-net.org>
7 * Based on IXP4XX gpio.h file
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
25#ifndef __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
26#define __ASM_ARM_HARDWARE_IOP3XX_GPIO_H
27
28#include <asm/hardware.h>
29#include <asm-generic/gpio.h>
30
31#define IOP3XX_N_GPIOS 8
32
33static inline int gpio_get_value(unsigned gpio)
34{
35 if (gpio > IOP3XX_N_GPIOS)
36 return __gpio_get_value(gpio);
37
38 return gpio_line_get(gpio);
39}
40
41static inline void gpio_set_value(unsigned gpio, int value)
42{
43 if (gpio > IOP3XX_N_GPIOS) {
44 __gpio_set_value(gpio, value);
45 return;
46 }
47 gpio_line_set(gpio, value);
48}
49
50static inline int gpio_cansleep(unsigned gpio)
51{
52 if (gpio < IOP3XX_N_GPIOS)
53 return 0;
54 else
55 return __gpio_cansleep(gpio);
56}
57
58/*
59 * The GPIOs are not generating any interrupt
60 * Note : manuals are not clear about this
61 */
62static inline int gpio_to_irq(int gpio)
63{
64 return -EINVAL;
65}
66
67static inline int irq_to_gpio(int gpio)
68{
69 return -EINVAL;
70}
71
72#endif
73
diff --git a/include/asm-arm/hw_irq.h b/include/asm-arm/hw_irq.h
index 98d594a973d6..f1a08a500604 100644
--- a/include/asm-arm/hw_irq.h
+++ b/include/asm-arm/hw_irq.h
@@ -6,15 +6,4 @@
6 6
7#include <asm/mach/irq.h> 7#include <asm/mach/irq.h>
8 8
9#if defined(CONFIG_NO_IDLE_HZ)
10# include <asm/dyntick.h>
11# define handle_dynamic_tick(action) \
12 if (!(action->flags & IRQF_TIMER) && system_timer->dyn_tick) { \
13 write_seqlock(&xtime_lock); \
14 if (system_timer->dyn_tick->state & DYN_TICK_ENABLED) \
15 system_timer->dyn_tick->handler(irq, NULL); \
16 write_sequnlock(&xtime_lock); \
17 }
18#endif
19
20#endif 9#endif
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 47fe34d692da..c8986bb99ed5 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -14,8 +14,6 @@
14 14
15#define KEXEC_ARCH KEXEC_ARCH_ARM 15#define KEXEC_ARCH KEXEC_ARCH_ARM
16 16
17#define KEXEC_BOOT_PARAMS_SIZE 1536
18
19#define KEXEC_ARM_ATAGS_OFFSET 0x1000 17#define KEXEC_ARM_ATAGS_OFFSET 0x1000
20#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000 18#define KEXEC_ARM_ZIMAGE_OFFSET 0x8000
21 19
diff --git a/include/asm-arm/kprobes.h b/include/asm-arm/kprobes.h
index c042194d3ab5..b1a37876942d 100644
--- a/include/asm-arm/kprobes.h
+++ b/include/asm-arm/kprobes.h
@@ -59,6 +59,7 @@ struct kprobe_ctlblk {
59}; 59};
60 60
61void arch_remove_kprobe(struct kprobe *); 61void arch_remove_kprobe(struct kprobe *);
62void kretprobe_trampoline(void);
62 63
63int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr); 64int kprobe_trap_handler(struct pt_regs *regs, unsigned int instr);
64int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr); 65int kprobe_fault_handler(struct pt_regs *regs, unsigned int fsr);
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 5dc357013b79..2fd36ea0130d 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -41,30 +41,8 @@ struct sys_timer {
41#ifndef CONFIG_GENERIC_TIME 41#ifndef CONFIG_GENERIC_TIME
42 unsigned long (*offset)(void); 42 unsigned long (*offset)(void);
43#endif 43#endif
44
45#ifdef CONFIG_NO_IDLE_HZ
46 struct dyn_tick_timer *dyn_tick;
47#endif
48};
49
50#ifdef CONFIG_NO_IDLE_HZ
51
52#define DYN_TICK_ENABLED (1 << 1)
53
54struct dyn_tick_timer {
55 spinlock_t lock;
56 unsigned int state; /* Current state */
57 int (*enable)(void); /* Enables dynamic tick */
58 int (*disable)(void); /* Disables dynamic tick */
59 void (*reprogram)(unsigned long); /* Reprograms the timer */
60 int (*handler)(int, void *);
61}; 44};
62 45
63void timer_dyn_reprogram(void);
64#else
65#define timer_dyn_reprogram() do { } while (0)
66#endif
67
68extern struct sys_timer *system_timer; 46extern struct sys_timer *system_timer;
69extern void timer_tick(void); 47extern void timer_tick(void);
70 48
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
index 6913d02ca5d6..91b9dfdfed52 100644
--- a/include/asm-arm/mmu_context.h
+++ b/include/asm-arm/mmu_context.h
@@ -97,6 +97,11 @@ switch_mm(struct mm_struct *prev, struct mm_struct *next,
97#ifdef CONFIG_MMU 97#ifdef CONFIG_MMU
98 unsigned int cpu = smp_processor_id(); 98 unsigned int cpu = smp_processor_id();
99 99
100#ifdef CONFIG_SMP
101 /* check for possible thread migration */
102 if (!cpus_empty(next->cpu_vm_mask) && !cpu_isset(cpu, next->cpu_vm_mask))
103 __flush_icache_all();
104#endif
100 if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) { 105 if (!cpu_test_and_set(cpu, next->cpu_vm_mask) || prev != next) {
101 check_context(next); 106 check_context(next);
102 cpu_switch_mm(next->pgd, next); 107 cpu_switch_mm(next->pgd, next);
diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h
new file mode 100644
index 000000000000..ba4e016d3ec0
--- /dev/null
+++ b/include/asm-arm/plat-orion/cache-feroceon-l2.h
@@ -0,0 +1,11 @@
1/*
2 * include/asm-arm/plat-orion/cache-feroceon-l2.h
3 *
4 * Copyright (C) 2008 Marvell Semiconductor
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11extern void __init feroceon_l2_init(int l2_wt_override);
diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h
index ffd3852a0dd7..ad4ce94c1998 100644
--- a/include/asm-arm/plat-orion/orion_nand.h
+++ b/include/asm-arm/plat-orion/orion_nand.h
@@ -18,6 +18,7 @@ struct orion_nand_data {
18 u8 ale; /* address line number connected to ALE */ 18 u8 ale; /* address line number connected to ALE */
19 u8 cle; /* address line number connected to CLE */ 19 u8 cle; /* address line number connected to CLE */
20 u8 width; /* buswidth */ 20 u8 width; /* buswidth */
21 u8 chip_delay;
21}; 22};
22 23
23 24
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
index 6434ac685d21..e61b7bd97af5 100644
--- a/include/asm-arm/plat-orion/pcie.h
+++ b/include/asm-arm/plat-orion/pcie.h
@@ -14,6 +14,7 @@
14u32 orion_pcie_dev_id(void __iomem *base); 14u32 orion_pcie_dev_id(void __iomem *base);
15u32 orion_pcie_rev(void __iomem *base); 15u32 orion_pcie_rev(void __iomem *base);
16int orion_pcie_link_up(void __iomem *base); 16int orion_pcie_link_up(void __iomem *base);
17int orion_pcie_x4_mode(void __iomem *base);
17int orion_pcie_get_local_bus_nr(void __iomem *base); 18int orion_pcie_get_local_bus_nr(void __iomem *base);
18void orion_pcie_set_local_bus_nr(void __iomem *base, int nr); 19void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
19void orion_pcie_setup(void __iomem *base, 20void orion_pcie_setup(void __iomem *base,
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 8b0d594397b1..b5bc692f3489 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -65,6 +65,15 @@
65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) 65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
66#define S3C2410_TCFG1_MUX0_MASK (15<<0) 66#define S3C2410_TCFG1_MUX0_MASK (15<<0)
67 67
68#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
69#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
70#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
71#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
72#define S3C2410_TCFG1_MUX_TCLK (4<<0)
73#define S3C2410_TCFG1_MUX_MASK (15<<0)
74
75#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
76
68/* for each timer, we have an count buffer, an compare buffer and 77/* for each timer, we have an count buffer, an compare buffer and
69 * an observation buffer 78 * an observation buffer
70*/ 79*/
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
index f9d6f0317bc1..badaac9d64a8 100644
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ b/include/asm-arm/plat-s3c24xx/devs.h
@@ -21,6 +21,8 @@ extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
21extern struct platform_device *s3c24xx_uart_devs[]; 21extern struct platform_device *s3c24xx_uart_devs[];
22extern struct platform_device *s3c24xx_uart_src[]; 22extern struct platform_device *s3c24xx_uart_src[];
23 23
24extern struct platform_device s3c_device_timer[];
25
24extern struct platform_device s3c_device_usb; 26extern struct platform_device s3c_device_usb;
25extern struct platform_device s3c_device_lcd; 27extern struct platform_device s3c_device_lcd;
26extern struct platform_device s3c_device_wdt; 28extern struct platform_device s3c_device_wdt;
@@ -36,11 +38,6 @@ extern struct platform_device s3c_device_spi1;
36 38
37extern struct platform_device s3c_device_nand; 39extern struct platform_device s3c_device_nand;
38 40
39extern struct platform_device s3c_device_timer0;
40extern struct platform_device s3c_device_timer1;
41extern struct platform_device s3c_device_timer2;
42extern struct platform_device s3c_device_timer3;
43
44extern struct platform_device s3c_device_usbgadget; 41extern struct platform_device s3c_device_usbgadget;
45 42
46/* s3c2440 specific devices */ 43/* s3c2440 specific devices */
diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h
deleted file mode 100644
index 1a5c9232a91e..000000000000
--- a/include/asm-arm/rtc.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * linux/include/asm-arm/rtc.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_RTC_H
11#define ASMARM_RTC_H
12
13struct module;
14
15struct rtc_ops {
16 struct module *owner;
17 int (*open)(void);
18 void (*release)(void);
19 int (*ioctl)(unsigned int, unsigned long);
20
21 int (*read_time)(struct rtc_time *);
22 int (*set_time)(struct rtc_time *);
23 int (*read_alarm)(struct rtc_wkalrm *);
24 int (*set_alarm)(struct rtc_wkalrm *);
25 int (*proc)(char *buf);
26};
27
28void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *);
29void rtc_update(unsigned long, unsigned long);
30int register_rtc(struct rtc_ops *);
31void unregister_rtc(struct rtc_ops *);
32
33static inline int rtc_periodic_alarm(struct rtc_time *tm)
34{
35 return (tm->tm_year == -1) ||
36 ((unsigned)tm->tm_mon >= 12) ||
37 ((unsigned)(tm->tm_mday - 1) >= 31) ||
38 ((unsigned)tm->tm_hour > 23) ||
39 ((unsigned)tm->tm_min > 59) ||
40 ((unsigned)tm->tm_sec > 59);
41}
42
43#endif
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
index af99636db400..7fffa2404b8e 100644
--- a/include/asm-arm/smp.h
+++ b/include/asm-arm/smp.h
@@ -101,6 +101,9 @@ extern void platform_cpu_die(unsigned int cpu);
101extern int platform_cpu_kill(unsigned int cpu); 101extern int platform_cpu_kill(unsigned int cpu);
102extern void platform_cpu_enable(unsigned int cpu); 102extern void platform_cpu_enable(unsigned int cpu);
103 103
104extern void arch_send_call_function_single_ipi(int cpu);
105extern void arch_send_call_function_ipi(cpumask_t mask);
106
104/* 107/*
105 * Local timer interrupt handling function (can be IPI'ed). 108 * Local timer interrupt handling function (can be IPI'ed).
106 */ 109 */
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 8c6bc1bb9d1a..909656c747ef 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -39,6 +39,7 @@
39#define TLB_V6_D_ASID (1 << 17) 39#define TLB_V6_D_ASID (1 << 17)
40#define TLB_V6_I_ASID (1 << 18) 40#define TLB_V6_I_ASID (1 << 18)
41 41
42#define TLB_L2CLEAN_FR (1 << 29) /* Feroceon */
42#define TLB_DCLEAN (1 << 30) 43#define TLB_DCLEAN (1 << 30)
43#define TLB_WB (1 << 31) 44#define TLB_WB (1 << 31)
44 45
@@ -51,6 +52,7 @@
51 * v4 - ARMv4 without write buffer 52 * v4 - ARMv4 without write buffer
52 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction 53 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
53 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction 54 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
55 * fr - Feroceon (v4wbi with non-outer-cacheable page table walks)
54 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction 56 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
55 */ 57 */
56#undef _TLB 58#undef _TLB
@@ -103,6 +105,23 @@
103# define v4wbi_always_flags (-1UL) 105# define v4wbi_always_flags (-1UL)
104#endif 106#endif
105 107
108#define fr_tlb_flags (TLB_WB | TLB_DCLEAN | TLB_L2CLEAN_FR | \
109 TLB_V4_I_FULL | TLB_V4_D_FULL | \
110 TLB_V4_I_PAGE | TLB_V4_D_PAGE)
111
112#ifdef CONFIG_CPU_TLB_FEROCEON
113# define fr_possible_flags fr_tlb_flags
114# define fr_always_flags fr_tlb_flags
115# ifdef _TLB
116# define MULTI_TLB 1
117# else
118# define _TLB v4wbi
119# endif
120#else
121# define fr_possible_flags 0
122# define fr_always_flags (-1UL)
123#endif
124
106#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \ 125#define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
107 TLB_V4_I_FULL | TLB_V4_D_FULL | \ 126 TLB_V4_I_FULL | TLB_V4_D_FULL | \
108 TLB_V4_D_PAGE) 127 TLB_V4_D_PAGE)
@@ -245,12 +264,14 @@ extern struct cpu_tlb_fns cpu_tlb;
245#define possible_tlb_flags (v3_possible_flags | \ 264#define possible_tlb_flags (v3_possible_flags | \
246 v4_possible_flags | \ 265 v4_possible_flags | \
247 v4wbi_possible_flags | \ 266 v4wbi_possible_flags | \
267 fr_possible_flags | \
248 v4wb_possible_flags | \ 268 v4wb_possible_flags | \
249 v6wbi_possible_flags) 269 v6wbi_possible_flags)
250 270
251#define always_tlb_flags (v3_always_flags & \ 271#define always_tlb_flags (v3_always_flags & \
252 v4_always_flags & \ 272 v4_always_flags & \
253 v4wbi_always_flags & \ 273 v4wbi_always_flags & \
274 fr_always_flags & \
254 v4wb_always_flags & \ 275 v4wb_always_flags & \
255 v6wbi_always_flags) 276 v6wbi_always_flags)
256 277
@@ -417,6 +438,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
417 if (tlb_flag(TLB_DCLEAN)) 438 if (tlb_flag(TLB_DCLEAN))
418 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 439 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
419 : : "r" (pmd) : "cc"); 440 : : "r" (pmd) : "cc");
441
442 if (tlb_flag(TLB_L2CLEAN_FR))
443 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
444 : : "r" (pmd) : "cc");
445
420 if (tlb_flag(TLB_WB)) 446 if (tlb_flag(TLB_WB))
421 dsb(); 447 dsb();
422} 448}
@@ -428,6 +454,10 @@ static inline void clean_pmd_entry(pmd_t *pmd)
428 if (tlb_flag(TLB_DCLEAN)) 454 if (tlb_flag(TLB_DCLEAN))
429 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" 455 asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
430 : : "r" (pmd) : "cc"); 456 : : "r" (pmd) : "cc");
457
458 if (tlb_flag(TLB_L2CLEAN_FR))
459 asm("mcr p15, 1, %0, c15, c9, 1 @ L2 flush_pmd"
460 : : "r" (pmd) : "cc");
431} 461}
432 462
433#undef tlb_flag 463#undef tlb_flag
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index a4e2d28bfb58..b4cddfaca90e 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -8,6 +8,12 @@
8 8
9#define GPIO_PIN_NONE (-1) 9#define GPIO_PIN_NONE (-1)
10 10
11/*
12 * Clock rates for various on-board oscillators. The number of entries
13 * in this array is chip-dependent.
14 */
15extern unsigned long at32_board_osc_rates[];
16
11/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */ 17/* Add basic devices: system manager, interrupt controller, portmuxes, etc. */
12void at32_add_system_devices(void); 18void at32_add_system_devices(void);
13 19
@@ -36,7 +42,8 @@ at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
36struct atmel_lcdfb_info; 42struct atmel_lcdfb_info;
37struct platform_device * 43struct platform_device *
38at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, 44at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
39 unsigned long fbmem_start, unsigned long fbmem_len); 45 unsigned long fbmem_start, unsigned long fbmem_len,
46 unsigned int pin_config);
40 47
41struct usba_platform_data; 48struct usba_platform_data;
42struct platform_device * 49struct platform_device *
@@ -73,6 +80,7 @@ struct platform_device *at32_add_device_twi(unsigned int id,
73struct platform_device *at32_add_device_mci(unsigned int id); 80struct platform_device *at32_add_device_mci(unsigned int id);
74struct platform_device *at32_add_device_ac97c(unsigned int id); 81struct platform_device *at32_add_device_ac97c(unsigned int id);
75struct platform_device *at32_add_device_abdac(unsigned int id); 82struct platform_device *at32_add_device_abdac(unsigned int id);
83struct platform_device *at32_add_device_psif(unsigned int id);
76 84
77struct cf_platform_data { 85struct cf_platform_data {
78 int detect_pin; 86 int detect_pin;
diff --git a/include/asm-avr32/arch-at32ap/init.h b/include/asm-avr32/arch-at32ap/init.h
index 5e75d850d707..bc40e3d46150 100644
--- a/include/asm-avr32/arch-at32ap/init.h
+++ b/include/asm-avr32/arch-at32ap/init.h
@@ -13,10 +13,6 @@
13void setup_platform(void); 13void setup_platform(void);
14void setup_board(void); 14void setup_board(void);
15 15
16/* Called by setup_platform */
17void at32_clock_init(void);
18void at32_portmux_init(void);
19
20void at32_setup_serial_console(unsigned int usart_id); 16void at32_setup_serial_console(unsigned int usart_id);
21 17
22#endif /* __ASM_AVR32_AT32AP_INIT_H__ */ 18#endif /* __ASM_AVR32_AT32AP_INIT_H__ */
diff --git a/include/asm-avr32/arch-at32ap/pm.h b/include/asm-avr32/arch-at32ap/pm.h
index 356e43064903..979b355b77b6 100644
--- a/include/asm-avr32/arch-at32ap/pm.h
+++ b/include/asm-avr32/arch-at32ap/pm.h
@@ -19,6 +19,7 @@
19 19
20#ifndef __ASSEMBLY__ 20#ifndef __ASSEMBLY__
21extern void cpu_enter_idle(void); 21extern void cpu_enter_idle(void);
22extern void cpu_enter_standby(unsigned long sdramc_base);
22 23
23extern bool disable_idle_sleep; 24extern bool disable_idle_sleep;
24 25
@@ -43,6 +44,8 @@ static inline void cpu_idle_sleep(void)
43 else 44 else
44 cpu_enter_idle(); 45 cpu_enter_idle();
45} 46}
47
48void intc_set_suspend_handler(unsigned long offset);
46#endif 49#endif
47 50
48#endif /* __ASM_AVR32_ARCH_PM_H */ 51#endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/arch-at32ap/sram.h b/include/asm-avr32/arch-at32ap/sram.h
new file mode 100644
index 000000000000..4838dae7601a
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/sram.h
@@ -0,0 +1,30 @@
1/*
2 * Simple SRAM allocator
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_ARCH_SRAM_H
11#define __ASM_AVR32_ARCH_SRAM_H
12
13#include <linux/genalloc.h>
14
15extern struct gen_pool *sram_pool;
16
17static inline unsigned long sram_alloc(size_t len)
18{
19 if (!sram_pool)
20 return 0UL;
21
22 return gen_pool_alloc(sram_pool, len);
23}
24
25static inline void sram_free(unsigned long addr, size_t len)
26{
27 return gen_pool_free(sram_pool, addr, len);
28}
29
30#endif /* __ASM_AVR32_ARCH_SRAM_H */
diff --git a/include/asm-avr32/mmu_context.h b/include/asm-avr32/mmu_context.h
index c37c391faef6..27ff23407100 100644
--- a/include/asm-avr32/mmu_context.h
+++ b/include/asm-avr32/mmu_context.h
@@ -13,7 +13,6 @@
13#define __ASM_AVR32_MMU_CONTEXT_H 13#define __ASM_AVR32_MMU_CONTEXT_H
14 14
15#include <asm/tlbflush.h> 15#include <asm/tlbflush.h>
16#include <asm/pgalloc.h>
17#include <asm/sysreg.h> 16#include <asm/sysreg.h>
18#include <asm-generic/mm_hooks.h> 17#include <asm-generic/mm_hooks.h>
19 18
diff --git a/include/asm-avr32/pci.h b/include/asm-avr32/pci.h
index 0f5f134b896a..a32a02372017 100644
--- a/include/asm-avr32/pci.h
+++ b/include/asm-avr32/pci.h
@@ -5,4 +5,6 @@
5 5
6#define PCI_DMA_BUS_IS_PHYS (1) 6#define PCI_DMA_BUS_IS_PHYS (1)
7 7
8#include <asm-generic/pci-dma-compat.h>
9
8#endif /* __ASM_AVR32_PCI_H__ */ 10#endif /* __ASM_AVR32_PCI_H__ */
diff --git a/include/asm-avr32/pgalloc.h b/include/asm-avr32/pgalloc.h
index 51fc1f6e4b17..640821323943 100644
--- a/include/asm-avr32/pgalloc.h
+++ b/include/asm-avr32/pgalloc.h
@@ -8,65 +8,79 @@
8#ifndef __ASM_AVR32_PGALLOC_H 8#ifndef __ASM_AVR32_PGALLOC_H
9#define __ASM_AVR32_PGALLOC_H 9#define __ASM_AVR32_PGALLOC_H
10 10
11#include <asm/processor.h> 11#include <linux/quicklist.h>
12#include <linux/threads.h> 12#include <asm/page.h>
13#include <linux/slab.h> 13#include <asm/pgtable.h>
14#include <linux/mm.h>
15 14
16#define pmd_populate_kernel(mm, pmd, pte) \ 15#define QUICK_PGD 0 /* Preserve kernel mappings over free */
17 set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) 16#define QUICK_PT 1 /* Zero on free */
18 17
19static __inline__ void pmd_populate(struct mm_struct *mm, pmd_t *pmd, 18static inline void pmd_populate_kernel(struct mm_struct *mm,
19 pmd_t *pmd, pte_t *pte)
20{
21 set_pmd(pmd, __pmd((unsigned long)pte));
22}
23
24static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
20 pgtable_t pte) 25 pgtable_t pte)
21{ 26{
22 set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); 27 set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
23} 28}
24#define pmd_pgtable(pmd) pmd_page(pmd) 29#define pmd_pgtable(pmd) pmd_page(pmd)
25 30
31static inline void pgd_ctor(void *x)
32{
33 pgd_t *pgd = x;
34
35 memcpy(pgd + USER_PTRS_PER_PGD,
36 swapper_pg_dir + USER_PTRS_PER_PGD,
37 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
38}
39
26/* 40/*
27 * Allocate and free page tables 41 * Allocate and free page tables
28 */ 42 */
29static __inline__ pgd_t *pgd_alloc(struct mm_struct *mm) 43static inline pgd_t *pgd_alloc(struct mm_struct *mm)
30{ 44{
31 return kcalloc(USER_PTRS_PER_PGD, sizeof(pgd_t), GFP_KERNEL); 45 return quicklist_alloc(QUICK_PGD, GFP_KERNEL | __GFP_REPEAT, pgd_ctor);
32} 46}
33 47
34static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd) 48static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
35{ 49{
36 kfree(pgd); 50 quicklist_free(QUICK_PGD, NULL, pgd);
37} 51}
38 52
39static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, 53static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
40 unsigned long address) 54 unsigned long address)
41{ 55{
42 pte_t *pte; 56 return quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
43
44 pte = (pte_t *)get_zeroed_page(GFP_KERNEL | __GFP_REPEAT);
45
46 return pte;
47} 57}
48 58
49static inline struct page *pte_alloc_one(struct mm_struct *mm, 59static inline pgtable_t pte_alloc_one(struct mm_struct *mm,
50 unsigned long address) 60 unsigned long address)
51{ 61{
52 struct page *pte; 62 struct page *page;
63 void *pg;
53 64
54 pte = alloc_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); 65 pg = quicklist_alloc(QUICK_PT, GFP_KERNEL | __GFP_REPEAT, NULL);
55 if (!pte) 66 if (!pg)
56 return NULL; 67 return NULL;
57 pgtable_page_ctor(pte); 68
58 return pte; 69 page = virt_to_page(pg);
70 pgtable_page_ctor(page);
71
72 return page;
59} 73}
60 74
61static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte) 75static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
62{ 76{
63 free_page((unsigned long)pte); 77 quicklist_free(QUICK_PT, NULL, pte);
64} 78}
65 79
66static inline void pte_free(struct mm_struct *mm, pgtable_t pte) 80static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
67{ 81{
68 pgtable_page_dtor(pte); 82 pgtable_page_dtor(pte);
69 __free_page(pte); 83 quicklist_free_page(QUICK_PT, NULL, pte);
70} 84}
71 85
72#define __pte_free_tlb(tlb,pte) \ 86#define __pte_free_tlb(tlb,pte) \
@@ -75,6 +89,10 @@ do { \
75 tlb_remove_page((tlb), pte); \ 89 tlb_remove_page((tlb), pte); \
76} while (0) 90} while (0)
77 91
78#define check_pgt_cache() do { } while(0) 92static inline void check_pgt_cache(void)
93{
94 quicklist_trim(QUICK_PGD, NULL, 25, 16);
95 quicklist_trim(QUICK_PT, NULL, 25, 16);
96}
79 97
80#endif /* __ASM_AVR32_PGALLOC_H */ 98#endif /* __ASM_AVR32_PGALLOC_H */
diff --git a/include/asm-avr32/pgtable.h b/include/asm-avr32/pgtable.h
index c0e5e29417df..fecdda16f444 100644
--- a/include/asm-avr32/pgtable.h
+++ b/include/asm-avr32/pgtable.h
@@ -129,13 +129,6 @@ extern struct page *empty_zero_page;
129 129
130#define _PAGE_FLAGS_CACHE_MASK (_PAGE_CACHABLE | _PAGE_BUFFER | _PAGE_WT) 130#define _PAGE_FLAGS_CACHE_MASK (_PAGE_CACHABLE | _PAGE_BUFFER | _PAGE_WT)
131 131
132/* TODO: Check for saneness */
133/* User-mode page table flags (to be set in a pgd or pmd entry) */
134#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
135 | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
136/* Kernel-mode page table flags */
137#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_TYPE_SMALL | _PAGE_RW \
138 | _PAGE_ACCESSED | _PAGE_DIRTY)
139/* Flags that may be modified by software */ 132/* Flags that may be modified by software */
140#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY \ 133#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY \
141 | _PAGE_FLAGS_CACHE_MASK) 134 | _PAGE_FLAGS_CACHE_MASK)
@@ -262,10 +255,14 @@ static inline pte_t pte_mkspecial(pte_t pte)
262} 255}
263 256
264#define pmd_none(x) (!pmd_val(x)) 257#define pmd_none(x) (!pmd_val(x))
265#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) 258#define pmd_present(x) (pmd_val(x))
266#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) 259
267#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) \ 260static inline void pmd_clear(pmd_t *pmdp)
268 != _KERNPG_TABLE) 261{
262 set_pmd(pmdp, __pmd(0));
263}
264
265#define pmd_bad(x) (pmd_val(x) & ~PAGE_MASK)
269 266
270/* 267/*
271 * Permanent address of a page. We don't support highmem, so this is 268 * Permanent address of a page. We don't support highmem, so this is
@@ -303,19 +300,16 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
303 300
304#define page_pte(page) page_pte_prot(page, __pgprot(0)) 301#define page_pte(page) page_pte_prot(page, __pgprot(0))
305 302
306#define pmd_page_vaddr(pmd) \ 303#define pmd_page_vaddr(pmd) pmd_val(pmd)
307 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) 304#define pmd_page(pmd) (virt_to_page(pmd_val(pmd)))
308
309#define pmd_page(pmd) (phys_to_page(pmd_val(pmd)))
310 305
311/* to find an entry in a page-table-directory. */ 306/* to find an entry in a page-table-directory. */
312#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 307#define pgd_index(address) (((address) >> PGDIR_SHIFT) \
313#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) 308 & (PTRS_PER_PGD - 1))
314#define pgd_offset_current(address) \ 309#define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
315 ((pgd_t *)__mfsr(SYSREG_PTBR) + pgd_index(address))
316 310
317/* to find an entry in a kernel page-table-directory */ 311/* to find an entry in a kernel page-table-directory */
318#define pgd_offset_k(address) pgd_offset(&init_mm, address) 312#define pgd_offset_k(address) pgd_offset(&init_mm, address)
319 313
320/* Find an entry in the third-level page table.. */ 314/* Find an entry in the third-level page table.. */
321#define pte_index(address) \ 315#define pte_index(address) \
diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h
index ea3070ff13a5..ff5b7cf6be4d 100644
--- a/include/asm-avr32/setup.h
+++ b/include/asm-avr32/setup.h
@@ -2,7 +2,7 @@
2 * Copyright (C) 2004-2006 Atmel Corporation 2 * Copyright (C) 2004-2006 Atmel Corporation
3 * 3 *
4 * Based on linux/include/asm-arm/setup.h 4 * Based on linux/include/asm-arm/setup.h
5 * Copyright (C) 1997-1999 Russel King 5 * Copyright (C) 1997-1999 Russell King
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index 07049f6c0d41..df68631b7b27 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -88,6 +88,7 @@ static inline struct thread_info *current_thread_info(void)
88#define TIF_MEMDIE 6 88#define TIF_MEMDIE 6
89#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */ 89#define TIF_RESTORE_SIGMASK 7 /* restore signal mask in do_signal */
90#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */ 90#define TIF_CPU_GOING_TO_SLEEP 8 /* CPU is entering sleep 0 mode */
91#define TIF_FREEZE 29
91#define TIF_DEBUG 30 /* debugging enabled */ 92#define TIF_DEBUG 30 /* debugging enabled */
92#define TIF_USERSPACE 31 /* true if FS sets userspace */ 93#define TIF_USERSPACE 31 /* true if FS sets userspace */
93 94
diff --git a/include/asm-avr32/tlbflush.h b/include/asm-avr32/tlbflush.h
index 5bc7c88a5770..bf90a786f6be 100644
--- a/include/asm-avr32/tlbflush.h
+++ b/include/asm-avr32/tlbflush.h
@@ -26,7 +26,6 @@ extern void flush_tlb_mm(struct mm_struct *mm);
26extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 26extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
27 unsigned long end); 27 unsigned long end);
28extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page); 28extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
29extern void __flush_tlb_page(unsigned long asid, unsigned long page);
30 29
31extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); 30extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
32 31
diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h
index d3a12a9079f7..7742ec000cc4 100644
--- a/include/asm-frv/system.h
+++ b/include/asm-frv/system.h
@@ -87,7 +87,7 @@ do { \
87} while(0) 87} while(0)
88 88
89#define irqs_disabled() \ 89#define irqs_disabled() \
90 ({unsigned long flags; local_save_flags(flags); flags; }) 90 ({unsigned long flags; local_save_flags(flags); !!flags; })
91 91
92#define local_irq_save(flags) \ 92#define local_irq_save(flags) \
93do { \ 93do { \
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index 44ef329531c3..ef87f889ef62 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -195,6 +195,63 @@ static inline int pmd_none_or_clear_bad(pmd_t *pmd)
195 } 195 }
196 return 0; 196 return 0;
197} 197}
198
199static inline pte_t __ptep_modify_prot_start(struct mm_struct *mm,
200 unsigned long addr,
201 pte_t *ptep)
202{
203 /*
204 * Get the current pte state, but zero it out to make it
205 * non-present, preventing the hardware from asynchronously
206 * updating it.
207 */
208 return ptep_get_and_clear(mm, addr, ptep);
209}
210
211static inline void __ptep_modify_prot_commit(struct mm_struct *mm,
212 unsigned long addr,
213 pte_t *ptep, pte_t pte)
214{
215 /*
216 * The pte is non-present, so there's no hardware state to
217 * preserve.
218 */
219 set_pte_at(mm, addr, ptep, pte);
220}
221
222#ifndef __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
223/*
224 * Start a pte protection read-modify-write transaction, which
225 * protects against asynchronous hardware modifications to the pte.
226 * The intention is not to prevent the hardware from making pte
227 * updates, but to prevent any updates it may make from being lost.
228 *
229 * This does not protect against other software modifications of the
230 * pte; the appropriate pte lock must be held over the transation.
231 *
232 * Note that this interface is intended to be batchable, meaning that
233 * ptep_modify_prot_commit may not actually update the pte, but merely
234 * queue the update to be done at some later time. The update must be
235 * actually committed before the pte lock is released, however.
236 */
237static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
238 unsigned long addr,
239 pte_t *ptep)
240{
241 return __ptep_modify_prot_start(mm, addr, ptep);
242}
243
244/*
245 * Commit an update to a pte, leaving any hardware-controlled bits in
246 * the PTE unmodified.
247 */
248static inline void ptep_modify_prot_commit(struct mm_struct *mm,
249 unsigned long addr,
250 pte_t *ptep, pte_t pte)
251{
252 __ptep_modify_prot_commit(mm, addr, ptep, pte);
253}
254#endif /* __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION */
198#endif /* CONFIG_MMU */ 255#endif /* CONFIG_MMU */
199 256
200/* 257/*
diff --git a/include/asm-generic/topology.h b/include/asm-generic/topology.h
index a6aea79bca4f..54bbf6e04ee8 100644
--- a/include/asm-generic/topology.h
+++ b/include/asm-generic/topology.h
@@ -60,7 +60,8 @@
60#ifndef node_to_cpumask_ptr 60#ifndef node_to_cpumask_ptr
61 61
62#define node_to_cpumask_ptr(v, node) \ 62#define node_to_cpumask_ptr(v, node) \
63 cpumask_t _##v = node_to_cpumask(node), *v = &_##v 63 cpumask_t _##v = node_to_cpumask(node); \
64 const cpumask_t *v = &_##v
64 65
65#define node_to_cpumask_ptr_next(v, node) \ 66#define node_to_cpumask_ptr_next(v, node) \
66 _##v = node_to_cpumask(node) 67 _##v = node_to_cpumask(node)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index f054778e916c..b20409404c7d 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -67,6 +67,8 @@
67 *(.rodata1) \ 67 *(.rodata1) \
68 } \ 68 } \
69 \ 69 \
70 BUG_TABLE \
71 \
70 /* PCI quirks */ \ 72 /* PCI quirks */ \
71 .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \ 73 .pci_fixup : AT(ADDR(.pci_fixup) - LOAD_OFFSET) { \
72 VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \ 74 VMLINUX_SYMBOL(__start_pci_fixups_early) = .; \
@@ -86,6 +88,13 @@
86 VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \ 88 VMLINUX_SYMBOL(__end_pci_fixups_resume) = .; \
87 } \ 89 } \
88 \ 90 \
91 /* Built-in firmware blobs */ \
92 .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \
93 VMLINUX_SYMBOL(__start_builtin_fw) = .; \
94 *(.builtin_fw) \
95 VMLINUX_SYMBOL(__end_builtin_fw) = .; \
96 } \
97 \
89 /* RapidIO route ops */ \ 98 /* RapidIO route ops */ \
90 .rio_route : AT(ADDR(.rio_route) - LOAD_OFFSET) { \ 99 .rio_route : AT(ADDR(.rio_route) - LOAD_OFFSET) { \
91 VMLINUX_SYMBOL(__start_rio_route_ops) = .; \ 100 VMLINUX_SYMBOL(__start_rio_route_ops) = .; \
@@ -93,6 +102,8 @@
93 VMLINUX_SYMBOL(__end_rio_route_ops) = .; \ 102 VMLINUX_SYMBOL(__end_rio_route_ops) = .; \
94 } \ 103 } \
95 \ 104 \
105 TRACEDATA \
106 \
96 /* Kernel symbol table: Normal symbols */ \ 107 /* Kernel symbol table: Normal symbols */ \
97 __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \ 108 __ksymtab : AT(ADDR(__ksymtab) - LOAD_OFFSET) { \
98 VMLINUX_SYMBOL(__start___ksymtab) = .; \ 109 VMLINUX_SYMBOL(__start___ksymtab) = .; \
@@ -310,6 +321,7 @@
310 .stab.indexstr 0 : { *(.stab.indexstr) } \ 321 .stab.indexstr 0 : { *(.stab.indexstr) } \
311 .comment 0 : { *(.comment) } 322 .comment 0 : { *(.comment) }
312 323
324#ifdef CONFIG_GENERIC_BUG
313#define BUG_TABLE \ 325#define BUG_TABLE \
314 . = ALIGN(8); \ 326 . = ALIGN(8); \
315 __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \ 327 __bug_table : AT(ADDR(__bug_table) - LOAD_OFFSET) { \
@@ -317,6 +329,21 @@
317 *(__bug_table) \ 329 *(__bug_table) \
318 __stop___bug_table = .; \ 330 __stop___bug_table = .; \
319 } 331 }
332#else
333#define BUG_TABLE
334#endif
335
336#ifdef CONFIG_PM_TRACE
337#define TRACEDATA \
338 . = ALIGN(4); \
339 .tracedata : AT(ADDR(.tracedata) - LOAD_OFFSET) { \
340 __tracedata_start = .; \
341 *(.tracedata) \
342 __tracedata_end = .; \
343 }
344#else
345#define TRACEDATA
346#endif
320 347
321#define NOTES \ 348#define NOTES \
322 .notes : AT(ADDR(.notes) - LOAD_OFFSET) { \ 349 .notes : AT(ADDR(.notes) - LOAD_OFFSET) { \
diff --git a/include/asm-ia64/smp.h b/include/asm-ia64/smp.h
index ec5f355fb7e3..27731e032ee9 100644
--- a/include/asm-ia64/smp.h
+++ b/include/asm-ia64/smp.h
@@ -38,9 +38,6 @@ ia64_get_lid (void)
38 return lid.f.id << 8 | lid.f.eid; 38 return lid.f.id << 8 | lid.f.eid;
39} 39}
40 40
41extern int smp_call_function_mask(cpumask_t mask, void (*func)(void *),
42 void *info, int wait);
43
44#define hard_smp_processor_id() ia64_get_lid() 41#define hard_smp_processor_id() ia64_get_lid()
45 42
46#ifdef CONFIG_SMP 43#ifdef CONFIG_SMP
@@ -124,11 +121,12 @@ extern void __init init_smp_config (void);
124extern void smp_do_timer (struct pt_regs *regs); 121extern void smp_do_timer (struct pt_regs *regs);
125 122
126extern void smp_send_reschedule (int cpu); 123extern void smp_send_reschedule (int cpu);
127extern void lock_ipi_calllock(void);
128extern void unlock_ipi_calllock(void);
129extern void identify_siblings (struct cpuinfo_ia64 *); 124extern void identify_siblings (struct cpuinfo_ia64 *);
130extern int is_multithreading_enabled(void); 125extern int is_multithreading_enabled(void);
131 126
127extern void arch_send_call_function_single_ipi(int cpu);
128extern void arch_send_call_function_ipi(cpumask_t mask);
129
132#else /* CONFIG_SMP */ 130#else /* CONFIG_SMP */
133 131
134#define cpu_logical_id(i) 0 132#define cpu_logical_id(i) 0
diff --git a/include/asm-m32r/smp.h b/include/asm-m32r/smp.h
index 078e1a51a042..c5dd66916692 100644
--- a/include/asm-m32r/smp.h
+++ b/include/asm-m32r/smp.h
@@ -89,6 +89,9 @@ static __inline__ unsigned int num_booting_cpus(void)
89extern void smp_send_timer(void); 89extern void smp_send_timer(void);
90extern unsigned long send_IPI_mask_phys(cpumask_t, int, int); 90extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
91 91
92extern void arch_send_call_function_single_ipi(int cpu);
93extern void arch_send_call_function_ipi(cpumask_t mask);
94
92#endif /* not __ASSEMBLY__ */ 95#endif /* not __ASSEMBLY__ */
93 96
94#define NO_PROC_ID (0xff) /* No processor magic marker */ 97#define NO_PROC_ID (0xff) /* No processor magic marker */
@@ -104,6 +107,7 @@ extern unsigned long send_IPI_mask_phys(cpumask_t, int, int);
104#define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0) 107#define LOCAL_TIMER_IPI (M32R_IRQ_IPI3-M32R_IRQ_IPI0)
105#define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0) 108#define INVALIDATE_CACHE_IPI (M32R_IRQ_IPI4-M32R_IRQ_IPI0)
106#define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0) 109#define CPU_BOOT_IPI (M32R_IRQ_IPI5-M32R_IRQ_IPI0)
110#define CALL_FUNC_SINGLE_IPI (M32R_IRQ_IPI6-M32R_IRQ_IPI0)
107 111
108#define IPI_SHIFT (0) 112#define IPI_SHIFT (0)
109#define NR_IPIS (8) 113#define NR_IPIS (8)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
index dae4eca2417e..892b7f168eb4 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_psc.h
@@ -204,6 +204,14 @@ typedef struct psc_i2s {
204 u32 psc_i2sudf; 204 u32 psc_i2sudf;
205} psc_i2s_t; 205} psc_i2s_t;
206 206
207#define PSC_I2SCFG_OFFSET 0x08
208#define PSC_I2SMASK_OFFSET 0x0C
209#define PSC_I2SPCR_OFFSET 0x10
210#define PSC_I2SSTAT_OFFSET 0x14
211#define PSC_I2SEVENT_OFFSET 0x18
212#define PSC_I2SRXTX_OFFSET 0x1C
213#define PSC_I2SUDF_OFFSET 0x20
214
207/* I2S Config Register. */ 215/* I2S Config Register. */
208#define PSC_I2SCFG_RT_MASK (3 << 30) 216#define PSC_I2SCFG_RT_MASK (3 << 30)
209#define PSC_I2SCFG_RT_FIFO1 (0 << 30) 217#define PSC_I2SCFG_RT_FIFO1 (0 << 30)
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
index 84fef1aeec0c..0ff5b523ea77 100644
--- a/include/asm-mips/smp.h
+++ b/include/asm-mips/smp.h
@@ -35,16 +35,6 @@ extern int __cpu_logical_map[NR_CPUS];
35 35
36#define NO_PROC_ID (-1) 36#define NO_PROC_ID (-1)
37 37
38struct call_data_struct {
39 void (*func)(void *);
40 void *info;
41 atomic_t started;
42 atomic_t finished;
43 int wait;
44};
45
46extern struct call_data_struct *call_data;
47
48#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ 38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
49#define SMP_CALL_FUNCTION 0x2 39#define SMP_CALL_FUNCTION 0x2
50 40
@@ -67,4 +57,7 @@ static inline void smp_send_reschedule(int cpu)
67 57
68extern asmlinkage void smp_call_function_interrupt(void); 58extern asmlinkage void smp_call_function_interrupt(void);
69 59
60extern void arch_send_call_function_single_ipi(int cpu);
61extern void arch_send_call_function_ipi(cpumask_t mask);
62
70#endif /* __ASM_SMP_H */ 63#endif /* __ASM_SMP_H */
diff --git a/include/asm-parisc/smp.h b/include/asm-parisc/smp.h
index 306f4950e32e..398cdbaf4e54 100644
--- a/include/asm-parisc/smp.h
+++ b/include/asm-parisc/smp.h
@@ -30,6 +30,9 @@ extern cpumask_t cpu_online_map;
30extern void smp_send_reschedule(int cpu); 30extern void smp_send_reschedule(int cpu);
31extern void smp_send_all_nop(void); 31extern void smp_send_all_nop(void);
32 32
33extern void arch_send_call_function_single_ipi(int cpu);
34extern void arch_send_call_function_ipi(cpumask_t mask);
35
33#endif /* !ASSEMBLY */ 36#endif /* !ASSEMBLY */
34 37
35/* 38/*
diff --git a/include/asm-powerpc/ftrace.h b/include/asm-powerpc/ftrace.h
new file mode 100644
index 000000000000..de921326cca8
--- /dev/null
+++ b/include/asm-powerpc/ftrace.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_POWERPC_FTRACE
2#define _ASM_POWERPC_FTRACE
3
4#ifdef CONFIG_FTRACE
5#define MCOUNT_ADDR ((long)(_mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void _mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_POWERPC_FTRACE */
diff --git a/include/asm-powerpc/hugetlb.h b/include/asm-powerpc/hugetlb.h
index 649c6c3b87b3..be32ff02f4a0 100644
--- a/include/asm-powerpc/hugetlb.h
+++ b/include/asm-powerpc/hugetlb.h
@@ -49,12 +49,6 @@ static inline pte_t huge_pte_wrprotect(pte_t pte)
49 return pte_wrprotect(pte); 49 return pte_wrprotect(pte);
50} 50}
51 51
52static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
53 unsigned long addr, pte_t *ptep)
54{
55 ptep_set_wrprotect(mm, addr, ptep);
56}
57
58static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma, 52static inline int huge_ptep_set_access_flags(struct vm_area_struct *vma,
59 unsigned long addr, pte_t *ptep, 53 unsigned long addr, pte_t *ptep,
60 pte_t pte, int dirty) 54 pte_t pte, int dirty)
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index ad8c9f7fd0e3..f75a5fc64d2e 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -59,6 +59,11 @@ extern void iseries_handle_interrupts(void);
59 get_paca()->hard_enabled = 0; \ 59 get_paca()->hard_enabled = 0; \
60 } while(0) 60 } while(0)
61 61
62static inline int irqs_disabled_flags(unsigned long flags)
63{
64 return flags == 0;
65}
66
62#else 67#else
63 68
64#if defined(CONFIG_BOOKE) 69#if defined(CONFIG_BOOKE)
@@ -113,6 +118,11 @@ static inline void local_irq_save_ptr(unsigned long *flags)
113#define hard_irq_enable() local_irq_enable() 118#define hard_irq_enable() local_irq_enable()
114#define hard_irq_disable() local_irq_disable() 119#define hard_irq_disable() local_irq_disable()
115 120
121static inline int irqs_disabled_flags(unsigned long flags)
122{
123 return (flags & MSR_EE) == 0;
124}
125
116#endif /* CONFIG_PPC64 */ 126#endif /* CONFIG_PPC64 */
117 127
118/* 128/*
diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h
index cc6a43ba41d0..7686569a0bef 100644
--- a/include/asm-powerpc/pgtable-ppc64.h
+++ b/include/asm-powerpc/pgtable-ppc64.h
@@ -314,6 +314,16 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
314 old = pte_update(mm, addr, ptep, _PAGE_RW, 0); 314 old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
315} 315}
316 316
317static inline void huge_ptep_set_wrprotect(struct mm_struct *mm,
318 unsigned long addr, pte_t *ptep)
319{
320 unsigned long old;
321
322 if ((pte_val(*ptep) & _PAGE_RW) == 0)
323 return;
324 old = pte_update(mm, addr, ptep, _PAGE_RW, 1);
325}
326
317/* 327/*
318 * We currently remove entries from the hashtable regardless of whether 328 * We currently remove entries from the hashtable regardless of whether
319 * the entry was young or dirty. The generic routines only flush if the 329 * the entry was young or dirty. The generic routines only flush if the
diff --git a/include/asm-powerpc/smp.h b/include/asm-powerpc/smp.h
index 505f35bacaa9..c663a1fa77c5 100644
--- a/include/asm-powerpc/smp.h
+++ b/include/asm-powerpc/smp.h
@@ -67,10 +67,7 @@ DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
67 * in /proc/interrupts will be wrong!!! --Troy */ 67 * in /proc/interrupts will be wrong!!! --Troy */
68#define PPC_MSG_CALL_FUNCTION 0 68#define PPC_MSG_CALL_FUNCTION 0
69#define PPC_MSG_RESCHEDULE 1 69#define PPC_MSG_RESCHEDULE 1
70/* This is unused now */ 70#define PPC_MSG_CALL_FUNC_SINGLE 2
71#if 0
72#define PPC_MSG_MIGRATE_TASK 2
73#endif
74#define PPC_MSG_DEBUGGER_BREAK 3 71#define PPC_MSG_DEBUGGER_BREAK 3
75 72
76void smp_init_iSeries(void); 73void smp_init_iSeries(void);
@@ -117,6 +114,9 @@ extern void smp_generic_take_timebase(void);
117 114
118extern struct smp_ops_t *smp_ops; 115extern struct smp_ops_t *smp_ops;
119 116
117extern void arch_send_call_function_single_ipi(int cpu);
118extern void arch_send_call_function_ipi(cpumask_t mask);
119
120#endif /* __ASSEMBLY__ */ 120#endif /* __ASSEMBLY__ */
121 121
122#endif /* __KERNEL__ */ 122#endif /* __KERNEL__ */
diff --git a/include/asm-s390/Kbuild b/include/asm-s390/Kbuild
index 13c9805349f1..09f312501eb5 100644
--- a/include/asm-s390/Kbuild
+++ b/include/asm-s390/Kbuild
@@ -8,6 +8,9 @@ header-y += ucontext.h
8header-y += vtoc.h 8header-y += vtoc.h
9header-y += zcrypt.h 9header-y += zcrypt.h
10header-y += kvm.h 10header-y += kvm.h
11header-y += schid.h
12header-y += chsc.h
11 13
12unifdef-y += cmb.h 14unifdef-y += cmb.h
13unifdef-y += debug.h 15unifdef-y += debug.h
16unifdef-y += chpid.h
diff --git a/include/asm-s390/airq.h b/include/asm-s390/airq.h
index 41d028cb52a4..1ac80d6b0588 100644
--- a/include/asm-s390/airq.h
+++ b/include/asm-s390/airq.h
@@ -13,7 +13,7 @@
13 13
14typedef void (*adapter_int_handler_t)(void *, void *); 14typedef void (*adapter_int_handler_t)(void *, void *);
15 15
16void *s390_register_adapter_interrupt(adapter_int_handler_t, void *); 16void *s390_register_adapter_interrupt(adapter_int_handler_t, void *, u8);
17void s390_unregister_adapter_interrupt(void *); 17void s390_unregister_adapter_interrupt(void *, u8);
18 18
19#endif /* _ASM_S390_AIRQ_H */ 19#endif /* _ASM_S390_AIRQ_H */
diff --git a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h
index 066aa70518ce..ba007d8df941 100644
--- a/include/asm-s390/ccwdev.h
+++ b/include/asm-s390/ccwdev.h
@@ -12,6 +12,7 @@
12 12
13#include <linux/device.h> 13#include <linux/device.h>
14#include <linux/mod_devicetable.h> 14#include <linux/mod_devicetable.h>
15#include <asm/fcx.h>
15 16
16/* structs from asm/cio.h */ 17/* structs from asm/cio.h */
17struct irb; 18struct irb;
@@ -157,6 +158,17 @@ extern int ccw_device_start_timeout_key(struct ccw_device *, struct ccw1 *,
157extern int ccw_device_resume(struct ccw_device *); 158extern int ccw_device_resume(struct ccw_device *);
158extern int ccw_device_halt(struct ccw_device *, unsigned long); 159extern int ccw_device_halt(struct ccw_device *, unsigned long);
159extern int ccw_device_clear(struct ccw_device *, unsigned long); 160extern int ccw_device_clear(struct ccw_device *, unsigned long);
161int ccw_device_tm_start_key(struct ccw_device *cdev, struct tcw *tcw,
162 unsigned long intparm, u8 lpm, u8 key);
163int ccw_device_tm_start_key(struct ccw_device *, struct tcw *,
164 unsigned long, u8, u8);
165int ccw_device_tm_start_timeout_key(struct ccw_device *, struct tcw *,
166 unsigned long, u8, u8, int);
167int ccw_device_tm_start(struct ccw_device *, struct tcw *,
168 unsigned long, u8);
169int ccw_device_tm_start_timeout(struct ccw_device *, struct tcw *,
170 unsigned long, u8, int);
171int ccw_device_tm_intrg(struct ccw_device *cdev);
160 172
161extern int ccw_device_set_online(struct ccw_device *cdev); 173extern int ccw_device_set_online(struct ccw_device *cdev);
162extern int ccw_device_set_offline(struct ccw_device *cdev); 174extern int ccw_device_set_offline(struct ccw_device *cdev);
diff --git a/include/asm-s390/chpid.h b/include/asm-s390/chpid.h
index b203336fd892..606844d0a5c3 100644
--- a/include/asm-s390/chpid.h
+++ b/include/asm-s390/chpid.h
@@ -10,7 +10,6 @@
10 10
11#include <linux/string.h> 11#include <linux/string.h>
12#include <asm/types.h> 12#include <asm/types.h>
13#include <asm/cio.h>
14 13
15#define __MAX_CHPID 255 14#define __MAX_CHPID 255
16 15
@@ -41,6 +40,9 @@ static inline void chp_id_next(struct chp_id *chpid)
41 } 40 }
42} 41}
43 42
43#ifdef __KERNEL__
44#include <asm/cio.h>
45
44static inline int chp_id_is_valid(struct chp_id *chpid) 46static inline int chp_id_is_valid(struct chp_id *chpid)
45{ 47{
46 return (chpid->cssid <= __MAX_CSSID); 48 return (chpid->cssid <= __MAX_CSSID);
@@ -49,5 +51,6 @@ static inline int chp_id_is_valid(struct chp_id *chpid)
49 51
50#define chp_id_for_each(c) \ 52#define chp_id_for_each(c) \
51 for (chp_id_init(c); chp_id_is_valid(c); chp_id_next(c)) 53 for (chp_id_init(c); chp_id_is_valid(c); chp_id_next(c))
54#endif /* __KERNEL */
52 55
53#endif /* _ASM_S390_CHPID_H */ 56#endif /* _ASM_S390_CHPID_H */
diff --git a/include/asm-s390/chsc.h b/include/asm-s390/chsc.h
new file mode 100644
index 000000000000..d38d0cf62d4b
--- /dev/null
+++ b/include/asm-s390/chsc.h
@@ -0,0 +1,127 @@
1/*
2 * ioctl interface for /dev/chsc
3 *
4 * Copyright 2008 IBM Corp.
5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
6 */
7
8#ifndef _ASM_CHSC_H
9#define _ASM_CHSC_H
10
11#include <asm/chpid.h>
12#include <asm/schid.h>
13
14struct chsc_async_header {
15 __u16 length;
16 __u16 code;
17 __u32 cmd_dependend;
18 __u32 key : 4;
19 __u32 : 28;
20 struct subchannel_id sid;
21} __attribute__ ((packed));
22
23struct chsc_async_area {
24 struct chsc_async_header header;
25 __u8 data[PAGE_SIZE - 16 /* size of chsc_async_header */];
26} __attribute__ ((packed));
27
28
29struct chsc_response_struct {
30 __u16 length;
31 __u16 code;
32 __u32 parms;
33 __u8 data[PAGE_SIZE - 8];
34} __attribute__ ((packed));
35
36struct chsc_chp_cd {
37 struct chp_id chpid;
38 int m;
39 int fmt;
40 struct chsc_response_struct cpcb;
41};
42
43struct chsc_cu_cd {
44 __u16 cun;
45 __u8 cssid;
46 int m;
47 int fmt;
48 struct chsc_response_struct cucb;
49};
50
51struct chsc_sch_cud {
52 struct subchannel_id schid;
53 int fmt;
54 struct chsc_response_struct scub;
55};
56
57struct conf_id {
58 int m;
59 __u8 cssid;
60 __u8 ssid;
61};
62
63struct chsc_conf_info {
64 struct conf_id id;
65 int fmt;
66 struct chsc_response_struct scid;
67};
68
69struct ccl_parm_chpid {
70 int m;
71 struct chp_id chp;
72};
73
74struct ccl_parm_cssids {
75 __u8 f_cssid;
76 __u8 l_cssid;
77};
78
79struct chsc_comp_list {
80 struct {
81 enum {
82 CCL_CU_ON_CHP = 1,
83 CCL_CHP_TYPE_CAP = 2,
84 CCL_CSS_IMG = 4,
85 CCL_CSS_IMG_CONF_CHAR = 5,
86 CCL_IOP_CHP = 6,
87 } ctype;
88 int fmt;
89 struct ccl_parm_chpid chpid;
90 struct ccl_parm_cssids cssids;
91 } req;
92 struct chsc_response_struct sccl;
93};
94
95struct chsc_dcal {
96 struct {
97 enum {
98 DCAL_CSS_IID_PN = 4,
99 } atype;
100 __u32 list_parm[2];
101 int fmt;
102 } req;
103 struct chsc_response_struct sdcal;
104};
105
106struct chsc_cpd_info {
107 struct chp_id chpid;
108 int m;
109 int fmt;
110 int rfmt;
111 int c;
112 struct chsc_response_struct chpdb;
113};
114
115#define CHSC_IOCTL_MAGIC 'c'
116
117#define CHSC_START _IOWR(CHSC_IOCTL_MAGIC, 0x81, struct chsc_async_area)
118#define CHSC_INFO_CHANNEL_PATH _IOWR(CHSC_IOCTL_MAGIC, 0x82, \
119 struct chsc_chp_cd)
120#define CHSC_INFO_CU _IOWR(CHSC_IOCTL_MAGIC, 0x83, struct chsc_cu_cd)
121#define CHSC_INFO_SCH_CU _IOWR(CHSC_IOCTL_MAGIC, 0x84, struct chsc_sch_cud)
122#define CHSC_INFO_CI _IOWR(CHSC_IOCTL_MAGIC, 0x85, struct chsc_conf_info)
123#define CHSC_INFO_CCL _IOWR(CHSC_IOCTL_MAGIC, 0x86, struct chsc_comp_list)
124#define CHSC_INFO_CPD _IOWR(CHSC_IOCTL_MAGIC, 0x87, struct chsc_cpd_info)
125#define CHSC_INFO_DCAL _IOWR(CHSC_IOCTL_MAGIC, 0x88, struct chsc_dcal)
126
127#endif
diff --git a/include/asm-s390/cio.h b/include/asm-s390/cio.h
index 0818ecd30ca6..6dccb071aec3 100644
--- a/include/asm-s390/cio.h
+++ b/include/asm-s390/cio.h
@@ -16,7 +16,7 @@
16#define __MAX_CSSID 0 16#define __MAX_CSSID 0
17 17
18/** 18/**
19 * struct scsw - subchannel status word 19 * struct cmd_scsw - command-mode subchannel status word
20 * @key: subchannel key 20 * @key: subchannel key
21 * @sctl: suspend control 21 * @sctl: suspend control
22 * @eswf: esw format 22 * @eswf: esw format
@@ -38,7 +38,7 @@
38 * @cstat: subchannel status 38 * @cstat: subchannel status
39 * @count: residual count 39 * @count: residual count
40 */ 40 */
41struct scsw { 41struct cmd_scsw {
42 __u32 key : 4; 42 __u32 key : 4;
43 __u32 sctl : 1; 43 __u32 sctl : 1;
44 __u32 eswf : 1; 44 __u32 eswf : 1;
@@ -61,6 +61,114 @@ struct scsw {
61 __u32 count : 16; 61 __u32 count : 16;
62} __attribute__ ((packed)); 62} __attribute__ ((packed));
63 63
64/**
65 * struct tm_scsw - transport-mode subchannel status word
66 * @key: subchannel key
67 * @eswf: esw format
68 * @cc: deferred condition code
69 * @fmt: format
70 * @x: IRB-format control
71 * @q: interrogate-complete
72 * @ectl: extended control
73 * @pno: path not operational
74 * @fctl: function control
75 * @actl: activity control
76 * @stctl: status control
77 * @tcw: TCW address
78 * @dstat: device status
79 * @cstat: subchannel status
80 * @fcxs: FCX status
81 * @schxs: subchannel-extended status
82 */
83struct tm_scsw {
84 u32 key:4;
85 u32 :1;
86 u32 eswf:1;
87 u32 cc:2;
88 u32 fmt:3;
89 u32 x:1;
90 u32 q:1;
91 u32 :1;
92 u32 ectl:1;
93 u32 pno:1;
94 u32 :1;
95 u32 fctl:3;
96 u32 actl:7;
97 u32 stctl:5;
98 u32 tcw;
99 u32 dstat:8;
100 u32 cstat:8;
101 u32 fcxs:8;
102 u32 schxs:8;
103} __attribute__ ((packed));
104
105/**
106 * union scsw - subchannel status word
107 * @cmd: command-mode SCSW
108 * @tm: transport-mode SCSW
109 */
110union scsw {
111 struct cmd_scsw cmd;
112 struct tm_scsw tm;
113} __attribute__ ((packed));
114
115int scsw_is_tm(union scsw *scsw);
116u32 scsw_key(union scsw *scsw);
117u32 scsw_eswf(union scsw *scsw);
118u32 scsw_cc(union scsw *scsw);
119u32 scsw_ectl(union scsw *scsw);
120u32 scsw_pno(union scsw *scsw);
121u32 scsw_fctl(union scsw *scsw);
122u32 scsw_actl(union scsw *scsw);
123u32 scsw_stctl(union scsw *scsw);
124u32 scsw_dstat(union scsw *scsw);
125u32 scsw_cstat(union scsw *scsw);
126int scsw_is_solicited(union scsw *scsw);
127int scsw_is_valid_key(union scsw *scsw);
128int scsw_is_valid_eswf(union scsw *scsw);
129int scsw_is_valid_cc(union scsw *scsw);
130int scsw_is_valid_ectl(union scsw *scsw);
131int scsw_is_valid_pno(union scsw *scsw);
132int scsw_is_valid_fctl(union scsw *scsw);
133int scsw_is_valid_actl(union scsw *scsw);
134int scsw_is_valid_stctl(union scsw *scsw);
135int scsw_is_valid_dstat(union scsw *scsw);
136int scsw_is_valid_cstat(union scsw *scsw);
137int scsw_cmd_is_valid_key(union scsw *scsw);
138int scsw_cmd_is_valid_sctl(union scsw *scsw);
139int scsw_cmd_is_valid_eswf(union scsw *scsw);
140int scsw_cmd_is_valid_cc(union scsw *scsw);
141int scsw_cmd_is_valid_fmt(union scsw *scsw);
142int scsw_cmd_is_valid_pfch(union scsw *scsw);
143int scsw_cmd_is_valid_isic(union scsw *scsw);
144int scsw_cmd_is_valid_alcc(union scsw *scsw);
145int scsw_cmd_is_valid_ssi(union scsw *scsw);
146int scsw_cmd_is_valid_zcc(union scsw *scsw);
147int scsw_cmd_is_valid_ectl(union scsw *scsw);
148int scsw_cmd_is_valid_pno(union scsw *scsw);
149int scsw_cmd_is_valid_fctl(union scsw *scsw);
150int scsw_cmd_is_valid_actl(union scsw *scsw);
151int scsw_cmd_is_valid_stctl(union scsw *scsw);
152int scsw_cmd_is_valid_dstat(union scsw *scsw);
153int scsw_cmd_is_valid_cstat(union scsw *scsw);
154int scsw_cmd_is_solicited(union scsw *scsw);
155int scsw_tm_is_valid_key(union scsw *scsw);
156int scsw_tm_is_valid_eswf(union scsw *scsw);
157int scsw_tm_is_valid_cc(union scsw *scsw);
158int scsw_tm_is_valid_fmt(union scsw *scsw);
159int scsw_tm_is_valid_x(union scsw *scsw);
160int scsw_tm_is_valid_q(union scsw *scsw);
161int scsw_tm_is_valid_ectl(union scsw *scsw);
162int scsw_tm_is_valid_pno(union scsw *scsw);
163int scsw_tm_is_valid_fctl(union scsw *scsw);
164int scsw_tm_is_valid_actl(union scsw *scsw);
165int scsw_tm_is_valid_stctl(union scsw *scsw);
166int scsw_tm_is_valid_dstat(union scsw *scsw);
167int scsw_tm_is_valid_cstat(union scsw *scsw);
168int scsw_tm_is_valid_fcxs(union scsw *scsw);
169int scsw_tm_is_valid_schxs(union scsw *scsw);
170int scsw_tm_is_solicited(union scsw *scsw);
171
64#define SCSW_FCTL_CLEAR_FUNC 0x1 172#define SCSW_FCTL_CLEAR_FUNC 0x1
65#define SCSW_FCTL_HALT_FUNC 0x2 173#define SCSW_FCTL_HALT_FUNC 0x2
66#define SCSW_FCTL_START_FUNC 0x4 174#define SCSW_FCTL_START_FUNC 0x4
@@ -303,7 +411,7 @@ struct esw3 {
303 * if applicable). 411 * if applicable).
304 */ 412 */
305struct irb { 413struct irb {
306 struct scsw scsw; 414 union scsw scsw;
307 union { 415 union {
308 struct esw0 esw0; 416 struct esw0 esw0;
309 struct esw1 esw1; 417 struct esw1 esw1;
diff --git a/include/asm-s390/elf.h b/include/asm-s390/elf.h
index b3ac262c4582..3cad56923815 100644
--- a/include/asm-s390/elf.h
+++ b/include/asm-s390/elf.h
@@ -113,6 +113,9 @@
113typedef s390_fp_regs elf_fpregset_t; 113typedef s390_fp_regs elf_fpregset_t;
114typedef s390_regs elf_gregset_t; 114typedef s390_regs elf_gregset_t;
115 115
116typedef s390_fp_regs compat_elf_fpregset_t;
117typedef s390_compat_regs compat_elf_gregset_t;
118
116#include <linux/sched.h> /* for task_struct */ 119#include <linux/sched.h> /* for task_struct */
117#include <asm/system.h> /* for save_access_regs */ 120#include <asm/system.h> /* for save_access_regs */
118#include <asm/mmu_context.h> 121#include <asm/mmu_context.h>
@@ -123,6 +126,10 @@ typedef s390_regs elf_gregset_t;
123#define elf_check_arch(x) \ 126#define elf_check_arch(x) \
124 (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \ 127 (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
125 && (x)->e_ident[EI_CLASS] == ELF_CLASS) 128 && (x)->e_ident[EI_CLASS] == ELF_CLASS)
129#define compat_elf_check_arch(x) \
130 (((x)->e_machine == EM_S390 || (x)->e_machine == EM_S390_OLD) \
131 && (x)->e_ident[EI_CLASS] == ELF_CLASS)
132#define compat_start_thread start_thread31
126 133
127/* For SVR4/S390 the function pointer to be registered with `atexit` is 134/* For SVR4/S390 the function pointer to be registered with `atexit` is
128 passed in R14. */ 135 passed in R14. */
@@ -131,6 +138,7 @@ typedef s390_regs elf_gregset_t;
131 _r->gprs[14] = 0; \ 138 _r->gprs[14] = 0; \
132 } while (0) 139 } while (0)
133 140
141#define CORE_DUMP_USE_REGSET
134#define USE_ELF_CORE_DUMP 142#define USE_ELF_CORE_DUMP
135#define ELF_EXEC_PAGESIZE 4096 143#define ELF_EXEC_PAGESIZE 4096
136 144
@@ -140,44 +148,6 @@ typedef s390_regs elf_gregset_t;
140 that it will "exec", and that there is sufficient room for the brk. */ 148 that it will "exec", and that there is sufficient room for the brk. */
141#define ELF_ET_DYN_BASE (STACK_TOP / 3 * 2) 149#define ELF_ET_DYN_BASE (STACK_TOP / 3 * 2)
142 150
143/* Wow, the "main" arch needs arch dependent functions too.. :) */
144
145/* regs is struct pt_regs, pr_reg is elf_gregset_t (which is
146 now struct_user_regs, they are different) */
147
148static inline int dump_regs(struct pt_regs *ptregs, elf_gregset_t *regs)
149{
150 memcpy(&regs->psw, &ptregs->psw, sizeof(regs->psw)+sizeof(regs->gprs));
151 save_access_regs(regs->acrs);
152 regs->orig_gpr2 = ptregs->orig_gpr2;
153 return 1;
154}
155
156#define ELF_CORE_COPY_REGS(pr_reg, regs) dump_regs(regs, &pr_reg);
157
158static inline int dump_task_regs(struct task_struct *tsk, elf_gregset_t *regs)
159{
160 struct pt_regs *ptregs = task_pt_regs(tsk);
161 memcpy(&regs->psw, &ptregs->psw, sizeof(regs->psw)+sizeof(regs->gprs));
162 memcpy(regs->acrs, tsk->thread.acrs, sizeof(regs->acrs));
163 regs->orig_gpr2 = ptregs->orig_gpr2;
164 return 1;
165}
166
167#define ELF_CORE_COPY_TASK_REGS(tsk, regs) dump_task_regs(tsk, regs)
168
169static inline int dump_task_fpu(struct task_struct *tsk, elf_fpregset_t *fpregs)
170{
171 if (tsk == current)
172 save_fp_regs(fpregs);
173 else
174 memcpy(fpregs, &tsk->thread.fp_regs, sizeof(elf_fpregset_t));
175 return 1;
176}
177
178#define ELF_CORE_COPY_FPREGS(tsk, fpregs) dump_task_fpu(tsk, fpregs)
179
180
181/* This yields a mask that user programs can use to figure out what 151/* This yields a mask that user programs can use to figure out what
182 instruction set this CPU supports. */ 152 instruction set this CPU supports. */
183 153
@@ -204,7 +174,10 @@ do { \
204 set_personality(PER_SVR4); \ 174 set_personality(PER_SVR4); \
205 else if (current->personality != PER_LINUX32) \ 175 else if (current->personality != PER_LINUX32) \
206 set_personality(PER_LINUX); \ 176 set_personality(PER_LINUX); \
207 clear_thread_flag(TIF_31BIT); \ 177 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
178 set_thread_flag(TIF_31BIT); \
179 else \
180 clear_thread_flag(TIF_31BIT); \
208} while (0) 181} while (0)
209#endif /* __s390x__ */ 182#endif /* __s390x__ */
210 183
diff --git a/include/asm-s390/etr.h b/include/asm-s390/etr.h
index b498f19bb9a7..80ef58c61970 100644
--- a/include/asm-s390/etr.h
+++ b/include/asm-s390/etr.h
@@ -122,7 +122,7 @@ struct etr_aib {
122} __attribute__ ((packed,aligned(8))); 122} __attribute__ ((packed,aligned(8)));
123 123
124/* ETR interruption parameter */ 124/* ETR interruption parameter */
125struct etr_interruption_parameter { 125struct etr_irq_parm {
126 unsigned int _pad0 : 8; 126 unsigned int _pad0 : 8;
127 unsigned int pc0 : 1; /* port 0 state change */ 127 unsigned int pc0 : 1; /* port 0 state change */
128 unsigned int pc1 : 1; /* port 1 state change */ 128 unsigned int pc1 : 1; /* port 1 state change */
@@ -213,7 +213,46 @@ static inline int etr_ptff(void *ptff_block, unsigned int func)
213#define ETR_PTFF_SGS 0x43 /* set gross steering rate */ 213#define ETR_PTFF_SGS 0x43 /* set gross steering rate */
214 214
215/* Functions needed by the machine check handler */ 215/* Functions needed by the machine check handler */
216extern void etr_switch_to_local(void); 216void etr_switch_to_local(void);
217extern void etr_sync_check(void); 217void etr_sync_check(void);
218
219/* STP interruption parameter */
220struct stp_irq_parm {
221 unsigned int _pad0 : 14;
222 unsigned int tsc : 1; /* Timing status change */
223 unsigned int lac : 1; /* Link availability change */
224 unsigned int tcpc : 1; /* Time control parameter change */
225 unsigned int _pad2 : 15;
226} __attribute__ ((packed));
227
228#define STP_OP_SYNC 1
229#define STP_OP_CTRL 3
230
231struct stp_sstpi {
232 unsigned int rsvd0;
233 unsigned int rsvd1 : 8;
234 unsigned int stratum : 8;
235 unsigned int vbits : 16;
236 unsigned int leaps : 16;
237 unsigned int tmd : 4;
238 unsigned int ctn : 4;
239 unsigned int rsvd2 : 3;
240 unsigned int c : 1;
241 unsigned int tst : 4;
242 unsigned int tzo : 16;
243 unsigned int dsto : 16;
244 unsigned int ctrl : 16;
245 unsigned int rsvd3 : 16;
246 unsigned int tto;
247 unsigned int rsvd4;
248 unsigned int ctnid[3];
249 unsigned int rsvd5;
250 unsigned int todoff[4];
251 unsigned int rsvd6[48];
252} __attribute__ ((packed));
253
254/* Functions needed by the machine check handler */
255void stp_sync_check(void);
256void stp_island_check(void);
218 257
219#endif /* __S390_ETR_H */ 258#endif /* __S390_ETR_H */
diff --git a/include/asm-s390/fcx.h b/include/asm-s390/fcx.h
new file mode 100644
index 000000000000..8be1f3a58042
--- /dev/null
+++ b/include/asm-s390/fcx.h
@@ -0,0 +1,311 @@
1/*
2 * Functions for assembling fcx enabled I/O control blocks.
3 *
4 * Copyright IBM Corp. 2008
5 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_FCX_H
9#define _ASM_S390_FCX_H _ASM_S390_FCX_H
10
11#include <linux/types.h>
12
13#define TCW_FORMAT_DEFAULT 0
14#define TCW_TIDAW_FORMAT_DEFAULT 0
15#define TCW_FLAGS_INPUT_TIDA 1 << (23 - 5)
16#define TCW_FLAGS_TCCB_TIDA 1 << (23 - 6)
17#define TCW_FLAGS_OUTPUT_TIDA 1 << (23 - 7)
18#define TCW_FLAGS_TIDAW_FORMAT(x) ((x) & 3) << (23 - 9)
19#define TCW_FLAGS_GET_TIDAW_FORMAT(x) (((x) >> (23 - 9)) & 3)
20
21/**
22 * struct tcw - Transport Control Word (TCW)
23 * @format: TCW format
24 * @flags: TCW flags
25 * @tccbl: Transport-Command-Control-Block Length
26 * @r: Read Operations
27 * @w: Write Operations
28 * @output: Output-Data Address
29 * @input: Input-Data Address
30 * @tsb: Transport-Status-Block Address
31 * @tccb: Transport-Command-Control-Block Address
32 * @output_count: Output Count
33 * @input_count: Input Count
34 * @intrg: Interrogate TCW Address
35 */
36struct tcw {
37 u32 format:2;
38 u32 :6;
39 u32 flags:24;
40 u32 :8;
41 u32 tccbl:6;
42 u32 r:1;
43 u32 w:1;
44 u32 :16;
45 u64 output;
46 u64 input;
47 u64 tsb;
48 u64 tccb;
49 u32 output_count;
50 u32 input_count;
51 u32 :32;
52 u32 :32;
53 u32 :32;
54 u32 intrg;
55} __attribute__ ((packed, aligned(64)));
56
57#define TIDAW_FLAGS_LAST 1 << (7 - 0)
58#define TIDAW_FLAGS_SKIP 1 << (7 - 1)
59#define TIDAW_FLAGS_DATA_INT 1 << (7 - 2)
60#define TIDAW_FLAGS_TTIC 1 << (7 - 3)
61#define TIDAW_FLAGS_INSERT_CBC 1 << (7 - 4)
62
63/**
64 * struct tidaw - Transport-Indirect-Addressing Word (TIDAW)
65 * @flags: TIDAW flags. Can be an arithmetic OR of the following constants:
66 * %TIDAW_FLAGS_LAST, %TIDAW_FLAGS_SKIP, %TIDAW_FLAGS_DATA_INT,
67 * %TIDAW_FLAGS_TTIC, %TIDAW_FLAGS_INSERT_CBC
68 * @count: Count
69 * @addr: Address
70 */
71struct tidaw {
72 u32 flags:8;
73 u32 :24;
74 u32 count;
75 u64 addr;
76} __attribute__ ((packed, aligned(16)));
77
78/**
79 * struct tsa_iostat - I/O-Status Transport-Status Area (IO-Stat TSA)
80 * @dev_time: Device Time
81 * @def_time: Defer Time
82 * @queue_time: Queue Time
83 * @dev_busy_time: Device-Busy Time
84 * @dev_act_time: Device-Active-Only Time
85 * @sense: Sense Data (if present)
86 */
87struct tsa_iostat {
88 u32 dev_time;
89 u32 def_time;
90 u32 queue_time;
91 u32 dev_busy_time;
92 u32 dev_act_time;
93 u8 sense[32];
94} __attribute__ ((packed));
95
96/**
97 * struct tsa_ddpcs - Device-Detected-Program-Check Transport-Status Area (DDPC TSA)
98 * @rc: Reason Code
99 * @rcq: Reason Code Qualifier
100 * @sense: Sense Data (if present)
101 */
102struct tsa_ddpc {
103 u32 :24;
104 u32 rc:8;
105 u8 rcq[16];
106 u8 sense[32];
107} __attribute__ ((packed));
108
109#define TSA_INTRG_FLAGS_CU_STATE_VALID 1 << (7 - 0)
110#define TSA_INTRG_FLAGS_DEV_STATE_VALID 1 << (7 - 1)
111#define TSA_INTRG_FLAGS_OP_STATE_VALID 1 << (7 - 2)
112
113/**
114 * struct tsa_intrg - Interrogate Transport-Status Area (Intrg. TSA)
115 * @format: Format
116 * @flags: Flags. Can be an arithmetic OR of the following constants:
117 * %TSA_INTRG_FLAGS_CU_STATE_VALID, %TSA_INTRG_FLAGS_DEV_STATE_VALID,
118 * %TSA_INTRG_FLAGS_OP_STATE_VALID
119 * @cu_state: Controle-Unit State
120 * @dev_state: Device State
121 * @op_state: Operation State
122 * @sd_info: State-Dependent Information
123 * @dl_id: Device-Level Identifier
124 * @dd_data: Device-Dependent Data
125 */
126struct tsa_intrg {
127 u32 format:8;
128 u32 flags:8;
129 u32 cu_state:8;
130 u32 dev_state:8;
131 u32 op_state:8;
132 u32 :24;
133 u8 sd_info[12];
134 u32 dl_id;
135 u8 dd_data[28];
136} __attribute__ ((packed));
137
138#define TSB_FORMAT_NONE 0
139#define TSB_FORMAT_IOSTAT 1
140#define TSB_FORMAT_DDPC 2
141#define TSB_FORMAT_INTRG 3
142
143#define TSB_FLAGS_DCW_OFFSET_VALID 1 << (7 - 0)
144#define TSB_FLAGS_COUNT_VALID 1 << (7 - 1)
145#define TSB_FLAGS_CACHE_MISS 1 << (7 - 2)
146#define TSB_FLAGS_TIME_VALID 1 << (7 - 3)
147#define TSB_FLAGS_FORMAT(x) ((x) & 7)
148#define TSB_FORMAT(t) ((t)->flags & 7)
149
150/**
151 * struct tsb - Transport-Status Block (TSB)
152 * @length: Length
153 * @flags: Flags. Can be an arithmetic OR of the following constants:
154 * %TSB_FLAGS_DCW_OFFSET_VALID, %TSB_FLAGS_COUNT_VALID, %TSB_FLAGS_CACHE_MISS,
155 * %TSB_FLAGS_TIME_VALID
156 * @dcw_offset: DCW Offset
157 * @count: Count
158 * @tsa: Transport-Status-Area
159 */
160struct tsb {
161 u32 length:8;
162 u32 flags:8;
163 u32 dcw_offset:16;
164 u32 count;
165 u32 :32;
166 union {
167 struct tsa_iostat iostat;
168 struct tsa_ddpc ddpc;
169 struct tsa_intrg intrg;
170 } __attribute__ ((packed)) tsa;
171} __attribute__ ((packed, aligned(8)));
172
173#define DCW_INTRG_FORMAT_DEFAULT 0
174
175#define DCW_INTRG_RC_UNSPECIFIED 0
176#define DCW_INTRG_RC_TIMEOUT 1
177
178#define DCW_INTRG_RCQ_UNSPECIFIED 0
179#define DCW_INTRG_RCQ_PRIMARY 1
180#define DCW_INTRG_RCQ_SECONDARY 2
181
182#define DCW_INTRG_FLAGS_MPM 1 < (7 - 0)
183#define DCW_INTRG_FLAGS_PPR 1 < (7 - 1)
184#define DCW_INTRG_FLAGS_CRIT 1 < (7 - 2)
185
186/**
187 * struct dcw_intrg_data - Interrogate DCW data
188 * @format: Format. Should be %DCW_INTRG_FORMAT_DEFAULT
189 * @rc: Reason Code. Can be one of %DCW_INTRG_RC_UNSPECIFIED,
190 * %DCW_INTRG_RC_TIMEOUT
191 * @rcq: Reason Code Qualifier: Can be one of %DCW_INTRG_RCQ_UNSPECIFIED,
192 * %DCW_INTRG_RCQ_PRIMARY, %DCW_INTRG_RCQ_SECONDARY
193 * @lpm: Logical-Path Mask
194 * @pam: Path-Available Mask
195 * @pim: Path-Installed Mask
196 * @timeout: Timeout
197 * @flags: Flags. Can be an arithmetic OR of %DCW_INTRG_FLAGS_MPM,
198 * %DCW_INTRG_FLAGS_PPR, %DCW_INTRG_FLAGS_CRIT
199 * @time: Time
200 * @prog_id: Program Identifier
201 * @prog_data: Program-Dependent Data
202 */
203struct dcw_intrg_data {
204 u32 format:8;
205 u32 rc:8;
206 u32 rcq:8;
207 u32 lpm:8;
208 u32 pam:8;
209 u32 pim:8;
210 u32 timeout:16;
211 u32 flags:8;
212 u32 :24;
213 u32 :32;
214 u64 time;
215 u64 prog_id;
216 u8 prog_data[0];
217} __attribute__ ((packed));
218
219#define DCW_FLAGS_CC 1 << (7 - 1)
220
221#define DCW_CMD_WRITE 0x01
222#define DCW_CMD_READ 0x02
223#define DCW_CMD_CONTROL 0x03
224#define DCW_CMD_SENSE 0x04
225#define DCW_CMD_SENSE_ID 0xe4
226#define DCW_CMD_INTRG 0x40
227
228/**
229 * struct dcw - Device-Command Word (DCW)
230 * @cmd: Command Code. Can be one of %DCW_CMD_WRITE, %DCW_CMD_READ,
231 * %DCW_CMD_CONTROL, %DCW_CMD_SENSE, %DCW_CMD_SENSE_ID, %DCW_CMD_INTRG
232 * @flags: Flags. Can be an arithmetic OR of %DCW_FLAGS_CC
233 * @cd_count: Control-Data Count
234 * @count: Count
235 * @cd: Control Data
236 */
237struct dcw {
238 u32 cmd:8;
239 u32 flags:8;
240 u32 :8;
241 u32 cd_count:8;
242 u32 count;
243 u8 cd[0];
244} __attribute__ ((packed));
245
246#define TCCB_FORMAT_DEFAULT 0x7f
247#define TCCB_MAX_DCW 30
248#define TCCB_MAX_SIZE (sizeof(struct tccb_tcah) + \
249 TCCB_MAX_DCW * sizeof(struct dcw) + \
250 sizeof(struct tccb_tcat))
251#define TCCB_SAC_DEFAULT 0xf901
252#define TCCB_SAC_INTRG 0xf902
253
254/**
255 * struct tccb_tcah - Transport-Command-Area Header (TCAH)
256 * @format: Format. Should be %TCCB_FORMAT_DEFAULT
257 * @tcal: Transport-Command-Area Length
258 * @sac: Service-Action Code. Can be one of %TCCB_SAC_DEFAULT, %TCCB_SAC_INTRG
259 * @prio: Priority
260 */
261struct tccb_tcah {
262 u32 format:8;
263 u32 :24;
264 u32 :24;
265 u32 tcal:8;
266 u32 sac:16;
267 u32 :8;
268 u32 prio:8;
269 u32 :32;
270} __attribute__ ((packed));
271
272/**
273 * struct tccb_tcat - Transport-Command-Area Trailer (TCAT)
274 * @count: Transport Count
275 */
276struct tccb_tcat {
277 u32 :32;
278 u32 count;
279} __attribute__ ((packed));
280
281/**
282 * struct tccb - (partial) Transport-Command-Control Block (TCCB)
283 * @tcah: TCAH
284 * @tca: Transport-Command Area
285 */
286struct tccb {
287 struct tccb_tcah tcah;
288 u8 tca[0];
289} __attribute__ ((packed, aligned(8)));
290
291struct tcw *tcw_get_intrg(struct tcw *tcw);
292void *tcw_get_data(struct tcw *tcw);
293struct tccb *tcw_get_tccb(struct tcw *tcw);
294struct tsb *tcw_get_tsb(struct tcw *tcw);
295
296void tcw_init(struct tcw *tcw, int r, int w);
297void tcw_finalize(struct tcw *tcw, int num_tidaws);
298
299void tcw_set_intrg(struct tcw *tcw, struct tcw *intrg_tcw);
300void tcw_set_data(struct tcw *tcw, void *data, int use_tidal);
301void tcw_set_tccb(struct tcw *tcw, struct tccb *tccb);
302void tcw_set_tsb(struct tcw *tcw, struct tsb *tsb);
303
304void tccb_init(struct tccb *tccb, size_t tccb_size, u32 sac);
305void tsb_init(struct tsb *tsb);
306struct dcw *tccb_add_dcw(struct tccb *tccb, size_t tccb_size, u8 cmd, u8 flags,
307 void *cd, u8 cd_count, u32 count);
308struct tidaw *tcw_add_tidaw(struct tcw *tcw, int num_tidaws, u8 flags,
309 void *addr, u32 count);
310
311#endif /* _ASM_S390_FCX_H */
diff --git a/include/asm-s390/ipl.h b/include/asm-s390/ipl.h
index c1b2e50392bb..eaca6dff5405 100644
--- a/include/asm-s390/ipl.h
+++ b/include/asm-s390/ipl.h
@@ -56,15 +56,19 @@ struct ipl_block_fcp {
56 u8 scp_data[]; 56 u8 scp_data[];
57} __attribute__((packed)); 57} __attribute__((packed));
58 58
59#define DIAG308_VMPARM_SIZE 64
60
59struct ipl_block_ccw { 61struct ipl_block_ccw {
60 u8 load_param[8]; 62 u8 load_parm[8];
61 u8 reserved1[84]; 63 u8 reserved1[84];
62 u8 reserved2[2]; 64 u8 reserved2[2];
63 u16 devno; 65 u16 devno;
64 u8 vm_flags; 66 u8 vm_flags;
65 u8 reserved3[3]; 67 u8 reserved3[3];
66 u32 vm_parm_len; 68 u32 vm_parm_len;
67 u8 reserved4[80]; 69 u8 nss_name[8];
70 u8 vm_parm[DIAG308_VMPARM_SIZE];
71 u8 reserved4[8];
68} __attribute__((packed)); 72} __attribute__((packed));
69 73
70struct ipl_parameter_block { 74struct ipl_parameter_block {
@@ -73,7 +77,7 @@ struct ipl_parameter_block {
73 struct ipl_block_fcp fcp; 77 struct ipl_block_fcp fcp;
74 struct ipl_block_ccw ccw; 78 struct ipl_block_ccw ccw;
75 } ipl_info; 79 } ipl_info;
76} __attribute__((packed)); 80} __attribute__((packed,aligned(4096)));
77 81
78/* 82/*
79 * IPL validity flags 83 * IPL validity flags
@@ -86,6 +90,8 @@ extern void do_reipl(void);
86extern void do_halt(void); 90extern void do_halt(void);
87extern void do_poff(void); 91extern void do_poff(void);
88extern void ipl_save_parameters(void); 92extern void ipl_save_parameters(void);
93extern void ipl_update_parameters(void);
94extern void get_ipl_vmparm(char *);
89 95
90enum { 96enum {
91 IPL_DEVNO_VALID = 1, 97 IPL_DEVNO_VALID = 1,
@@ -147,6 +153,11 @@ enum diag308_flags {
147 DIAG308_FLAGS_LP_VALID = 0x80, 153 DIAG308_FLAGS_LP_VALID = 0x80,
148}; 154};
149 155
156enum diag308_vm_flags {
157 DIAG308_VM_FLAGS_NSS_VALID = 0x80,
158 DIAG308_VM_FLAGS_VP_VALID = 0x40,
159};
160
150enum diag308_rc { 161enum diag308_rc {
151 DIAG308_RC_OK = 1, 162 DIAG308_RC_OK = 1,
152}; 163};
diff --git a/include/asm-s390/isc.h b/include/asm-s390/isc.h
new file mode 100644
index 000000000000..34bb8916db4f
--- /dev/null
+++ b/include/asm-s390/isc.h
@@ -0,0 +1,25 @@
1#ifndef _ASM_S390_ISC_H
2#define _ASM_S390_ISC_H
3
4#include <linux/types.h>
5
6/*
7 * I/O interruption subclasses used by drivers.
8 * Please add all used iscs here so that it is possible to distribute
9 * isc usage between drivers.
10 * Reminder: 0 is highest priority, 7 lowest.
11 */
12#define MAX_ISC 7
13
14/* Regular I/O interrupts. */
15#define IO_SCH_ISC 3 /* regular I/O subchannels */
16#define CONSOLE_ISC 1 /* console I/O subchannel */
17#define CHSC_SCH_ISC 7 /* CHSC subchannels */
18/* Adapter interrupts. */
19#define QDIO_AIRQ_ISC IO_SCH_ISC /* I/O subchannel in qdio mode */
20
21/* Functions for registration of I/O interruption subclasses */
22void isc_register(unsigned int isc);
23void isc_unregister(unsigned int isc);
24
25#endif /* _ASM_S390_ISC_H */
diff --git a/include/asm-s390/itcw.h b/include/asm-s390/itcw.h
new file mode 100644
index 000000000000..a9bc5c36b32a
--- /dev/null
+++ b/include/asm-s390/itcw.h
@@ -0,0 +1,30 @@
1/*
2 * Functions for incremental construction of fcx enabled I/O control blocks.
3 *
4 * Copyright IBM Corp. 2008
5 * Author(s): Peter Oberparleiter <peter.oberparleiter@de.ibm.com>
6 */
7
8#ifndef _ASM_S390_ITCW_H
9#define _ASM_S390_ITCW_H _ASM_S390_ITCW_H
10
11#include <linux/types.h>
12#include <asm/fcx.h>
13
14#define ITCW_OP_READ 0
15#define ITCW_OP_WRITE 1
16
17struct itcw;
18
19struct tcw *itcw_get_tcw(struct itcw *itcw);
20size_t itcw_calc_size(int intrg, int max_tidaws, int intrg_max_tidaws);
21struct itcw *itcw_init(void *buffer, size_t size, int op, int intrg,
22 int max_tidaws, int intrg_max_tidaws);
23struct dcw *itcw_add_dcw(struct itcw *itcw, u8 cmd, u8 flags, void *cd,
24 u8 cd_count, u32 count);
25struct tidaw *itcw_add_tidaw(struct itcw *itcw, u8 flags, void *addr,
26 u32 count);
27void itcw_set_data(struct itcw *itcw, void *addr, int use_tidal);
28void itcw_finalize(struct itcw *itcw);
29
30#endif /* _ASM_S390_ITCW_H */
diff --git a/include/asm-s390/pgtable.h b/include/asm-s390/pgtable.h
index c7f4f8e3e297..0bdb704ae051 100644
--- a/include/asm-s390/pgtable.h
+++ b/include/asm-s390/pgtable.h
@@ -29,6 +29,7 @@
29 * the S390 page table tree. 29 * the S390 page table tree.
30 */ 30 */
31#ifndef __ASSEMBLY__ 31#ifndef __ASSEMBLY__
32#include <linux/sched.h>
32#include <linux/mm_types.h> 33#include <linux/mm_types.h>
33#include <asm/bitops.h> 34#include <asm/bitops.h>
34#include <asm/bug.h> 35#include <asm/bug.h>
@@ -223,6 +224,9 @@ extern char empty_zero_page[PAGE_SIZE];
223#define _PAGE_SPECIAL 0x004 /* SW associated with special page */ 224#define _PAGE_SPECIAL 0x004 /* SW associated with special page */
224#define __HAVE_ARCH_PTE_SPECIAL 225#define __HAVE_ARCH_PTE_SPECIAL
225 226
227/* Set of bits not changed in pte_modify */
228#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL)
229
226/* Six different types of pages. */ 230/* Six different types of pages. */
227#define _PAGE_TYPE_EMPTY 0x400 231#define _PAGE_TYPE_EMPTY 0x400
228#define _PAGE_TYPE_NONE 0x401 232#define _PAGE_TYPE_NONE 0x401
@@ -681,7 +685,7 @@ static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *pt
681 */ 685 */
682static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 686static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
683{ 687{
684 pte_val(pte) &= PAGE_MASK; 688 pte_val(pte) &= _PAGE_CHG_MASK;
685 pte_val(pte) |= pgprot_val(newprot); 689 pte_val(pte) |= pgprot_val(newprot);
686 return pte; 690 return pte;
687} 691}
diff --git a/include/asm-s390/processor.h b/include/asm-s390/processor.h
index a00f79dd323b..4af80af2a88f 100644
--- a/include/asm-s390/processor.h
+++ b/include/asm-s390/processor.h
@@ -143,11 +143,19 @@ struct stack_frame {
143/* 143/*
144 * Do necessary setup to start up a new thread. 144 * Do necessary setup to start up a new thread.
145 */ 145 */
146#define start_thread(regs, new_psw, new_stackp) do { \ 146#define start_thread(regs, new_psw, new_stackp) do { \
147 set_fs(USER_DS); \ 147 set_fs(USER_DS); \
148 regs->psw.mask = psw_user_bits; \ 148 regs->psw.mask = psw_user_bits; \
149 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \ 149 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
150 regs->gprs[15] = new_stackp ; \ 150 regs->gprs[15] = new_stackp; \
151} while (0)
152
153#define start_thread31(regs, new_psw, new_stackp) do { \
154 set_fs(USER_DS); \
155 regs->psw.mask = psw_user32_bits; \
156 regs->psw.addr = new_psw | PSW_ADDR_AMODE; \
157 regs->gprs[15] = new_stackp; \
158 crst_table_downgrade(current->mm, 1UL << 31); \
151} while (0) 159} while (0)
152 160
153/* Forward declaration, a strange C thing */ 161/* Forward declaration, a strange C thing */
@@ -328,16 +336,6 @@ extern void (*s390_base_mcck_handler_fn)(void);
328extern void (*s390_base_pgm_handler_fn)(void); 336extern void (*s390_base_pgm_handler_fn)(void);
329extern void (*s390_base_ext_handler_fn)(void); 337extern void (*s390_base_ext_handler_fn)(void);
330 338
331/*
332 * CPU idle notifier chain.
333 */
334#define S390_CPU_IDLE 0
335#define S390_CPU_NOT_IDLE 1
336
337struct notifier_block;
338int register_idle_notifier(struct notifier_block *nb);
339int unregister_idle_notifier(struct notifier_block *nb);
340
341#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL 339#define ARCH_LOW_ADDRESS_LIMIT 0x7fffffffUL
342 340
343#endif 341#endif
diff --git a/include/asm-s390/ptrace.h b/include/asm-s390/ptrace.h
index d7d4e2eb3e6f..af2c9ac28a07 100644
--- a/include/asm-s390/ptrace.h
+++ b/include/asm-s390/ptrace.h
@@ -215,6 +215,12 @@ typedef struct
215 unsigned long addr; 215 unsigned long addr;
216} __attribute__ ((aligned(8))) psw_t; 216} __attribute__ ((aligned(8))) psw_t;
217 217
218typedef struct
219{
220 __u32 mask;
221 __u32 addr;
222} __attribute__ ((aligned(8))) psw_compat_t;
223
218#ifndef __s390x__ 224#ifndef __s390x__
219 225
220#define PSW_MASK_PER 0x40000000UL 226#define PSW_MASK_PER 0x40000000UL
@@ -292,6 +298,15 @@ typedef struct
292 unsigned long orig_gpr2; 298 unsigned long orig_gpr2;
293} s390_regs; 299} s390_regs;
294 300
301typedef struct
302{
303 psw_compat_t psw;
304 __u32 gprs[NUM_GPRS];
305 __u32 acrs[NUM_ACRS];
306 __u32 orig_gpr2;
307} s390_compat_regs;
308
309
295#ifdef __KERNEL__ 310#ifdef __KERNEL__
296#include <asm/setup.h> 311#include <asm/setup.h>
297#include <asm/page.h> 312#include <asm/page.h>
diff --git a/include/asm-s390/schid.h b/include/asm-s390/schid.h
new file mode 100644
index 000000000000..5017ffa78e04
--- /dev/null
+++ b/include/asm-s390/schid.h
@@ -0,0 +1,28 @@
1#ifndef ASM_SCHID_H
2#define ASM_SCHID_H
3
4struct subchannel_id {
5 __u32 cssid : 8;
6 __u32 : 4;
7 __u32 m : 1;
8 __u32 ssid : 2;
9 __u32 one : 1;
10 __u32 sch_no : 16;
11} __attribute__ ((packed, aligned(4)));
12
13
14/* Helper function for sane state of pre-allocated subchannel_id. */
15static inline void
16init_subchannel_id(struct subchannel_id *schid)
17{
18 memset(schid, 0, sizeof(struct subchannel_id));
19 schid->one = 1;
20}
21
22static inline int
23schid_equal(struct subchannel_id *schid1, struct subchannel_id *schid2)
24{
25 return !memcmp(schid1, schid2, sizeof(struct subchannel_id));
26}
27
28#endif /* ASM_SCHID_H */
diff --git a/include/asm-s390/sclp.h b/include/asm-s390/sclp.h
index b5f2843013a3..fed7bee650a0 100644
--- a/include/asm-s390/sclp.h
+++ b/include/asm-s390/sclp.h
@@ -45,9 +45,9 @@ struct sclp_cpu_info {
45int sclp_get_cpu_info(struct sclp_cpu_info *info); 45int sclp_get_cpu_info(struct sclp_cpu_info *info);
46int sclp_cpu_configure(u8 cpu); 46int sclp_cpu_configure(u8 cpu);
47int sclp_cpu_deconfigure(u8 cpu); 47int sclp_cpu_deconfigure(u8 cpu);
48void sclp_read_info_early(void);
49void sclp_facilities_detect(void); 48void sclp_facilities_detect(void);
50unsigned long long sclp_memory_detect(void); 49unsigned long long sclp_get_rnmax(void);
50unsigned long long sclp_get_rzm(void);
51int sclp_sdias_blk_count(void); 51int sclp_sdias_blk_count(void);
52int sclp_sdias_copy(void *dest, int blk_num, int nr_blks); 52int sclp_sdias_copy(void *dest, int blk_num, int nr_blks);
53int sclp_chp_configure(struct chp_id chpid); 53int sclp_chp_configure(struct chp_id chpid);
diff --git a/include/asm-s390/setup.h b/include/asm-s390/setup.h
index ba69674012a7..f09ee3f72977 100644
--- a/include/asm-s390/setup.h
+++ b/include/asm-s390/setup.h
@@ -8,14 +8,16 @@
8#ifndef _ASM_S390_SETUP_H 8#ifndef _ASM_S390_SETUP_H
9#define _ASM_S390_SETUP_H 9#define _ASM_S390_SETUP_H
10 10
11#define COMMAND_LINE_SIZE 896 11#define COMMAND_LINE_SIZE 1024
12
13#define ARCH_COMMAND_LINE_SIZE 896
12 14
13#ifdef __KERNEL__ 15#ifdef __KERNEL__
14 16
15#include <asm/types.h> 17#include <asm/types.h>
16 18
17#define PARMAREA 0x10400 19#define PARMAREA 0x10400
18#define MEMORY_CHUNKS 16 /* max 0x7fff */ 20#define MEMORY_CHUNKS 256
19 21
20#ifndef __ASSEMBLY__ 22#ifndef __ASSEMBLY__
21 23
@@ -36,12 +38,14 @@
36struct mem_chunk { 38struct mem_chunk {
37 unsigned long addr; 39 unsigned long addr;
38 unsigned long size; 40 unsigned long size;
39 unsigned long type; 41 int type;
40}; 42};
41 43
42extern struct mem_chunk memory_chunk[]; 44extern struct mem_chunk memory_chunk[];
43extern unsigned long real_memory_size; 45extern unsigned long real_memory_size;
44 46
47void detect_memory_layout(struct mem_chunk chunk[]);
48
45#ifdef CONFIG_S390_SWITCH_AMODE 49#ifdef CONFIG_S390_SWITCH_AMODE
46extern unsigned int switch_amode; 50extern unsigned int switch_amode;
47#else 51#else
@@ -61,7 +65,6 @@ extern unsigned long machine_flags;
61 65
62#define MACHINE_FLAG_VM (1UL << 0) 66#define MACHINE_FLAG_VM (1UL << 0)
63#define MACHINE_FLAG_IEEE (1UL << 1) 67#define MACHINE_FLAG_IEEE (1UL << 1)
64#define MACHINE_FLAG_P390 (1UL << 2)
65#define MACHINE_FLAG_CSP (1UL << 3) 68#define MACHINE_FLAG_CSP (1UL << 3)
66#define MACHINE_FLAG_MVPG (1UL << 4) 69#define MACHINE_FLAG_MVPG (1UL << 4)
67#define MACHINE_FLAG_DIAG44 (1UL << 5) 70#define MACHINE_FLAG_DIAG44 (1UL << 5)
@@ -97,7 +100,6 @@ extern unsigned long machine_flags;
97#define MACHINE_HAS_PFMF (machine_flags & MACHINE_FLAG_PFMF) 100#define MACHINE_HAS_PFMF (machine_flags & MACHINE_FLAG_PFMF)
98#endif /* __s390x__ */ 101#endif /* __s390x__ */
99 102
100#define MACHINE_HAS_SCLP (!MACHINE_IS_P390)
101#define ZFCPDUMP_HSA_SIZE (32UL<<20) 103#define ZFCPDUMP_HSA_SIZE (32UL<<20)
102 104
103/* 105/*
diff --git a/include/asm-s390/sparsemem.h b/include/asm-s390/sparsemem.h
index 06dfdab6c0e8..545d219e6a2d 100644
--- a/include/asm-s390/sparsemem.h
+++ b/include/asm-s390/sparsemem.h
@@ -1,15 +1,15 @@
1#ifndef _ASM_S390_SPARSEMEM_H 1#ifndef _ASM_S390_SPARSEMEM_H
2#define _ASM_S390_SPARSEMEM_H 2#define _ASM_S390_SPARSEMEM_H
3 3
4#define SECTION_SIZE_BITS 25
5
6#ifdef CONFIG_64BIT 4#ifdef CONFIG_64BIT
7 5
6#define SECTION_SIZE_BITS 28
8#define MAX_PHYSADDR_BITS 42 7#define MAX_PHYSADDR_BITS 42
9#define MAX_PHYSMEM_BITS 42 8#define MAX_PHYSMEM_BITS 42
10 9
11#else 10#else
12 11
12#define SECTION_SIZE_BITS 25
13#define MAX_PHYSADDR_BITS 31 13#define MAX_PHYSADDR_BITS 31
14#define MAX_PHYSMEM_BITS 31 14#define MAX_PHYSMEM_BITS 31
15 15
diff --git a/include/asm-s390/timer.h b/include/asm-s390/timer.h
index adb34860a543..d98d79e35cd6 100644
--- a/include/asm-s390/timer.h
+++ b/include/asm-s390/timer.h
@@ -48,6 +48,18 @@ extern int del_virt_timer(struct vtimer_list *timer);
48extern void init_cpu_vtimer(void); 48extern void init_cpu_vtimer(void);
49extern void vtime_init(void); 49extern void vtime_init(void);
50 50
51#ifdef CONFIG_VIRT_TIMER
52
53extern void vtime_start_cpu_timer(void);
54extern void vtime_stop_cpu_timer(void);
55
56#else
57
58static inline void vtime_start_cpu_timer(void) { }
59static inline void vtime_stop_cpu_timer(void) { }
60
61#endif /* CONFIG_VIRT_TIMER */
62
51#endif /* __KERNEL__ */ 63#endif /* __KERNEL__ */
52 64
53#endif /* _ASM_S390_TIMER_H */ 65#endif /* _ASM_S390_TIMER_H */
diff --git a/include/asm-s390/zcrypt.h b/include/asm-s390/zcrypt.h
index f228f1b86877..00d3bbd44117 100644
--- a/include/asm-s390/zcrypt.h
+++ b/include/asm-s390/zcrypt.h
@@ -29,7 +29,7 @@
29 29
30#define ZCRYPT_VERSION 2 30#define ZCRYPT_VERSION 2
31#define ZCRYPT_RELEASE 1 31#define ZCRYPT_RELEASE 1
32#define ZCRYPT_VARIANT 0 32#define ZCRYPT_VARIANT 1
33 33
34#include <linux/ioctl.h> 34#include <linux/ioctl.h>
35#include <linux/compiler.h> 35#include <linux/compiler.h>
diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h
index 9c8d34b07ebf..593343cd26ee 100644
--- a/include/asm-sh/smp.h
+++ b/include/asm-sh/smp.h
@@ -26,18 +26,10 @@ extern int __cpu_logical_map[NR_CPUS];
26 26
27#define NO_PROC_ID (-1) 27#define NO_PROC_ID (-1)
28 28
29struct smp_fn_call_struct {
30 spinlock_t lock;
31 atomic_t finished;
32 void (*fn)(void *);
33 void *data;
34};
35
36extern struct smp_fn_call_struct smp_fn_call;
37
38#define SMP_MSG_FUNCTION 0 29#define SMP_MSG_FUNCTION 0
39#define SMP_MSG_RESCHEDULE 1 30#define SMP_MSG_RESCHEDULE 1
40#define SMP_MSG_NR 2 31#define SMP_MSG_FUNCTION_SINGLE 2
32#define SMP_MSG_NR 3
41 33
42void plat_smp_setup(void); 34void plat_smp_setup(void);
43void plat_prepare_cpus(unsigned int max_cpus); 35void plat_prepare_cpus(unsigned int max_cpus);
@@ -46,6 +38,8 @@ void plat_start_cpu(unsigned int cpu, unsigned long entry_point);
46void plat_send_ipi(unsigned int cpu, unsigned int message); 38void plat_send_ipi(unsigned int cpu, unsigned int message);
47int plat_register_ipi_handler(unsigned int message, 39int plat_register_ipi_handler(unsigned int message,
48 void (*handler)(void *), void *arg); 40 void (*handler)(void *), void *arg);
41extern void arch_send_call_function_single_ipi(int cpu);
42extern void arch_send_call_function_ipi(cpumask_t mask);
49 43
50#else 44#else
51 45
diff --git a/include/asm-sparc/smp.h b/include/asm-sparc/smp.h
index e6d561599726..b61e74bea06a 100644
--- a/include/asm-sparc/smp.h
+++ b/include/asm-sparc/smp.h
@@ -72,7 +72,7 @@ static inline void xc5(smpfunc_t func, unsigned long arg1, unsigned long arg2,
72 unsigned long arg3, unsigned long arg4, unsigned long arg5) 72 unsigned long arg3, unsigned long arg4, unsigned long arg5)
73{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); } 73{ smp_cross_call(func, arg1, arg2, arg3, arg4, arg5); }
74 74
75static inline int smp_call_function(void (*func)(void *info), void *info, int nonatomic, int wait) 75static inline int smp_call_function(void (*func)(void *info), void *info, int wait)
76{ 76{
77 xc1((smpfunc_t)func, (unsigned long)info); 77 xc1((smpfunc_t)func, (unsigned long)info);
78 return 0; 78 return 0;
diff --git a/include/asm-sparc64/ftrace.h b/include/asm-sparc64/ftrace.h
new file mode 100644
index 000000000000..d27716cd38c1
--- /dev/null
+++ b/include/asm-sparc64/ftrace.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_SPARC64_FTRACE
2#define _ASM_SPARC64_FTRACE
3
4#ifdef CONFIG_MCOUNT
5#define MCOUNT_ADDR ((long)(_mcount))
6#define MCOUNT_INSN_SIZE 4 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void _mcount(void);
10#endif
11
12#endif
13
14#endif /* _ASM_SPARC64_FTRACE */
diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
index 14411c9de46f..635d764dc13e 100644
--- a/include/asm-x86/acpi.h
+++ b/include/asm-x86/acpi.h
@@ -28,6 +28,7 @@
28#include <asm/numa.h> 28#include <asm/numa.h>
29#include <asm/processor.h> 29#include <asm/processor.h>
30#include <asm/mmu.h> 30#include <asm/mmu.h>
31#include <asm/mpspec.h>
31 32
32#define COMPILER_DEPENDENT_INT64 long long 33#define COMPILER_DEPENDENT_INT64 long long
33#define COMPILER_DEPENDENT_UINT64 unsigned long long 34#define COMPILER_DEPENDENT_UINT64 unsigned long long
@@ -160,9 +161,7 @@ struct bootnode;
160#ifdef CONFIG_ACPI_NUMA 161#ifdef CONFIG_ACPI_NUMA
161extern int acpi_numa; 162extern int acpi_numa;
162extern int acpi_scan_nodes(unsigned long start, unsigned long end); 163extern int acpi_scan_nodes(unsigned long start, unsigned long end);
163#ifdef CONFIG_X86_64 164#define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
164# define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
165#endif
166extern void acpi_fake_nodes(const struct bootnode *fake_nodes, 165extern void acpi_fake_nodes(const struct bootnode *fake_nodes,
167 int num_nodes); 166 int num_nodes);
168#else 167#else
diff --git a/include/asm-x86/alternative.h b/include/asm-x86/alternative.h
index 1f6a9ca10126..f6aa18eadf71 100644
--- a/include/asm-x86/alternative.h
+++ b/include/asm-x86/alternative.h
@@ -72,6 +72,8 @@ static inline void alternatives_smp_module_del(struct module *mod) {}
72static inline void alternatives_smp_switch(int smp) {} 72static inline void alternatives_smp_switch(int smp) {}
73#endif /* CONFIG_SMP */ 73#endif /* CONFIG_SMP */
74 74
75const unsigned char *const *find_nop_table(void);
76
75/* 77/*
76 * Alternative instructions for different CPU types or capabilities. 78 * Alternative instructions for different CPU types or capabilities.
77 * 79 *
diff --git a/include/asm-x86/amd_iommu.h b/include/asm-x86/amd_iommu.h
new file mode 100644
index 000000000000..30a12049353b
--- /dev/null
+++ b/include/asm-x86/amd_iommu.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ASM_X86_AMD_IOMMU_H
21#define _ASM_X86_AMD_IOMMU_H
22
23#ifdef CONFIG_AMD_IOMMU
24extern int amd_iommu_init(void);
25extern int amd_iommu_init_dma_ops(void);
26extern void amd_iommu_detect(void);
27#else
28static inline int amd_iommu_init(void) { return -ENODEV; }
29static inline void amd_iommu_detect(void) { }
30#endif
31
32#endif
diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
new file mode 100644
index 000000000000..7bfcb47cc452
--- /dev/null
+++ b/include/asm-x86/amd_iommu_types.h
@@ -0,0 +1,244 @@
1/*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __AMD_IOMMU_TYPES_H__
21#define __AMD_IOMMU_TYPES_H__
22
23#include <linux/types.h>
24#include <linux/list.h>
25#include <linux/spinlock.h>
26
27/*
28 * some size calculation constants
29 */
30#define DEV_TABLE_ENTRY_SIZE 256
31#define ALIAS_TABLE_ENTRY_SIZE 2
32#define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
33
34/* helper macros */
35#define LOW_U32(x) ((x) & ((1ULL << 32)-1))
36#define HIGH_U32(x) (LOW_U32((x) >> 32))
37
38/* Length of the MMIO region for the AMD IOMMU */
39#define MMIO_REGION_LENGTH 0x4000
40
41/* Capability offsets used by the driver */
42#define MMIO_CAP_HDR_OFFSET 0x00
43#define MMIO_RANGE_OFFSET 0x0c
44
45/* Masks, shifts and macros to parse the device range capability */
46#define MMIO_RANGE_LD_MASK 0xff000000
47#define MMIO_RANGE_FD_MASK 0x00ff0000
48#define MMIO_RANGE_BUS_MASK 0x0000ff00
49#define MMIO_RANGE_LD_SHIFT 24
50#define MMIO_RANGE_FD_SHIFT 16
51#define MMIO_RANGE_BUS_SHIFT 8
52#define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
53#define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
54#define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
55
56/* Flag masks for the AMD IOMMU exclusion range */
57#define MMIO_EXCL_ENABLE_MASK 0x01ULL
58#define MMIO_EXCL_ALLOW_MASK 0x02ULL
59
60/* Used offsets into the MMIO space */
61#define MMIO_DEV_TABLE_OFFSET 0x0000
62#define MMIO_CMD_BUF_OFFSET 0x0008
63#define MMIO_EVT_BUF_OFFSET 0x0010
64#define MMIO_CONTROL_OFFSET 0x0018
65#define MMIO_EXCL_BASE_OFFSET 0x0020
66#define MMIO_EXCL_LIMIT_OFFSET 0x0028
67#define MMIO_CMD_HEAD_OFFSET 0x2000
68#define MMIO_CMD_TAIL_OFFSET 0x2008
69#define MMIO_EVT_HEAD_OFFSET 0x2010
70#define MMIO_EVT_TAIL_OFFSET 0x2018
71#define MMIO_STATUS_OFFSET 0x2020
72
73/* feature control bits */
74#define CONTROL_IOMMU_EN 0x00ULL
75#define CONTROL_HT_TUN_EN 0x01ULL
76#define CONTROL_EVT_LOG_EN 0x02ULL
77#define CONTROL_EVT_INT_EN 0x03ULL
78#define CONTROL_COMWAIT_EN 0x04ULL
79#define CONTROL_PASSPW_EN 0x08ULL
80#define CONTROL_RESPASSPW_EN 0x09ULL
81#define CONTROL_COHERENT_EN 0x0aULL
82#define CONTROL_ISOC_EN 0x0bULL
83#define CONTROL_CMDBUF_EN 0x0cULL
84#define CONTROL_PPFLOG_EN 0x0dULL
85#define CONTROL_PPFINT_EN 0x0eULL
86
87/* command specific defines */
88#define CMD_COMPL_WAIT 0x01
89#define CMD_INV_DEV_ENTRY 0x02
90#define CMD_INV_IOMMU_PAGES 0x03
91
92#define CMD_COMPL_WAIT_STORE_MASK 0x01
93#define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
94#define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
95
96#define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
97
98/* macros and definitions for device table entries */
99#define DEV_ENTRY_VALID 0x00
100#define DEV_ENTRY_TRANSLATION 0x01
101#define DEV_ENTRY_IR 0x3d
102#define DEV_ENTRY_IW 0x3e
103#define DEV_ENTRY_EX 0x67
104#define DEV_ENTRY_SYSMGT1 0x68
105#define DEV_ENTRY_SYSMGT2 0x69
106#define DEV_ENTRY_INIT_PASS 0xb8
107#define DEV_ENTRY_EINT_PASS 0xb9
108#define DEV_ENTRY_NMI_PASS 0xba
109#define DEV_ENTRY_LINT0_PASS 0xbe
110#define DEV_ENTRY_LINT1_PASS 0xbf
111
112/* constants to configure the command buffer */
113#define CMD_BUFFER_SIZE 8192
114#define CMD_BUFFER_ENTRIES 512
115#define MMIO_CMD_SIZE_SHIFT 56
116#define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
117
118#define PAGE_MODE_1_LEVEL 0x01
119#define PAGE_MODE_2_LEVEL 0x02
120#define PAGE_MODE_3_LEVEL 0x03
121
122#define IOMMU_PDE_NL_0 0x000ULL
123#define IOMMU_PDE_NL_1 0x200ULL
124#define IOMMU_PDE_NL_2 0x400ULL
125#define IOMMU_PDE_NL_3 0x600ULL
126
127#define IOMMU_PTE_L2_INDEX(address) (((address) >> 30) & 0x1ffULL)
128#define IOMMU_PTE_L1_INDEX(address) (((address) >> 21) & 0x1ffULL)
129#define IOMMU_PTE_L0_INDEX(address) (((address) >> 12) & 0x1ffULL)
130
131#define IOMMU_MAP_SIZE_L1 (1ULL << 21)
132#define IOMMU_MAP_SIZE_L2 (1ULL << 30)
133#define IOMMU_MAP_SIZE_L3 (1ULL << 39)
134
135#define IOMMU_PTE_P (1ULL << 0)
136#define IOMMU_PTE_U (1ULL << 59)
137#define IOMMU_PTE_FC (1ULL << 60)
138#define IOMMU_PTE_IR (1ULL << 61)
139#define IOMMU_PTE_IW (1ULL << 62)
140
141#define IOMMU_L1_PDE(address) \
142 ((address) | IOMMU_PDE_NL_1 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
143#define IOMMU_L2_PDE(address) \
144 ((address) | IOMMU_PDE_NL_2 | IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
145
146#define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
147#define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
148#define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
149#define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
150
151#define IOMMU_PROT_MASK 0x03
152#define IOMMU_PROT_IR 0x01
153#define IOMMU_PROT_IW 0x02
154
155/* IOMMU capabilities */
156#define IOMMU_CAP_IOTLB 24
157#define IOMMU_CAP_NPCACHE 26
158
159#define MAX_DOMAIN_ID 65536
160
161struct protection_domain {
162 spinlock_t lock;
163 u16 id;
164 int mode;
165 u64 *pt_root;
166 void *priv;
167};
168
169struct dma_ops_domain {
170 struct list_head list;
171 struct protection_domain domain;
172 unsigned long aperture_size;
173 unsigned long next_bit;
174 unsigned long *bitmap;
175 u64 **pte_pages;
176};
177
178struct amd_iommu {
179 struct list_head list;
180 spinlock_t lock;
181
182 u16 devid;
183 u16 cap_ptr;
184
185 u64 mmio_phys;
186 u8 *mmio_base;
187 u32 cap;
188 u16 first_device;
189 u16 last_device;
190 u64 exclusion_start;
191 u64 exclusion_length;
192
193 u8 *cmd_buf;
194 u32 cmd_buf_size;
195
196 int need_sync;
197
198 struct dma_ops_domain *default_dom;
199};
200
201extern struct list_head amd_iommu_list;
202
203struct dev_table_entry {
204 u32 data[8];
205};
206
207struct unity_map_entry {
208 struct list_head list;
209 u16 devid_start;
210 u16 devid_end;
211 u64 address_start;
212 u64 address_end;
213 int prot;
214};
215
216extern struct list_head amd_iommu_unity_map;
217
218/* data structures for device handling */
219extern struct dev_table_entry *amd_iommu_dev_table;
220extern u16 *amd_iommu_alias_table;
221extern struct amd_iommu **amd_iommu_rlookup_table;
222
223extern unsigned amd_iommu_aperture_order;
224
225extern u16 amd_iommu_last_bdf;
226
227/* data structures for protection domain handling */
228extern struct protection_domain **amd_iommu_pd_table;
229extern unsigned long *amd_iommu_pd_alloc_bitmap;
230
231extern int amd_iommu_isolate;
232
233static inline void print_devid(u16 devid, int nl)
234{
235 int bus = devid >> 8;
236 int dev = devid >> 3 & 0x1f;
237 int fn = devid & 0x07;
238
239 printk("%02x:%02x.%x", bus, dev, fn);
240 if (nl)
241 printk("\n");
242}
243
244#endif
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
index be9639a9a186..4e2c1e517f06 100644
--- a/include/asm-x86/apic.h
+++ b/include/asm-x86/apic.h
@@ -36,15 +36,11 @@ extern void generic_apic_probe(void);
36#ifdef CONFIG_X86_LOCAL_APIC 36#ifdef CONFIG_X86_LOCAL_APIC
37 37
38extern int apic_verbosity; 38extern int apic_verbosity;
39extern int timer_over_8254;
40extern int local_apic_timer_c2_ok; 39extern int local_apic_timer_c2_ok;
41extern int local_apic_timer_disabled;
42 40
43extern int apic_runs_main_timer;
44extern int ioapic_force; 41extern int ioapic_force;
45extern int disable_apic;
46extern int disable_apic_timer;
47 42
43extern int disable_apic;
48/* 44/*
49 * Basic functions accessing APICs. 45 * Basic functions accessing APICs.
50 */ 46 */
@@ -125,16 +121,22 @@ extern void enable_NMI_through_LVT0(void);
125 */ 121 */
126#ifdef CONFIG_X86_64 122#ifdef CONFIG_X86_64
127extern void early_init_lapic_mapping(void); 123extern void early_init_lapic_mapping(void);
124extern int apic_is_clustered_box(void);
125#else
126static inline int apic_is_clustered_box(void)
127{
128 return 0;
129}
128#endif 130#endif
129 131
130extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask); 132extern u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask);
131extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask); 133extern u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask);
132 134
133extern int apic_is_clustered_box(void);
134 135
135#else /* !CONFIG_X86_LOCAL_APIC */ 136#else /* !CONFIG_X86_LOCAL_APIC */
136static inline void lapic_shutdown(void) { } 137static inline void lapic_shutdown(void) { }
137#define local_apic_timer_c2_ok 1 138#define local_apic_timer_c2_ok 1
139static inline void init_apic_mappings(void) { }
138 140
139#endif /* !CONFIG_X86_LOCAL_APIC */ 141#endif /* !CONFIG_X86_LOCAL_APIC */
140 142
diff --git a/include/asm-x86/asm.h b/include/asm-x86/asm.h
index 90dec0c23646..97220321f39d 100644
--- a/include/asm-x86/asm.h
+++ b/include/asm-x86/asm.h
@@ -1,37 +1,40 @@
1#ifndef _ASM_X86_ASM_H 1#ifndef _ASM_X86_ASM_H
2#define _ASM_X86_ASM_H 2#define _ASM_X86_ASM_H
3 3
4#ifdef CONFIG_X86_32 4#ifdef __ASSEMBLY__
5/* 32 bits */ 5# define __ASM_FORM(x) x
6 6# define __ASM_EX_SEC .section __ex_table
7# define _ASM_PTR " .long "
8# define _ASM_ALIGN " .balign 4 "
9# define _ASM_MOV_UL " movl "
10
11# define _ASM_INC " incl "
12# define _ASM_DEC " decl "
13# define _ASM_ADD " addl "
14# define _ASM_SUB " subl "
15# define _ASM_XADD " xaddl "
16
17#else 7#else
18/* 64 bits */ 8# define __ASM_FORM(x) " " #x " "
9# define __ASM_EX_SEC " .section __ex_table,\"a\"\n"
10#endif
19 11
20# define _ASM_PTR " .quad " 12#ifdef CONFIG_X86_32
21# define _ASM_ALIGN " .balign 8 " 13# define __ASM_SEL(a,b) __ASM_FORM(a)
22# define _ASM_MOV_UL " movq " 14#else
23 15# define __ASM_SEL(a,b) __ASM_FORM(b)
24# define _ASM_INC " incq " 16#endif
25# define _ASM_DEC " decq " 17
26# define _ASM_ADD " addq " 18#define __ASM_SIZE(inst) __ASM_SEL(inst##l, inst##q)
27# define _ASM_SUB " subq " 19#define __ASM_REG(reg) __ASM_SEL(e##reg, r##reg)
28# define _ASM_XADD " xaddq " 20
29 21#define _ASM_PTR __ASM_SEL(.long, .quad)
30#endif /* CONFIG_X86_32 */ 22#define _ASM_ALIGN __ASM_SEL(.balign 4, .balign 8)
23#define _ASM_MOV_UL __ASM_SIZE(mov)
24
25#define _ASM_INC __ASM_SIZE(inc)
26#define _ASM_DEC __ASM_SIZE(dec)
27#define _ASM_ADD __ASM_SIZE(add)
28#define _ASM_SUB __ASM_SIZE(sub)
29#define _ASM_XADD __ASM_SIZE(xadd)
30#define _ASM_AX __ASM_REG(ax)
31#define _ASM_BX __ASM_REG(bx)
32#define _ASM_CX __ASM_REG(cx)
33#define _ASM_DX __ASM_REG(dx)
31 34
32/* Exception table entry */ 35/* Exception table entry */
33# define _ASM_EXTABLE(from,to) \ 36# define _ASM_EXTABLE(from,to) \
34 " .section __ex_table,\"a\"\n" \ 37 __ASM_EX_SEC \
35 _ASM_ALIGN "\n" \ 38 _ASM_ALIGN "\n" \
36 _ASM_PTR #from "," #to "\n" \ 39 _ASM_PTR #from "," #to "\n" \
37 " .previous\n" 40 " .previous\n"
diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h
index 3e0cd7d38335..a0095191c02e 100644
--- a/include/asm-x86/atomic_64.h
+++ b/include/asm-x86/atomic_64.h
@@ -11,12 +11,6 @@
11 * resource counting etc.. 11 * resource counting etc..
12 */ 12 */
13 13
14#ifdef CONFIG_SMP
15#define LOCK "lock ; "
16#else
17#define LOCK ""
18#endif
19
20/* 14/*
21 * Make sure gcc doesn't try to be clever and move things around 15 * Make sure gcc doesn't try to be clever and move things around
22 * on us. We need to use _exactly_ the address the user gave us, 16 * on us. We need to use _exactly_ the address the user gave us,
@@ -431,6 +425,32 @@ static inline int atomic64_add_unless(atomic64_t *v, long a, long u)
431 return c != (u); 425 return c != (u);
432} 426}
433 427
428/**
429 * atomic_inc_short - increment of a short integer
430 * @v: pointer to type int
431 *
432 * Atomically adds 1 to @v
433 * Returns the new value of @u
434 */
435static inline short int atomic_inc_short(short int *v)
436{
437 asm(LOCK_PREFIX "addw $1, %0" : "+m" (*v));
438 return *v;
439}
440
441/**
442 * atomic_or_long - OR of two long integers
443 * @v1: pointer to type unsigned long
444 * @v2: pointer to type unsigned long
445 *
446 * Atomically ORs @v1 and @v2
447 * Returns the result of the OR
448 */
449static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
450{
451 asm(LOCK_PREFIX "orq %1, %0" : "+m" (*v1) : "r" (v2));
452}
453
434#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0) 454#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
435 455
436/* These are x86-specific, used by some header files */ 456/* These are x86-specific, used by some header files */
diff --git a/include/asm-x86/bios_ebda.h b/include/asm-x86/bios_ebda.h
index b4a46b7be794..0033e50c13b2 100644
--- a/include/asm-x86/bios_ebda.h
+++ b/include/asm-x86/bios_ebda.h
@@ -14,4 +14,6 @@ static inline unsigned int get_bios_ebda(void)
14 return address; /* 0 means none */ 14 return address; /* 0 means none */
15} 15}
16 16
17void reserve_ebda_region(void);
18
17#endif /* _MACH_BIOS_EBDA_H */ 19#endif /* _MACH_BIOS_EBDA_H */
diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h
index ee4b3ead6a43..96b1829cea15 100644
--- a/include/asm-x86/bitops.h
+++ b/include/asm-x86/bitops.h
@@ -23,11 +23,21 @@
23#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1) 23#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ < 1)
24/* Technically wrong, but this avoids compilation errors on some gcc 24/* Technically wrong, but this avoids compilation errors on some gcc
25 versions. */ 25 versions. */
26#define ADDR "=m" (*(volatile long *) addr) 26#define BITOP_ADDR(x) "=m" (*(volatile long *) (x))
27#else 27#else
28#define ADDR "+m" (*(volatile long *) addr) 28#define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
29#endif 29#endif
30 30
31#define ADDR BITOP_ADDR(addr)
32
33/*
34 * We do the locked ops that don't return the old value as
35 * a mask operation on a byte.
36 */
37#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
38#define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3))
39#define CONST_MASK(nr) (1 << ((nr) & 7))
40
31/** 41/**
32 * set_bit - Atomically set a bit in memory 42 * set_bit - Atomically set a bit in memory
33 * @nr: the bit to set 43 * @nr: the bit to set
@@ -43,9 +53,17 @@
43 * Note that @nr may be almost arbitrarily large; this function is not 53 * Note that @nr may be almost arbitrarily large; this function is not
44 * restricted to acting on a single-word quantity. 54 * restricted to acting on a single-word quantity.
45 */ 55 */
46static inline void set_bit(int nr, volatile void *addr) 56static inline void set_bit(unsigned int nr, volatile unsigned long *addr)
47{ 57{
48 asm volatile(LOCK_PREFIX "bts %1,%0" : ADDR : "Ir" (nr) : "memory"); 58 if (IS_IMMEDIATE(nr)) {
59 asm volatile(LOCK_PREFIX "orb %1,%0"
60 : CONST_MASK_ADDR(nr, addr)
61 : "iq" ((u8)CONST_MASK(nr))
62 : "memory");
63 } else {
64 asm volatile(LOCK_PREFIX "bts %1,%0"
65 : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
66 }
49} 67}
50 68
51/** 69/**
@@ -57,7 +75,7 @@ static inline void set_bit(int nr, volatile void *addr)
57 * If it's called on the same region of memory simultaneously, the effect 75 * If it's called on the same region of memory simultaneously, the effect
58 * may be that only one operation succeeds. 76 * may be that only one operation succeeds.
59 */ 77 */
60static inline void __set_bit(int nr, volatile void *addr) 78static inline void __set_bit(int nr, volatile unsigned long *addr)
61{ 79{
62 asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory"); 80 asm volatile("bts %1,%0" : ADDR : "Ir" (nr) : "memory");
63} 81}
@@ -72,9 +90,17 @@ static inline void __set_bit(int nr, volatile void *addr)
72 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() 90 * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
73 * in order to ensure changes are visible on other processors. 91 * in order to ensure changes are visible on other processors.
74 */ 92 */
75static inline void clear_bit(int nr, volatile void *addr) 93static inline void clear_bit(int nr, volatile unsigned long *addr)
76{ 94{
77 asm volatile(LOCK_PREFIX "btr %1,%0" : ADDR : "Ir" (nr)); 95 if (IS_IMMEDIATE(nr)) {
96 asm volatile(LOCK_PREFIX "andb %1,%0"
97 : CONST_MASK_ADDR(nr, addr)
98 : "iq" ((u8)~CONST_MASK(nr)));
99 } else {
100 asm volatile(LOCK_PREFIX "btr %1,%0"
101 : BITOP_ADDR(addr)
102 : "Ir" (nr));
103 }
78} 104}
79 105
80/* 106/*
@@ -85,13 +111,13 @@ static inline void clear_bit(int nr, volatile void *addr)
85 * clear_bit() is atomic and implies release semantics before the memory 111 * clear_bit() is atomic and implies release semantics before the memory
86 * operation. It can be used for an unlock. 112 * operation. It can be used for an unlock.
87 */ 113 */
88static inline void clear_bit_unlock(unsigned nr, volatile void *addr) 114static inline void clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
89{ 115{
90 barrier(); 116 barrier();
91 clear_bit(nr, addr); 117 clear_bit(nr, addr);
92} 118}
93 119
94static inline void __clear_bit(int nr, volatile void *addr) 120static inline void __clear_bit(int nr, volatile unsigned long *addr)
95{ 121{
96 asm volatile("btr %1,%0" : ADDR : "Ir" (nr)); 122 asm volatile("btr %1,%0" : ADDR : "Ir" (nr));
97} 123}
@@ -108,7 +134,7 @@ static inline void __clear_bit(int nr, volatile void *addr)
108 * No memory barrier is required here, because x86 cannot reorder stores past 134 * No memory barrier is required here, because x86 cannot reorder stores past
109 * older loads. Same principle as spin_unlock. 135 * older loads. Same principle as spin_unlock.
110 */ 136 */
111static inline void __clear_bit_unlock(unsigned nr, volatile void *addr) 137static inline void __clear_bit_unlock(unsigned nr, volatile unsigned long *addr)
112{ 138{
113 barrier(); 139 barrier();
114 __clear_bit(nr, addr); 140 __clear_bit(nr, addr);
@@ -126,7 +152,7 @@ static inline void __clear_bit_unlock(unsigned nr, volatile void *addr)
126 * If it's called on the same region of memory simultaneously, the effect 152 * If it's called on the same region of memory simultaneously, the effect
127 * may be that only one operation succeeds. 153 * may be that only one operation succeeds.
128 */ 154 */
129static inline void __change_bit(int nr, volatile void *addr) 155static inline void __change_bit(int nr, volatile unsigned long *addr)
130{ 156{
131 asm volatile("btc %1,%0" : ADDR : "Ir" (nr)); 157 asm volatile("btc %1,%0" : ADDR : "Ir" (nr));
132} 158}
@@ -140,7 +166,7 @@ static inline void __change_bit(int nr, volatile void *addr)
140 * Note that @nr may be almost arbitrarily large; this function is not 166 * Note that @nr may be almost arbitrarily large; this function is not
141 * restricted to acting on a single-word quantity. 167 * restricted to acting on a single-word quantity.
142 */ 168 */
143static inline void change_bit(int nr, volatile void *addr) 169static inline void change_bit(int nr, volatile unsigned long *addr)
144{ 170{
145 asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr)); 171 asm volatile(LOCK_PREFIX "btc %1,%0" : ADDR : "Ir" (nr));
146} 172}
@@ -153,7 +179,7 @@ static inline void change_bit(int nr, volatile void *addr)
153 * This operation is atomic and cannot be reordered. 179 * This operation is atomic and cannot be reordered.
154 * It also implies a memory barrier. 180 * It also implies a memory barrier.
155 */ 181 */
156static inline int test_and_set_bit(int nr, volatile void *addr) 182static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
157{ 183{
158 int oldbit; 184 int oldbit;
159 185
@@ -170,7 +196,7 @@ static inline int test_and_set_bit(int nr, volatile void *addr)
170 * 196 *
171 * This is the same as test_and_set_bit on x86. 197 * This is the same as test_and_set_bit on x86.
172 */ 198 */
173static inline int test_and_set_bit_lock(int nr, volatile void *addr) 199static inline int test_and_set_bit_lock(int nr, volatile unsigned long *addr)
174{ 200{
175 return test_and_set_bit(nr, addr); 201 return test_and_set_bit(nr, addr);
176} 202}
@@ -184,7 +210,7 @@ static inline int test_and_set_bit_lock(int nr, volatile void *addr)
184 * If two examples of this operation race, one can appear to succeed 210 * If two examples of this operation race, one can appear to succeed
185 * but actually fail. You must protect multiple accesses with a lock. 211 * but actually fail. You must protect multiple accesses with a lock.
186 */ 212 */
187static inline int __test_and_set_bit(int nr, volatile void *addr) 213static inline int __test_and_set_bit(int nr, volatile unsigned long *addr)
188{ 214{
189 int oldbit; 215 int oldbit;
190 216
@@ -203,7 +229,7 @@ static inline int __test_and_set_bit(int nr, volatile void *addr)
203 * This operation is atomic and cannot be reordered. 229 * This operation is atomic and cannot be reordered.
204 * It also implies a memory barrier. 230 * It also implies a memory barrier.
205 */ 231 */
206static inline int test_and_clear_bit(int nr, volatile void *addr) 232static inline int test_and_clear_bit(int nr, volatile unsigned long *addr)
207{ 233{
208 int oldbit; 234 int oldbit;
209 235
@@ -223,7 +249,7 @@ static inline int test_and_clear_bit(int nr, volatile void *addr)
223 * If two examples of this operation race, one can appear to succeed 249 * If two examples of this operation race, one can appear to succeed
224 * but actually fail. You must protect multiple accesses with a lock. 250 * but actually fail. You must protect multiple accesses with a lock.
225 */ 251 */
226static inline int __test_and_clear_bit(int nr, volatile void *addr) 252static inline int __test_and_clear_bit(int nr, volatile unsigned long *addr)
227{ 253{
228 int oldbit; 254 int oldbit;
229 255
@@ -235,7 +261,7 @@ static inline int __test_and_clear_bit(int nr, volatile void *addr)
235} 261}
236 262
237/* WARNING: non atomic and it can be reordered! */ 263/* WARNING: non atomic and it can be reordered! */
238static inline int __test_and_change_bit(int nr, volatile void *addr) 264static inline int __test_and_change_bit(int nr, volatile unsigned long *addr)
239{ 265{
240 int oldbit; 266 int oldbit;
241 267
@@ -255,7 +281,7 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
255 * This operation is atomic and cannot be reordered. 281 * This operation is atomic and cannot be reordered.
256 * It also implies a memory barrier. 282 * It also implies a memory barrier.
257 */ 283 */
258static inline int test_and_change_bit(int nr, volatile void *addr) 284static inline int test_and_change_bit(int nr, volatile unsigned long *addr)
259{ 285{
260 int oldbit; 286 int oldbit;
261 287
@@ -266,13 +292,13 @@ static inline int test_and_change_bit(int nr, volatile void *addr)
266 return oldbit; 292 return oldbit;
267} 293}
268 294
269static inline int constant_test_bit(int nr, const volatile void *addr) 295static inline int constant_test_bit(int nr, const volatile unsigned long *addr)
270{ 296{
271 return ((1UL << (nr % BITS_PER_LONG)) & 297 return ((1UL << (nr % BITS_PER_LONG)) &
272 (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0; 298 (((unsigned long *)addr)[nr / BITS_PER_LONG])) != 0;
273} 299}
274 300
275static inline int variable_test_bit(int nr, volatile const void *addr) 301static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
276{ 302{
277 int oldbit; 303 int oldbit;
278 304
diff --git a/include/asm-x86/bootparam.h b/include/asm-x86/bootparam.h
index f62f4733606b..ae22bdf0ab14 100644
--- a/include/asm-x86/bootparam.h
+++ b/include/asm-x86/bootparam.h
@@ -11,6 +11,7 @@
11 11
12/* setup data types */ 12/* setup data types */
13#define SETUP_NONE 0 13#define SETUP_NONE 0
14#define SETUP_E820_EXT 1
14 15
15/* extensible setup data list node */ 16/* extensible setup data list node */
16struct setup_data { 17struct setup_data {
@@ -40,6 +41,7 @@ struct setup_header {
40 __u8 type_of_loader; 41 __u8 type_of_loader;
41 __u8 loadflags; 42 __u8 loadflags;
42#define LOADED_HIGH (1<<0) 43#define LOADED_HIGH (1<<0)
44#define QUIET_FLAG (1<<5)
43#define KEEP_SEGMENTS (1<<6) 45#define KEEP_SEGMENTS (1<<6)
44#define CAN_USE_HEAP (1<<7) 46#define CAN_USE_HEAP (1<<7)
45 __u16 setup_move_size; 47 __u16 setup_move_size;
diff --git a/include/asm-x86/cmpxchg_64.h b/include/asm-x86/cmpxchg_64.h
index d9b26b9a28cf..17463ccf8166 100644
--- a/include/asm-x86/cmpxchg_64.h
+++ b/include/asm-x86/cmpxchg_64.h
@@ -93,6 +93,39 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
93 return old; 93 return old;
94} 94}
95 95
96/*
97 * Always use locked operations when touching memory shared with a
98 * hypervisor, since the system may be SMP even if the guest kernel
99 * isn't.
100 */
101static inline unsigned long __sync_cmpxchg(volatile void *ptr,
102 unsigned long old,
103 unsigned long new, int size)
104{
105 unsigned long prev;
106 switch (size) {
107 case 1:
108 asm volatile("lock; cmpxchgb %b1,%2"
109 : "=a"(prev)
110 : "q"(new), "m"(*__xg(ptr)), "0"(old)
111 : "memory");
112 return prev;
113 case 2:
114 asm volatile("lock; cmpxchgw %w1,%2"
115 : "=a"(prev)
116 : "r"(new), "m"(*__xg(ptr)), "0"(old)
117 : "memory");
118 return prev;
119 case 4:
120 asm volatile("lock; cmpxchgl %1,%2"
121 : "=a"(prev)
122 : "r"(new), "m"(*__xg(ptr)), "0"(old)
123 : "memory");
124 return prev;
125 }
126 return old;
127}
128
96static inline unsigned long __cmpxchg_local(volatile void *ptr, 129static inline unsigned long __cmpxchg_local(volatile void *ptr,
97 unsigned long old, 130 unsigned long old,
98 unsigned long new, int size) 131 unsigned long new, int size)
@@ -139,6 +172,10 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
139 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \ 172 ((__typeof__(*(ptr)))__cmpxchg_local((ptr), (unsigned long)(o), \
140 (unsigned long)(n), \ 173 (unsigned long)(n), \
141 sizeof(*(ptr)))) 174 sizeof(*(ptr))))
175#define sync_cmpxchg(ptr, o, n) \
176 ((__typeof__(*(ptr)))__sync_cmpxchg((ptr), (unsigned long)(o), \
177 (unsigned long)(n), \
178 sizeof(*(ptr))))
142#define cmpxchg64_local(ptr, o, n) \ 179#define cmpxchg64_local(ptr, o, n) \
143({ \ 180({ \
144 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \ 181 BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 0d609c837a41..75ef959db329 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -74,8 +74,8 @@
74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */ 74#define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */ 75#define X86_FEATURE_PEBS (3*32+12) /* Precise-Event Based Sampling */
76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */ 76#define X86_FEATURE_BTS (3*32+13) /* Branch Trace Store */
77/* 14 free */ 77#define X86_FEATURE_SYSCALL32 (3*32+14) /* syscall in ia32 userspace */
78/* 15 free */ 78#define X86_FEATURE_SYSENTER32 (3*32+15) /* sysenter in ia32 userspace */
79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */ 79#define X86_FEATURE_REP_GOOD (3*32+16) /* rep microcode works well on this CPU */
80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */ 80#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */ 81#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
@@ -106,6 +106,7 @@
106/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ 106/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
107#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ 107#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
108#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ 108#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
109#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */
109 110
110/* 111/*
111 * Auxiliary flags: Linux defined - For features scattered in various 112 * Auxiliary flags: Linux defined - For features scattered in various
@@ -142,11 +143,11 @@ extern const char * const x86_power_flags[32];
142#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability)) 143#define clear_cpu_cap(c, bit) clear_bit(bit, (unsigned long *)((c)->x86_capability))
143#define setup_clear_cpu_cap(bit) do { \ 144#define setup_clear_cpu_cap(bit) do { \
144 clear_cpu_cap(&boot_cpu_data, bit); \ 145 clear_cpu_cap(&boot_cpu_data, bit); \
145 set_bit(bit, cleared_cpu_caps); \ 146 set_bit(bit, (unsigned long *)cleared_cpu_caps); \
146} while (0) 147} while (0)
147#define setup_force_cpu_cap(bit) do { \ 148#define setup_force_cpu_cap(bit) do { \
148 set_cpu_cap(&boot_cpu_data, bit); \ 149 set_cpu_cap(&boot_cpu_data, bit); \
149 clear_bit(bit, cleared_cpu_caps); \ 150 clear_bit(bit, (unsigned long *)cleared_cpu_caps); \
150} while (0) 151} while (0)
151 152
152#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU) 153#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
diff --git a/include/asm-x86/current.h b/include/asm-x86/current.h
index d2526d3f7346..7515c19d4988 100644
--- a/include/asm-x86/current.h
+++ b/include/asm-x86/current.h
@@ -1,5 +1,39 @@
1#ifndef _X86_CURRENT_H
2#define _X86_CURRENT_H
3
1#ifdef CONFIG_X86_32 4#ifdef CONFIG_X86_32
2# include "current_32.h" 5#include <linux/compiler.h>
3#else 6#include <asm/percpu.h>
4# include "current_64.h" 7
5#endif 8struct task_struct;
9
10DECLARE_PER_CPU(struct task_struct *, current_task);
11static __always_inline struct task_struct *get_current(void)
12{
13 return x86_read_percpu(current_task);
14}
15
16#else /* X86_32 */
17
18#ifndef __ASSEMBLY__
19#include <asm/pda.h>
20
21struct task_struct;
22
23static __always_inline struct task_struct *get_current(void)
24{
25 return read_pda(pcurrent);
26}
27
28#else /* __ASSEMBLY__ */
29
30#include <asm/asm-offsets.h>
31#define GET_CURRENT(reg) movq %gs:(pda_pcurrent),reg
32
33#endif /* __ASSEMBLY__ */
34
35#endif /* X86_32 */
36
37#define current get_current()
38
39#endif /* X86_CURRENT_H */
diff --git a/include/asm-x86/current_32.h b/include/asm-x86/current_32.h
deleted file mode 100644
index 5af9bdb97a16..000000000000
--- a/include/asm-x86/current_32.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef _I386_CURRENT_H
2#define _I386_CURRENT_H
3
4#include <linux/compiler.h>
5#include <asm/percpu.h>
6
7struct task_struct;
8
9DECLARE_PER_CPU(struct task_struct *, current_task);
10static __always_inline struct task_struct *get_current(void)
11{
12 return x86_read_percpu(current_task);
13}
14
15#define current get_current()
16
17#endif /* !(_I386_CURRENT_H) */
diff --git a/include/asm-x86/current_64.h b/include/asm-x86/current_64.h
deleted file mode 100644
index 2d368ede2fc1..000000000000
--- a/include/asm-x86/current_64.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef _X86_64_CURRENT_H
2#define _X86_64_CURRENT_H
3
4#if !defined(__ASSEMBLY__)
5struct task_struct;
6
7#include <asm/pda.h>
8
9static inline struct task_struct *get_current(void)
10{
11 struct task_struct *t = read_pda(pcurrent);
12 return t;
13}
14
15#define current get_current()
16
17#else
18
19#ifndef ASM_OFFSET_H
20#include <asm/asm-offsets.h>
21#endif
22
23#define GET_CURRENT(reg) movq %gs:(pda_pcurrent),reg
24
25#endif
26
27#endif /* !(_X86_64_CURRENT_H) */
diff --git a/include/asm-x86/desc.h b/include/asm-x86/desc.h
index 268a012bcd79..a44c4dc70590 100644
--- a/include/asm-x86/desc.h
+++ b/include/asm-x86/desc.h
@@ -29,11 +29,17 @@ static inline void fill_ldt(struct desc_struct *desc,
29extern struct desc_ptr idt_descr; 29extern struct desc_ptr idt_descr;
30extern gate_desc idt_table[]; 30extern gate_desc idt_table[];
31 31
32struct gdt_page {
33 struct desc_struct gdt[GDT_ENTRIES];
34} __attribute__((aligned(PAGE_SIZE)));
35DECLARE_PER_CPU(struct gdt_page, gdt_page);
36
37static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
38{
39 return per_cpu(gdt_page, cpu).gdt;
40}
41
32#ifdef CONFIG_X86_64 42#ifdef CONFIG_X86_64
33extern struct desc_struct cpu_gdt_table[GDT_ENTRIES];
34extern struct desc_ptr cpu_gdt_descr[];
35/* the cpu gdt accessor */
36#define get_cpu_gdt_table(x) ((struct desc_struct *)cpu_gdt_descr[x].address)
37 43
38static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func, 44static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
39 unsigned dpl, unsigned ist, unsigned seg) 45 unsigned dpl, unsigned ist, unsigned seg)
@@ -51,16 +57,6 @@ static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
51} 57}
52 58
53#else 59#else
54struct gdt_page {
55 struct desc_struct gdt[GDT_ENTRIES];
56} __attribute__((aligned(PAGE_SIZE)));
57DECLARE_PER_CPU(struct gdt_page, gdt_page);
58
59static inline struct desc_struct *get_cpu_gdt_table(unsigned int cpu)
60{
61 return per_cpu(gdt_page, cpu).gdt;
62}
63
64static inline void pack_gate(gate_desc *gate, unsigned char type, 60static inline void pack_gate(gate_desc *gate, unsigned char type,
65 unsigned long base, unsigned dpl, unsigned flags, 61 unsigned long base, unsigned dpl, unsigned flags,
66 unsigned short seg) 62 unsigned short seg)
@@ -192,8 +188,8 @@ static inline void native_set_ldt(const void *addr, unsigned int entries)
192 unsigned cpu = smp_processor_id(); 188 unsigned cpu = smp_processor_id();
193 ldt_desc ldt; 189 ldt_desc ldt;
194 190
195 set_tssldt_descriptor(&ldt, (unsigned long)addr, 191 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
196 DESC_LDT, entries * sizeof(ldt) - 1); 192 entries * LDT_ENTRY_SIZE - 1);
197 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT, 193 write_gdt_entry(get_cpu_gdt_table(cpu), GDT_ENTRY_LDT,
198 &ldt, DESC_LDT); 194 &ldt, DESC_LDT);
199 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8)); 195 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
@@ -311,6 +307,28 @@ static inline void set_intr_gate(unsigned int n, void *addr)
311 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS); 307 _set_gate(n, GATE_INTERRUPT, addr, 0, 0, __KERNEL_CS);
312} 308}
313 309
310#define SYS_VECTOR_FREE 0
311#define SYS_VECTOR_ALLOCED 1
312
313extern int first_system_vector;
314extern char system_vectors[];
315
316static inline void alloc_system_vector(int vector)
317{
318 if (system_vectors[vector] == SYS_VECTOR_FREE) {
319 system_vectors[vector] = SYS_VECTOR_ALLOCED;
320 if (first_system_vector > vector)
321 first_system_vector = vector;
322 } else
323 BUG();
324}
325
326static inline void alloc_intr_gate(unsigned int n, void *addr)
327{
328 alloc_system_vector(n);
329 set_intr_gate(n, addr);
330}
331
314/* 332/*
315 * This routine sets up an interrupt gate at directory privilege level 3. 333 * This routine sets up an interrupt gate at directory privilege level 3.
316 */ 334 */
diff --git a/include/asm-x86/desc_defs.h b/include/asm-x86/desc_defs.h
index eccb4ea1f918..f7bacf357dac 100644
--- a/include/asm-x86/desc_defs.h
+++ b/include/asm-x86/desc_defs.h
@@ -75,10 +75,14 @@ struct ldttss_desc64 {
75typedef struct gate_struct64 gate_desc; 75typedef struct gate_struct64 gate_desc;
76typedef struct ldttss_desc64 ldt_desc; 76typedef struct ldttss_desc64 ldt_desc;
77typedef struct ldttss_desc64 tss_desc; 77typedef struct ldttss_desc64 tss_desc;
78#define gate_offset(g) ((g).offset_low | ((unsigned long)(g).offset_middle << 16) | ((unsigned long)(g).offset_high << 32))
79#define gate_segment(g) ((g).segment)
78#else 80#else
79typedef struct desc_struct gate_desc; 81typedef struct desc_struct gate_desc;
80typedef struct desc_struct ldt_desc; 82typedef struct desc_struct ldt_desc;
81typedef struct desc_struct tss_desc; 83typedef struct desc_struct tss_desc;
84#define gate_offset(g) (((g).b & 0xffff0000) | ((g).a & 0x0000ffff))
85#define gate_segment(g) ((g).a >> 16)
82#endif 86#endif
83 87
84struct desc_ptr { 88struct desc_ptr {
diff --git a/include/asm-x86/dmi.h b/include/asm-x86/dmi.h
index 4edf7514a750..58a86571fe0f 100644
--- a/include/asm-x86/dmi.h
+++ b/include/asm-x86/dmi.h
@@ -3,12 +3,6 @@
3 3
4#include <asm/io.h> 4#include <asm/io.h>
5 5
6#ifdef CONFIG_X86_32
7
8#define dmi_alloc alloc_bootmem
9
10#else /* CONFIG_X86_32 */
11
12#define DMI_MAX_DATA 2048 6#define DMI_MAX_DATA 2048
13 7
14extern int dmi_alloc_index; 8extern int dmi_alloc_index;
@@ -25,8 +19,6 @@ static inline void *dmi_alloc(unsigned len)
25 return dmi_alloc_data + idx; 19 return dmi_alloc_data + idx;
26} 20}
27 21
28#endif
29
30/* Use early IO mappings for DMI because it's initialized early */ 22/* Use early IO mappings for DMI because it's initialized early */
31#define dmi_ioremap early_ioremap 23#define dmi_ioremap early_ioremap
32#define dmi_iounmap early_iounmap 24#define dmi_iounmap early_iounmap
diff --git a/include/asm-x86/dwarf2.h b/include/asm-x86/dwarf2.h
index b3cbb0ccae18..738bb9fb3e53 100644
--- a/include/asm-x86/dwarf2.h
+++ b/include/asm-x86/dwarf2.h
@@ -1,5 +1,61 @@
1#ifdef CONFIG_X86_32 1#ifndef _DWARF2_H
2# include "dwarf2_32.h" 2#define _DWARF2_H
3
4#ifndef __ASSEMBLY__
5#warning "asm/dwarf2.h should be only included in pure assembly files"
6#endif
7
8/*
9 Macros for dwarf2 CFI unwind table entries.
10 See "as.info" for details on these pseudo ops. Unfortunately
11 they are only supported in very new binutils, so define them
12 away for older version.
13 */
14
15#ifdef CONFIG_AS_CFI
16
17#define CFI_STARTPROC .cfi_startproc
18#define CFI_ENDPROC .cfi_endproc
19#define CFI_DEF_CFA .cfi_def_cfa
20#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
21#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
22#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
23#define CFI_OFFSET .cfi_offset
24#define CFI_REL_OFFSET .cfi_rel_offset
25#define CFI_REGISTER .cfi_register
26#define CFI_RESTORE .cfi_restore
27#define CFI_REMEMBER_STATE .cfi_remember_state
28#define CFI_RESTORE_STATE .cfi_restore_state
29#define CFI_UNDEFINED .cfi_undefined
30
31#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
32#define CFI_SIGNAL_FRAME .cfi_signal_frame
33#else
34#define CFI_SIGNAL_FRAME
35#endif
36
3#else 37#else
4# include "dwarf2_64.h" 38
39/* Due to the structure of pre-exisiting code, don't use assembler line
40 comment character # to ignore the arguments. Instead, use a dummy macro. */
41.macro cfi_ignore a=0, b=0, c=0, d=0
42.endm
43
44#define CFI_STARTPROC cfi_ignore
45#define CFI_ENDPROC cfi_ignore
46#define CFI_DEF_CFA cfi_ignore
47#define CFI_DEF_CFA_REGISTER cfi_ignore
48#define CFI_DEF_CFA_OFFSET cfi_ignore
49#define CFI_ADJUST_CFA_OFFSET cfi_ignore
50#define CFI_OFFSET cfi_ignore
51#define CFI_REL_OFFSET cfi_ignore
52#define CFI_REGISTER cfi_ignore
53#define CFI_RESTORE cfi_ignore
54#define CFI_REMEMBER_STATE cfi_ignore
55#define CFI_RESTORE_STATE cfi_ignore
56#define CFI_UNDEFINED cfi_ignore
57#define CFI_SIGNAL_FRAME cfi_ignore
58
59#endif
60
5#endif 61#endif
diff --git a/include/asm-x86/dwarf2_32.h b/include/asm-x86/dwarf2_32.h
deleted file mode 100644
index 6d66398a307d..000000000000
--- a/include/asm-x86/dwarf2_32.h
+++ /dev/null
@@ -1,61 +0,0 @@
1#ifndef _DWARF2_H
2#define _DWARF2_H
3
4#ifndef __ASSEMBLY__
5#warning "asm/dwarf2.h should be only included in pure assembly files"
6#endif
7
8/*
9 Macros for dwarf2 CFI unwind table entries.
10 See "as.info" for details on these pseudo ops. Unfortunately
11 they are only supported in very new binutils, so define them
12 away for older version.
13 */
14
15#ifdef CONFIG_UNWIND_INFO
16
17#define CFI_STARTPROC .cfi_startproc
18#define CFI_ENDPROC .cfi_endproc
19#define CFI_DEF_CFA .cfi_def_cfa
20#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
21#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
22#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
23#define CFI_OFFSET .cfi_offset
24#define CFI_REL_OFFSET .cfi_rel_offset
25#define CFI_REGISTER .cfi_register
26#define CFI_RESTORE .cfi_restore
27#define CFI_REMEMBER_STATE .cfi_remember_state
28#define CFI_RESTORE_STATE .cfi_restore_state
29#define CFI_UNDEFINED .cfi_undefined
30
31#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
32#define CFI_SIGNAL_FRAME .cfi_signal_frame
33#else
34#define CFI_SIGNAL_FRAME
35#endif
36
37#else
38
39/* Due to the structure of pre-exisiting code, don't use assembler line
40 comment character # to ignore the arguments. Instead, use a dummy macro. */
41.macro ignore a=0, b=0, c=0, d=0
42.endm
43
44#define CFI_STARTPROC ignore
45#define CFI_ENDPROC ignore
46#define CFI_DEF_CFA ignore
47#define CFI_DEF_CFA_REGISTER ignore
48#define CFI_DEF_CFA_OFFSET ignore
49#define CFI_ADJUST_CFA_OFFSET ignore
50#define CFI_OFFSET ignore
51#define CFI_REL_OFFSET ignore
52#define CFI_REGISTER ignore
53#define CFI_RESTORE ignore
54#define CFI_REMEMBER_STATE ignore
55#define CFI_RESTORE_STATE ignore
56#define CFI_UNDEFINED ignore
57#define CFI_SIGNAL_FRAME ignore
58
59#endif
60
61#endif
diff --git a/include/asm-x86/dwarf2_64.h b/include/asm-x86/dwarf2_64.h
deleted file mode 100644
index c950519a264d..000000000000
--- a/include/asm-x86/dwarf2_64.h
+++ /dev/null
@@ -1,56 +0,0 @@
1#ifndef _DWARF2_H
2#define _DWARF2_H 1
3
4#ifndef __ASSEMBLY__
5#warning "asm/dwarf2.h should be only included in pure assembly files"
6#endif
7
8/*
9 Macros for dwarf2 CFI unwind table entries.
10 See "as.info" for details on these pseudo ops. Unfortunately
11 they are only supported in very new binutils, so define them
12 away for older version.
13 */
14
15#ifdef CONFIG_AS_CFI
16
17#define CFI_STARTPROC .cfi_startproc
18#define CFI_ENDPROC .cfi_endproc
19#define CFI_DEF_CFA .cfi_def_cfa
20#define CFI_DEF_CFA_REGISTER .cfi_def_cfa_register
21#define CFI_DEF_CFA_OFFSET .cfi_def_cfa_offset
22#define CFI_ADJUST_CFA_OFFSET .cfi_adjust_cfa_offset
23#define CFI_OFFSET .cfi_offset
24#define CFI_REL_OFFSET .cfi_rel_offset
25#define CFI_REGISTER .cfi_register
26#define CFI_RESTORE .cfi_restore
27#define CFI_REMEMBER_STATE .cfi_remember_state
28#define CFI_RESTORE_STATE .cfi_restore_state
29#define CFI_UNDEFINED .cfi_undefined
30#ifdef CONFIG_AS_CFI_SIGNAL_FRAME
31#define CFI_SIGNAL_FRAME .cfi_signal_frame
32#else
33#define CFI_SIGNAL_FRAME
34#endif
35
36#else
37
38/* use assembler line comment character # to ignore the arguments. */
39#define CFI_STARTPROC #
40#define CFI_ENDPROC #
41#define CFI_DEF_CFA #
42#define CFI_DEF_CFA_REGISTER #
43#define CFI_DEF_CFA_OFFSET #
44#define CFI_ADJUST_CFA_OFFSET #
45#define CFI_OFFSET #
46#define CFI_REL_OFFSET #
47#define CFI_REGISTER #
48#define CFI_RESTORE #
49#define CFI_REMEMBER_STATE #
50#define CFI_RESTORE_STATE #
51#define CFI_UNDEFINED #
52#define CFI_SIGNAL_FRAME #
53
54#endif
55
56#endif
diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h
index 7004251fc66b..33e793e991d0 100644
--- a/include/asm-x86/e820.h
+++ b/include/asm-x86/e820.h
@@ -2,6 +2,41 @@
2#define __ASM_E820_H 2#define __ASM_E820_H
3#define E820MAP 0x2d0 /* our map */ 3#define E820MAP 0x2d0 /* our map */
4#define E820MAX 128 /* number of entries in E820MAP */ 4#define E820MAX 128 /* number of entries in E820MAP */
5
6/*
7 * Legacy E820 BIOS limits us to 128 (E820MAX) nodes due to the
8 * constrained space in the zeropage. If we have more nodes than
9 * that, and if we've booted off EFI firmware, then the EFI tables
10 * passed us from the EFI firmware can list more nodes. Size our
11 * internal memory map tables to have room for these additional
12 * nodes, based on up to three entries per node for which the
13 * kernel was built: MAX_NUMNODES == (1 << CONFIG_NODES_SHIFT),
14 * plus E820MAX, allowing space for the possible duplicate E820
15 * entries that might need room in the same arrays, prior to the
16 * call to sanitize_e820_map() to remove duplicates. The allowance
17 * of three memory map entries per node is "enough" entries for
18 * the initial hardware platform motivating this mechanism to make
19 * use of additional EFI map entries. Future platforms may want
20 * to allow more than three entries per node or otherwise refine
21 * this size.
22 */
23
24/*
25 * Odd: 'make headers_check' complains about numa.h if I try
26 * to collapse the next two #ifdef lines to a single line:
27 * #if defined(__KERNEL__) && defined(CONFIG_EFI)
28 */
29#ifdef __KERNEL__
30#ifdef CONFIG_EFI
31#include <linux/numa.h>
32#define E820_X_MAX (E820MAX + 3 * MAX_NUMNODES)
33#else /* ! CONFIG_EFI */
34#define E820_X_MAX E820MAX
35#endif
36#else /* ! __KERNEL__ */
37#define E820_X_MAX E820MAX
38#endif
39
5#define E820NR 0x1e8 /* # entries in E820MAP */ 40#define E820NR 0x1e8 /* # entries in E820MAP */
6 41
7#define E820_RAM 1 42#define E820_RAM 1
@@ -9,6 +44,9 @@
9#define E820_ACPI 3 44#define E820_ACPI 3
10#define E820_NVS 4 45#define E820_NVS 4
11 46
47/* reserved RAM used by kernel itself */
48#define E820_RESERVED_KERN 128
49
12#ifndef __ASSEMBLY__ 50#ifndef __ASSEMBLY__
13struct e820entry { 51struct e820entry {
14 __u64 addr; /* start of memory segment */ 52 __u64 addr; /* start of memory segment */
@@ -18,22 +56,79 @@ struct e820entry {
18 56
19struct e820map { 57struct e820map {
20 __u32 nr_map; 58 __u32 nr_map;
21 struct e820entry map[E820MAX]; 59 struct e820entry map[E820_X_MAX];
22}; 60};
61
62/* see comment in arch/x86/kernel/e820.c */
63extern struct e820map e820;
64extern struct e820map e820_saved;
65
66extern int e820_any_mapped(u64 start, u64 end, unsigned type);
67extern int e820_all_mapped(u64 start, u64 end, unsigned type);
68extern void e820_add_region(u64 start, u64 size, int type);
69extern void e820_print_map(char *who);
70extern int
71sanitize_e820_map(struct e820entry *biosmap, int max_nr_map, int *pnr_map);
72extern u64 e820_update_range(u64 start, u64 size, unsigned old_type,
73 unsigned new_type);
74extern u64 e820_remove_range(u64 start, u64 size, unsigned old_type,
75 int checktype);
76extern void update_e820(void);
77extern void e820_setup_gap(void);
78extern int e820_search_gap(unsigned long *gapstart, unsigned long *gapsize,
79 unsigned long start_addr, unsigned long long end_addr);
80struct setup_data;
81extern void parse_e820_ext(struct setup_data *data, unsigned long pa_data);
82
83#if defined(CONFIG_X86_64) || \
84 (defined(CONFIG_X86_32) && defined(CONFIG_HIBERNATION))
85extern void e820_mark_nosave_regions(unsigned long limit_pfn);
86#else
87static inline void e820_mark_nosave_regions(unsigned long limit_pfn)
88{
89}
90#endif
91
92extern unsigned long end_user_pfn;
93
94extern u64 find_e820_area(u64 start, u64 end, u64 size, u64 align);
95extern u64 find_e820_area_size(u64 start, u64 *sizep, u64 align);
96extern void reserve_early(u64 start, u64 end, char *name);
97extern void reserve_early_overlap_ok(u64 start, u64 end, char *name);
98extern void free_early(u64 start, u64 end);
99extern void early_res_to_bootmem(u64 start, u64 end);
100extern u64 early_reserve_e820(u64 startt, u64 sizet, u64 align);
101
102extern unsigned long e820_end_of_ram_pfn(void);
103extern unsigned long e820_end_of_low_ram_pfn(void);
104extern int e820_find_active_region(const struct e820entry *ei,
105 unsigned long start_pfn,
106 unsigned long last_pfn,
107 unsigned long *ei_startpfn,
108 unsigned long *ei_endpfn);
109extern void e820_register_active_regions(int nid, unsigned long start_pfn,
110 unsigned long end_pfn);
111extern u64 e820_hole_size(u64 start, u64 end);
112extern void finish_e820_parsing(void);
113extern void e820_reserve_resources(void);
114extern void setup_memory_map(void);
115extern char *default_machine_specific_memory_setup(void);
116extern char *machine_specific_memory_setup(void);
117extern char *memory_setup(void);
118
23#endif /* __ASSEMBLY__ */ 119#endif /* __ASSEMBLY__ */
24 120
25#define ISA_START_ADDRESS 0xa0000 121#define ISA_START_ADDRESS 0xa0000
26#define ISA_END_ADDRESS 0x100000 122#define ISA_END_ADDRESS 0x100000
123#define is_ISA_range(s, e) ((s) >= ISA_START_ADDRESS && (e) < ISA_END_ADDRESS)
27 124
28#define BIOS_BEGIN 0x000a0000 125#define BIOS_BEGIN 0x000a0000
29#define BIOS_END 0x00100000 126#define BIOS_END 0x00100000
30 127
31#ifdef __KERNEL__ 128#ifdef __KERNEL__
32#ifdef CONFIG_X86_32 129#include <linux/ioport.h>
33# include "e820_32.h" 130
34#else 131#define HIGH_MEMORY (1024*1024)
35# include "e820_64.h"
36#endif
37#endif /* __KERNEL__ */ 132#endif /* __KERNEL__ */
38 133
39#endif /* __ASM_E820_H */ 134#endif /* __ASM_E820_H */
diff --git a/include/asm-x86/e820_32.h b/include/asm-x86/e820_32.h
deleted file mode 100644
index a9f7c6ec32bf..000000000000
--- a/include/asm-x86/e820_32.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * structures and definitions for the int 15, ax=e820 memory map
3 * scheme.
4 *
5 * In a nutshell, arch/i386/boot/setup.S populates a scratch table
6 * in the empty_zero_block that contains a list of usable address/size
7 * duples. In arch/i386/kernel/setup.c, this information is
8 * transferred into the e820map, and in arch/i386/mm/init.c, that
9 * new information is used to mark pages reserved or not.
10 *
11 */
12#ifndef __E820_HEADER
13#define __E820_HEADER
14
15#include <linux/ioport.h>
16
17#define HIGH_MEMORY (1024*1024)
18
19#ifndef __ASSEMBLY__
20
21extern struct e820map e820;
22extern void update_e820(void);
23
24extern int e820_all_mapped(unsigned long start, unsigned long end,
25 unsigned type);
26extern int e820_any_mapped(u64 start, u64 end, unsigned type);
27extern void propagate_e820_map(void);
28extern void register_bootmem_low_pages(unsigned long max_low_pfn);
29extern void add_memory_region(unsigned long long start,
30 unsigned long long size, int type);
31extern void update_memory_range(u64 start, u64 size, unsigned old_type,
32 unsigned new_type);
33extern void e820_register_memory(void);
34extern void limit_regions(unsigned long long size);
35extern void print_memory_map(char *who);
36extern void init_iomem_resources(struct resource *code_resource,
37 struct resource *data_resource,
38 struct resource *bss_resource);
39
40#if defined(CONFIG_PM) && defined(CONFIG_HIBERNATION)
41extern void e820_mark_nosave_regions(void);
42#else
43static inline void e820_mark_nosave_regions(void)
44{
45}
46#endif
47
48
49#endif/*!__ASSEMBLY__*/
50#endif/*__E820_HEADER*/
diff --git a/include/asm-x86/e820_64.h b/include/asm-x86/e820_64.h
deleted file mode 100644
index 71c4d685d30d..000000000000
--- a/include/asm-x86/e820_64.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * structures and definitions for the int 15, ax=e820 memory map
3 * scheme.
4 *
5 * In a nutshell, setup.S populates a scratch table in the
6 * empty_zero_block that contains a list of usable address/size
7 * duples. setup.c, this information is transferred into the e820map,
8 * and in init.c/numa.c, that new information is used to mark pages
9 * reserved or not.
10 */
11#ifndef __E820_HEADER
12#define __E820_HEADER
13
14#include <linux/ioport.h>
15
16#ifndef __ASSEMBLY__
17extern unsigned long find_e820_area(unsigned long start, unsigned long end,
18 unsigned long size, unsigned long align);
19extern unsigned long find_e820_area_size(unsigned long start,
20 unsigned long *sizep,
21 unsigned long align);
22extern void add_memory_region(unsigned long start, unsigned long size,
23 int type);
24extern void update_memory_range(u64 start, u64 size, unsigned old_type,
25 unsigned new_type);
26extern void setup_memory_region(void);
27extern void contig_e820_setup(void);
28extern unsigned long e820_end_of_ram(void);
29extern void e820_reserve_resources(void);
30extern void e820_mark_nosave_regions(void);
31extern int e820_any_mapped(unsigned long start, unsigned long end,
32 unsigned type);
33extern int e820_all_mapped(unsigned long start, unsigned long end,
34 unsigned type);
35extern int e820_any_non_reserved(unsigned long start, unsigned long end);
36extern int is_memory_any_valid(unsigned long start, unsigned long end);
37extern int e820_all_non_reserved(unsigned long start, unsigned long end);
38extern int is_memory_all_valid(unsigned long start, unsigned long end);
39extern unsigned long e820_hole_size(unsigned long start, unsigned long end);
40
41extern void e820_setup_gap(void);
42extern void e820_register_active_regions(int nid, unsigned long start_pfn,
43 unsigned long end_pfn);
44
45extern void finish_e820_parsing(void);
46
47extern struct e820map e820;
48extern void update_e820(void);
49
50extern void reserve_early(unsigned long start, unsigned long end, char *name);
51extern void free_early(unsigned long start, unsigned long end);
52extern void early_res_to_bootmem(unsigned long start, unsigned long end);
53
54#endif/*!__ASSEMBLY__*/
55
56#endif/*__E820_HEADER*/
diff --git a/include/asm-x86/efi.h b/include/asm-x86/efi.h
index d53004b855cc..7ed2bd7a7f51 100644
--- a/include/asm-x86/efi.h
+++ b/include/asm-x86/efi.h
@@ -90,7 +90,7 @@ extern void *efi_ioremap(unsigned long addr, unsigned long size);
90 90
91#endif /* CONFIG_X86_32 */ 91#endif /* CONFIG_X86_32 */
92 92
93extern void efi_reserve_bootmem(void); 93extern void efi_reserve_early(void);
94extern void efi_call_phys_prelog(void); 94extern void efi_call_phys_prelog(void);
95extern void efi_call_phys_epilog(void); 95extern void efi_call_phys_epilog(void);
96 96
diff --git a/include/asm-x86/elf.h b/include/asm-x86/elf.h
index 8f232dc5b5fe..7be4733c793e 100644
--- a/include/asm-x86/elf.h
+++ b/include/asm-x86/elf.h
@@ -83,9 +83,9 @@ extern unsigned int vdso_enabled;
83 (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486)) 83 (((x)->e_machine == EM_386) || ((x)->e_machine == EM_486))
84 84
85#include <asm/processor.h> 85#include <asm/processor.h>
86#include <asm/system.h>
86 87
87#ifdef CONFIG_X86_32 88#ifdef CONFIG_X86_32
88#include <asm/system.h> /* for savesegment */
89#include <asm/desc.h> 89#include <asm/desc.h>
90 90
91#define elf_check_arch(x) elf_check_arch_ia32(x) 91#define elf_check_arch(x) elf_check_arch_ia32(x)
diff --git a/include/asm-x86/fixmap.h b/include/asm-x86/fixmap.h
index 5bd206973dca..44d4f8217349 100644
--- a/include/asm-x86/fixmap.h
+++ b/include/asm-x86/fixmap.h
@@ -7,7 +7,62 @@
7# include "fixmap_64.h" 7# include "fixmap_64.h"
8#endif 8#endif
9 9
10extern int fixmaps_set;
11
12void __native_set_fixmap(enum fixed_addresses idx, pte_t pte);
13void native_set_fixmap(enum fixed_addresses idx,
14 unsigned long phys, pgprot_t flags);
15
16#ifndef CONFIG_PARAVIRT
17static inline void __set_fixmap(enum fixed_addresses idx,
18 unsigned long phys, pgprot_t flags)
19{
20 native_set_fixmap(idx, phys, flags);
21}
22#endif
23
24#define set_fixmap(idx, phys) \
25 __set_fixmap(idx, phys, PAGE_KERNEL)
26
27/*
28 * Some hardware wants to get fixmapped without caching.
29 */
30#define set_fixmap_nocache(idx, phys) \
31 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
32
10#define clear_fixmap(idx) \ 33#define clear_fixmap(idx) \
11 __set_fixmap(idx, 0, __pgprot(0)) 34 __set_fixmap(idx, 0, __pgprot(0))
12 35
36#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
37#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
38
39extern void __this_fixmap_does_not_exist(void);
40
41/*
42 * 'index to address' translation. If anyone tries to use the idx
43 * directly without translation, we catch the bug with a NULL-deference
44 * kernel oops. Illegal ranges of incoming indices are caught too.
45 */
46static __always_inline unsigned long fix_to_virt(const unsigned int idx)
47{
48 /*
49 * this branch gets completely eliminated after inlining,
50 * except when someone tries to use fixaddr indices in an
51 * illegal way. (such as mixing up address types or using
52 * out-of-range indices).
53 *
54 * If it doesn't get removed, the linker will complain
55 * loudly with a reasonably clear error message..
56 */
57 if (idx >= __end_of_fixed_addresses)
58 __this_fixmap_does_not_exist();
59
60 return __fix_to_virt(idx);
61}
62
63static inline unsigned long virt_to_fix(const unsigned long vaddr)
64{
65 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
66 return __virt_to_fix(vaddr);
67}
13#endif 68#endif
diff --git a/include/asm-x86/fixmap_32.h b/include/asm-x86/fixmap_32.h
index 4b96148e90c1..aae2f0501a40 100644
--- a/include/asm-x86/fixmap_32.h
+++ b/include/asm-x86/fixmap_32.h
@@ -79,10 +79,6 @@ enum fixed_addresses {
79 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ 79 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
80 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, 80 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
81#endif 81#endif
82#ifdef CONFIG_ACPI
83 FIX_ACPI_BEGIN,
84 FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
85#endif
86#ifdef CONFIG_PCI_MMCONFIG 82#ifdef CONFIG_PCI_MMCONFIG
87 FIX_PCIE_MCFG, 83 FIX_PCIE_MCFG,
88#endif 84#endif
@@ -103,23 +99,18 @@ enum fixed_addresses {
103 (__end_of_permanent_fixed_addresses & 511), 99 (__end_of_permanent_fixed_addresses & 511),
104 FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_NESTING - 1, 100 FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_NESTING - 1,
105 FIX_WP_TEST, 101 FIX_WP_TEST,
102#ifdef CONFIG_ACPI
103 FIX_ACPI_BEGIN,
104 FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
105#endif
106#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT 106#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
107 FIX_OHCI1394_BASE, 107 FIX_OHCI1394_BASE,
108#endif 108#endif
109 __end_of_fixed_addresses 109 __end_of_fixed_addresses
110}; 110};
111 111
112extern void __set_fixmap(enum fixed_addresses idx,
113 unsigned long phys, pgprot_t flags);
114extern void reserve_top_address(unsigned long reserve); 112extern void reserve_top_address(unsigned long reserve);
115 113
116#define set_fixmap(idx, phys) \
117 __set_fixmap(idx, phys, PAGE_KERNEL)
118/*
119 * Some hardware wants to get fixmapped without caching.
120 */
121#define set_fixmap_nocache(idx, phys) \
122 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
123 114
124#define FIXADDR_TOP ((unsigned long)__FIXADDR_TOP) 115#define FIXADDR_TOP ((unsigned long)__FIXADDR_TOP)
125 116
@@ -128,38 +119,5 @@ extern void reserve_top_address(unsigned long reserve);
128#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE) 119#define FIXADDR_START (FIXADDR_TOP - __FIXADDR_SIZE)
129#define FIXADDR_BOOT_START (FIXADDR_TOP - __FIXADDR_BOOT_SIZE) 120#define FIXADDR_BOOT_START (FIXADDR_TOP - __FIXADDR_BOOT_SIZE)
130 121
131#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
132#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
133
134extern void __this_fixmap_does_not_exist(void);
135
136/*
137 * 'index to address' translation. If anyone tries to use the idx
138 * directly without tranlation, we catch the bug with a NULL-deference
139 * kernel oops. Illegal ranges of incoming indices are caught too.
140 */
141static __always_inline unsigned long fix_to_virt(const unsigned int idx)
142{
143 /*
144 * this branch gets completely eliminated after inlining,
145 * except when someone tries to use fixaddr indices in an
146 * illegal way. (such as mixing up address types or using
147 * out-of-range indices).
148 *
149 * If it doesn't get removed, the linker will complain
150 * loudly with a reasonably clear error message..
151 */
152 if (idx >= __end_of_fixed_addresses)
153 __this_fixmap_does_not_exist();
154
155 return __fix_to_virt(idx);
156}
157
158static inline unsigned long virt_to_fix(const unsigned long vaddr)
159{
160 BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
161 return __virt_to_fix(vaddr);
162}
163
164#endif /* !__ASSEMBLY__ */ 122#endif /* !__ASSEMBLY__ */
165#endif 123#endif
diff --git a/include/asm-x86/fixmap_64.h b/include/asm-x86/fixmap_64.h
index 355d26a75a82..00f3d74a0524 100644
--- a/include/asm-x86/fixmap_64.h
+++ b/include/asm-x86/fixmap_64.h
@@ -12,6 +12,7 @@
12#define _ASM_FIXMAP_64_H 12#define _ASM_FIXMAP_64_H
13 13
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <asm/acpi.h>
15#include <asm/apicdef.h> 16#include <asm/apicdef.h>
16#include <asm/page.h> 17#include <asm/page.h>
17#include <asm/vsyscall.h> 18#include <asm/vsyscall.h>
@@ -39,30 +40,38 @@ enum fixed_addresses {
39 VSYSCALL_HPET, 40 VSYSCALL_HPET,
40 FIX_DBGP_BASE, 41 FIX_DBGP_BASE,
41 FIX_EARLYCON_MEM_BASE, 42 FIX_EARLYCON_MEM_BASE,
42 FIX_HPET_BASE,
43 FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */ 43 FIX_APIC_BASE, /* local (CPU) APIC) -- required for SMP or not */
44 FIX_IO_APIC_BASE_0, 44 FIX_IO_APIC_BASE_0,
45 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1, 45 FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
46 FIX_EFI_IO_MAP_LAST_PAGE, 46 FIX_EFI_IO_MAP_LAST_PAGE,
47 FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE 47 FIX_EFI_IO_MAP_FIRST_PAGE = FIX_EFI_IO_MAP_LAST_PAGE
48 + MAX_EFI_IO_PAGES - 1, 48 + MAX_EFI_IO_PAGES - 1,
49#ifdef CONFIG_PARAVIRT
50 FIX_PARAVIRT_BOOTMAP,
51#endif
52#ifdef CONFIG_ACPI
53 FIX_ACPI_BEGIN,
54 FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
55#endif
49#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT 56#ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
50 FIX_OHCI1394_BASE, 57 FIX_OHCI1394_BASE,
51#endif 58#endif
59 __end_of_permanent_fixed_addresses,
60 /*
61 * 256 temporary boot-time mappings, used by early_ioremap(),
62 * before ioremap() is functional.
63 *
64 * We round it up to the next 512 pages boundary so that we
65 * can have a single pgd entry and a single pte table:
66 */
67#define NR_FIX_BTMAPS 64
68#define FIX_BTMAPS_NESTING 4
69 FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 512 -
70 (__end_of_permanent_fixed_addresses & 511),
71 FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_NESTING - 1,
52 __end_of_fixed_addresses 72 __end_of_fixed_addresses
53}; 73};
54 74
55extern void __set_fixmap(enum fixed_addresses idx,
56 unsigned long phys, pgprot_t flags);
57
58#define set_fixmap(idx, phys) \
59 __set_fixmap(idx, phys, PAGE_KERNEL)
60/*
61 * Some hardware wants to get fixmapped without caching.
62 */
63#define set_fixmap_nocache(idx, phys) \
64 __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
65
66#define FIXADDR_TOP (VSYSCALL_END-PAGE_SIZE) 75#define FIXADDR_TOP (VSYSCALL_END-PAGE_SIZE)
67#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) 76#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
68#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) 77#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
@@ -71,30 +80,4 @@ extern void __set_fixmap(enum fixed_addresses idx,
71#define FIXADDR_USER_START ((unsigned long)VSYSCALL32_VSYSCALL) 80#define FIXADDR_USER_START ((unsigned long)VSYSCALL32_VSYSCALL)
72#define FIXADDR_USER_END (FIXADDR_USER_START + PAGE_SIZE) 81#define FIXADDR_USER_END (FIXADDR_USER_START + PAGE_SIZE)
73 82
74#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
75
76extern void __this_fixmap_does_not_exist(void);
77
78/*
79 * 'index to address' translation. If anyone tries to use the idx
80 * directly without translation, we catch the bug with a NULL-deference
81 * kernel oops. Illegal ranges of incoming indices are caught too.
82 */
83static __always_inline unsigned long fix_to_virt(const unsigned int idx)
84{
85 /*
86 * this branch gets completely eliminated after inlining,
87 * except when someone tries to use fixaddr indices in an
88 * illegal way. (such as mixing up address types or using
89 * out-of-range indices).
90 *
91 * If it doesn't get removed, the linker will complain
92 * loudly with a reasonably clear error message..
93 */
94 if (idx >= __end_of_fixed_addresses)
95 __this_fixmap_does_not_exist();
96
97 return __fix_to_virt(idx);
98}
99
100#endif 83#endif
diff --git a/include/asm-x86/ftrace.h b/include/asm-x86/ftrace.h
new file mode 100644
index 000000000000..c184441133f2
--- /dev/null
+++ b/include/asm-x86/ftrace.h
@@ -0,0 +1,14 @@
1#ifndef _ASM_X86_FTRACE
2#define _ASM_SPARC64_FTRACE
3
4#ifdef CONFIG_FTRACE
5#define MCOUNT_ADDR ((long)(mcount))
6#define MCOUNT_INSN_SIZE 5 /* sizeof mcount call */
7
8#ifndef __ASSEMBLY__
9extern void mcount(void);
10#endif
11
12#endif /* CONFIG_FTRACE */
13
14#endif /* _ASM_X86_FTRACE */
diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h
index 90958ed993fa..33b9aeeb35a2 100644
--- a/include/asm-x86/gart.h
+++ b/include/asm-x86/gart.h
@@ -1,34 +1,72 @@
1#ifndef _ASM_X8664_IOMMU_H 1#ifndef _ASM_X8664_GART_H
2#define _ASM_X8664_IOMMU_H 1 2#define _ASM_X8664_GART_H 1
3 3
4extern void pci_iommu_shutdown(void); 4#include <asm/e820.h>
5extern void no_iommu_init(void); 5#include <asm/iommu.h>
6extern int force_iommu, no_iommu; 6
7extern int iommu_detected; 7extern void set_up_gart_resume(u32, u32);
8#ifdef CONFIG_GART_IOMMU 8
9extern void gart_iommu_init(void);
10extern void gart_iommu_shutdown(void);
11extern void __init gart_parse_options(char *);
12extern void early_gart_iommu_check(void);
13extern void gart_iommu_hole_init(void);
14extern int fallback_aper_order; 9extern int fallback_aper_order;
15extern int fallback_aper_force; 10extern int fallback_aper_force;
16extern int gart_iommu_aperture;
17extern int gart_iommu_aperture_allowed;
18extern int gart_iommu_aperture_disabled;
19extern int fix_aperture; 11extern int fix_aperture;
20#else
21#define gart_iommu_aperture 0
22#define gart_iommu_aperture_allowed 0
23 12
24static inline void early_gart_iommu_check(void) 13/* PTE bits. */
14#define GPTE_VALID 1
15#define GPTE_COHERENT 2
16
17/* Aperture control register bits. */
18#define GARTEN (1<<0)
19#define DISGARTCPU (1<<4)
20#define DISGARTIO (1<<5)
21
22/* GART cache control register bits. */
23#define INVGART (1<<0)
24#define GARTPTEERR (1<<1)
25
26/* K8 On-cpu GART registers */
27#define AMD64_GARTAPERTURECTL 0x90
28#define AMD64_GARTAPERTUREBASE 0x94
29#define AMD64_GARTTABLEBASE 0x98
30#define AMD64_GARTCACHECTL 0x9c
31#define AMD64_GARTEN (1<<0)
32
33static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
25{ 34{
35 u32 tmp, ctl;
36
37 /* address of the mappings table */
38 addr >>= 12;
39 tmp = (u32) addr<<4;
40 tmp &= ~0xf;
41 pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
42
43 /* Enable GART translation for this hammer. */
44 pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
45 ctl |= GARTEN;
46 ctl &= ~(DISGARTCPU | DISGARTIO);
47 pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
26} 48}
27 49
28static inline void gart_iommu_shutdown(void) 50static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
29{ 51{
30} 52 if (!aper_base)
53 return 0;
31 54
32#endif 55 if (aper_base + aper_size > 0x100000000ULL) {
56 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
57 return 0;
58 }
59 if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
60 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
61 return 0;
62 }
63 if (aper_size < min_size) {
64 printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
65 aper_size>>20, min_size>>20);
66 return 0;
67 }
68
69 return 1;
70}
33 71
34#endif 72#endif
diff --git a/include/asm-x86/genapic_64.h b/include/asm-x86/genapic_64.h
index 1de931b263ce..0f8504627c41 100644
--- a/include/asm-x86/genapic_64.h
+++ b/include/asm-x86/genapic_64.h
@@ -44,4 +44,6 @@ DECLARE_PER_CPU(int, x2apic_extra_bits);
44extern void uv_cpu_init(void); 44extern void uv_cpu_init(void);
45extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip); 45extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip);
46 46
47extern void setup_apic_routing(void);
48
47#endif 49#endif
diff --git a/include/asm-x86/hardirq.h b/include/asm-x86/hardirq.h
index 314434d664e7..000787df66e6 100644
--- a/include/asm-x86/hardirq.h
+++ b/include/asm-x86/hardirq.h
@@ -3,3 +3,9 @@
3#else 3#else
4# include "hardirq_64.h" 4# include "hardirq_64.h"
5#endif 5#endif
6
7extern u64 arch_irq_stat_cpu(unsigned int cpu);
8#define arch_irq_stat_cpu arch_irq_stat_cpu
9
10extern u64 arch_irq_stat(void);
11#define arch_irq_stat arch_irq_stat
diff --git a/include/asm-x86/highmem.h b/include/asm-x86/highmem.h
index e153f3b44774..4514b16cc723 100644
--- a/include/asm-x86/highmem.h
+++ b/include/asm-x86/highmem.h
@@ -74,6 +74,9 @@ struct page *kmap_atomic_to_page(void *ptr);
74 74
75#define flush_cache_kmaps() do { } while (0) 75#define flush_cache_kmaps() do { } while (0)
76 76
77extern void add_highpages_with_active_regions(int nid, unsigned long start_pfn,
78 unsigned long end_pfn);
79
77#endif /* __KERNEL__ */ 80#endif /* __KERNEL__ */
78 81
79#endif /* _ASM_HIGHMEM_H */ 82#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h
index 6a9b4ac59bf7..82f1ac641bd7 100644
--- a/include/asm-x86/hpet.h
+++ b/include/asm-x86/hpet.h
@@ -86,8 +86,8 @@ extern void hpet_unregister_irq_handler(rtc_irq_handler handler);
86#else /* CONFIG_HPET_TIMER */ 86#else /* CONFIG_HPET_TIMER */
87 87
88static inline int hpet_enable(void) { return 0; } 88static inline int hpet_enable(void) { return 0; }
89static inline unsigned long hpet_readl(unsigned long a) { return 0; }
90static inline int is_hpet_enabled(void) { return 0; } 89static inline int is_hpet_enabled(void) { return 0; }
90#define hpet_readl(a) 0
91 91
92#endif 92#endif
93#endif /* ASM_X86_HPET_H */ 93#endif /* ASM_X86_HPET_H */
diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h
index bf025399d939..77ba51df5668 100644
--- a/include/asm-x86/hw_irq.h
+++ b/include/asm-x86/hw_irq.h
@@ -1,5 +1,107 @@
1#ifndef _ASM_HW_IRQ_H
2#define _ASM_HW_IRQ_H
3
4/*
5 * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
6 *
7 * moved some of the old arch/i386/kernel/irq.h to here. VY
8 *
9 * IRQ/IPI changes taken from work by Thomas Radke
10 * <tomsoft@informatik.tu-chemnitz.de>
11 *
12 * hacked by Andi Kleen for x86-64.
13 * unified by tglx
14 */
15
16#include <asm/irq_vectors.h>
17
18#ifndef __ASSEMBLY__
19
20#include <linux/percpu.h>
21#include <linux/profile.h>
22#include <linux/smp.h>
23
24#include <asm/atomic.h>
25#include <asm/irq.h>
26#include <asm/sections.h>
27
28#define platform_legacy_irq(irq) ((irq) < 16)
29
30/* Interrupt handlers registered during init_IRQ */
31extern void apic_timer_interrupt(void);
32extern void error_interrupt(void);
33extern void spurious_interrupt(void);
34extern void thermal_interrupt(void);
35extern void reschedule_interrupt(void);
36
37extern void invalidate_interrupt(void);
38extern void invalidate_interrupt0(void);
39extern void invalidate_interrupt1(void);
40extern void invalidate_interrupt2(void);
41extern void invalidate_interrupt3(void);
42extern void invalidate_interrupt4(void);
43extern void invalidate_interrupt5(void);
44extern void invalidate_interrupt6(void);
45extern void invalidate_interrupt7(void);
46
47extern void irq_move_cleanup_interrupt(void);
48extern void threshold_interrupt(void);
49
50extern void call_function_interrupt(void);
51extern void call_function_single_interrupt(void);
52
53/* PIC specific functions */
54extern void disable_8259A_irq(unsigned int irq);
55extern void enable_8259A_irq(unsigned int irq);
56extern int i8259A_irq_pending(unsigned int irq);
57extern void make_8259A_irq(unsigned int irq);
58extern void init_8259A(int aeoi);
59
60/* IOAPIC */
61#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
62extern unsigned long io_apic_irqs;
63
64extern void init_VISWS_APIC_irqs(void);
65extern void setup_IO_APIC(void);
66extern void disable_IO_APIC(void);
67extern void print_IO_APIC(void);
68extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
69extern void setup_ioapic_dest(void);
70
71#ifdef CONFIG_X86_64
72extern void enable_IO_APIC(void);
73#endif
74
75/* IPI functions */
76extern void send_IPI_self(int vector);
77extern void send_IPI(int dest, int vector);
78
79/* Statistics */
80extern atomic_t irq_err_count;
81extern atomic_t irq_mis_count;
82
83/* EISA */
84extern void eisa_set_level_irq(unsigned int irq);
85
86/* Voyager functions */
87extern asmlinkage void vic_cpi_interrupt(void);
88extern asmlinkage void vic_sys_interrupt(void);
89extern asmlinkage void vic_cmn_interrupt(void);
90extern asmlinkage void qic_timer_interrupt(void);
91extern asmlinkage void qic_invalidate_interrupt(void);
92extern asmlinkage void qic_reschedule_interrupt(void);
93extern asmlinkage void qic_enable_irq_interrupt(void);
94extern asmlinkage void qic_call_function_interrupt(void);
95
1#ifdef CONFIG_X86_32 96#ifdef CONFIG_X86_32
2# include "hw_irq_32.h" 97extern void (*const interrupt[NR_IRQS])(void);
3#else 98#else
4# include "hw_irq_64.h" 99typedef int vector_irq_t[NR_VECTORS];
100DECLARE_PER_CPU(vector_irq_t, vector_irq);
101extern spinlock_t vector_lock;
102#endif
103extern void setup_vector_irq(int cpu);
104
105#endif /* !ASSEMBLY_ */
106
5#endif 107#endif
diff --git a/include/asm-x86/hw_irq_32.h b/include/asm-x86/hw_irq_32.h
deleted file mode 100644
index ea88054e03f3..000000000000
--- a/include/asm-x86/hw_irq_32.h
+++ /dev/null
@@ -1,66 +0,0 @@
1#ifndef _ASM_HW_IRQ_H
2#define _ASM_HW_IRQ_H
3
4/*
5 * linux/include/asm/hw_irq.h
6 *
7 * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
8 *
9 * moved some of the old arch/i386/kernel/irq.h to here. VY
10 *
11 * IRQ/IPI changes taken from work by Thomas Radke
12 * <tomsoft@informatik.tu-chemnitz.de>
13 */
14
15#include <linux/profile.h>
16#include <asm/atomic.h>
17#include <asm/irq.h>
18#include <asm/sections.h>
19
20#define NMI_VECTOR 0x02
21
22/*
23 * Various low-level irq details needed by irq.c, process.c,
24 * time.c, io_apic.c and smp.c
25 *
26 * Interrupt entry/exit code at both C and assembly level
27 */
28
29extern void (*const interrupt[NR_IRQS])(void);
30
31#ifdef CONFIG_SMP
32void reschedule_interrupt(void);
33void invalidate_interrupt(void);
34void call_function_interrupt(void);
35#endif
36
37#ifdef CONFIG_X86_LOCAL_APIC
38void apic_timer_interrupt(void);
39void error_interrupt(void);
40void spurious_interrupt(void);
41void thermal_interrupt(void);
42#define platform_legacy_irq(irq) ((irq) < 16)
43#endif
44
45void disable_8259A_irq(unsigned int irq);
46void enable_8259A_irq(unsigned int irq);
47int i8259A_irq_pending(unsigned int irq);
48void make_8259A_irq(unsigned int irq);
49void init_8259A(int aeoi);
50void send_IPI_self(int vector);
51void init_VISWS_APIC_irqs(void);
52void setup_IO_APIC(void);
53void disable_IO_APIC(void);
54void print_IO_APIC(void);
55int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
56void send_IPI(int dest, int vector);
57void setup_ioapic_dest(void);
58
59extern unsigned long io_apic_irqs;
60
61extern atomic_t irq_err_count;
62extern atomic_t irq_mis_count;
63
64#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
65
66#endif /* _ASM_HW_IRQ_H */
diff --git a/include/asm-x86/hw_irq_64.h b/include/asm-x86/hw_irq_64.h
deleted file mode 100644
index 0062ef390f67..000000000000
--- a/include/asm-x86/hw_irq_64.h
+++ /dev/null
@@ -1,173 +0,0 @@
1#ifndef _ASM_HW_IRQ_H
2#define _ASM_HW_IRQ_H
3
4/*
5 * linux/include/asm/hw_irq.h
6 *
7 * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
8 *
9 * moved some of the old arch/i386/kernel/irq.h to here. VY
10 *
11 * IRQ/IPI changes taken from work by Thomas Radke
12 * <tomsoft@informatik.tu-chemnitz.de>
13 *
14 * hacked by Andi Kleen for x86-64.
15 */
16
17#ifndef __ASSEMBLY__
18#include <asm/atomic.h>
19#include <asm/irq.h>
20#include <linux/profile.h>
21#include <linux/smp.h>
22#include <linux/percpu.h>
23#endif
24
25#define NMI_VECTOR 0x02
26/*
27 * IDT vectors usable for external interrupt sources start
28 * at 0x20:
29 */
30#define FIRST_EXTERNAL_VECTOR 0x20
31
32#define IA32_SYSCALL_VECTOR 0x80
33
34
35/* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
36 * cleanup after irq migration.
37 */
38#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
39
40/*
41 * Vectors 0x30-0x3f are used for ISA interrupts.
42 */
43#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
44#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
45#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
46#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
47#define IRQ4_VECTOR (IRQ0_VECTOR + 4)
48#define IRQ5_VECTOR (IRQ0_VECTOR + 5)
49#define IRQ6_VECTOR (IRQ0_VECTOR + 6)
50#define IRQ7_VECTOR (IRQ0_VECTOR + 7)
51#define IRQ8_VECTOR (IRQ0_VECTOR + 8)
52#define IRQ9_VECTOR (IRQ0_VECTOR + 9)
53#define IRQ10_VECTOR (IRQ0_VECTOR + 10)
54#define IRQ11_VECTOR (IRQ0_VECTOR + 11)
55#define IRQ12_VECTOR (IRQ0_VECTOR + 12)
56#define IRQ13_VECTOR (IRQ0_VECTOR + 13)
57#define IRQ14_VECTOR (IRQ0_VECTOR + 14)
58#define IRQ15_VECTOR (IRQ0_VECTOR + 15)
59
60/*
61 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
62 *
63 * some of the following vectors are 'rare', they are merged
64 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
65 * TLB, reschedule and local APIC vectors are performance-critical.
66 */
67#define SPURIOUS_APIC_VECTOR 0xff
68#define ERROR_APIC_VECTOR 0xfe
69#define RESCHEDULE_VECTOR 0xfd
70#define CALL_FUNCTION_VECTOR 0xfc
71/* fb free - please don't readd KDB here because it's useless
72 (hint - think what a NMI bit does to a vector) */
73#define THERMAL_APIC_VECTOR 0xfa
74#define THRESHOLD_APIC_VECTOR 0xf9
75/* f8 free */
76#define INVALIDATE_TLB_VECTOR_END 0xf7
77#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
78
79#define NUM_INVALIDATE_TLB_VECTORS 8
80
81/*
82 * Local APIC timer IRQ vector is on a different priority level,
83 * to work around the 'lost local interrupt if more than 2 IRQ
84 * sources per level' errata.
85 */
86#define LOCAL_TIMER_VECTOR 0xef
87
88/*
89 * First APIC vector available to drivers: (vectors 0x30-0xee)
90 * we start at 0x41 to spread out vectors evenly between priority
91 * levels. (0x80 is the syscall vector)
92 */
93#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
94#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in irq.h */
95
96
97#ifndef __ASSEMBLY__
98
99/* Interrupt handlers registered during init_IRQ */
100void apic_timer_interrupt(void);
101void spurious_interrupt(void);
102void error_interrupt(void);
103void reschedule_interrupt(void);
104void call_function_interrupt(void);
105void irq_move_cleanup_interrupt(void);
106void invalidate_interrupt0(void);
107void invalidate_interrupt1(void);
108void invalidate_interrupt2(void);
109void invalidate_interrupt3(void);
110void invalidate_interrupt4(void);
111void invalidate_interrupt5(void);
112void invalidate_interrupt6(void);
113void invalidate_interrupt7(void);
114void thermal_interrupt(void);
115void threshold_interrupt(void);
116void i8254_timer_resume(void);
117
118typedef int vector_irq_t[NR_VECTORS];
119DECLARE_PER_CPU(vector_irq_t, vector_irq);
120extern void __setup_vector_irq(int cpu);
121extern spinlock_t vector_lock;
122
123/*
124 * Various low-level irq details needed by irq.c, process.c,
125 * time.c, io_apic.c and smp.c
126 *
127 * Interrupt entry/exit code at both C and assembly level
128 */
129
130extern void disable_8259A_irq(unsigned int irq);
131extern void enable_8259A_irq(unsigned int irq);
132extern int i8259A_irq_pending(unsigned int irq);
133extern void make_8259A_irq(unsigned int irq);
134extern void init_8259A(int aeoi);
135extern void send_IPI_self(int vector);
136extern void init_VISWS_APIC_irqs(void);
137extern void setup_IO_APIC(void);
138extern void enable_IO_APIC(void);
139extern void disable_IO_APIC(void);
140extern void print_IO_APIC(void);
141extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
142extern void send_IPI(int dest, int vector);
143extern void setup_ioapic_dest(void);
144extern void native_init_IRQ(void);
145
146extern unsigned long io_apic_irqs;
147
148extern atomic_t irq_err_count;
149extern atomic_t irq_mis_count;
150
151#define IO_APIC_IRQ(x) (((x) >= 16) || ((1<<(x)) & io_apic_irqs))
152
153#include <asm/ptrace.h>
154
155#define IRQ_NAME2(nr) nr##_interrupt(void)
156#define IRQ_NAME(nr) IRQ_NAME2(IRQ##nr)
157
158/*
159 * SMP has a few special interrupts for IPI messages
160 */
161
162#define BUILD_IRQ(nr) \
163 asmlinkage void IRQ_NAME(nr); \
164 asm("\n.p2align\n" \
165 "IRQ" #nr "_interrupt:\n\t" \
166 "push $~(" #nr ") ; " \
167 "jmp common_interrupt");
168
169#define platform_legacy_irq(irq) ((irq) < 16)
170
171#endif
172
173#endif /* _ASM_HW_IRQ_H */
diff --git a/include/asm-x86/i8259.h b/include/asm-x86/i8259.h
index 45d4df3e51e6..2f98df91f1f2 100644
--- a/include/asm-x86/i8259.h
+++ b/include/asm-x86/i8259.h
@@ -55,4 +55,6 @@ static inline void outb_pic(unsigned char value, unsigned int port)
55 udelay(2); 55 udelay(2);
56} 56}
57 57
58extern struct irq_chip i8259A_chip;
59
58#endif /* __ASM_I8259_H__ */ 60#endif /* __ASM_I8259_H__ */
diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h
index d5b11f60dbd0..bf5d629b3a39 100644
--- a/include/asm-x86/io.h
+++ b/include/asm-x86/io.h
@@ -3,6 +3,76 @@
3 3
4#define ARCH_HAS_IOREMAP_WC 4#define ARCH_HAS_IOREMAP_WC
5 5
6#include <linux/compiler.h>
7
8/*
9 * early_ioremap() and early_iounmap() are for temporary early boot-time
10 * mappings, before the real ioremap() is functional.
11 * A boot-time mapping is currently limited to at most 16 pages.
12 */
13#ifndef __ASSEMBLY__
14extern void early_ioremap_init(void);
15extern void early_ioremap_clear(void);
16extern void early_ioremap_reset(void);
17extern void *early_ioremap(unsigned long offset, unsigned long size);
18extern void early_iounmap(void *addr, unsigned long size);
19extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
20#endif
21
22#define build_mmio_read(name, size, type, reg, barrier) \
23static inline type name(const volatile void __iomem *addr) \
24{ type ret; asm volatile("mov" size " %1,%0":"=" reg (ret) \
25:"m" (*(volatile type __force *)addr) barrier); return ret; }
26
27#define build_mmio_write(name, size, type, reg, barrier) \
28static inline void name(type val, volatile void __iomem *addr) \
29{ asm volatile("mov" size " %0,%1": :reg (val), \
30"m" (*(volatile type __force *)addr) barrier); }
31
32build_mmio_read(readb, "b", unsigned char, "q", :"memory")
33build_mmio_read(readw, "w", unsigned short, "r", :"memory")
34build_mmio_read(readl, "l", unsigned int, "r", :"memory")
35
36build_mmio_read(__readb, "b", unsigned char, "q", )
37build_mmio_read(__readw, "w", unsigned short, "r", )
38build_mmio_read(__readl, "l", unsigned int, "r", )
39
40build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
41build_mmio_write(writew, "w", unsigned short, "r", :"memory")
42build_mmio_write(writel, "l", unsigned int, "r", :"memory")
43
44build_mmio_write(__writeb, "b", unsigned char, "q", )
45build_mmio_write(__writew, "w", unsigned short, "r", )
46build_mmio_write(__writel, "l", unsigned int, "r", )
47
48#define readb_relaxed(a) __readb(a)
49#define readw_relaxed(a) __readw(a)
50#define readl_relaxed(a) __readl(a)
51#define __raw_readb __readb
52#define __raw_readw __readw
53#define __raw_readl __readl
54
55#define __raw_writeb __writeb
56#define __raw_writew __writew
57#define __raw_writel __writel
58
59#define mmiowb() barrier()
60
61#ifdef CONFIG_X86_64
62build_mmio_read(readq, "q", unsigned long, "r", :"memory")
63build_mmio_read(__readq, "q", unsigned long, "r", )
64build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
65build_mmio_write(__writeq, "q", unsigned long, "r", )
66
67#define readq_relaxed(a) __readq(a)
68#define __raw_readq __readq
69#define __raw_writeq writeq
70
71/* Let people know we have them */
72#define readq readq
73#define writeq writeq
74#endif
75
6#ifdef CONFIG_X86_32 76#ifdef CONFIG_X86_32
7# include "io_32.h" 77# include "io_32.h"
8#else 78#else
@@ -16,4 +86,17 @@ extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
16 unsigned long prot_val); 86 unsigned long prot_val);
17extern void __iomem *ioremap_wc(unsigned long offset, unsigned long size); 87extern void __iomem *ioremap_wc(unsigned long offset, unsigned long size);
18 88
89/*
90 * early_ioremap() and early_iounmap() are for temporary early boot-time
91 * mappings, before the real ioremap() is functional.
92 * A boot-time mapping is currently limited to at most 16 pages.
93 */
94extern void early_ioremap_init(void);
95extern void early_ioremap_clear(void);
96extern void early_ioremap_reset(void);
97extern void *early_ioremap(unsigned long offset, unsigned long size);
98extern void early_iounmap(void *addr, unsigned long size);
99extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
100
101
19#endif /* _ASM_X86_IO_H */ 102#endif /* _ASM_X86_IO_H */
diff --git a/include/asm-x86/io_32.h b/include/asm-x86/io_32.h
index 049e81e797a0..4df44ed54077 100644
--- a/include/asm-x86/io_32.h
+++ b/include/asm-x86/io_32.h
@@ -122,18 +122,6 @@ static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
122extern void iounmap(volatile void __iomem *addr); 122extern void iounmap(volatile void __iomem *addr);
123 123
124/* 124/*
125 * early_ioremap() and early_iounmap() are for temporary early boot-time
126 * mappings, before the real ioremap() is functional.
127 * A boot-time mapping is currently limited to at most 16 pages.
128 */
129extern void early_ioremap_init(void);
130extern void early_ioremap_clear(void);
131extern void early_ioremap_reset(void);
132extern void *early_ioremap(unsigned long offset, unsigned long size);
133extern void early_iounmap(void *addr, unsigned long size);
134extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
135
136/*
137 * ISA I/O bus memory addresses are 1:1 with the physical address. 125 * ISA I/O bus memory addresses are 1:1 with the physical address.
138 */ 126 */
139#define isa_virt_to_bus virt_to_phys 127#define isa_virt_to_bus virt_to_phys
@@ -149,55 +137,6 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
149#define virt_to_bus virt_to_phys 137#define virt_to_bus virt_to_phys
150#define bus_to_virt phys_to_virt 138#define bus_to_virt phys_to_virt
151 139
152/*
153 * readX/writeX() are used to access memory mapped devices. On some
154 * architectures the memory mapped IO stuff needs to be accessed
155 * differently. On the x86 architecture, we just read/write the
156 * memory location directly.
157 */
158
159static inline unsigned char readb(const volatile void __iomem *addr)
160{
161 return *(volatile unsigned char __force *)addr;
162}
163
164static inline unsigned short readw(const volatile void __iomem *addr)
165{
166 return *(volatile unsigned short __force *)addr;
167}
168
169static inline unsigned int readl(const volatile void __iomem *addr)
170{
171 return *(volatile unsigned int __force *) addr;
172}
173
174#define readb_relaxed(addr) readb(addr)
175#define readw_relaxed(addr) readw(addr)
176#define readl_relaxed(addr) readl(addr)
177#define __raw_readb readb
178#define __raw_readw readw
179#define __raw_readl readl
180
181static inline void writeb(unsigned char b, volatile void __iomem *addr)
182{
183 *(volatile unsigned char __force *)addr = b;
184}
185
186static inline void writew(unsigned short b, volatile void __iomem *addr)
187{
188 *(volatile unsigned short __force *)addr = b;
189}
190
191static inline void writel(unsigned int b, volatile void __iomem *addr)
192{
193 *(volatile unsigned int __force *)addr = b;
194}
195#define __raw_writeb writeb
196#define __raw_writew writew
197#define __raw_writel writel
198
199#define mmiowb()
200
201static inline void 140static inline void
202memset_io(volatile void __iomem *addr, unsigned char val, int count) 141memset_io(volatile void __iomem *addr, unsigned char val, int count)
203{ 142{
diff --git a/include/asm-x86/io_64.h b/include/asm-x86/io_64.h
index 0930bedf9e4d..ddd8058a5026 100644
--- a/include/asm-x86/io_64.h
+++ b/include/asm-x86/io_64.h
@@ -204,77 +204,6 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
204#define virt_to_bus virt_to_phys 204#define virt_to_bus virt_to_phys
205#define bus_to_virt phys_to_virt 205#define bus_to_virt phys_to_virt
206 206
207/*
208 * readX/writeX() are used to access memory mapped devices. On some
209 * architectures the memory mapped IO stuff needs to be accessed
210 * differently. On the x86 architecture, we just read/write the
211 * memory location directly.
212 */
213
214static inline __u8 __readb(const volatile void __iomem *addr)
215{
216 return *(__force volatile __u8 *)addr;
217}
218
219static inline __u16 __readw(const volatile void __iomem *addr)
220{
221 return *(__force volatile __u16 *)addr;
222}
223
224static __always_inline __u32 __readl(const volatile void __iomem *addr)
225{
226 return *(__force volatile __u32 *)addr;
227}
228
229static inline __u64 __readq(const volatile void __iomem *addr)
230{
231 return *(__force volatile __u64 *)addr;
232}
233
234#define readb(x) __readb(x)
235#define readw(x) __readw(x)
236#define readl(x) __readl(x)
237#define readq(x) __readq(x)
238#define readb_relaxed(a) readb(a)
239#define readw_relaxed(a) readw(a)
240#define readl_relaxed(a) readl(a)
241#define readq_relaxed(a) readq(a)
242#define __raw_readb readb
243#define __raw_readw readw
244#define __raw_readl readl
245#define __raw_readq readq
246
247#define mmiowb()
248
249static inline void __writel(__u32 b, volatile void __iomem *addr)
250{
251 *(__force volatile __u32 *)addr = b;
252}
253
254static inline void __writeq(__u64 b, volatile void __iomem *addr)
255{
256 *(__force volatile __u64 *)addr = b;
257}
258
259static inline void __writeb(__u8 b, volatile void __iomem *addr)
260{
261 *(__force volatile __u8 *)addr = b;
262}
263
264static inline void __writew(__u16 b, volatile void __iomem *addr)
265{
266 *(__force volatile __u16 *)addr = b;
267}
268
269#define writeq(val, addr) __writeq((val), (addr))
270#define writel(val, addr) __writel((val), (addr))
271#define writew(val, addr) __writew((val), (addr))
272#define writeb(val, addr) __writeb((val), (addr))
273#define __raw_writeb writeb
274#define __raw_writew writew
275#define __raw_writel writel
276#define __raw_writeq writeq
277
278void __memcpy_fromio(void *, unsigned long, unsigned); 207void __memcpy_fromio(void *, unsigned long, unsigned);
279void __memcpy_toio(unsigned long, const void *, unsigned); 208void __memcpy_toio(unsigned long, const void *, unsigned);
280 209
diff --git a/include/asm-x86/io_apic.h b/include/asm-x86/io_apic.h
index d593e14f0341..14f82bbcb5fd 100644
--- a/include/asm-x86/io_apic.h
+++ b/include/asm-x86/io_apic.h
@@ -11,6 +11,15 @@
11 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar 11 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar
12 */ 12 */
13 13
14/* I/O Unit Redirection Table */
15#define IO_APIC_REDIR_VECTOR_MASK 0x000FF
16#define IO_APIC_REDIR_DEST_LOGICAL 0x00800
17#define IO_APIC_REDIR_DEST_PHYSICAL 0x00000
18#define IO_APIC_REDIR_SEND_PENDING (1 << 12)
19#define IO_APIC_REDIR_REMOTE_IRR (1 << 14)
20#define IO_APIC_REDIR_LEVEL_TRIGGER (1 << 15)
21#define IO_APIC_REDIR_MASKED (1 << 16)
22
14/* 23/*
15 * The structure of the IO-APIC: 24 * The structure of the IO-APIC:
16 */ 25 */
@@ -112,21 +121,32 @@ extern int nr_ioapic_registers[MAX_IO_APICS];
112 121
113#define MP_MAX_IOAPIC_PIN 127 122#define MP_MAX_IOAPIC_PIN 127
114 123
115struct mp_ioapic_routing { 124struct mp_config_ioapic {
116 int apic_id; 125 unsigned long mp_apicaddr;
117 int gsi_base; 126 unsigned int mp_apicid;
118 int gsi_end; 127 unsigned char mp_type;
119 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); 128 unsigned char mp_apicver;
129 unsigned char mp_flags;
130};
131
132struct mp_config_intsrc {
133 unsigned int mp_dstapic;
134 unsigned char mp_type;
135 unsigned char mp_irqtype;
136 unsigned short mp_irqflag;
137 unsigned char mp_srcbus;
138 unsigned char mp_srcbusirq;
139 unsigned char mp_dstirq;
120}; 140};
121 141
122/* I/O APIC entries */ 142/* I/O APIC entries */
123extern struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; 143extern struct mp_config_ioapic mp_ioapics[MAX_IO_APICS];
124 144
125/* # of MP IRQ source entries */ 145/* # of MP IRQ source entries */
126extern int mp_irq_entries; 146extern int mp_irq_entries;
127 147
128/* MP IRQ source entries */ 148/* MP IRQ source entries */
129extern struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES]; 149extern struct mp_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
130 150
131/* non-0 if default (table-less) MP configuration */ 151/* non-0 if default (table-less) MP configuration */
132extern int mpc_default_type; 152extern int mpc_default_type;
@@ -137,6 +157,9 @@ extern int sis_apic_bug;
137/* 1 if "noapic" boot option passed */ 157/* 1 if "noapic" boot option passed */
138extern int skip_ioapic_setup; 158extern int skip_ioapic_setup;
139 159
160/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
161extern int timer_through_8259;
162
140static inline void disable_ioapic_setup(void) 163static inline void disable_ioapic_setup(void)
141{ 164{
142 skip_ioapic_setup = 1; 165 skip_ioapic_setup = 1;
@@ -162,6 +185,8 @@ extern void ioapic_init_mappings(void);
162 185
163#else /* !CONFIG_X86_IO_APIC */ 186#else /* !CONFIG_X86_IO_APIC */
164#define io_apic_assign_pci_irqs 0 187#define io_apic_assign_pci_irqs 0
188static const int timer_through_8259 = 0;
189static inline void ioapic_init_mappings(void) { }
165#endif 190#endif
166 191
167#endif 192#endif
diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h
index 07862fdd23c0..068c9a40aa5b 100644
--- a/include/asm-x86/iommu.h
+++ b/include/asm-x86/iommu.h
@@ -1,29 +1,34 @@
1#ifndef _ASM_X8664_GART_H 1#ifndef _ASM_X8664_IOMMU_H
2#define _ASM_X8664_GART_H 1 2#define _ASM_X8664_IOMMU_H 1
3 3
4extern void pci_iommu_shutdown(void); 4extern void pci_iommu_shutdown(void);
5extern void no_iommu_init(void); 5extern void no_iommu_init(void);
6extern int force_iommu, no_iommu; 6extern int force_iommu, no_iommu;
7extern int iommu_detected; 7extern int iommu_detected;
8#ifdef CONFIG_IOMMU 8
9#ifdef CONFIG_GART_IOMMU
10extern int gart_iommu_aperture;
11extern int gart_iommu_aperture_allowed;
12extern int gart_iommu_aperture_disabled;
13
14extern void early_gart_iommu_check(void);
9extern void gart_iommu_init(void); 15extern void gart_iommu_init(void);
10extern void gart_iommu_shutdown(void); 16extern void gart_iommu_shutdown(void);
11extern void __init gart_parse_options(char *); 17extern void __init gart_parse_options(char *);
12extern void iommu_hole_init(void); 18extern void gart_iommu_hole_init(void);
13extern int fallback_aper_order; 19
14extern int fallback_aper_force;
15extern int iommu_aperture;
16extern int iommu_aperture_allowed;
17extern int iommu_aperture_disabled;
18extern int fix_aperture;
19#else 20#else
20#define iommu_aperture 0 21#define gart_iommu_aperture 0
21#define iommu_aperture_allowed 0 22#define gart_iommu_aperture_allowed 0
23#define gart_iommu_aperture_disabled 1
22 24
23static inline void gart_iommu_shutdown(void) 25static inline void early_gart_iommu_check(void)
24{ 26{
25} 27}
26 28
29static inline void gart_iommu_shutdown(void)
30{
31}
27#endif 32#endif
28 33
29#endif 34#endif
diff --git a/include/asm-x86/ipi.h b/include/asm-x86/ipi.h
index 5f7310aa3efd..bb1c09f7a76c 100644
--- a/include/asm-x86/ipi.h
+++ b/include/asm-x86/ipi.h
@@ -20,6 +20,7 @@
20 20
21#include <asm/hw_irq.h> 21#include <asm/hw_irq.h>
22#include <asm/apic.h> 22#include <asm/apic.h>
23#include <asm/smp.h>
23 24
24/* 25/*
25 * the following functions deal with sending IPIs between CPUs. 26 * the following functions deal with sending IPIs between CPUs.
diff --git a/include/asm-x86/irq.h b/include/asm-x86/irq.h
index 7ba905465a53..1a2925757317 100644
--- a/include/asm-x86/irq.h
+++ b/include/asm-x86/irq.h
@@ -1,5 +1,50 @@
1#ifdef CONFIG_X86_32 1#ifndef _ASM_IRQ_H
2# include "irq_32.h" 2#define _ASM_IRQ_H
3/*
4 * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
5 *
6 * IRQ/IPI changes taken from work by Thomas Radke
7 * <tomsoft@informatik.tu-chemnitz.de>
8 */
9
10#include <asm/apicdef.h>
11#include <asm/irq_vectors.h>
12
13static inline int irq_canonicalize(int irq)
14{
15 return ((irq == 2) ? 9 : irq);
16}
17
18#ifdef CONFIG_X86_LOCAL_APIC
19# define ARCH_HAS_NMI_WATCHDOG
20#endif
21
22#ifdef CONFIG_4KSTACKS
23 extern void irq_ctx_init(int cpu);
24 extern void irq_ctx_exit(int cpu);
25# define __ARCH_HAS_DO_SOFTIRQ
3#else 26#else
4# include "irq_64.h" 27# define irq_ctx_init(cpu) do { } while (0)
28# define irq_ctx_exit(cpu) do { } while (0)
29# ifdef CONFIG_X86_64
30# define __ARCH_HAS_DO_SOFTIRQ
31# endif
32#endif
33
34#ifdef CONFIG_IRQBALANCE
35extern int irqbalance_disable(char *str);
36#endif
37
38#ifdef CONFIG_HOTPLUG_CPU
39#include <linux/cpumask.h>
40extern void fixup_irqs(cpumask_t map);
5#endif 41#endif
42
43extern unsigned int do_IRQ(struct pt_regs *regs);
44extern void init_IRQ(void);
45extern void native_init_IRQ(void);
46
47/* Interrupt vector management */
48extern DECLARE_BITMAP(used_vectors, NR_VECTORS);
49
50#endif /* _ASM_IRQ_H */
diff --git a/include/asm-x86/irq_32.h b/include/asm-x86/irq_32.h
deleted file mode 100644
index 0b79f3185243..000000000000
--- a/include/asm-x86/irq_32.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _ASM_IRQ_H
2#define _ASM_IRQ_H
3
4/*
5 * linux/include/asm/irq.h
6 *
7 * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
8 *
9 * IRQ/IPI changes taken from work by Thomas Radke
10 * <tomsoft@informatik.tu-chemnitz.de>
11 */
12
13#include <linux/sched.h>
14/* include comes from machine specific directory */
15#include "irq_vectors.h"
16#include <asm/thread_info.h>
17
18static inline int irq_canonicalize(int irq)
19{
20 return ((irq == 2) ? 9 : irq);
21}
22
23#ifdef CONFIG_X86_LOCAL_APIC
24# define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */
25#endif
26
27#ifdef CONFIG_4KSTACKS
28 extern void irq_ctx_init(int cpu);
29 extern void irq_ctx_exit(int cpu);
30# define __ARCH_HAS_DO_SOFTIRQ
31#else
32# define irq_ctx_init(cpu) do { } while (0)
33# define irq_ctx_exit(cpu) do { } while (0)
34#endif
35
36#ifdef CONFIG_IRQBALANCE
37extern int irqbalance_disable(char *str);
38#endif
39
40#ifdef CONFIG_HOTPLUG_CPU
41extern void fixup_irqs(cpumask_t map);
42#endif
43
44unsigned int do_IRQ(struct pt_regs *regs);
45void init_IRQ(void);
46void __init native_init_IRQ(void);
47
48/* Interrupt vector management */
49extern DECLARE_BITMAP(used_vectors, NR_VECTORS);
50
51#endif /* _ASM_IRQ_H */
diff --git a/include/asm-x86/irq_64.h b/include/asm-x86/irq_64.h
deleted file mode 100644
index 083d35a62c94..000000000000
--- a/include/asm-x86/irq_64.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef _ASM_IRQ_H
2#define _ASM_IRQ_H
3
4/*
5 * linux/include/asm/irq.h
6 *
7 * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
8 *
9 * IRQ/IPI changes taken from work by Thomas Radke
10 * <tomsoft@informatik.tu-chemnitz.de>
11 */
12
13#define TIMER_IRQ 0
14
15/*
16 * 16 8259A IRQ's, 208 potential APIC interrupt sources.
17 * Right now the APIC is mostly only used for SMP.
18 * 256 vectors is an architectural limit. (we can have
19 * more than 256 devices theoretically, but they will
20 * have to use shared interrupts)
21 * Since vectors 0x00-0x1f are used/reserved for the CPU,
22 * the usable vector space is 0x20-0xff (224 vectors)
23 */
24
25/*
26 * The maximum number of vectors supported by x86_64 processors
27 * is limited to 256. For processors other than x86_64, NR_VECTORS
28 * should be changed accordingly.
29 */
30#define NR_VECTORS 256
31
32#define FIRST_SYSTEM_VECTOR 0xef /* duplicated in hw_irq.h */
33
34#define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
35#define NR_IRQ_VECTORS NR_IRQS
36
37static inline int irq_canonicalize(int irq)
38{
39 return ((irq == 2) ? 9 : irq);
40}
41
42#define ARCH_HAS_NMI_WATCHDOG /* See include/linux/nmi.h */
43
44#ifdef CONFIG_HOTPLUG_CPU
45#include <linux/cpumask.h>
46extern void fixup_irqs(cpumask_t map);
47#endif
48
49#define __ARCH_HAS_DO_SOFTIRQ 1
50
51#endif /* _ASM_IRQ_H */
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
new file mode 100644
index 000000000000..90b1d1f12f08
--- /dev/null
+++ b/include/asm-x86/irq_vectors.h
@@ -0,0 +1,173 @@
1#ifndef _ASM_IRQ_VECTORS_H
2#define _ASM_IRQ_VECTORS_H
3
4#include <linux/threads.h>
5
6#define NMI_VECTOR 0x02
7
8/*
9 * IDT vectors usable for external interrupt sources start
10 * at 0x20:
11 */
12#define FIRST_EXTERNAL_VECTOR 0x20
13
14#ifdef CONFIG_X86_32
15# define SYSCALL_VECTOR 0x80
16#else
17# define IA32_SYSCALL_VECTOR 0x80
18#endif
19
20/*
21 * Reserve the lowest usable priority level 0x20 - 0x2f for triggering
22 * cleanup after irq migration on 64 bit.
23 */
24#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
25
26/*
27 * Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
28 * Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
29 */
30#ifdef CONFIG_X86_32
31#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR)
32#else
33#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
34#endif
35#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
36#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
37#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
38#define IRQ4_VECTOR (IRQ0_VECTOR + 4)
39#define IRQ5_VECTOR (IRQ0_VECTOR + 5)
40#define IRQ6_VECTOR (IRQ0_VECTOR + 6)
41#define IRQ7_VECTOR (IRQ0_VECTOR + 7)
42#define IRQ8_VECTOR (IRQ0_VECTOR + 8)
43#define IRQ9_VECTOR (IRQ0_VECTOR + 9)
44#define IRQ10_VECTOR (IRQ0_VECTOR + 10)
45#define IRQ11_VECTOR (IRQ0_VECTOR + 11)
46#define IRQ12_VECTOR (IRQ0_VECTOR + 12)
47#define IRQ13_VECTOR (IRQ0_VECTOR + 13)
48#define IRQ14_VECTOR (IRQ0_VECTOR + 14)
49#define IRQ15_VECTOR (IRQ0_VECTOR + 15)
50
51/*
52 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
53 *
54 * some of the following vectors are 'rare', they are merged
55 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
56 * TLB, reschedule and local APIC vectors are performance-critical.
57 *
58 * Vectors 0xf0-0xfa are free (reserved for future Linux use).
59 */
60#ifdef CONFIG_X86_32
61
62# define SPURIOUS_APIC_VECTOR 0xff
63# define ERROR_APIC_VECTOR 0xfe
64# define INVALIDATE_TLB_VECTOR 0xfd
65# define RESCHEDULE_VECTOR 0xfc
66# define CALL_FUNCTION_VECTOR 0xfb
67# define CALL_FUNCTION_SINGLE_VECTOR 0xfa
68# define THERMAL_APIC_VECTOR 0xf0
69
70#else
71
72#define SPURIOUS_APIC_VECTOR 0xff
73#define ERROR_APIC_VECTOR 0xfe
74#define RESCHEDULE_VECTOR 0xfd
75#define CALL_FUNCTION_VECTOR 0xfc
76#define CALL_FUNCTION_SINGLE_VECTOR 0xfb
77#define THERMAL_APIC_VECTOR 0xfa
78#define THRESHOLD_APIC_VECTOR 0xf9
79#define INVALIDATE_TLB_VECTOR_END 0xf7
80#define INVALIDATE_TLB_VECTOR_START 0xf0 /* f0-f7 used for TLB flush */
81
82#define NUM_INVALIDATE_TLB_VECTORS 8
83
84#endif
85
86/*
87 * Local APIC timer IRQ vector is on a different priority level,
88 * to work around the 'lost local interrupt if more than 2 IRQ
89 * sources per level' errata.
90 */
91#define LOCAL_TIMER_VECTOR 0xef
92
93/*
94 * First APIC vector available to drivers: (vectors 0x30-0xee) we
95 * start at 0x31(0x41) to spread out vectors evenly between priority
96 * levels. (0x80 is the syscall vector)
97 */
98#ifdef CONFIG_X86_32
99# define FIRST_DEVICE_VECTOR 0x31
100#else
101# define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
102#endif
103
104#define NR_VECTORS 256
105
106#define FPU_IRQ 13
107
108#define FIRST_VM86_IRQ 3
109#define LAST_VM86_IRQ 15
110#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
111
112#if !defined(CONFIG_X86_VOYAGER)
113
114# if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)
115
116# define NR_IRQS 224
117
118# if (224 >= 32 * NR_CPUS)
119# define NR_IRQ_VECTORS NR_IRQS
120# else
121# define NR_IRQ_VECTORS (32 * NR_CPUS)
122# endif
123
124# else /* IO_APIC || PARAVIRT */
125
126# define NR_IRQS 16
127# define NR_IRQ_VECTORS NR_IRQS
128
129# endif
130
131#else /* !VISWS && !VOYAGER */
132
133# define NR_IRQS 224
134# define NR_IRQ_VECTORS NR_IRQS
135
136#endif /* VISWS */
137
138/* Voyager specific defines */
139/* These define the CPIs we use in linux */
140#define VIC_CPI_LEVEL0 0
141#define VIC_CPI_LEVEL1 1
142/* now the fake CPIs */
143#define VIC_TIMER_CPI 2
144#define VIC_INVALIDATE_CPI 3
145#define VIC_RESCHEDULE_CPI 4
146#define VIC_ENABLE_IRQ_CPI 5
147#define VIC_CALL_FUNCTION_CPI 6
148#define VIC_CALL_FUNCTION_SINGLE_CPI 7
149
150/* Now the QIC CPIs: Since we don't need the two initial levels,
151 * these are 2 less than the VIC CPIs */
152#define QIC_CPI_OFFSET 1
153#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET)
154#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
155#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
156#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
157#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
158#define QIC_CALL_FUNCTION_SINGLE_CPI (VIC_CALL_FUNCTION_SINGLE_CPI - QIC_CPI_OFFSET)
159
160#define VIC_START_FAKE_CPI VIC_TIMER_CPI
161#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_SINGLE_CPI
162
163/* this is the SYS_INT CPI. */
164#define VIC_SYS_INT 8
165#define VIC_CMN_INT 15
166
167/* This is the boot CPI for alternate processors. It gets overwritten
168 * by the above once the system has activated all available processors */
169#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0
170#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8)
171
172
173#endif /* _ASM_IRQ_VECTORS_H */
diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h
index c242527f970e..424acb48cd61 100644
--- a/include/asm-x86/irqflags.h
+++ b/include/asm-x86/irqflags.h
@@ -111,14 +111,35 @@ static inline unsigned long __raw_local_irq_save(void)
111#define DISABLE_INTERRUPTS(x) cli 111#define DISABLE_INTERRUPTS(x) cli
112 112
113#ifdef CONFIG_X86_64 113#ifdef CONFIG_X86_64
114#define SWAPGS swapgs
115/*
116 * Currently paravirt can't handle swapgs nicely when we
117 * don't have a stack we can rely on (such as a user space
118 * stack). So we either find a way around these or just fault
119 * and emulate if a guest tries to call swapgs directly.
120 *
121 * Either way, this is a good way to document that we don't
122 * have a reliable stack. x86_64 only.
123 */
124#define SWAPGS_UNSAFE_STACK swapgs
125
126#define PARAVIRT_ADJUST_EXCEPTION_FRAME /* */
127
114#define INTERRUPT_RETURN iretq 128#define INTERRUPT_RETURN iretq
115#define ENABLE_INTERRUPTS_SYSCALL_RET \ 129#define USERGS_SYSRET64 \
116 movq %gs:pda_oldrsp, %rsp; \ 130 swapgs; \
117 swapgs; \ 131 sysretq;
118 sysretq; 132#define USERGS_SYSRET32 \
133 swapgs; \
134 sysretl
135#define ENABLE_INTERRUPTS_SYSEXIT32 \
136 swapgs; \
137 sti; \
138 sysexit
139
119#else 140#else
120#define INTERRUPT_RETURN iret 141#define INTERRUPT_RETURN iret
121#define ENABLE_INTERRUPTS_SYSCALL_RET sti; sysexit 142#define ENABLE_INTERRUPTS_SYSEXIT sti; sysexit
122#define GET_CR0_INTO_EAX movl %cr0, %eax 143#define GET_CR0_INTO_EAX movl %cr0, %eax
123#endif 144#endif
124 145
@@ -169,18 +190,6 @@ static inline void trace_hardirqs_fixup(void)
169#else 190#else
170 191
171#ifdef CONFIG_X86_64 192#ifdef CONFIG_X86_64
172/*
173 * Currently paravirt can't handle swapgs nicely when we
174 * don't have a stack we can rely on (such as a user space
175 * stack). So we either find a way around these or just fault
176 * and emulate if a guest tries to call swapgs directly.
177 *
178 * Either way, this is a good way to document that we don't
179 * have a reliable stack. x86_64 only.
180 */
181#define SWAPGS_UNSAFE_STACK swapgs
182#define ARCH_TRACE_IRQS_ON call trace_hardirqs_on_thunk
183#define ARCH_TRACE_IRQS_OFF call trace_hardirqs_off_thunk
184#define ARCH_LOCKDEP_SYS_EXIT call lockdep_sys_exit_thunk 193#define ARCH_LOCKDEP_SYS_EXIT call lockdep_sys_exit_thunk
185#define ARCH_LOCKDEP_SYS_EXIT_IRQ \ 194#define ARCH_LOCKDEP_SYS_EXIT_IRQ \
186 TRACE_IRQS_ON; \ 195 TRACE_IRQS_ON; \
@@ -192,24 +201,6 @@ static inline void trace_hardirqs_fixup(void)
192 TRACE_IRQS_OFF; 201 TRACE_IRQS_OFF;
193 202
194#else 203#else
195#define ARCH_TRACE_IRQS_ON \
196 pushl %eax; \
197 pushl %ecx; \
198 pushl %edx; \
199 call trace_hardirqs_on; \
200 popl %edx; \
201 popl %ecx; \
202 popl %eax;
203
204#define ARCH_TRACE_IRQS_OFF \
205 pushl %eax; \
206 pushl %ecx; \
207 pushl %edx; \
208 call trace_hardirqs_off; \
209 popl %edx; \
210 popl %ecx; \
211 popl %eax;
212
213#define ARCH_LOCKDEP_SYS_EXIT \ 204#define ARCH_LOCKDEP_SYS_EXIT \
214 pushl %eax; \ 205 pushl %eax; \
215 pushl %ecx; \ 206 pushl %ecx; \
@@ -223,8 +214,8 @@ static inline void trace_hardirqs_fixup(void)
223#endif 214#endif
224 215
225#ifdef CONFIG_TRACE_IRQFLAGS 216#ifdef CONFIG_TRACE_IRQFLAGS
226# define TRACE_IRQS_ON ARCH_TRACE_IRQS_ON 217# define TRACE_IRQS_ON call trace_hardirqs_on_thunk;
227# define TRACE_IRQS_OFF ARCH_TRACE_IRQS_OFF 218# define TRACE_IRQS_OFF call trace_hardirqs_off_thunk;
228#else 219#else
229# define TRACE_IRQS_ON 220# define TRACE_IRQS_ON
230# define TRACE_IRQS_OFF 221# define TRACE_IRQS_OFF
diff --git a/include/asm-x86/kvm_para.h b/include/asm-x86/kvm_para.h
index bfd9900742bf..76f392146daa 100644
--- a/include/asm-x86/kvm_para.h
+++ b/include/asm-x86/kvm_para.h
@@ -71,7 +71,8 @@ static inline long kvm_hypercall0(unsigned int nr)
71 long ret; 71 long ret;
72 asm volatile(KVM_HYPERCALL 72 asm volatile(KVM_HYPERCALL
73 : "=a"(ret) 73 : "=a"(ret)
74 : "a"(nr)); 74 : "a"(nr)
75 : "memory");
75 return ret; 76 return ret;
76} 77}
77 78
@@ -80,7 +81,8 @@ static inline long kvm_hypercall1(unsigned int nr, unsigned long p1)
80 long ret; 81 long ret;
81 asm volatile(KVM_HYPERCALL 82 asm volatile(KVM_HYPERCALL
82 : "=a"(ret) 83 : "=a"(ret)
83 : "a"(nr), "b"(p1)); 84 : "a"(nr), "b"(p1)
85 : "memory");
84 return ret; 86 return ret;
85} 87}
86 88
@@ -90,7 +92,8 @@ static inline long kvm_hypercall2(unsigned int nr, unsigned long p1,
90 long ret; 92 long ret;
91 asm volatile(KVM_HYPERCALL 93 asm volatile(KVM_HYPERCALL
92 : "=a"(ret) 94 : "=a"(ret)
93 : "a"(nr), "b"(p1), "c"(p2)); 95 : "a"(nr), "b"(p1), "c"(p2)
96 : "memory");
94 return ret; 97 return ret;
95} 98}
96 99
@@ -100,7 +103,8 @@ static inline long kvm_hypercall3(unsigned int nr, unsigned long p1,
100 long ret; 103 long ret;
101 asm volatile(KVM_HYPERCALL 104 asm volatile(KVM_HYPERCALL
102 : "=a"(ret) 105 : "=a"(ret)
103 : "a"(nr), "b"(p1), "c"(p2), "d"(p3)); 106 : "a"(nr), "b"(p1), "c"(p2), "d"(p3)
107 : "memory");
104 return ret; 108 return ret;
105} 109}
106 110
@@ -111,7 +115,8 @@ static inline long kvm_hypercall4(unsigned int nr, unsigned long p1,
111 long ret; 115 long ret;
112 asm volatile(KVM_HYPERCALL 116 asm volatile(KVM_HYPERCALL
113 : "=a"(ret) 117 : "=a"(ret)
114 : "a"(nr), "b"(p1), "c"(p2), "d"(p3), "S"(p4)); 118 : "a"(nr), "b"(p1), "c"(p2), "d"(p3), "S"(p4)
119 : "memory");
115 return ret; 120 return ret;
116} 121}
117 122
diff --git a/include/asm-x86/mach-bigsmp/mach_apic.h b/include/asm-x86/mach-bigsmp/mach_apic.h
index 8327907c79bf..017c8c19ad8f 100644
--- a/include/asm-x86/mach-bigsmp/mach_apic.h
+++ b/include/asm-x86/mach-bigsmp/mach_apic.h
@@ -81,7 +81,7 @@ static inline int multi_timer_check(int apic, int irq)
81 81
82static inline int apicid_to_node(int logical_apicid) 82static inline int apicid_to_node(int logical_apicid)
83{ 83{
84 return (0); 84 return apicid_2_node[hard_smp_processor_id()];
85} 85}
86 86
87static inline int cpu_present_to_apicid(int mps_cpu) 87static inline int cpu_present_to_apicid(int mps_cpu)
diff --git a/include/asm-x86/mach-bigsmp/mach_mpspec.h b/include/asm-x86/mach-bigsmp/mach_mpspec.h
deleted file mode 100644
index 6b5dadcf1d0e..000000000000
--- a/include/asm-x86/mach-bigsmp/mach_mpspec.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_MACH_MPSPEC_H
2#define __ASM_MACH_MPSPEC_H
3
4#define MAX_IRQ_SOURCES 256
5
6#define MAX_MP_BUSSES 32
7
8#endif /* __ASM_MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-default/entry_arch.h b/include/asm-x86/mach-default/entry_arch.h
index bc861469bdba..9283b60a1dd2 100644
--- a/include/asm-x86/mach-default/entry_arch.h
+++ b/include/asm-x86/mach-default/entry_arch.h
@@ -13,6 +13,7 @@
13BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR) 13BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
14BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR) 14BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
15BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR) 15BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
16BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
16#endif 17#endif
17 18
18/* 19/*
diff --git a/include/asm-x86/mach-default/irq_vectors.h b/include/asm-x86/mach-default/irq_vectors.h
deleted file mode 100644
index 881c63ca61ad..000000000000
--- a/include/asm-x86/mach-default/irq_vectors.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/*
2 * This file should contain #defines for all of the interrupt vector
3 * numbers used by this architecture.
4 *
5 * In addition, there are some standard defines:
6 *
7 * FIRST_EXTERNAL_VECTOR:
8 * The first free place for external interrupts
9 *
10 * SYSCALL_VECTOR:
11 * The IRQ vector a syscall makes the user to kernel transition
12 * under.
13 *
14 * TIMER_IRQ:
15 * The IRQ number the timer interrupt comes in at.
16 *
17 * NR_IRQS:
18 * The total number of interrupt vectors (including all the
19 * architecture specific interrupts) needed.
20 *
21 */
22#ifndef _ASM_IRQ_VECTORS_H
23#define _ASM_IRQ_VECTORS_H
24
25/*
26 * IDT vectors usable for external interrupt sources start
27 * at 0x20:
28 */
29#define FIRST_EXTERNAL_VECTOR 0x20
30
31#define SYSCALL_VECTOR 0x80
32
33/*
34 * Vectors 0x20-0x2f are used for ISA interrupts.
35 */
36
37/*
38 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
39 *
40 * some of the following vectors are 'rare', they are merged
41 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
42 * TLB, reschedule and local APIC vectors are performance-critical.
43 *
44 * Vectors 0xf0-0xfa are free (reserved for future Linux use).
45 */
46#define SPURIOUS_APIC_VECTOR 0xff
47#define ERROR_APIC_VECTOR 0xfe
48#define INVALIDATE_TLB_VECTOR 0xfd
49#define RESCHEDULE_VECTOR 0xfc
50#define CALL_FUNCTION_VECTOR 0xfb
51
52#define THERMAL_APIC_VECTOR 0xf0
53/*
54 * Local APIC timer IRQ vector is on a different priority level,
55 * to work around the 'lost local interrupt if more than 2 IRQ
56 * sources per level' errata.
57 */
58#define LOCAL_TIMER_VECTOR 0xef
59
60/*
61 * First APIC vector available to drivers: (vectors 0x30-0xee)
62 * we start at 0x31 to spread out vectors evenly between priority
63 * levels. (0x80 is the syscall vector)
64 */
65#define FIRST_DEVICE_VECTOR 0x31
66#define FIRST_SYSTEM_VECTOR 0xef
67
68#define TIMER_IRQ 0
69
70/*
71 * 16 8259A IRQ's, 208 potential APIC interrupt sources.
72 * Right now the APIC is mostly only used for SMP.
73 * 256 vectors is an architectural limit. (we can have
74 * more than 256 devices theoretically, but they will
75 * have to use shared interrupts)
76 * Since vectors 0x00-0x1f are used/reserved for the CPU,
77 * the usable vector space is 0x20-0xff (224 vectors)
78 */
79
80/*
81 * The maximum number of vectors supported by i386 processors
82 * is limited to 256. For processors other than i386, NR_VECTORS
83 * should be changed accordingly.
84 */
85#define NR_VECTORS 256
86
87#include "irq_vectors_limits.h"
88
89#define FPU_IRQ 13
90
91#define FIRST_VM86_IRQ 3
92#define LAST_VM86_IRQ 15
93#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
94
95
96#endif /* _ASM_IRQ_VECTORS_H */
diff --git a/include/asm-x86/mach-default/irq_vectors_limits.h b/include/asm-x86/mach-default/irq_vectors_limits.h
deleted file mode 100644
index a90c7a60109f..000000000000
--- a/include/asm-x86/mach-default/irq_vectors_limits.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef _ASM_IRQ_VECTORS_LIMITS_H
2#define _ASM_IRQ_VECTORS_LIMITS_H
3
4#if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT)
5#define NR_IRQS 224
6# if (224 >= 32 * NR_CPUS)
7# define NR_IRQ_VECTORS NR_IRQS
8# else
9# define NR_IRQ_VECTORS (32 * NR_CPUS)
10# endif
11#else
12#define NR_IRQS 16
13#define NR_IRQ_VECTORS NR_IRQS
14#endif
15
16#endif /* _ASM_IRQ_VECTORS_LIMITS_H */
diff --git a/include/asm-x86/mach-default/mach_apic.h b/include/asm-x86/mach-default/mach_apic.h
index 21003b56ae95..0b2cde5e1b74 100644
--- a/include/asm-x86/mach-default/mach_apic.h
+++ b/include/asm-x86/mach-default/mach_apic.h
@@ -77,7 +77,11 @@ static inline void setup_apic_routing(void)
77 77
78static inline int apicid_to_node(int logical_apicid) 78static inline int apicid_to_node(int logical_apicid)
79{ 79{
80#ifdef CONFIG_SMP
81 return apicid_2_node[hard_smp_processor_id()];
82#else
80 return 0; 83 return 0;
84#endif
81} 85}
82#endif 86#endif
83 87
diff --git a/include/asm-x86/mach-default/setup_arch.h b/include/asm-x86/mach-default/setup_arch.h
index 605e3ccb991b..38846208b548 100644
--- a/include/asm-x86/mach-default/setup_arch.h
+++ b/include/asm-x86/mach-default/setup_arch.h
@@ -1,7 +1,3 @@
1/* Hook to call BIOS initialisation function */ 1/* Hook to call BIOS initialisation function */
2 2
3/* no action for generic */ 3/* no action for generic */
4
5#ifndef ARCH_SETUP
6#define ARCH_SETUP
7#endif
diff --git a/include/asm-x86/mach-default/smpboot_hooks.h b/include/asm-x86/mach-default/smpboot_hooks.h
index 56d0e1fa0258..56d001b9dce4 100644
--- a/include/asm-x86/mach-default/smpboot_hooks.h
+++ b/include/asm-x86/mach-default/smpboot_hooks.h
@@ -3,7 +3,9 @@
3 3
4static inline void smpboot_clear_io_apic_irqs(void) 4static inline void smpboot_clear_io_apic_irqs(void)
5{ 5{
6#ifdef CONFIG_X86_IO_APIC
6 io_apic_irqs = 0; 7 io_apic_irqs = 0;
8#endif
7} 9}
8 10
9static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 11static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
@@ -35,17 +37,23 @@ static inline void smpboot_restore_warm_reset_vector(void)
35 37
36static inline void __init smpboot_setup_io_apic(void) 38static inline void __init smpboot_setup_io_apic(void)
37{ 39{
40#ifdef CONFIG_X86_IO_APIC
38 /* 41 /*
39 * Here we can be sure that there is an IO-APIC in the system. Let's 42 * Here we can be sure that there is an IO-APIC in the system. Let's
40 * go and set it up: 43 * go and set it up:
41 */ 44 */
42 if (!skip_ioapic_setup && nr_ioapics) 45 if (!skip_ioapic_setup && nr_ioapics)
43 setup_IO_APIC(); 46 setup_IO_APIC();
44 else 47 else {
45 nr_ioapics = 0; 48 nr_ioapics = 0;
49 localise_nmi_watchdog();
50 }
51#endif
46} 52}
47 53
48static inline void smpboot_clear_io_apic(void) 54static inline void smpboot_clear_io_apic(void)
49{ 55{
56#ifdef CONFIG_X86_IO_APIC
50 nr_ioapics = 0; 57 nr_ioapics = 0;
58#endif
51} 59}
diff --git a/include/asm-x86/mach-es7000/mach_mpspec.h b/include/asm-x86/mach-es7000/mach_mpspec.h
deleted file mode 100644
index b1f5039d4506..000000000000
--- a/include/asm-x86/mach-es7000/mach_mpspec.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_MACH_MPSPEC_H
2#define __ASM_MACH_MPSPEC_H
3
4#define MAX_IRQ_SOURCES 256
5
6#define MAX_MP_BUSSES 256
7
8#endif /* __ASM_MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-generic/mach_mpparse.h b/include/asm-x86/mach-generic/mach_mpparse.h
index 0d0b5ba2e9d1..586cadbf3787 100644
--- a/include/asm-x86/mach-generic/mach_mpparse.h
+++ b/include/asm-x86/mach-generic/mach_mpparse.h
@@ -1,7 +1,10 @@
1#ifndef _MACH_MPPARSE_H 1#ifndef _MACH_MPPARSE_H
2#define _MACH_MPPARSE_H 1 2#define _MACH_MPPARSE_H 1
3 3
4int mps_oem_check(struct mp_config_table *mpc, char *oem, char *productid); 4
5int acpi_madt_oem_check(char *oem_id, char *oem_table_id); 5extern int mps_oem_check(struct mp_config_table *mpc, char *oem,
6 char *productid);
7
8extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id);
6 9
7#endif 10#endif
diff --git a/include/asm-x86/mach-numaq/mach_apic.h b/include/asm-x86/mach-numaq/mach_apic.h
index 75a56e5afbe7..d802465e026a 100644
--- a/include/asm-x86/mach-numaq/mach_apic.h
+++ b/include/asm-x86/mach-numaq/mach_apic.h
@@ -20,8 +20,14 @@ static inline cpumask_t target_cpus(void)
20#define INT_DELIVERY_MODE dest_LowestPrio 20#define INT_DELIVERY_MODE dest_LowestPrio
21#define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */ 21#define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */
22 22
23#define check_apicid_used(bitmap, apicid) physid_isset(apicid, bitmap) 23static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
24#define check_apicid_present(bit) physid_isset(bit, phys_cpu_present_map) 24{
25 return physid_isset(apicid, bitmap);
26}
27static inline unsigned long check_apicid_present(int bit)
28{
29 return physid_isset(bit, phys_cpu_present_map);
30}
25#define apicid_cluster(apicid) (apicid & 0xF0) 31#define apicid_cluster(apicid) (apicid & 0xF0)
26 32
27static inline int apic_id_registered(void) 33static inline int apic_id_registered(void)
@@ -77,11 +83,6 @@ static inline int cpu_present_to_apicid(int mps_cpu)
77 return BAD_APICID; 83 return BAD_APICID;
78} 84}
79 85
80static inline int generate_logical_apicid(int quad, int phys_apicid)
81{
82 return (quad << 4) + (phys_apicid ? phys_apicid << 1 : 1);
83}
84
85static inline int apicid_to_node(int logical_apicid) 86static inline int apicid_to_node(int logical_apicid)
86{ 87{
87 return logical_apicid >> 4; 88 return logical_apicid >> 4;
@@ -95,30 +96,6 @@ static inline physid_mask_t apicid_to_cpu_present(int logical_apicid)
95 return physid_mask_of_physid(cpu + 4*node); 96 return physid_mask_of_physid(cpu + 4*node);
96} 97}
97 98
98struct mpc_config_translation {
99 unsigned char mpc_type;
100 unsigned char trans_len;
101 unsigned char trans_type;
102 unsigned char trans_quad;
103 unsigned char trans_global;
104 unsigned char trans_local;
105 unsigned short trans_reserved;
106};
107
108static inline int mpc_apic_id(struct mpc_config_processor *m,
109 struct mpc_config_translation *translation_record)
110{
111 int quad = translation_record->trans_quad;
112 int logical_apicid = generate_logical_apicid(quad, m->mpc_apicid);
113
114 printk("Processor #%d %u:%u APIC version %d (quad %d, apic %d)\n",
115 m->mpc_apicid,
116 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
117 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
118 m->mpc_apicver, quad, logical_apicid);
119 return logical_apicid;
120}
121
122extern void *xquad_portio; 99extern void *xquad_portio;
123 100
124static inline void setup_portio_remap(void) 101static inline void setup_portio_remap(void)
diff --git a/include/asm-x86/mach-numaq/mach_mpparse.h b/include/asm-x86/mach-numaq/mach_mpparse.h
index 459b12401187..626aef6b155f 100644
--- a/include/asm-x86/mach-numaq/mach_mpparse.h
+++ b/include/asm-x86/mach-numaq/mach_mpparse.h
@@ -1,14 +1,7 @@
1#ifndef __ASM_MACH_MPPARSE_H 1#ifndef __ASM_MACH_MPPARSE_H
2#define __ASM_MACH_MPPARSE_H 2#define __ASM_MACH_MPPARSE_H
3 3
4extern void mpc_oem_bus_info(struct mpc_config_bus *m, char *name, 4extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
5 struct mpc_config_translation *translation); 5 char *productid);
6extern void mpc_oem_pci_bus(struct mpc_config_bus *m,
7 struct mpc_config_translation *translation);
8
9/* Hook from generic ACPI tables.c */
10static inline void acpi_madt_oem_check(char *oem_id, char *oem_table_id)
11{
12}
13 6
14#endif /* __ASM_MACH_MPPARSE_H */ 7#endif /* __ASM_MACH_MPPARSE_H */
diff --git a/include/asm-x86/mach-numaq/mach_mpspec.h b/include/asm-x86/mach-numaq/mach_mpspec.h
deleted file mode 100644
index dffb09856f8f..000000000000
--- a/include/asm-x86/mach-numaq/mach_mpspec.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_MACH_MPSPEC_H
2#define __ASM_MACH_MPSPEC_H
3
4#define MAX_IRQ_SOURCES 512
5
6#define MAX_MP_BUSSES 32
7
8#endif /* __ASM_MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-summit/mach_mpspec.h b/include/asm-x86/mach-summit/mach_mpspec.h
deleted file mode 100644
index bd765523511a..000000000000
--- a/include/asm-x86/mach-summit/mach_mpspec.h
+++ /dev/null
@@ -1,9 +0,0 @@
1#ifndef __ASM_MACH_MPSPEC_H
2#define __ASM_MACH_MPSPEC_H
3
4#define MAX_IRQ_SOURCES 256
5
6/* Maximum 256 PCI busses, plus 1 ISA bus in each of 4 cabinets. */
7#define MAX_MP_BUSSES 260
8
9#endif /* __ASM_MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-visws/entry_arch.h b/include/asm-x86/mach-visws/entry_arch.h
index b183fa6d83d9..86be554342d4 100644
--- a/include/asm-x86/mach-visws/entry_arch.h
+++ b/include/asm-x86/mach-visws/entry_arch.h
@@ -1,23 +1,5 @@
1/* 1/*
2 * The following vectors are part of the Linux architecture, there 2 * VISWS uses the standard Linux entry points:
3 * is no hardware IRQ pin equivalent for them, they are triggered
4 * through the ICC by us (IPIs)
5 */ 3 */
6#ifdef CONFIG_X86_SMP
7BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
8BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
9BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
10#endif
11 4
12/* 5#include "../mach-default/entry_arch.h"
13 * every pentium local APIC has two 'local interrupts', with a
14 * soft-definable vector attached to both interrupts, one of
15 * which is a timer interrupt, the other one is error counter
16 * overflow. Linux uses the local APIC timer interrupt to get
17 * a much simpler SMP time architecture:
18 */
19#ifdef CONFIG_X86_LOCAL_APIC
20BUILD_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
21BUILD_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
22BUILD_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
23#endif
diff --git a/include/asm-x86/mach-visws/irq_vectors.h b/include/asm-x86/mach-visws/irq_vectors.h
deleted file mode 100644
index cb572d8db505..000000000000
--- a/include/asm-x86/mach-visws/irq_vectors.h
+++ /dev/null
@@ -1,62 +0,0 @@
1#ifndef _ASM_IRQ_VECTORS_H
2#define _ASM_IRQ_VECTORS_H
3
4/*
5 * IDT vectors usable for external interrupt sources start
6 * at 0x20:
7 */
8#define FIRST_EXTERNAL_VECTOR 0x20
9
10#define SYSCALL_VECTOR 0x80
11
12/*
13 * Vectors 0x20-0x2f are used for ISA interrupts.
14 */
15
16/*
17 * Special IRQ vectors used by the SMP architecture, 0xf0-0xff
18 *
19 * some of the following vectors are 'rare', they are merged
20 * into a single vector (CALL_FUNCTION_VECTOR) to save vector space.
21 * TLB, reschedule and local APIC vectors are performance-critical.
22 *
23 * Vectors 0xf0-0xfa are free (reserved for future Linux use).
24 */
25#define SPURIOUS_APIC_VECTOR 0xff
26#define ERROR_APIC_VECTOR 0xfe
27#define INVALIDATE_TLB_VECTOR 0xfd
28#define RESCHEDULE_VECTOR 0xfc
29#define CALL_FUNCTION_VECTOR 0xfb
30
31#define THERMAL_APIC_VECTOR 0xf0
32/*
33 * Local APIC timer IRQ vector is on a different priority level,
34 * to work around the 'lost local interrupt if more than 2 IRQ
35 * sources per level' errata.
36 */
37#define LOCAL_TIMER_VECTOR 0xef
38
39/*
40 * First APIC vector available to drivers: (vectors 0x30-0xee)
41 * we start at 0x31 to spread out vectors evenly between priority
42 * levels. (0x80 is the syscall vector)
43 */
44#define FIRST_DEVICE_VECTOR 0x31
45#define FIRST_SYSTEM_VECTOR 0xef
46
47#define TIMER_IRQ 0
48
49/*
50 * IRQ definitions
51 */
52#define NR_VECTORS 256
53#define NR_IRQS 224
54#define NR_IRQ_VECTORS NR_IRQS
55
56#define FPU_IRQ 13
57
58#define FIRST_VM86_IRQ 3
59#define LAST_VM86_IRQ 15
60#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
61
62#endif /* _ASM_IRQ_VECTORS_H */
diff --git a/include/asm-x86/mach-visws/mach_apic.h b/include/asm-x86/mach-visws/mach_apic.h
index a9ef33a8a995..6943e7a1d0e6 100644
--- a/include/asm-x86/mach-visws/mach_apic.h
+++ b/include/asm-x86/mach-visws/mach_apic.h
@@ -1,103 +1 @@
1#ifndef __ASM_MACH_APIC_H #include "../mach-default/mach_apic.h"
2#define __ASM_MACH_APIC_H
3
4#include <mach_apicdef.h>
5#include <asm/smp.h>
6
7#define APIC_DFR_VALUE (APIC_DFR_FLAT)
8
9#define no_balance_irq (0)
10#define esr_disable (0)
11
12#define INT_DELIVERY_MODE dest_LowestPrio
13#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
14
15#ifdef CONFIG_SMP
16 #define TARGET_CPUS cpu_online_map
17#else
18 #define TARGET_CPUS cpumask_of_cpu(0)
19#endif
20
21#define check_apicid_used(bitmap, apicid) physid_isset(apicid, bitmap)
22#define check_apicid_present(bit) physid_isset(bit, phys_cpu_present_map)
23
24static inline int apic_id_registered(void)
25{
26 return physid_isset(GET_APIC_ID(read_apic_id()), phys_cpu_present_map);
27}
28
29/*
30 * Set up the logical destination ID.
31 *
32 * Intel recommends to set DFR, LDR and TPR before enabling
33 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
34 * document number 292116). So here it goes...
35 */
36static inline void init_apic_ldr(void)
37{
38 unsigned long val;
39
40 apic_write_around(APIC_DFR, APIC_DFR_VALUE);
41 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
42 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
43 apic_write_around(APIC_LDR, val);
44}
45
46static inline void summit_check(char *oem, char *productid)
47{
48}
49
50static inline void setup_apic_routing(void)
51{
52}
53
54static inline int apicid_to_node(int logical_apicid)
55{
56 return 0;
57}
58
59/* Mapping from cpu number to logical apicid */
60static inline int cpu_to_logical_apicid(int cpu)
61{
62 return 1 << cpu;
63}
64
65static inline int cpu_present_to_apicid(int mps_cpu)
66{
67 if (mps_cpu < get_physical_broadcast())
68 return mps_cpu;
69 else
70 return BAD_APICID;
71}
72
73static inline physid_mask_t apicid_to_cpu_present(int apicid)
74{
75 return physid_mask_of_physid(apicid);
76}
77
78#define WAKE_SECONDARY_VIA_INIT
79
80static inline void setup_portio_remap(void)
81{
82}
83
84static inline void enable_apic_mode(void)
85{
86}
87
88static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
89{
90 return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map);
91}
92
93static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
94{
95 return cpus_addr(cpumask)[0];
96}
97
98static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
99{
100 return cpuid_apic >> index_msb;
101}
102
103#endif /* __ASM_MACH_APIC_H */
diff --git a/include/asm-x86/mach-visws/mach_apicdef.h b/include/asm-x86/mach-visws/mach_apicdef.h
index 826cfa97d778..42711d152a93 100644
--- a/include/asm-x86/mach-visws/mach_apicdef.h
+++ b/include/asm-x86/mach-visws/mach_apicdef.h
@@ -1,12 +1 @@
1#ifndef __ASM_MACH_APICDEF_H #include "../mach-default/mach_apicdef.h"
2#define __ASM_MACH_APICDEF_H
3
4#define APIC_ID_MASK (0xF<<24)
5
6static inline unsigned get_apic_id(unsigned long x)
7{
8 return (((x)>>24)&0xF);
9}
10#define GET_APIC_ID(x) get_apic_id(x)
11
12#endif
diff --git a/include/asm-x86/mach-visws/setup_arch.h b/include/asm-x86/mach-visws/setup_arch.h
index 33f700ef6831..fa4766ca2d10 100644
--- a/include/asm-x86/mach-visws/setup_arch.h
+++ b/include/asm-x86/mach-visws/setup_arch.h
@@ -1,8 +1 @@
1/* Hook to call BIOS initialisation function */ #include "../mach-default/setup_arch.h"
2
3extern unsigned long sgivwfb_mem_phys;
4extern unsigned long sgivwfb_mem_size;
5
6/* no action for visws */
7
8#define ARCH_SETUP
diff --git a/include/asm-x86/mach-visws/smpboot_hooks.h b/include/asm-x86/mach-visws/smpboot_hooks.h
index c9b83e395a2e..e4433ca88715 100644
--- a/include/asm-x86/mach-visws/smpboot_hooks.h
+++ b/include/asm-x86/mach-visws/smpboot_hooks.h
@@ -1,28 +1 @@
1static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) #include "../mach-default/smpboot_hooks.h"
2{
3 CMOS_WRITE(0xa, 0xf);
4 local_flush_tlb();
5 Dprintk("1.\n");
6 *((volatile unsigned short *) TRAMPOLINE_HIGH) = start_eip >> 4;
7 Dprintk("2.\n");
8 *((volatile unsigned short *) TRAMPOLINE_LOW) = start_eip & 0xf;
9 Dprintk("3.\n");
10}
11
12/* for visws do nothing for any of these */
13
14static inline void smpboot_clear_io_apic_irqs(void)
15{
16}
17
18static inline void smpboot_restore_warm_reset_vector(void)
19{
20}
21
22static inline void smpboot_setup_io_apic(void)
23{
24}
25
26static inline void smpboot_clear_io_apic(void)
27{
28}
diff --git a/include/asm-x86/mach-voyager/entry_arch.h b/include/asm-x86/mach-voyager/entry_arch.h
index 4a1e1e8c10b6..ae52624b5937 100644
--- a/include/asm-x86/mach-voyager/entry_arch.h
+++ b/include/asm-x86/mach-voyager/entry_arch.h
@@ -23,4 +23,4 @@ BUILD_INTERRUPT(qic_invalidate_interrupt, QIC_INVALIDATE_CPI);
23BUILD_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI); 23BUILD_INTERRUPT(qic_reschedule_interrupt, QIC_RESCHEDULE_CPI);
24BUILD_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI); 24BUILD_INTERRUPT(qic_enable_irq_interrupt, QIC_ENABLE_IRQ_CPI);
25BUILD_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI); 25BUILD_INTERRUPT(qic_call_function_interrupt, QIC_CALL_FUNCTION_CPI);
26 26BUILD_INTERRUPT(qic_call_function_single_interrupt, QIC_CALL_FUNCTION_SINGLE_CPI);
diff --git a/include/asm-x86/mach-voyager/irq_vectors.h b/include/asm-x86/mach-voyager/irq_vectors.h
deleted file mode 100644
index 165421f5821c..000000000000
--- a/include/asm-x86/mach-voyager/irq_vectors.h
+++ /dev/null
@@ -1,79 +0,0 @@
1/* -*- mode: c; c-basic-offset: 8 -*- */
2
3/* Copyright (C) 2002
4 *
5 * Author: James.Bottomley@HansenPartnership.com
6 *
7 * linux/arch/i386/voyager/irq_vectors.h
8 *
9 * This file provides definitions for the VIC and QIC CPIs
10 */
11
12#ifndef _ASM_IRQ_VECTORS_H
13#define _ASM_IRQ_VECTORS_H
14
15/*
16 * IDT vectors usable for external interrupt sources start
17 * at 0x20:
18 */
19#define FIRST_EXTERNAL_VECTOR 0x20
20
21#define SYSCALL_VECTOR 0x80
22
23/*
24 * Vectors 0x20-0x2f are used for ISA interrupts.
25 */
26
27/* These define the CPIs we use in linux */
28#define VIC_CPI_LEVEL0 0
29#define VIC_CPI_LEVEL1 1
30/* now the fake CPIs */
31#define VIC_TIMER_CPI 2
32#define VIC_INVALIDATE_CPI 3
33#define VIC_RESCHEDULE_CPI 4
34#define VIC_ENABLE_IRQ_CPI 5
35#define VIC_CALL_FUNCTION_CPI 6
36
37/* Now the QIC CPIs: Since we don't need the two initial levels,
38 * these are 2 less than the VIC CPIs */
39#define QIC_CPI_OFFSET 1
40#define QIC_TIMER_CPI (VIC_TIMER_CPI - QIC_CPI_OFFSET)
41#define QIC_INVALIDATE_CPI (VIC_INVALIDATE_CPI - QIC_CPI_OFFSET)
42#define QIC_RESCHEDULE_CPI (VIC_RESCHEDULE_CPI - QIC_CPI_OFFSET)
43#define QIC_ENABLE_IRQ_CPI (VIC_ENABLE_IRQ_CPI - QIC_CPI_OFFSET)
44#define QIC_CALL_FUNCTION_CPI (VIC_CALL_FUNCTION_CPI - QIC_CPI_OFFSET)
45
46#define VIC_START_FAKE_CPI VIC_TIMER_CPI
47#define VIC_END_FAKE_CPI VIC_CALL_FUNCTION_CPI
48
49/* this is the SYS_INT CPI. */
50#define VIC_SYS_INT 8
51#define VIC_CMN_INT 15
52
53/* This is the boot CPI for alternate processors. It gets overwritten
54 * by the above once the system has activated all available processors */
55#define VIC_CPU_BOOT_CPI VIC_CPI_LEVEL0
56#define VIC_CPU_BOOT_ERRATA_CPI (VIC_CPI_LEVEL0 + 8)
57
58#define NR_VECTORS 256
59#define NR_IRQS 224
60#define NR_IRQ_VECTORS NR_IRQS
61
62#define FPU_IRQ 13
63
64#define FIRST_VM86_IRQ 3
65#define LAST_VM86_IRQ 15
66#define invalid_vm86_irq(irq) ((irq) < 3 || (irq) > 15)
67
68#ifndef __ASSEMBLY__
69extern asmlinkage void vic_cpi_interrupt(void);
70extern asmlinkage void vic_sys_interrupt(void);
71extern asmlinkage void vic_cmn_interrupt(void);
72extern asmlinkage void qic_timer_interrupt(void);
73extern asmlinkage void qic_invalidate_interrupt(void);
74extern asmlinkage void qic_reschedule_interrupt(void);
75extern asmlinkage void qic_enable_irq_interrupt(void);
76extern asmlinkage void qic_call_function_interrupt(void);
77#endif /* !__ASSEMBLY__ */
78
79#endif /* _ASM_IRQ_VECTORS_H */
diff --git a/include/asm-x86/mmconfig.h b/include/asm-x86/mmconfig.h
new file mode 100644
index 000000000000..95beda07c6fa
--- /dev/null
+++ b/include/asm-x86/mmconfig.h
@@ -0,0 +1,12 @@
1#ifndef _ASM_MMCONFIG_H
2#define _ASM_MMCONFIG_H
3
4#ifdef CONFIG_PCI_MMCONFIG
5extern void __cpuinit fam10h_check_enable_mmcfg(void);
6extern void __init check_enable_amd_mmconf_dmi(void);
7#else
8static inline void fam10h_check_enable_mmcfg(void) { }
9static inline void check_enable_amd_mmconf_dmi(void) { }
10#endif
11
12#endif
diff --git a/include/asm-x86/mmu_context.h b/include/asm-x86/mmu_context.h
index 6598450da6c6..fac57014e7c6 100644
--- a/include/asm-x86/mmu_context.h
+++ b/include/asm-x86/mmu_context.h
@@ -1,5 +1,37 @@
1#ifndef __ASM_X86_MMU_CONTEXT_H
2#define __ASM_X86_MMU_CONTEXT_H
3
4#include <asm/desc.h>
5#include <asm/atomic.h>
6#include <asm/pgalloc.h>
7#include <asm/tlbflush.h>
8#include <asm/paravirt.h>
9#ifndef CONFIG_PARAVIRT
10#include <asm-generic/mm_hooks.h>
11
12static inline void paravirt_activate_mm(struct mm_struct *prev,
13 struct mm_struct *next)
14{
15}
16#endif /* !CONFIG_PARAVIRT */
17
18/*
19 * Used for LDT copy/destruction.
20 */
21int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
22void destroy_context(struct mm_struct *mm);
23
1#ifdef CONFIG_X86_32 24#ifdef CONFIG_X86_32
2# include "mmu_context_32.h" 25# include "mmu_context_32.h"
3#else 26#else
4# include "mmu_context_64.h" 27# include "mmu_context_64.h"
5#endif 28#endif
29
30#define activate_mm(prev, next) \
31do { \
32 paravirt_activate_mm((prev), (next)); \
33 switch_mm((prev), (next), NULL); \
34} while (0);
35
36
37#endif /* __ASM_X86_MMU_CONTEXT_H */
diff --git a/include/asm-x86/mmu_context_32.h b/include/asm-x86/mmu_context_32.h
index 9756ae0f1dd3..824fc575c6d8 100644
--- a/include/asm-x86/mmu_context_32.h
+++ b/include/asm-x86/mmu_context_32.h
@@ -1,28 +1,6 @@
1#ifndef __I386_SCHED_H 1#ifndef __I386_SCHED_H
2#define __I386_SCHED_H 2#define __I386_SCHED_H
3 3
4#include <asm/desc.h>
5#include <asm/atomic.h>
6#include <asm/pgalloc.h>
7#include <asm/tlbflush.h>
8#include <asm/paravirt.h>
9#ifndef CONFIG_PARAVIRT
10#include <asm-generic/mm_hooks.h>
11
12static inline void paravirt_activate_mm(struct mm_struct *prev,
13 struct mm_struct *next)
14{
15}
16#endif /* !CONFIG_PARAVIRT */
17
18
19/*
20 * Used for LDT copy/destruction.
21 */
22int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
23void destroy_context(struct mm_struct *mm);
24
25
26static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 4static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
27{ 5{
28#ifdef CONFIG_SMP 6#ifdef CONFIG_SMP
@@ -75,10 +53,4 @@ static inline void switch_mm(struct mm_struct *prev,
75#define deactivate_mm(tsk, mm) \ 53#define deactivate_mm(tsk, mm) \
76 asm("movl %0,%%gs": :"r" (0)); 54 asm("movl %0,%%gs": :"r" (0));
77 55
78#define activate_mm(prev, next) \
79do { \
80 paravirt_activate_mm((prev), (next)); \
81 switch_mm((prev), (next), NULL); \
82} while (0);
83
84#endif 56#endif
diff --git a/include/asm-x86/mmu_context_64.h b/include/asm-x86/mmu_context_64.h
index ca44c71e7fb3..c7000634ccae 100644
--- a/include/asm-x86/mmu_context_64.h
+++ b/include/asm-x86/mmu_context_64.h
@@ -1,21 +1,7 @@
1#ifndef __X86_64_MMU_CONTEXT_H 1#ifndef __X86_64_MMU_CONTEXT_H
2#define __X86_64_MMU_CONTEXT_H 2#define __X86_64_MMU_CONTEXT_H
3 3
4#include <asm/desc.h>
5#include <asm/atomic.h>
6#include <asm/pgalloc.h>
7#include <asm/pda.h> 4#include <asm/pda.h>
8#include <asm/pgtable.h>
9#include <asm/tlbflush.h>
10#ifndef CONFIG_PARAVIRT
11#include <asm-generic/mm_hooks.h>
12#endif
13
14/*
15 * possibly do the LDT unload here?
16 */
17int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
18void destroy_context(struct mm_struct *mm);
19 5
20static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) 6static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
21{ 7{
@@ -65,8 +51,4 @@ do { \
65 asm volatile("movl %0,%%fs"::"r"(0)); \ 51 asm volatile("movl %0,%%fs"::"r"(0)); \
66} while (0) 52} while (0)
67 53
68#define activate_mm(prev, next) \
69 switch_mm((prev), (next), NULL)
70
71
72#endif 54#endif
diff --git a/include/asm-x86/mmzone_32.h b/include/asm-x86/mmzone_32.h
index cb2cad0b65a7..b2298a227567 100644
--- a/include/asm-x86/mmzone_32.h
+++ b/include/asm-x86/mmzone_32.h
@@ -12,11 +12,9 @@
12extern struct pglist_data *node_data[]; 12extern struct pglist_data *node_data[];
13#define NODE_DATA(nid) (node_data[nid]) 13#define NODE_DATA(nid) (node_data[nid])
14 14
15#ifdef CONFIG_X86_NUMAQ 15#include <asm/numaq.h>
16 #include <asm/numaq.h> 16/* summit or generic arch */
17#elif defined(CONFIG_ACPI_SRAT)/* summit or generic arch */ 17#include <asm/srat.h>
18 #include <asm/srat.h>
19#endif
20 18
21extern int get_memcfg_numa_flat(void); 19extern int get_memcfg_numa_flat(void);
22/* 20/*
@@ -26,28 +24,20 @@ extern int get_memcfg_numa_flat(void);
26 */ 24 */
27static inline void get_memcfg_numa(void) 25static inline void get_memcfg_numa(void)
28{ 26{
29#ifdef CONFIG_X86_NUMAQ 27
30 if (get_memcfg_numaq()) 28 if (get_memcfg_numaq())
31 return; 29 return;
32#elif defined(CONFIG_ACPI_SRAT)
33 if (get_memcfg_from_srat()) 30 if (get_memcfg_from_srat())
34 return; 31 return;
35#endif
36
37 get_memcfg_numa_flat(); 32 get_memcfg_numa_flat();
38} 33}
39 34
40extern int early_pfn_to_nid(unsigned long pfn); 35extern int early_pfn_to_nid(unsigned long pfn);
41extern void numa_kva_reserve(void);
42 36
43#else /* !CONFIG_NUMA */ 37#else /* !CONFIG_NUMA */
44 38
45#define get_memcfg_numa get_memcfg_numa_flat 39#define get_memcfg_numa get_memcfg_numa_flat
46#define get_zholes_size(n) (0)
47 40
48static inline void numa_kva_reserve(void)
49{
50}
51#endif /* CONFIG_NUMA */ 41#endif /* CONFIG_NUMA */
52 42
53#ifdef CONFIG_DISCONTIGMEM 43#ifdef CONFIG_DISCONTIGMEM
@@ -55,14 +45,14 @@ static inline void numa_kva_reserve(void)
55/* 45/*
56 * generic node memory support, the following assumptions apply: 46 * generic node memory support, the following assumptions apply:
57 * 47 *
58 * 1) memory comes in 256Mb contigious chunks which are either present or not 48 * 1) memory comes in 64Mb contigious chunks which are either present or not
59 * 2) we will not have more than 64Gb in total 49 * 2) we will not have more than 64Gb in total
60 * 50 *
61 * for now assume that 64Gb is max amount of RAM for whole system 51 * for now assume that 64Gb is max amount of RAM for whole system
62 * 64Gb / 4096bytes/page = 16777216 pages 52 * 64Gb / 4096bytes/page = 16777216 pages
63 */ 53 */
64#define MAX_NR_PAGES 16777216 54#define MAX_NR_PAGES 16777216
65#define MAX_ELEMENTS 256 55#define MAX_ELEMENTS 1024
66#define PAGES_PER_ELEMENT (MAX_NR_PAGES/MAX_ELEMENTS) 56#define PAGES_PER_ELEMENT (MAX_NR_PAGES/MAX_ELEMENTS)
67 57
68extern s8 physnode_map[]; 58extern s8 physnode_map[];
@@ -87,9 +77,6 @@ static inline int pfn_to_nid(unsigned long pfn)
87 __pgdat->node_start_pfn + __pgdat->node_spanned_pages; \ 77 __pgdat->node_start_pfn + __pgdat->node_spanned_pages; \
88}) 78})
89 79
90#ifdef CONFIG_X86_NUMAQ /* we have contiguous memory on NUMA-Q */
91#define pfn_valid(pfn) ((pfn) < num_physpages)
92#else
93static inline int pfn_valid(int pfn) 80static inline int pfn_valid(int pfn)
94{ 81{
95 int nid = pfn_to_nid(pfn); 82 int nid = pfn_to_nid(pfn);
@@ -98,7 +85,6 @@ static inline int pfn_valid(int pfn)
98 return (pfn < node_end_pfn(nid)); 85 return (pfn < node_end_pfn(nid));
99 return 0; 86 return 0;
100} 87}
101#endif /* CONFIG_X86_NUMAQ */
102 88
103#endif /* CONFIG_DISCONTIGMEM */ 89#endif /* CONFIG_DISCONTIGMEM */
104 90
diff --git a/include/asm-x86/mpspec.h b/include/asm-x86/mpspec.h
index 57a991b9c053..b6995e567fcc 100644
--- a/include/asm-x86/mpspec.h
+++ b/include/asm-x86/mpspec.h
@@ -13,6 +13,12 @@ extern int apic_version[MAX_APICS];
13extern u8 apicid_2_node[]; 13extern u8 apicid_2_node[];
14extern int pic_mode; 14extern int pic_mode;
15 15
16#ifdef CONFIG_X86_NUMAQ
17extern int mp_bus_id_to_node[MAX_MP_BUSSES];
18extern int mp_bus_id_to_local[MAX_MP_BUSSES];
19extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
20#endif
21
16#define MAX_APICID 256 22#define MAX_APICID 256
17 23
18#else 24#else
@@ -21,26 +27,30 @@ extern int pic_mode;
21/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ 27/* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */
22#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) 28#define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4)
23 29
30#endif
31
24extern void early_find_smp_config(void); 32extern void early_find_smp_config(void);
25extern void early_get_smp_config(void); 33extern void early_get_smp_config(void);
26 34
27#endif
28
29#if defined(CONFIG_MCA) || defined(CONFIG_EISA) 35#if defined(CONFIG_MCA) || defined(CONFIG_EISA)
30extern int mp_bus_id_to_type[MAX_MP_BUSSES]; 36extern int mp_bus_id_to_type[MAX_MP_BUSSES];
31#endif 37#endif
32 38
33extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 39extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
34 40
35extern int mp_bus_id_to_pci_bus[MAX_MP_BUSSES];
36
37extern unsigned int boot_cpu_physical_apicid; 41extern unsigned int boot_cpu_physical_apicid;
42extern unsigned int max_physical_apicid;
38extern int smp_found_config; 43extern int smp_found_config;
39extern int mpc_default_type; 44extern int mpc_default_type;
40extern unsigned long mp_lapic_addr; 45extern unsigned long mp_lapic_addr;
41 46
42extern void find_smp_config(void); 47extern void find_smp_config(void);
43extern void get_smp_config(void); 48extern void get_smp_config(void);
49#ifdef CONFIG_X86_MPPARSE
50extern void early_reserve_e820_mpc_new(void);
51#else
52static inline void early_reserve_e820_mpc_new(void) { }
53#endif
44 54
45void __cpuinit generic_processor_info(int apicid, int version); 55void __cpuinit generic_processor_info(int apicid, int version);
46#ifdef CONFIG_ACPI 56#ifdef CONFIG_ACPI
@@ -49,6 +59,17 @@ extern void mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger,
49 u32 gsi); 59 u32 gsi);
50extern void mp_config_acpi_legacy_irqs(void); 60extern void mp_config_acpi_legacy_irqs(void);
51extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low); 61extern int mp_register_gsi(u32 gsi, int edge_level, int active_high_low);
62#ifdef CONFIG_X86_IO_APIC
63extern int mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
64 u32 gsi, int triggering, int polarity);
65#else
66static inline int
67mp_config_acpi_gsi(unsigned char number, unsigned int devfn, u8 pin,
68 u32 gsi, int triggering, int polarity)
69{
70 return 0;
71}
72#endif
52#endif /* CONFIG_ACPI */ 73#endif /* CONFIG_ACPI */
53 74
54#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) 75#define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS)
@@ -101,6 +122,7 @@ typedef struct physid_mask physid_mask_t;
101 __physid_mask; \ 122 __physid_mask; \
102 }) 123 })
103 124
125/* Note: will create very large stack frames if physid_mask_t is big */
104#define physid_mask_of_physid(physid) \ 126#define physid_mask_of_physid(physid) \
105 ({ \ 127 ({ \
106 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ 128 physid_mask_t __physid_mask = PHYSID_MASK_NONE; \
@@ -108,6 +130,12 @@ typedef struct physid_mask physid_mask_t;
108 __physid_mask; \ 130 __physid_mask; \
109 }) 131 })
110 132
133static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
134{
135 physids_clear(*map);
136 physid_set(physid, *map);
137}
138
111#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } 139#define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} }
112#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } 140#define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} }
113 141
diff --git a/include/asm-x86/mpspec_def.h b/include/asm-x86/mpspec_def.h
index dc6ef85e3624..38d1e73b49e4 100644
--- a/include/asm-x86/mpspec_def.h
+++ b/include/asm-x86/mpspec_def.h
@@ -17,10 +17,11 @@
17# define MAX_MPC_ENTRY 1024 17# define MAX_MPC_ENTRY 1024
18# define MAX_APICS 256 18# define MAX_APICS 256
19#else 19#else
20/* 20# if NR_CPUS <= 255
21 * A maximum of 255 APICs with the current APIC ID architecture. 21# define MAX_APICS 255
22 */ 22# else
23# define MAX_APICS 255 23# define MAX_APICS 32768
24# endif
24#endif 25#endif
25 26
26struct intel_mp_floating { 27struct intel_mp_floating {
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index 09413ad39d3c..44bce773012e 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -111,7 +111,9 @@
111#define MSR_K8_TOP_MEM2 0xc001001d 111#define MSR_K8_TOP_MEM2 0xc001001d
112#define MSR_K8_SYSCFG 0xc0010010 112#define MSR_K8_SYSCFG 0xc0010010
113#define MSR_K8_HWCR 0xc0010015 113#define MSR_K8_HWCR 0xc0010015
114#define MSR_K8_ENABLE_C1E 0xc0010055 114#define MSR_K8_INT_PENDING_MSG 0xc0010055
115/* C1E active bits in int pending message */
116#define K8_INTP_C1E_ACTIVE_MASK 0x18000000
115#define MSR_K8_TSEG_ADDR 0xc0010112 117#define MSR_K8_TSEG_ADDR 0xc0010112
116#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */ 118#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
117#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */ 119#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index 2b5f2c91db25..ca110ee73f07 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -66,7 +66,7 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
66static inline void native_write_msr(unsigned int msr, 66static inline void native_write_msr(unsigned int msr,
67 unsigned low, unsigned high) 67 unsigned low, unsigned high)
68{ 68{
69 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high)); 69 asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory");
70} 70}
71 71
72static inline int native_write_msr_safe(unsigned int msr, 72static inline int native_write_msr_safe(unsigned int msr,
@@ -81,7 +81,8 @@ static inline int native_write_msr_safe(unsigned int msr,
81 _ASM_EXTABLE(2b, 3b) 81 _ASM_EXTABLE(2b, 3b)
82 : "=a" (err) 82 : "=a" (err)
83 : "c" (msr), "0" (low), "d" (high), 83 : "c" (msr), "0" (low), "d" (high),
84 "i" (-EFAULT)); 84 "i" (-EFAULT)
85 : "memory");
85 return err; 86 return err;
86} 87}
87 88
diff --git a/include/asm-x86/nmi.h b/include/asm-x86/nmi.h
index 1e363021e72f..21f8d0202a82 100644
--- a/include/asm-x86/nmi.h
+++ b/include/asm-x86/nmi.h
@@ -15,38 +15,13 @@
15 */ 15 */
16int do_nmi_callback(struct pt_regs *regs, int cpu); 16int do_nmi_callback(struct pt_regs *regs, int cpu);
17 17
18#ifdef CONFIG_PM
19
20/** Replace the PM callback routine for NMI. */
21struct pm_dev *set_nmi_pm_callback(pm_callback callback);
22
23/** Unset the PM callback routine back to the default. */
24void unset_nmi_pm_callback(struct pm_dev *dev);
25
26#else
27
28static inline struct pm_dev *set_nmi_pm_callback(pm_callback callback)
29{
30 return 0;
31}
32
33static inline void unset_nmi_pm_callback(struct pm_dev *dev)
34{
35}
36
37#endif /* CONFIG_PM */
38
39#ifdef CONFIG_X86_64 18#ifdef CONFIG_X86_64
40extern void default_do_nmi(struct pt_regs *); 19extern void default_do_nmi(struct pt_regs *);
41extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
42extern void nmi_watchdog_default(void);
43#else
44#define nmi_watchdog_default() do {} while (0)
45#endif 20#endif
46 21
22extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
47extern int check_nmi_watchdog(void); 23extern int check_nmi_watchdog(void);
48extern int nmi_watchdog_enabled; 24extern int nmi_watchdog_enabled;
49extern int unknown_nmi_panic;
50extern int avail_to_resrv_perfctr_nmi_bit(unsigned int); 25extern int avail_to_resrv_perfctr_nmi_bit(unsigned int);
51extern int avail_to_resrv_perfctr_nmi(unsigned int); 26extern int avail_to_resrv_perfctr_nmi(unsigned int);
52extern int reserve_perfctr_nmi(unsigned int); 27extern int reserve_perfctr_nmi(unsigned int);
@@ -62,12 +37,10 @@ extern int nmi_watchdog_tick(struct pt_regs *regs, unsigned reason);
62 37
63extern atomic_t nmi_active; 38extern atomic_t nmi_active;
64extern unsigned int nmi_watchdog; 39extern unsigned int nmi_watchdog;
65#define NMI_DISABLED -1
66#define NMI_NONE 0 40#define NMI_NONE 0
67#define NMI_IO_APIC 1 41#define NMI_IO_APIC 1
68#define NMI_LOCAL_APIC 2 42#define NMI_LOCAL_APIC 2
69#define NMI_INVALID 3 43#define NMI_INVALID 3
70#define NMI_DEFAULT NMI_DISABLED
71 44
72struct ctl_table; 45struct ctl_table;
73struct file; 46struct file;
@@ -78,6 +51,24 @@ extern int unknown_nmi_panic;
78void __trigger_all_cpu_backtrace(void); 51void __trigger_all_cpu_backtrace(void);
79#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace() 52#define trigger_all_cpu_backtrace() __trigger_all_cpu_backtrace()
80 53
54static inline void localise_nmi_watchdog(void)
55{
56 if (nmi_watchdog == NMI_IO_APIC)
57 nmi_watchdog = NMI_LOCAL_APIC;
58}
59
60/* check if nmi_watchdog is active (ie was specified at boot) */
61static inline int nmi_watchdog_active(void)
62{
63 /*
64 * actually it should be:
65 * return (nmi_watchdog == NMI_LOCAL_APIC ||
66 * nmi_watchdog == NMI_IO_APIC)
67 * but since they are power of two we could use a
68 * cheaper way --cvg
69 */
70 return nmi_watchdog & 0x3;
71}
81#endif 72#endif
82 73
83void lapic_watchdog_stop(void); 74void lapic_watchdog_stop(void);
diff --git a/include/asm-x86/numa_32.h b/include/asm-x86/numa_32.h
index 03d0f7a9bf02..220d7b7707a0 100644
--- a/include/asm-x86/numa_32.h
+++ b/include/asm-x86/numa_32.h
@@ -2,14 +2,10 @@
2#define _ASM_X86_32_NUMA_H 1 2#define _ASM_X86_32_NUMA_H 1
3 3
4extern int pxm_to_nid(int pxm); 4extern int pxm_to_nid(int pxm);
5extern void numa_remove_cpu(int cpu);
5 6
6#ifdef CONFIG_NUMA 7#ifdef CONFIG_NUMA
7extern void __init remap_numa_kva(void); 8extern void set_highmem_pages_init(void);
8extern void set_highmem_pages_init(int);
9#else
10static inline void remap_numa_kva(void)
11{
12}
13#endif 9#endif
14 10
15#endif /* _ASM_X86_32_NUMA_H */ 11#endif /* _ASM_X86_32_NUMA_H */
diff --git a/include/asm-x86/numa_64.h b/include/asm-x86/numa_64.h
index 22e87c9f6a80..3830094434a9 100644
--- a/include/asm-x86/numa_64.h
+++ b/include/asm-x86/numa_64.h
@@ -14,32 +14,30 @@ extern int compute_hash_shift(struct bootnode *nodes, int numblks,
14 14
15#define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT)) 15#define ZONE_ALIGN (1UL << (MAX_ORDER+PAGE_SHIFT))
16 16
17extern void numa_add_cpu(int cpu);
18extern void numa_init_array(void); 17extern void numa_init_array(void);
19extern int numa_off; 18extern int numa_off;
20 19
21extern void numa_set_node(int cpu, int node);
22extern void srat_reserve_add_area(int nodeid); 20extern void srat_reserve_add_area(int nodeid);
23extern int hotadd_percent; 21extern int hotadd_percent;
24 22
25extern s16 apicid_to_node[MAX_LOCAL_APIC]; 23extern s16 apicid_to_node[MAX_LOCAL_APIC];
26 24
27extern void numa_initmem_init(unsigned long start_pfn, unsigned long end_pfn);
28extern unsigned long numa_free_all_bootmem(void); 25extern unsigned long numa_free_all_bootmem(void);
29extern void setup_node_bootmem(int nodeid, unsigned long start, 26extern void setup_node_bootmem(int nodeid, unsigned long start,
30 unsigned long end); 27 unsigned long end);
31 28
32#ifdef CONFIG_NUMA 29#ifdef CONFIG_NUMA
33extern void __init init_cpu_to_node(void); 30extern void __init init_cpu_to_node(void);
34 31extern void __cpuinit numa_set_node(int cpu, int node);
35static inline void clear_node_cpumask(int cpu) 32extern void __cpuinit numa_clear_node(int cpu);
36{ 33extern void __cpuinit numa_add_cpu(int cpu);
37 clear_bit(cpu, (unsigned long *)&node_to_cpumask_map[cpu_to_node(cpu)]); 34extern void __cpuinit numa_remove_cpu(int cpu);
38}
39
40#else 35#else
41#define init_cpu_to_node() do {} while (0) 36static inline void init_cpu_to_node(void) { }
42#define clear_node_cpumask(cpu) do {} while (0) 37static inline void numa_set_node(int cpu, int node) { }
38static inline void numa_clear_node(int cpu) { }
39static inline void numa_add_cpu(int cpu, int node) { }
40static inline void numa_remove_cpu(int cpu) { }
43#endif 41#endif
44 42
45#endif 43#endif
diff --git a/include/asm-x86/numaq.h b/include/asm-x86/numaq.h
index 94b86c31239a..34b92d581fa3 100644
--- a/include/asm-x86/numaq.h
+++ b/include/asm-x86/numaq.h
@@ -28,6 +28,7 @@
28 28
29#ifdef CONFIG_X86_NUMAQ 29#ifdef CONFIG_X86_NUMAQ
30 30
31extern int found_numaq;
31extern int get_memcfg_numaq(void); 32extern int get_memcfg_numaq(void);
32 33
33/* 34/*
@@ -156,9 +157,12 @@ struct sys_cfg_data {
156 struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */ 157 struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */
157}; 158};
158 159
159static inline unsigned long *get_zholes_size(int nid) 160void numaq_tsc_disable(void);
161
162#else
163static inline int get_memcfg_numaq(void)
160{ 164{
161 return NULL; 165 return 0;
162} 166}
163#endif /* CONFIG_X86_NUMAQ */ 167#endif /* CONFIG_X86_NUMAQ */
164#endif /* NUMAQ_H */ 168#endif /* NUMAQ_H */
diff --git a/include/asm-x86/page.h b/include/asm-x86/page.h
index dc936dddf161..28d7b4533b1a 100644
--- a/include/asm-x86/page.h
+++ b/include/asm-x86/page.h
@@ -51,9 +51,17 @@
51 51
52#ifndef __ASSEMBLY__ 52#ifndef __ASSEMBLY__
53 53
54typedef struct { pgdval_t pgd; } pgd_t;
55typedef struct { pgprotval_t pgprot; } pgprot_t;
56
54extern int page_is_ram(unsigned long pagenr); 57extern int page_is_ram(unsigned long pagenr);
55extern int devmem_is_allowed(unsigned long pagenr); 58extern int devmem_is_allowed(unsigned long pagenr);
59extern void map_devmem(unsigned long pfn, unsigned long size,
60 pgprot_t vma_prot);
61extern void unmap_devmem(unsigned long pfn, unsigned long size,
62 pgprot_t vma_prot);
56 63
64extern unsigned long max_low_pfn_mapped;
57extern unsigned long max_pfn_mapped; 65extern unsigned long max_pfn_mapped;
58 66
59struct page; 67struct page;
@@ -74,9 +82,6 @@ static inline void copy_user_page(void *to, void *from, unsigned long vaddr,
74 alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr) 82 alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
75#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE 83#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
76 84
77typedef struct { pgdval_t pgd; } pgd_t;
78typedef struct { pgprotval_t pgprot; } pgprot_t;
79
80static inline pgd_t native_make_pgd(pgdval_t val) 85static inline pgd_t native_make_pgd(pgdval_t val)
81{ 86{
82 return (pgd_t) { val }; 87 return (pgd_t) { val };
@@ -160,6 +165,7 @@ static inline pteval_t native_pte_val(pte_t pte)
160#endif 165#endif
161 166
162#define pte_val(x) native_pte_val(x) 167#define pte_val(x) native_pte_val(x)
168#define pte_flags(x) native_pte_val(x)
163#define __pte(x) native_make_pte(x) 169#define __pte(x) native_make_pte(x)
164 170
165#endif /* CONFIG_PARAVIRT */ 171#endif /* CONFIG_PARAVIRT */
diff --git a/include/asm-x86/page_32.h b/include/asm-x86/page_32.h
index ccf0ba3c3aba..ab8528793f08 100644
--- a/include/asm-x86/page_32.h
+++ b/include/asm-x86/page_32.h
@@ -13,6 +13,14 @@
13 */ 13 */
14#define __PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL) 14#define __PAGE_OFFSET _AC(CONFIG_PAGE_OFFSET, UL)
15 15
16#ifdef CONFIG_4KSTACKS
17#define THREAD_ORDER 0
18#else
19#define THREAD_ORDER 1
20#endif
21#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER)
22
23
16#ifdef CONFIG_X86_PAE 24#ifdef CONFIG_X86_PAE
17/* 44=32+12, the limit we can fit into an unsigned long pfn */ 25/* 44=32+12, the limit we can fit into an unsigned long pfn */
18#define __PHYSICAL_MASK_SHIFT 44 26#define __PHYSICAL_MASK_SHIFT 44
@@ -84,6 +92,13 @@ extern int sysctl_legacy_va_layout;
84#define VMALLOC_RESERVE ((unsigned long)__VMALLOC_RESERVE) 92#define VMALLOC_RESERVE ((unsigned long)__VMALLOC_RESERVE)
85#define MAXMEM (-__PAGE_OFFSET - __VMALLOC_RESERVE) 93#define MAXMEM (-__PAGE_OFFSET - __VMALLOC_RESERVE)
86 94
95extern void find_low_pfn_range(void);
96extern unsigned long init_memory_mapping(unsigned long start,
97 unsigned long end);
98extern void initmem_init(unsigned long, unsigned long);
99extern void setup_bootmem_allocator(void);
100
101
87#ifdef CONFIG_X86_USE_3DNOW 102#ifdef CONFIG_X86_USE_3DNOW
88#include <asm/mmx.h> 103#include <asm/mmx.h>
89 104
diff --git a/include/asm-x86/page_64.h b/include/asm-x86/page_64.h
index 6ea72859c491..c6916c83e6b1 100644
--- a/include/asm-x86/page_64.h
+++ b/include/asm-x86/page_64.h
@@ -26,7 +26,13 @@
26#define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT) 26#define PUD_PAGE_SIZE (_AC(1, UL) << PUD_SHIFT)
27#define PUD_PAGE_MASK (~(PUD_PAGE_SIZE-1)) 27#define PUD_PAGE_MASK (~(PUD_PAGE_SIZE-1))
28 28
29#define __PAGE_OFFSET _AC(0xffff810000000000, UL) 29/*
30 * Set __PAGE_OFFSET to the most negative possible address +
31 * PGDIR_SIZE*16 (pgd slot 272). The gap is to allow a space for a
32 * hypervisor to fit. Choosing 16 slots here is arbitrary, but it's
33 * what Xen requires.
34 */
35#define __PAGE_OFFSET _AC(0xffff880000000000, UL)
30 36
31#define __PHYSICAL_START CONFIG_PHYSICAL_START 37#define __PHYSICAL_START CONFIG_PHYSICAL_START
32#define __KERNEL_ALIGN 0x200000 38#define __KERNEL_ALIGN 0x200000
@@ -58,7 +64,8 @@
58void clear_page(void *page); 64void clear_page(void *page);
59void copy_page(void *to, void *from); 65void copy_page(void *to, void *from);
60 66
61extern unsigned long end_pfn; 67/* duplicated to the one in bootmem.h */
68extern unsigned long max_pfn;
62extern unsigned long phys_base; 69extern unsigned long phys_base;
63 70
64extern unsigned long __phys_addr(unsigned long); 71extern unsigned long __phys_addr(unsigned long);
@@ -83,10 +90,15 @@ typedef struct { pteval_t pte; } pte_t;
83extern unsigned long init_memory_mapping(unsigned long start, 90extern unsigned long init_memory_mapping(unsigned long start,
84 unsigned long end); 91 unsigned long end);
85 92
93extern void initmem_init(unsigned long start_pfn, unsigned long end_pfn);
94
95extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
96extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
97
86#endif /* !__ASSEMBLY__ */ 98#endif /* !__ASSEMBLY__ */
87 99
88#ifdef CONFIG_FLATMEM 100#ifdef CONFIG_FLATMEM
89#define pfn_valid(pfn) ((pfn) < end_pfn) 101#define pfn_valid(pfn) ((pfn) < max_pfn)
90#endif 102#endif
91 103
92 104
diff --git a/include/asm-x86/paravirt.h b/include/asm-x86/paravirt.h
index 0f13b945e240..ef5e8ec6a6ab 100644
--- a/include/asm-x86/paravirt.h
+++ b/include/asm-x86/paravirt.h
@@ -84,7 +84,7 @@ struct pv_time_ops {
84 int (*set_wallclock)(unsigned long); 84 int (*set_wallclock)(unsigned long);
85 85
86 unsigned long long (*sched_clock)(void); 86 unsigned long long (*sched_clock)(void);
87 unsigned long (*get_cpu_khz)(void); 87 unsigned long (*get_tsc_khz)(void);
88}; 88};
89 89
90struct pv_cpu_ops { 90struct pv_cpu_ops {
@@ -115,6 +115,9 @@ struct pv_cpu_ops {
115 void (*set_ldt)(const void *desc, unsigned entries); 115 void (*set_ldt)(const void *desc, unsigned entries);
116 unsigned long (*store_tr)(void); 116 unsigned long (*store_tr)(void);
117 void (*load_tls)(struct thread_struct *t, unsigned int cpu); 117 void (*load_tls)(struct thread_struct *t, unsigned int cpu);
118#ifdef CONFIG_X86_64
119 void (*load_gs_index)(unsigned int idx);
120#endif
118 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum, 121 void (*write_ldt_entry)(struct desc_struct *ldt, int entrynum,
119 const void *desc); 122 const void *desc);
120 void (*write_gdt_entry)(struct desc_struct *, 123 void (*write_gdt_entry)(struct desc_struct *,
@@ -141,8 +144,32 @@ struct pv_cpu_ops {
141 u64 (*read_pmc)(int counter); 144 u64 (*read_pmc)(int counter);
142 unsigned long long (*read_tscp)(unsigned int *aux); 145 unsigned long long (*read_tscp)(unsigned int *aux);
143 146
144 /* These two are jmp to, not actually called. */ 147 /*
145 void (*irq_enable_syscall_ret)(void); 148 * Atomically enable interrupts and return to userspace. This
149 * is only ever used to return to 32-bit processes; in a
150 * 64-bit kernel, it's used for 32-on-64 compat processes, but
151 * never native 64-bit processes. (Jump, not call.)
152 */
153 void (*irq_enable_sysexit)(void);
154
155 /*
156 * Switch to usermode gs and return to 64-bit usermode using
157 * sysret. Only used in 64-bit kernels to return to 64-bit
158 * processes. Usermode register state, including %rsp, must
159 * already be restored.
160 */
161 void (*usergs_sysret64)(void);
162
163 /*
164 * Switch to usermode gs and return to 32-bit usermode using
165 * sysret. Used to return to 32-on-64 compat processes.
166 * Other usermode register state, including %esp, must already
167 * be restored.
168 */
169 void (*usergs_sysret32)(void);
170
171 /* Normal iret. Jump to this with the standard iret stack
172 frame set up. */
146 void (*iret)(void); 173 void (*iret)(void);
147 174
148 void (*swapgs)(void); 175 void (*swapgs)(void);
@@ -165,6 +192,10 @@ struct pv_irq_ops {
165 void (*irq_enable)(void); 192 void (*irq_enable)(void);
166 void (*safe_halt)(void); 193 void (*safe_halt)(void);
167 void (*halt)(void); 194 void (*halt)(void);
195
196#ifdef CONFIG_X86_64
197 void (*adjust_exception_frame)(void);
198#endif
168}; 199};
169 200
170struct pv_apic_ops { 201struct pv_apic_ops {
@@ -219,7 +250,14 @@ struct pv_mmu_ops {
219 void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm, 250 void (*flush_tlb_others)(const cpumask_t *cpus, struct mm_struct *mm,
220 unsigned long va); 251 unsigned long va);
221 252
222 /* Hooks for allocating/releasing pagetable pages */ 253 /* Hooks for allocating and freeing a pagetable top-level */
254 int (*pgd_alloc)(struct mm_struct *mm);
255 void (*pgd_free)(struct mm_struct *mm, pgd_t *pgd);
256
257 /*
258 * Hooks for allocating/releasing pagetable pages when they're
259 * attached to a pagetable
260 */
223 void (*alloc_pte)(struct mm_struct *mm, u32 pfn); 261 void (*alloc_pte)(struct mm_struct *mm, u32 pfn);
224 void (*alloc_pmd)(struct mm_struct *mm, u32 pfn); 262 void (*alloc_pmd)(struct mm_struct *mm, u32 pfn);
225 void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count); 263 void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
@@ -238,7 +276,13 @@ struct pv_mmu_ops {
238 void (*pte_update_defer)(struct mm_struct *mm, 276 void (*pte_update_defer)(struct mm_struct *mm,
239 unsigned long addr, pte_t *ptep); 277 unsigned long addr, pte_t *ptep);
240 278
279 pte_t (*ptep_modify_prot_start)(struct mm_struct *mm, unsigned long addr,
280 pte_t *ptep);
281 void (*ptep_modify_prot_commit)(struct mm_struct *mm, unsigned long addr,
282 pte_t *ptep, pte_t pte);
283
241 pteval_t (*pte_val)(pte_t); 284 pteval_t (*pte_val)(pte_t);
285 pteval_t (*pte_flags)(pte_t);
242 pte_t (*make_pte)(pteval_t pte); 286 pte_t (*make_pte)(pteval_t pte);
243 287
244 pgdval_t (*pgd_val)(pgd_t); 288 pgdval_t (*pgd_val)(pgd_t);
@@ -273,6 +317,13 @@ struct pv_mmu_ops {
273#endif 317#endif
274 318
275 struct pv_lazy_ops lazy_mode; 319 struct pv_lazy_ops lazy_mode;
320
321 /* dom0 ops */
322
323 /* Sometimes the physical address is a pfn, and sometimes its
324 an mfn. We can tell which is which from the index. */
325 void (*set_fixmap)(unsigned /* enum fixed_addresses */ idx,
326 unsigned long phys, pgprot_t flags);
276}; 327};
277 328
278/* This contains all the paravirt structures: we get a convenient 329/* This contains all the paravirt structures: we get a convenient
@@ -439,10 +490,17 @@ int paravirt_disable_iospace(void);
439#define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11" 490#define VEXTRA_CLOBBERS , "rax", "r8", "r9", "r10", "r11"
440#endif 491#endif
441 492
493#ifdef CONFIG_PARAVIRT_DEBUG
494#define PVOP_TEST_NULL(op) BUG_ON(op == NULL)
495#else
496#define PVOP_TEST_NULL(op) ((void)op)
497#endif
498
442#define __PVOP_CALL(rettype, op, pre, post, ...) \ 499#define __PVOP_CALL(rettype, op, pre, post, ...) \
443 ({ \ 500 ({ \
444 rettype __ret; \ 501 rettype __ret; \
445 PVOP_CALL_ARGS; \ 502 PVOP_CALL_ARGS; \
503 PVOP_TEST_NULL(op); \
446 /* This is 32-bit specific, but is okay in 64-bit */ \ 504 /* This is 32-bit specific, but is okay in 64-bit */ \
447 /* since this condition will never hold */ \ 505 /* since this condition will never hold */ \
448 if (sizeof(rettype) > sizeof(unsigned long)) { \ 506 if (sizeof(rettype) > sizeof(unsigned long)) { \
@@ -471,6 +529,7 @@ int paravirt_disable_iospace(void);
471#define __PVOP_VCALL(op, pre, post, ...) \ 529#define __PVOP_VCALL(op, pre, post, ...) \
472 ({ \ 530 ({ \
473 PVOP_VCALL_ARGS; \ 531 PVOP_VCALL_ARGS; \
532 PVOP_TEST_NULL(op); \
474 asm volatile(pre \ 533 asm volatile(pre \
475 paravirt_alt(PARAVIRT_CALL) \ 534 paravirt_alt(PARAVIRT_CALL) \
476 post \ 535 post \
@@ -720,7 +779,7 @@ static inline unsigned long long paravirt_sched_clock(void)
720{ 779{
721 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock); 780 return PVOP_CALL0(unsigned long long, pv_time_ops.sched_clock);
722} 781}
723#define calculate_cpu_khz() (pv_time_ops.get_cpu_khz()) 782#define calibrate_tsc() (pv_time_ops.get_tsc_khz())
724 783
725static inline unsigned long long paravirt_read_pmc(int counter) 784static inline unsigned long long paravirt_read_pmc(int counter)
726{ 785{
@@ -789,6 +848,13 @@ static inline void load_TLS(struct thread_struct *t, unsigned cpu)
789 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu); 848 PVOP_VCALL2(pv_cpu_ops.load_tls, t, cpu);
790} 849}
791 850
851#ifdef CONFIG_X86_64
852static inline void load_gs_index(unsigned int gs)
853{
854 PVOP_VCALL1(pv_cpu_ops.load_gs_index, gs);
855}
856#endif
857
792static inline void write_ldt_entry(struct desc_struct *dt, int entry, 858static inline void write_ldt_entry(struct desc_struct *dt, int entry,
793 const void *desc) 859 const void *desc)
794{ 860{
@@ -912,6 +978,16 @@ static inline void flush_tlb_others(cpumask_t cpumask, struct mm_struct *mm,
912 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va); 978 PVOP_VCALL3(pv_mmu_ops.flush_tlb_others, &cpumask, mm, va);
913} 979}
914 980
981static inline int paravirt_pgd_alloc(struct mm_struct *mm)
982{
983 return PVOP_CALL1(int, pv_mmu_ops.pgd_alloc, mm);
984}
985
986static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
987{
988 PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
989}
990
915static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn) 991static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn)
916{ 992{
917 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn); 993 PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
@@ -996,6 +1072,20 @@ static inline pteval_t pte_val(pte_t pte)
996 return ret; 1072 return ret;
997} 1073}
998 1074
1075static inline pteval_t pte_flags(pte_t pte)
1076{
1077 pteval_t ret;
1078
1079 if (sizeof(pteval_t) > sizeof(long))
1080 ret = PVOP_CALL2(pteval_t, pv_mmu_ops.pte_flags,
1081 pte.pte, (u64)pte.pte >> 32);
1082 else
1083 ret = PVOP_CALL1(pteval_t, pv_mmu_ops.pte_flags,
1084 pte.pte);
1085
1086 return ret;
1087}
1088
999static inline pgd_t __pgd(pgdval_t val) 1089static inline pgd_t __pgd(pgdval_t val)
1000{ 1090{
1001 pgdval_t ret; 1091 pgdval_t ret;
@@ -1024,6 +1114,29 @@ static inline pgdval_t pgd_val(pgd_t pgd)
1024 return ret; 1114 return ret;
1025} 1115}
1026 1116
1117#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1118static inline pte_t ptep_modify_prot_start(struct mm_struct *mm, unsigned long addr,
1119 pte_t *ptep)
1120{
1121 pteval_t ret;
1122
1123 ret = PVOP_CALL3(pteval_t, pv_mmu_ops.ptep_modify_prot_start,
1124 mm, addr, ptep);
1125
1126 return (pte_t) { .pte = ret };
1127}
1128
1129static inline void ptep_modify_prot_commit(struct mm_struct *mm, unsigned long addr,
1130 pte_t *ptep, pte_t pte)
1131{
1132 if (sizeof(pteval_t) > sizeof(long))
1133 /* 5 arg words */
1134 pv_mmu_ops.ptep_modify_prot_commit(mm, addr, ptep, pte);
1135 else
1136 PVOP_VCALL4(pv_mmu_ops.ptep_modify_prot_commit,
1137 mm, addr, ptep, pte.pte);
1138}
1139
1027static inline void set_pte(pte_t *ptep, pte_t pte) 1140static inline void set_pte(pte_t *ptep, pte_t pte)
1028{ 1141{
1029 if (sizeof(pteval_t) > sizeof(long)) 1142 if (sizeof(pteval_t) > sizeof(long))
@@ -1252,6 +1365,12 @@ static inline void arch_flush_lazy_mmu_mode(void)
1252 } 1365 }
1253} 1366}
1254 1367
1368static inline void __set_fixmap(unsigned /* enum fixed_addresses */ idx,
1369 unsigned long phys, pgprot_t flags)
1370{
1371 pv_mmu_ops.set_fixmap(idx, phys, flags);
1372}
1373
1255void _paravirt_nop(void); 1374void _paravirt_nop(void);
1256#define paravirt_nop ((void *)_paravirt_nop) 1375#define paravirt_nop ((void *)_paravirt_nop)
1257 1376
@@ -1374,54 +1493,86 @@ static inline unsigned long __raw_local_irq_save(void)
1374#define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax 1493#define PV_RESTORE_REGS popq %rdx; popq %rcx; popq %rdi; popq %rax
1375#define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8) 1494#define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 8)
1376#define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8) 1495#define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .quad, 8)
1496#define PARA_INDIRECT(addr) *addr(%rip)
1377#else 1497#else
1378#define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx 1498#define PV_SAVE_REGS pushl %eax; pushl %edi; pushl %ecx; pushl %edx
1379#define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax 1499#define PV_RESTORE_REGS popl %edx; popl %ecx; popl %edi; popl %eax
1380#define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4) 1500#define PARA_PATCH(struct, off) ((PARAVIRT_PATCH_##struct + (off)) / 4)
1381#define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4) 1501#define PARA_SITE(ptype, clobbers, ops) _PVSITE(ptype, clobbers, ops, .long, 4)
1502#define PARA_INDIRECT(addr) *%cs:addr
1382#endif 1503#endif
1383 1504
1384#define INTERRUPT_RETURN \ 1505#define INTERRUPT_RETURN \
1385 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \ 1506 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_iret), CLBR_NONE, \
1386 jmp *%cs:pv_cpu_ops+PV_CPU_iret) 1507 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_iret))
1387 1508
1388#define DISABLE_INTERRUPTS(clobbers) \ 1509#define DISABLE_INTERRUPTS(clobbers) \
1389 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \ 1510 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_disable), clobbers, \
1390 PV_SAVE_REGS; \ 1511 PV_SAVE_REGS; \
1391 call *%cs:pv_irq_ops+PV_IRQ_irq_disable; \ 1512 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_disable); \
1392 PV_RESTORE_REGS;) \ 1513 PV_RESTORE_REGS;) \
1393 1514
1394#define ENABLE_INTERRUPTS(clobbers) \ 1515#define ENABLE_INTERRUPTS(clobbers) \
1395 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \ 1516 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_irq_enable), clobbers, \
1396 PV_SAVE_REGS; \ 1517 PV_SAVE_REGS; \
1397 call *%cs:pv_irq_ops+PV_IRQ_irq_enable; \ 1518 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_irq_enable); \
1398 PV_RESTORE_REGS;) 1519 PV_RESTORE_REGS;)
1399 1520
1400#define ENABLE_INTERRUPTS_SYSCALL_RET \ 1521#define USERGS_SYSRET32 \
1401 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_syscall_ret),\ 1522 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret32), \
1402 CLBR_NONE, \ 1523 CLBR_NONE, \
1403 jmp *%cs:pv_cpu_ops+PV_CPU_irq_enable_syscall_ret) 1524 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret32))
1404
1405 1525
1406#ifdef CONFIG_X86_32 1526#ifdef CONFIG_X86_32
1407#define GET_CR0_INTO_EAX \ 1527#define GET_CR0_INTO_EAX \
1408 push %ecx; push %edx; \ 1528 push %ecx; push %edx; \
1409 call *pv_cpu_ops+PV_CPU_read_cr0; \ 1529 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_read_cr0); \
1410 pop %edx; pop %ecx 1530 pop %edx; pop %ecx
1411#else 1531
1532#define ENABLE_INTERRUPTS_SYSEXIT \
1533 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1534 CLBR_NONE, \
1535 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1536
1537
1538#else /* !CONFIG_X86_32 */
1539
1540/*
1541 * If swapgs is used while the userspace stack is still current,
1542 * there's no way to call a pvop. The PV replacement *must* be
1543 * inlined, or the swapgs instruction must be trapped and emulated.
1544 */
1545#define SWAPGS_UNSAFE_STACK \
1546 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1547 swapgs)
1548
1412#define SWAPGS \ 1549#define SWAPGS \
1413 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \ 1550 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_swapgs), CLBR_NONE, \
1414 PV_SAVE_REGS; \ 1551 PV_SAVE_REGS; \
1415 call *pv_cpu_ops+PV_CPU_swapgs; \ 1552 call PARA_INDIRECT(pv_cpu_ops+PV_CPU_swapgs); \
1416 PV_RESTORE_REGS \ 1553 PV_RESTORE_REGS \
1417 ) 1554 )
1418 1555
1419#define GET_CR2_INTO_RCX \ 1556#define GET_CR2_INTO_RCX \
1420 call *pv_mmu_ops+PV_MMU_read_cr2; \ 1557 call PARA_INDIRECT(pv_mmu_ops+PV_MMU_read_cr2); \
1421 movq %rax, %rcx; \ 1558 movq %rax, %rcx; \
1422 xorq %rax, %rax; 1559 xorq %rax, %rax;
1423 1560
1424#endif 1561#define PARAVIRT_ADJUST_EXCEPTION_FRAME \
1562 PARA_SITE(PARA_PATCH(pv_irq_ops, PV_IRQ_adjust_exception_frame), \
1563 CLBR_NONE, \
1564 call PARA_INDIRECT(pv_irq_ops+PV_IRQ_adjust_exception_frame))
1565
1566#define USERGS_SYSRET64 \
1567 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_usergs_sysret64), \
1568 CLBR_NONE, \
1569 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_usergs_sysret64))
1570
1571#define ENABLE_INTERRUPTS_SYSEXIT32 \
1572 PARA_SITE(PARA_PATCH(pv_cpu_ops, PV_CPU_irq_enable_sysexit), \
1573 CLBR_NONE, \
1574 jmp PARA_INDIRECT(pv_cpu_ops+PV_CPU_irq_enable_sysexit))
1575#endif /* CONFIG_X86_32 */
1425 1576
1426#endif /* __ASSEMBLY__ */ 1577#endif /* __ASSEMBLY__ */
1427#endif /* CONFIG_PARAVIRT */ 1578#endif /* CONFIG_PARAVIRT */
diff --git a/include/asm-x86/pat.h b/include/asm-x86/pat.h
index 88f60cc6a227..7edc47307217 100644
--- a/include/asm-x86/pat.h
+++ b/include/asm-x86/pat.h
@@ -1,14 +1,13 @@
1
2#ifndef _ASM_PAT_H 1#ifndef _ASM_PAT_H
3#define _ASM_PAT_H 1 2#define _ASM_PAT_H
4 3
5#include <linux/types.h> 4#include <linux/types.h>
6 5
7#ifdef CONFIG_X86_PAT 6#ifdef CONFIG_X86_PAT
8extern int pat_wc_enabled; 7extern int pat_enabled;
9extern void validate_pat_support(struct cpuinfo_x86 *c); 8extern void validate_pat_support(struct cpuinfo_x86 *c);
10#else 9#else
11static const int pat_wc_enabled = 0; 10static const int pat_enabled;
12static inline void validate_pat_support(struct cpuinfo_x86 *c) { } 11static inline void validate_pat_support(struct cpuinfo_x86 *c) { }
13#endif 12#endif
14 13
@@ -21,4 +20,3 @@ extern int free_memtype(u64 start, u64 end);
21extern void pat_disable(char *reason); 20extern void pat_disable(char *reason);
22 21
23#endif 22#endif
24
diff --git a/include/asm-x86/pci.h b/include/asm-x86/pci.h
index 30bbde0cb34b..2db14cf17db8 100644
--- a/include/asm-x86/pci.h
+++ b/include/asm-x86/pci.h
@@ -18,6 +18,8 @@ struct pci_sysdata {
18#endif 18#endif
19}; 19};
20 20
21extern int pci_routeirq;
22
21/* scan a bus after allocating a pci_sysdata for it */ 23/* scan a bus after allocating a pci_sysdata for it */
22extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops, 24extern struct pci_bus *pci_scan_bus_on_node(int busno, struct pci_ops *ops,
23 int node); 25 int node);
diff --git a/include/asm-x86/pci_32.h b/include/asm-x86/pci_32.h
index 8c4c3a0368e2..a50d46851285 100644
--- a/include/asm-x86/pci_32.h
+++ b/include/asm-x86/pci_32.h
@@ -18,12 +18,14 @@ struct pci_dev;
18#define PCI_DMA_BUS_IS_PHYS (1) 18#define PCI_DMA_BUS_IS_PHYS (1)
19 19
20/* pci_unmap_{page,single} is a nop so... */ 20/* pci_unmap_{page,single} is a nop so... */
21#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) 21#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) dma_addr_t ADDR_NAME[0];
22#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) 22#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) unsigned LEN_NAME[0];
23#define pci_unmap_addr(PTR, ADDR_NAME) (0) 23#define pci_unmap_addr(PTR, ADDR_NAME) sizeof((PTR)->ADDR_NAME)
24#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) 24#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
25#define pci_unmap_len(PTR, LEN_NAME) (0) 25 do { break; } while (pci_unmap_addr(PTR, ADDR_NAME))
26#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) 26#define pci_unmap_len(PTR, LEN_NAME) sizeof((PTR)->LEN_NAME)
27#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
28 do { break; } while (pci_unmap_len(PTR, LEN_NAME))
27 29
28 30
29#endif /* __KERNEL__ */ 31#endif /* __KERNEL__ */
diff --git a/include/asm-x86/pda.h b/include/asm-x86/pda.h
index 101fb9e11954..b34e9a7cc80b 100644
--- a/include/asm-x86/pda.h
+++ b/include/asm-x86/pda.h
@@ -22,6 +22,8 @@ struct x8664_pda {
22 offset 40!!! */ 22 offset 40!!! */
23#endif 23#endif
24 char *irqstackptr; 24 char *irqstackptr;
25 short nodenumber; /* number of current node (32k max) */
26 short in_bootmem; /* pda lives in bootmem */
25 unsigned int __softirq_pending; 27 unsigned int __softirq_pending;
26 unsigned int __nmi_count; /* number of NMI on this CPUs */ 28 unsigned int __nmi_count; /* number of NMI on this CPUs */
27 short mmu_state; 29 short mmu_state;
@@ -37,8 +39,7 @@ struct x8664_pda {
37 unsigned irq_spurious_count; 39 unsigned irq_spurious_count;
38} ____cacheline_aligned_in_smp; 40} ____cacheline_aligned_in_smp;
39 41
40extern struct x8664_pda *_cpu_pda[]; 42extern struct x8664_pda **_cpu_pda;
41extern struct x8664_pda boot_cpu_pda[];
42extern void pda_init(int); 43extern void pda_init(int);
43 44
44#define cpu_pda(i) (_cpu_pda[i]) 45#define cpu_pda(i) (_cpu_pda[i])
diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h
index 736fc3bb8e1e..912a3a17b9db 100644
--- a/include/asm-x86/percpu.h
+++ b/include/asm-x86/percpu.h
@@ -143,4 +143,50 @@ do { \
143#define x86_or_percpu(var, val) percpu_to_op("or", per_cpu__##var, val) 143#define x86_or_percpu(var, val) percpu_to_op("or", per_cpu__##var, val)
144#endif /* !__ASSEMBLY__ */ 144#endif /* !__ASSEMBLY__ */
145#endif /* !CONFIG_X86_64 */ 145#endif /* !CONFIG_X86_64 */
146
147#ifdef CONFIG_SMP
148
149/*
150 * Define the "EARLY_PER_CPU" macros. These are used for some per_cpu
151 * variables that are initialized and accessed before there are per_cpu
152 * areas allocated.
153 */
154
155#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
156 DEFINE_PER_CPU(_type, _name) = _initvalue; \
157 __typeof__(_type) _name##_early_map[NR_CPUS] __initdata = \
158 { [0 ... NR_CPUS-1] = _initvalue }; \
159 __typeof__(_type) *_name##_early_ptr = _name##_early_map
160
161#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
162 EXPORT_PER_CPU_SYMBOL(_name)
163
164#define DECLARE_EARLY_PER_CPU(_type, _name) \
165 DECLARE_PER_CPU(_type, _name); \
166 extern __typeof__(_type) *_name##_early_ptr; \
167 extern __typeof__(_type) _name##_early_map[]
168
169#define early_per_cpu_ptr(_name) (_name##_early_ptr)
170#define early_per_cpu_map(_name, _idx) (_name##_early_map[_idx])
171#define early_per_cpu(_name, _cpu) \
172 (early_per_cpu_ptr(_name) ? \
173 early_per_cpu_ptr(_name)[_cpu] : \
174 per_cpu(_name, _cpu))
175
176#else /* !CONFIG_SMP */
177#define DEFINE_EARLY_PER_CPU(_type, _name, _initvalue) \
178 DEFINE_PER_CPU(_type, _name) = _initvalue
179
180#define EXPORT_EARLY_PER_CPU_SYMBOL(_name) \
181 EXPORT_PER_CPU_SYMBOL(_name)
182
183#define DECLARE_EARLY_PER_CPU(_type, _name) \
184 DECLARE_PER_CPU(_type, _name)
185
186#define early_per_cpu(_name, _cpu) per_cpu(_name, _cpu)
187#define early_per_cpu_ptr(_name) NULL
188/* no early_per_cpu_map() */
189
190#endif /* !CONFIG_SMP */
191
146#endif /* _ASM_X86_PERCPU_H_ */ 192#endif /* _ASM_X86_PERCPU_H_ */
diff --git a/include/asm-x86/pgalloc.h b/include/asm-x86/pgalloc.h
index 91e4641f3f31..d63ea431cb3b 100644
--- a/include/asm-x86/pgalloc.h
+++ b/include/asm-x86/pgalloc.h
@@ -5,9 +5,13 @@
5#include <linux/mm.h> /* for struct page */ 5#include <linux/mm.h> /* for struct page */
6#include <linux/pagemap.h> 6#include <linux/pagemap.h>
7 7
8static inline int __paravirt_pgd_alloc(struct mm_struct *mm) { return 0; }
9
8#ifdef CONFIG_PARAVIRT 10#ifdef CONFIG_PARAVIRT
9#include <asm/paravirt.h> 11#include <asm/paravirt.h>
10#else 12#else
13#define paravirt_pgd_alloc(mm) __paravirt_pgd_alloc(mm)
14static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd) {}
11static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) {} 15static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn) {}
12static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) {} 16static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn) {}
13static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn, 17static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h
index 97c271b2910b..49cbd76b9547 100644
--- a/include/asm-x86/pgtable.h
+++ b/include/asm-x86/pgtable.h
@@ -20,30 +20,25 @@
20#define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */ 20#define _PAGE_BIT_PAT_LARGE 12 /* On 2MB or 1GB pages */
21#define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */ 21#define _PAGE_BIT_NX 63 /* No execute: only valid after cpuid check */
22 22
23/* 23#define _PAGE_PRESENT (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
24 * Note: we use _AC(1, L) instead of _AC(1, UL) so that we get a 24#define _PAGE_RW (_AT(pteval_t, 1) << _PAGE_BIT_RW)
25 * sign-extended value on 32-bit with all 1's in the upper word, 25#define _PAGE_USER (_AT(pteval_t, 1) << _PAGE_BIT_USER)
26 * which preserves the upper pte values on 64-bit ptes: 26#define _PAGE_PWT (_AT(pteval_t, 1) << _PAGE_BIT_PWT)
27 */ 27#define _PAGE_PCD (_AT(pteval_t, 1) << _PAGE_BIT_PCD)
28#define _PAGE_PRESENT (_AC(1, L)<<_PAGE_BIT_PRESENT) 28#define _PAGE_ACCESSED (_AT(pteval_t, 1) << _PAGE_BIT_ACCESSED)
29#define _PAGE_RW (_AC(1, L)<<_PAGE_BIT_RW) 29#define _PAGE_DIRTY (_AT(pteval_t, 1) << _PAGE_BIT_DIRTY)
30#define _PAGE_USER (_AC(1, L)<<_PAGE_BIT_USER) 30#define _PAGE_PSE (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
31#define _PAGE_PWT (_AC(1, L)<<_PAGE_BIT_PWT) 31#define _PAGE_GLOBAL (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
32#define _PAGE_PCD (_AC(1, L)<<_PAGE_BIT_PCD) 32#define _PAGE_UNUSED1 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1)
33#define _PAGE_ACCESSED (_AC(1, L)<<_PAGE_BIT_ACCESSED) 33#define _PAGE_UNUSED2 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED2)
34#define _PAGE_DIRTY (_AC(1, L)<<_PAGE_BIT_DIRTY) 34#define _PAGE_UNUSED3 (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED3)
35#define _PAGE_PSE (_AC(1, L)<<_PAGE_BIT_PSE) /* 2MB page */ 35#define _PAGE_PAT (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
36#define _PAGE_GLOBAL (_AC(1, L)<<_PAGE_BIT_GLOBAL) /* Global TLB entry */ 36#define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
37#define _PAGE_UNUSED1 (_AC(1, L)<<_PAGE_BIT_UNUSED1)
38#define _PAGE_UNUSED2 (_AC(1, L)<<_PAGE_BIT_UNUSED2)
39#define _PAGE_UNUSED3 (_AC(1, L)<<_PAGE_BIT_UNUSED3)
40#define _PAGE_PAT (_AC(1, L)<<_PAGE_BIT_PAT)
41#define _PAGE_PAT_LARGE (_AC(1, L)<<_PAGE_BIT_PAT_LARGE)
42 37
43#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE) 38#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
44#define _PAGE_NX (_AC(1, ULL) << _PAGE_BIT_NX) 39#define _PAGE_NX (_AT(pteval_t, 1) << _PAGE_BIT_NX)
45#else 40#else
46#define _PAGE_NX 0 41#define _PAGE_NX (_AT(pteval_t, 0))
47#endif 42#endif
48 43
49/* If _PAGE_PRESENT is clear, we use these: */ 44/* If _PAGE_PRESENT is clear, we use these: */
@@ -83,19 +78,9 @@
83#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \ 78#define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | \
84 _PAGE_ACCESSED) 79 _PAGE_ACCESSED)
85 80
86#ifdef CONFIG_X86_32
87#define _PAGE_KERNEL_EXEC \
88 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
89#define _PAGE_KERNEL (_PAGE_KERNEL_EXEC | _PAGE_NX)
90
91#ifndef __ASSEMBLY__
92extern pteval_t __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
93#endif /* __ASSEMBLY__ */
94#else
95#define __PAGE_KERNEL_EXEC \ 81#define __PAGE_KERNEL_EXEC \
96 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED) 82 (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_GLOBAL)
97#define __PAGE_KERNEL (__PAGE_KERNEL_EXEC | _PAGE_NX) 83#define __PAGE_KERNEL (__PAGE_KERNEL_EXEC | _PAGE_NX)
98#endif
99 84
100#define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW) 85#define __PAGE_KERNEL_RO (__PAGE_KERNEL & ~_PAGE_RW)
101#define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW) 86#define __PAGE_KERNEL_RX (__PAGE_KERNEL_EXEC & ~_PAGE_RW)
@@ -106,26 +91,22 @@ extern pteval_t __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
106#define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER) 91#define __PAGE_KERNEL_VSYSCALL (__PAGE_KERNEL_RX | _PAGE_USER)
107#define __PAGE_KERNEL_VSYSCALL_NOCACHE (__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT) 92#define __PAGE_KERNEL_VSYSCALL_NOCACHE (__PAGE_KERNEL_VSYSCALL | _PAGE_PCD | _PAGE_PWT)
108#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE) 93#define __PAGE_KERNEL_LARGE (__PAGE_KERNEL | _PAGE_PSE)
94#define __PAGE_KERNEL_LARGE_NOCACHE (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
109#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE) 95#define __PAGE_KERNEL_LARGE_EXEC (__PAGE_KERNEL_EXEC | _PAGE_PSE)
110 96
111#ifdef CONFIG_X86_32 97#define PAGE_KERNEL __pgprot(__PAGE_KERNEL)
112# define MAKE_GLOBAL(x) __pgprot((x)) 98#define PAGE_KERNEL_RO __pgprot(__PAGE_KERNEL_RO)
113#else 99#define PAGE_KERNEL_EXEC __pgprot(__PAGE_KERNEL_EXEC)
114# define MAKE_GLOBAL(x) __pgprot((x) | _PAGE_GLOBAL) 100#define PAGE_KERNEL_RX __pgprot(__PAGE_KERNEL_RX)
115#endif 101#define PAGE_KERNEL_WC __pgprot(__PAGE_KERNEL_WC)
116 102#define PAGE_KERNEL_NOCACHE __pgprot(__PAGE_KERNEL_NOCACHE)
117#define PAGE_KERNEL MAKE_GLOBAL(__PAGE_KERNEL) 103#define PAGE_KERNEL_UC_MINUS __pgprot(__PAGE_KERNEL_UC_MINUS)
118#define PAGE_KERNEL_RO MAKE_GLOBAL(__PAGE_KERNEL_RO) 104#define PAGE_KERNEL_EXEC_NOCACHE __pgprot(__PAGE_KERNEL_EXEC_NOCACHE)
119#define PAGE_KERNEL_EXEC MAKE_GLOBAL(__PAGE_KERNEL_EXEC) 105#define PAGE_KERNEL_LARGE __pgprot(__PAGE_KERNEL_LARGE)
120#define PAGE_KERNEL_RX MAKE_GLOBAL(__PAGE_KERNEL_RX) 106#define PAGE_KERNEL_LARGE_NOCACHE __pgprot(__PAGE_KERNEL_LARGE_NOCACHE)
121#define PAGE_KERNEL_WC MAKE_GLOBAL(__PAGE_KERNEL_WC) 107#define PAGE_KERNEL_LARGE_EXEC __pgprot(__PAGE_KERNEL_LARGE_EXEC)
122#define PAGE_KERNEL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_NOCACHE) 108#define PAGE_KERNEL_VSYSCALL __pgprot(__PAGE_KERNEL_VSYSCALL)
123#define PAGE_KERNEL_UC_MINUS MAKE_GLOBAL(__PAGE_KERNEL_UC_MINUS) 109#define PAGE_KERNEL_VSYSCALL_NOCACHE __pgprot(__PAGE_KERNEL_VSYSCALL_NOCACHE)
124#define PAGE_KERNEL_EXEC_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_EXEC_NOCACHE)
125#define PAGE_KERNEL_LARGE MAKE_GLOBAL(__PAGE_KERNEL_LARGE)
126#define PAGE_KERNEL_LARGE_EXEC MAKE_GLOBAL(__PAGE_KERNEL_LARGE_EXEC)
127#define PAGE_KERNEL_VSYSCALL MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL)
128#define PAGE_KERNEL_VSYSCALL_NOCACHE MAKE_GLOBAL(__PAGE_KERNEL_VSYSCALL_NOCACHE)
129 110
130/* xwr */ 111/* xwr */
131#define __P000 PAGE_NONE 112#define __P000 PAGE_NONE
@@ -164,37 +145,37 @@ extern struct list_head pgd_list;
164 */ 145 */
165static inline int pte_dirty(pte_t pte) 146static inline int pte_dirty(pte_t pte)
166{ 147{
167 return pte_val(pte) & _PAGE_DIRTY; 148 return pte_flags(pte) & _PAGE_DIRTY;
168} 149}
169 150
170static inline int pte_young(pte_t pte) 151static inline int pte_young(pte_t pte)
171{ 152{
172 return pte_val(pte) & _PAGE_ACCESSED; 153 return pte_flags(pte) & _PAGE_ACCESSED;
173} 154}
174 155
175static inline int pte_write(pte_t pte) 156static inline int pte_write(pte_t pte)
176{ 157{
177 return pte_val(pte) & _PAGE_RW; 158 return pte_flags(pte) & _PAGE_RW;
178} 159}
179 160
180static inline int pte_file(pte_t pte) 161static inline int pte_file(pte_t pte)
181{ 162{
182 return pte_val(pte) & _PAGE_FILE; 163 return pte_flags(pte) & _PAGE_FILE;
183} 164}
184 165
185static inline int pte_huge(pte_t pte) 166static inline int pte_huge(pte_t pte)
186{ 167{
187 return pte_val(pte) & _PAGE_PSE; 168 return pte_flags(pte) & _PAGE_PSE;
188} 169}
189 170
190static inline int pte_global(pte_t pte) 171static inline int pte_global(pte_t pte)
191{ 172{
192 return pte_val(pte) & _PAGE_GLOBAL; 173 return pte_flags(pte) & _PAGE_GLOBAL;
193} 174}
194 175
195static inline int pte_exec(pte_t pte) 176static inline int pte_exec(pte_t pte)
196{ 177{
197 return !(pte_val(pte) & _PAGE_NX); 178 return !(pte_flags(pte) & _PAGE_NX);
198} 179}
199 180
200static inline int pte_special(pte_t pte) 181static inline int pte_special(pte_t pte)
@@ -210,22 +191,22 @@ static inline int pmd_large(pmd_t pte)
210 191
211static inline pte_t pte_mkclean(pte_t pte) 192static inline pte_t pte_mkclean(pte_t pte)
212{ 193{
213 return __pte(pte_val(pte) & ~(pteval_t)_PAGE_DIRTY); 194 return __pte(pte_val(pte) & ~_PAGE_DIRTY);
214} 195}
215 196
216static inline pte_t pte_mkold(pte_t pte) 197static inline pte_t pte_mkold(pte_t pte)
217{ 198{
218 return __pte(pte_val(pte) & ~(pteval_t)_PAGE_ACCESSED); 199 return __pte(pte_val(pte) & ~_PAGE_ACCESSED);
219} 200}
220 201
221static inline pte_t pte_wrprotect(pte_t pte) 202static inline pte_t pte_wrprotect(pte_t pte)
222{ 203{
223 return __pte(pte_val(pte) & ~(pteval_t)_PAGE_RW); 204 return __pte(pte_val(pte) & ~_PAGE_RW);
224} 205}
225 206
226static inline pte_t pte_mkexec(pte_t pte) 207static inline pte_t pte_mkexec(pte_t pte)
227{ 208{
228 return __pte(pte_val(pte) & ~(pteval_t)_PAGE_NX); 209 return __pte(pte_val(pte) & ~_PAGE_NX);
229} 210}
230 211
231static inline pte_t pte_mkdirty(pte_t pte) 212static inline pte_t pte_mkdirty(pte_t pte)
@@ -250,7 +231,7 @@ static inline pte_t pte_mkhuge(pte_t pte)
250 231
251static inline pte_t pte_clrhuge(pte_t pte) 232static inline pte_t pte_clrhuge(pte_t pte)
252{ 233{
253 return __pte(pte_val(pte) & ~(pteval_t)_PAGE_PSE); 234 return __pte(pte_val(pte) & ~_PAGE_PSE);
254} 235}
255 236
256static inline pte_t pte_mkglobal(pte_t pte) 237static inline pte_t pte_mkglobal(pte_t pte)
@@ -260,7 +241,7 @@ static inline pte_t pte_mkglobal(pte_t pte)
260 241
261static inline pte_t pte_clrglobal(pte_t pte) 242static inline pte_t pte_clrglobal(pte_t pte)
262{ 243{
263 return __pte(pte_val(pte) & ~(pteval_t)_PAGE_GLOBAL); 244 return __pte(pte_val(pte) & ~_PAGE_GLOBAL);
264} 245}
265 246
266static inline pte_t pte_mkspecial(pte_t pte) 247static inline pte_t pte_mkspecial(pte_t pte)
@@ -305,7 +286,7 @@ static inline pgprot_t pgprot_modify(pgprot_t oldprot, pgprot_t newprot)
305 return __pgprot(preservebits | addbits); 286 return __pgprot(preservebits | addbits);
306} 287}
307 288
308#define pte_pgprot(x) __pgprot(pte_val(x) & ~PTE_MASK) 289#define pte_pgprot(x) __pgprot(pte_flags(x) & ~PTE_MASK)
309 290
310#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask) 291#define canon_pgprot(p) __pgprot(pgprot_val(p) & __supported_pte_mask)
311 292
@@ -318,6 +299,9 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
318 unsigned long size, pgprot_t *vma_prot); 299 unsigned long size, pgprot_t *vma_prot);
319#endif 300#endif
320 301
302/* Install a pte for a particular vaddr in kernel space. */
303void set_pte_vaddr(unsigned long vaddr, pte_t pte);
304
321#ifdef CONFIG_PARAVIRT 305#ifdef CONFIG_PARAVIRT
322#include <asm/paravirt.h> 306#include <asm/paravirt.h>
323#else /* !CONFIG_PARAVIRT */ 307#else /* !CONFIG_PARAVIRT */
@@ -359,6 +343,26 @@ int phys_mem_access_prot_allowed(struct file *file, unsigned long pfn,
359# include "pgtable_64.h" 343# include "pgtable_64.h"
360#endif 344#endif
361 345
346/*
347 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
348 *
349 * this macro returns the index of the entry in the pgd page which would
350 * control the given virtual address
351 */
352#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
353
354/*
355 * pgd_offset() returns a (pgd_t *)
356 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
357 */
358#define pgd_offset(mm, address) ((mm)->pgd + pgd_index((address)))
359/*
360 * a shortcut which implies the use of the kernel's pgd, instead
361 * of a process's
362 */
363#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
364
365
362#define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET) 366#define KERNEL_PGD_BOUNDARY pgd_index(PAGE_OFFSET)
363#define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY) 367#define KERNEL_PGD_PTRS (PTRS_PER_PGD - KERNEL_PGD_BOUNDARY)
364 368
@@ -369,8 +373,15 @@ enum {
369 PG_LEVEL_4K, 373 PG_LEVEL_4K,
370 PG_LEVEL_2M, 374 PG_LEVEL_2M,
371 PG_LEVEL_1G, 375 PG_LEVEL_1G,
376 PG_LEVEL_NUM
372}; 377};
373 378
379#ifdef CONFIG_PROC_FS
380extern void update_page_count(int level, unsigned long pages);
381#else
382static inline void update_page_count(int level, unsigned long pages) { }
383#endif
384
374/* 385/*
375 * Helper function that returns the kernel pagetable entry controlling 386 * Helper function that returns the kernel pagetable entry controlling
376 * the virtual address 'address'. NULL means no pagetable entry present. 387 * the virtual address 'address'. NULL means no pagetable entry present.
@@ -420,6 +431,8 @@ static inline void native_set_pte_at(struct mm_struct *mm, unsigned long addr,
420 * race with other CPU's that might be updating the dirty 431 * race with other CPU's that might be updating the dirty
421 * bit at the same time. 432 * bit at the same time.
422 */ 433 */
434struct vm_area_struct;
435
423#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS 436#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
424extern int ptep_set_access_flags(struct vm_area_struct *vma, 437extern int ptep_set_access_flags(struct vm_area_struct *vma,
425 unsigned long address, pte_t *ptep, 438 unsigned long address, pte_t *ptep,
diff --git a/include/asm-x86/pgtable_32.h b/include/asm-x86/pgtable_32.h
index 32ca03109a4c..ec871c420d7e 100644
--- a/include/asm-x86/pgtable_32.h
+++ b/include/asm-x86/pgtable_32.h
@@ -113,26 +113,6 @@ extern unsigned long pg0[];
113 */ 113 */
114#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) 114#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot))
115 115
116/*
117 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
118 *
119 * this macro returns the index of the entry in the pgd page which would
120 * control the given virtual address
121 */
122#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
123#define pgd_index_k(addr) pgd_index((addr))
124
125/*
126 * pgd_offset() returns a (pgd_t *)
127 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
128 */
129#define pgd_offset(mm, address) ((mm)->pgd + pgd_index((address)))
130
131/*
132 * a shortcut which implies the use of the kernel's pgd, instead
133 * of a process's
134 */
135#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
136 116
137static inline int pud_large(pud_t pud) { return 0; } 117static inline int pud_large(pud_t pud) { return 0; }
138 118
diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
index 1cc50d22d735..fa7208b483ca 100644
--- a/include/asm-x86/pgtable_64.h
+++ b/include/asm-x86/pgtable_64.h
@@ -70,6 +70,9 @@ extern void paging_init(void);
70 70
71struct mm_struct; 71struct mm_struct;
72 72
73void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte);
74
75
73static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr, 76static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
74 pte_t *ptep) 77 pte_t *ptep)
75{ 78{
@@ -190,12 +193,9 @@ static inline int pmd_bad(pmd_t pmd)
190#define pgd_page_vaddr(pgd) \ 193#define pgd_page_vaddr(pgd) \
191 ((unsigned long)__va((unsigned long)pgd_val((pgd)) & PTE_MASK)) 194 ((unsigned long)__va((unsigned long)pgd_val((pgd)) & PTE_MASK))
192#define pgd_page(pgd) (pfn_to_page(pgd_val((pgd)) >> PAGE_SHIFT)) 195#define pgd_page(pgd) (pfn_to_page(pgd_val((pgd)) >> PAGE_SHIFT))
193#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1))
194#define pgd_offset(mm, address) ((mm)->pgd + pgd_index((address)))
195#define pgd_offset_k(address) (init_level4_pgt + pgd_index((address)))
196#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT) 196#define pgd_present(pgd) (pgd_val(pgd) & _PAGE_PRESENT)
197static inline int pgd_large(pgd_t pgd) { return 0; } 197static inline int pgd_large(pgd_t pgd) { return 0; }
198#define mk_kernel_pgd(address) ((pgd_t){ (address) | _KERNPG_TABLE }) 198#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
199 199
200/* PUD - Level3 access */ 200/* PUD - Level3 access */
201/* to find an entry in a page-table-directory. */ 201/* to find an entry in a page-table-directory. */
diff --git a/include/asm-x86/processor-flags.h b/include/asm-x86/processor-flags.h
index 199cab107d85..092b39b3a7e6 100644
--- a/include/asm-x86/processor-flags.h
+++ b/include/asm-x86/processor-flags.h
@@ -88,4 +88,10 @@
88#define CX86_ARR_BASE 0xc4 88#define CX86_ARR_BASE 0xc4
89#define CX86_RCR_BASE 0xdc 89#define CX86_RCR_BASE 0xdc
90 90
91#ifdef CONFIG_VM86
92#define X86_VM_MASK X86_EFLAGS_VM
93#else
94#define X86_VM_MASK 0 /* No VM86 support */
95#endif
96
91#endif /* __ASM_I386_PROCESSOR_FLAGS_H */ 97#endif /* __ASM_I386_PROCESSOR_FLAGS_H */
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 559105220a47..7f7382704592 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -153,7 +153,7 @@ static inline int hlt_works(int cpu)
153 153
154extern void cpu_detect(struct cpuinfo_x86 *c); 154extern void cpu_detect(struct cpuinfo_x86 *c);
155 155
156extern void identify_cpu(struct cpuinfo_x86 *); 156extern void early_cpu_init(void);
157extern void identify_boot_cpu(void); 157extern void identify_boot_cpu(void);
158extern void identify_secondary_cpu(struct cpuinfo_x86 *); 158extern void identify_secondary_cpu(struct cpuinfo_x86 *);
159extern void print_cpu_info(struct cpuinfo_x86 *); 159extern void print_cpu_info(struct cpuinfo_x86 *);
@@ -263,15 +263,11 @@ struct tss_struct {
263 struct thread_struct *io_bitmap_owner; 263 struct thread_struct *io_bitmap_owner;
264 264
265 /* 265 /*
266 * Pad the TSS to be cacheline-aligned (size is 0x100):
267 */
268 unsigned long __cacheline_filler[35];
269 /*
270 * .. and then another 0x100 bytes for the emergency kernel stack: 266 * .. and then another 0x100 bytes for the emergency kernel stack:
271 */ 267 */
272 unsigned long stack[64]; 268 unsigned long stack[64];
273 269
274} __attribute__((packed)); 270} ____cacheline_aligned;
275 271
276DECLARE_PER_CPU(struct tss_struct, init_tss); 272DECLARE_PER_CPU(struct tss_struct, init_tss);
277 273
@@ -535,7 +531,6 @@ static inline void load_sp0(struct tss_struct *tss,
535} 531}
536 532
537#define set_iopl_mask native_set_iopl_mask 533#define set_iopl_mask native_set_iopl_mask
538#define SWAPGS swapgs
539#endif /* CONFIG_PARAVIRT */ 534#endif /* CONFIG_PARAVIRT */
540 535
541/* 536/*
diff --git a/include/asm-x86/proto.h b/include/asm-x86/proto.h
index 6c8b41b03f6d..3dd458c385c0 100644
--- a/include/asm-x86/proto.h
+++ b/include/asm-x86/proto.h
@@ -14,8 +14,6 @@ extern void ia32_syscall(void);
14extern void ia32_cstar_target(void); 14extern void ia32_cstar_target(void);
15extern void ia32_sysenter_target(void); 15extern void ia32_sysenter_target(void);
16 16
17extern void reserve_bootmem_generic(unsigned long phys, unsigned len);
18
19extern void syscall32_cpu_init(void); 17extern void syscall32_cpu_init(void);
20 18
21extern void check_efer(void); 19extern void check_efer(void);
diff --git a/include/asm-x86/ptrace.h b/include/asm-x86/ptrace.h
index 9f922b0b95d6..8a71db803da6 100644
--- a/include/asm-x86/ptrace.h
+++ b/include/asm-x86/ptrace.h
@@ -3,7 +3,12 @@
3 3
4#include <linux/compiler.h> /* For __user */ 4#include <linux/compiler.h> /* For __user */
5#include <asm/ptrace-abi.h> 5#include <asm/ptrace-abi.h>
6#include <asm/processor-flags.h>
6 7
8#ifdef __KERNEL__
9#include <asm/ds.h> /* the DS BTS struct is used for ptrace too */
10#include <asm/segment.h>
11#endif
7 12
8#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
9 14
@@ -55,9 +60,6 @@ struct pt_regs {
55 unsigned long ss; 60 unsigned long ss;
56}; 61};
57 62
58#include <asm/vm86.h>
59#include <asm/segment.h>
60
61#endif /* __KERNEL__ */ 63#endif /* __KERNEL__ */
62 64
63#else /* __i386__ */ 65#else /* __i386__ */
diff --git a/include/asm-x86/reboot.h b/include/asm-x86/reboot.h
index e63741f19392..206f355786dc 100644
--- a/include/asm-x86/reboot.h
+++ b/include/asm-x86/reboot.h
@@ -14,8 +14,8 @@ struct machine_ops {
14 14
15extern struct machine_ops machine_ops; 15extern struct machine_ops machine_ops;
16 16
17void machine_real_restart(unsigned char *code, int length);
18void native_machine_crash_shutdown(struct pt_regs *regs); 17void native_machine_crash_shutdown(struct pt_regs *regs);
19void native_machine_shutdown(void); 18void native_machine_shutdown(void);
19void machine_real_restart(const unsigned char *code, int length);
20 20
21#endif /* _ASM_REBOOT_H */ 21#endif /* _ASM_REBOOT_H */
diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h
index 7400d3ad75c6..adec887dd7cd 100644
--- a/include/asm-x86/required-features.h
+++ b/include/asm-x86/required-features.h
@@ -19,9 +19,13 @@
19 19
20#if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64) 20#if defined(CONFIG_X86_PAE) || defined(CONFIG_X86_64)
21# define NEED_PAE (1<<(X86_FEATURE_PAE & 31)) 21# define NEED_PAE (1<<(X86_FEATURE_PAE & 31))
22# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31))
23#else 22#else
24# define NEED_PAE 0 23# define NEED_PAE 0
24#endif
25
26#ifdef CONFIG_X86_CMPXCHG64
27# define NEED_CX8 (1<<(X86_FEATURE_CX8 & 31))
28#else
25# define NEED_CX8 0 29# define NEED_CX8 0
26#endif 30#endif
27 31
@@ -38,7 +42,7 @@
38#endif 42#endif
39 43
40#ifdef CONFIG_X86_64 44#ifdef CONFIG_X86_64
41#define NEED_PSE (1<<(X86_FEATURE_PSE & 31)) 45#define NEED_PSE 0
42#define NEED_MSR (1<<(X86_FEATURE_MSR & 31)) 46#define NEED_MSR (1<<(X86_FEATURE_MSR & 31))
43#define NEED_PGE (1<<(X86_FEATURE_PGE & 31)) 47#define NEED_PGE (1<<(X86_FEATURE_PGE & 31))
44#define NEED_FXSR (1<<(X86_FEATURE_FXSR & 31)) 48#define NEED_FXSR (1<<(X86_FEATURE_FXSR & 31))
diff --git a/include/asm-x86/resume-trace.h b/include/asm-x86/resume-trace.h
index 2557514d7ef6..8d9f0b41ee86 100644
--- a/include/asm-x86/resume-trace.h
+++ b/include/asm-x86/resume-trace.h
@@ -6,7 +6,7 @@
6#define TRACE_RESUME(user) \ 6#define TRACE_RESUME(user) \
7do { \ 7do { \
8 if (pm_trace_enabled) { \ 8 if (pm_trace_enabled) { \
9 void *tracedata; \ 9 const void *tracedata; \
10 asm volatile(_ASM_MOV_UL " $1f,%0\n" \ 10 asm volatile(_ASM_MOV_UL " $1f,%0\n" \
11 ".section .tracedata,\"a\"\n" \ 11 ".section .tracedata,\"a\"\n" \
12 "1:\t.word %c1\n\t" \ 12 "1:\t.word %c1\n\t" \
diff --git a/include/asm-x86/seccomp_32.h b/include/asm-x86/seccomp_32.h
index 18da19e89bff..36e71c5f306f 100644
--- a/include/asm-x86/seccomp_32.h
+++ b/include/asm-x86/seccomp_32.h
@@ -1,4 +1,5 @@
1#ifndef _ASM_SECCOMP_H 1#ifndef _ASM_SECCOMP_H
2#define _ASM_SECCOMP_H
2 3
3#include <linux/thread_info.h> 4#include <linux/thread_info.h>
4 5
diff --git a/include/asm-x86/seccomp_64.h b/include/asm-x86/seccomp_64.h
index 553af65a2287..76cfe69aa63c 100644
--- a/include/asm-x86/seccomp_64.h
+++ b/include/asm-x86/seccomp_64.h
@@ -1,4 +1,5 @@
1#ifndef _ASM_SECCOMP_H 1#ifndef _ASM_SECCOMP_H
2#define _ASM_SECCOMP_H
2 3
3#include <linux/thread_info.h> 4#include <linux/thread_info.h>
4 5
diff --git a/include/asm-x86/segment.h b/include/asm-x86/segment.h
index ed5131dd7d92..dfc8601c0892 100644
--- a/include/asm-x86/segment.h
+++ b/include/asm-x86/segment.h
@@ -61,18 +61,14 @@
61#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1) 61#define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
62 62
63#define GDT_ENTRY_DEFAULT_USER_CS 14 63#define GDT_ENTRY_DEFAULT_USER_CS 14
64#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS * 8 + 3)
65 64
66#define GDT_ENTRY_DEFAULT_USER_DS 15 65#define GDT_ENTRY_DEFAULT_USER_DS 15
67#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS * 8 + 3)
68 66
69#define GDT_ENTRY_KERNEL_BASE 12 67#define GDT_ENTRY_KERNEL_BASE 12
70 68
71#define GDT_ENTRY_KERNEL_CS (GDT_ENTRY_KERNEL_BASE + 0) 69#define GDT_ENTRY_KERNEL_CS (GDT_ENTRY_KERNEL_BASE + 0)
72#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS * 8)
73 70
74#define GDT_ENTRY_KERNEL_DS (GDT_ENTRY_KERNEL_BASE + 1) 71#define GDT_ENTRY_KERNEL_DS (GDT_ENTRY_KERNEL_BASE + 1)
75#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS * 8)
76 72
77#define GDT_ENTRY_TSS (GDT_ENTRY_KERNEL_BASE + 4) 73#define GDT_ENTRY_TSS (GDT_ENTRY_KERNEL_BASE + 4)
78#define GDT_ENTRY_LDT (GDT_ENTRY_KERNEL_BASE + 5) 74#define GDT_ENTRY_LDT (GDT_ENTRY_KERNEL_BASE + 5)
@@ -139,10 +135,11 @@
139#else 135#else
140#include <asm/cache.h> 136#include <asm/cache.h>
141 137
142#define __KERNEL_CS 0x10 138#define GDT_ENTRY_KERNEL32_CS 1
143#define __KERNEL_DS 0x18 139#define GDT_ENTRY_KERNEL_CS 2
140#define GDT_ENTRY_KERNEL_DS 3
144 141
145#define __KERNEL32_CS 0x08 142#define __KERNEL32_CS (GDT_ENTRY_KERNEL32_CS * 8)
146 143
147/* 144/*
148 * we cannot use the same code segment descriptor for user and kernel 145 * we cannot use the same code segment descriptor for user and kernel
@@ -150,10 +147,10 @@
150 * The segment offset needs to contain a RPL. Grr. -AK 147 * The segment offset needs to contain a RPL. Grr. -AK
151 * GDT layout to get 64bit syscall right (sysret hardcodes gdt offsets) 148 * GDT layout to get 64bit syscall right (sysret hardcodes gdt offsets)
152 */ 149 */
153 150#define GDT_ENTRY_DEFAULT_USER32_CS 4
154#define __USER32_CS 0x23 /* 4*8+3 */ 151#define GDT_ENTRY_DEFAULT_USER_DS 5
155#define __USER_DS 0x2b /* 5*8+3 */ 152#define GDT_ENTRY_DEFAULT_USER_CS 6
156#define __USER_CS 0x33 /* 6*8+3 */ 153#define __USER32_CS (GDT_ENTRY_DEFAULT_USER32_CS * 8 + 3)
157#define __USER32_DS __USER_DS 154#define __USER32_DS __USER_DS
158 155
159#define GDT_ENTRY_TSS 8 /* needs two entries */ 156#define GDT_ENTRY_TSS 8 /* needs two entries */
@@ -175,6 +172,10 @@
175 172
176#endif 173#endif
177 174
175#define __KERNEL_CS (GDT_ENTRY_KERNEL_CS * 8)
176#define __KERNEL_DS (GDT_ENTRY_KERNEL_DS * 8)
177#define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS* 8 + 3)
178#define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS* 8 + 3)
178#ifndef CONFIG_PARAVIRT 179#ifndef CONFIG_PARAVIRT
179#define get_kernel_rpl() 0 180#define get_kernel_rpl() 0
180#endif 181#endif
diff --git a/include/asm-x86/setup.h b/include/asm-x86/setup.h
index fa6763af8d26..90ab2225e71b 100644
--- a/include/asm-x86/setup.h
+++ b/include/asm-x86/setup.h
@@ -8,7 +8,25 @@
8/* Interrupt control for vSMPowered x86_64 systems */ 8/* Interrupt control for vSMPowered x86_64 systems */
9void vsmp_init(void); 9void vsmp_init(void);
10 10
11char *machine_specific_memory_setup(void); 11#ifdef CONFIG_X86_VISWS
12extern void visws_early_detect(void);
13extern int is_visws_box(void);
14#else
15static inline void visws_early_detect(void) { }
16static inline int is_visws_box(void) { return 0; }
17#endif
18
19/*
20 * Any setup quirks to be performed?
21 */
22extern int (*arch_time_init_quirk)(void);
23extern int (*arch_pre_intr_init_quirk)(void);
24extern int (*arch_intr_init_quirk)(void);
25extern int (*arch_trap_init_quirk)(void);
26extern char * (*arch_memory_setup_quirk)(void);
27extern int (*mach_get_smp_config_quirk)(unsigned int early);
28extern int (*mach_find_smp_config_quirk)(unsigned int reserve);
29
12#ifndef CONFIG_PARAVIRT 30#ifndef CONFIG_PARAVIRT
13#define paravirt_post_allocator_init() do {} while (0) 31#define paravirt_post_allocator_init() do {} while (0)
14#endif 32#endif
@@ -43,26 +61,23 @@ char *machine_specific_memory_setup(void);
43 */ 61 */
44extern struct boot_params boot_params; 62extern struct boot_params boot_params;
45 63
46#ifdef __i386__
47/* 64/*
48 * Do NOT EVER look at the BIOS memory size location. 65 * Do NOT EVER look at the BIOS memory size location.
49 * It does not work on many machines. 66 * It does not work on many machines.
50 */ 67 */
51#define LOWMEMSIZE() (0x9f000) 68#define LOWMEMSIZE() (0x9f000)
52 69
53struct e820entry; 70#ifdef __i386__
54
55char * __init machine_specific_memory_setup(void);
56char *memory_setup(void);
57 71
58int __init copy_e820_map(struct e820entry *biosmap, int nr_map); 72void __init i386_start_kernel(void);
59int __init sanitize_e820_map(struct e820entry *biosmap, char *pnr_map); 73extern void probe_roms(void);
60void __init add_memory_region(unsigned long long start,
61 unsigned long long size, int type);
62 74
75extern unsigned long init_pg_tables_start;
63extern unsigned long init_pg_tables_end; 76extern unsigned long init_pg_tables_end;
64 77
65 78#else
79void __init x86_64_start_kernel(char *real_mode);
80void __init x86_64_start_reservations(char *real_mode_data);
66 81
67#endif /* __i386__ */ 82#endif /* __i386__ */
68#endif /* _SETUP */ 83#endif /* _SETUP */
diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
index 1ebaa5cd3112..c2784b3e0b77 100644
--- a/include/asm-x86/smp.h
+++ b/include/asm-x86/smp.h
@@ -29,21 +29,12 @@ extern int smp_num_siblings;
29extern unsigned int num_processors; 29extern unsigned int num_processors;
30extern cpumask_t cpu_initialized; 30extern cpumask_t cpu_initialized;
31 31
32#ifdef CONFIG_SMP
33extern u16 x86_cpu_to_apicid_init[];
34extern u16 x86_bios_cpu_apicid_init[];
35extern void *x86_cpu_to_apicid_early_ptr;
36extern void *x86_bios_cpu_apicid_early_ptr;
37#else
38#define x86_cpu_to_apicid_early_ptr NULL
39#define x86_bios_cpu_apicid_early_ptr NULL
40#endif
41
42DECLARE_PER_CPU(cpumask_t, cpu_sibling_map); 32DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
43DECLARE_PER_CPU(cpumask_t, cpu_core_map); 33DECLARE_PER_CPU(cpumask_t, cpu_core_map);
44DECLARE_PER_CPU(u16, cpu_llc_id); 34DECLARE_PER_CPU(u16, cpu_llc_id);
45DECLARE_PER_CPU(u16, x86_cpu_to_apicid); 35
46DECLARE_PER_CPU(u16, x86_bios_cpu_apicid); 36DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid);
37DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
47 38
48/* Static state in head.S used to set up a CPU */ 39/* Static state in head.S used to set up a CPU */
49extern struct { 40extern struct {
@@ -59,9 +50,9 @@ struct smp_ops {
59 50
60 void (*smp_send_stop)(void); 51 void (*smp_send_stop)(void);
61 void (*smp_send_reschedule)(int cpu); 52 void (*smp_send_reschedule)(int cpu);
62 int (*smp_call_function_mask)(cpumask_t mask, 53
63 void (*func)(void *info), void *info, 54 void (*send_call_func_ipi)(cpumask_t mask);
64 int wait); 55 void (*send_call_func_single_ipi)(int cpu);
65}; 56};
66 57
67/* Globals due to paravirt */ 58/* Globals due to paravirt */
@@ -103,23 +94,26 @@ static inline void smp_send_reschedule(int cpu)
103 smp_ops.smp_send_reschedule(cpu); 94 smp_ops.smp_send_reschedule(cpu);
104} 95}
105 96
106static inline int smp_call_function_mask(cpumask_t mask, 97static inline void arch_send_call_function_single_ipi(int cpu)
107 void (*func) (void *info), void *info, 98{
108 int wait) 99 smp_ops.send_call_func_single_ipi(cpu);
100}
101
102static inline void arch_send_call_function_ipi(cpumask_t mask)
109{ 103{
110 return smp_ops.smp_call_function_mask(mask, func, info, wait); 104 smp_ops.send_call_func_ipi(mask);
111} 105}
112 106
113void native_smp_prepare_boot_cpu(void); 107void native_smp_prepare_boot_cpu(void);
114void native_smp_prepare_cpus(unsigned int max_cpus); 108void native_smp_prepare_cpus(unsigned int max_cpus);
115void native_smp_cpus_done(unsigned int max_cpus); 109void native_smp_cpus_done(unsigned int max_cpus);
116int native_cpu_up(unsigned int cpunum); 110int native_cpu_up(unsigned int cpunum);
111void native_send_call_func_ipi(cpumask_t mask);
112void native_send_call_func_single_ipi(int cpu);
117 113
118extern int __cpu_disable(void); 114extern int __cpu_disable(void);
119extern void __cpu_die(unsigned int cpu); 115extern void __cpu_die(unsigned int cpu);
120 116
121extern void prefill_possible_map(void);
122
123void smp_store_cpu_info(int id); 117void smp_store_cpu_info(int id);
124#define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu) 118#define cpu_physical_id(cpu) per_cpu(x86_cpu_to_apicid, cpu)
125 119
@@ -130,6 +124,14 @@ static inline int num_booting_cpus(void)
130} 124}
131#endif /* CONFIG_SMP */ 125#endif /* CONFIG_SMP */
132 126
127#if defined(CONFIG_SMP) && defined(CONFIG_HOTPLUG_CPU)
128extern void prefill_possible_map(void);
129#else
130static inline void prefill_possible_map(void)
131{
132}
133#endif
134
133extern unsigned disabled_cpus __cpuinitdata; 135extern unsigned disabled_cpus __cpuinitdata;
134 136
135#ifdef CONFIG_X86_32_SMP 137#ifdef CONFIG_X86_32_SMP
@@ -197,12 +199,8 @@ static inline int hard_smp_processor_id(void)
197#endif /* CONFIG_X86_LOCAL_APIC */ 199#endif /* CONFIG_X86_LOCAL_APIC */
198 200
199#ifdef CONFIG_HOTPLUG_CPU 201#ifdef CONFIG_HOTPLUG_CPU
200extern void cpu_exit_clear(void);
201extern void cpu_uninit(void); 202extern void cpu_uninit(void);
202#endif 203#endif
203 204
204extern void smp_alloc_memory(void);
205extern void lock_ipi_call_lock(void);
206extern void unlock_ipi_call_lock(void);
207#endif /* __ASSEMBLY__ */ 205#endif /* __ASSEMBLY__ */
208#endif 206#endif
diff --git a/include/asm-x86/srat.h b/include/asm-x86/srat.h
index f4bba131d068..774c919dc232 100644
--- a/include/asm-x86/srat.h
+++ b/include/asm-x86/srat.h
@@ -27,11 +27,13 @@
27#ifndef _ASM_SRAT_H_ 27#ifndef _ASM_SRAT_H_
28#define _ASM_SRAT_H_ 28#define _ASM_SRAT_H_
29 29
30#ifndef CONFIG_ACPI_SRAT 30#ifdef CONFIG_ACPI_NUMA
31#error CONFIG_ACPI_SRAT not defined, and srat.h header has been included
32#endif
33
34extern int get_memcfg_from_srat(void); 31extern int get_memcfg_from_srat(void);
35extern unsigned long *get_zholes_size(int); 32#else
33static inline int get_memcfg_from_srat(void)
34{
35 return 0;
36}
37#endif
36 38
37#endif /* _ASM_SRAT_H_ */ 39#endif /* _ASM_SRAT_H_ */
diff --git a/include/asm-x86/string_32.h b/include/asm-x86/string_32.h
index b49369ad9a61..193578cd1fd9 100644
--- a/include/asm-x86/string_32.h
+++ b/include/asm-x86/string_32.h
@@ -29,81 +29,116 @@ extern char *strchr(const char *s, int c);
29#define __HAVE_ARCH_STRLEN 29#define __HAVE_ARCH_STRLEN
30extern size_t strlen(const char *s); 30extern size_t strlen(const char *s);
31 31
32static __always_inline void * __memcpy(void * to, const void * from, size_t n) 32static __always_inline void *__memcpy(void *to, const void *from, size_t n)
33{ 33{
34int d0, d1, d2; 34 int d0, d1, d2;
35__asm__ __volatile__( 35 asm volatile("rep ; movsl\n\t"
36 "rep ; movsl\n\t" 36 "movl %4,%%ecx\n\t"
37 "movl %4,%%ecx\n\t" 37 "andl $3,%%ecx\n\t"
38 "andl $3,%%ecx\n\t" 38 "jz 1f\n\t"
39 "jz 1f\n\t" 39 "rep ; movsb\n\t"
40 "rep ; movsb\n\t" 40 "1:"
41 "1:" 41 : "=&c" (d0), "=&D" (d1), "=&S" (d2)
42 : "=&c" (d0), "=&D" (d1), "=&S" (d2) 42 : "0" (n / 4), "g" (n), "1" ((long)to), "2" ((long)from)
43 : "0" (n/4), "g" (n), "1" ((long) to), "2" ((long) from) 43 : "memory");
44 : "memory"); 44 return to;
45return (to);
46} 45}
47 46
48/* 47/*
49 * This looks ugly, but the compiler can optimize it totally, 48 * This looks ugly, but the compiler can optimize it totally,
50 * as the count is constant. 49 * as the count is constant.
51 */ 50 */
52static __always_inline void * __constant_memcpy(void * to, const void * from, size_t n) 51static __always_inline void *__constant_memcpy(void *to, const void *from,
52 size_t n)
53{ 53{
54 long esi, edi; 54 long esi, edi;
55 if (!n) return to; 55 if (!n)
56#if 1 /* want to do small copies with non-string ops? */ 56 return to;
57
57 switch (n) { 58 switch (n) {
58 case 1: *(char*)to = *(char*)from; return to; 59 case 1:
59 case 2: *(short*)to = *(short*)from; return to; 60 *(char *)to = *(char *)from;
60 case 4: *(int*)to = *(int*)from; return to; 61 return to;
61#if 1 /* including those doable with two moves? */ 62 case 2:
62 case 3: *(short*)to = *(short*)from; 63 *(short *)to = *(short *)from;
63 *((char*)to+2) = *((char*)from+2); return to; 64 return to;
64 case 5: *(int*)to = *(int*)from; 65 case 4:
65 *((char*)to+4) = *((char*)from+4); return to; 66 *(int *)to = *(int *)from;
66 case 6: *(int*)to = *(int*)from; 67 return to;
67 *((short*)to+2) = *((short*)from+2); return to; 68
68 case 8: *(int*)to = *(int*)from; 69 case 3:
69 *((int*)to+1) = *((int*)from+1); return to; 70 *(short *)to = *(short *)from;
70#endif 71 *((char *)to + 2) = *((char *)from + 2);
72 return to;
73 case 5:
74 *(int *)to = *(int *)from;
75 *((char *)to + 4) = *((char *)from + 4);
76 return to;
77 case 6:
78 *(int *)to = *(int *)from;
79 *((short *)to + 2) = *((short *)from + 2);
80 return to;
81 case 8:
82 *(int *)to = *(int *)from;
83 *((int *)to + 1) = *((int *)from + 1);
84 return to;
71 } 85 }
72#endif 86
73 esi = (long) from; 87 esi = (long)from;
74 edi = (long) to; 88 edi = (long)to;
75 if (n >= 5*4) { 89 if (n >= 5 * 4) {
76 /* large block: use rep prefix */ 90 /* large block: use rep prefix */
77 int ecx; 91 int ecx;
78 __asm__ __volatile__( 92 asm volatile("rep ; movsl"
79 "rep ; movsl" 93 : "=&c" (ecx), "=&D" (edi), "=&S" (esi)
80 : "=&c" (ecx), "=&D" (edi), "=&S" (esi) 94 : "0" (n / 4), "1" (edi), "2" (esi)
81 : "0" (n/4), "1" (edi),"2" (esi) 95 : "memory"
82 : "memory"
83 ); 96 );
84 } else { 97 } else {
85 /* small block: don't clobber ecx + smaller code */ 98 /* small block: don't clobber ecx + smaller code */
86 if (n >= 4*4) __asm__ __volatile__("movsl" 99 if (n >= 4 * 4)
87 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 100 asm volatile("movsl"
88 if (n >= 3*4) __asm__ __volatile__("movsl" 101 : "=&D"(edi), "=&S"(esi)
89 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 102 : "0"(edi), "1"(esi)
90 if (n >= 2*4) __asm__ __volatile__("movsl" 103 : "memory");
91 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 104 if (n >= 3 * 4)
92 if (n >= 1*4) __asm__ __volatile__("movsl" 105 asm volatile("movsl"
93 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 106 : "=&D"(edi), "=&S"(esi)
107 : "0"(edi), "1"(esi)
108 : "memory");
109 if (n >= 2 * 4)
110 asm volatile("movsl"
111 : "=&D"(edi), "=&S"(esi)
112 : "0"(edi), "1"(esi)
113 : "memory");
114 if (n >= 1 * 4)
115 asm volatile("movsl"
116 : "=&D"(edi), "=&S"(esi)
117 : "0"(edi), "1"(esi)
118 : "memory");
94 } 119 }
95 switch (n % 4) { 120 switch (n % 4) {
96 /* tail */ 121 /* tail */
97 case 0: return to; 122 case 0:
98 case 1: __asm__ __volatile__("movsb" 123 return to;
99 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 124 case 1:
100 return to; 125 asm volatile("movsb"
101 case 2: __asm__ __volatile__("movsw" 126 : "=&D"(edi), "=&S"(esi)
102 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 127 : "0"(edi), "1"(esi)
103 return to; 128 : "memory");
104 default: __asm__ __volatile__("movsw\n\tmovsb" 129 return to;
105 :"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory"); 130 case 2:
106 return to; 131 asm volatile("movsw"
132 : "=&D"(edi), "=&S"(esi)
133 : "0"(edi), "1"(esi)
134 : "memory");
135 return to;
136 default:
137 asm volatile("movsw\n\tmovsb"
138 : "=&D"(edi), "=&S"(esi)
139 : "0"(edi), "1"(esi)
140 : "memory");
141 return to;
107 } 142 }
108} 143}
109 144
@@ -117,87 +152,86 @@ static __always_inline void * __constant_memcpy(void * to, const void * from, si
117 * This CPU favours 3DNow strongly (eg AMD Athlon) 152 * This CPU favours 3DNow strongly (eg AMD Athlon)
118 */ 153 */
119 154
120static inline void * __constant_memcpy3d(void * to, const void * from, size_t len) 155static inline void *__constant_memcpy3d(void *to, const void *from, size_t len)
121{ 156{
122 if (len < 512) 157 if (len < 512)
123 return __constant_memcpy(to, from, len); 158 return __constant_memcpy(to, from, len);
124 return _mmx_memcpy(to, from, len); 159 return _mmx_memcpy(to, from, len);
125} 160}
126 161
127static __inline__ void *__memcpy3d(void *to, const void *from, size_t len) 162static inline void *__memcpy3d(void *to, const void *from, size_t len)
128{ 163{
129 if (len < 512) 164 if (len < 512)
130 return __memcpy(to, from, len); 165 return __memcpy(to, from, len);
131 return _mmx_memcpy(to, from, len); 166 return _mmx_memcpy(to, from, len);
132} 167}
133 168
134#define memcpy(t, f, n) \ 169#define memcpy(t, f, n) \
135(__builtin_constant_p(n) ? \ 170 (__builtin_constant_p((n)) \
136 __constant_memcpy3d((t),(f),(n)) : \ 171 ? __constant_memcpy3d((t), (f), (n)) \
137 __memcpy3d((t),(f),(n))) 172 : __memcpy3d((t), (f), (n)))
138 173
139#else 174#else
140 175
141/* 176/*
142 * No 3D Now! 177 * No 3D Now!
143 */ 178 */
144 179
145#define memcpy(t, f, n) \ 180#define memcpy(t, f, n) \
146(__builtin_constant_p(n) ? \ 181 (__builtin_constant_p((n)) \
147 __constant_memcpy((t),(f),(n)) : \ 182 ? __constant_memcpy((t), (f), (n)) \
148 __memcpy((t),(f),(n))) 183 : __memcpy((t), (f), (n)))
149 184
150#endif 185#endif
151 186
152#define __HAVE_ARCH_MEMMOVE 187#define __HAVE_ARCH_MEMMOVE
153void *memmove(void * dest,const void * src, size_t n); 188void *memmove(void *dest, const void *src, size_t n);
154 189
155#define memcmp __builtin_memcmp 190#define memcmp __builtin_memcmp
156 191
157#define __HAVE_ARCH_MEMCHR 192#define __HAVE_ARCH_MEMCHR
158extern void *memchr(const void * cs,int c,size_t count); 193extern void *memchr(const void *cs, int c, size_t count);
159 194
160static inline void * __memset_generic(void * s, char c,size_t count) 195static inline void *__memset_generic(void *s, char c, size_t count)
161{ 196{
162int d0, d1; 197 int d0, d1;
163__asm__ __volatile__( 198 asm volatile("rep\n\t"
164 "rep\n\t" 199 "stosb"
165 "stosb" 200 : "=&c" (d0), "=&D" (d1)
166 : "=&c" (d0), "=&D" (d1) 201 : "a" (c), "1" (s), "0" (count)
167 :"a" (c),"1" (s),"0" (count) 202 : "memory");
168 :"memory"); 203 return s;
169return s;
170} 204}
171 205
172/* we might want to write optimized versions of these later */ 206/* we might want to write optimized versions of these later */
173#define __constant_count_memset(s,c,count) __memset_generic((s),(c),(count)) 207#define __constant_count_memset(s, c, count) __memset_generic((s), (c), (count))
174 208
175/* 209/*
176 * memset(x,0,y) is a reasonably common thing to do, so we want to fill 210 * memset(x, 0, y) is a reasonably common thing to do, so we want to fill
177 * things 32 bits at a time even when we don't know the size of the 211 * things 32 bits at a time even when we don't know the size of the
178 * area at compile-time.. 212 * area at compile-time..
179 */ 213 */
180static __always_inline void * __constant_c_memset(void * s, unsigned long c, size_t count) 214static __always_inline
215void *__constant_c_memset(void *s, unsigned long c, size_t count)
181{ 216{
182int d0, d1; 217 int d0, d1;
183__asm__ __volatile__( 218 asm volatile("rep ; stosl\n\t"
184 "rep ; stosl\n\t" 219 "testb $2,%b3\n\t"
185 "testb $2,%b3\n\t" 220 "je 1f\n\t"
186 "je 1f\n\t" 221 "stosw\n"
187 "stosw\n" 222 "1:\ttestb $1,%b3\n\t"
188 "1:\ttestb $1,%b3\n\t" 223 "je 2f\n\t"
189 "je 2f\n\t" 224 "stosb\n"
190 "stosb\n" 225 "2:"
191 "2:" 226 : "=&c" (d0), "=&D" (d1)
192 :"=&c" (d0), "=&D" (d1) 227 : "a" (c), "q" (count), "0" (count/4), "1" ((long)s)
193 :"a" (c), "q" (count), "0" (count/4), "1" ((long) s) 228 : "memory");
194 :"memory"); 229 return s;
195return (s);
196} 230}
197 231
198/* Added by Gertjan van Wingerde to make minix and sysv module work */ 232/* Added by Gertjan van Wingerde to make minix and sysv module work */
199#define __HAVE_ARCH_STRNLEN 233#define __HAVE_ARCH_STRNLEN
200extern size_t strnlen(const char * s, size_t count); 234extern size_t strnlen(const char *s, size_t count);
201/* end of additional stuff */ 235/* end of additional stuff */
202 236
203#define __HAVE_ARCH_STRSTR 237#define __HAVE_ARCH_STRSTR
@@ -207,66 +241,85 @@ extern char *strstr(const char *cs, const char *ct);
207 * This looks horribly ugly, but the compiler can optimize it totally, 241 * This looks horribly ugly, but the compiler can optimize it totally,
208 * as we by now know that both pattern and count is constant.. 242 * as we by now know that both pattern and count is constant..
209 */ 243 */
210static __always_inline void * __constant_c_and_count_memset(void * s, unsigned long pattern, size_t count) 244static __always_inline
245void *__constant_c_and_count_memset(void *s, unsigned long pattern,
246 size_t count)
211{ 247{
212 switch (count) { 248 switch (count) {
249 case 0:
250 return s;
251 case 1:
252 *(unsigned char *)s = pattern & 0xff;
253 return s;
254 case 2:
255 *(unsigned short *)s = pattern & 0xffff;
256 return s;
257 case 3:
258 *(unsigned short *)s = pattern & 0xffff;
259 *((unsigned char *)s + 2) = pattern & 0xff;
260 return s;
261 case 4:
262 *(unsigned long *)s = pattern;
263 return s;
264 }
265
266#define COMMON(x) \
267 asm volatile("rep ; stosl" \
268 x \
269 : "=&c" (d0), "=&D" (d1) \
270 : "a" (eax), "0" (count/4), "1" ((long)s) \
271 : "memory")
272
273 {
274 int d0, d1;
275#if __GNUC__ == 4 && __GNUC_MINOR__ == 0
276 /* Workaround for broken gcc 4.0 */
277 register unsigned long eax asm("%eax") = pattern;
278#else
279 unsigned long eax = pattern;
280#endif
281
282 switch (count % 4) {
213 case 0: 283 case 0:
284 COMMON("");
214 return s; 285 return s;
215 case 1: 286 case 1:
216 *(unsigned char *)s = pattern & 0xff; 287 COMMON("\n\tstosb");
217 return s; 288 return s;
218 case 2: 289 case 2:
219 *(unsigned short *)s = pattern & 0xffff; 290 COMMON("\n\tstosw");
220 return s; 291 return s;
221 case 3: 292 default:
222 *(unsigned short *)s = pattern & 0xffff; 293 COMMON("\n\tstosw\n\tstosb");
223 *(2+(unsigned char *)s) = pattern & 0xff;
224 return s;
225 case 4:
226 *(unsigned long *)s = pattern;
227 return s; 294 return s;
295 }
228 } 296 }
229#define COMMON(x) \ 297
230__asm__ __volatile__( \
231 "rep ; stosl" \
232 x \
233 : "=&c" (d0), "=&D" (d1) \
234 : "a" (pattern),"0" (count/4),"1" ((long) s) \
235 : "memory")
236{
237 int d0, d1;
238 switch (count % 4) {
239 case 0: COMMON(""); return s;
240 case 1: COMMON("\n\tstosb"); return s;
241 case 2: COMMON("\n\tstosw"); return s;
242 default: COMMON("\n\tstosw\n\tstosb"); return s;
243 }
244}
245
246#undef COMMON 298#undef COMMON
247} 299}
248 300
249#define __constant_c_x_memset(s, c, count) \ 301#define __constant_c_x_memset(s, c, count) \
250(__builtin_constant_p(count) ? \ 302 (__builtin_constant_p(count) \
251 __constant_c_and_count_memset((s),(c),(count)) : \ 303 ? __constant_c_and_count_memset((s), (c), (count)) \
252 __constant_c_memset((s),(c),(count))) 304 : __constant_c_memset((s), (c), (count)))
253 305
254#define __memset(s, c, count) \ 306#define __memset(s, c, count) \
255(__builtin_constant_p(count) ? \ 307 (__builtin_constant_p(count) \
256 __constant_count_memset((s),(c),(count)) : \ 308 ? __constant_count_memset((s), (c), (count)) \
257 __memset_generic((s),(c),(count))) 309 : __memset_generic((s), (c), (count)))
258 310
259#define __HAVE_ARCH_MEMSET 311#define __HAVE_ARCH_MEMSET
260#define memset(s, c, count) \ 312#define memset(s, c, count) \
261(__builtin_constant_p(c) ? \ 313 (__builtin_constant_p(c) \
262 __constant_c_x_memset((s),(0x01010101UL*(unsigned char)(c)),(count)) : \ 314 ? __constant_c_x_memset((s), (0x01010101UL * (unsigned char)(c)), \
263 __memset((s),(c),(count))) 315 (count)) \
316 : __memset((s), (c), (count)))
264 317
265/* 318/*
266 * find the first occurrence of byte 'c', or 1 past the area if none 319 * find the first occurrence of byte 'c', or 1 past the area if none
267 */ 320 */
268#define __HAVE_ARCH_MEMSCAN 321#define __HAVE_ARCH_MEMSCAN
269extern void *memscan(void * addr, int c, size_t size); 322extern void *memscan(void *addr, int c, size_t size);
270 323
271#endif /* __KERNEL__ */ 324#endif /* __KERNEL__ */
272 325
diff --git a/include/asm-x86/suspend_32.h b/include/asm-x86/suspend_32.h
index 24e1c080aa8a..8675c6782a7d 100644
--- a/include/asm-x86/suspend_32.h
+++ b/include/asm-x86/suspend_32.h
@@ -3,6 +3,9 @@
3 * Based on code 3 * Based on code
4 * Copyright 2001 Patrick Mochel <mochel@osdl.org> 4 * Copyright 2001 Patrick Mochel <mochel@osdl.org>
5 */ 5 */
6#ifndef __ASM_X86_32_SUSPEND_H
7#define __ASM_X86_32_SUSPEND_H
8
6#include <asm/desc.h> 9#include <asm/desc.h>
7#include <asm/i387.h> 10#include <asm/i387.h>
8 11
@@ -44,3 +47,5 @@ static inline void acpi_save_register_state(unsigned long return_point)
44/* routines for saving/restoring kernel state */ 47/* routines for saving/restoring kernel state */
45extern int acpi_save_state_mem(void); 48extern int acpi_save_state_mem(void);
46#endif 49#endif
50
51#endif /* __ASM_X86_32_SUSPEND_H */
diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h
index a2f04cd79b29..983ce37c491f 100644
--- a/include/asm-x86/system.h
+++ b/include/asm-x86/system.h
@@ -136,7 +136,7 @@ __asm__ __volatile__ ("movw %%dx,%1\n\t" \
136#define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base)) 136#define set_base(ldt, base) _set_base(((char *)&(ldt)) , (base))
137#define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1)) 137#define set_limit(ldt, limit) _set_limit(((char *)&(ldt)) , ((limit)-1))
138 138
139extern void load_gs_index(unsigned); 139extern void native_load_gs_index(unsigned);
140 140
141/* 141/*
142 * Load a segment. Fall back on loading the zero 142 * Load a segment. Fall back on loading the zero
@@ -153,14 +153,14 @@ extern void load_gs_index(unsigned);
153 "jmp 2b\n" \ 153 "jmp 2b\n" \
154 ".previous\n" \ 154 ".previous\n" \
155 _ASM_EXTABLE(1b,3b) \ 155 _ASM_EXTABLE(1b,3b) \
156 : :"r" (value), "r" (0)) 156 : :"r" (value), "r" (0) : "memory")
157 157
158 158
159/* 159/*
160 * Save a segment register away 160 * Save a segment register away
161 */ 161 */
162#define savesegment(seg, value) \ 162#define savesegment(seg, value) \
163 asm volatile("mov %%" #seg ",%0":"=rm" (value)) 163 asm("mov %%" #seg ",%0":"=r" (value) : : "memory")
164 164
165static inline unsigned long get_limit(unsigned long segment) 165static inline unsigned long get_limit(unsigned long segment)
166{ 166{
@@ -282,6 +282,7 @@ static inline void native_wbinvd(void)
282#ifdef CONFIG_X86_64 282#ifdef CONFIG_X86_64
283#define read_cr8() (native_read_cr8()) 283#define read_cr8() (native_read_cr8())
284#define write_cr8(x) (native_write_cr8(x)) 284#define write_cr8(x) (native_write_cr8(x))
285#define load_gs_index native_load_gs_index
285#endif 286#endif
286 287
287/* Clear the 'TS' bit */ 288/* Clear the 'TS' bit */
@@ -289,7 +290,7 @@ static inline void native_wbinvd(void)
289 290
290#endif/* CONFIG_PARAVIRT */ 291#endif/* CONFIG_PARAVIRT */
291 292
292#define stts() write_cr0(8 | read_cr0()) 293#define stts() write_cr0(read_cr0() | X86_CR0_TS)
293 294
294#endif /* __KERNEL__ */ 295#endif /* __KERNEL__ */
295 296
@@ -303,7 +304,6 @@ static inline void clflush(volatile void *__p)
303void disable_hlt(void); 304void disable_hlt(void);
304void enable_hlt(void); 305void enable_hlt(void);
305 306
306extern int es7000_plat;
307void cpu_idle_wait(void); 307void cpu_idle_wait(void);
308 308
309extern unsigned long arch_align_stack(unsigned long sp); 309extern unsigned long arch_align_stack(unsigned long sp);
diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h
index 77244f17993f..895339d2bc0b 100644
--- a/include/asm-x86/thread_info.h
+++ b/include/asm-x86/thread_info.h
@@ -1,9 +1,253 @@
1/* thread_info.h: low-level thread information
2 *
3 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
4 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
5 */
6
1#ifndef _ASM_X86_THREAD_INFO_H 7#ifndef _ASM_X86_THREAD_INFO_H
8#define _ASM_X86_THREAD_INFO_H
9
10#include <linux/compiler.h>
11#include <asm/page.h>
12#include <asm/types.h>
13
14/*
15 * low level task data that entry.S needs immediate access to
16 * - this struct should fit entirely inside of one cache line
17 * - this struct shares the supervisor stack pages
18 */
19#ifndef __ASSEMBLY__
20struct task_struct;
21struct exec_domain;
22#include <asm/processor.h>
23
24struct thread_info {
25 struct task_struct *task; /* main task structure */
26 struct exec_domain *exec_domain; /* execution domain */
27 unsigned long flags; /* low level flags */
28 __u32 status; /* thread synchronous flags */
29 __u32 cpu; /* current CPU */
30 int preempt_count; /* 0 => preemptable,
31 <0 => BUG */
32 mm_segment_t addr_limit;
33 struct restart_block restart_block;
34 void __user *sysenter_return;
35#ifdef CONFIG_X86_32
36 unsigned long previous_esp; /* ESP of the previous stack in
37 case of nested (IRQ) stacks
38 */
39 __u8 supervisor_stack[0];
40#endif
41};
42
43#define INIT_THREAD_INFO(tsk) \
44{ \
45 .task = &tsk, \
46 .exec_domain = &default_exec_domain, \
47 .flags = 0, \
48 .cpu = 0, \
49 .preempt_count = 1, \
50 .addr_limit = KERNEL_DS, \
51 .restart_block = { \
52 .fn = do_no_restart_syscall, \
53 }, \
54}
55
56#define init_thread_info (init_thread_union.thread_info)
57#define init_stack (init_thread_union.stack)
58
59#else /* !__ASSEMBLY__ */
60
61#include <asm/asm-offsets.h>
62
63#endif
64
65/*
66 * thread information flags
67 * - these are process state flags that various assembly files
68 * may need to access
69 * - pending work-to-be-done flags are in LSW
70 * - other flags in MSW
71 * Warning: layout of LSW is hardcoded in entry.S
72 */
73#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
74#define TIF_SIGPENDING 2 /* signal pending */
75#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
76#define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/
77#define TIF_IRET 5 /* force IRET */
2#ifdef CONFIG_X86_32 78#ifdef CONFIG_X86_32
3# include "thread_info_32.h" 79#define TIF_SYSCALL_EMU 6 /* syscall emulation active */
80#endif
81#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
82#define TIF_SECCOMP 8 /* secure computing */
83#define TIF_MCE_NOTIFY 10 /* notify userspace of an MCE */
84#define TIF_HRTICK_RESCHED 11 /* reprogram hrtick timer */
85#define TIF_NOTSC 16 /* TSC is not accessible in userland */
86#define TIF_IA32 17 /* 32bit process */
87#define TIF_FORK 18 /* ret_from_fork */
88#define TIF_ABI_PENDING 19
89#define TIF_MEMDIE 20
90#define TIF_DEBUG 21 /* uses debug registers */
91#define TIF_IO_BITMAP 22 /* uses I/O bitmap */
92#define TIF_FREEZE 23 /* is freezing for suspend */
93#define TIF_FORCED_TF 24 /* true if TF in eflags artificially */
94#define TIF_DEBUGCTLMSR 25 /* uses thread_struct.debugctlmsr */
95#define TIF_DS_AREA_MSR 26 /* uses thread_struct.ds_area_msr */
96#define TIF_BTS_TRACE_TS 27 /* record scheduling event timestamps */
97
98#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
99#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
100#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
101#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
102#define _TIF_IRET (1 << TIF_IRET)
103#ifdef CONFIG_X86_32
104#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
4#else 105#else
5# include "thread_info_64.h" 106#define _TIF_SYSCALL_EMU 0
6#endif 107#endif
108#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
109#define _TIF_SECCOMP (1 << TIF_SECCOMP)
110#define _TIF_MCE_NOTIFY (1 << TIF_MCE_NOTIFY)
111#define _TIF_HRTICK_RESCHED (1 << TIF_HRTICK_RESCHED)
112#define _TIF_NOTSC (1 << TIF_NOTSC)
113#define _TIF_IA32 (1 << TIF_IA32)
114#define _TIF_FORK (1 << TIF_FORK)
115#define _TIF_ABI_PENDING (1 << TIF_ABI_PENDING)
116#define _TIF_DEBUG (1 << TIF_DEBUG)
117#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP)
118#define _TIF_FREEZE (1 << TIF_FREEZE)
119#define _TIF_FORCED_TF (1 << TIF_FORCED_TF)
120#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR)
121#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR)
122#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS)
123
124/* work to do on interrupt/exception return */
125#define _TIF_WORK_MASK \
126 (0x0000FFFF & \
127 ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP| \
128 _TIF_SECCOMP|_TIF_SYSCALL_EMU))
129
130/* work to do on any return to user space */
131#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP)
132
133/* Only used for 64 bit */
134#define _TIF_DO_NOTIFY_MASK \
135 (_TIF_SIGPENDING|_TIF_SINGLESTEP|_TIF_MCE_NOTIFY|_TIF_HRTICK_RESCHED)
136
137/* flags to check in __switch_to() */
138#define _TIF_WORK_CTXSW \
139 (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS| \
140 _TIF_NOTSC)
141
142#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
143#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
144
145#define PREEMPT_ACTIVE 0x10000000
146
147/* thread information allocation */
148#ifdef CONFIG_DEBUG_STACK_USAGE
149#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO)
150#else
151#define THREAD_FLAGS GFP_KERNEL
152#endif
153
154#define alloc_thread_info(tsk) \
155 ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
156
157#ifdef CONFIG_X86_32
158
159#define STACK_WARN (THREAD_SIZE/8)
160/*
161 * macros/functions for gaining access to the thread information structure
162 *
163 * preempt_count needs to be 1 initially, until the scheduler is functional.
164 */
165#ifndef __ASSEMBLY__
166
167
168/* how to get the current stack pointer from C */
169register unsigned long current_stack_pointer asm("esp") __used;
170
171/* how to get the thread information struct from C */
172static inline struct thread_info *current_thread_info(void)
173{
174 return (struct thread_info *)
175 (current_stack_pointer & ~(THREAD_SIZE - 1));
176}
177
178#else /* !__ASSEMBLY__ */
179
180/* how to get the thread information struct from ASM */
181#define GET_THREAD_INFO(reg) \
182 movl $-THREAD_SIZE, reg; \
183 andl %esp, reg
184
185/* use this one if reg already contains %esp */
186#define GET_THREAD_INFO_WITH_ESP(reg) \
187 andl $-THREAD_SIZE, reg
188
189#endif
190
191#else /* X86_32 */
192
193#include <asm/pda.h>
194
195/*
196 * macros/functions for gaining access to the thread information structure
197 * preempt_count needs to be 1 initially, until the scheduler is functional.
198 */
199#ifndef __ASSEMBLY__
200static inline struct thread_info *current_thread_info(void)
201{
202 struct thread_info *ti;
203 ti = (void *)(read_pda(kernelstack) + PDA_STACKOFFSET - THREAD_SIZE);
204 return ti;
205}
206
207/* do not use in interrupt context */
208static inline struct thread_info *stack_thread_info(void)
209{
210 struct thread_info *ti;
211 asm("andq %%rsp,%0; " : "=r" (ti) : "0" (~(THREAD_SIZE - 1)));
212 return ti;
213}
214
215#else /* !__ASSEMBLY__ */
216
217/* how to get the thread information struct from ASM */
218#define GET_THREAD_INFO(reg) \
219 movq %gs:pda_kernelstack,reg ; \
220 subq $(THREAD_SIZE-PDA_STACKOFFSET),reg
221
222#endif
223
224#endif /* !X86_32 */
225
226/*
227 * Thread-synchronous status.
228 *
229 * This is different from the flags in that nobody else
230 * ever touches our thread-synchronous status, so we don't
231 * have to worry about atomic accesses.
232 */
233#define TS_USEDFPU 0x0001 /* FPU was used by this task
234 this quantum (SMP) */
235#define TS_COMPAT 0x0002 /* 32bit syscall active (64BIT)*/
236#define TS_POLLING 0x0004 /* true if in idle loop
237 and not sleeping */
238#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */
239
240#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
241
242#ifndef __ASSEMBLY__
243#define HAVE_SET_RESTORE_SIGMASK 1
244static inline void set_restore_sigmask(void)
245{
246 struct thread_info *ti = current_thread_info();
247 ti->status |= TS_RESTORE_SIGMASK;
248 set_bit(TIF_SIGPENDING, (unsigned long *)&ti->flags);
249}
250#endif /* !__ASSEMBLY__ */
7 251
8#ifndef __ASSEMBLY__ 252#ifndef __ASSEMBLY__
9extern void arch_task_cache_init(void); 253extern void arch_task_cache_init(void);
diff --git a/include/asm-x86/thread_info_32.h b/include/asm-x86/thread_info_32.h
deleted file mode 100644
index b6338829d1a8..000000000000
--- a/include/asm-x86/thread_info_32.h
+++ /dev/null
@@ -1,205 +0,0 @@
1/* thread_info.h: i386 low-level thread information
2 *
3 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
4 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
5 */
6
7#ifndef _ASM_THREAD_INFO_H
8#define _ASM_THREAD_INFO_H
9
10#ifdef __KERNEL__
11
12#include <linux/compiler.h>
13#include <asm/page.h>
14
15#ifndef __ASSEMBLY__
16#include <asm/processor.h>
17#endif
18
19/*
20 * low level task data that entry.S needs immediate access to
21 * - this struct should fit entirely inside of one cache line
22 * - this struct shares the supervisor stack pages
23 * - if the contents of this structure are changed,
24 * the assembly constants must also be changed
25 */
26#ifndef __ASSEMBLY__
27
28struct thread_info {
29 struct task_struct *task; /* main task structure */
30 struct exec_domain *exec_domain; /* execution domain */
31 unsigned long flags; /* low level flags */
32 unsigned long status; /* thread-synchronous flags */
33 __u32 cpu; /* current CPU */
34 int preempt_count; /* 0 => preemptable,
35 <0 => BUG */
36 mm_segment_t addr_limit; /* thread address space:
37 0-0xBFFFFFFF user-thread
38 0-0xFFFFFFFF kernel-thread
39 */
40 void *sysenter_return;
41 struct restart_block restart_block;
42 unsigned long previous_esp; /* ESP of the previous stack in
43 case of nested (IRQ) stacks
44 */
45 __u8 supervisor_stack[0];
46};
47
48#else /* !__ASSEMBLY__ */
49
50#include <asm/asm-offsets.h>
51
52#endif
53
54#define PREEMPT_ACTIVE 0x10000000
55#ifdef CONFIG_4KSTACKS
56#define THREAD_SIZE (4096)
57#else
58#define THREAD_SIZE (8192)
59#endif
60
61#define STACK_WARN (THREAD_SIZE/8)
62/*
63 * macros/functions for gaining access to the thread information structure
64 *
65 * preempt_count needs to be 1 initially, until the scheduler is functional.
66 */
67#ifndef __ASSEMBLY__
68
69#define INIT_THREAD_INFO(tsk) \
70{ \
71 .task = &tsk, \
72 .exec_domain = &default_exec_domain, \
73 .flags = 0, \
74 .cpu = 0, \
75 .preempt_count = 1, \
76 .addr_limit = KERNEL_DS, \
77 .restart_block = { \
78 .fn = do_no_restart_syscall, \
79 }, \
80}
81
82#define init_thread_info (init_thread_union.thread_info)
83#define init_stack (init_thread_union.stack)
84
85
86/* how to get the current stack pointer from C */
87register unsigned long current_stack_pointer asm("esp") __used;
88
89/* how to get the thread information struct from C */
90static inline struct thread_info *current_thread_info(void)
91{
92 return (struct thread_info *)
93 (current_stack_pointer & ~(THREAD_SIZE - 1));
94}
95
96/* thread information allocation */
97#ifdef CONFIG_DEBUG_STACK_USAGE
98#define alloc_thread_info(tsk) ((struct thread_info *) \
99 __get_free_pages(GFP_KERNEL | __GFP_ZERO, get_order(THREAD_SIZE)))
100#else
101#define alloc_thread_info(tsk) ((struct thread_info *) \
102 __get_free_pages(GFP_KERNEL, get_order(THREAD_SIZE)))
103#endif
104
105#else /* !__ASSEMBLY__ */
106
107/* how to get the thread information struct from ASM */
108#define GET_THREAD_INFO(reg) \
109 movl $-THREAD_SIZE, reg; \
110 andl %esp, reg
111
112/* use this one if reg already contains %esp */
113#define GET_THREAD_INFO_WITH_ESP(reg) \
114 andl $-THREAD_SIZE, reg
115
116#endif
117
118/*
119 * thread information flags
120 * - these are process state flags that various
121 * assembly files may need to access
122 * - pending work-to-be-done flags are in LSW
123 * - other flags in MSW
124 */
125#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
126#define TIF_SIGPENDING 1 /* signal pending */
127#define TIF_NEED_RESCHED 2 /* rescheduling necessary */
128#define TIF_SINGLESTEP 3 /* restore singlestep on return to
129 user mode */
130#define TIF_IRET 4 /* return with iret */
131#define TIF_SYSCALL_EMU 5 /* syscall emulation active */
132#define TIF_SYSCALL_AUDIT 6 /* syscall auditing active */
133#define TIF_SECCOMP 7 /* secure computing */
134#define TIF_HRTICK_RESCHED 9 /* reprogram hrtick timer */
135#define TIF_MEMDIE 16
136#define TIF_DEBUG 17 /* uses debug registers */
137#define TIF_IO_BITMAP 18 /* uses I/O bitmap */
138#define TIF_FREEZE 19 /* is freezing for suspend */
139#define TIF_NOTSC 20 /* TSC is not accessible in userland */
140#define TIF_FORCED_TF 21 /* true if TF in eflags artificially */
141#define TIF_DEBUGCTLMSR 22 /* uses thread_struct.debugctlmsr */
142#define TIF_DS_AREA_MSR 23 /* uses thread_struct.ds_area_msr */
143#define TIF_BTS_TRACE_TS 24 /* record scheduling event timestamps */
144
145#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
146#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
147#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
148#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
149#define _TIF_IRET (1 << TIF_IRET)
150#define _TIF_SYSCALL_EMU (1 << TIF_SYSCALL_EMU)
151#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
152#define _TIF_SECCOMP (1 << TIF_SECCOMP)
153#define _TIF_HRTICK_RESCHED (1 << TIF_HRTICK_RESCHED)
154#define _TIF_DEBUG (1 << TIF_DEBUG)
155#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP)
156#define _TIF_FREEZE (1 << TIF_FREEZE)
157#define _TIF_NOTSC (1 << TIF_NOTSC)
158#define _TIF_FORCED_TF (1 << TIF_FORCED_TF)
159#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR)
160#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR)
161#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS)
162
163/* work to do on interrupt/exception return */
164#define _TIF_WORK_MASK \
165 (0x0000FFFF & ~(_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | \
166 _TIF_SECCOMP | _TIF_SYSCALL_EMU))
167/* work to do on any return to u-space */
168#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP)
169
170/* flags to check in __switch_to() */
171#define _TIF_WORK_CTXSW \
172 (_TIF_IO_BITMAP | _TIF_NOTSC | _TIF_DEBUGCTLMSR | \
173 _TIF_DS_AREA_MSR | _TIF_BTS_TRACE_TS)
174#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
175#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW | _TIF_DEBUG)
176
177
178/*
179 * Thread-synchronous status.
180 *
181 * This is different from the flags in that nobody else
182 * ever touches our thread-synchronous status, so we don't
183 * have to worry about atomic accesses.
184 */
185#define TS_USEDFPU 0x0001 /* FPU was used by this task
186 this quantum (SMP) */
187#define TS_POLLING 0x0002 /* True if in idle loop
188 and not sleeping */
189#define TS_RESTORE_SIGMASK 0x0004 /* restore signal mask in do_signal() */
190
191#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
192
193#ifndef __ASSEMBLY__
194#define HAVE_SET_RESTORE_SIGMASK 1
195static inline void set_restore_sigmask(void)
196{
197 struct thread_info *ti = current_thread_info();
198 ti->status |= TS_RESTORE_SIGMASK;
199 set_bit(TIF_SIGPENDING, &ti->flags);
200}
201#endif /* !__ASSEMBLY__ */
202
203#endif /* __KERNEL__ */
204
205#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-x86/thread_info_64.h b/include/asm-x86/thread_info_64.h
deleted file mode 100644
index cb69f70abba1..000000000000
--- a/include/asm-x86/thread_info_64.h
+++ /dev/null
@@ -1,195 +0,0 @@
1/* thread_info.h: x86_64 low-level thread information
2 *
3 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
4 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
5 */
6
7#ifndef _ASM_THREAD_INFO_H
8#define _ASM_THREAD_INFO_H
9
10#ifdef __KERNEL__
11
12#include <asm/page.h>
13#include <asm/types.h>
14#include <asm/pda.h>
15
16/*
17 * low level task data that entry.S needs immediate access to
18 * - this struct should fit entirely inside of one cache line
19 * - this struct shares the supervisor stack pages
20 */
21#ifndef __ASSEMBLY__
22struct task_struct;
23struct exec_domain;
24#include <asm/processor.h>
25
26struct thread_info {
27 struct task_struct *task; /* main task structure */
28 struct exec_domain *exec_domain; /* execution domain */
29 __u32 flags; /* low level flags */
30 __u32 status; /* thread synchronous flags */
31 __u32 cpu; /* current CPU */
32 int preempt_count; /* 0 => preemptable,
33 <0 => BUG */
34 mm_segment_t addr_limit;
35 struct restart_block restart_block;
36#ifdef CONFIG_IA32_EMULATION
37 void __user *sysenter_return;
38#endif
39};
40#endif
41
42/*
43 * macros/functions for gaining access to the thread information structure
44 * preempt_count needs to be 1 initially, until the scheduler is functional.
45 */
46#ifndef __ASSEMBLY__
47#define INIT_THREAD_INFO(tsk) \
48{ \
49 .task = &tsk, \
50 .exec_domain = &default_exec_domain, \
51 .flags = 0, \
52 .cpu = 0, \
53 .preempt_count = 1, \
54 .addr_limit = KERNEL_DS, \
55 .restart_block = { \
56 .fn = do_no_restart_syscall, \
57 }, \
58}
59
60#define init_thread_info (init_thread_union.thread_info)
61#define init_stack (init_thread_union.stack)
62
63static inline struct thread_info *current_thread_info(void)
64{
65 struct thread_info *ti;
66 ti = (void *)(read_pda(kernelstack) + PDA_STACKOFFSET - THREAD_SIZE);
67 return ti;
68}
69
70/* do not use in interrupt context */
71static inline struct thread_info *stack_thread_info(void)
72{
73 struct thread_info *ti;
74 asm("andq %%rsp,%0; " : "=r" (ti) : "0" (~(THREAD_SIZE - 1)));
75 return ti;
76}
77
78/* thread information allocation */
79#ifdef CONFIG_DEBUG_STACK_USAGE
80#define THREAD_FLAGS (GFP_KERNEL | __GFP_ZERO)
81#else
82#define THREAD_FLAGS GFP_KERNEL
83#endif
84
85#define alloc_thread_info(tsk) \
86 ((struct thread_info *)__get_free_pages(THREAD_FLAGS, THREAD_ORDER))
87
88#else /* !__ASSEMBLY__ */
89
90/* how to get the thread information struct from ASM */
91#define GET_THREAD_INFO(reg) \
92 movq %gs:pda_kernelstack,reg ; \
93 subq $(THREAD_SIZE-PDA_STACKOFFSET),reg
94
95#endif
96
97/*
98 * thread information flags
99 * - these are process state flags that various assembly files
100 * may need to access
101 * - pending work-to-be-done flags are in LSW
102 * - other flags in MSW
103 * Warning: layout of LSW is hardcoded in entry.S
104 */
105#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
106#define TIF_SIGPENDING 2 /* signal pending */
107#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
108#define TIF_SINGLESTEP 4 /* reenable singlestep on user return*/
109#define TIF_IRET 5 /* force IRET */
110#define TIF_SYSCALL_AUDIT 7 /* syscall auditing active */
111#define TIF_SECCOMP 8 /* secure computing */
112#define TIF_MCE_NOTIFY 10 /* notify userspace of an MCE */
113#define TIF_HRTICK_RESCHED 11 /* reprogram hrtick timer */
114/* 16 free */
115#define TIF_IA32 17 /* 32bit process */
116#define TIF_FORK 18 /* ret_from_fork */
117#define TIF_ABI_PENDING 19
118#define TIF_MEMDIE 20
119#define TIF_DEBUG 21 /* uses debug registers */
120#define TIF_IO_BITMAP 22 /* uses I/O bitmap */
121#define TIF_FREEZE 23 /* is freezing for suspend */
122#define TIF_FORCED_TF 24 /* true if TF in eflags artificially */
123#define TIF_DEBUGCTLMSR 25 /* uses thread_struct.debugctlmsr */
124#define TIF_DS_AREA_MSR 26 /* uses thread_struct.ds_area_msr */
125#define TIF_BTS_TRACE_TS 27 /* record scheduling event timestamps */
126#define TIF_NOTSC 28 /* TSC is not accessible in userland */
127
128#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
129#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
130#define _TIF_SINGLESTEP (1 << TIF_SINGLESTEP)
131#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
132#define _TIF_IRET (1 << TIF_IRET)
133#define _TIF_SYSCALL_AUDIT (1 << TIF_SYSCALL_AUDIT)
134#define _TIF_SECCOMP (1 << TIF_SECCOMP)
135#define _TIF_MCE_NOTIFY (1 << TIF_MCE_NOTIFY)
136#define _TIF_HRTICK_RESCHED (1 << TIF_HRTICK_RESCHED)
137#define _TIF_IA32 (1 << TIF_IA32)
138#define _TIF_FORK (1 << TIF_FORK)
139#define _TIF_ABI_PENDING (1 << TIF_ABI_PENDING)
140#define _TIF_DEBUG (1 << TIF_DEBUG)
141#define _TIF_IO_BITMAP (1 << TIF_IO_BITMAP)
142#define _TIF_FREEZE (1 << TIF_FREEZE)
143#define _TIF_FORCED_TF (1 << TIF_FORCED_TF)
144#define _TIF_DEBUGCTLMSR (1 << TIF_DEBUGCTLMSR)
145#define _TIF_DS_AREA_MSR (1 << TIF_DS_AREA_MSR)
146#define _TIF_BTS_TRACE_TS (1 << TIF_BTS_TRACE_TS)
147#define _TIF_NOTSC (1 << TIF_NOTSC)
148
149/* work to do on interrupt/exception return */
150#define _TIF_WORK_MASK \
151 (0x0000FFFF & \
152 ~(_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SINGLESTEP|_TIF_SECCOMP))
153/* work to do on any return to user space */
154#define _TIF_ALLWORK_MASK (0x0000FFFF & ~_TIF_SECCOMP)
155
156#define _TIF_DO_NOTIFY_MASK \
157 (_TIF_SIGPENDING|_TIF_SINGLESTEP|_TIF_MCE_NOTIFY|_TIF_HRTICK_RESCHED)
158
159/* flags to check in __switch_to() */
160#define _TIF_WORK_CTXSW \
161 (_TIF_IO_BITMAP|_TIF_DEBUGCTLMSR|_TIF_DS_AREA_MSR|_TIF_BTS_TRACE_TS|_TIF_NOTSC)
162#define _TIF_WORK_CTXSW_PREV _TIF_WORK_CTXSW
163#define _TIF_WORK_CTXSW_NEXT (_TIF_WORK_CTXSW|_TIF_DEBUG)
164
165#define PREEMPT_ACTIVE 0x10000000
166
167/*
168 * Thread-synchronous status.
169 *
170 * This is different from the flags in that nobody else
171 * ever touches our thread-synchronous status, so we don't
172 * have to worry about atomic accesses.
173 */
174#define TS_USEDFPU 0x0001 /* FPU was used by this task
175 this quantum (SMP) */
176#define TS_COMPAT 0x0002 /* 32bit syscall active */
177#define TS_POLLING 0x0004 /* true if in idle loop
178 and not sleeping */
179#define TS_RESTORE_SIGMASK 0x0008 /* restore signal mask in do_signal() */
180
181#define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
182
183#ifndef __ASSEMBLY__
184#define HAVE_SET_RESTORE_SIGMASK 1
185static inline void set_restore_sigmask(void)
186{
187 struct thread_info *ti = current_thread_info();
188 ti->status |= TS_RESTORE_SIGMASK;
189 set_bit(TIF_SIGPENDING, &ti->flags);
190}
191#endif /* !__ASSEMBLY__ */
192
193#endif /* __KERNEL__ */
194
195#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-x86/time.h b/include/asm-x86/time.h
index bce72d7a958c..a17fa473e91d 100644
--- a/include/asm-x86/time.h
+++ b/include/asm-x86/time.h
@@ -56,4 +56,6 @@ static inline int native_set_wallclock(unsigned long nowtime)
56 56
57#endif /* CONFIG_PARAVIRT */ 57#endif /* CONFIG_PARAVIRT */
58 58
59extern unsigned long __init calibrate_cpu(void);
60
59#endif 61#endif
diff --git a/include/asm-x86/timer.h b/include/asm-x86/timer.h
index 4f6fcb050c11..fb2a4ddddf3d 100644
--- a/include/asm-x86/timer.h
+++ b/include/asm-x86/timer.h
@@ -7,14 +7,14 @@
7#define TICK_SIZE (tick_nsec / 1000) 7#define TICK_SIZE (tick_nsec / 1000)
8 8
9unsigned long long native_sched_clock(void); 9unsigned long long native_sched_clock(void);
10unsigned long native_calculate_cpu_khz(void); 10unsigned long native_calibrate_tsc(void);
11 11
12extern int timer_ack; 12extern int timer_ack;
13extern int no_timer_check; 13extern int no_timer_check;
14extern int recalibrate_cpu_khz(void); 14extern int recalibrate_cpu_khz(void);
15 15
16#ifndef CONFIG_PARAVIRT 16#ifndef CONFIG_PARAVIRT
17#define calculate_cpu_khz() native_calculate_cpu_khz() 17#define calibrate_tsc() native_calibrate_tsc()
18#endif 18#endif
19 19
20/* Accelerators for sched_clock() 20/* Accelerators for sched_clock()
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index dcf3f8131d6b..90ac7718469a 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -35,79 +35,93 @@
35# endif 35# endif
36#endif 36#endif
37 37
38/* Node not present */
39#define NUMA_NO_NODE (-1)
40
38#ifdef CONFIG_NUMA 41#ifdef CONFIG_NUMA
39#include <linux/cpumask.h> 42#include <linux/cpumask.h>
40#include <asm/mpspec.h> 43#include <asm/mpspec.h>
41 44
42/* Mappings between logical cpu number and node number */
43#ifdef CONFIG_X86_32 45#ifdef CONFIG_X86_32
44extern int cpu_to_node_map[];
45#else
46/* Returns the number of the current Node. */
47#define numa_node_id() (early_cpu_to_node(raw_smp_processor_id()))
48#endif
49
50DECLARE_PER_CPU(int, x86_cpu_to_node_map);
51
52#ifdef CONFIG_SMP
53extern int x86_cpu_to_node_map_init[];
54extern void *x86_cpu_to_node_map_early_ptr;
55#else
56#define x86_cpu_to_node_map_early_ptr NULL
57#endif
58 46
47/* Mappings between node number and cpus on that node. */
59extern cpumask_t node_to_cpumask_map[]; 48extern cpumask_t node_to_cpumask_map[];
60 49
61#define NUMA_NO_NODE (-1) 50/* Mappings between logical cpu number and node number */
51extern int cpu_to_node_map[];
62 52
63/* Returns the number of the node containing CPU 'cpu' */ 53/* Returns the number of the node containing CPU 'cpu' */
64#ifdef CONFIG_X86_32
65#define early_cpu_to_node(cpu) cpu_to_node(cpu)
66static inline int cpu_to_node(int cpu) 54static inline int cpu_to_node(int cpu)
67{ 55{
68 return cpu_to_node_map[cpu]; 56 return cpu_to_node_map[cpu];
69} 57}
58#define early_cpu_to_node(cpu) cpu_to_node(cpu)
70 59
71#else /* CONFIG_X86_64 */ 60/* Returns a bitmask of CPUs on Node 'node'.
72 61 *
73#ifdef CONFIG_SMP 62 * Side note: this function creates the returned cpumask on the stack
74static inline int early_cpu_to_node(int cpu) 63 * so with a high NR_CPUS count, excessive stack space is used. The
64 * node_to_cpumask_ptr function should be used whenever possible.
65 */
66static inline cpumask_t node_to_cpumask(int node)
75{ 67{
76 int *cpu_to_node_map = x86_cpu_to_node_map_early_ptr; 68 return node_to_cpumask_map[node];
77
78 if (cpu_to_node_map)
79 return cpu_to_node_map[cpu];
80 else if (per_cpu_offset(cpu))
81 return per_cpu(x86_cpu_to_node_map, cpu);
82 else
83 return NUMA_NO_NODE;
84} 69}
85#else
86#define early_cpu_to_node(cpu) cpu_to_node(cpu)
87#endif
88 70
71#else /* CONFIG_X86_64 */
72
73/* Mappings between node number and cpus on that node. */
74extern cpumask_t *node_to_cpumask_map;
75
76/* Mappings between logical cpu number and node number */
77DECLARE_EARLY_PER_CPU(int, x86_cpu_to_node_map);
78
79/* Returns the number of the current Node. */
80#define numa_node_id() read_pda(nodenumber)
81
82#ifdef CONFIG_DEBUG_PER_CPU_MAPS
83extern int cpu_to_node(int cpu);
84extern int early_cpu_to_node(int cpu);
85extern const cpumask_t *_node_to_cpumask_ptr(int node);
86extern cpumask_t node_to_cpumask(int node);
87
88#else /* !CONFIG_DEBUG_PER_CPU_MAPS */
89
90/* Returns the number of the node containing CPU 'cpu' */
89static inline int cpu_to_node(int cpu) 91static inline int cpu_to_node(int cpu)
90{ 92{
91#ifdef CONFIG_DEBUG_PER_CPU_MAPS
92 if (x86_cpu_to_node_map_early_ptr) {
93 printk("KERN_NOTICE cpu_to_node(%d): usage too early!\n",
94 (int)cpu);
95 dump_stack();
96 return ((int *)x86_cpu_to_node_map_early_ptr)[cpu];
97 }
98#endif
99 return per_cpu(x86_cpu_to_node_map, cpu); 93 return per_cpu(x86_cpu_to_node_map, cpu);
100} 94}
101 95
102#ifdef CONFIG_NUMA 96/* Same function but used if called before per_cpu areas are setup */
97static inline int early_cpu_to_node(int cpu)
98{
99 if (early_per_cpu_ptr(x86_cpu_to_node_map))
100 return early_per_cpu_ptr(x86_cpu_to_node_map)[cpu];
101
102 return per_cpu(x86_cpu_to_node_map, cpu);
103}
103 104
104/* Returns a pointer to the cpumask of CPUs on Node 'node'. */ 105/* Returns a pointer to the cpumask of CPUs on Node 'node'. */
106static inline const cpumask_t *_node_to_cpumask_ptr(int node)
107{
108 return &node_to_cpumask_map[node];
109}
110
111/* Returns a bitmask of CPUs on Node 'node'. */
112static inline cpumask_t node_to_cpumask(int node)
113{
114 return node_to_cpumask_map[node];
115}
116
117#endif /* !CONFIG_DEBUG_PER_CPU_MAPS */
118
119/* Replace default node_to_cpumask_ptr with optimized version */
105#define node_to_cpumask_ptr(v, node) \ 120#define node_to_cpumask_ptr(v, node) \
106 cpumask_t *v = &(node_to_cpumask_map[node]) 121 const cpumask_t *v = _node_to_cpumask_ptr(node)
107 122
108#define node_to_cpumask_ptr_next(v, node) \ 123#define node_to_cpumask_ptr_next(v, node) \
109 v = &(node_to_cpumask_map[node]) 124 v = _node_to_cpumask_ptr(node)
110#endif
111 125
112#endif /* CONFIG_X86_64 */ 126#endif /* CONFIG_X86_64 */
113 127
@@ -117,20 +131,6 @@ static inline int cpu_to_node(int cpu)
117 */ 131 */
118#define parent_node(node) (node) 132#define parent_node(node) (node)
119 133
120/* Returns a bitmask of CPUs on Node 'node'. */
121static inline cpumask_t node_to_cpumask(int node)
122{
123 return node_to_cpumask_map[node];
124}
125
126/* Returns the number of the first CPU on Node 'node'. */
127static inline int node_to_first_cpu(int node)
128{
129 cpumask_t mask = node_to_cpumask(node);
130
131 return first_cpu(mask);
132}
133
134#define pcibus_to_node(bus) __pcibus_to_node(bus) 134#define pcibus_to_node(bus) __pcibus_to_node(bus)
135#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus) 135#define pcibus_to_cpumask(bus) __pcibus_to_cpumask(bus)
136 136
@@ -180,12 +180,44 @@ extern int __node_distance(int, int);
180#define node_distance(a, b) __node_distance(a, b) 180#define node_distance(a, b) __node_distance(a, b)
181#endif 181#endif
182 182
183#else /* CONFIG_NUMA */ 183#else /* !CONFIG_NUMA */
184 184
185#define numa_node_id() 0
186#define cpu_to_node(cpu) 0
187#define early_cpu_to_node(cpu) 0
188
189static inline const cpumask_t *_node_to_cpumask_ptr(int node)
190{
191 return &cpu_online_map;
192}
193static inline cpumask_t node_to_cpumask(int node)
194{
195 return cpu_online_map;
196}
197static inline int node_to_first_cpu(int node)
198{
199 return first_cpu(cpu_online_map);
200}
201
202/* Replace default node_to_cpumask_ptr with optimized version */
203#define node_to_cpumask_ptr(v, node) \
204 const cpumask_t *v = _node_to_cpumask_ptr(node)
205
206#define node_to_cpumask_ptr_next(v, node) \
207 v = _node_to_cpumask_ptr(node)
185#endif 208#endif
186 209
187#include <asm-generic/topology.h> 210#include <asm-generic/topology.h>
188 211
212#ifdef CONFIG_NUMA
213/* Returns the number of the first CPU on Node 'node'. */
214static inline int node_to_first_cpu(int node)
215{
216 node_to_cpumask_ptr(mask, node);
217 return first_cpu(*mask);
218}
219#endif
220
189extern cpumask_t cpu_coregroup_map(int cpu); 221extern cpumask_t cpu_coregroup_map(int cpu);
190 222
191#ifdef ENABLE_TOPO_DEFINES 223#ifdef ENABLE_TOPO_DEFINES
@@ -193,6 +225,9 @@ extern cpumask_t cpu_coregroup_map(int cpu);
193#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id) 225#define topology_core_id(cpu) (cpu_data(cpu).cpu_core_id)
194#define topology_core_siblings(cpu) (per_cpu(cpu_core_map, cpu)) 226#define topology_core_siblings(cpu) (per_cpu(cpu_core_map, cpu))
195#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu)) 227#define topology_thread_siblings(cpu) (per_cpu(cpu_sibling_map, cpu))
228
229/* indicates that pointers to the topology cpumask_t maps are valid */
230#define arch_provides_topology_pointers yes
196#endif 231#endif
197 232
198static inline void arch_fix_phys_package_id(int num, u32 slot) 233static inline void arch_fix_phys_package_id(int num, u32 slot)
@@ -220,4 +255,4 @@ static inline void set_mp_bus_to_node(int busnum, int node)
220} 255}
221#endif 256#endif
222 257
223#endif 258#endif /* _ASM_X86_TOPOLOGY_H */
diff --git a/include/asm-x86/tsc.h b/include/asm-x86/tsc.h
index 548873ab5fc1..cb6f6ee45b8f 100644
--- a/include/asm-x86/tsc.h
+++ b/include/asm-x86/tsc.h
@@ -48,7 +48,6 @@ static __always_inline cycles_t vget_cycles(void)
48extern void tsc_init(void); 48extern void tsc_init(void);
49extern void mark_tsc_unstable(char *reason); 49extern void mark_tsc_unstable(char *reason);
50extern int unsynchronized_tsc(void); 50extern int unsynchronized_tsc(void);
51extern void init_tsc_clocksource(void);
52int check_tsc_unstable(void); 51int check_tsc_unstable(void);
53 52
54/* 53/*
@@ -58,7 +57,6 @@ int check_tsc_unstable(void);
58extern void check_tsc_sync_source(int cpu); 57extern void check_tsc_sync_source(int cpu);
59extern void check_tsc_sync_target(void); 58extern void check_tsc_sync_target(void);
60 59
61extern void tsc_calibrate(void);
62extern int notsc_setup(char *); 60extern int notsc_setup(char *);
63 61
64#endif 62#endif
diff --git a/include/asm-x86/uaccess.h b/include/asm-x86/uaccess.h
index 9fefd2947e78..f6fa4d841bbc 100644
--- a/include/asm-x86/uaccess.h
+++ b/include/asm-x86/uaccess.h
@@ -1,5 +1,453 @@
1#ifndef _ASM_UACCES_H_
2#define _ASM_UACCES_H_
3/*
4 * User space memory access functions
5 */
6#include <linux/errno.h>
7#include <linux/compiler.h>
8#include <linux/thread_info.h>
9#include <linux/prefetch.h>
10#include <linux/string.h>
11#include <asm/asm.h>
12#include <asm/page.h>
13
14#define VERIFY_READ 0
15#define VERIFY_WRITE 1
16
17/*
18 * The fs value determines whether argument validity checking should be
19 * performed or not. If get_fs() == USER_DS, checking is performed, with
20 * get_fs() == KERNEL_DS, checking is bypassed.
21 *
22 * For historical reasons, these macros are grossly misnamed.
23 */
24
25#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
26
27#define KERNEL_DS MAKE_MM_SEG(-1UL)
28#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
29
30#define get_ds() (KERNEL_DS)
31#define get_fs() (current_thread_info()->addr_limit)
32#define set_fs(x) (current_thread_info()->addr_limit = (x))
33
34#define segment_eq(a, b) ((a).seg == (b).seg)
35
36#define __addr_ok(addr) \
37 ((unsigned long __force)(addr) < \
38 (current_thread_info()->addr_limit.seg))
39
40/*
41 * Test whether a block of memory is a valid user space address.
42 * Returns 0 if the range is valid, nonzero otherwise.
43 *
44 * This is equivalent to the following test:
45 * (u33)addr + (u33)size >= (u33)current->addr_limit.seg (u65 for x86_64)
46 *
47 * This needs 33-bit (65-bit for x86_64) arithmetic. We have a carry...
48 */
49
50#define __range_not_ok(addr, size) \
51({ \
52 unsigned long flag, roksum; \
53 __chk_user_ptr(addr); \
54 asm("add %3,%1 ; sbb %0,%0 ; cmp %1,%4 ; sbb $0,%0" \
55 : "=&r" (flag), "=r" (roksum) \
56 : "1" (addr), "g" ((long)(size)), \
57 "rm" (current_thread_info()->addr_limit.seg)); \
58 flag; \
59})
60
61/**
62 * access_ok: - Checks if a user space pointer is valid
63 * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
64 * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
65 * to write to a block, it is always safe to read from it.
66 * @addr: User space pointer to start of block to check
67 * @size: Size of block to check
68 *
69 * Context: User context only. This function may sleep.
70 *
71 * Checks if a pointer to a block of memory in user space is valid.
72 *
73 * Returns true (nonzero) if the memory block may be valid, false (zero)
74 * if it is definitely invalid.
75 *
76 * Note that, depending on architecture, this function probably just
77 * checks that the pointer is in the user space range - after calling
78 * this function, memory access functions may still return -EFAULT.
79 */
80#define access_ok(type, addr, size) (likely(__range_not_ok(addr, size) == 0))
81
82/*
83 * The exception table consists of pairs of addresses: the first is the
84 * address of an instruction that is allowed to fault, and the second is
85 * the address at which the program should continue. No registers are
86 * modified, so it is entirely up to the continuation code to figure out
87 * what to do.
88 *
89 * All the routines below use bits of fixup code that are out of line
90 * with the main instruction path. This means when everything is well,
91 * we don't even have to jump over them. Further, they do not intrude
92 * on our cache or tlb entries.
93 */
94
95struct exception_table_entry {
96 unsigned long insn, fixup;
97};
98
99extern int fixup_exception(struct pt_regs *regs);
100
101/*
102 * These are the main single-value transfer routines. They automatically
103 * use the right size if we just have the right pointer type.
104 *
105 * This gets kind of ugly. We want to return _two_ values in "get_user()"
106 * and yet we don't want to do any pointers, because that is too much
107 * of a performance impact. Thus we have a few rather ugly macros here,
108 * and hide all the ugliness from the user.
109 *
110 * The "__xxx" versions of the user access functions are versions that
111 * do not verify the address space, that must have been done previously
112 * with a separate "access_ok()" call (this is used when we do multiple
113 * accesses to the same area of user memory).
114 */
115
116extern int __get_user_1(void);
117extern int __get_user_2(void);
118extern int __get_user_4(void);
119extern int __get_user_8(void);
120extern int __get_user_bad(void);
121
122#define __get_user_x(size, ret, x, ptr) \
123 asm volatile("call __get_user_" #size \
124 : "=a" (ret),"=d" (x) \
125 : "0" (ptr)) \
126
127/* Careful: we have to cast the result to the type of the pointer
128 * for sign reasons */
129
130/**
131 * get_user: - Get a simple variable from user space.
132 * @x: Variable to store result.
133 * @ptr: Source address, in user space.
134 *
135 * Context: User context only. This function may sleep.
136 *
137 * This macro copies a single simple variable from user space to kernel
138 * space. It supports simple types like char and int, but not larger
139 * data types like structures or arrays.
140 *
141 * @ptr must have pointer-to-simple-variable type, and the result of
142 * dereferencing @ptr must be assignable to @x without a cast.
143 *
144 * Returns zero on success, or -EFAULT on error.
145 * On error, the variable @x is set to zero.
146 */
147#ifdef CONFIG_X86_32
148#define __get_user_8(__ret_gu, __val_gu, ptr) \
149 __get_user_x(X, __ret_gu, __val_gu, ptr)
150#else
151#define __get_user_8(__ret_gu, __val_gu, ptr) \
152 __get_user_x(8, __ret_gu, __val_gu, ptr)
153#endif
154
155#define get_user(x, ptr) \
156({ \
157 int __ret_gu; \
158 unsigned long __val_gu; \
159 __chk_user_ptr(ptr); \
160 switch (sizeof(*(ptr))) { \
161 case 1: \
162 __get_user_x(1, __ret_gu, __val_gu, ptr); \
163 break; \
164 case 2: \
165 __get_user_x(2, __ret_gu, __val_gu, ptr); \
166 break; \
167 case 4: \
168 __get_user_x(4, __ret_gu, __val_gu, ptr); \
169 break; \
170 case 8: \
171 __get_user_8(__ret_gu, __val_gu, ptr); \
172 break; \
173 default: \
174 __get_user_x(X, __ret_gu, __val_gu, ptr); \
175 break; \
176 } \
177 (x) = (__typeof__(*(ptr)))__val_gu; \
178 __ret_gu; \
179})
180
181#define __put_user_x(size, x, ptr, __ret_pu) \
182 asm volatile("call __put_user_" #size : "=a" (__ret_pu) \
183 :"0" ((typeof(*(ptr)))(x)), "c" (ptr) : "ebx")
184
185
186
187#ifdef CONFIG_X86_32
188#define __put_user_u64(x, addr, err) \
189 asm volatile("1: movl %%eax,0(%2)\n" \
190 "2: movl %%edx,4(%2)\n" \
191 "3:\n" \
192 ".section .fixup,\"ax\"\n" \
193 "4: movl %3,%0\n" \
194 " jmp 3b\n" \
195 ".previous\n" \
196 _ASM_EXTABLE(1b, 4b) \
197 _ASM_EXTABLE(2b, 4b) \
198 : "=r" (err) \
199 : "A" (x), "r" (addr), "i" (-EFAULT), "0" (err))
200
201#define __put_user_x8(x, ptr, __ret_pu) \
202 asm volatile("call __put_user_8" : "=a" (__ret_pu) \
203 : "A" ((typeof(*(ptr)))(x)), "c" (ptr) : "ebx")
204#else
205#define __put_user_u64(x, ptr, retval) \
206 __put_user_asm(x, ptr, retval, "q", "", "Zr", -EFAULT)
207#define __put_user_x8(x, ptr, __ret_pu) __put_user_x(8, x, ptr, __ret_pu)
208#endif
209
210extern void __put_user_bad(void);
211
212/*
213 * Strange magic calling convention: pointer in %ecx,
214 * value in %eax(:%edx), return value in %eax. clobbers %rbx
215 */
216extern void __put_user_1(void);
217extern void __put_user_2(void);
218extern void __put_user_4(void);
219extern void __put_user_8(void);
220
221#ifdef CONFIG_X86_WP_WORKS_OK
222
223/**
224 * put_user: - Write a simple value into user space.
225 * @x: Value to copy to user space.
226 * @ptr: Destination address, in user space.
227 *
228 * Context: User context only. This function may sleep.
229 *
230 * This macro copies a single simple value from kernel space to user
231 * space. It supports simple types like char and int, but not larger
232 * data types like structures or arrays.
233 *
234 * @ptr must have pointer-to-simple-variable type, and @x must be assignable
235 * to the result of dereferencing @ptr.
236 *
237 * Returns zero on success, or -EFAULT on error.
238 */
239#define put_user(x, ptr) \
240({ \
241 int __ret_pu; \
242 __typeof__(*(ptr)) __pu_val; \
243 __chk_user_ptr(ptr); \
244 __pu_val = x; \
245 switch (sizeof(*(ptr))) { \
246 case 1: \
247 __put_user_x(1, __pu_val, ptr, __ret_pu); \
248 break; \
249 case 2: \
250 __put_user_x(2, __pu_val, ptr, __ret_pu); \
251 break; \
252 case 4: \
253 __put_user_x(4, __pu_val, ptr, __ret_pu); \
254 break; \
255 case 8: \
256 __put_user_x8(__pu_val, ptr, __ret_pu); \
257 break; \
258 default: \
259 __put_user_x(X, __pu_val, ptr, __ret_pu); \
260 break; \
261 } \
262 __ret_pu; \
263})
264
265#define __put_user_size(x, ptr, size, retval, errret) \
266do { \
267 retval = 0; \
268 __chk_user_ptr(ptr); \
269 switch (size) { \
270 case 1: \
271 __put_user_asm(x, ptr, retval, "b", "b", "iq", errret); \
272 break; \
273 case 2: \
274 __put_user_asm(x, ptr, retval, "w", "w", "ir", errret); \
275 break; \
276 case 4: \
277 __put_user_asm(x, ptr, retval, "l", "k", "ir", errret);\
278 break; \
279 case 8: \
280 __put_user_u64((__typeof__(*ptr))(x), ptr, retval); \
281 break; \
282 default: \
283 __put_user_bad(); \
284 } \
285} while (0)
286
287#else
288
289#define __put_user_size(x, ptr, size, retval, errret) \
290do { \
291 __typeof__(*(ptr))__pus_tmp = x; \
292 retval = 0; \
293 \
294 if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, size) != 0)) \
295 retval = errret; \
296} while (0)
297
298#define put_user(x, ptr) \
299({ \
300 int __ret_pu; \
301 __typeof__(*(ptr))__pus_tmp = x; \
302 __ret_pu = 0; \
303 if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, \
304 sizeof(*(ptr))) != 0)) \
305 __ret_pu = -EFAULT; \
306 __ret_pu; \
307})
308#endif
309
310#ifdef CONFIG_X86_32
311#define __get_user_asm_u64(x, ptr, retval, errret) (x) = __get_user_bad()
312#else
313#define __get_user_asm_u64(x, ptr, retval, errret) \
314 __get_user_asm(x, ptr, retval, "q", "", "=r", errret)
315#endif
316
317#define __get_user_size(x, ptr, size, retval, errret) \
318do { \
319 retval = 0; \
320 __chk_user_ptr(ptr); \
321 switch (size) { \
322 case 1: \
323 __get_user_asm(x, ptr, retval, "b", "b", "=q", errret); \
324 break; \
325 case 2: \
326 __get_user_asm(x, ptr, retval, "w", "w", "=r", errret); \
327 break; \
328 case 4: \
329 __get_user_asm(x, ptr, retval, "l", "k", "=r", errret); \
330 break; \
331 case 8: \
332 __get_user_asm_u64(x, ptr, retval, errret); \
333 break; \
334 default: \
335 (x) = __get_user_bad(); \
336 } \
337} while (0)
338
339#define __get_user_asm(x, addr, err, itype, rtype, ltype, errret) \
340 asm volatile("1: mov"itype" %2,%"rtype"1\n" \
341 "2:\n" \
342 ".section .fixup,\"ax\"\n" \
343 "3: mov %3,%0\n" \
344 " xor"itype" %"rtype"1,%"rtype"1\n" \
345 " jmp 2b\n" \
346 ".previous\n" \
347 _ASM_EXTABLE(1b, 3b) \
348 : "=r" (err), ltype(x) \
349 : "m" (__m(addr)), "i" (errret), "0" (err))
350
351#define __put_user_nocheck(x, ptr, size) \
352({ \
353 long __pu_err; \
354 __put_user_size((x), (ptr), (size), __pu_err, -EFAULT); \
355 __pu_err; \
356})
357
358#define __get_user_nocheck(x, ptr, size) \
359({ \
360 long __gu_err; \
361 unsigned long __gu_val; \
362 __get_user_size(__gu_val, (ptr), (size), __gu_err, -EFAULT); \
363 (x) = (__force __typeof__(*(ptr)))__gu_val; \
364 __gu_err; \
365})
366
367/* FIXME: this hack is definitely wrong -AK */
368struct __large_struct { unsigned long buf[100]; };
369#define __m(x) (*(struct __large_struct __user *)(x))
370
371/*
372 * Tell gcc we read from memory instead of writing: this is because
373 * we do not write to any memory gcc knows about, so there are no
374 * aliasing issues.
375 */
376#define __put_user_asm(x, addr, err, itype, rtype, ltype, errret) \
377 asm volatile("1: mov"itype" %"rtype"1,%2\n" \
378 "2:\n" \
379 ".section .fixup,\"ax\"\n" \
380 "3: mov %3,%0\n" \
381 " jmp 2b\n" \
382 ".previous\n" \
383 _ASM_EXTABLE(1b, 3b) \
384 : "=r"(err) \
385 : ltype(x), "m" (__m(addr)), "i" (errret), "0" (err))
386/**
387 * __get_user: - Get a simple variable from user space, with less checking.
388 * @x: Variable to store result.
389 * @ptr: Source address, in user space.
390 *
391 * Context: User context only. This function may sleep.
392 *
393 * This macro copies a single simple variable from user space to kernel
394 * space. It supports simple types like char and int, but not larger
395 * data types like structures or arrays.
396 *
397 * @ptr must have pointer-to-simple-variable type, and the result of
398 * dereferencing @ptr must be assignable to @x without a cast.
399 *
400 * Caller must check the pointer with access_ok() before calling this
401 * function.
402 *
403 * Returns zero on success, or -EFAULT on error.
404 * On error, the variable @x is set to zero.
405 */
406
407#define __get_user(x, ptr) \
408 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
409/**
410 * __put_user: - Write a simple value into user space, with less checking.
411 * @x: Value to copy to user space.
412 * @ptr: Destination address, in user space.
413 *
414 * Context: User context only. This function may sleep.
415 *
416 * This macro copies a single simple value from kernel space to user
417 * space. It supports simple types like char and int, but not larger
418 * data types like structures or arrays.
419 *
420 * @ptr must have pointer-to-simple-variable type, and @x must be assignable
421 * to the result of dereferencing @ptr.
422 *
423 * Caller must check the pointer with access_ok() before calling this
424 * function.
425 *
426 * Returns zero on success, or -EFAULT on error.
427 */
428
429#define __put_user(x, ptr) \
430 __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
431
432#define __get_user_unaligned __get_user
433#define __put_user_unaligned __put_user
434
435/*
436 * movsl can be slow when source and dest are not both 8-byte aligned
437 */
438#ifdef CONFIG_X86_INTEL_USERCOPY
439extern struct movsl_mask {
440 int mask;
441} ____cacheline_aligned_in_smp movsl_mask;
442#endif
443
444#define ARCH_HAS_NOCACHE_UACCESS 1
445
1#ifdef CONFIG_X86_32 446#ifdef CONFIG_X86_32
2# include "uaccess_32.h" 447# include "uaccess_32.h"
3#else 448#else
449# define ARCH_HAS_SEARCH_EXTABLE
4# include "uaccess_64.h" 450# include "uaccess_64.h"
5#endif 451#endif
452
453#endif
diff --git a/include/asm-x86/uaccess_32.h b/include/asm-x86/uaccess_32.h
index 8e7595c1f34e..6fdef39a0bcb 100644
--- a/include/asm-x86/uaccess_32.h
+++ b/include/asm-x86/uaccess_32.h
@@ -11,426 +11,6 @@
11#include <asm/asm.h> 11#include <asm/asm.h>
12#include <asm/page.h> 12#include <asm/page.h>
13 13
14#define VERIFY_READ 0
15#define VERIFY_WRITE 1
16
17/*
18 * The fs value determines whether argument validity checking should be
19 * performed or not. If get_fs() == USER_DS, checking is performed, with
20 * get_fs() == KERNEL_DS, checking is bypassed.
21 *
22 * For historical reasons, these macros are grossly misnamed.
23 */
24
25#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
26
27
28#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFUL)
29#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
30
31#define get_ds() (KERNEL_DS)
32#define get_fs() (current_thread_info()->addr_limit)
33#define set_fs(x) (current_thread_info()->addr_limit = (x))
34
35#define segment_eq(a, b) ((a).seg == (b).seg)
36
37/*
38 * movsl can be slow when source and dest are not both 8-byte aligned
39 */
40#ifdef CONFIG_X86_INTEL_USERCOPY
41extern struct movsl_mask {
42 int mask;
43} ____cacheline_aligned_in_smp movsl_mask;
44#endif
45
46#define __addr_ok(addr) \
47 ((unsigned long __force)(addr) < \
48 (current_thread_info()->addr_limit.seg))
49
50/*
51 * Test whether a block of memory is a valid user space address.
52 * Returns 0 if the range is valid, nonzero otherwise.
53 *
54 * This is equivalent to the following test:
55 * (u33)addr + (u33)size >= (u33)current->addr_limit.seg
56 *
57 * This needs 33-bit arithmetic. We have a carry...
58 */
59#define __range_ok(addr, size) \
60({ \
61 unsigned long flag, roksum; \
62 __chk_user_ptr(addr); \
63 asm("addl %3,%1 ; sbbl %0,%0; cmpl %1,%4; sbbl $0,%0" \
64 :"=&r" (flag), "=r" (roksum) \
65 :"1" (addr), "g" ((int)(size)), \
66 "rm" (current_thread_info()->addr_limit.seg)); \
67 flag; \
68})
69
70/**
71 * access_ok: - Checks if a user space pointer is valid
72 * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE. Note that
73 * %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
74 * to write to a block, it is always safe to read from it.
75 * @addr: User space pointer to start of block to check
76 * @size: Size of block to check
77 *
78 * Context: User context only. This function may sleep.
79 *
80 * Checks if a pointer to a block of memory in user space is valid.
81 *
82 * Returns true (nonzero) if the memory block may be valid, false (zero)
83 * if it is definitely invalid.
84 *
85 * Note that, depending on architecture, this function probably just
86 * checks that the pointer is in the user space range - after calling
87 * this function, memory access functions may still return -EFAULT.
88 */
89#define access_ok(type, addr, size) (likely(__range_ok(addr, size) == 0))
90
91/*
92 * The exception table consists of pairs of addresses: the first is the
93 * address of an instruction that is allowed to fault, and the second is
94 * the address at which the program should continue. No registers are
95 * modified, so it is entirely up to the continuation code to figure out
96 * what to do.
97 *
98 * All the routines below use bits of fixup code that are out of line
99 * with the main instruction path. This means when everything is well,
100 * we don't even have to jump over them. Further, they do not intrude
101 * on our cache or tlb entries.
102 */
103
104struct exception_table_entry {
105 unsigned long insn, fixup;
106};
107
108extern int fixup_exception(struct pt_regs *regs);
109
110/*
111 * These are the main single-value transfer routines. They automatically
112 * use the right size if we just have the right pointer type.
113 *
114 * This gets kind of ugly. We want to return _two_ values in "get_user()"
115 * and yet we don't want to do any pointers, because that is too much
116 * of a performance impact. Thus we have a few rather ugly macros here,
117 * and hide all the ugliness from the user.
118 *
119 * The "__xxx" versions of the user access functions are versions that
120 * do not verify the address space, that must have been done previously
121 * with a separate "access_ok()" call (this is used when we do multiple
122 * accesses to the same area of user memory).
123 */
124
125extern void __get_user_1(void);
126extern void __get_user_2(void);
127extern void __get_user_4(void);
128
129#define __get_user_x(size, ret, x, ptr) \
130 asm volatile("call __get_user_" #size \
131 :"=a" (ret),"=d" (x) \
132 :"0" (ptr))
133
134
135/* Careful: we have to cast the result to the type of the pointer
136 * for sign reasons */
137
138/**
139 * get_user: - Get a simple variable from user space.
140 * @x: Variable to store result.
141 * @ptr: Source address, in user space.
142 *
143 * Context: User context only. This function may sleep.
144 *
145 * This macro copies a single simple variable from user space to kernel
146 * space. It supports simple types like char and int, but not larger
147 * data types like structures or arrays.
148 *
149 * @ptr must have pointer-to-simple-variable type, and the result of
150 * dereferencing @ptr must be assignable to @x without a cast.
151 *
152 * Returns zero on success, or -EFAULT on error.
153 * On error, the variable @x is set to zero.
154 */
155#define get_user(x, ptr) \
156({ \
157 int __ret_gu; \
158 unsigned long __val_gu; \
159 __chk_user_ptr(ptr); \
160 switch (sizeof(*(ptr))) { \
161 case 1: \
162 __get_user_x(1, __ret_gu, __val_gu, ptr); \
163 break; \
164 case 2: \
165 __get_user_x(2, __ret_gu, __val_gu, ptr); \
166 break; \
167 case 4: \
168 __get_user_x(4, __ret_gu, __val_gu, ptr); \
169 break; \
170 default: \
171 __get_user_x(X, __ret_gu, __val_gu, ptr); \
172 break; \
173 } \
174 (x) = (__typeof__(*(ptr)))__val_gu; \
175 __ret_gu; \
176})
177
178extern void __put_user_bad(void);
179
180/*
181 * Strange magic calling convention: pointer in %ecx,
182 * value in %eax(:%edx), return value in %eax, no clobbers.
183 */
184extern void __put_user_1(void);
185extern void __put_user_2(void);
186extern void __put_user_4(void);
187extern void __put_user_8(void);
188
189#define __put_user_1(x, ptr) \
190 asm volatile("call __put_user_1" : "=a" (__ret_pu) \
191 : "0" ((typeof(*(ptr)))(x)), "c" (ptr))
192
193#define __put_user_2(x, ptr) \
194 asm volatile("call __put_user_2" : "=a" (__ret_pu) \
195 : "0" ((typeof(*(ptr)))(x)), "c" (ptr))
196
197#define __put_user_4(x, ptr) \
198 asm volatile("call __put_user_4" : "=a" (__ret_pu) \
199 : "0" ((typeof(*(ptr)))(x)), "c" (ptr))
200
201#define __put_user_8(x, ptr) \
202 asm volatile("call __put_user_8" : "=a" (__ret_pu) \
203 : "A" ((typeof(*(ptr)))(x)), "c" (ptr))
204
205#define __put_user_X(x, ptr) \
206 asm volatile("call __put_user_X" : "=a" (__ret_pu) \
207 : "c" (ptr))
208
209/**
210 * put_user: - Write a simple value into user space.
211 * @x: Value to copy to user space.
212 * @ptr: Destination address, in user space.
213 *
214 * Context: User context only. This function may sleep.
215 *
216 * This macro copies a single simple value from kernel space to user
217 * space. It supports simple types like char and int, but not larger
218 * data types like structures or arrays.
219 *
220 * @ptr must have pointer-to-simple-variable type, and @x must be assignable
221 * to the result of dereferencing @ptr.
222 *
223 * Returns zero on success, or -EFAULT on error.
224 */
225#ifdef CONFIG_X86_WP_WORKS_OK
226
227#define put_user(x, ptr) \
228({ \
229 int __ret_pu; \
230 __typeof__(*(ptr)) __pu_val; \
231 __chk_user_ptr(ptr); \
232 __pu_val = x; \
233 switch (sizeof(*(ptr))) { \
234 case 1: \
235 __put_user_1(__pu_val, ptr); \
236 break; \
237 case 2: \
238 __put_user_2(__pu_val, ptr); \
239 break; \
240 case 4: \
241 __put_user_4(__pu_val, ptr); \
242 break; \
243 case 8: \
244 __put_user_8(__pu_val, ptr); \
245 break; \
246 default: \
247 __put_user_X(__pu_val, ptr); \
248 break; \
249 } \
250 __ret_pu; \
251})
252
253#else
254#define put_user(x, ptr) \
255({ \
256 int __ret_pu; \
257 __typeof__(*(ptr))__pus_tmp = x; \
258 __ret_pu = 0; \
259 if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, \
260 sizeof(*(ptr))) != 0)) \
261 __ret_pu = -EFAULT; \
262 __ret_pu; \
263})
264
265
266#endif
267
268/**
269 * __get_user: - Get a simple variable from user space, with less checking.
270 * @x: Variable to store result.
271 * @ptr: Source address, in user space.
272 *
273 * Context: User context only. This function may sleep.
274 *
275 * This macro copies a single simple variable from user space to kernel
276 * space. It supports simple types like char and int, but not larger
277 * data types like structures or arrays.
278 *
279 * @ptr must have pointer-to-simple-variable type, and the result of
280 * dereferencing @ptr must be assignable to @x without a cast.
281 *
282 * Caller must check the pointer with access_ok() before calling this
283 * function.
284 *
285 * Returns zero on success, or -EFAULT on error.
286 * On error, the variable @x is set to zero.
287 */
288#define __get_user(x, ptr) \
289 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
290
291
292/**
293 * __put_user: - Write a simple value into user space, with less checking.
294 * @x: Value to copy to user space.
295 * @ptr: Destination address, in user space.
296 *
297 * Context: User context only. This function may sleep.
298 *
299 * This macro copies a single simple value from kernel space to user
300 * space. It supports simple types like char and int, but not larger
301 * data types like structures or arrays.
302 *
303 * @ptr must have pointer-to-simple-variable type, and @x must be assignable
304 * to the result of dereferencing @ptr.
305 *
306 * Caller must check the pointer with access_ok() before calling this
307 * function.
308 *
309 * Returns zero on success, or -EFAULT on error.
310 */
311#define __put_user(x, ptr) \
312 __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
313
314#define __put_user_nocheck(x, ptr, size) \
315({ \
316 long __pu_err; \
317 __put_user_size((x), (ptr), (size), __pu_err, -EFAULT); \
318 __pu_err; \
319})
320
321
322#define __put_user_u64(x, addr, err) \
323 asm volatile("1: movl %%eax,0(%2)\n" \
324 "2: movl %%edx,4(%2)\n" \
325 "3:\n" \
326 ".section .fixup,\"ax\"\n" \
327 "4: movl %3,%0\n" \
328 " jmp 3b\n" \
329 ".previous\n" \
330 _ASM_EXTABLE(1b, 4b) \
331 _ASM_EXTABLE(2b, 4b) \
332 : "=r" (err) \
333 : "A" (x), "r" (addr), "i" (-EFAULT), "0" (err))
334
335#ifdef CONFIG_X86_WP_WORKS_OK
336
337#define __put_user_size(x, ptr, size, retval, errret) \
338do { \
339 retval = 0; \
340 __chk_user_ptr(ptr); \
341 switch (size) { \
342 case 1: \
343 __put_user_asm(x, ptr, retval, "b", "b", "iq", errret); \
344 break; \
345 case 2: \
346 __put_user_asm(x, ptr, retval, "w", "w", "ir", errret); \
347 break; \
348 case 4: \
349 __put_user_asm(x, ptr, retval, "l", "", "ir", errret); \
350 break; \
351 case 8: \
352 __put_user_u64((__typeof__(*ptr))(x), ptr, retval); \
353 break; \
354 default: \
355 __put_user_bad(); \
356 } \
357} while (0)
358
359#else
360
361#define __put_user_size(x, ptr, size, retval, errret) \
362do { \
363 __typeof__(*(ptr))__pus_tmp = x; \
364 retval = 0; \
365 \
366 if (unlikely(__copy_to_user_ll(ptr, &__pus_tmp, size) != 0)) \
367 retval = errret; \
368} while (0)
369
370#endif
371struct __large_struct { unsigned long buf[100]; };
372#define __m(x) (*(struct __large_struct __user *)(x))
373
374/*
375 * Tell gcc we read from memory instead of writing: this is because
376 * we do not write to any memory gcc knows about, so there are no
377 * aliasing issues.
378 */
379#define __put_user_asm(x, addr, err, itype, rtype, ltype, errret) \
380 asm volatile("1: mov"itype" %"rtype"1,%2\n" \
381 "2:\n" \
382 ".section .fixup,\"ax\"\n" \
383 "3: movl %3,%0\n" \
384 " jmp 2b\n" \
385 ".previous\n" \
386 _ASM_EXTABLE(1b, 3b) \
387 : "=r"(err) \
388 : ltype (x), "m" (__m(addr)), "i" (errret), "0" (err))
389
390
391#define __get_user_nocheck(x, ptr, size) \
392({ \
393 long __gu_err; \
394 unsigned long __gu_val; \
395 __get_user_size(__gu_val, (ptr), (size), __gu_err, -EFAULT); \
396 (x) = (__typeof__(*(ptr)))__gu_val; \
397 __gu_err; \
398})
399
400extern long __get_user_bad(void);
401
402#define __get_user_size(x, ptr, size, retval, errret) \
403do { \
404 retval = 0; \
405 __chk_user_ptr(ptr); \
406 switch (size) { \
407 case 1: \
408 __get_user_asm(x, ptr, retval, "b", "b", "=q", errret); \
409 break; \
410 case 2: \
411 __get_user_asm(x, ptr, retval, "w", "w", "=r", errret); \
412 break; \
413 case 4: \
414 __get_user_asm(x, ptr, retval, "l", "", "=r", errret); \
415 break; \
416 default: \
417 (x) = __get_user_bad(); \
418 } \
419} while (0)
420
421#define __get_user_asm(x, addr, err, itype, rtype, ltype, errret) \
422 asm volatile("1: mov"itype" %2,%"rtype"1\n" \
423 "2:\n" \
424 ".section .fixup,\"ax\"\n" \
425 "3: movl %3,%0\n" \
426 " xor"itype" %"rtype"1,%"rtype"1\n" \
427 " jmp 2b\n" \
428 ".previous\n" \
429 _ASM_EXTABLE(1b, 3b) \
430 : "=r" (err), ltype (x) \
431 : "m" (__m(addr)), "i" (errret), "0" (err))
432
433
434unsigned long __must_check __copy_to_user_ll 14unsigned long __must_check __copy_to_user_ll
435 (void __user *to, const void *from, unsigned long n); 15 (void __user *to, const void *from, unsigned long n);
436unsigned long __must_check __copy_from_user_ll 16unsigned long __must_check __copy_from_user_ll
@@ -576,8 +156,6 @@ __copy_from_user(void *to, const void __user *from, unsigned long n)
576 return __copy_from_user_ll(to, from, n); 156 return __copy_from_user_ll(to, from, n);
577} 157}
578 158
579#define ARCH_HAS_NOCACHE_UACCESS
580
581static __always_inline unsigned long __copy_from_user_nocache(void *to, 159static __always_inline unsigned long __copy_from_user_nocache(void *to,
582 const void __user *from, unsigned long n) 160 const void __user *from, unsigned long n)
583{ 161{
diff --git a/include/asm-x86/uaccess_64.h b/include/asm-x86/uaccess_64.h
index b8a2f4339903..515d4dce96b5 100644
--- a/include/asm-x86/uaccess_64.h
+++ b/include/asm-x86/uaccess_64.h
@@ -9,265 +9,6 @@
9#include <linux/prefetch.h> 9#include <linux/prefetch.h>
10#include <asm/page.h> 10#include <asm/page.h>
11 11
12#define VERIFY_READ 0
13#define VERIFY_WRITE 1
14
15/*
16 * The fs value determines whether argument validity checking should be
17 * performed or not. If get_fs() == USER_DS, checking is performed, with
18 * get_fs() == KERNEL_DS, checking is bypassed.
19 *
20 * For historical reasons, these macros are grossly misnamed.
21 */
22
23#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) })
24
25#define KERNEL_DS MAKE_MM_SEG(0xFFFFFFFFFFFFFFFFUL)
26#define USER_DS MAKE_MM_SEG(PAGE_OFFSET)
27
28#define get_ds() (KERNEL_DS)
29#define get_fs() (current_thread_info()->addr_limit)
30#define set_fs(x) (current_thread_info()->addr_limit = (x))
31
32#define segment_eq(a, b) ((a).seg == (b).seg)
33
34#define __addr_ok(addr) (!((unsigned long)(addr) & \
35 (current_thread_info()->addr_limit.seg)))
36
37/*
38 * Uhhuh, this needs 65-bit arithmetic. We have a carry..
39 */
40#define __range_not_ok(addr, size) \
41({ \
42 unsigned long flag, roksum; \
43 __chk_user_ptr(addr); \
44 asm("# range_ok\n\r" \
45 "addq %3,%1 ; sbbq %0,%0 ; cmpq %1,%4 ; sbbq $0,%0" \
46 : "=&r" (flag), "=r" (roksum) \
47 : "1" (addr), "g" ((long)(size)), \
48 "g" (current_thread_info()->addr_limit.seg)); \
49 flag; \
50})
51
52#define access_ok(type, addr, size) (__range_not_ok(addr, size) == 0)
53
54/*
55 * The exception table consists of pairs of addresses: the first is the
56 * address of an instruction that is allowed to fault, and the second is
57 * the address at which the program should continue. No registers are
58 * modified, so it is entirely up to the continuation code to figure out
59 * what to do.
60 *
61 * All the routines below use bits of fixup code that are out of line
62 * with the main instruction path. This means when everything is well,
63 * we don't even have to jump over them. Further, they do not intrude
64 * on our cache or tlb entries.
65 */
66
67struct exception_table_entry {
68 unsigned long insn, fixup;
69};
70
71extern int fixup_exception(struct pt_regs *regs);
72
73#define ARCH_HAS_SEARCH_EXTABLE
74
75/*
76 * These are the main single-value transfer routines. They automatically
77 * use the right size if we just have the right pointer type.
78 *
79 * This gets kind of ugly. We want to return _two_ values in "get_user()"
80 * and yet we don't want to do any pointers, because that is too much
81 * of a performance impact. Thus we have a few rather ugly macros here,
82 * and hide all the ugliness from the user.
83 *
84 * The "__xxx" versions of the user access functions are versions that
85 * do not verify the address space, that must have been done previously
86 * with a separate "access_ok()" call (this is used when we do multiple
87 * accesses to the same area of user memory).
88 */
89
90#define __get_user_x(size, ret, x, ptr) \
91 asm volatile("call __get_user_" #size \
92 : "=a" (ret),"=d" (x) \
93 : "c" (ptr) \
94 : "r8")
95
96/* Careful: we have to cast the result to the type of the pointer
97 * for sign reasons */
98
99#define get_user(x, ptr) \
100({ \
101 unsigned long __val_gu; \
102 int __ret_gu; \
103 __chk_user_ptr(ptr); \
104 switch (sizeof(*(ptr))) { \
105 case 1: \
106 __get_user_x(1, __ret_gu, __val_gu, ptr); \
107 break; \
108 case 2: \
109 __get_user_x(2, __ret_gu, __val_gu, ptr); \
110 break; \
111 case 4: \
112 __get_user_x(4, __ret_gu, __val_gu, ptr); \
113 break; \
114 case 8: \
115 __get_user_x(8, __ret_gu, __val_gu, ptr); \
116 break; \
117 default: \
118 __get_user_bad(); \
119 break; \
120 } \
121 (x) = (__force typeof(*(ptr)))__val_gu; \
122 __ret_gu; \
123})
124
125extern void __put_user_1(void);
126extern void __put_user_2(void);
127extern void __put_user_4(void);
128extern void __put_user_8(void);
129extern void __put_user_bad(void);
130
131#define __put_user_x(size, ret, x, ptr) \
132 asm volatile("call __put_user_" #size \
133 :"=a" (ret) \
134 :"c" (ptr),"d" (x) \
135 :"r8")
136
137#define put_user(x, ptr) \
138 __put_user_check((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
139
140#define __get_user(x, ptr) \
141 __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
142#define __put_user(x, ptr) \
143 __put_user_nocheck((__typeof__(*(ptr)))(x), (ptr), sizeof(*(ptr)))
144
145#define __get_user_unaligned __get_user
146#define __put_user_unaligned __put_user
147
148#define __put_user_nocheck(x, ptr, size) \
149({ \
150 int __pu_err; \
151 __put_user_size((x), (ptr), (size), __pu_err); \
152 __pu_err; \
153})
154
155
156#define __put_user_check(x, ptr, size) \
157({ \
158 int __pu_err; \
159 typeof(*(ptr)) __user *__pu_addr = (ptr); \
160 switch (size) { \
161 case 1: \
162 __put_user_x(1, __pu_err, x, __pu_addr); \
163 break; \
164 case 2: \
165 __put_user_x(2, __pu_err, x, __pu_addr); \
166 break; \
167 case 4: \
168 __put_user_x(4, __pu_err, x, __pu_addr); \
169 break; \
170 case 8: \
171 __put_user_x(8, __pu_err, x, __pu_addr); \
172 break; \
173 default: \
174 __put_user_bad(); \
175 } \
176 __pu_err; \
177})
178
179#define __put_user_size(x, ptr, size, retval) \
180do { \
181 retval = 0; \
182 __chk_user_ptr(ptr); \
183 switch (size) { \
184 case 1: \
185 __put_user_asm(x, ptr, retval, "b", "b", "iq", -EFAULT);\
186 break; \
187 case 2: \
188 __put_user_asm(x, ptr, retval, "w", "w", "ir", -EFAULT);\
189 break; \
190 case 4: \
191 __put_user_asm(x, ptr, retval, "l", "k", "ir", -EFAULT);\
192 break; \
193 case 8: \
194 __put_user_asm(x, ptr, retval, "q", "", "Zr", -EFAULT); \
195 break; \
196 default: \
197 __put_user_bad(); \
198 } \
199} while (0)
200
201/* FIXME: this hack is definitely wrong -AK */
202struct __large_struct { unsigned long buf[100]; };
203#define __m(x) (*(struct __large_struct __user *)(x))
204
205/*
206 * Tell gcc we read from memory instead of writing: this is because
207 * we do not write to any memory gcc knows about, so there are no
208 * aliasing issues.
209 */
210#define __put_user_asm(x, addr, err, itype, rtype, ltype, errno) \
211 asm volatile("1: mov"itype" %"rtype"1,%2\n" \
212 "2:\n" \
213 ".section .fixup, \"ax\"\n" \
214 "3: mov %3,%0\n" \
215 " jmp 2b\n" \
216 ".previous\n" \
217 _ASM_EXTABLE(1b, 3b) \
218 : "=r"(err) \
219 : ltype (x), "m" (__m(addr)), "i" (errno), "0" (err))
220
221
222#define __get_user_nocheck(x, ptr, size) \
223({ \
224 int __gu_err; \
225 unsigned long __gu_val; \
226 __get_user_size(__gu_val, (ptr), (size), __gu_err); \
227 (x) = (__force typeof(*(ptr)))__gu_val; \
228 __gu_err; \
229})
230
231extern int __get_user_1(void);
232extern int __get_user_2(void);
233extern int __get_user_4(void);
234extern int __get_user_8(void);
235extern int __get_user_bad(void);
236
237#define __get_user_size(x, ptr, size, retval) \
238do { \
239 retval = 0; \
240 __chk_user_ptr(ptr); \
241 switch (size) { \
242 case 1: \
243 __get_user_asm(x, ptr, retval, "b", "b", "=q", -EFAULT);\
244 break; \
245 case 2: \
246 __get_user_asm(x, ptr, retval, "w", "w", "=r", -EFAULT);\
247 break; \
248 case 4: \
249 __get_user_asm(x, ptr, retval, "l", "k", "=r", -EFAULT);\
250 break; \
251 case 8: \
252 __get_user_asm(x, ptr, retval, "q", "", "=r", -EFAULT); \
253 break; \
254 default: \
255 (x) = __get_user_bad(); \
256 } \
257} while (0)
258
259#define __get_user_asm(x, addr, err, itype, rtype, ltype, errno) \
260 asm volatile("1: mov"itype" %2,%"rtype"1\n" \
261 "2:\n" \
262 ".section .fixup, \"ax\"\n" \
263 "3: mov %3,%0\n" \
264 " xor"itype" %"rtype"1,%"rtype"1\n" \
265 " jmp 2b\n" \
266 ".previous\n" \
267 _ASM_EXTABLE(1b, 3b) \
268 : "=r" (err), ltype (x) \
269 : "m" (__m(addr)), "i"(errno), "0"(err))
270
271/* 12/*
272 * Copy To/From Userspace 13 * Copy To/From Userspace
273 */ 14 */
@@ -437,7 +178,6 @@ __copy_to_user_inatomic(void __user *dst, const void *src, unsigned size)
437 return copy_user_generic((__force void *)dst, src, size); 178 return copy_user_generic((__force void *)dst, src, size);
438} 179}
439 180
440#define ARCH_HAS_NOCACHE_UACCESS 1
441extern long __copy_user_nocache(void *dst, const void __user *src, 181extern long __copy_user_nocache(void *dst, const void __user *src,
442 unsigned size, int zerorest); 182 unsigned size, int zerorest);
443 183
@@ -455,4 +195,7 @@ static inline int __copy_from_user_inatomic_nocache(void *dst,
455 return __copy_user_nocache(dst, src, size, 0); 195 return __copy_user_nocache(dst, src, size, 0);
456} 196}
457 197
198unsigned long
199copy_user_handle_tail(char *to, char *from, unsigned len, unsigned zerorest);
200
458#endif /* __X86_64_UACCESS_H */ 201#endif /* __X86_64_UACCESS_H */
diff --git a/include/asm-x86/unistd_64.h b/include/asm-x86/unistd_64.h
index fe26e36d0f51..9c1a4a3470d9 100644
--- a/include/asm-x86/unistd_64.h
+++ b/include/asm-x86/unistd_64.h
@@ -290,7 +290,7 @@ __SYSCALL(__NR_rt_sigtimedwait, sys_rt_sigtimedwait)
290#define __NR_rt_sigqueueinfo 129 290#define __NR_rt_sigqueueinfo 129
291__SYSCALL(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo) 291__SYSCALL(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo)
292#define __NR_rt_sigsuspend 130 292#define __NR_rt_sigsuspend 130
293__SYSCALL(__NR_rt_sigsuspend, stub_rt_sigsuspend) 293__SYSCALL(__NR_rt_sigsuspend, sys_rt_sigsuspend)
294#define __NR_sigaltstack 131 294#define __NR_sigaltstack 131
295__SYSCALL(__NR_sigaltstack, stub_sigaltstack) 295__SYSCALL(__NR_sigaltstack, stub_sigaltstack)
296#define __NR_utime 132 296#define __NR_utime 132
diff --git a/include/asm-x86/uv/uv_bau.h b/include/asm-x86/uv/uv_bau.h
new file mode 100644
index 000000000000..91ac0dfb7588
--- /dev/null
+++ b/include/asm-x86/uv/uv_bau.h
@@ -0,0 +1,337 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * SGI UV Broadcast Assist Unit definitions
7 *
8 * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
9 */
10
11#ifndef __ASM_X86_UV_BAU__
12#define __ASM_X86_UV_BAU__
13
14#include <linux/bitmap.h>
15#define BITSPERBYTE 8
16
17/*
18 * Broadcast Assist Unit messaging structures
19 *
20 * Selective Broadcast activations are induced by software action
21 * specifying a particular 8-descriptor "set" via a 6-bit index written
22 * to an MMR.
23 * Thus there are 64 unique 512-byte sets of SB descriptors - one set for
24 * each 6-bit index value. These descriptor sets are mapped in sequence
25 * starting with set 0 located at the address specified in the
26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
28 *
29 * We will use 31 sets, one for sending BAU messages from each of the 32
30 * cpu's on the node.
31 *
32 * TLB shootdown will use the first of the 8 descriptors of each set.
33 * Each of the descriptors is 64 bytes in size (8*64 = 512 bytes in a set).
34 */
35
36#define UV_ITEMS_PER_DESCRIPTOR 8
37#define UV_CPUS_PER_ACT_STATUS 32
38#define UV_ACT_STATUS_MASK 0x3
39#define UV_ACT_STATUS_SIZE 2
40#define UV_ACTIVATION_DESCRIPTOR_SIZE 32
41#define UV_DISTRIBUTION_SIZE 256
42#define UV_SW_ACK_NPENDING 8
43#define UV_BAU_MESSAGE 200
44/*
45 * Messaging irq; see irq_64.h and include/asm-x86/hw_irq_64.h
46 * To be dynamically allocated in the future
47 */
48#define UV_NET_ENDPOINT_INTD 0x38
49#define UV_DESC_BASE_PNODE_SHIFT 49
50#define UV_PAYLOADQ_PNODE_SHIFT 49
51#define UV_PTC_BASENAME "sgi_uv/ptc_statistics"
52#define uv_physnodeaddr(x) ((__pa((unsigned long)(x)) & uv_mmask))
53
54/*
55 * bits in UVH_LB_BAU_SB_ACTIVATION_STATUS_0/1
56 */
57#define DESC_STATUS_IDLE 0
58#define DESC_STATUS_ACTIVE 1
59#define DESC_STATUS_DESTINATION_TIMEOUT 2
60#define DESC_STATUS_SOURCE_TIMEOUT 3
61
62/*
63 * source side threshholds at which message retries print a warning
64 */
65#define SOURCE_TIMEOUT_LIMIT 20
66#define DESTINATION_TIMEOUT_LIMIT 20
67
68/*
69 * number of entries in the destination side payload queue
70 */
71#define DEST_Q_SIZE 17
72/*
73 * number of destination side software ack resources
74 */
75#define DEST_NUM_RESOURCES 8
76#define MAX_CPUS_PER_NODE 32
77/*
78 * completion statuses for sending a TLB flush message
79 */
80#define FLUSH_RETRY 1
81#define FLUSH_GIVEUP 2
82#define FLUSH_COMPLETE 3
83
84/*
85 * Distribution: 32 bytes (256 bits) (bytes 0-0x1f of descriptor)
86 * If the 'multilevel' flag in the header portion of the descriptor
87 * has been set to 0, then endpoint multi-unicast mode is selected.
88 * The distribution specification (32 bytes) is interpreted as a 256-bit
89 * distribution vector. Adjacent bits correspond to consecutive even numbered
90 * nodeIDs. The result of adding the index of a given bit to the 15-bit
91 * 'base_dest_nodeid' field of the header corresponds to the
92 * destination nodeID associated with that specified bit.
93 */
94struct bau_target_nodemask {
95 unsigned long bits[BITS_TO_LONGS(256)];
96};
97
98/*
99 * mask of cpu's on a node
100 * (during initialization we need to check that unsigned long has
101 * enough bits for max. cpu's per node)
102 */
103struct bau_local_cpumask {
104 unsigned long bits;
105};
106
107/*
108 * Payload: 16 bytes (128 bits) (bytes 0x20-0x2f of descriptor)
109 * only 12 bytes (96 bits) of the payload area are usable.
110 * An additional 3 bytes (bits 27:4) of the header address are carried
111 * to the next bytes of the destination payload queue.
112 * And an additional 2 bytes of the header Suppl_A field are also
113 * carried to the destination payload queue.
114 * But the first byte of the Suppl_A becomes bits 127:120 (the 16th byte)
115 * of the destination payload queue, which is written by the hardware
116 * with the s/w ack resource bit vector.
117 * [ effective message contents (16 bytes (128 bits) maximum), not counting
118 * the s/w ack bit vector ]
119 */
120
121/*
122 * The payload is software-defined for INTD transactions
123 */
124struct bau_msg_payload {
125 unsigned long address; /* signifies a page or all TLB's
126 of the cpu */
127 /* 64 bits */
128 unsigned short sending_cpu; /* filled in by sender */
129 /* 16 bits */
130 unsigned short acknowledge_count;/* filled in by destination */
131 /* 16 bits */
132 unsigned int reserved1:32; /* not usable */
133};
134
135
136/*
137 * Message header: 16 bytes (128 bits) (bytes 0x30-0x3f of descriptor)
138 * see table 4.2.3.0.1 in broacast_assist spec.
139 */
140struct bau_msg_header {
141 int dest_subnodeid:6; /* must be zero */
142 /* bits 5:0 */
143 int base_dest_nodeid:15; /* nasid>>1 (pnode) of first bit in node_map */
144 /* bits 20:6 */
145 int command:8; /* message type */
146 /* bits 28:21 */
147 /* 0x38: SN3net EndPoint Message */
148 int rsvd_1:3; /* must be zero */
149 /* bits 31:29 */
150 /* int will align on 32 bits */
151 int rsvd_2:9; /* must be zero */
152 /* bits 40:32 */
153 /* Suppl_A is 56-41 */
154 int payload_2a:8; /* becomes byte 16 of msg */
155 /* bits 48:41 */ /* not currently using */
156 int payload_2b:8; /* becomes byte 17 of msg */
157 /* bits 56:49 */ /* not currently using */
158 /* Address field (96:57) is never used as an
159 address (these are address bits 42:3) */
160 int rsvd_3:1; /* must be zero */
161 /* bit 57 */
162 /* address bits 27:4 are payload */
163 /* these 24 bits become bytes 12-14 of msg */
164 int replied_to:1; /* sent as 0 by the source to byte 12 */
165 /* bit 58 */
166
167 int payload_1a:5; /* not currently used */
168 /* bits 63:59 */
169 int payload_1b:8; /* not currently used */
170 /* bits 71:64 */
171 int payload_1c:8; /* not currently used */
172 /* bits 79:72 */
173 int payload_1d:2; /* not currently used */
174 /* bits 81:80 */
175
176 int rsvd_4:7; /* must be zero */
177 /* bits 88:82 */
178 int sw_ack_flag:1; /* software acknowledge flag */
179 /* bit 89 */
180 /* INTD trasactions at destination are to
181 wait for software acknowledge */
182 int rsvd_5:6; /* must be zero */
183 /* bits 95:90 */
184 int rsvd_6:5; /* must be zero */
185 /* bits 100:96 */
186 int int_both:1; /* if 1, interrupt both sockets on the blade */
187 /* bit 101*/
188 int fairness:3; /* usually zero */
189 /* bits 104:102 */
190 int multilevel:1; /* multi-level multicast format */
191 /* bit 105 */
192 /* 0 for TLB: endpoint multi-unicast messages */
193 int chaining:1; /* next descriptor is part of this activation*/
194 /* bit 106 */
195 int rsvd_7:21; /* must be zero */
196 /* bits 127:107 */
197};
198
199/*
200 * The activation descriptor:
201 * The format of the message to send, plus all accompanying control
202 * Should be 64 bytes
203 */
204struct bau_desc {
205 struct bau_target_nodemask distribution;
206 /*
207 * message template, consisting of header and payload:
208 */
209 struct bau_msg_header header;
210 struct bau_msg_payload payload;
211};
212/*
213 * -payload-- ---------header------
214 * bytes 0-11 bits 41-56 bits 58-81
215 * A B (2) C (3)
216 *
217 * A/B/C are moved to:
218 * A C B
219 * bytes 0-11 bytes 12-14 bytes 16-17 (byte 15 filled in by hw as vector)
220 * ------------payload queue-----------
221 */
222
223/*
224 * The payload queue on the destination side is an array of these.
225 * With BAU_MISC_CONTROL set for software acknowledge mode, the messages
226 * are 32 bytes (2 micropackets) (256 bits) in length, but contain only 17
227 * bytes of usable data, including the sw ack vector in byte 15 (bits 127:120)
228 * (12 bytes come from bau_msg_payload, 3 from payload_1, 2 from
229 * sw_ack_vector and payload_2)
230 * "Enabling Software Acknowledgment mode (see Section 4.3.3 Software
231 * Acknowledge Processing) also selects 32 byte (17 bytes usable) payload
232 * operation."
233 */
234struct bau_payload_queue_entry {
235 unsigned long address; /* signifies a page or all TLB's
236 of the cpu */
237 /* 64 bits, bytes 0-7 */
238
239 unsigned short sending_cpu; /* cpu that sent the message */
240 /* 16 bits, bytes 8-9 */
241
242 unsigned short acknowledge_count; /* filled in by destination */
243 /* 16 bits, bytes 10-11 */
244
245 unsigned short replied_to:1; /* sent as 0 by the source */
246 /* 1 bit */
247 unsigned short unused1:7; /* not currently using */
248 /* 7 bits: byte 12) */
249
250 unsigned char unused2[2]; /* not currently using */
251 /* bytes 13-14 */
252
253 unsigned char sw_ack_vector; /* filled in by the hardware */
254 /* byte 15 (bits 127:120) */
255
256 unsigned char unused4[3]; /* not currently using bytes 17-19 */
257 /* bytes 17-19 */
258
259 int number_of_cpus; /* filled in at destination */
260 /* 32 bits, bytes 20-23 (aligned) */
261
262 unsigned char unused5[8]; /* not using */
263 /* bytes 24-31 */
264};
265
266/*
267 * one for every slot in the destination payload queue
268 */
269struct bau_msg_status {
270 struct bau_local_cpumask seen_by; /* map of cpu's */
271};
272
273/*
274 * one for every slot in the destination software ack resources
275 */
276struct bau_sw_ack_status {
277 struct bau_payload_queue_entry *msg; /* associated message */
278 int watcher; /* cpu monitoring, or -1 */
279};
280
281/*
282 * one on every node and per-cpu; to locate the software tables
283 */
284struct bau_control {
285 struct bau_desc *descriptor_base;
286 struct bau_payload_queue_entry *bau_msg_head;
287 struct bau_payload_queue_entry *va_queue_first;
288 struct bau_payload_queue_entry *va_queue_last;
289 struct bau_msg_status *msg_statuses;
290 int *watching; /* pointer to array */
291};
292
293/*
294 * This structure is allocated per_cpu for UV TLB shootdown statistics.
295 */
296struct ptc_stats {
297 unsigned long ptc_i; /* number of IPI-style flushes */
298 unsigned long requestor; /* number of nodes this cpu sent to */
299 unsigned long requestee; /* times cpu was remotely requested */
300 unsigned long alltlb; /* times all tlb's on this cpu were flushed */
301 unsigned long onetlb; /* times just one tlb on this cpu was flushed */
302 unsigned long s_retry; /* retries on source side timeouts */
303 unsigned long d_retry; /* retries on destination side timeouts */
304 unsigned long sflush; /* cycles spent in uv_flush_tlb_others */
305 unsigned long dflush; /* cycles spent on destination side */
306 unsigned long retriesok; /* successes on retries */
307 unsigned long nomsg; /* interrupts with no message */
308 unsigned long multmsg; /* interrupts with multiple messages */
309 unsigned long ntargeted;/* nodes targeted */
310};
311
312static inline int bau_node_isset(int node, struct bau_target_nodemask *dstp)
313{
314 return constant_test_bit(node, &dstp->bits[0]);
315}
316static inline void bau_node_set(int node, struct bau_target_nodemask *dstp)
317{
318 __set_bit(node, &dstp->bits[0]);
319}
320static inline void bau_nodes_clear(struct bau_target_nodemask *dstp, int nbits)
321{
322 bitmap_zero(&dstp->bits[0], nbits);
323}
324
325static inline void bau_cpubits_clear(struct bau_local_cpumask *dstp, int nbits)
326{
327 bitmap_zero(&dstp->bits, nbits);
328}
329
330#define cpubit_isset(cpu, bau_local_cpumask) \
331 test_bit((cpu), (bau_local_cpumask).bits)
332
333extern int uv_flush_tlb_others(cpumask_t *, struct mm_struct *, unsigned long);
334extern void uv_bau_message_intr1(void);
335extern void uv_bau_timeout_intr1(void);
336
337#endif /* __ASM_X86_UV_BAU__ */
diff --git a/include/asm-x86/uv/uv_hub.h b/include/asm-x86/uv/uv_hub.h
index 26b9240d1e23..a4ef26e5850b 100644
--- a/include/asm-x86/uv/uv_hub.h
+++ b/include/asm-x86/uv/uv_hub.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * SGI UV architectural definitions 6 * SGI UV architectural definitions
7 * 7 *
8 * Copyright (C) 2007 Silicon Graphics, Inc. All rights reserved. 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
9 */ 9 */
10 10
11#ifndef __ASM_X86_UV_HUB_H__ 11#ifndef __ASM_X86_UV_HUB_H__
@@ -20,26 +20,49 @@
20/* 20/*
21 * Addressing Terminology 21 * Addressing Terminology
22 * 22 *
23 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of 23 * M - The low M bits of a physical address represent the offset
24 * routers always have low bit of 1, C/MBricks have low bit 24 * into the blade local memory. RAM memory on a blade is physically
25 * equal to 0. Most addressing macros that target UV hub chips 25 * contiguous (although various IO spaces may punch holes in
26 * right shift the NASID by 1 to exclude the always-zero bit. 26 * it)..
27 * 27 *
28 * SNASID - NASID right shifted by 1 bit. 28 * N - Number of bits in the node portion of a socket physical
29 * address.
30 *
31 * NASID - network ID of a router, Mbrick or Cbrick. Nasid values of
32 * routers always have low bit of 1, C/MBricks have low bit
33 * equal to 0. Most addressing macros that target UV hub chips
34 * right shift the NASID by 1 to exclude the always-zero bit.
35 * NASIDs contain up to 15 bits.
36 *
37 * GNODE - NASID right shifted by 1 bit. Most mmrs contain gnodes instead
38 * of nasids.
39 *
40 * PNODE - the low N bits of the GNODE. The PNODE is the most useful variant
41 * of the nasid for socket usage.
42 *
43 *
44 * NumaLink Global Physical Address Format:
45 * +--------------------------------+---------------------+
46 * |00..000| GNODE | NodeOffset |
47 * +--------------------------------+---------------------+
48 * |<-------53 - M bits --->|<--------M bits ----->
49 *
50 * M - number of node offset bits (35 .. 40)
29 * 51 *
30 * 52 *
31 * Memory/UV-HUB Processor Socket Address Format: 53 * Memory/UV-HUB Processor Socket Address Format:
32 * +--------+---------------+---------------------+ 54 * +----------------+---------------+---------------------+
33 * |00..0000| SNASID | NodeOffset | 55 * |00..000000000000| PNODE | NodeOffset |
34 * +--------+---------------+---------------------+ 56 * +----------------+---------------+---------------------+
35 * <--- N bits --->|<--------M bits -----> 57 * <--- N bits --->|<--------M bits ----->
36 * 58 *
37 * M number of node offset bits (35 .. 40) 59 * M - number of node offset bits (35 .. 40)
38 * N number of SNASID bits (0 .. 10) 60 * N - number of PNODE bits (0 .. 10)
39 * 61 *
40 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64). 62 * Note: M + N cannot currently exceed 44 (x86_64) or 46 (IA64).
41 * The actual values are configuration dependent and are set at 63 * The actual values are configuration dependent and are set at
42 * boot time 64 * boot time. M & N values are set by the hardware/BIOS at boot.
65 *
43 * 66 *
44 * APICID format 67 * APICID format
45 * NOTE!!!!!! This is the current format of the APICID. However, code 68 * NOTE!!!!!! This is the current format of the APICID. However, code
@@ -48,14 +71,14 @@
48 * 71 *
49 * 1111110000000000 72 * 1111110000000000
50 * 5432109876543210 73 * 5432109876543210
51 * nnnnnnnnnnlc0cch 74 * pppppppppplc0cch
52 * sssssssssss 75 * sssssssssss
53 * 76 *
54 * n = snasid bits 77 * p = pnode bits
55 * l = socket number on board 78 * l = socket number on board
56 * c = core 79 * c = core
57 * h = hyperthread 80 * h = hyperthread
58 * s = bits that are in the socket CSR 81 * s = bits that are in the SOCKET_ID CSR
59 * 82 *
60 * Note: Processor only supports 12 bits in the APICID register. The ACPI 83 * Note: Processor only supports 12 bits in the APICID register. The ACPI
61 * tables hold all 16 bits. Software needs to be aware of this. 84 * tables hold all 16 bits. Software needs to be aware of this.
@@ -74,7 +97,7 @@
74 * This value is also the value of the maximum number of non-router NASIDs 97 * This value is also the value of the maximum number of non-router NASIDs
75 * in the numalink fabric. 98 * in the numalink fabric.
76 * 99 *
77 * NOTE: a brick may be 1 or 2 OS nodes. Don't get these confused. 100 * NOTE: a brick may contain 1 or 2 OS nodes. Don't get these confused.
78 */ 101 */
79#define UV_MAX_NUMALINK_BLADES 16384 102#define UV_MAX_NUMALINK_BLADES 16384
80 103
@@ -96,8 +119,12 @@
96 */ 119 */
97struct uv_hub_info_s { 120struct uv_hub_info_s {
98 unsigned long global_mmr_base; 121 unsigned long global_mmr_base;
99 unsigned short local_nasid; 122 unsigned long gpa_mask;
100 unsigned short gnode_upper; 123 unsigned long gnode_upper;
124 unsigned long lowmem_remap_top;
125 unsigned long lowmem_remap_base;
126 unsigned short pnode;
127 unsigned short pnode_mask;
101 unsigned short coherency_domain_number; 128 unsigned short coherency_domain_number;
102 unsigned short numa_blade_id; 129 unsigned short numa_blade_id;
103 unsigned char blade_processor_id; 130 unsigned char blade_processor_id;
@@ -112,83 +139,126 @@ DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
112 * Local & Global MMR space macros. 139 * Local & Global MMR space macros.
113 * Note: macros are intended to be used ONLY by inline functions 140 * Note: macros are intended to be used ONLY by inline functions
114 * in this file - not by other kernel code. 141 * in this file - not by other kernel code.
142 * n - NASID (full 15-bit global nasid)
143 * g - GNODE (full 15-bit global nasid, right shifted 1)
144 * p - PNODE (local part of nsids, right shifted 1)
115 */ 145 */
116#define UV_SNASID(n) ((n) >> 1) 146#define UV_NASID_TO_PNODE(n) (((n) >> 1) & uv_hub_info->pnode_mask)
117#define UV_NASID(n) ((n) << 1) 147#define UV_PNODE_TO_NASID(p) (((p) << 1) | uv_hub_info->gnode_upper)
118 148
119#define UV_LOCAL_MMR_BASE 0xf4000000UL 149#define UV_LOCAL_MMR_BASE 0xf4000000UL
120#define UV_GLOBAL_MMR32_BASE 0xf8000000UL 150#define UV_GLOBAL_MMR32_BASE 0xf8000000UL
121#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 151#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
152#define UV_LOCAL_MMR_SIZE (64UL * 1024 * 1024)
153#define UV_GLOBAL_MMR32_SIZE (64UL * 1024 * 1024)
122 154
123#define UV_GLOBAL_MMR32_SNASID_MASK 0x3ff 155#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
124#define UV_GLOBAL_MMR32_SNASID_SHIFT 15 156#define UV_GLOBAL_MMR64_PNODE_SHIFT 26
125#define UV_GLOBAL_MMR64_SNASID_SHIFT 26
126 157
127#define UV_GLOBAL_MMR32_NASID_BITS(n) \ 158#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
128 (((UV_SNASID(n) & UV_GLOBAL_MMR32_SNASID_MASK)) << \
129 (UV_GLOBAL_MMR32_SNASID_SHIFT))
130 159
131#define UV_GLOBAL_MMR64_NASID_BITS(n) \ 160#define UV_GLOBAL_MMR64_PNODE_BITS(p) \
132 ((unsigned long)UV_SNASID(n) << UV_GLOBAL_MMR64_SNASID_SHIFT) 161 ((unsigned long)(p) << UV_GLOBAL_MMR64_PNODE_SHIFT)
162
163#define UV_APIC_PNODE_SHIFT 6
164
165/*
166 * Macros for converting between kernel virtual addresses, socket local physical
167 * addresses, and UV global physical addresses.
168 * Note: use the standard __pa() & __va() macros for converting
169 * between socket virtual and socket physical addresses.
170 */
171
172/* socket phys RAM --> UV global physical address */
173static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
174{
175 if (paddr < uv_hub_info->lowmem_remap_top)
176 paddr += uv_hub_info->lowmem_remap_base;
177 return paddr | uv_hub_info->gnode_upper;
178}
179
180
181/* socket virtual --> UV global physical address */
182static inline unsigned long uv_gpa(void *v)
183{
184 return __pa(v) | uv_hub_info->gnode_upper;
185}
186
187/* socket virtual --> UV global physical address */
188static inline void *uv_vgpa(void *v)
189{
190 return (void *)uv_gpa(v);
191}
192
193/* UV global physical address --> socket virtual */
194static inline void *uv_va(unsigned long gpa)
195{
196 return __va(gpa & uv_hub_info->gpa_mask);
197}
198
199/* pnode, offset --> socket virtual */
200static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
201{
202 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset);
203}
133 204
134#define UV_APIC_NASID_SHIFT 6
135 205
136/* 206/*
137 * Extract a NASID from an APICID (full apicid, not processor subset) 207 * Extract a PNODE from an APICID (full apicid, not processor subset)
138 */ 208 */
139static inline int uv_apicid_to_nasid(int apicid) 209static inline int uv_apicid_to_pnode(int apicid)
140{ 210{
141 return (UV_NASID(apicid >> UV_APIC_NASID_SHIFT)); 211 return (apicid >> UV_APIC_PNODE_SHIFT);
142} 212}
143 213
144/* 214/*
145 * Access global MMRs using the low memory MMR32 space. This region supports 215 * Access global MMRs using the low memory MMR32 space. This region supports
146 * faster MMR access but not all MMRs are accessible in this space. 216 * faster MMR access but not all MMRs are accessible in this space.
147 */ 217 */
148static inline unsigned long *uv_global_mmr32_address(int nasid, 218static inline unsigned long *uv_global_mmr32_address(int pnode,
149 unsigned long offset) 219 unsigned long offset)
150{ 220{
151 return __va(UV_GLOBAL_MMR32_BASE | 221 return __va(UV_GLOBAL_MMR32_BASE |
152 UV_GLOBAL_MMR32_NASID_BITS(nasid) | offset); 222 UV_GLOBAL_MMR32_PNODE_BITS(pnode) | offset);
153} 223}
154 224
155static inline void uv_write_global_mmr32(int nasid, unsigned long offset, 225static inline void uv_write_global_mmr32(int pnode, unsigned long offset,
156 unsigned long val) 226 unsigned long val)
157{ 227{
158 *uv_global_mmr32_address(nasid, offset) = val; 228 *uv_global_mmr32_address(pnode, offset) = val;
159} 229}
160 230
161static inline unsigned long uv_read_global_mmr32(int nasid, 231static inline unsigned long uv_read_global_mmr32(int pnode,
162 unsigned long offset) 232 unsigned long offset)
163{ 233{
164 return *uv_global_mmr32_address(nasid, offset); 234 return *uv_global_mmr32_address(pnode, offset);
165} 235}
166 236
167/* 237/*
168 * Access Global MMR space using the MMR space located at the top of physical 238 * Access Global MMR space using the MMR space located at the top of physical
169 * memory. 239 * memory.
170 */ 240 */
171static inline unsigned long *uv_global_mmr64_address(int nasid, 241static inline unsigned long *uv_global_mmr64_address(int pnode,
172 unsigned long offset) 242 unsigned long offset)
173{ 243{
174 return __va(UV_GLOBAL_MMR64_BASE | 244 return __va(UV_GLOBAL_MMR64_BASE |
175 UV_GLOBAL_MMR64_NASID_BITS(nasid) | offset); 245 UV_GLOBAL_MMR64_PNODE_BITS(pnode) | offset);
176} 246}
177 247
178static inline void uv_write_global_mmr64(int nasid, unsigned long offset, 248static inline void uv_write_global_mmr64(int pnode, unsigned long offset,
179 unsigned long val) 249 unsigned long val)
180{ 250{
181 *uv_global_mmr64_address(nasid, offset) = val; 251 *uv_global_mmr64_address(pnode, offset) = val;
182} 252}
183 253
184static inline unsigned long uv_read_global_mmr64(int nasid, 254static inline unsigned long uv_read_global_mmr64(int pnode,
185 unsigned long offset) 255 unsigned long offset)
186{ 256{
187 return *uv_global_mmr64_address(nasid, offset); 257 return *uv_global_mmr64_address(pnode, offset);
188} 258}
189 259
190/* 260/*
191 * Access node local MMRs. Faster than using global space but only local MMRs 261 * Access hub local MMRs. Faster than using global space but only local MMRs
192 * are accessible. 262 * are accessible.
193 */ 263 */
194static inline unsigned long *uv_local_mmr_address(unsigned long offset) 264static inline unsigned long *uv_local_mmr_address(unsigned long offset)
@@ -207,15 +277,15 @@ static inline void uv_write_local_mmr(unsigned long offset, unsigned long val)
207} 277}
208 278
209/* 279/*
210 * Structures and definitions for converting between cpu, node, and blade 280 * Structures and definitions for converting between cpu, node, pnode, and blade
211 * numbers. 281 * numbers.
212 */ 282 */
213struct uv_blade_info { 283struct uv_blade_info {
214 unsigned short nr_posible_cpus; 284 unsigned short nr_possible_cpus;
215 unsigned short nr_online_cpus; 285 unsigned short nr_online_cpus;
216 unsigned short nasid; 286 unsigned short pnode;
217}; 287};
218struct uv_blade_info *uv_blade_info; 288extern struct uv_blade_info *uv_blade_info;
219extern short *uv_node_to_blade; 289extern short *uv_node_to_blade;
220extern short *uv_cpu_to_blade; 290extern short *uv_cpu_to_blade;
221extern short uv_possible_blades; 291extern short uv_possible_blades;
@@ -244,16 +314,16 @@ static inline int uv_node_to_blade_id(int nid)
244 return uv_node_to_blade[nid]; 314 return uv_node_to_blade[nid];
245} 315}
246 316
247/* Convert a blade id to the NASID of the blade */ 317/* Convert a blade id to the PNODE of the blade */
248static inline int uv_blade_to_nasid(int bid) 318static inline int uv_blade_to_pnode(int bid)
249{ 319{
250 return uv_blade_info[bid].nasid; 320 return uv_blade_info[bid].pnode;
251} 321}
252 322
253/* Determine the number of possible cpus on a blade */ 323/* Determine the number of possible cpus on a blade */
254static inline int uv_blade_nr_possible_cpus(int bid) 324static inline int uv_blade_nr_possible_cpus(int bid)
255{ 325{
256 return uv_blade_info[bid].nr_posible_cpus; 326 return uv_blade_info[bid].nr_possible_cpus;
257} 327}
258 328
259/* Determine the number of online cpus on a blade */ 329/* Determine the number of online cpus on a blade */
@@ -262,16 +332,16 @@ static inline int uv_blade_nr_online_cpus(int bid)
262 return uv_blade_info[bid].nr_online_cpus; 332 return uv_blade_info[bid].nr_online_cpus;
263} 333}
264 334
265/* Convert a cpu id to the NASID of the blade containing the cpu */ 335/* Convert a cpu id to the PNODE of the blade containing the cpu */
266static inline int uv_cpu_to_nasid(int cpu) 336static inline int uv_cpu_to_pnode(int cpu)
267{ 337{
268 return uv_blade_info[uv_cpu_to_blade_id(cpu)].nasid; 338 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode;
269} 339}
270 340
271/* Convert a node number to the NASID of the blade */ 341/* Convert a linux node number to the PNODE of the blade */
272static inline int uv_node_to_nasid(int nid) 342static inline int uv_node_to_pnode(int nid)
273{ 343{
274 return uv_blade_info[uv_node_to_blade_id(nid)].nasid; 344 return uv_blade_info[uv_node_to_blade_id(nid)].pnode;
275} 345}
276 346
277/* Maximum possible number of blades */ 347/* Maximum possible number of blades */
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h
index 3b69fe6b6376..151fd7fcb809 100644
--- a/include/asm-x86/uv/uv_mmrs.h
+++ b/include/asm-x86/uv/uv_mmrs.h
@@ -11,17 +11,290 @@
11#ifndef __ASM_X86_UV_MMRS__ 11#ifndef __ASM_X86_UV_MMRS__
12#define __ASM_X86_UV_MMRS__ 12#define __ASM_X86_UV_MMRS__
13 13
14/* 14#define UV_MMR_ENABLE (1UL << 63)
15 * AUTO GENERATED - Do not edit 15
16 */ 16/* ========================================================================= */
17/* UVH_BAU_DATA_CONFIG */
18/* ========================================================================= */
19#define UVH_BAU_DATA_CONFIG 0x61680UL
20#define UVH_BAU_DATA_CONFIG_32 0x0438
21
22#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
23#define UVH_BAU_DATA_CONFIG_VECTOR_MASK 0x00000000000000ffUL
24#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
25#define UVH_BAU_DATA_CONFIG_DM_MASK 0x0000000000000700UL
26#define UVH_BAU_DATA_CONFIG_DESTMODE_SHFT 11
27#define UVH_BAU_DATA_CONFIG_DESTMODE_MASK 0x0000000000000800UL
28#define UVH_BAU_DATA_CONFIG_STATUS_SHFT 12
29#define UVH_BAU_DATA_CONFIG_STATUS_MASK 0x0000000000001000UL
30#define UVH_BAU_DATA_CONFIG_P_SHFT 13
31#define UVH_BAU_DATA_CONFIG_P_MASK 0x0000000000002000UL
32#define UVH_BAU_DATA_CONFIG_T_SHFT 15
33#define UVH_BAU_DATA_CONFIG_T_MASK 0x0000000000008000UL
34#define UVH_BAU_DATA_CONFIG_M_SHFT 16
35#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
36#define UVH_BAU_DATA_CONFIG_APIC_ID_SHFT 32
37#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
38
39union uvh_bau_data_config_u {
40 unsigned long v;
41 struct uvh_bau_data_config_s {
42 unsigned long vector_ : 8; /* RW */
43 unsigned long dm : 3; /* RW */
44 unsigned long destmode : 1; /* RW */
45 unsigned long status : 1; /* RO */
46 unsigned long p : 1; /* RO */
47 unsigned long rsvd_14 : 1; /* */
48 unsigned long t : 1; /* RO */
49 unsigned long m : 1; /* RW */
50 unsigned long rsvd_17_31: 15; /* */
51 unsigned long apic_id : 32; /* RW */
52 } s;
53};
54
55/* ========================================================================= */
56/* UVH_EVENT_OCCURRED0 */
57/* ========================================================================= */
58#define UVH_EVENT_OCCURRED0 0x70000UL
59#define UVH_EVENT_OCCURRED0_32 0x005e8
60
61#define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0
62#define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL
63#define UVH_EVENT_OCCURRED0_GR0_HCERR_SHFT 1
64#define UVH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000002UL
65#define UVH_EVENT_OCCURRED0_GR1_HCERR_SHFT 2
66#define UVH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000004UL
67#define UVH_EVENT_OCCURRED0_LH_HCERR_SHFT 3
68#define UVH_EVENT_OCCURRED0_LH_HCERR_MASK 0x0000000000000008UL
69#define UVH_EVENT_OCCURRED0_RH_HCERR_SHFT 4
70#define UVH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000010UL
71#define UVH_EVENT_OCCURRED0_XN_HCERR_SHFT 5
72#define UVH_EVENT_OCCURRED0_XN_HCERR_MASK 0x0000000000000020UL
73#define UVH_EVENT_OCCURRED0_SI_HCERR_SHFT 6
74#define UVH_EVENT_OCCURRED0_SI_HCERR_MASK 0x0000000000000040UL
75#define UVH_EVENT_OCCURRED0_LB_AOERR0_SHFT 7
76#define UVH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000080UL
77#define UVH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 8
78#define UVH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000000100UL
79#define UVH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 9
80#define UVH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000000200UL
81#define UVH_EVENT_OCCURRED0_LH_AOERR0_SHFT 10
82#define UVH_EVENT_OCCURRED0_LH_AOERR0_MASK 0x0000000000000400UL
83#define UVH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11
84#define UVH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL
85#define UVH_EVENT_OCCURRED0_XN_AOERR0_SHFT 12
86#define UVH_EVENT_OCCURRED0_XN_AOERR0_MASK 0x0000000000001000UL
87#define UVH_EVENT_OCCURRED0_SI_AOERR0_SHFT 13
88#define UVH_EVENT_OCCURRED0_SI_AOERR0_MASK 0x0000000000002000UL
89#define UVH_EVENT_OCCURRED0_LB_AOERR1_SHFT 14
90#define UVH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000004000UL
91#define UVH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 15
92#define UVH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000000008000UL
93#define UVH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 16
94#define UVH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000000010000UL
95#define UVH_EVENT_OCCURRED0_LH_AOERR1_SHFT 17
96#define UVH_EVENT_OCCURRED0_LH_AOERR1_MASK 0x0000000000020000UL
97#define UVH_EVENT_OCCURRED0_RH_AOERR1_SHFT 18
98#define UVH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000040000UL
99#define UVH_EVENT_OCCURRED0_XN_AOERR1_SHFT 19
100#define UVH_EVENT_OCCURRED0_XN_AOERR1_MASK 0x0000000000080000UL
101#define UVH_EVENT_OCCURRED0_SI_AOERR1_SHFT 20
102#define UVH_EVENT_OCCURRED0_SI_AOERR1_MASK 0x0000000000100000UL
103#define UVH_EVENT_OCCURRED0_RH_VPI_INT_SHFT 21
104#define UVH_EVENT_OCCURRED0_RH_VPI_INT_MASK 0x0000000000200000UL
105#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 22
106#define UVH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
107#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 23
108#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000000800000UL
109#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 24
110#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000001000000UL
111#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 25
112#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000002000000UL
113#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 26
114#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000004000000UL
115#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 27
116#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000000008000000UL
117#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 28
118#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000000010000000UL
119#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 29
120#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000000020000000UL
121#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 30
122#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000000040000000UL
123#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 31
124#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000000080000000UL
125#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 32
126#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000000100000000UL
127#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 33
128#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000000200000000UL
129#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 34
130#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000000400000000UL
131#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 35
132#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000000800000000UL
133#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 36
134#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000001000000000UL
135#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 37
136#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000002000000000UL
137#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 38
138#define UVH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000004000000000UL
139#define UVH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 39
140#define UVH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0000008000000000UL
141#define UVH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 40
142#define UVH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0000010000000000UL
143#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 41
144#define UVH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0000020000000000UL
145#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 42
146#define UVH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0000040000000000UL
147#define UVH_EVENT_OCCURRED0_LTC_INT_SHFT 43
148#define UVH_EVENT_OCCURRED0_LTC_INT_MASK 0x0000080000000000UL
149#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 44
150#define UVH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
151#define UVH_EVENT_OCCURRED0_IPI_INT_SHFT 45
152#define UVH_EVENT_OCCURRED0_IPI_INT_MASK 0x0000200000000000UL
153#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 46
154#define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0000400000000000UL
155#define UVH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 47
156#define UVH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0000800000000000UL
157#define UVH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 48
158#define UVH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0001000000000000UL
159#define UVH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 49
160#define UVH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0002000000000000UL
161#define UVH_EVENT_OCCURRED0_PROFILE_INT_SHFT 50
162#define UVH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0004000000000000UL
163#define UVH_EVENT_OCCURRED0_RTC0_SHFT 51
164#define UVH_EVENT_OCCURRED0_RTC0_MASK 0x0008000000000000UL
165#define UVH_EVENT_OCCURRED0_RTC1_SHFT 52
166#define UVH_EVENT_OCCURRED0_RTC1_MASK 0x0010000000000000UL
167#define UVH_EVENT_OCCURRED0_RTC2_SHFT 53
168#define UVH_EVENT_OCCURRED0_RTC2_MASK 0x0020000000000000UL
169#define UVH_EVENT_OCCURRED0_RTC3_SHFT 54
170#define UVH_EVENT_OCCURRED0_RTC3_MASK 0x0040000000000000UL
171#define UVH_EVENT_OCCURRED0_BAU_DATA_SHFT 55
172#define UVH_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
173#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_SHFT 56
174#define UVH_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
175union uvh_event_occurred0_u {
176 unsigned long v;
177 struct uvh_event_occurred0_s {
178 unsigned long lb_hcerr : 1; /* RW, W1C */
179 unsigned long gr0_hcerr : 1; /* RW, W1C */
180 unsigned long gr1_hcerr : 1; /* RW, W1C */
181 unsigned long lh_hcerr : 1; /* RW, W1C */
182 unsigned long rh_hcerr : 1; /* RW, W1C */
183 unsigned long xn_hcerr : 1; /* RW, W1C */
184 unsigned long si_hcerr : 1; /* RW, W1C */
185 unsigned long lb_aoerr0 : 1; /* RW, W1C */
186 unsigned long gr0_aoerr0 : 1; /* RW, W1C */
187 unsigned long gr1_aoerr0 : 1; /* RW, W1C */
188 unsigned long lh_aoerr0 : 1; /* RW, W1C */
189 unsigned long rh_aoerr0 : 1; /* RW, W1C */
190 unsigned long xn_aoerr0 : 1; /* RW, W1C */
191 unsigned long si_aoerr0 : 1; /* RW, W1C */
192 unsigned long lb_aoerr1 : 1; /* RW, W1C */
193 unsigned long gr0_aoerr1 : 1; /* RW, W1C */
194 unsigned long gr1_aoerr1 : 1; /* RW, W1C */
195 unsigned long lh_aoerr1 : 1; /* RW, W1C */
196 unsigned long rh_aoerr1 : 1; /* RW, W1C */
197 unsigned long xn_aoerr1 : 1; /* RW, W1C */
198 unsigned long si_aoerr1 : 1; /* RW, W1C */
199 unsigned long rh_vpi_int : 1; /* RW, W1C */
200 unsigned long system_shutdown_int : 1; /* RW, W1C */
201 unsigned long lb_irq_int_0 : 1; /* RW, W1C */
202 unsigned long lb_irq_int_1 : 1; /* RW, W1C */
203 unsigned long lb_irq_int_2 : 1; /* RW, W1C */
204 unsigned long lb_irq_int_3 : 1; /* RW, W1C */
205 unsigned long lb_irq_int_4 : 1; /* RW, W1C */
206 unsigned long lb_irq_int_5 : 1; /* RW, W1C */
207 unsigned long lb_irq_int_6 : 1; /* RW, W1C */
208 unsigned long lb_irq_int_7 : 1; /* RW, W1C */
209 unsigned long lb_irq_int_8 : 1; /* RW, W1C */
210 unsigned long lb_irq_int_9 : 1; /* RW, W1C */
211 unsigned long lb_irq_int_10 : 1; /* RW, W1C */
212 unsigned long lb_irq_int_11 : 1; /* RW, W1C */
213 unsigned long lb_irq_int_12 : 1; /* RW, W1C */
214 unsigned long lb_irq_int_13 : 1; /* RW, W1C */
215 unsigned long lb_irq_int_14 : 1; /* RW, W1C */
216 unsigned long lb_irq_int_15 : 1; /* RW, W1C */
217 unsigned long l1_nmi_int : 1; /* RW, W1C */
218 unsigned long stop_clock : 1; /* RW, W1C */
219 unsigned long asic_to_l1 : 1; /* RW, W1C */
220 unsigned long l1_to_asic : 1; /* RW, W1C */
221 unsigned long ltc_int : 1; /* RW, W1C */
222 unsigned long la_seq_trigger : 1; /* RW, W1C */
223 unsigned long ipi_int : 1; /* RW, W1C */
224 unsigned long extio_int0 : 1; /* RW, W1C */
225 unsigned long extio_int1 : 1; /* RW, W1C */
226 unsigned long extio_int2 : 1; /* RW, W1C */
227 unsigned long extio_int3 : 1; /* RW, W1C */
228 unsigned long profile_int : 1; /* RW, W1C */
229 unsigned long rtc0 : 1; /* RW, W1C */
230 unsigned long rtc1 : 1; /* RW, W1C */
231 unsigned long rtc2 : 1; /* RW, W1C */
232 unsigned long rtc3 : 1; /* RW, W1C */
233 unsigned long bau_data : 1; /* RW, W1C */
234 unsigned long power_management_req : 1; /* RW, W1C */
235 unsigned long rsvd_57_63 : 7; /* */
236 } s;
237};
238
239/* ========================================================================= */
240/* UVH_EVENT_OCCURRED0_ALIAS */
241/* ========================================================================= */
242#define UVH_EVENT_OCCURRED0_ALIAS 0x0000000000070008UL
243#define UVH_EVENT_OCCURRED0_ALIAS_32 0x005f0
244
245/* ========================================================================= */
246/* UVH_INT_CMPB */
247/* ========================================================================= */
248#define UVH_INT_CMPB 0x22080UL
249
250#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
251#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
252
253union uvh_int_cmpb_u {
254 unsigned long v;
255 struct uvh_int_cmpb_s {
256 unsigned long real_time_cmpb : 56; /* RW */
257 unsigned long rsvd_56_63 : 8; /* */
258 } s;
259};
260
261/* ========================================================================= */
262/* UVH_INT_CMPC */
263/* ========================================================================= */
264#define UVH_INT_CMPC 0x22100UL
265
266#define UVH_INT_CMPC_REAL_TIME_CMPC_SHFT 0
267#define UVH_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
268
269union uvh_int_cmpc_u {
270 unsigned long v;
271 struct uvh_int_cmpc_s {
272 unsigned long real_time_cmpc : 56; /* RW */
273 unsigned long rsvd_56_63 : 8; /* */
274 } s;
275};
276
277/* ========================================================================= */
278/* UVH_INT_CMPD */
279/* ========================================================================= */
280#define UVH_INT_CMPD 0x22180UL
17 281
18 #define UV_MMR_ENABLE (1UL << 63) 282#define UVH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
283#define UVH_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
284
285union uvh_int_cmpd_u {
286 unsigned long v;
287 struct uvh_int_cmpd_s {
288 unsigned long real_time_cmpd : 56; /* RW */
289 unsigned long rsvd_56_63 : 8; /* */
290 } s;
291};
19 292
20/* ========================================================================= */ 293/* ========================================================================= */
21/* UVH_IPI_INT */ 294/* UVH_IPI_INT */
22/* ========================================================================= */ 295/* ========================================================================= */
23#define UVH_IPI_INT 0x60500UL 296#define UVH_IPI_INT 0x60500UL
24#define UVH_IPI_INT_32 0x0360 297#define UVH_IPI_INT_32 0x0348
25 298
26#define UVH_IPI_INT_VECTOR_SHFT 0 299#define UVH_IPI_INT_VECTOR_SHFT 0
27#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL 300#define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL
@@ -51,7 +324,7 @@ union uvh_ipi_int_u {
51/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 324/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
52/* ========================================================================= */ 325/* ========================================================================= */
53#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 326#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
54#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009f0 327#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x009c0
55 328
56#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 329#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
57#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 330#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -73,7 +346,7 @@ union uvh_lb_bau_intd_payload_queue_first_u {
73/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 346/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
74/* ========================================================================= */ 347/* ========================================================================= */
75#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 348#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
76#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009f8 349#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x009c8
77 350
78#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 351#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
79#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 352#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
@@ -91,7 +364,7 @@ union uvh_lb_bau_intd_payload_queue_last_u {
91/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 364/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
92/* ========================================================================= */ 365/* ========================================================================= */
93#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 366#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
94#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x00a00 367#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x009d0
95 368
96#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 369#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
97#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 370#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
@@ -109,6 +382,7 @@ union uvh_lb_bau_intd_payload_queue_tail_u {
109/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 382/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
110/* ========================================================================= */ 383/* ========================================================================= */
111#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 384#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
385#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0x0a68
112 386
113#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 387#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
114#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 388#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
@@ -169,12 +443,13 @@ union uvh_lb_bau_intd_software_acknowledge_u {
169/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 443/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
170/* ========================================================================= */ 444/* ========================================================================= */
171#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL 445#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x0000000000320088UL
446#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0x0a70
172 447
173/* ========================================================================= */ 448/* ========================================================================= */
174/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 449/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
175/* ========================================================================= */ 450/* ========================================================================= */
176#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 451#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
177#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009d8 452#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x009a8
178 453
179#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 454#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
180#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL 455#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_MASK 0x000000000000003fUL
@@ -197,7 +472,7 @@ union uvh_lb_bau_sb_activation_control_u {
197/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 472/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
198/* ========================================================================= */ 473/* ========================================================================= */
199#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 474#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
200#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009e0 475#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x009b0
201 476
202#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 477#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
203#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 478#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
@@ -213,7 +488,7 @@ union uvh_lb_bau_sb_activation_status_0_u {
213/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 488/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
214/* ========================================================================= */ 489/* ========================================================================= */
215#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 490#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
216#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009e8 491#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x009b8
217 492
218#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 493#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
219#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 494#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
@@ -229,7 +504,7 @@ union uvh_lb_bau_sb_activation_status_1_u {
229/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 504/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
230/* ========================================================================= */ 505/* ========================================================================= */
231#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 506#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
232#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009d0 507#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x009a0
233 508
234#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 509#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
235#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL 510#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
@@ -248,6 +523,334 @@ union uvh_lb_bau_sb_descriptor_base_u {
248}; 523};
249 524
250/* ========================================================================= */ 525/* ========================================================================= */
526/* UVH_LB_MCAST_AOERR0_RPT_ENABLE */
527/* ========================================================================= */
528#define UVH_LB_MCAST_AOERR0_RPT_ENABLE 0x50b20UL
529
530#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_SHFT 0
531#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_OBESE_MSG_MASK 0x0000000000000001UL
532#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_SHFT 1
533#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_DATA_SB_ERR_MASK 0x0000000000000002UL
534#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_SHFT 2
535#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_NACK_BUFF_PARITY_MASK 0x0000000000000004UL
536#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_SHFT 3
537#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_TIMEOUT_MASK 0x0000000000000008UL
538#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_SHFT 4
539#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_INACTIVE_REPLY_MASK 0x0000000000000010UL
540#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_SHFT 5
541#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_UPGRADE_ERROR_MASK 0x0000000000000020UL
542#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_SHFT 6
543#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REG_COUNT_UNDERFLOW_MASK 0x0000000000000040UL
544#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_SHFT 7
545#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MCAST_REP_OBESE_MSG_MASK 0x0000000000000080UL
546#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_SHFT 8
547#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_RUNT_MSG_MASK 0x0000000000000100UL
548#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_SHFT 9
549#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_OBESE_MSG_MASK 0x0000000000000200UL
550#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_SHFT 10
551#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REQ_DATA_SB_ERR_MASK 0x0000000000000400UL
552#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_SHFT 11
553#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_RUNT_MSG_MASK 0x0000000000000800UL
554#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_SHFT 12
555#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_OBESE_MSG_MASK 0x0000000000001000UL
556#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_SHFT 13
557#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_DATA_SB_ERR_MASK 0x0000000000002000UL
558#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_SHFT 14
559#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_REP_COMMAND_ERR_MASK 0x0000000000004000UL
560#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_SHFT 15
561#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_UCACHE_PEND_TIMEOUT_MASK 0x0000000000008000UL
562#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_SHFT 16
563#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_RUNT_MSG_MASK 0x0000000000010000UL
564#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_SHFT 17
565#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_OBESE_MSG_MASK 0x0000000000020000UL
566#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_SHFT 18
567#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REQ_DATA_SB_ERR_MASK 0x0000000000040000UL
568#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_SHFT 19
569#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_RUNT_MSG_MASK 0x0000000000080000UL
570#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_SHFT 20
571#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_OBESE_MSG_MASK 0x0000000000100000UL
572#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_SHFT 21
573#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_REP_DATA_SB_ERR_MASK 0x0000000000200000UL
574#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_SHFT 22
575#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_AMO_TIMEOUT_MASK 0x0000000000400000UL
576#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_SHFT 23
577#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_PUT_TIMEOUT_MASK 0x0000000000800000UL
578#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_SHFT 24
579#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_MACC_SPURIOUS_EVENT_MASK 0x0000000001000000UL
580#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_SHFT 25
581#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IOH_DESTINATION_TABLE_PARITY_MASK 0x0000000002000000UL
582#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_SHFT 26
583#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_HAD_ERROR_REPLY_MASK 0x0000000004000000UL
584#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_SHFT 27
585#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_GET_TIMEOUT_MASK 0x0000000008000000UL
586#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_SHFT 28
587#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_LOCK_MANAGER_HAD_ERROR_REPLY_MASK 0x0000000010000000UL
588#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_SHFT 29
589#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_HAD_ERROR_REPLY_MASK 0x0000000020000000UL
590#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_SHFT 30
591#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_PUT_TIMEOUT_MASK 0x0000000040000000UL
592#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_SHFT 31
593#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SB_ACTIVATION_OVERRUN_MASK 0x0000000080000000UL
594#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_SHFT 32
595#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_HAD_ERROR_REPLY_MASK 0x0000000100000000UL
596#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_SHFT 33
597#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_COMPLETED_GB_ACTIVATION_TIMEOUT_MASK 0x0000000200000000UL
598#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_SHFT 34
599#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_0_PARITY_MASK 0x0000000400000000UL
600#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_SHFT 35
601#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_DESCRIPTOR_BUFFER_1_PARITY_MASK 0x0000000800000000UL
602#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_SHFT 36
603#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_SOCKET_DESTINATION_TABLE_PARITY_MASK 0x0000001000000000UL
604#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_SHFT 37
605#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_BAU_REPLY_PAYLOAD_CORRUPTION_MASK 0x0000002000000000UL
606#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_SHFT 38
607#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_IO_PORT_DESTINATION_TABLE_PARITY_MASK 0x0000004000000000UL
608#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_SHFT 39
609#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INTD_SOFT_ACK_TIMEOUT_MASK 0x0000008000000000UL
610#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_SHFT 40
611#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_OBESE_MSG_MASK 0x0000010000000000UL
612#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_SHFT 41
613#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_REP_COMMAND_ERR_MASK 0x0000020000000000UL
614#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_SHFT 42
615#define UVH_LB_MCAST_AOERR0_RPT_ENABLE_INT_TIMEOUT_MASK 0x0000040000000000UL
616
617union uvh_lb_mcast_aoerr0_rpt_enable_u {
618 unsigned long v;
619 struct uvh_lb_mcast_aoerr0_rpt_enable_s {
620 unsigned long mcast_obese_msg : 1; /* RW */
621 unsigned long mcast_data_sb_err : 1; /* RW */
622 unsigned long mcast_nack_buff_parity : 1; /* RW */
623 unsigned long mcast_timeout : 1; /* RW */
624 unsigned long mcast_inactive_reply : 1; /* RW */
625 unsigned long mcast_upgrade_error : 1; /* RW */
626 unsigned long mcast_reg_count_underflow : 1; /* RW */
627 unsigned long mcast_rep_obese_msg : 1; /* RW */
628 unsigned long ucache_req_runt_msg : 1; /* RW */
629 unsigned long ucache_req_obese_msg : 1; /* RW */
630 unsigned long ucache_req_data_sb_err : 1; /* RW */
631 unsigned long ucache_rep_runt_msg : 1; /* RW */
632 unsigned long ucache_rep_obese_msg : 1; /* RW */
633 unsigned long ucache_rep_data_sb_err : 1; /* RW */
634 unsigned long ucache_rep_command_err : 1; /* RW */
635 unsigned long ucache_pend_timeout : 1; /* RW */
636 unsigned long macc_req_runt_msg : 1; /* RW */
637 unsigned long macc_req_obese_msg : 1; /* RW */
638 unsigned long macc_req_data_sb_err : 1; /* RW */
639 unsigned long macc_rep_runt_msg : 1; /* RW */
640 unsigned long macc_rep_obese_msg : 1; /* RW */
641 unsigned long macc_rep_data_sb_err : 1; /* RW */
642 unsigned long macc_amo_timeout : 1; /* RW */
643 unsigned long macc_put_timeout : 1; /* RW */
644 unsigned long macc_spurious_event : 1; /* RW */
645 unsigned long ioh_destination_table_parity : 1; /* RW */
646 unsigned long get_had_error_reply : 1; /* RW */
647 unsigned long get_timeout : 1; /* RW */
648 unsigned long lock_manager_had_error_reply : 1; /* RW */
649 unsigned long put_had_error_reply : 1; /* RW */
650 unsigned long put_timeout : 1; /* RW */
651 unsigned long sb_activation_overrun : 1; /* RW */
652 unsigned long completed_gb_activation_had_error_reply : 1; /* RW */
653 unsigned long completed_gb_activation_timeout : 1; /* RW */
654 unsigned long descriptor_buffer_0_parity : 1; /* RW */
655 unsigned long descriptor_buffer_1_parity : 1; /* RW */
656 unsigned long socket_destination_table_parity : 1; /* RW */
657 unsigned long bau_reply_payload_corruption : 1; /* RW */
658 unsigned long io_port_destination_table_parity : 1; /* RW */
659 unsigned long intd_soft_ack_timeout : 1; /* RW */
660 unsigned long int_rep_obese_msg : 1; /* RW */
661 unsigned long int_rep_command_err : 1; /* RW */
662 unsigned long int_timeout : 1; /* RW */
663 unsigned long rsvd_43_63 : 21; /* */
664 } s;
665};
666
667/* ========================================================================= */
668/* UVH_LOCAL_INT0_CONFIG */
669/* ========================================================================= */
670#define UVH_LOCAL_INT0_CONFIG 0x61000UL
671
672#define UVH_LOCAL_INT0_CONFIG_VECTOR_SHFT 0
673#define UVH_LOCAL_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL
674#define UVH_LOCAL_INT0_CONFIG_DM_SHFT 8
675#define UVH_LOCAL_INT0_CONFIG_DM_MASK 0x0000000000000700UL
676#define UVH_LOCAL_INT0_CONFIG_DESTMODE_SHFT 11
677#define UVH_LOCAL_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL
678#define UVH_LOCAL_INT0_CONFIG_STATUS_SHFT 12
679#define UVH_LOCAL_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL
680#define UVH_LOCAL_INT0_CONFIG_P_SHFT 13
681#define UVH_LOCAL_INT0_CONFIG_P_MASK 0x0000000000002000UL
682#define UVH_LOCAL_INT0_CONFIG_T_SHFT 15
683#define UVH_LOCAL_INT0_CONFIG_T_MASK 0x0000000000008000UL
684#define UVH_LOCAL_INT0_CONFIG_M_SHFT 16
685#define UVH_LOCAL_INT0_CONFIG_M_MASK 0x0000000000010000UL
686#define UVH_LOCAL_INT0_CONFIG_APIC_ID_SHFT 32
687#define UVH_LOCAL_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
688
689union uvh_local_int0_config_u {
690 unsigned long v;
691 struct uvh_local_int0_config_s {
692 unsigned long vector_ : 8; /* RW */
693 unsigned long dm : 3; /* RW */
694 unsigned long destmode : 1; /* RW */
695 unsigned long status : 1; /* RO */
696 unsigned long p : 1; /* RO */
697 unsigned long rsvd_14 : 1; /* */
698 unsigned long t : 1; /* RO */
699 unsigned long m : 1; /* RW */
700 unsigned long rsvd_17_31: 15; /* */
701 unsigned long apic_id : 32; /* RW */
702 } s;
703};
704
705/* ========================================================================= */
706/* UVH_LOCAL_INT0_ENABLE */
707/* ========================================================================= */
708#define UVH_LOCAL_INT0_ENABLE 0x65000UL
709
710#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_SHFT 0
711#define UVH_LOCAL_INT0_ENABLE_LB_HCERR_MASK 0x0000000000000001UL
712#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_SHFT 1
713#define UVH_LOCAL_INT0_ENABLE_GR0_HCERR_MASK 0x0000000000000002UL
714#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_SHFT 2
715#define UVH_LOCAL_INT0_ENABLE_GR1_HCERR_MASK 0x0000000000000004UL
716#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_SHFT 3
717#define UVH_LOCAL_INT0_ENABLE_LH_HCERR_MASK 0x0000000000000008UL
718#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_SHFT 4
719#define UVH_LOCAL_INT0_ENABLE_RH_HCERR_MASK 0x0000000000000010UL
720#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_SHFT 5
721#define UVH_LOCAL_INT0_ENABLE_XN_HCERR_MASK 0x0000000000000020UL
722#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_SHFT 6
723#define UVH_LOCAL_INT0_ENABLE_SI_HCERR_MASK 0x0000000000000040UL
724#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_SHFT 7
725#define UVH_LOCAL_INT0_ENABLE_LB_AOERR0_MASK 0x0000000000000080UL
726#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_SHFT 8
727#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR0_MASK 0x0000000000000100UL
728#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_SHFT 9
729#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR0_MASK 0x0000000000000200UL
730#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_SHFT 10
731#define UVH_LOCAL_INT0_ENABLE_LH_AOERR0_MASK 0x0000000000000400UL
732#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_SHFT 11
733#define UVH_LOCAL_INT0_ENABLE_RH_AOERR0_MASK 0x0000000000000800UL
734#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_SHFT 12
735#define UVH_LOCAL_INT0_ENABLE_XN_AOERR0_MASK 0x0000000000001000UL
736#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_SHFT 13
737#define UVH_LOCAL_INT0_ENABLE_SI_AOERR0_MASK 0x0000000000002000UL
738#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_SHFT 14
739#define UVH_LOCAL_INT0_ENABLE_LB_AOERR1_MASK 0x0000000000004000UL
740#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_SHFT 15
741#define UVH_LOCAL_INT0_ENABLE_GR0_AOERR1_MASK 0x0000000000008000UL
742#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_SHFT 16
743#define UVH_LOCAL_INT0_ENABLE_GR1_AOERR1_MASK 0x0000000000010000UL
744#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_SHFT 17
745#define UVH_LOCAL_INT0_ENABLE_LH_AOERR1_MASK 0x0000000000020000UL
746#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_SHFT 18
747#define UVH_LOCAL_INT0_ENABLE_RH_AOERR1_MASK 0x0000000000040000UL
748#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_SHFT 19
749#define UVH_LOCAL_INT0_ENABLE_XN_AOERR1_MASK 0x0000000000080000UL
750#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_SHFT 20
751#define UVH_LOCAL_INT0_ENABLE_SI_AOERR1_MASK 0x0000000000100000UL
752#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_SHFT 21
753#define UVH_LOCAL_INT0_ENABLE_RH_VPI_INT_MASK 0x0000000000200000UL
754#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_SHFT 22
755#define UVH_LOCAL_INT0_ENABLE_SYSTEM_SHUTDOWN_INT_MASK 0x0000000000400000UL
756#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_SHFT 23
757#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_0_MASK 0x0000000000800000UL
758#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_SHFT 24
759#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_1_MASK 0x0000000001000000UL
760#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_SHFT 25
761#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_2_MASK 0x0000000002000000UL
762#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_SHFT 26
763#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_3_MASK 0x0000000004000000UL
764#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_SHFT 27
765#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_4_MASK 0x0000000008000000UL
766#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_SHFT 28
767#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_5_MASK 0x0000000010000000UL
768#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_SHFT 29
769#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_6_MASK 0x0000000020000000UL
770#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_SHFT 30
771#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_7_MASK 0x0000000040000000UL
772#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_SHFT 31
773#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_8_MASK 0x0000000080000000UL
774#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_SHFT 32
775#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_9_MASK 0x0000000100000000UL
776#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_SHFT 33
777#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_10_MASK 0x0000000200000000UL
778#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_SHFT 34
779#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_11_MASK 0x0000000400000000UL
780#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_SHFT 35
781#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_12_MASK 0x0000000800000000UL
782#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_SHFT 36
783#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_13_MASK 0x0000001000000000UL
784#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_SHFT 37
785#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_14_MASK 0x0000002000000000UL
786#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_SHFT 38
787#define UVH_LOCAL_INT0_ENABLE_LB_IRQ_INT_15_MASK 0x0000004000000000UL
788#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_SHFT 39
789#define UVH_LOCAL_INT0_ENABLE_L1_NMI_INT_MASK 0x0000008000000000UL
790#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_SHFT 40
791#define UVH_LOCAL_INT0_ENABLE_STOP_CLOCK_MASK 0x0000010000000000UL
792#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_SHFT 41
793#define UVH_LOCAL_INT0_ENABLE_ASIC_TO_L1_MASK 0x0000020000000000UL
794#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_SHFT 42
795#define UVH_LOCAL_INT0_ENABLE_L1_TO_ASIC_MASK 0x0000040000000000UL
796#define UVH_LOCAL_INT0_ENABLE_LTC_INT_SHFT 43
797#define UVH_LOCAL_INT0_ENABLE_LTC_INT_MASK 0x0000080000000000UL
798#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_SHFT 44
799#define UVH_LOCAL_INT0_ENABLE_LA_SEQ_TRIGGER_MASK 0x0000100000000000UL
800
801union uvh_local_int0_enable_u {
802 unsigned long v;
803 struct uvh_local_int0_enable_s {
804 unsigned long lb_hcerr : 1; /* RW */
805 unsigned long gr0_hcerr : 1; /* RW */
806 unsigned long gr1_hcerr : 1; /* RW */
807 unsigned long lh_hcerr : 1; /* RW */
808 unsigned long rh_hcerr : 1; /* RW */
809 unsigned long xn_hcerr : 1; /* RW */
810 unsigned long si_hcerr : 1; /* RW */
811 unsigned long lb_aoerr0 : 1; /* RW */
812 unsigned long gr0_aoerr0 : 1; /* RW */
813 unsigned long gr1_aoerr0 : 1; /* RW */
814 unsigned long lh_aoerr0 : 1; /* RW */
815 unsigned long rh_aoerr0 : 1; /* RW */
816 unsigned long xn_aoerr0 : 1; /* RW */
817 unsigned long si_aoerr0 : 1; /* RW */
818 unsigned long lb_aoerr1 : 1; /* RW */
819 unsigned long gr0_aoerr1 : 1; /* RW */
820 unsigned long gr1_aoerr1 : 1; /* RW */
821 unsigned long lh_aoerr1 : 1; /* RW */
822 unsigned long rh_aoerr1 : 1; /* RW */
823 unsigned long xn_aoerr1 : 1; /* RW */
824 unsigned long si_aoerr1 : 1; /* RW */
825 unsigned long rh_vpi_int : 1; /* RW */
826 unsigned long system_shutdown_int : 1; /* RW */
827 unsigned long lb_irq_int_0 : 1; /* RW */
828 unsigned long lb_irq_int_1 : 1; /* RW */
829 unsigned long lb_irq_int_2 : 1; /* RW */
830 unsigned long lb_irq_int_3 : 1; /* RW */
831 unsigned long lb_irq_int_4 : 1; /* RW */
832 unsigned long lb_irq_int_5 : 1; /* RW */
833 unsigned long lb_irq_int_6 : 1; /* RW */
834 unsigned long lb_irq_int_7 : 1; /* RW */
835 unsigned long lb_irq_int_8 : 1; /* RW */
836 unsigned long lb_irq_int_9 : 1; /* RW */
837 unsigned long lb_irq_int_10 : 1; /* RW */
838 unsigned long lb_irq_int_11 : 1; /* RW */
839 unsigned long lb_irq_int_12 : 1; /* RW */
840 unsigned long lb_irq_int_13 : 1; /* RW */
841 unsigned long lb_irq_int_14 : 1; /* RW */
842 unsigned long lb_irq_int_15 : 1; /* RW */
843 unsigned long l1_nmi_int : 1; /* RW */
844 unsigned long stop_clock : 1; /* RW */
845 unsigned long asic_to_l1 : 1; /* RW */
846 unsigned long l1_to_asic : 1; /* RW */
847 unsigned long ltc_int : 1; /* RW */
848 unsigned long la_seq_trigger : 1; /* RW */
849 unsigned long rsvd_45_63 : 19; /* */
850 } s;
851};
852
853/* ========================================================================= */
251/* UVH_NODE_ID */ 854/* UVH_NODE_ID */
252/* ========================================================================= */ 855/* ========================================================================= */
253#define UVH_NODE_ID 0x0UL 856#define UVH_NODE_ID 0x0UL
@@ -284,14 +887,101 @@ union uvh_node_id_u {
284}; 887};
285 888
286/* ========================================================================= */ 889/* ========================================================================= */
890/* UVH_NODE_PRESENT_TABLE */
891/* ========================================================================= */
892#define UVH_NODE_PRESENT_TABLE 0x1400UL
893#define UVH_NODE_PRESENT_TABLE_DEPTH 16
894
895#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
896#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
897
898union uvh_node_present_table_u {
899 unsigned long v;
900 struct uvh_node_present_table_s {
901 unsigned long nodes : 64; /* RW */
902 } s;
903};
904
905/* ========================================================================= */
906/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
907/* ========================================================================= */
908#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
909
910#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
911#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
912
913union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
914 unsigned long v;
915 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
916 unsigned long rsvd_0_23 : 24; /* */
917 unsigned long dest_base : 22; /* RW */
918 unsigned long rsvd_46_63: 18; /* */
919 } s;
920};
921
922/* ========================================================================= */
923/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
924/* ========================================================================= */
925#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
926
927#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
928#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
929
930union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
931 unsigned long v;
932 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
933 unsigned long rsvd_0_23 : 24; /* */
934 unsigned long dest_base : 22; /* RW */
935 unsigned long rsvd_46_63: 18; /* */
936 } s;
937};
938
939/* ========================================================================= */
940/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
941/* ========================================================================= */
942#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
943
944#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
945#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
946
947union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
948 unsigned long v;
949 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
950 unsigned long rsvd_0_23 : 24; /* */
951 unsigned long dest_base : 22; /* RW */
952 unsigned long rsvd_46_63: 18; /* */
953 } s;
954};
955
956/* ========================================================================= */
957/* UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR */
958/* ========================================================================= */
959#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR 0x1600020UL
960
961#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT 26
962#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
963#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
964#define UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
965
966union uvh_rh_gam_cfg_overlay_config_mmr_u {
967 unsigned long v;
968 struct uvh_rh_gam_cfg_overlay_config_mmr_s {
969 unsigned long rsvd_0_25: 26; /* */
970 unsigned long base : 20; /* RW */
971 unsigned long rsvd_46_62: 17; /* */
972 unsigned long enable : 1; /* RW */
973 } s;
974};
975
976/* ========================================================================= */
287/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 977/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
288/* ========================================================================= */ 978/* ========================================================================= */
289#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 979#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
290 980
291#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28 981#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
292#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL 982#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
293#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 46 983#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_SHFT 48
294#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0000400000000000UL 984#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_GR4_MASK 0x0001000000000000UL
295#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 985#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
296#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 986#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
297#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 987#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
@@ -302,8 +992,9 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
302 struct uvh_rh_gam_gru_overlay_config_mmr_s { 992 struct uvh_rh_gam_gru_overlay_config_mmr_s {
303 unsigned long rsvd_0_27: 28; /* */ 993 unsigned long rsvd_0_27: 28; /* */
304 unsigned long base : 18; /* RW */ 994 unsigned long base : 18; /* RW */
995 unsigned long rsvd_46_47: 2; /* */
305 unsigned long gr4 : 1; /* RW */ 996 unsigned long gr4 : 1; /* RW */
306 unsigned long rsvd_47_51: 5; /* */ 997 unsigned long rsvd_49_51: 3; /* */
307 unsigned long n_gru : 4; /* RW */ 998 unsigned long n_gru : 4; /* RW */
308 unsigned long rsvd_56_62: 7; /* */ 999 unsigned long rsvd_56_62: 7; /* */
309 unsigned long enable : 1; /* RW */ 1000 unsigned long enable : 1; /* RW */
@@ -311,6 +1002,32 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
311}; 1002};
312 1003
313/* ========================================================================= */ 1004/* ========================================================================= */
1005/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
1006/* ========================================================================= */
1007#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1008
1009#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1010#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1011#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1012#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1013#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1014#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1015#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1016#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1017
1018union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1019 unsigned long v;
1020 struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
1021 unsigned long rsvd_0_29: 30; /* */
1022 unsigned long base : 16; /* RW */
1023 unsigned long m_io : 6; /* RW */
1024 unsigned long n_io : 4; /* RW */
1025 unsigned long rsvd_56_62: 7; /* */
1026 unsigned long enable : 1; /* RW */
1027 } s;
1028};
1029
1030/* ========================================================================= */
314/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 1031/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
315/* ========================================================================= */ 1032/* ========================================================================= */
316#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 1033#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
@@ -336,7 +1053,7 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u {
336/* ========================================================================= */ 1053/* ========================================================================= */
337/* UVH_RTC */ 1054/* UVH_RTC */
338/* ========================================================================= */ 1055/* ========================================================================= */
339#define UVH_RTC 0x28000UL 1056#define UVH_RTC 0x340000UL
340 1057
341#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 1058#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
342#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 1059#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
@@ -350,6 +1067,139 @@ union uvh_rtc_u {
350}; 1067};
351 1068
352/* ========================================================================= */ 1069/* ========================================================================= */
1070/* UVH_RTC1_INT_CONFIG */
1071/* ========================================================================= */
1072#define UVH_RTC1_INT_CONFIG 0x615c0UL
1073
1074#define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0
1075#define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1076#define UVH_RTC1_INT_CONFIG_DM_SHFT 8
1077#define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL
1078#define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11
1079#define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1080#define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12
1081#define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1082#define UVH_RTC1_INT_CONFIG_P_SHFT 13
1083#define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL
1084#define UVH_RTC1_INT_CONFIG_T_SHFT 15
1085#define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL
1086#define UVH_RTC1_INT_CONFIG_M_SHFT 16
1087#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
1088#define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32
1089#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1090
1091union uvh_rtc1_int_config_u {
1092 unsigned long v;
1093 struct uvh_rtc1_int_config_s {
1094 unsigned long vector_ : 8; /* RW */
1095 unsigned long dm : 3; /* RW */
1096 unsigned long destmode : 1; /* RW */
1097 unsigned long status : 1; /* RO */
1098 unsigned long p : 1; /* RO */
1099 unsigned long rsvd_14 : 1; /* */
1100 unsigned long t : 1; /* RO */
1101 unsigned long m : 1; /* RW */
1102 unsigned long rsvd_17_31: 15; /* */
1103 unsigned long apic_id : 32; /* RW */
1104 } s;
1105};
1106
1107/* ========================================================================= */
1108/* UVH_RTC2_INT_CONFIG */
1109/* ========================================================================= */
1110#define UVH_RTC2_INT_CONFIG 0x61600UL
1111
1112#define UVH_RTC2_INT_CONFIG_VECTOR_SHFT 0
1113#define UVH_RTC2_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1114#define UVH_RTC2_INT_CONFIG_DM_SHFT 8
1115#define UVH_RTC2_INT_CONFIG_DM_MASK 0x0000000000000700UL
1116#define UVH_RTC2_INT_CONFIG_DESTMODE_SHFT 11
1117#define UVH_RTC2_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1118#define UVH_RTC2_INT_CONFIG_STATUS_SHFT 12
1119#define UVH_RTC2_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1120#define UVH_RTC2_INT_CONFIG_P_SHFT 13
1121#define UVH_RTC2_INT_CONFIG_P_MASK 0x0000000000002000UL
1122#define UVH_RTC2_INT_CONFIG_T_SHFT 15
1123#define UVH_RTC2_INT_CONFIG_T_MASK 0x0000000000008000UL
1124#define UVH_RTC2_INT_CONFIG_M_SHFT 16
1125#define UVH_RTC2_INT_CONFIG_M_MASK 0x0000000000010000UL
1126#define UVH_RTC2_INT_CONFIG_APIC_ID_SHFT 32
1127#define UVH_RTC2_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1128
1129union uvh_rtc2_int_config_u {
1130 unsigned long v;
1131 struct uvh_rtc2_int_config_s {
1132 unsigned long vector_ : 8; /* RW */
1133 unsigned long dm : 3; /* RW */
1134 unsigned long destmode : 1; /* RW */
1135 unsigned long status : 1; /* RO */
1136 unsigned long p : 1; /* RO */
1137 unsigned long rsvd_14 : 1; /* */
1138 unsigned long t : 1; /* RO */
1139 unsigned long m : 1; /* RW */
1140 unsigned long rsvd_17_31: 15; /* */
1141 unsigned long apic_id : 32; /* RW */
1142 } s;
1143};
1144
1145/* ========================================================================= */
1146/* UVH_RTC3_INT_CONFIG */
1147/* ========================================================================= */
1148#define UVH_RTC3_INT_CONFIG 0x61640UL
1149
1150#define UVH_RTC3_INT_CONFIG_VECTOR_SHFT 0
1151#define UVH_RTC3_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL
1152#define UVH_RTC3_INT_CONFIG_DM_SHFT 8
1153#define UVH_RTC3_INT_CONFIG_DM_MASK 0x0000000000000700UL
1154#define UVH_RTC3_INT_CONFIG_DESTMODE_SHFT 11
1155#define UVH_RTC3_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL
1156#define UVH_RTC3_INT_CONFIG_STATUS_SHFT 12
1157#define UVH_RTC3_INT_CONFIG_STATUS_MASK 0x0000000000001000UL
1158#define UVH_RTC3_INT_CONFIG_P_SHFT 13
1159#define UVH_RTC3_INT_CONFIG_P_MASK 0x0000000000002000UL
1160#define UVH_RTC3_INT_CONFIG_T_SHFT 15
1161#define UVH_RTC3_INT_CONFIG_T_MASK 0x0000000000008000UL
1162#define UVH_RTC3_INT_CONFIG_M_SHFT 16
1163#define UVH_RTC3_INT_CONFIG_M_MASK 0x0000000000010000UL
1164#define UVH_RTC3_INT_CONFIG_APIC_ID_SHFT 32
1165#define UVH_RTC3_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
1166
1167union uvh_rtc3_int_config_u {
1168 unsigned long v;
1169 struct uvh_rtc3_int_config_s {
1170 unsigned long vector_ : 8; /* RW */
1171 unsigned long dm : 3; /* RW */
1172 unsigned long destmode : 1; /* RW */
1173 unsigned long status : 1; /* RO */
1174 unsigned long p : 1; /* RO */
1175 unsigned long rsvd_14 : 1; /* */
1176 unsigned long t : 1; /* RO */
1177 unsigned long m : 1; /* RW */
1178 unsigned long rsvd_17_31: 15; /* */
1179 unsigned long apic_id : 32; /* RW */
1180 } s;
1181};
1182
1183/* ========================================================================= */
1184/* UVH_RTC_INC_RATIO */
1185/* ========================================================================= */
1186#define UVH_RTC_INC_RATIO 0x350000UL
1187
1188#define UVH_RTC_INC_RATIO_FRACTION_SHFT 0
1189#define UVH_RTC_INC_RATIO_FRACTION_MASK 0x00000000000fffffUL
1190#define UVH_RTC_INC_RATIO_RATIO_SHFT 20
1191#define UVH_RTC_INC_RATIO_RATIO_MASK 0x0000000000700000UL
1192
1193union uvh_rtc_inc_ratio_u {
1194 unsigned long v;
1195 struct uvh_rtc_inc_ratio_s {
1196 unsigned long fraction : 20; /* RW */
1197 unsigned long ratio : 3; /* RW */
1198 unsigned long rsvd_23_63: 41; /* */
1199 } s;
1200};
1201
1202/* ========================================================================= */
353/* UVH_SI_ADDR_MAP_CONFIG */ 1203/* UVH_SI_ADDR_MAP_CONFIG */
354/* ========================================================================= */ 1204/* ========================================================================= */
355#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL 1205#define UVH_SI_ADDR_MAP_CONFIG 0xc80000UL
@@ -369,5 +1219,77 @@ union uvh_si_addr_map_config_u {
369 } s; 1219 } s;
370}; 1220};
371 1221
1222/* ========================================================================= */
1223/* UVH_SI_ALIAS0_OVERLAY_CONFIG */
1224/* ========================================================================= */
1225#define UVH_SI_ALIAS0_OVERLAY_CONFIG 0xc80008UL
1226
1227#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_SHFT 24
1228#define UVH_SI_ALIAS0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1229#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1230#define UVH_SI_ALIAS0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1231#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_SHFT 63
1232#define UVH_SI_ALIAS0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1233
1234union uvh_si_alias0_overlay_config_u {
1235 unsigned long v;
1236 struct uvh_si_alias0_overlay_config_s {
1237 unsigned long rsvd_0_23: 24; /* */
1238 unsigned long base : 8; /* RW */
1239 unsigned long rsvd_32_47: 16; /* */
1240 unsigned long m_alias : 5; /* RW */
1241 unsigned long rsvd_53_62: 10; /* */
1242 unsigned long enable : 1; /* RW */
1243 } s;
1244};
1245
1246/* ========================================================================= */
1247/* UVH_SI_ALIAS1_OVERLAY_CONFIG */
1248/* ========================================================================= */
1249#define UVH_SI_ALIAS1_OVERLAY_CONFIG 0xc80010UL
1250
1251#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_SHFT 24
1252#define UVH_SI_ALIAS1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1253#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1254#define UVH_SI_ALIAS1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1255#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_SHFT 63
1256#define UVH_SI_ALIAS1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1257
1258union uvh_si_alias1_overlay_config_u {
1259 unsigned long v;
1260 struct uvh_si_alias1_overlay_config_s {
1261 unsigned long rsvd_0_23: 24; /* */
1262 unsigned long base : 8; /* RW */
1263 unsigned long rsvd_32_47: 16; /* */
1264 unsigned long m_alias : 5; /* RW */
1265 unsigned long rsvd_53_62: 10; /* */
1266 unsigned long enable : 1; /* RW */
1267 } s;
1268};
1269
1270/* ========================================================================= */
1271/* UVH_SI_ALIAS2_OVERLAY_CONFIG */
1272/* ========================================================================= */
1273#define UVH_SI_ALIAS2_OVERLAY_CONFIG 0xc80018UL
1274
1275#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_SHFT 24
1276#define UVH_SI_ALIAS2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL
1277#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_SHFT 48
1278#define UVH_SI_ALIAS2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL
1279#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_SHFT 63
1280#define UVH_SI_ALIAS2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL
1281
1282union uvh_si_alias2_overlay_config_u {
1283 unsigned long v;
1284 struct uvh_si_alias2_overlay_config_s {
1285 unsigned long rsvd_0_23: 24; /* */
1286 unsigned long base : 8; /* RW */
1287 unsigned long rsvd_32_47: 16; /* */
1288 unsigned long m_alias : 5; /* RW */
1289 unsigned long rsvd_53_62: 10; /* */
1290 unsigned long enable : 1; /* RW */
1291 } s;
1292};
1293
372 1294
373#endif /* __ASM_X86_UV_MMRS__ */ 1295#endif /* __ASM_X86_UV_MMRS__ */
diff --git a/include/asm-x86/mach-visws/cobalt.h b/include/asm-x86/visws/cobalt.h
index 995258831b7f..995258831b7f 100644
--- a/include/asm-x86/mach-visws/cobalt.h
+++ b/include/asm-x86/visws/cobalt.h
diff --git a/include/asm-x86/mach-visws/lithium.h b/include/asm-x86/visws/lithium.h
index dfcd4f07ab85..dfcd4f07ab85 100644
--- a/include/asm-x86/mach-visws/lithium.h
+++ b/include/asm-x86/visws/lithium.h
diff --git a/include/asm-x86/mach-visws/piix4.h b/include/asm-x86/visws/piix4.h
index 83ea4f46e419..83ea4f46e419 100644
--- a/include/asm-x86/mach-visws/piix4.h
+++ b/include/asm-x86/visws/piix4.h
diff --git a/include/asm-x86/visws/sgivw.h b/include/asm-x86/visws/sgivw.h
new file mode 100644
index 000000000000..5fbf63e1003c
--- /dev/null
+++ b/include/asm-x86/visws/sgivw.h
@@ -0,0 +1,5 @@
1/*
2 * Frame buffer position and size:
3 */
4extern unsigned long sgivwfb_mem_phys;
5extern unsigned long sgivwfb_mem_size;
diff --git a/include/asm-x86/vm86.h b/include/asm-x86/vm86.h
index 074b357146df..5ce351325e01 100644
--- a/include/asm-x86/vm86.h
+++ b/include/asm-x86/vm86.h
@@ -14,12 +14,6 @@
14 14
15#include <asm/processor-flags.h> 15#include <asm/processor-flags.h>
16 16
17#ifdef CONFIG_VM86
18#define X86_VM_MASK X86_EFLAGS_VM
19#else
20#define X86_VM_MASK 0 /* No VM86 support */
21#endif
22
23#define BIOSSEG 0x0f000 17#define BIOSSEG 0x0f000
24 18
25#define CPU_086 0 19#define CPU_086 0
@@ -121,7 +115,6 @@ struct vm86plus_info_struct {
121 unsigned long is_vm86pus:1; /* for vm86 internal use */ 115 unsigned long is_vm86pus:1; /* for vm86 internal use */
122 unsigned char vm86dbg_intxxtab[32]; /* for debugger */ 116 unsigned char vm86dbg_intxxtab[32]; /* for debugger */
123}; 117};
124
125struct vm86plus_struct { 118struct vm86plus_struct {
126 struct vm86_regs regs; 119 struct vm86_regs regs;
127 unsigned long flags; 120 unsigned long flags;
@@ -133,6 +126,9 @@ struct vm86plus_struct {
133}; 126};
134 127
135#ifdef __KERNEL__ 128#ifdef __KERNEL__
129
130#include <asm/ptrace.h>
131
136/* 132/*
137 * This is the (kernel) stack-layout when we have done a "SAVE_ALL" from vm86 133 * This is the (kernel) stack-layout when we have done a "SAVE_ALL" from vm86
138 * mode - the main change is that the old segment descriptors aren't 134 * mode - the main change is that the old segment descriptors aren't
@@ -141,7 +137,6 @@ struct vm86plus_struct {
141 * at the end of the structure. Look at ptrace.h to see the "normal" 137 * at the end of the structure. Look at ptrace.h to see the "normal"
142 * setup. For user space layout see 'struct vm86_regs' above. 138 * setup. For user space layout see 'struct vm86_regs' above.
143 */ 139 */
144#include <asm/ptrace.h>
145 140
146struct kernel_vm86_regs { 141struct kernel_vm86_regs {
147/* 142/*
diff --git a/include/asm-x86/vmi_time.h b/include/asm-x86/vmi_time.h
index 478188130328..c3118c385156 100644
--- a/include/asm-x86/vmi_time.h
+++ b/include/asm-x86/vmi_time.h
@@ -50,7 +50,7 @@ extern void __init vmi_time_init(void);
50extern unsigned long vmi_get_wallclock(void); 50extern unsigned long vmi_get_wallclock(void);
51extern int vmi_set_wallclock(unsigned long now); 51extern int vmi_set_wallclock(unsigned long now);
52extern unsigned long long vmi_sched_clock(void); 52extern unsigned long long vmi_sched_clock(void);
53extern unsigned long vmi_cpu_khz(void); 53extern unsigned long vmi_tsc_khz(void);
54 54
55#ifdef CONFIG_X86_LOCAL_APIC 55#ifdef CONFIG_X86_LOCAL_APIC
56extern void __devinit vmi_time_bsp_init(void); 56extern void __devinit vmi_time_bsp_init(void);
diff --git a/include/asm-x86/vsyscall.h b/include/asm-x86/vsyscall.h
index 17b3700949bf..6b66ff905af0 100644
--- a/include/asm-x86/vsyscall.h
+++ b/include/asm-x86/vsyscall.h
@@ -24,7 +24,8 @@ enum vsyscall_num {
24 ((unused, __section__ (".vsyscall_gtod_data"),aligned(16))) 24 ((unused, __section__ (".vsyscall_gtod_data"),aligned(16)))
25#define __section_vsyscall_clock __attribute__ \ 25#define __section_vsyscall_clock __attribute__ \
26 ((unused, __section__ (".vsyscall_clock"),aligned(16))) 26 ((unused, __section__ (".vsyscall_clock"),aligned(16)))
27#define __vsyscall_fn __attribute__ ((unused,__section__(".vsyscall_fn"))) 27#define __vsyscall_fn \
28 __attribute__ ((unused, __section__(".vsyscall_fn"))) notrace
28 29
29#define VGETCPU_RDTSCP 1 30#define VGETCPU_RDTSCP 1
30#define VGETCPU_LSL 2 31#define VGETCPU_LSL 2
diff --git a/include/asm-x86/xen/events.h b/include/asm-x86/xen/events.h
index 596312a7bfc9..f8d57ea1f05f 100644
--- a/include/asm-x86/xen/events.h
+++ b/include/asm-x86/xen/events.h
@@ -4,6 +4,7 @@
4enum ipi_vector { 4enum ipi_vector {
5 XEN_RESCHEDULE_VECTOR, 5 XEN_RESCHEDULE_VECTOR,
6 XEN_CALL_FUNCTION_VECTOR, 6 XEN_CALL_FUNCTION_VECTOR,
7 XEN_CALL_FUNCTION_SINGLE_VECTOR,
7 8
8 XEN_NR_IPIS, 9 XEN_NR_IPIS,
9}; 10};
diff --git a/include/asm-x86/xen/hypercall.h b/include/asm-x86/xen/hypercall.h
index c2ccd997ed35..2a4f9b41d684 100644
--- a/include/asm-x86/xen/hypercall.h
+++ b/include/asm-x86/xen/hypercall.h
@@ -176,9 +176,9 @@ HYPERVISOR_fpu_taskswitch(int set)
176} 176}
177 177
178static inline int 178static inline int
179HYPERVISOR_sched_op(int cmd, unsigned long arg) 179HYPERVISOR_sched_op(int cmd, void *arg)
180{ 180{
181 return _hypercall2(int, sched_op, cmd, arg); 181 return _hypercall2(int, sched_op_new, cmd, arg);
182} 182}
183 183
184static inline long 184static inline long
@@ -315,6 +315,13 @@ HYPERVISOR_nmi_op(unsigned long op, unsigned long arg)
315} 315}
316 316
317static inline void 317static inline void
318MULTI_fpu_taskswitch(struct multicall_entry *mcl, int set)
319{
320 mcl->op = __HYPERVISOR_fpu_taskswitch;
321 mcl->args[0] = set;
322}
323
324static inline void
318MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va, 325MULTI_update_va_mapping(struct multicall_entry *mcl, unsigned long va,
319 pte_t new_val, unsigned long flags) 326 pte_t new_val, unsigned long flags)
320{ 327{
diff --git a/include/asm-x86/xen/page.h b/include/asm-x86/xen/page.h
index e11f24038b1d..377c04591c15 100644
--- a/include/asm-x86/xen/page.h
+++ b/include/asm-x86/xen/page.h
@@ -26,15 +26,20 @@ typedef struct xpaddr {
26#define FOREIGN_FRAME_BIT (1UL<<31) 26#define FOREIGN_FRAME_BIT (1UL<<31)
27#define FOREIGN_FRAME(m) ((m) | FOREIGN_FRAME_BIT) 27#define FOREIGN_FRAME(m) ((m) | FOREIGN_FRAME_BIT)
28 28
29extern unsigned long *phys_to_machine_mapping; 29/* Maximum amount of memory we can handle in a domain in pages */
30#define MAX_DOMAIN_PAGES \
31 ((unsigned long)((u64)CONFIG_XEN_MAX_DOMAIN_MEMORY * 1024 * 1024 * 1024 / PAGE_SIZE))
32
33
34extern unsigned long get_phys_to_machine(unsigned long pfn);
35extern void set_phys_to_machine(unsigned long pfn, unsigned long mfn);
30 36
31static inline unsigned long pfn_to_mfn(unsigned long pfn) 37static inline unsigned long pfn_to_mfn(unsigned long pfn)
32{ 38{
33 if (xen_feature(XENFEAT_auto_translated_physmap)) 39 if (xen_feature(XENFEAT_auto_translated_physmap))
34 return pfn; 40 return pfn;
35 41
36 return phys_to_machine_mapping[(unsigned int)(pfn)] & 42 return get_phys_to_machine(pfn) & ~FOREIGN_FRAME_BIT;
37 ~FOREIGN_FRAME_BIT;
38} 43}
39 44
40static inline int phys_to_machine_mapping_valid(unsigned long pfn) 45static inline int phys_to_machine_mapping_valid(unsigned long pfn)
@@ -42,7 +47,7 @@ static inline int phys_to_machine_mapping_valid(unsigned long pfn)
42 if (xen_feature(XENFEAT_auto_translated_physmap)) 47 if (xen_feature(XENFEAT_auto_translated_physmap))
43 return 1; 48 return 1;
44 49
45 return (phys_to_machine_mapping[pfn] != INVALID_P2M_ENTRY); 50 return get_phys_to_machine(pfn) != INVALID_P2M_ENTRY;
46} 51}
47 52
48static inline unsigned long mfn_to_pfn(unsigned long mfn) 53static inline unsigned long mfn_to_pfn(unsigned long mfn)
@@ -106,20 +111,12 @@ static inline unsigned long mfn_to_local_pfn(unsigned long mfn)
106 unsigned long pfn = mfn_to_pfn(mfn); 111 unsigned long pfn = mfn_to_pfn(mfn);
107 if ((pfn < max_mapnr) 112 if ((pfn < max_mapnr)
108 && !xen_feature(XENFEAT_auto_translated_physmap) 113 && !xen_feature(XENFEAT_auto_translated_physmap)
109 && (phys_to_machine_mapping[pfn] != mfn)) 114 && (get_phys_to_machine(pfn) != mfn))
110 return max_mapnr; /* force !pfn_valid() */ 115 return max_mapnr; /* force !pfn_valid() */
116 /* XXX fixme; not true with sparsemem */
111 return pfn; 117 return pfn;
112} 118}
113 119
114static inline void set_phys_to_machine(unsigned long pfn, unsigned long mfn)
115{
116 if (xen_feature(XENFEAT_auto_translated_physmap)) {
117 BUG_ON(pfn != mfn && mfn != INVALID_P2M_ENTRY);
118 return;
119 }
120 phys_to_machine_mapping[pfn] = mfn;
121}
122
123/* VIRT <-> MACHINE conversion */ 120/* VIRT <-> MACHINE conversion */
124#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v)))) 121#define virt_to_machine(v) (phys_to_machine(XPADDR(__pa(v))))
125#define virt_to_mfn(v) (pfn_to_mfn(PFN_DOWN(__pa(v)))) 122#define virt_to_mfn(v) (pfn_to_mfn(PFN_DOWN(__pa(v))))
diff --git a/include/asm-x86/xor_32.h b/include/asm-x86/xor_32.h
index 067b5c1835a3..921b45840449 100644
--- a/include/asm-x86/xor_32.h
+++ b/include/asm-x86/xor_32.h
@@ -1,3 +1,6 @@
1#ifndef ASM_X86__XOR_32_H
2#define ASM_X86__XOR_32_H
3
1/* 4/*
2 * Optimized RAID-5 checksumming functions for MMX and SSE. 5 * Optimized RAID-5 checksumming functions for MMX and SSE.
3 * 6 *
@@ -881,3 +884,5 @@ do { \
881 deals with a load to a line that is being prefetched. */ 884 deals with a load to a line that is being prefetched. */
882#define XOR_SELECT_TEMPLATE(FASTEST) \ 885#define XOR_SELECT_TEMPLATE(FASTEST) \
883 (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST) 886 (cpu_has_xmm ? &xor_block_pIII_sse : FASTEST)
887
888#endif /* ASM_X86__XOR_32_H */
diff --git a/include/asm-x86/xor_64.h b/include/asm-x86/xor_64.h
index 24957e39ac8a..2d3a18de295b 100644
--- a/include/asm-x86/xor_64.h
+++ b/include/asm-x86/xor_64.h
@@ -1,3 +1,6 @@
1#ifndef ASM_X86__XOR_64_H
2#define ASM_X86__XOR_64_H
3
1/* 4/*
2 * Optimized RAID-5 checksumming functions for MMX and SSE. 5 * Optimized RAID-5 checksumming functions for MMX and SSE.
3 * 6 *
@@ -354,3 +357,5 @@ do { \
354 We may also be able to load into the L1 only depending on how the cpu 357 We may also be able to load into the L1 only depending on how the cpu
355 deals with a load to a line that is being prefetched. */ 358 deals with a load to a line that is being prefetched. */
356#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse) 359#define XOR_SELECT_TEMPLATE(FASTEST) (&xor_block_sse)
360
361#endif /* ASM_X86__XOR_64_H */
diff --git a/include/crypto/hash.h b/include/crypto/hash.h
new file mode 100644
index 000000000000..d12498ec8a4e
--- /dev/null
+++ b/include/crypto/hash.h
@@ -0,0 +1,154 @@
1/*
2 * Hash: Hash algorithms under the crypto API
3 *
4 * Copyright (c) 2008 Herbert Xu <herbert@gondor.apana.org.au>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 */
12
13#ifndef _CRYPTO_HASH_H
14#define _CRYPTO_HASH_H
15
16#include <linux/crypto.h>
17
18struct crypto_ahash {
19 struct crypto_tfm base;
20};
21
22static inline struct crypto_ahash *__crypto_ahash_cast(struct crypto_tfm *tfm)
23{
24 return (struct crypto_ahash *)tfm;
25}
26
27static inline struct crypto_ahash *crypto_alloc_ahash(const char *alg_name,
28 u32 type, u32 mask)
29{
30 type &= ~CRYPTO_ALG_TYPE_MASK;
31 mask &= ~CRYPTO_ALG_TYPE_MASK;
32 type |= CRYPTO_ALG_TYPE_AHASH;
33 mask |= CRYPTO_ALG_TYPE_AHASH_MASK;
34
35 return __crypto_ahash_cast(crypto_alloc_base(alg_name, type, mask));
36}
37
38static inline struct crypto_tfm *crypto_ahash_tfm(struct crypto_ahash *tfm)
39{
40 return &tfm->base;
41}
42
43static inline void crypto_free_ahash(struct crypto_ahash *tfm)
44{
45 crypto_free_tfm(crypto_ahash_tfm(tfm));
46}
47
48static inline unsigned int crypto_ahash_alignmask(
49 struct crypto_ahash *tfm)
50{
51 return crypto_tfm_alg_alignmask(crypto_ahash_tfm(tfm));
52}
53
54static inline struct ahash_tfm *crypto_ahash_crt(struct crypto_ahash *tfm)
55{
56 return &crypto_ahash_tfm(tfm)->crt_ahash;
57}
58
59static inline unsigned int crypto_ahash_digestsize(struct crypto_ahash *tfm)
60{
61 return crypto_ahash_crt(tfm)->digestsize;
62}
63
64static inline u32 crypto_ahash_get_flags(struct crypto_ahash *tfm)
65{
66 return crypto_tfm_get_flags(crypto_ahash_tfm(tfm));
67}
68
69static inline void crypto_ahash_set_flags(struct crypto_ahash *tfm, u32 flags)
70{
71 crypto_tfm_set_flags(crypto_ahash_tfm(tfm), flags);
72}
73
74static inline void crypto_ahash_clear_flags(struct crypto_ahash *tfm, u32 flags)
75{
76 crypto_tfm_clear_flags(crypto_ahash_tfm(tfm), flags);
77}
78
79static inline struct crypto_ahash *crypto_ahash_reqtfm(
80 struct ahash_request *req)
81{
82 return __crypto_ahash_cast(req->base.tfm);
83}
84
85static inline unsigned int crypto_ahash_reqsize(struct crypto_ahash *tfm)
86{
87 return crypto_ahash_crt(tfm)->reqsize;
88}
89
90static inline int crypto_ahash_setkey(struct crypto_ahash *tfm,
91 const u8 *key, unsigned int keylen)
92{
93 struct ahash_tfm *crt = crypto_ahash_crt(tfm);
94
95 return crt->setkey(tfm, key, keylen);
96}
97
98static inline int crypto_ahash_digest(struct ahash_request *req)
99{
100 struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req));
101 return crt->digest(req);
102}
103
104static inline void ahash_request_set_tfm(struct ahash_request *req,
105 struct crypto_ahash *tfm)
106{
107 req->base.tfm = crypto_ahash_tfm(tfm);
108}
109
110static inline struct ahash_request *ahash_request_alloc(
111 struct crypto_ahash *tfm, gfp_t gfp)
112{
113 struct ahash_request *req;
114
115 req = kmalloc(sizeof(struct ahash_request) +
116 crypto_ahash_reqsize(tfm), gfp);
117
118 if (likely(req))
119 ahash_request_set_tfm(req, tfm);
120
121 return req;
122}
123
124static inline void ahash_request_free(struct ahash_request *req)
125{
126 kfree(req);
127}
128
129static inline struct ahash_request *ahash_request_cast(
130 struct crypto_async_request *req)
131{
132 return container_of(req, struct ahash_request, base);
133}
134
135static inline void ahash_request_set_callback(struct ahash_request *req,
136 u32 flags,
137 crypto_completion_t complete,
138 void *data)
139{
140 req->base.complete = complete;
141 req->base.data = data;
142 req->base.flags = flags;
143}
144
145static inline void ahash_request_set_crypt(struct ahash_request *req,
146 struct scatterlist *src, u8 *result,
147 unsigned int nbytes)
148{
149 req->src = src;
150 req->nbytes = nbytes;
151 req->result = result;
152}
153
154#endif /* _CRYPTO_HASH_H */
diff --git a/include/crypto/internal/hash.h b/include/crypto/internal/hash.h
new file mode 100644
index 000000000000..917ae57bad4a
--- /dev/null
+++ b/include/crypto/internal/hash.h
@@ -0,0 +1,78 @@
1/*
2 * Hash algorithms.
3 *
4 * Copyright (c) 2008 Herbert Xu <herbert@gondor.apana.org.au>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 *
11 */
12
13#ifndef _CRYPTO_INTERNAL_HASH_H
14#define _CRYPTO_INTERNAL_HASH_H
15
16#include <crypto/algapi.h>
17#include <crypto/hash.h>
18
19struct ahash_request;
20struct scatterlist;
21
22struct crypto_hash_walk {
23 char *data;
24
25 unsigned int offset;
26 unsigned int alignmask;
27
28 struct page *pg;
29 unsigned int entrylen;
30
31 unsigned int total;
32 struct scatterlist *sg;
33
34 unsigned int flags;
35};
36
37extern const struct crypto_type crypto_ahash_type;
38
39int crypto_hash_walk_done(struct crypto_hash_walk *walk, int err);
40int crypto_hash_walk_first(struct ahash_request *req,
41 struct crypto_hash_walk *walk);
42
43static inline void *crypto_ahash_ctx(struct crypto_ahash *tfm)
44{
45 return crypto_tfm_ctx(&tfm->base);
46}
47
48static inline struct ahash_alg *crypto_ahash_alg(
49 struct crypto_ahash *tfm)
50{
51 return &crypto_ahash_tfm(tfm)->__crt_alg->cra_ahash;
52}
53
54static inline int ahash_enqueue_request(struct crypto_queue *queue,
55 struct ahash_request *request)
56{
57 return crypto_enqueue_request(queue, &request->base);
58}
59
60static inline struct ahash_request *ahash_dequeue_request(
61 struct crypto_queue *queue)
62{
63 return ahash_request_cast(crypto_dequeue_request(queue));
64}
65
66static inline void *ahash_request_ctx(struct ahash_request *req)
67{
68 return req->__ctx;
69}
70
71static inline int ahash_tfm_in_queue(struct crypto_queue *queue,
72 struct crypto_ahash *tfm)
73{
74 return crypto_tfm_in_queue(queue, crypto_ahash_tfm(tfm));
75}
76
77#endif /* _CRYPTO_INTERNAL_HASH_H */
78
diff --git a/include/drm/Kbuild b/include/drm/Kbuild
new file mode 100644
index 000000000000..82b6983b7fbb
--- /dev/null
+++ b/include/drm/Kbuild
@@ -0,0 +1,10 @@
1unifdef-y += drm.h drm_sarea.h
2unifdef-y += i810_drm.h
3unifdef-y += i830_drm.h
4unifdef-y += i915_drm.h
5unifdef-y += mga_drm.h
6unifdef-y += r128_drm.h
7unifdef-y += radeon_drm.h
8unifdef-y += sis_drm.h
9unifdef-y += savage_drm.h
10unifdef-y += via_drm.h
diff --git a/include/drm/drm.h b/include/drm/drm.h
new file mode 100644
index 000000000000..38d3c6b8276a
--- /dev/null
+++ b/include/drm/drm.h
@@ -0,0 +1,694 @@
1/**
2 * \file drm.h
3 * Header for the Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 *
7 * \par Acknowledgments:
8 * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg.
9 */
10
11/*
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All rights reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
35
36#ifndef _DRM_H_
37#define _DRM_H_
38
39#if defined(__linux__)
40#if defined(__KERNEL__)
41#endif
42#include <asm/ioctl.h> /* For _IO* macros */
43#define DRM_IOCTL_NR(n) _IOC_NR(n)
44#define DRM_IOC_VOID _IOC_NONE
45#define DRM_IOC_READ _IOC_READ
46#define DRM_IOC_WRITE _IOC_WRITE
47#define DRM_IOC_READWRITE _IOC_READ|_IOC_WRITE
48#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
49#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
50#if defined(__FreeBSD__) && defined(IN_MODULE)
51/* Prevent name collision when including sys/ioccom.h */
52#undef ioctl
53#include <sys/ioccom.h>
54#define ioctl(a,b,c) xf86ioctl(a,b,c)
55#else
56#include <sys/ioccom.h>
57#endif /* __FreeBSD__ && xf86ioctl */
58#define DRM_IOCTL_NR(n) ((n) & 0xff)
59#define DRM_IOC_VOID IOC_VOID
60#define DRM_IOC_READ IOC_OUT
61#define DRM_IOC_WRITE IOC_IN
62#define DRM_IOC_READWRITE IOC_INOUT
63#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
64#endif
65
66#define DRM_MAJOR 226
67#define DRM_MAX_MINOR 15
68
69#define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */
70#define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */
71#define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */
72#define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */
73
74#define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */
75#define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */
76#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
77#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
78#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT))
79
80typedef unsigned int drm_handle_t;
81typedef unsigned int drm_context_t;
82typedef unsigned int drm_drawable_t;
83typedef unsigned int drm_magic_t;
84
85/**
86 * Cliprect.
87 *
88 * \warning: If you change this structure, make sure you change
89 * XF86DRIClipRectRec in the server as well
90 *
91 * \note KW: Actually it's illegal to change either for
92 * backwards-compatibility reasons.
93 */
94struct drm_clip_rect {
95 unsigned short x1;
96 unsigned short y1;
97 unsigned short x2;
98 unsigned short y2;
99};
100
101/**
102 * Drawable information.
103 */
104struct drm_drawable_info {
105 unsigned int num_rects;
106 struct drm_clip_rect *rects;
107};
108
109/**
110 * Texture region,
111 */
112struct drm_tex_region {
113 unsigned char next;
114 unsigned char prev;
115 unsigned char in_use;
116 unsigned char padding;
117 unsigned int age;
118};
119
120/**
121 * Hardware lock.
122 *
123 * The lock structure is a simple cache-line aligned integer. To avoid
124 * processor bus contention on a multiprocessor system, there should not be any
125 * other data stored in the same cache line.
126 */
127struct drm_hw_lock {
128 __volatile__ unsigned int lock; /**< lock variable */
129 char padding[60]; /**< Pad to cache line */
130};
131
132/**
133 * DRM_IOCTL_VERSION ioctl argument type.
134 *
135 * \sa drmGetVersion().
136 */
137struct drm_version {
138 int version_major; /**< Major version */
139 int version_minor; /**< Minor version */
140 int version_patchlevel; /**< Patch level */
141 size_t name_len; /**< Length of name buffer */
142 char __user *name; /**< Name of driver */
143 size_t date_len; /**< Length of date buffer */
144 char __user *date; /**< User-space buffer to hold date */
145 size_t desc_len; /**< Length of desc buffer */
146 char __user *desc; /**< User-space buffer to hold desc */
147};
148
149/**
150 * DRM_IOCTL_GET_UNIQUE ioctl argument type.
151 *
152 * \sa drmGetBusid() and drmSetBusId().
153 */
154struct drm_unique {
155 size_t unique_len; /**< Length of unique */
156 char __user *unique; /**< Unique name for driver instantiation */
157};
158
159struct drm_list {
160 int count; /**< Length of user-space structures */
161 struct drm_version __user *version;
162};
163
164struct drm_block {
165 int unused;
166};
167
168/**
169 * DRM_IOCTL_CONTROL ioctl argument type.
170 *
171 * \sa drmCtlInstHandler() and drmCtlUninstHandler().
172 */
173struct drm_control {
174 enum {
175 DRM_ADD_COMMAND,
176 DRM_RM_COMMAND,
177 DRM_INST_HANDLER,
178 DRM_UNINST_HANDLER
179 } func;
180 int irq;
181};
182
183/**
184 * Type of memory to map.
185 */
186enum drm_map_type {
187 _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */
188 _DRM_REGISTERS = 1, /**< no caching, no core dump */
189 _DRM_SHM = 2, /**< shared, cached */
190 _DRM_AGP = 3, /**< AGP/GART */
191 _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */
192 _DRM_CONSISTENT = 5, /**< Consistent memory for PCI DMA */
193};
194
195/**
196 * Memory mapping flags.
197 */
198enum drm_map_flags {
199 _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */
200 _DRM_READ_ONLY = 0x02,
201 _DRM_LOCKED = 0x04, /**< shared, cached, locked */
202 _DRM_KERNEL = 0x08, /**< kernel requires access */
203 _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */
204 _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */
205 _DRM_REMOVABLE = 0x40, /**< Removable mapping */
206 _DRM_DRIVER = 0x80 /**< Managed by driver */
207};
208
209struct drm_ctx_priv_map {
210 unsigned int ctx_id; /**< Context requesting private mapping */
211 void *handle; /**< Handle of map */
212};
213
214/**
215 * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
216 * argument type.
217 *
218 * \sa drmAddMap().
219 */
220struct drm_map {
221 unsigned long offset; /**< Requested physical address (0 for SAREA)*/
222 unsigned long size; /**< Requested physical size (bytes) */
223 enum drm_map_type type; /**< Type of memory to map */
224 enum drm_map_flags flags; /**< Flags */
225 void *handle; /**< User-space: "Handle" to pass to mmap() */
226 /**< Kernel-space: kernel-virtual address */
227 int mtrr; /**< MTRR slot used */
228 /* Private data */
229};
230
231/**
232 * DRM_IOCTL_GET_CLIENT ioctl argument type.
233 */
234struct drm_client {
235 int idx; /**< Which client desired? */
236 int auth; /**< Is client authenticated? */
237 unsigned long pid; /**< Process ID */
238 unsigned long uid; /**< User ID */
239 unsigned long magic; /**< Magic */
240 unsigned long iocs; /**< Ioctl count */
241};
242
243enum drm_stat_type {
244 _DRM_STAT_LOCK,
245 _DRM_STAT_OPENS,
246 _DRM_STAT_CLOSES,
247 _DRM_STAT_IOCTLS,
248 _DRM_STAT_LOCKS,
249 _DRM_STAT_UNLOCKS,
250 _DRM_STAT_VALUE, /**< Generic value */
251 _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */
252 _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */
253
254 _DRM_STAT_IRQ, /**< IRQ */
255 _DRM_STAT_PRIMARY, /**< Primary DMA bytes */
256 _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */
257 _DRM_STAT_DMA, /**< DMA */
258 _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */
259 _DRM_STAT_MISSED /**< Missed DMA opportunity */
260 /* Add to the *END* of the list */
261};
262
263/**
264 * DRM_IOCTL_GET_STATS ioctl argument type.
265 */
266struct drm_stats {
267 unsigned long count;
268 struct {
269 unsigned long value;
270 enum drm_stat_type type;
271 } data[15];
272};
273
274/**
275 * Hardware locking flags.
276 */
277enum drm_lock_flags {
278 _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */
279 _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */
280 _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */
281 _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */
282 /* These *HALT* flags aren't supported yet
283 -- they will be used to support the
284 full-screen DGA-like mode. */
285 _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */
286 _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */
287};
288
289/**
290 * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
291 *
292 * \sa drmGetLock() and drmUnlock().
293 */
294struct drm_lock {
295 int context;
296 enum drm_lock_flags flags;
297};
298
299/**
300 * DMA flags
301 *
302 * \warning
303 * These values \e must match xf86drm.h.
304 *
305 * \sa drm_dma.
306 */
307enum drm_dma_flags {
308 /* Flags for DMA buffer dispatch */
309 _DRM_DMA_BLOCK = 0x01, /**<
310 * Block until buffer dispatched.
311 *
312 * \note The buffer may not yet have
313 * been processed by the hardware --
314 * getting a hardware lock with the
315 * hardware quiescent will ensure
316 * that the buffer has been
317 * processed.
318 */
319 _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */
320 _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */
321
322 /* Flags for DMA buffer request */
323 _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */
324 _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */
325 _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */
326};
327
328/**
329 * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
330 *
331 * \sa drmAddBufs().
332 */
333struct drm_buf_desc {
334 int count; /**< Number of buffers of this size */
335 int size; /**< Size in bytes */
336 int low_mark; /**< Low water mark */
337 int high_mark; /**< High water mark */
338 enum {
339 _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */
340 _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */
341 _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */
342 _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */
343 _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */
344 } flags;
345 unsigned long agp_start; /**<
346 * Start address of where the AGP buffers are
347 * in the AGP aperture
348 */
349};
350
351/**
352 * DRM_IOCTL_INFO_BUFS ioctl argument type.
353 */
354struct drm_buf_info {
355 int count; /**< Entries in list */
356 struct drm_buf_desc __user *list;
357};
358
359/**
360 * DRM_IOCTL_FREE_BUFS ioctl argument type.
361 */
362struct drm_buf_free {
363 int count;
364 int __user *list;
365};
366
367/**
368 * Buffer information
369 *
370 * \sa drm_buf_map.
371 */
372struct drm_buf_pub {
373 int idx; /**< Index into the master buffer list */
374 int total; /**< Buffer size */
375 int used; /**< Amount of buffer in use (for DMA) */
376 void __user *address; /**< Address of buffer */
377};
378
379/**
380 * DRM_IOCTL_MAP_BUFS ioctl argument type.
381 */
382struct drm_buf_map {
383 int count; /**< Length of the buffer list */
384 void __user *virtual; /**< Mmap'd area in user-virtual */
385 struct drm_buf_pub __user *list; /**< Buffer information */
386};
387
388/**
389 * DRM_IOCTL_DMA ioctl argument type.
390 *
391 * Indices here refer to the offset into the buffer list in drm_buf_get.
392 *
393 * \sa drmDMA().
394 */
395struct drm_dma {
396 int context; /**< Context handle */
397 int send_count; /**< Number of buffers to send */
398 int __user *send_indices; /**< List of handles to buffers */
399 int __user *send_sizes; /**< Lengths of data to send */
400 enum drm_dma_flags flags; /**< Flags */
401 int request_count; /**< Number of buffers requested */
402 int request_size; /**< Desired size for buffers */
403 int __user *request_indices; /**< Buffer information */
404 int __user *request_sizes;
405 int granted_count; /**< Number of buffers granted */
406};
407
408enum drm_ctx_flags {
409 _DRM_CONTEXT_PRESERVED = 0x01,
410 _DRM_CONTEXT_2DONLY = 0x02
411};
412
413/**
414 * DRM_IOCTL_ADD_CTX ioctl argument type.
415 *
416 * \sa drmCreateContext() and drmDestroyContext().
417 */
418struct drm_ctx {
419 drm_context_t handle;
420 enum drm_ctx_flags flags;
421};
422
423/**
424 * DRM_IOCTL_RES_CTX ioctl argument type.
425 */
426struct drm_ctx_res {
427 int count;
428 struct drm_ctx __user *contexts;
429};
430
431/**
432 * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
433 */
434struct drm_draw {
435 drm_drawable_t handle;
436};
437
438/**
439 * DRM_IOCTL_UPDATE_DRAW ioctl argument type.
440 */
441typedef enum {
442 DRM_DRAWABLE_CLIPRECTS,
443} drm_drawable_info_type_t;
444
445struct drm_update_draw {
446 drm_drawable_t handle;
447 unsigned int type;
448 unsigned int num;
449 unsigned long long data;
450};
451
452/**
453 * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
454 */
455struct drm_auth {
456 drm_magic_t magic;
457};
458
459/**
460 * DRM_IOCTL_IRQ_BUSID ioctl argument type.
461 *
462 * \sa drmGetInterruptFromBusID().
463 */
464struct drm_irq_busid {
465 int irq; /**< IRQ number */
466 int busnum; /**< bus number */
467 int devnum; /**< device number */
468 int funcnum; /**< function number */
469};
470
471enum drm_vblank_seq_type {
472 _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */
473 _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */
474 _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */
475 _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */
476 _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
477};
478
479#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE)
480#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL | _DRM_VBLANK_SECONDARY | \
481 _DRM_VBLANK_NEXTONMISS)
482
483struct drm_wait_vblank_request {
484 enum drm_vblank_seq_type type;
485 unsigned int sequence;
486 unsigned long signal;
487};
488
489struct drm_wait_vblank_reply {
490 enum drm_vblank_seq_type type;
491 unsigned int sequence;
492 long tval_sec;
493 long tval_usec;
494};
495
496/**
497 * DRM_IOCTL_WAIT_VBLANK ioctl argument type.
498 *
499 * \sa drmWaitVBlank().
500 */
501union drm_wait_vblank {
502 struct drm_wait_vblank_request request;
503 struct drm_wait_vblank_reply reply;
504};
505
506/**
507 * DRM_IOCTL_AGP_ENABLE ioctl argument type.
508 *
509 * \sa drmAgpEnable().
510 */
511struct drm_agp_mode {
512 unsigned long mode; /**< AGP mode */
513};
514
515/**
516 * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
517 *
518 * \sa drmAgpAlloc() and drmAgpFree().
519 */
520struct drm_agp_buffer {
521 unsigned long size; /**< In bytes -- will round to page boundary */
522 unsigned long handle; /**< Used for binding / unbinding */
523 unsigned long type; /**< Type of memory to allocate */
524 unsigned long physical; /**< Physical used by i810 */
525};
526
527/**
528 * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
529 *
530 * \sa drmAgpBind() and drmAgpUnbind().
531 */
532struct drm_agp_binding {
533 unsigned long handle; /**< From drm_agp_buffer */
534 unsigned long offset; /**< In bytes -- will round to page boundary */
535};
536
537/**
538 * DRM_IOCTL_AGP_INFO ioctl argument type.
539 *
540 * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
541 * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
542 * drmAgpVendorId() and drmAgpDeviceId().
543 */
544struct drm_agp_info {
545 int agp_version_major;
546 int agp_version_minor;
547 unsigned long mode;
548 unsigned long aperture_base; /* physical address */
549 unsigned long aperture_size; /* bytes */
550 unsigned long memory_allowed; /* bytes */
551 unsigned long memory_used;
552
553 /* PCI information */
554 unsigned short id_vendor;
555 unsigned short id_device;
556};
557
558/**
559 * DRM_IOCTL_SG_ALLOC ioctl argument type.
560 */
561struct drm_scatter_gather {
562 unsigned long size; /**< In bytes -- will round to page boundary */
563 unsigned long handle; /**< Used for mapping / unmapping */
564};
565
566/**
567 * DRM_IOCTL_SET_VERSION ioctl argument type.
568 */
569struct drm_set_version {
570 int drm_di_major;
571 int drm_di_minor;
572 int drm_dd_major;
573 int drm_dd_minor;
574};
575
576#define DRM_IOCTL_BASE 'd'
577#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
578#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
579#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
580#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
581
582#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
583#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
584#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
585#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
586#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
587#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
588#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
589#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
590
591#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
592#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
593#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
594#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
595#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
596#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
597#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
598#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
599#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
600#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
601#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
602
603#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
604
605#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
606#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
607
608#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
609#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
610#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
611#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
612#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
613#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
614#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
615#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
616#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
617#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
618#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
619#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
620#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
621
622#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
623#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
624#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
625#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
626#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
627#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
628#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
629#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
630
631#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
632#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
633
634#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
635
636#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
637
638/**
639 * Device specific ioctls should only be in their respective headers
640 * The device specific ioctl range is from 0x40 to 0x99.
641 * Generic IOCTLS restart at 0xA0.
642 *
643 * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
644 * drmCommandReadWrite().
645 */
646#define DRM_COMMAND_BASE 0x40
647#define DRM_COMMAND_END 0xA0
648
649/* typedef area */
650#ifndef __KERNEL__
651typedef struct drm_clip_rect drm_clip_rect_t;
652typedef struct drm_drawable_info drm_drawable_info_t;
653typedef struct drm_tex_region drm_tex_region_t;
654typedef struct drm_hw_lock drm_hw_lock_t;
655typedef struct drm_version drm_version_t;
656typedef struct drm_unique drm_unique_t;
657typedef struct drm_list drm_list_t;
658typedef struct drm_block drm_block_t;
659typedef struct drm_control drm_control_t;
660typedef enum drm_map_type drm_map_type_t;
661typedef enum drm_map_flags drm_map_flags_t;
662typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
663typedef struct drm_map drm_map_t;
664typedef struct drm_client drm_client_t;
665typedef enum drm_stat_type drm_stat_type_t;
666typedef struct drm_stats drm_stats_t;
667typedef enum drm_lock_flags drm_lock_flags_t;
668typedef struct drm_lock drm_lock_t;
669typedef enum drm_dma_flags drm_dma_flags_t;
670typedef struct drm_buf_desc drm_buf_desc_t;
671typedef struct drm_buf_info drm_buf_info_t;
672typedef struct drm_buf_free drm_buf_free_t;
673typedef struct drm_buf_pub drm_buf_pub_t;
674typedef struct drm_buf_map drm_buf_map_t;
675typedef struct drm_dma drm_dma_t;
676typedef union drm_wait_vblank drm_wait_vblank_t;
677typedef struct drm_agp_mode drm_agp_mode_t;
678typedef enum drm_ctx_flags drm_ctx_flags_t;
679typedef struct drm_ctx drm_ctx_t;
680typedef struct drm_ctx_res drm_ctx_res_t;
681typedef struct drm_draw drm_draw_t;
682typedef struct drm_update_draw drm_update_draw_t;
683typedef struct drm_auth drm_auth_t;
684typedef struct drm_irq_busid drm_irq_busid_t;
685typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
686
687typedef struct drm_agp_buffer drm_agp_buffer_t;
688typedef struct drm_agp_binding drm_agp_binding_t;
689typedef struct drm_agp_info drm_agp_info_t;
690typedef struct drm_scatter_gather drm_scatter_gather_t;
691typedef struct drm_set_version drm_set_version_t;
692#endif
693
694#endif
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
new file mode 100644
index 000000000000..1c1b13e29223
--- /dev/null
+++ b/include/drm/drmP.h
@@ -0,0 +1,1154 @@
1/**
2 * \file drmP.h
3 * Private header for Direct Rendering Manager
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com>
7 */
8
9/*
10 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12 * All rights reserved.
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
23 * Software.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
31 * OTHER DEALINGS IN THE SOFTWARE.
32 */
33
34#ifndef _DRM_P_H_
35#define _DRM_P_H_
36
37/* If you want the memory alloc debug functionality, change define below */
38/* #define DEBUG_MEMORY */
39
40#ifdef __KERNEL__
41#ifdef __alpha__
42/* add include of current.h so that "current" is defined
43 * before static inline funcs in wait.h. Doing this so we
44 * can build the DRM (part of PI DRI). 4/21/2000 S + B */
45#include <asm/current.h>
46#endif /* __alpha__ */
47#include <linux/module.h>
48#include <linux/kernel.h>
49#include <linux/miscdevice.h>
50#include <linux/fs.h>
51#include <linux/proc_fs.h>
52#include <linux/init.h>
53#include <linux/file.h>
54#include <linux/pci.h>
55#include <linux/jiffies.h>
56#include <linux/smp_lock.h> /* For (un)lock_kernel */
57#include <linux/dma-mapping.h>
58#include <linux/mm.h>
59#include <linux/cdev.h>
60#include <linux/mutex.h>
61#if defined(__alpha__) || defined(__powerpc__)
62#include <asm/pgtable.h> /* For pte_wrprotect */
63#endif
64#include <asm/io.h>
65#include <asm/mman.h>
66#include <asm/uaccess.h>
67#ifdef CONFIG_MTRR
68#include <asm/mtrr.h>
69#endif
70#if defined(CONFIG_AGP) || defined(CONFIG_AGP_MODULE)
71#include <linux/types.h>
72#include <linux/agp_backend.h>
73#endif
74#include <linux/workqueue.h>
75#include <linux/poll.h>
76#include <asm/pgalloc.h>
77#include "drm.h"
78
79#include <linux/idr.h>
80
81#define __OS_HAS_AGP (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
82#define __OS_HAS_MTRR (defined(CONFIG_MTRR))
83
84struct drm_file;
85struct drm_device;
86
87#include "drm_os_linux.h"
88#include "drm_hashtab.h"
89
90/***********************************************************************/
91/** \name DRM template customization defaults */
92/*@{*/
93
94/* driver capabilities and requirements mask */
95#define DRIVER_USE_AGP 0x1
96#define DRIVER_REQUIRE_AGP 0x2
97#define DRIVER_USE_MTRR 0x4
98#define DRIVER_PCI_DMA 0x8
99#define DRIVER_SG 0x10
100#define DRIVER_HAVE_DMA 0x20
101#define DRIVER_HAVE_IRQ 0x40
102#define DRIVER_IRQ_SHARED 0x80
103#define DRIVER_IRQ_VBL 0x100
104#define DRIVER_DMA_QUEUE 0x200
105#define DRIVER_FB_DMA 0x400
106#define DRIVER_IRQ_VBL2 0x800
107
108/***********************************************************************/
109/** \name Begin the DRM... */
110/*@{*/
111
112#define DRM_DEBUG_CODE 2 /**< Include debugging code if > 1, then
113 also include looping detection. */
114
115#define DRM_MAGIC_HASH_ORDER 4 /**< Size of key hash table. Must be power of 2. */
116#define DRM_KERNEL_CONTEXT 0 /**< Change drm_resctx if changed */
117#define DRM_RESERVED_CONTEXTS 1 /**< Change drm_resctx if changed */
118#define DRM_LOOPING_LIMIT 5000000
119#define DRM_TIME_SLICE (HZ/20) /**< Time slice for GLXContexts */
120#define DRM_LOCK_SLICE 1 /**< Time slice for lock, in jiffies */
121
122#define DRM_FLAG_DEBUG 0x01
123
124#define DRM_MEM_DMA 0
125#define DRM_MEM_SAREA 1
126#define DRM_MEM_DRIVER 2
127#define DRM_MEM_MAGIC 3
128#define DRM_MEM_IOCTLS 4
129#define DRM_MEM_MAPS 5
130#define DRM_MEM_VMAS 6
131#define DRM_MEM_BUFS 7
132#define DRM_MEM_SEGS 8
133#define DRM_MEM_PAGES 9
134#define DRM_MEM_FILES 10
135#define DRM_MEM_QUEUES 11
136#define DRM_MEM_CMDS 12
137#define DRM_MEM_MAPPINGS 13
138#define DRM_MEM_BUFLISTS 14
139#define DRM_MEM_AGPLISTS 15
140#define DRM_MEM_TOTALAGP 16
141#define DRM_MEM_BOUNDAGP 17
142#define DRM_MEM_CTXBITMAP 18
143#define DRM_MEM_STUB 19
144#define DRM_MEM_SGLISTS 20
145#define DRM_MEM_CTXLIST 21
146#define DRM_MEM_MM 22
147#define DRM_MEM_HASHTAB 23
148
149#define DRM_MAX_CTXBITMAP (PAGE_SIZE * 8)
150#define DRM_MAP_HASH_OFFSET 0x10000000
151
152/*@}*/
153
154/***********************************************************************/
155/** \name Macros to make printk easier */
156/*@{*/
157
158/**
159 * Error output.
160 *
161 * \param fmt printf() like format string.
162 * \param arg arguments
163 */
164#define DRM_ERROR(fmt, arg...) \
165 printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg)
166
167/**
168 * Memory error output.
169 *
170 * \param area memory area where the error occurred.
171 * \param fmt printf() like format string.
172 * \param arg arguments
173 */
174#define DRM_MEM_ERROR(area, fmt, arg...) \
175 printk(KERN_ERR "[" DRM_NAME ":%s:%s] *ERROR* " fmt , __func__, \
176 drm_mem_stats[area].name , ##arg)
177
178#define DRM_INFO(fmt, arg...) printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg)
179
180/**
181 * Debug output.
182 *
183 * \param fmt printf() like format string.
184 * \param arg arguments
185 */
186#if DRM_DEBUG_CODE
187#define DRM_DEBUG(fmt, arg...) \
188 do { \
189 if ( drm_debug ) \
190 printk(KERN_DEBUG \
191 "[" DRM_NAME ":%s] " fmt , \
192 __func__ , ##arg); \
193 } while (0)
194#else
195#define DRM_DEBUG(fmt, arg...) do { } while (0)
196#endif
197
198#define DRM_PROC_LIMIT (PAGE_SIZE-80)
199
200#define DRM_PROC_PRINT(fmt, arg...) \
201 len += sprintf(&buf[len], fmt , ##arg); \
202 if (len > DRM_PROC_LIMIT) { *eof = 1; return len - offset; }
203
204#define DRM_PROC_PRINT_RET(ret, fmt, arg...) \
205 len += sprintf(&buf[len], fmt , ##arg); \
206 if (len > DRM_PROC_LIMIT) { ret; *eof = 1; return len - offset; }
207
208/*@}*/
209
210/***********************************************************************/
211/** \name Internal types and structures */
212/*@{*/
213
214#define DRM_ARRAY_SIZE(x) ARRAY_SIZE(x)
215
216#define DRM_LEFTCOUNT(x) (((x)->rp + (x)->count - (x)->wp) % ((x)->count + 1))
217#define DRM_BUFCOUNT(x) ((x)->count - DRM_LEFTCOUNT(x))
218#define DRM_WAITCOUNT(dev,idx) DRM_BUFCOUNT(&dev->queuelist[idx]->waitlist)
219
220#define DRM_IF_VERSION(maj, min) (maj << 16 | min)
221/**
222 * Get the private SAREA mapping.
223 *
224 * \param _dev DRM device.
225 * \param _ctx context number.
226 * \param _map output mapping.
227 */
228#define DRM_GET_PRIV_SAREA(_dev, _ctx, _map) do { \
229 (_map) = (_dev)->context_sareas[_ctx]; \
230} while(0)
231
232/**
233 * Test that the hardware lock is held by the caller, returning otherwise.
234 *
235 * \param dev DRM device.
236 * \param filp file pointer of the caller.
237 */
238#define LOCK_TEST_WITH_RETURN( dev, file_priv ) \
239do { \
240 if ( !_DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ) || \
241 dev->lock.file_priv != file_priv ) { \
242 DRM_ERROR( "%s called without lock held, held %d owner %p %p\n",\
243 __func__, _DRM_LOCK_IS_HELD( dev->lock.hw_lock->lock ),\
244 dev->lock.file_priv, file_priv ); \
245 return -EINVAL; \
246 } \
247} while (0)
248
249/**
250 * Copy and IOCTL return string to user space
251 */
252#define DRM_COPY( name, value ) \
253 len = strlen( value ); \
254 if ( len > name##_len ) len = name##_len; \
255 name##_len = strlen( value ); \
256 if ( len && name ) { \
257 if ( copy_to_user( name, value, len ) ) \
258 return -EFAULT; \
259 }
260
261/**
262 * Ioctl function type.
263 *
264 * \param inode device inode.
265 * \param file_priv DRM file private pointer.
266 * \param cmd command.
267 * \param arg argument.
268 */
269typedef int drm_ioctl_t(struct drm_device *dev, void *data,
270 struct drm_file *file_priv);
271
272typedef int drm_ioctl_compat_t(struct file *filp, unsigned int cmd,
273 unsigned long arg);
274
275#define DRM_AUTH 0x1
276#define DRM_MASTER 0x2
277#define DRM_ROOT_ONLY 0x4
278
279struct drm_ioctl_desc {
280 unsigned int cmd;
281 drm_ioctl_t *func;
282 int flags;
283};
284
285/**
286 * Creates a driver or general drm_ioctl_desc array entry for the given
287 * ioctl, for use by drm_ioctl().
288 */
289#define DRM_IOCTL_DEF(ioctl, func, flags) \
290 [DRM_IOCTL_NR(ioctl)] = {ioctl, func, flags}
291
292struct drm_magic_entry {
293 struct list_head head;
294 struct drm_hash_item hash_item;
295 struct drm_file *priv;
296};
297
298struct drm_vma_entry {
299 struct list_head head;
300 struct vm_area_struct *vma;
301 pid_t pid;
302};
303
304/**
305 * DMA buffer.
306 */
307struct drm_buf {
308 int idx; /**< Index into master buflist */
309 int total; /**< Buffer size */
310 int order; /**< log-base-2(total) */
311 int used; /**< Amount of buffer in use (for DMA) */
312 unsigned long offset; /**< Byte offset (used internally) */
313 void *address; /**< Address of buffer */
314 unsigned long bus_address; /**< Bus address of buffer */
315 struct drm_buf *next; /**< Kernel-only: used for free list */
316 __volatile__ int waiting; /**< On kernel DMA queue */
317 __volatile__ int pending; /**< On hardware DMA queue */
318 wait_queue_head_t dma_wait; /**< Processes waiting */
319 struct drm_file *file_priv; /**< Private of holding file descr */
320 int context; /**< Kernel queue for this buffer */
321 int while_locked; /**< Dispatch this buffer while locked */
322 enum {
323 DRM_LIST_NONE = 0,
324 DRM_LIST_FREE = 1,
325 DRM_LIST_WAIT = 2,
326 DRM_LIST_PEND = 3,
327 DRM_LIST_PRIO = 4,
328 DRM_LIST_RECLAIM = 5
329 } list; /**< Which list we're on */
330
331 int dev_priv_size; /**< Size of buffer private storage */
332 void *dev_private; /**< Per-buffer private storage */
333};
334
335/** bufs is one longer than it has to be */
336struct drm_waitlist {
337 int count; /**< Number of possible buffers */
338 struct drm_buf **bufs; /**< List of pointers to buffers */
339 struct drm_buf **rp; /**< Read pointer */
340 struct drm_buf **wp; /**< Write pointer */
341 struct drm_buf **end; /**< End pointer */
342 spinlock_t read_lock;
343 spinlock_t write_lock;
344};
345
346struct drm_freelist {
347 int initialized; /**< Freelist in use */
348 atomic_t count; /**< Number of free buffers */
349 struct drm_buf *next; /**< End pointer */
350
351 wait_queue_head_t waiting; /**< Processes waiting on free bufs */
352 int low_mark; /**< Low water mark */
353 int high_mark; /**< High water mark */
354 atomic_t wfh; /**< If waiting for high mark */
355 spinlock_t lock;
356};
357
358typedef struct drm_dma_handle {
359 dma_addr_t busaddr;
360 void *vaddr;
361 size_t size;
362} drm_dma_handle_t;
363
364/**
365 * Buffer entry. There is one of this for each buffer size order.
366 */
367struct drm_buf_entry {
368 int buf_size; /**< size */
369 int buf_count; /**< number of buffers */
370 struct drm_buf *buflist; /**< buffer list */
371 int seg_count;
372 int page_order;
373 struct drm_dma_handle **seglist;
374
375 struct drm_freelist freelist;
376};
377
378/** File private data */
379struct drm_file {
380 int authenticated;
381 int master;
382 pid_t pid;
383 uid_t uid;
384 drm_magic_t magic;
385 unsigned long ioctl_count;
386 struct list_head lhead;
387 struct drm_minor *minor;
388 int remove_auth_on_close;
389 unsigned long lock_count;
390 struct file *filp;
391 void *driver_priv;
392};
393
394/** Wait queue */
395struct drm_queue {
396 atomic_t use_count; /**< Outstanding uses (+1) */
397 atomic_t finalization; /**< Finalization in progress */
398 atomic_t block_count; /**< Count of processes waiting */
399 atomic_t block_read; /**< Queue blocked for reads */
400 wait_queue_head_t read_queue; /**< Processes waiting on block_read */
401 atomic_t block_write; /**< Queue blocked for writes */
402 wait_queue_head_t write_queue; /**< Processes waiting on block_write */
403 atomic_t total_queued; /**< Total queued statistic */
404 atomic_t total_flushed; /**< Total flushes statistic */
405 atomic_t total_locks; /**< Total locks statistics */
406 enum drm_ctx_flags flags; /**< Context preserving and 2D-only */
407 struct drm_waitlist waitlist; /**< Pending buffers */
408 wait_queue_head_t flush_queue; /**< Processes waiting until flush */
409};
410
411/**
412 * Lock data.
413 */
414struct drm_lock_data {
415 struct drm_hw_lock *hw_lock; /**< Hardware lock */
416 /** Private of lock holder's file (NULL=kernel) */
417 struct drm_file *file_priv;
418 wait_queue_head_t lock_queue; /**< Queue of blocked processes */
419 unsigned long lock_time; /**< Time of last lock in jiffies */
420 spinlock_t spinlock;
421 uint32_t kernel_waiters;
422 uint32_t user_waiters;
423 int idle_has_lock;
424};
425
426/**
427 * DMA data.
428 */
429struct drm_device_dma {
430
431 struct drm_buf_entry bufs[DRM_MAX_ORDER + 1]; /**< buffers, grouped by their size order */
432 int buf_count; /**< total number of buffers */
433 struct drm_buf **buflist; /**< Vector of pointers into drm_device_dma::bufs */
434 int seg_count;
435 int page_count; /**< number of pages */
436 unsigned long *pagelist; /**< page list */
437 unsigned long byte_count;
438 enum {
439 _DRM_DMA_USE_AGP = 0x01,
440 _DRM_DMA_USE_SG = 0x02,
441 _DRM_DMA_USE_FB = 0x04,
442 _DRM_DMA_USE_PCI_RO = 0x08
443 } flags;
444
445};
446
447/**
448 * AGP memory entry. Stored as a doubly linked list.
449 */
450struct drm_agp_mem {
451 unsigned long handle; /**< handle */
452 DRM_AGP_MEM *memory;
453 unsigned long bound; /**< address */
454 int pages;
455 struct list_head head;
456};
457
458/**
459 * AGP data.
460 *
461 * \sa drm_agp_init() and drm_device::agp.
462 */
463struct drm_agp_head {
464 DRM_AGP_KERN agp_info; /**< AGP device information */
465 struct list_head memory;
466 unsigned long mode; /**< AGP mode */
467 struct agp_bridge_data *bridge;
468 int enabled; /**< whether the AGP bus as been enabled */
469 int acquired; /**< whether the AGP device has been acquired */
470 unsigned long base;
471 int agp_mtrr;
472 int cant_use_aperture;
473 unsigned long page_mask;
474};
475
476/**
477 * Scatter-gather memory.
478 */
479struct drm_sg_mem {
480 unsigned long handle;
481 void *virtual;
482 int pages;
483 struct page **pagelist;
484 dma_addr_t *busaddr;
485};
486
487struct drm_sigdata {
488 int context;
489 struct drm_hw_lock *lock;
490};
491
492
493/*
494 * Generic memory manager structs
495 */
496
497struct drm_mm_node {
498 struct list_head fl_entry;
499 struct list_head ml_entry;
500 int free;
501 unsigned long start;
502 unsigned long size;
503 struct drm_mm *mm;
504 void *private;
505};
506
507struct drm_mm {
508 struct list_head fl_entry;
509 struct list_head ml_entry;
510};
511
512
513/**
514 * Mappings list
515 */
516struct drm_map_list {
517 struct list_head head; /**< list head */
518 struct drm_hash_item hash;
519 struct drm_map *map; /**< mapping */
520 uint64_t user_token;
521};
522
523typedef struct drm_map drm_local_map_t;
524
525/**
526 * Context handle list
527 */
528struct drm_ctx_list {
529 struct list_head head; /**< list head */
530 drm_context_t handle; /**< context handle */
531 struct drm_file *tag; /**< associated fd private data */
532};
533
534struct drm_vbl_sig {
535 struct list_head head;
536 unsigned int sequence;
537 struct siginfo info;
538 struct task_struct *task;
539};
540
541/* location of GART table */
542#define DRM_ATI_GART_MAIN 1
543#define DRM_ATI_GART_FB 2
544
545#define DRM_ATI_GART_PCI 1
546#define DRM_ATI_GART_PCIE 2
547#define DRM_ATI_GART_IGP 3
548
549struct drm_ati_pcigart_info {
550 int gart_table_location;
551 int gart_reg_if;
552 void *addr;
553 dma_addr_t bus_addr;
554 dma_addr_t table_mask;
555 struct drm_dma_handle *table_handle;
556 drm_local_map_t mapping;
557 int table_size;
558};
559
560/**
561 * DRM driver structure. This structure represent the common code for
562 * a family of cards. There will one drm_device for each card present
563 * in this family
564 */
565struct drm_driver {
566 int (*load) (struct drm_device *, unsigned long flags);
567 int (*firstopen) (struct drm_device *);
568 int (*open) (struct drm_device *, struct drm_file *);
569 void (*preclose) (struct drm_device *, struct drm_file *file_priv);
570 void (*postclose) (struct drm_device *, struct drm_file *);
571 void (*lastclose) (struct drm_device *);
572 int (*unload) (struct drm_device *);
573 int (*suspend) (struct drm_device *, pm_message_t state);
574 int (*resume) (struct drm_device *);
575 int (*dma_ioctl) (struct drm_device *dev, void *data, struct drm_file *file_priv);
576 void (*dma_ready) (struct drm_device *);
577 int (*dma_quiescent) (struct drm_device *);
578 int (*context_ctor) (struct drm_device *dev, int context);
579 int (*context_dtor) (struct drm_device *dev, int context);
580 int (*kernel_context_switch) (struct drm_device *dev, int old,
581 int new);
582 void (*kernel_context_switch_unlock) (struct drm_device *dev);
583 int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence);
584 int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence);
585 int (*dri_library_name) (struct drm_device *dev, char *buf);
586
587 /**
588 * Called by \c drm_device_is_agp. Typically used to determine if a
589 * card is really attached to AGP or not.
590 *
591 * \param dev DRM device handle
592 *
593 * \returns
594 * One of three values is returned depending on whether or not the
595 * card is absolutely \b not AGP (return of 0), absolutely \b is AGP
596 * (return of 1), or may or may not be AGP (return of 2).
597 */
598 int (*device_is_agp) (struct drm_device *dev);
599
600 /* these have to be filled in */
601
602 irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
603 void (*irq_preinstall) (struct drm_device *dev);
604 void (*irq_postinstall) (struct drm_device *dev);
605 void (*irq_uninstall) (struct drm_device *dev);
606 void (*reclaim_buffers) (struct drm_device *dev,
607 struct drm_file * file_priv);
608 void (*reclaim_buffers_locked) (struct drm_device *dev,
609 struct drm_file *file_priv);
610 void (*reclaim_buffers_idlelocked) (struct drm_device *dev,
611 struct drm_file *file_priv);
612 unsigned long (*get_map_ofs) (struct drm_map * map);
613 unsigned long (*get_reg_ofs) (struct drm_device *dev);
614 void (*set_version) (struct drm_device *dev,
615 struct drm_set_version *sv);
616
617 int major;
618 int minor;
619 int patchlevel;
620 char *name;
621 char *desc;
622 char *date;
623
624 u32 driver_features;
625 int dev_priv_size;
626 struct drm_ioctl_desc *ioctls;
627 int num_ioctls;
628 struct file_operations fops;
629 struct pci_driver pci_driver;
630};
631
632#define DRM_MINOR_UNASSIGNED 0
633#define DRM_MINOR_LEGACY 1
634
635/**
636 * DRM minor structure. This structure represents a drm minor number.
637 */
638struct drm_minor {
639 int index; /**< Minor device number */
640 int type; /**< Control or render */
641 dev_t device; /**< Device number for mknod */
642 struct device kdev; /**< Linux device */
643 struct drm_device *dev;
644 struct proc_dir_entry *dev_root; /**< proc directory entry */
645};
646
647/**
648 * DRM device structure. This structure represent a complete card that
649 * may contain multiple heads.
650 */
651struct drm_device {
652 char *unique; /**< Unique identifier: e.g., busid */
653 int unique_len; /**< Length of unique field */
654 char *devname; /**< For /proc/interrupts */
655 int if_version; /**< Highest interface version set */
656
657 int blocked; /**< Blocked due to VC switch? */
658
659 /** \name Locks */
660 /*@{ */
661 spinlock_t count_lock; /**< For inuse, drm_device::open_count, drm_device::buf_use */
662 struct mutex struct_mutex; /**< For others */
663 /*@} */
664
665 /** \name Usage Counters */
666 /*@{ */
667 int open_count; /**< Outstanding files open */
668 atomic_t ioctl_count; /**< Outstanding IOCTLs pending */
669 atomic_t vma_count; /**< Outstanding vma areas open */
670 int buf_use; /**< Buffers in use -- cannot alloc */
671 atomic_t buf_alloc; /**< Buffer allocation in progress */
672 /*@} */
673
674 /** \name Performance counters */
675 /*@{ */
676 unsigned long counters;
677 enum drm_stat_type types[15];
678 atomic_t counts[15];
679 /*@} */
680
681 /** \name Authentication */
682 /*@{ */
683 struct list_head filelist;
684 struct drm_open_hash magiclist; /**< magic hash table */
685 struct list_head magicfree;
686 /*@} */
687
688 /** \name Memory management */
689 /*@{ */
690 struct list_head maplist; /**< Linked list of regions */
691 int map_count; /**< Number of mappable regions */
692 struct drm_open_hash map_hash; /**< User token hash table for maps */
693
694 /** \name Context handle management */
695 /*@{ */
696 struct list_head ctxlist; /**< Linked list of context handles */
697 int ctx_count; /**< Number of context handles */
698 struct mutex ctxlist_mutex; /**< For ctxlist */
699
700 struct idr ctx_idr;
701
702 struct list_head vmalist; /**< List of vmas (for debugging) */
703 struct drm_lock_data lock; /**< Information on hardware lock */
704 /*@} */
705
706 /** \name DMA queues (contexts) */
707 /*@{ */
708 int queue_count; /**< Number of active DMA queues */
709 int queue_reserved; /**< Number of reserved DMA queues */
710 int queue_slots; /**< Actual length of queuelist */
711 struct drm_queue **queuelist; /**< Vector of pointers to DMA queues */
712 struct drm_device_dma *dma; /**< Optional pointer for DMA support */
713 /*@} */
714
715 /** \name Context support */
716 /*@{ */
717 int irq; /**< Interrupt used by board */
718 int irq_enabled; /**< True if irq handler is enabled */
719 __volatile__ long context_flag; /**< Context swapping flag */
720 __volatile__ long interrupt_flag; /**< Interruption handler flag */
721 __volatile__ long dma_flag; /**< DMA dispatch flag */
722 struct timer_list timer; /**< Timer for delaying ctx switch */
723 wait_queue_head_t context_wait; /**< Processes waiting on ctx switch */
724 int last_checked; /**< Last context checked for DMA */
725 int last_context; /**< Last current context */
726 unsigned long last_switch; /**< jiffies at last context switch */
727 /*@} */
728
729 struct work_struct work;
730 /** \name VBLANK IRQ support */
731 /*@{ */
732
733 wait_queue_head_t vbl_queue; /**< VBLANK wait queue */
734 atomic_t vbl_received;
735 atomic_t vbl_received2; /**< number of secondary VBLANK interrupts */
736 spinlock_t vbl_lock;
737 struct list_head vbl_sigs; /**< signal list to send on VBLANK */
738 struct list_head vbl_sigs2; /**< signals to send on secondary VBLANK */
739 unsigned int vbl_pending;
740 spinlock_t tasklet_lock; /**< For drm_locked_tasklet */
741 void (*locked_tasklet_func)(struct drm_device *dev);
742
743 /*@} */
744 cycles_t ctx_start;
745 cycles_t lck_start;
746
747 struct fasync_struct *buf_async;/**< Processes waiting for SIGIO */
748 wait_queue_head_t buf_readers; /**< Processes waiting to read */
749 wait_queue_head_t buf_writers; /**< Processes waiting to ctx switch */
750
751 struct drm_agp_head *agp; /**< AGP data */
752
753 struct pci_dev *pdev; /**< PCI device structure */
754 int pci_vendor; /**< PCI vendor id */
755 int pci_device; /**< PCI device id */
756#ifdef __alpha__
757 struct pci_controller *hose;
758#endif
759 struct drm_sg_mem *sg; /**< Scatter gather memory */
760 void *dev_private; /**< device private data */
761 struct drm_sigdata sigdata; /**< For block_all_signals */
762 sigset_t sigmask;
763
764 struct drm_driver *driver;
765 drm_local_map_t *agp_buffer_map;
766 unsigned int agp_buffer_token;
767 struct drm_minor *primary; /**< render type primary screen head */
768
769 /** \name Drawable information */
770 /*@{ */
771 spinlock_t drw_lock;
772 struct idr drw_idr;
773 /*@} */
774};
775
776static __inline__ int drm_core_check_feature(struct drm_device *dev,
777 int feature)
778{
779 return ((dev->driver->driver_features & feature) ? 1 : 0);
780}
781
782#ifdef __alpha__
783#define drm_get_pci_domain(dev) dev->hose->index
784#else
785#define drm_get_pci_domain(dev) 0
786#endif
787
788#if __OS_HAS_AGP
789static inline int drm_core_has_AGP(struct drm_device *dev)
790{
791 return drm_core_check_feature(dev, DRIVER_USE_AGP);
792}
793#else
794#define drm_core_has_AGP(dev) (0)
795#endif
796
797#if __OS_HAS_MTRR
798static inline int drm_core_has_MTRR(struct drm_device *dev)
799{
800 return drm_core_check_feature(dev, DRIVER_USE_MTRR);
801}
802
803#define DRM_MTRR_WC MTRR_TYPE_WRCOMB
804
805static inline int drm_mtrr_add(unsigned long offset, unsigned long size,
806 unsigned int flags)
807{
808 return mtrr_add(offset, size, flags, 1);
809}
810
811static inline int drm_mtrr_del(int handle, unsigned long offset,
812 unsigned long size, unsigned int flags)
813{
814 return mtrr_del(handle, offset, size);
815}
816
817#else
818#define drm_core_has_MTRR(dev) (0)
819
820#define DRM_MTRR_WC 0
821
822static inline int drm_mtrr_add(unsigned long offset, unsigned long size,
823 unsigned int flags)
824{
825 return 0;
826}
827
828static inline int drm_mtrr_del(int handle, unsigned long offset,
829 unsigned long size, unsigned int flags)
830{
831 return 0;
832}
833#endif
834
835/******************************************************************/
836/** \name Internal function definitions */
837/*@{*/
838
839 /* Driver support (drm_drv.h) */
840extern int drm_init(struct drm_driver *driver);
841extern void drm_exit(struct drm_driver *driver);
842extern int drm_ioctl(struct inode *inode, struct file *filp,
843 unsigned int cmd, unsigned long arg);
844extern long drm_compat_ioctl(struct file *filp,
845 unsigned int cmd, unsigned long arg);
846extern int drm_lastclose(struct drm_device *dev);
847
848 /* Device support (drm_fops.h) */
849extern int drm_open(struct inode *inode, struct file *filp);
850extern int drm_stub_open(struct inode *inode, struct file *filp);
851extern int drm_fasync(int fd, struct file *filp, int on);
852extern int drm_release(struct inode *inode, struct file *filp);
853
854 /* Mapping support (drm_vm.h) */
855extern int drm_mmap(struct file *filp, struct vm_area_struct *vma);
856extern unsigned long drm_core_get_map_ofs(struct drm_map * map);
857extern unsigned long drm_core_get_reg_ofs(struct drm_device *dev);
858extern unsigned int drm_poll(struct file *filp, struct poll_table_struct *wait);
859
860 /* Memory management support (drm_memory.h) */
861#include "drm_memory.h"
862extern void drm_mem_init(void);
863extern int drm_mem_info(char *buf, char **start, off_t offset,
864 int request, int *eof, void *data);
865extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
866
867extern DRM_AGP_MEM *drm_alloc_agp(struct drm_device *dev, int pages, u32 type);
868extern int drm_free_agp(DRM_AGP_MEM * handle, int pages);
869extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
870extern int drm_unbind_agp(DRM_AGP_MEM * handle);
871
872 /* Misc. IOCTL support (drm_ioctl.h) */
873extern int drm_irq_by_busid(struct drm_device *dev, void *data,
874 struct drm_file *file_priv);
875extern int drm_getunique(struct drm_device *dev, void *data,
876 struct drm_file *file_priv);
877extern int drm_setunique(struct drm_device *dev, void *data,
878 struct drm_file *file_priv);
879extern int drm_getmap(struct drm_device *dev, void *data,
880 struct drm_file *file_priv);
881extern int drm_getclient(struct drm_device *dev, void *data,
882 struct drm_file *file_priv);
883extern int drm_getstats(struct drm_device *dev, void *data,
884 struct drm_file *file_priv);
885extern int drm_setversion(struct drm_device *dev, void *data,
886 struct drm_file *file_priv);
887extern int drm_noop(struct drm_device *dev, void *data,
888 struct drm_file *file_priv);
889
890 /* Context IOCTL support (drm_context.h) */
891extern int drm_resctx(struct drm_device *dev, void *data,
892 struct drm_file *file_priv);
893extern int drm_addctx(struct drm_device *dev, void *data,
894 struct drm_file *file_priv);
895extern int drm_modctx(struct drm_device *dev, void *data,
896 struct drm_file *file_priv);
897extern int drm_getctx(struct drm_device *dev, void *data,
898 struct drm_file *file_priv);
899extern int drm_switchctx(struct drm_device *dev, void *data,
900 struct drm_file *file_priv);
901extern int drm_newctx(struct drm_device *dev, void *data,
902 struct drm_file *file_priv);
903extern int drm_rmctx(struct drm_device *dev, void *data,
904 struct drm_file *file_priv);
905
906extern int drm_ctxbitmap_init(struct drm_device *dev);
907extern void drm_ctxbitmap_cleanup(struct drm_device *dev);
908extern void drm_ctxbitmap_free(struct drm_device *dev, int ctx_handle);
909
910extern int drm_setsareactx(struct drm_device *dev, void *data,
911 struct drm_file *file_priv);
912extern int drm_getsareactx(struct drm_device *dev, void *data,
913 struct drm_file *file_priv);
914
915 /* Drawable IOCTL support (drm_drawable.h) */
916extern int drm_adddraw(struct drm_device *dev, void *data,
917 struct drm_file *file_priv);
918extern int drm_rmdraw(struct drm_device *dev, void *data,
919 struct drm_file *file_priv);
920extern int drm_update_drawable_info(struct drm_device *dev, void *data,
921 struct drm_file *file_priv);
922extern struct drm_drawable_info *drm_get_drawable_info(struct drm_device *dev,
923 drm_drawable_t id);
924extern void drm_drawable_free_all(struct drm_device *dev);
925
926 /* Authentication IOCTL support (drm_auth.h) */
927extern int drm_getmagic(struct drm_device *dev, void *data,
928 struct drm_file *file_priv);
929extern int drm_authmagic(struct drm_device *dev, void *data,
930 struct drm_file *file_priv);
931
932 /* Locking IOCTL support (drm_lock.h) */
933extern int drm_lock(struct drm_device *dev, void *data,
934 struct drm_file *file_priv);
935extern int drm_unlock(struct drm_device *dev, void *data,
936 struct drm_file *file_priv);
937extern int drm_lock_take(struct drm_lock_data *lock_data, unsigned int context);
938extern int drm_lock_free(struct drm_lock_data *lock_data, unsigned int context);
939extern void drm_idlelock_take(struct drm_lock_data *lock_data);
940extern void drm_idlelock_release(struct drm_lock_data *lock_data);
941
942/*
943 * These are exported to drivers so that they can implement fencing using
944 * DMA quiscent + idle. DMA quiescent usually requires the hardware lock.
945 */
946
947extern int drm_i_have_hw_lock(struct drm_device *dev, struct drm_file *file_priv);
948
949 /* Buffer management support (drm_bufs.h) */
950extern int drm_addbufs_agp(struct drm_device *dev, struct drm_buf_desc * request);
951extern int drm_addbufs_pci(struct drm_device *dev, struct drm_buf_desc * request);
952extern int drm_addmap(struct drm_device *dev, unsigned int offset,
953 unsigned int size, enum drm_map_type type,
954 enum drm_map_flags flags, drm_local_map_t ** map_ptr);
955extern int drm_addmap_ioctl(struct drm_device *dev, void *data,
956 struct drm_file *file_priv);
957extern int drm_rmmap(struct drm_device *dev, drm_local_map_t *map);
958extern int drm_rmmap_locked(struct drm_device *dev, drm_local_map_t *map);
959extern int drm_rmmap_ioctl(struct drm_device *dev, void *data,
960 struct drm_file *file_priv);
961extern int drm_addbufs(struct drm_device *dev, void *data,
962 struct drm_file *file_priv);
963extern int drm_infobufs(struct drm_device *dev, void *data,
964 struct drm_file *file_priv);
965extern int drm_markbufs(struct drm_device *dev, void *data,
966 struct drm_file *file_priv);
967extern int drm_freebufs(struct drm_device *dev, void *data,
968 struct drm_file *file_priv);
969extern int drm_mapbufs(struct drm_device *dev, void *data,
970 struct drm_file *file_priv);
971extern int drm_order(unsigned long size);
972extern unsigned long drm_get_resource_start(struct drm_device *dev,
973 unsigned int resource);
974extern unsigned long drm_get_resource_len(struct drm_device *dev,
975 unsigned int resource);
976
977 /* DMA support (drm_dma.h) */
978extern int drm_dma_setup(struct drm_device *dev);
979extern void drm_dma_takedown(struct drm_device *dev);
980extern void drm_free_buffer(struct drm_device *dev, struct drm_buf * buf);
981extern void drm_core_reclaim_buffers(struct drm_device *dev,
982 struct drm_file *filp);
983
984 /* IRQ support (drm_irq.h) */
985extern int drm_control(struct drm_device *dev, void *data,
986 struct drm_file *file_priv);
987extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
988extern int drm_irq_uninstall(struct drm_device *dev);
989extern void drm_driver_irq_preinstall(struct drm_device *dev);
990extern void drm_driver_irq_postinstall(struct drm_device *dev);
991extern void drm_driver_irq_uninstall(struct drm_device *dev);
992
993extern int drm_wait_vblank(struct drm_device *dev, void *data,
994 struct drm_file *file_priv);
995extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
996extern void drm_vbl_send_signals(struct drm_device *dev);
997extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
998
999 /* AGP/GART support (drm_agpsupport.h) */
1000extern struct drm_agp_head *drm_agp_init(struct drm_device *dev);
1001extern int drm_agp_acquire(struct drm_device *dev);
1002extern int drm_agp_acquire_ioctl(struct drm_device *dev, void *data,
1003 struct drm_file *file_priv);
1004extern int drm_agp_release(struct drm_device *dev);
1005extern int drm_agp_release_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv);
1007extern int drm_agp_enable(struct drm_device *dev, struct drm_agp_mode mode);
1008extern int drm_agp_enable_ioctl(struct drm_device *dev, void *data,
1009 struct drm_file *file_priv);
1010extern int drm_agp_info(struct drm_device *dev, struct drm_agp_info *info);
1011extern int drm_agp_info_ioctl(struct drm_device *dev, void *data,
1012 struct drm_file *file_priv);
1013extern int drm_agp_alloc(struct drm_device *dev, struct drm_agp_buffer *request);
1014extern int drm_agp_alloc_ioctl(struct drm_device *dev, void *data,
1015 struct drm_file *file_priv);
1016extern int drm_agp_free(struct drm_device *dev, struct drm_agp_buffer *request);
1017extern int drm_agp_free_ioctl(struct drm_device *dev, void *data,
1018 struct drm_file *file_priv);
1019extern int drm_agp_unbind(struct drm_device *dev, struct drm_agp_binding *request);
1020extern int drm_agp_unbind_ioctl(struct drm_device *dev, void *data,
1021 struct drm_file *file_priv);
1022extern int drm_agp_bind(struct drm_device *dev, struct drm_agp_binding *request);
1023extern int drm_agp_bind_ioctl(struct drm_device *dev, void *data,
1024 struct drm_file *file_priv);
1025extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size_t pages, u32 type);
1026extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
1027extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
1028extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
1029
1030 /* Stub support (drm_stub.h) */
1031extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
1032 struct drm_driver *driver);
1033extern int drm_put_dev(struct drm_device *dev);
1034extern int drm_put_minor(struct drm_minor **minor);
1035extern unsigned int drm_debug;
1036
1037extern struct class *drm_class;
1038extern struct proc_dir_entry *drm_proc_root;
1039
1040extern struct idr drm_minors_idr;
1041
1042extern drm_local_map_t *drm_getsarea(struct drm_device *dev);
1043
1044 /* Proc support (drm_proc.h) */
1045extern int drm_proc_init(struct drm_minor *minor, int minor_id,
1046 struct proc_dir_entry *root);
1047extern int drm_proc_cleanup(struct drm_minor *minor, struct proc_dir_entry *root);
1048
1049 /* Scatter Gather Support (drm_scatter.h) */
1050extern void drm_sg_cleanup(struct drm_sg_mem * entry);
1051extern int drm_sg_alloc_ioctl(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv);
1053extern int drm_sg_alloc(struct drm_device *dev, struct drm_scatter_gather * request);
1054extern int drm_sg_free(struct drm_device *dev, void *data,
1055 struct drm_file *file_priv);
1056
1057 /* ATI PCIGART support (ati_pcigart.h) */
1058extern int drm_ati_pcigart_init(struct drm_device *dev,
1059 struct drm_ati_pcigart_info * gart_info);
1060extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
1061 struct drm_ati_pcigart_info * gart_info);
1062
1063extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
1064 size_t align, dma_addr_t maxaddr);
1065extern void __drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
1066extern void drm_pci_free(struct drm_device *dev, drm_dma_handle_t * dmah);
1067
1068 /* sysfs support (drm_sysfs.c) */
1069struct drm_sysfs_class;
1070extern struct class *drm_sysfs_create(struct module *owner, char *name);
1071extern void drm_sysfs_destroy(void);
1072extern int drm_sysfs_device_add(struct drm_minor *minor);
1073extern void drm_sysfs_device_remove(struct drm_minor *minor);
1074
1075/*
1076 * Basic memory manager support (drm_mm.c)
1077 */
1078extern struct drm_mm_node *drm_mm_get_block(struct drm_mm_node * parent,
1079 unsigned long size,
1080 unsigned alignment);
1081extern void drm_mm_put_block(struct drm_mm_node * cur);
1082extern struct drm_mm_node *drm_mm_search_free(const struct drm_mm *mm, unsigned long size,
1083 unsigned alignment, int best_match);
1084extern int drm_mm_init(struct drm_mm *mm, unsigned long start, unsigned long size);
1085extern void drm_mm_takedown(struct drm_mm *mm);
1086extern int drm_mm_clean(struct drm_mm *mm);
1087extern unsigned long drm_mm_tail_space(struct drm_mm *mm);
1088extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size);
1089extern int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size);
1090
1091extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev);
1092extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev);
1093extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev);
1094
1095static __inline__ struct drm_map *drm_core_findmap(struct drm_device *dev,
1096 unsigned int token)
1097{
1098 struct drm_map_list *_entry;
1099 list_for_each_entry(_entry, &dev->maplist, head)
1100 if (_entry->user_token == token)
1101 return _entry->map;
1102 return NULL;
1103}
1104
1105static __inline__ int drm_device_is_agp(struct drm_device *dev)
1106{
1107 if (dev->driver->device_is_agp != NULL) {
1108 int err = (*dev->driver->device_is_agp) (dev);
1109
1110 if (err != 2) {
1111 return err;
1112 }
1113 }
1114
1115 return pci_find_capability(dev->pdev, PCI_CAP_ID_AGP);
1116}
1117
1118static __inline__ int drm_device_is_pcie(struct drm_device *dev)
1119{
1120 return pci_find_capability(dev->pdev, PCI_CAP_ID_EXP);
1121}
1122
1123static __inline__ void drm_core_dropmap(struct drm_map *map)
1124{
1125}
1126
1127#ifndef DEBUG_MEMORY
1128/** Wrapper around kmalloc() */
1129static __inline__ void *drm_alloc(size_t size, int area)
1130{
1131 return kmalloc(size, GFP_KERNEL);
1132}
1133
1134/** Wrapper around kfree() */
1135static __inline__ void drm_free(void *pt, size_t size, int area)
1136{
1137 kfree(pt);
1138}
1139
1140/** Wrapper around kcalloc() */
1141static __inline__ void *drm_calloc(size_t nmemb, size_t size, int area)
1142{
1143 return kcalloc(nmemb, size, GFP_KERNEL);
1144}
1145#else
1146extern void *drm_alloc(size_t size, int area);
1147extern void drm_free(void *pt, size_t size, int area);
1148extern void *drm_calloc(size_t nmemb, size_t size, int area);
1149#endif
1150
1151/*@}*/
1152
1153#endif /* __KERNEL__ */
1154#endif
diff --git a/include/drm/drm_core.h b/include/drm/drm_core.h
new file mode 100644
index 000000000000..316739036079
--- /dev/null
+++ b/include/drm/drm_core.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2004 Jon Smirl <jonsmirl@gmail.com>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
13 * of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 */
23#define CORE_AUTHOR "Gareth Hughes, Leif Delgass, José Fonseca, Jon Smirl"
24
25#define CORE_NAME "drm"
26#define CORE_DESC "DRM shared core routines"
27#define CORE_DATE "20060810"
28
29#define DRM_IF_MAJOR 1
30#define DRM_IF_MINOR 3
31
32#define CORE_MAJOR 1
33#define CORE_MINOR 1
34#define CORE_PATCHLEVEL 0
diff --git a/include/drm/drm_hashtab.h b/include/drm/drm_hashtab.h
new file mode 100644
index 000000000000..cd2b189e1be6
--- /dev/null
+++ b/include/drm/drm_hashtab.h
@@ -0,0 +1,67 @@
1/**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Bismack, ND. USA.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 *
27 **************************************************************************/
28/*
29 * Simple open hash tab implementation.
30 *
31 * Authors:
32 * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
33 */
34
35#ifndef DRM_HASHTAB_H
36#define DRM_HASHTAB_H
37
38#define drm_hash_entry(_ptr, _type, _member) container_of(_ptr, _type, _member)
39
40struct drm_hash_item {
41 struct hlist_node head;
42 unsigned long key;
43};
44
45struct drm_open_hash {
46 unsigned int size;
47 unsigned int order;
48 unsigned int fill;
49 struct hlist_head *table;
50 int use_vmalloc;
51};
52
53
54extern int drm_ht_create(struct drm_open_hash *ht, unsigned int order);
55extern int drm_ht_insert_item(struct drm_open_hash *ht, struct drm_hash_item *item);
56extern int drm_ht_just_insert_please(struct drm_open_hash *ht, struct drm_hash_item *item,
57 unsigned long seed, int bits, int shift,
58 unsigned long add);
59extern int drm_ht_find_item(struct drm_open_hash *ht, unsigned long key, struct drm_hash_item **item);
60
61extern void drm_ht_verbose_list(struct drm_open_hash *ht, unsigned long key);
62extern int drm_ht_remove_key(struct drm_open_hash *ht, unsigned long key);
63extern int drm_ht_remove_item(struct drm_open_hash *ht, struct drm_hash_item *item);
64extern void drm_ht_remove(struct drm_open_hash *ht);
65
66
67#endif
diff --git a/include/drm/drm_memory.h b/include/drm/drm_memory.h
new file mode 100644
index 000000000000..63e425b5ea82
--- /dev/null
+++ b/include/drm/drm_memory.h
@@ -0,0 +1,61 @@
1/**
2 * \file drm_memory.h
3 * Memory management wrappers for DRM
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com>
7 */
8
9/*
10 * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com
11 *
12 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
13 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
14 * All Rights Reserved.
15 *
16 * Permission is hereby granted, free of charge, to any person obtaining a
17 * copy of this software and associated documentation files (the "Software"),
18 * to deal in the Software without restriction, including without limitation
19 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
20 * and/or sell copies of the Software, and to permit persons to whom the
21 * Software is furnished to do so, subject to the following conditions:
22 *
23 * The above copyright notice and this permission notice (including the next
24 * paragraph) shall be included in all copies or substantial portions of the
25 * Software.
26 *
27 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
28 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
29 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
30 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
31 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
32 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
33 * OTHER DEALINGS IN THE SOFTWARE.
34 */
35
36#include <linux/highmem.h>
37#include <linux/vmalloc.h>
38#include "drmP.h"
39
40/**
41 * Cut down version of drm_memory_debug.h, which used to be called
42 * drm_memory.h.
43 */
44
45#if __OS_HAS_AGP
46
47#include <linux/vmalloc.h>
48
49#ifdef HAVE_PAGE_AGP
50#include <asm/agp.h>
51#else
52# ifdef __powerpc__
53# define PAGE_AGP __pgprot(_PAGE_KERNEL | _PAGE_NO_CACHE)
54# else
55# define PAGE_AGP PAGE_KERNEL
56# endif
57#endif
58
59#else /* __OS_HAS_AGP */
60
61#endif
diff --git a/include/drm/drm_memory_debug.h b/include/drm/drm_memory_debug.h
new file mode 100644
index 000000000000..6463271deea8
--- /dev/null
+++ b/include/drm/drm_memory_debug.h
@@ -0,0 +1,309 @@
1/**
2 * \file drm_memory_debug.h
3 * Memory management wrappers for DRM.
4 *
5 * \author Rickard E. (Rik) Faith <faith@valinux.com>
6 * \author Gareth Hughes <gareth@valinux.com>
7 */
8
9/*
10 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
11 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
12 * All Rights Reserved.
13 *
14 * Permission is hereby granted, free of charge, to any person obtaining a
15 * copy of this software and associated documentation files (the "Software"),
16 * to deal in the Software without restriction, including without limitation
17 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
18 * and/or sell copies of the Software, and to permit persons to whom the
19 * Software is furnished to do so, subject to the following conditions:
20 *
21 * The above copyright notice and this permission notice (including the next
22 * paragraph) shall be included in all copies or substantial portions of the
23 * Software.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
26 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
27 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
28 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
29 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
30 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
31 * OTHER DEALINGS IN THE SOFTWARE.
32 */
33
34#include "drmP.h"
35
36typedef struct drm_mem_stats {
37 const char *name;
38 int succeed_count;
39 int free_count;
40 int fail_count;
41 unsigned long bytes_allocated;
42 unsigned long bytes_freed;
43} drm_mem_stats_t;
44
45static DEFINE_SPINLOCK(drm_mem_lock);
46static unsigned long drm_ram_available = 0; /* In pages */
47static unsigned long drm_ram_used = 0;
48static drm_mem_stats_t drm_mem_stats[] =
49{
50 [DRM_MEM_DMA] = {"dmabufs"},
51 [DRM_MEM_SAREA] = {"sareas"},
52 [DRM_MEM_DRIVER] = {"driver"},
53 [DRM_MEM_MAGIC] = {"magic"},
54 [DRM_MEM_IOCTLS] = {"ioctltab"},
55 [DRM_MEM_MAPS] = {"maplist"},
56 [DRM_MEM_VMAS] = {"vmalist"},
57 [DRM_MEM_BUFS] = {"buflist"},
58 [DRM_MEM_SEGS] = {"seglist"},
59 [DRM_MEM_PAGES] = {"pagelist"},
60 [DRM_MEM_FILES] = {"files"},
61 [DRM_MEM_QUEUES] = {"queues"},
62 [DRM_MEM_CMDS] = {"commands"},
63 [DRM_MEM_MAPPINGS] = {"mappings"},
64 [DRM_MEM_BUFLISTS] = {"buflists"},
65 [DRM_MEM_AGPLISTS] = {"agplist"},
66 [DRM_MEM_SGLISTS] = {"sglist"},
67 [DRM_MEM_TOTALAGP] = {"totalagp"},
68 [DRM_MEM_BOUNDAGP] = {"boundagp"},
69 [DRM_MEM_CTXBITMAP] = {"ctxbitmap"},
70 [DRM_MEM_CTXLIST] = {"ctxlist"},
71 [DRM_MEM_STUB] = {"stub"},
72 {NULL, 0,} /* Last entry must be null */
73};
74
75void drm_mem_init (void) {
76 drm_mem_stats_t *mem;
77 struct sysinfo si;
78
79 for (mem = drm_mem_stats; mem->name; ++mem) {
80 mem->succeed_count = 0;
81 mem->free_count = 0;
82 mem->fail_count = 0;
83 mem->bytes_allocated = 0;
84 mem->bytes_freed = 0;
85 }
86
87 si_meminfo(&si);
88 drm_ram_available = si.totalram;
89 drm_ram_used = 0;
90}
91
92/* drm_mem_info is called whenever a process reads /dev/drm/mem. */
93
94static int drm__mem_info (char *buf, char **start, off_t offset,
95 int request, int *eof, void *data) {
96 drm_mem_stats_t *pt;
97 int len = 0;
98
99 if (offset > DRM_PROC_LIMIT) {
100 *eof = 1;
101 return 0;
102 }
103
104 *eof = 0;
105 *start = &buf[offset];
106
107 DRM_PROC_PRINT(" total counts "
108 " | outstanding \n");
109 DRM_PROC_PRINT("type alloc freed fail bytes freed"
110 " | allocs bytes\n\n");
111 DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n",
112 "system", 0, 0, 0,
113 drm_ram_available << (PAGE_SHIFT - 10));
114 DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu kB |\n",
115 "locked", 0, 0, 0, drm_ram_used >> 10);
116 DRM_PROC_PRINT("\n");
117 for (pt = drm_mem_stats; pt->name; pt++) {
118 DRM_PROC_PRINT("%-9.9s %5d %5d %4d %10lu %10lu | %6d %10ld\n",
119 pt->name,
120 pt->succeed_count,
121 pt->free_count,
122 pt->fail_count,
123 pt->bytes_allocated,
124 pt->bytes_freed,
125 pt->succeed_count - pt->free_count,
126 (long)pt->bytes_allocated
127 - (long)pt->bytes_freed);
128 }
129
130 if (len > request + offset)
131 return request;
132 *eof = 1;
133 return len - offset;
134}
135
136int drm_mem_info (char *buf, char **start, off_t offset,
137 int len, int *eof, void *data) {
138 int ret;
139
140 spin_lock(&drm_mem_lock);
141 ret = drm__mem_info (buf, start, offset, len, eof, data);
142 spin_unlock(&drm_mem_lock);
143 return ret;
144}
145
146void *drm_alloc (size_t size, int area) {
147 void *pt;
148
149 if (!size) {
150 DRM_MEM_ERROR(area, "Allocating 0 bytes\n");
151 return NULL;
152 }
153
154 if (!(pt = kmalloc(size, GFP_KERNEL))) {
155 spin_lock(&drm_mem_lock);
156 ++drm_mem_stats[area].fail_count;
157 spin_unlock(&drm_mem_lock);
158 return NULL;
159 }
160 spin_lock(&drm_mem_lock);
161 ++drm_mem_stats[area].succeed_count;
162 drm_mem_stats[area].bytes_allocated += size;
163 spin_unlock(&drm_mem_lock);
164 return pt;
165}
166
167void *drm_calloc (size_t nmemb, size_t size, int area) {
168 void *addr;
169
170 addr = drm_alloc (nmemb * size, area);
171 if (addr != NULL)
172 memset((void *)addr, 0, size * nmemb);
173
174 return addr;
175}
176
177void *drm_realloc (void *oldpt, size_t oldsize, size_t size, int area) {
178 void *pt;
179
180 if (!(pt = drm_alloc (size, area)))
181 return NULL;
182 if (oldpt && oldsize) {
183 memcpy(pt, oldpt, oldsize);
184 drm_free (oldpt, oldsize, area);
185 }
186 return pt;
187}
188
189void drm_free (void *pt, size_t size, int area) {
190 int alloc_count;
191 int free_count;
192
193 if (!pt)
194 DRM_MEM_ERROR(area, "Attempt to free NULL pointer\n");
195 else
196 kfree(pt);
197 spin_lock(&drm_mem_lock);
198 drm_mem_stats[area].bytes_freed += size;
199 free_count = ++drm_mem_stats[area].free_count;
200 alloc_count = drm_mem_stats[area].succeed_count;
201 spin_unlock(&drm_mem_lock);
202 if (free_count > alloc_count) {
203 DRM_MEM_ERROR(area, "Excess frees: %d frees, %d allocs\n",
204 free_count, alloc_count);
205 }
206}
207
208#if __OS_HAS_AGP
209
210DRM_AGP_MEM *drm_alloc_agp (drm_device_t *dev, int pages, u32 type) {
211 DRM_AGP_MEM *handle;
212
213 if (!pages) {
214 DRM_MEM_ERROR(DRM_MEM_TOTALAGP, "Allocating 0 pages\n");
215 return NULL;
216 }
217
218 if ((handle = drm_agp_allocate_memory (pages, type))) {
219 spin_lock(&drm_mem_lock);
220 ++drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count;
221 drm_mem_stats[DRM_MEM_TOTALAGP].bytes_allocated
222 += pages << PAGE_SHIFT;
223 spin_unlock(&drm_mem_lock);
224 return handle;
225 }
226 spin_lock(&drm_mem_lock);
227 ++drm_mem_stats[DRM_MEM_TOTALAGP].fail_count;
228 spin_unlock(&drm_mem_lock);
229 return NULL;
230}
231
232int drm_free_agp (DRM_AGP_MEM * handle, int pages) {
233 int alloc_count;
234 int free_count;
235 int retval = -EINVAL;
236
237 if (!handle) {
238 DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
239 "Attempt to free NULL AGP handle\n");
240 return retval;
241 }
242
243 if (drm_agp_free_memory (handle)) {
244 spin_lock(&drm_mem_lock);
245 free_count = ++drm_mem_stats[DRM_MEM_TOTALAGP].free_count;
246 alloc_count = drm_mem_stats[DRM_MEM_TOTALAGP].succeed_count;
247 drm_mem_stats[DRM_MEM_TOTALAGP].bytes_freed
248 += pages << PAGE_SHIFT;
249 spin_unlock(&drm_mem_lock);
250 if (free_count > alloc_count) {
251 DRM_MEM_ERROR(DRM_MEM_TOTALAGP,
252 "Excess frees: %d frees, %d allocs\n",
253 free_count, alloc_count);
254 }
255 return 0;
256 }
257 return retval;
258}
259
260int drm_bind_agp (DRM_AGP_MEM * handle, unsigned int start) {
261 int retcode = -EINVAL;
262
263 if (!handle) {
264 DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
265 "Attempt to bind NULL AGP handle\n");
266 return retcode;
267 }
268
269 if (!(retcode = drm_agp_bind_memory (handle, start))) {
270 spin_lock(&drm_mem_lock);
271 ++drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count;
272 drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_allocated
273 += handle->page_count << PAGE_SHIFT;
274 spin_unlock(&drm_mem_lock);
275 return retcode;
276 }
277 spin_lock(&drm_mem_lock);
278 ++drm_mem_stats[DRM_MEM_BOUNDAGP].fail_count;
279 spin_unlock(&drm_mem_lock);
280 return retcode;
281}
282
283int drm_unbind_agp (DRM_AGP_MEM * handle) {
284 int alloc_count;
285 int free_count;
286 int retcode = -EINVAL;
287
288 if (!handle) {
289 DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
290 "Attempt to unbind NULL AGP handle\n");
291 return retcode;
292 }
293
294 if ((retcode = drm_agp_unbind_memory (handle)))
295 return retcode;
296 spin_lock(&drm_mem_lock);
297 free_count = ++drm_mem_stats[DRM_MEM_BOUNDAGP].free_count;
298 alloc_count = drm_mem_stats[DRM_MEM_BOUNDAGP].succeed_count;
299 drm_mem_stats[DRM_MEM_BOUNDAGP].bytes_freed
300 += handle->page_count << PAGE_SHIFT;
301 spin_unlock(&drm_mem_lock);
302 if (free_count > alloc_count) {
303 DRM_MEM_ERROR(DRM_MEM_BOUNDAGP,
304 "Excess frees: %d frees, %d allocs\n",
305 free_count, alloc_count);
306 }
307 return retcode;
308}
309#endif
diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h
new file mode 100644
index 000000000000..8dbd2572b7c3
--- /dev/null
+++ b/include/drm/drm_os_linux.h
@@ -0,0 +1,108 @@
1/**
2 * \file drm_os_linux.h
3 * OS abstraction macros.
4 */
5
6#include <linux/interrupt.h> /* For task queue support */
7#include <linux/delay.h>
8
9/** Current process ID */
10#define DRM_CURRENTPID task_pid_nr(current)
11#define DRM_SUSER(p) capable(CAP_SYS_ADMIN)
12#define DRM_UDELAY(d) udelay(d)
13/** Read a byte from a MMIO region */
14#define DRM_READ8(map, offset) readb(((void __iomem *)(map)->handle) + (offset))
15/** Read a word from a MMIO region */
16#define DRM_READ16(map, offset) readw(((void __iomem *)(map)->handle) + (offset))
17/** Read a dword from a MMIO region */
18#define DRM_READ32(map, offset) readl(((void __iomem *)(map)->handle) + (offset))
19/** Write a byte into a MMIO region */
20#define DRM_WRITE8(map, offset, val) writeb(val, ((void __iomem *)(map)->handle) + (offset))
21/** Write a word into a MMIO region */
22#define DRM_WRITE16(map, offset, val) writew(val, ((void __iomem *)(map)->handle) + (offset))
23/** Write a dword into a MMIO region */
24#define DRM_WRITE32(map, offset, val) writel(val, ((void __iomem *)(map)->handle) + (offset))
25/** Read memory barrier */
26#define DRM_READMEMORYBARRIER() rmb()
27/** Write memory barrier */
28#define DRM_WRITEMEMORYBARRIER() wmb()
29/** Read/write memory barrier */
30#define DRM_MEMORYBARRIER() mb()
31
32/** IRQ handler arguments and return type and values */
33#define DRM_IRQ_ARGS int irq, void *arg
34
35/** AGP types */
36#if __OS_HAS_AGP
37#define DRM_AGP_MEM struct agp_memory
38#define DRM_AGP_KERN struct agp_kern_info
39#else
40/* define some dummy types for non AGP supporting kernels */
41struct no_agp_kern {
42 unsigned long aper_base;
43 unsigned long aper_size;
44};
45#define DRM_AGP_MEM int
46#define DRM_AGP_KERN struct no_agp_kern
47#endif
48
49#if !(__OS_HAS_MTRR)
50static __inline__ int mtrr_add(unsigned long base, unsigned long size,
51 unsigned int type, char increment)
52{
53 return -ENODEV;
54}
55
56static __inline__ int mtrr_del(int reg, unsigned long base, unsigned long size)
57{
58 return -ENODEV;
59}
60
61#define MTRR_TYPE_WRCOMB 1
62
63#endif
64
65/** Other copying of data to kernel space */
66#define DRM_COPY_FROM_USER(arg1, arg2, arg3) \
67 copy_from_user(arg1, arg2, arg3)
68/** Other copying of data from kernel space */
69#define DRM_COPY_TO_USER(arg1, arg2, arg3) \
70 copy_to_user(arg1, arg2, arg3)
71/* Macros for copyfrom user, but checking readability only once */
72#define DRM_VERIFYAREA_READ( uaddr, size ) \
73 (access_ok( VERIFY_READ, uaddr, size ) ? 0 : -EFAULT)
74#define DRM_COPY_FROM_USER_UNCHECKED(arg1, arg2, arg3) \
75 __copy_from_user(arg1, arg2, arg3)
76#define DRM_COPY_TO_USER_UNCHECKED(arg1, arg2, arg3) \
77 __copy_to_user(arg1, arg2, arg3)
78#define DRM_GET_USER_UNCHECKED(val, uaddr) \
79 __get_user(val, uaddr)
80
81#define DRM_HZ HZ
82
83#define DRM_WAIT_ON( ret, queue, timeout, condition ) \
84do { \
85 DECLARE_WAITQUEUE(entry, current); \
86 unsigned long end = jiffies + (timeout); \
87 add_wait_queue(&(queue), &entry); \
88 \
89 for (;;) { \
90 __set_current_state(TASK_INTERRUPTIBLE); \
91 if (condition) \
92 break; \
93 if (time_after_eq(jiffies, end)) { \
94 ret = -EBUSY; \
95 break; \
96 } \
97 schedule_timeout((HZ/100 > 1) ? HZ/100 : 1); \
98 if (signal_pending(current)) { \
99 ret = -EINTR; \
100 break; \
101 } \
102 } \
103 __set_current_state(TASK_RUNNING); \
104 remove_wait_queue(&(queue), &entry); \
105} while (0)
106
107#define DRM_WAKEUP( queue ) wake_up_interruptible( queue )
108#define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
new file mode 100644
index 000000000000..135bd19499fc
--- /dev/null
+++ b/include/drm/drm_pciids.h
@@ -0,0 +1,415 @@
1/*
2 This file is auto-generated from the drm_pciids.txt in the DRM CVS
3 Please contact dri-devel@lists.sf.net to add new cards to this list
4*/
5#define radeon_PCI_IDS \
6 {0x1002, 0x3150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
7 {0x1002, 0x3152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
8 {0x1002, 0x3154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
9 {0x1002, 0x3E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
10 {0x1002, 0x3E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
11 {0x1002, 0x4136, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP}, \
12 {0x1002, 0x4137, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
13 {0x1002, 0x4144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
14 {0x1002, 0x4145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
15 {0x1002, 0x4146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
16 {0x1002, 0x4147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
17 {0x1002, 0x4148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
18 {0x1002, 0x4149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
19 {0x1002, 0x414A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
20 {0x1002, 0x414B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
21 {0x1002, 0x4150, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
22 {0x1002, 0x4151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
23 {0x1002, 0x4152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
24 {0x1002, 0x4153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
25 {0x1002, 0x4154, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
26 {0x1002, 0x4155, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
27 {0x1002, 0x4156, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350}, \
28 {0x1002, 0x4237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP}, \
29 {0x1002, 0x4242, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
30 {0x1002, 0x4243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
31 {0x1002, 0x4336, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS100|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
32 {0x1002, 0x4337, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
33 {0x1002, 0x4437, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS200|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
34 {0x1002, 0x4966, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
35 {0x1002, 0x4967, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250}, \
36 {0x1002, 0x4A48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
37 {0x1002, 0x4A49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
38 {0x1002, 0x4A4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
39 {0x1002, 0x4A4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
40 {0x1002, 0x4A4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
41 {0x1002, 0x4A4D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
42 {0x1002, 0x4A4E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
43 {0x1002, 0x4A4F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
44 {0x1002, 0x4A50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
45 {0x1002, 0x4A54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
46 {0x1002, 0x4B49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
47 {0x1002, 0x4B4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
48 {0x1002, 0x4B4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
49 {0x1002, 0x4B4C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
50 {0x1002, 0x4C57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \
51 {0x1002, 0x4C58, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200|RADEON_IS_MOBILITY}, \
52 {0x1002, 0x4C59, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \
53 {0x1002, 0x4C5A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100|RADEON_IS_MOBILITY}, \
54 {0x1002, 0x4C64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
55 {0x1002, 0x4C66, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
56 {0x1002, 0x4C67, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV250|RADEON_IS_MOBILITY}, \
57 {0x1002, 0x4E44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
58 {0x1002, 0x4E45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
59 {0x1002, 0x4E46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
60 {0x1002, 0x4E47, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R300}, \
61 {0x1002, 0x4E48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
62 {0x1002, 0x4E49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
63 {0x1002, 0x4E4A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
64 {0x1002, 0x4E4B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R350}, \
65 {0x1002, 0x4E50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
66 {0x1002, 0x4E51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
67 {0x1002, 0x4E52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
68 {0x1002, 0x4E53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
69 {0x1002, 0x4E54, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
70 {0x1002, 0x4E56, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV350|RADEON_IS_MOBILITY}, \
71 {0x1002, 0x5144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
72 {0x1002, 0x5145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
73 {0x1002, 0x5146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
74 {0x1002, 0x5147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R100|RADEON_SINGLE_CRTC}, \
75 {0x1002, 0x5148, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
76 {0x1002, 0x514C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
77 {0x1002, 0x514D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R200}, \
78 {0x1002, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
79 {0x1002, 0x5158, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV200}, \
80 {0x1002, 0x5159, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
81 {0x1002, 0x515A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
82 {0x1002, 0x515E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
83 {0x1002, 0x5460, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
84 {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
85 {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
86 {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
87 {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
88 {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
89 {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
90 {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
91 {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
92 {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
93 {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
94 {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
95 {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
96 {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
97 {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
98 {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
99 {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
100 {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
101 {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
102 {0x1002, 0x5652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
103 {0x1002, 0x5653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
104 {0x1002, 0x5834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP}, \
105 {0x1002, 0x5835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY}, \
106 {0x1002, 0x5954, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
107 {0x1002, 0x5955, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
108 {0x1002, 0x5974, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
109 {0x1002, 0x5975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
110 {0x1002, 0x5960, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
111 {0x1002, 0x5961, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
112 {0x1002, 0x5962, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
113 {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
114 {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
115 {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
116 {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
117 {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
118 {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
119 {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
120 {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
121 {0x1002, 0x5b64, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
122 {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
123 {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
124 {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
125 {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
126 {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
127 {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
128 {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
129 {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
130 {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
131 {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
132 {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
133 {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
134 {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
135 {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
136 {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
137 {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
138 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
139 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
140 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
141 {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
142 {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
143 {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x7103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x7104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x7105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
147 {0x1002, 0x7106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
148 {0x1002, 0x7108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
149 {0x1002, 0x7109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
150 {0x1002, 0x710A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
151 {0x1002, 0x710B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
152 {0x1002, 0x710C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
153 {0x1002, 0x710E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
154 {0x1002, 0x710F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
155 {0x1002, 0x7140, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x7141, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x7142, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
158 {0x1002, 0x7143, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
159 {0x1002, 0x7144, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
160 {0x1002, 0x7145, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
161 {0x1002, 0x7146, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
162 {0x1002, 0x7147, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
163 {0x1002, 0x7149, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
164 {0x1002, 0x714A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
165 {0x1002, 0x714B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
166 {0x1002, 0x714C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
167 {0x1002, 0x714D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
168 {0x1002, 0x714E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
169 {0x1002, 0x714F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
170 {0x1002, 0x7151, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
171 {0x1002, 0x7152, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
172 {0x1002, 0x7153, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
173 {0x1002, 0x715E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
174 {0x1002, 0x715F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
175 {0x1002, 0x7180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
176 {0x1002, 0x7181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
177 {0x1002, 0x7183, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
178 {0x1002, 0x7186, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
179 {0x1002, 0x7187, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
180 {0x1002, 0x7188, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
181 {0x1002, 0x718A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
182 {0x1002, 0x718B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
183 {0x1002, 0x718C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
184 {0x1002, 0x718D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
185 {0x1002, 0x718F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
186 {0x1002, 0x7193, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
187 {0x1002, 0x7196, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
188 {0x1002, 0x719B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
189 {0x1002, 0x719F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
190 {0x1002, 0x71C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
191 {0x1002, 0x71C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
192 {0x1002, 0x71C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
193 {0x1002, 0x71C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
194 {0x1002, 0x71C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
195 {0x1002, 0x71C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
196 {0x1002, 0x71C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
197 {0x1002, 0x71C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
198 {0x1002, 0x71CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
199 {0x1002, 0x71CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
200 {0x1002, 0x71D2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
201 {0x1002, 0x71D4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
202 {0x1002, 0x71D5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
203 {0x1002, 0x71D6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
204 {0x1002, 0x71DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_NEW_MEMMAP}, \
205 {0x1002, 0x71DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV530|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
206 {0x1002, 0x7200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_NEW_MEMMAP}, \
207 {0x1002, 0x7210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
208 {0x1002, 0x7211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV515|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
209 {0x1002, 0x7240, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
210 {0x1002, 0x7243, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
211 {0x1002, 0x7244, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
212 {0x1002, 0x7245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
213 {0x1002, 0x7246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
214 {0x1002, 0x7247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
215 {0x1002, 0x7248, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
216 {0x1002, 0x7249, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
217 {0x1002, 0x724A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
218 {0x1002, 0x724B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
219 {0x1002, 0x724C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
220 {0x1002, 0x724D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
221 {0x1002, 0x724E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
222 {0x1002, 0x724F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_NEW_MEMMAP}, \
223 {0x1002, 0x7280, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
224 {0x1002, 0x7281, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
225 {0x1002, 0x7283, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
226 {0x1002, 0x7284, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R580|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
227 {0x1002, 0x7287, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
228 {0x1002, 0x7288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
229 {0x1002, 0x7289, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
230 {0x1002, 0x728B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
231 {0x1002, 0x728C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV570|RADEON_NEW_MEMMAP}, \
232 {0x1002, 0x7290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
233 {0x1002, 0x7291, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
234 {0x1002, 0x7293, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
235 {0x1002, 0x7297, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV560|RADEON_NEW_MEMMAP}, \
236 {0x1002, 0x7834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
237 {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
238 {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
239 {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
240 {0, 0, 0}
241
242#define r128_PCI_IDS \
243 {0x1002, 0x4c45, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
244 {0x1002, 0x4c46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
245 {0x1002, 0x4d46, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
246 {0x1002, 0x4d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
247 {0x1002, 0x5041, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
248 {0x1002, 0x5042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
249 {0x1002, 0x5043, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
250 {0x1002, 0x5044, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
251 {0x1002, 0x5045, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
252 {0x1002, 0x5046, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
253 {0x1002, 0x5047, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
254 {0x1002, 0x5048, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
255 {0x1002, 0x5049, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
256 {0x1002, 0x504A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
257 {0x1002, 0x504B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
258 {0x1002, 0x504C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
259 {0x1002, 0x504D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
260 {0x1002, 0x504E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
261 {0x1002, 0x504F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
262 {0x1002, 0x5050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
263 {0x1002, 0x5051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
264 {0x1002, 0x5052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
265 {0x1002, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
266 {0x1002, 0x5054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
267 {0x1002, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
268 {0x1002, 0x5056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
269 {0x1002, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
270 {0x1002, 0x5058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
271 {0x1002, 0x5245, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
272 {0x1002, 0x5246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
273 {0x1002, 0x5247, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
274 {0x1002, 0x524b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
275 {0x1002, 0x524c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
276 {0x1002, 0x534d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
277 {0x1002, 0x5446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
278 {0x1002, 0x544C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
279 {0x1002, 0x5452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
280 {0, 0, 0}
281
282#define mga_PCI_IDS \
283 {0x102b, 0x0520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G200}, \
284 {0x102b, 0x0521, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G200}, \
285 {0x102b, 0x0525, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G400}, \
286 {0x102b, 0x2527, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MGA_CARD_TYPE_G550}, \
287 {0, 0, 0}
288
289#define mach64_PCI_IDS \
290 {0x1002, 0x4749, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
291 {0x1002, 0x4750, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
292 {0x1002, 0x4751, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
293 {0x1002, 0x4742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
294 {0x1002, 0x4744, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
295 {0x1002, 0x4c49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
296 {0x1002, 0x4c50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
297 {0x1002, 0x4c51, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
298 {0x1002, 0x4c42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
299 {0x1002, 0x4c44, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
300 {0x1002, 0x474c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
301 {0x1002, 0x474f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
302 {0x1002, 0x4752, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
303 {0x1002, 0x4753, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
304 {0x1002, 0x474d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
305 {0x1002, 0x474e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
306 {0x1002, 0x4c52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
307 {0x1002, 0x4c53, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
308 {0x1002, 0x4c4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
309 {0x1002, 0x4c4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
310 {0, 0, 0}
311
312#define sisdrv_PCI_IDS \
313 {0x1039, 0x0300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
314 {0x1039, 0x5300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
315 {0x1039, 0x6300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
316 {0x1039, 0x6330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \
317 {0x1039, 0x6351, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
318 {0x1039, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
319 {0x18CA, 0x0040, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \
320 {0x18CA, 0x0042, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_CHIP_315}, \
321 {0, 0, 0}
322
323#define tdfx_PCI_IDS \
324 {0x121a, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
325 {0x121a, 0x0004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
326 {0x121a, 0x0005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
327 {0x121a, 0x0007, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
328 {0x121a, 0x0009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
329 {0x121a, 0x000b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
330 {0, 0, 0}
331
332#define viadrv_PCI_IDS \
333 {0x1106, 0x3022, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
334 {0x1106, 0x3118, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
335 {0x1106, 0x3122, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
336 {0x1106, 0x7205, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
337 {0x1106, 0x3108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
338 {0x1106, 0x3344, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
339 {0x1106, 0x3343, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
340 {0x1106, 0x3230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_DX9_0}, \
341 {0x1106, 0x3157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VIA_PRO_GROUP_A}, \
342 {0, 0, 0}
343
344#define i810_PCI_IDS \
345 {0x8086, 0x7121, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
346 {0x8086, 0x7123, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
347 {0x8086, 0x7125, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
348 {0x8086, 0x1132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
349 {0, 0, 0}
350
351#define i830_PCI_IDS \
352 {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
353 {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
354 {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
355 {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
356 {0, 0, 0}
357
358#define gamma_PCI_IDS \
359 {0x3d3d, 0x0008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
360 {0, 0, 0}
361
362#define savage_PCI_IDS \
363 {0x5333, 0x8a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE3D}, \
364 {0x5333, 0x8a21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE3D}, \
365 {0x5333, 0x8a22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE4}, \
366 {0x5333, 0x8a23, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE4}, \
367 {0x5333, 0x8c10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
368 {0x5333, 0x8c11, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
369 {0x5333, 0x8c12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
370 {0x5333, 0x8c13, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SAVAGE_MX}, \
371 {0x5333, 0x8c22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
372 {0x5333, 0x8c24, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
373 {0x5333, 0x8c26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
374 {0x5333, 0x8c2a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
375 {0x5333, 0x8c2b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
376 {0x5333, 0x8c2c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
377 {0x5333, 0x8c2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
378 {0x5333, 0x8c2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
379 {0x5333, 0x8c2f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_SUPERSAVAGE}, \
380 {0x5333, 0x8a25, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGE}, \
381 {0x5333, 0x8a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGE}, \
382 {0x5333, 0x8d01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_TWISTER}, \
383 {0x5333, 0x8d02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_TWISTER}, \
384 {0x5333, 0x8d03, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGEDDR}, \
385 {0x5333, 0x8d04, PCI_ANY_ID, PCI_ANY_ID, 0, 0, S3_PROSAVAGEDDR}, \
386 {0, 0, 0}
387
388#define ffb_PCI_IDS \
389 {0, 0, 0}
390
391#define i915_PCI_IDS \
392 {0x8086, 0x3577, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
393 {0x8086, 0x2562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
394 {0x8086, 0x3582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
395 {0x8086, 0x2572, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
396 {0x8086, 0x2582, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
397 {0x8086, 0x258a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
398 {0x8086, 0x2592, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
399 {0x8086, 0x2772, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
400 {0x8086, 0x27a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
401 {0x8086, 0x27ae, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
402 {0x8086, 0x2972, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
403 {0x8086, 0x2982, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
404 {0x8086, 0x2992, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
405 {0x8086, 0x29a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
406 {0x8086, 0x29b2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
407 {0x8086, 0x29c2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
408 {0x8086, 0x29d2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
409 {0x8086, 0x2a02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
410 {0x8086, 0x2a12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
411 {0x8086, 0x2a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
412 {0x8086, 0x2e02, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
413 {0x8086, 0x2e12, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
414 {0x8086, 0x2e22, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, \
415 {0, 0, 0}
diff --git a/include/drm/drm_sarea.h b/include/drm/drm_sarea.h
new file mode 100644
index 000000000000..480037331e4e
--- /dev/null
+++ b/include/drm/drm_sarea.h
@@ -0,0 +1,84 @@
1/**
2 * \file drm_sarea.h
3 * \brief SAREA definitions
4 *
5 * \author Michel Dänzer <michel@daenzer.net>
6 */
7
8/*
9 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
10 * All Rights Reserved.
11 *
12 * Permission is hereby granted, free of charge, to any person obtaining a
13 * copy of this software and associated documentation files (the "Software"),
14 * to deal in the Software without restriction, including without limitation
15 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
16 * and/or sell copies of the Software, and to permit persons to whom the
17 * Software is furnished to do so, subject to the following conditions:
18 *
19 * The above copyright notice and this permission notice (including the next
20 * paragraph) shall be included in all copies or substantial portions of the
21 * Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
27 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
28 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
29 * OTHER DEALINGS IN THE SOFTWARE.
30 */
31
32#ifndef _DRM_SAREA_H_
33#define _DRM_SAREA_H_
34
35#include "drm.h"
36
37/* SAREA area needs to be at least a page */
38#if defined(__alpha__)
39#define SAREA_MAX 0x2000
40#elif defined(__ia64__)
41#define SAREA_MAX 0x10000 /* 64kB */
42#else
43/* Intel 830M driver needs at least 8k SAREA */
44#define SAREA_MAX 0x2000
45#endif
46
47/** Maximum number of drawables in the SAREA */
48#define SAREA_MAX_DRAWABLES 256
49
50#define SAREA_DRAWABLE_CLAIMED_ENTRY 0x80000000
51
52/** SAREA drawable */
53struct drm_sarea_drawable {
54 unsigned int stamp;
55 unsigned int flags;
56};
57
58/** SAREA frame */
59struct drm_sarea_frame {
60 unsigned int x;
61 unsigned int y;
62 unsigned int width;
63 unsigned int height;
64 unsigned int fullscreen;
65};
66
67/** SAREA */
68struct drm_sarea {
69 /** first thing is always the DRM locking structure */
70 struct drm_hw_lock lock;
71 /** \todo Use readers/writer lock for drm_sarea::drawable_lock */
72 struct drm_hw_lock drawable_lock;
73 struct drm_sarea_drawable drawableTable[SAREA_MAX_DRAWABLES]; /**< drawables */
74 struct drm_sarea_frame frame; /**< frame */
75 drm_context_t dummy_context;
76};
77
78#ifndef __KERNEL__
79typedef struct drm_sarea_drawable drm_sarea_drawable_t;
80typedef struct drm_sarea_frame drm_sarea_frame_t;
81typedef struct drm_sarea drm_sarea_t;
82#endif
83
84#endif /* _DRM_SAREA_H_ */
diff --git a/include/drm/drm_sman.h b/include/drm/drm_sman.h
new file mode 100644
index 000000000000..08ecf83ad5d4
--- /dev/null
+++ b/include/drm/drm_sman.h
@@ -0,0 +1,176 @@
1/**************************************************************************
2 *
3 * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 *
27 **************************************************************************/
28/*
29 * Simple memory MANager interface that keeps track on allocate regions on a
30 * per "owner" basis. All regions associated with an "owner" can be released
31 * with a simple call. Typically if the "owner" exists. The owner is any
32 * "unsigned long" identifier. Can typically be a pointer to a file private
33 * struct or a context identifier.
34 *
35 * Authors:
36 * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
37 */
38
39#ifndef DRM_SMAN_H
40#define DRM_SMAN_H
41
42#include "drmP.h"
43#include "drm_hashtab.h"
44
45/*
46 * A class that is an abstration of a simple memory allocator.
47 * The sman implementation provides a default such allocator
48 * using the drm_mm.c implementation. But the user can replace it.
49 * See the SiS implementation, which may use the SiS FB kernel module
50 * for memory management.
51 */
52
53struct drm_sman_mm {
54 /* private info. If allocated, needs to be destroyed by the destroy
55 function */
56 void *private;
57
58 /* Allocate a memory block with given size and alignment.
59 Return an opaque reference to the memory block */
60
61 void *(*allocate) (void *private, unsigned long size,
62 unsigned alignment);
63
64 /* Free a memory block. "ref" is the opaque reference that we got from
65 the "alloc" function */
66
67 void (*free) (void *private, void *ref);
68
69 /* Free all resources associated with this allocator */
70
71 void (*destroy) (void *private);
72
73 /* Return a memory offset from the opaque reference returned from the
74 "alloc" function */
75
76 unsigned long (*offset) (void *private, void *ref);
77};
78
79struct drm_memblock_item {
80 struct list_head owner_list;
81 struct drm_hash_item user_hash;
82 void *mm_info;
83 struct drm_sman_mm *mm;
84 struct drm_sman *sman;
85};
86
87struct drm_sman {
88 struct drm_sman_mm *mm;
89 int num_managers;
90 struct drm_open_hash owner_hash_tab;
91 struct drm_open_hash user_hash_tab;
92 struct list_head owner_items;
93};
94
95/*
96 * Take down a memory manager. This function should only be called after a
97 * successful init and after a call to drm_sman_cleanup.
98 */
99
100extern void drm_sman_takedown(struct drm_sman * sman);
101
102/*
103 * Allocate structures for a manager.
104 * num_managers are the number of memory pools to manage. (VRAM, AGP, ....)
105 * user_order is the log2 of the number of buckets in the user hash table.
106 * set this to approximately log2 of the max number of memory regions
107 * that will be allocated for _all_ pools together.
108 * owner_order is the log2 of the number of buckets in the owner hash table.
109 * set this to approximately log2 of
110 * the number of client file connections that will
111 * be using the manager.
112 *
113 */
114
115extern int drm_sman_init(struct drm_sman * sman, unsigned int num_managers,
116 unsigned int user_order, unsigned int owner_order);
117
118/*
119 * Initialize a drm_mm.c allocator. Should be called only once for each
120 * manager unless a customized allogator is used.
121 */
122
123extern int drm_sman_set_range(struct drm_sman * sman, unsigned int manager,
124 unsigned long start, unsigned long size);
125
126/*
127 * Initialize a customized allocator for one of the managers.
128 * (See the SiS module). The object pointed to by "allocator" is copied,
129 * so it can be destroyed after this call.
130 */
131
132extern int drm_sman_set_manager(struct drm_sman * sman, unsigned int mananger,
133 struct drm_sman_mm * allocator);
134
135/*
136 * Allocate a memory block. Aligment is not implemented yet.
137 */
138
139extern struct drm_memblock_item *drm_sman_alloc(struct drm_sman * sman,
140 unsigned int manager,
141 unsigned long size,
142 unsigned alignment,
143 unsigned long owner);
144/*
145 * Free a memory block identified by its user hash key.
146 */
147
148extern int drm_sman_free_key(struct drm_sman * sman, unsigned int key);
149
150/*
151 * returns 1 iff there are no stale memory blocks associated with this owner.
152 * Typically called to determine if we need to idle the hardware and call
153 * drm_sman_owner_cleanup. If there are no stale memory blocks, it removes all
154 * resources associated with owner.
155 */
156
157extern int drm_sman_owner_clean(struct drm_sman * sman, unsigned long owner);
158
159/*
160 * Frees all stale memory blocks associated with this owner. Note that this
161 * requires that the hardware is finished with all blocks, so the graphics engine
162 * should be idled before this call is made. This function also frees
163 * any resources associated with "owner" and should be called when owner
164 * is not going to be referenced anymore.
165 */
166
167extern void drm_sman_owner_cleanup(struct drm_sman * sman, unsigned long owner);
168
169/*
170 * Frees all stale memory blocks associated with the memory manager.
171 * See idling above.
172 */
173
174extern void drm_sman_cleanup(struct drm_sman * sman);
175
176#endif
diff --git a/include/drm/i810_drm.h b/include/drm/i810_drm.h
new file mode 100644
index 000000000000..7a10bb6f2c0f
--- /dev/null
+++ b/include/drm/i810_drm.h
@@ -0,0 +1,281 @@
1#ifndef _I810_DRM_H_
2#define _I810_DRM_H_
3
4/* WARNING: These defines must be the same as what the Xserver uses.
5 * if you change them, you must change the defines in the Xserver.
6 */
7
8#ifndef _I810_DEFINES_
9#define _I810_DEFINES_
10
11#define I810_DMA_BUF_ORDER 12
12#define I810_DMA_BUF_SZ (1<<I810_DMA_BUF_ORDER)
13#define I810_DMA_BUF_NR 256
14#define I810_NR_SAREA_CLIPRECTS 8
15
16/* Each region is a minimum of 64k, and there are at most 64 of them.
17 */
18#define I810_NR_TEX_REGIONS 64
19#define I810_LOG_MIN_TEX_REGION_SIZE 16
20#endif
21
22#define I810_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
23#define I810_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
24#define I810_UPLOAD_CTX 0x4
25#define I810_UPLOAD_BUFFERS 0x8
26#define I810_UPLOAD_TEX0 0x10
27#define I810_UPLOAD_TEX1 0x20
28#define I810_UPLOAD_CLIPRECTS 0x40
29
30/* Indices into buf.Setup where various bits of state are mirrored per
31 * context and per buffer. These can be fired at the card as a unit,
32 * or in a piecewise fashion as required.
33 */
34
35/* Destbuffer state
36 * - backbuffer linear offset and pitch -- invarient in the current dri
37 * - zbuffer linear offset and pitch -- also invarient
38 * - drawing origin in back and depth buffers.
39 *
40 * Keep the depth/back buffer state here to accommodate private buffers
41 * in the future.
42 */
43#define I810_DESTREG_DI0 0 /* CMD_OP_DESTBUFFER_INFO (2 dwords) */
44#define I810_DESTREG_DI1 1
45#define I810_DESTREG_DV0 2 /* GFX_OP_DESTBUFFER_VARS (2 dwords) */
46#define I810_DESTREG_DV1 3
47#define I810_DESTREG_DR0 4 /* GFX_OP_DRAWRECT_INFO (4 dwords) */
48#define I810_DESTREG_DR1 5
49#define I810_DESTREG_DR2 6
50#define I810_DESTREG_DR3 7
51#define I810_DESTREG_DR4 8
52#define I810_DEST_SETUP_SIZE 10
53
54/* Context state
55 */
56#define I810_CTXREG_CF0 0 /* GFX_OP_COLOR_FACTOR */
57#define I810_CTXREG_CF1 1
58#define I810_CTXREG_ST0 2 /* GFX_OP_STIPPLE */
59#define I810_CTXREG_ST1 3
60#define I810_CTXREG_VF 4 /* GFX_OP_VERTEX_FMT */
61#define I810_CTXREG_MT 5 /* GFX_OP_MAP_TEXELS */
62#define I810_CTXREG_MC0 6 /* GFX_OP_MAP_COLOR_STAGES - stage 0 */
63#define I810_CTXREG_MC1 7 /* GFX_OP_MAP_COLOR_STAGES - stage 1 */
64#define I810_CTXREG_MC2 8 /* GFX_OP_MAP_COLOR_STAGES - stage 2 */
65#define I810_CTXREG_MA0 9 /* GFX_OP_MAP_ALPHA_STAGES - stage 0 */
66#define I810_CTXREG_MA1 10 /* GFX_OP_MAP_ALPHA_STAGES - stage 1 */
67#define I810_CTXREG_MA2 11 /* GFX_OP_MAP_ALPHA_STAGES - stage 2 */
68#define I810_CTXREG_SDM 12 /* GFX_OP_SRC_DEST_MONO */
69#define I810_CTXREG_FOG 13 /* GFX_OP_FOG_COLOR */
70#define I810_CTXREG_B1 14 /* GFX_OP_BOOL_1 */
71#define I810_CTXREG_B2 15 /* GFX_OP_BOOL_2 */
72#define I810_CTXREG_LCS 16 /* GFX_OP_LINEWIDTH_CULL_SHADE_MODE */
73#define I810_CTXREG_PV 17 /* GFX_OP_PV_RULE -- Invarient! */
74#define I810_CTXREG_ZA 18 /* GFX_OP_ZBIAS_ALPHAFUNC */
75#define I810_CTXREG_AA 19 /* GFX_OP_ANTIALIAS */
76#define I810_CTX_SETUP_SIZE 20
77
78/* Texture state (per tex unit)
79 */
80#define I810_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (4 dwords) */
81#define I810_TEXREG_MI1 1
82#define I810_TEXREG_MI2 2
83#define I810_TEXREG_MI3 3
84#define I810_TEXREG_MF 4 /* GFX_OP_MAP_FILTER */
85#define I810_TEXREG_MLC 5 /* GFX_OP_MAP_LOD_CTL */
86#define I810_TEXREG_MLL 6 /* GFX_OP_MAP_LOD_LIMITS */
87#define I810_TEXREG_MCS 7 /* GFX_OP_MAP_COORD_SETS ??? */
88#define I810_TEX_SETUP_SIZE 8
89
90/* Flags for clear ioctl
91 */
92#define I810_FRONT 0x1
93#define I810_BACK 0x2
94#define I810_DEPTH 0x4
95
96typedef enum _drm_i810_init_func {
97 I810_INIT_DMA = 0x01,
98 I810_CLEANUP_DMA = 0x02,
99 I810_INIT_DMA_1_4 = 0x03
100} drm_i810_init_func_t;
101
102/* This is the init structure after v1.2 */
103typedef struct _drm_i810_init {
104 drm_i810_init_func_t func;
105 unsigned int mmio_offset;
106 unsigned int buffers_offset;
107 int sarea_priv_offset;
108 unsigned int ring_start;
109 unsigned int ring_end;
110 unsigned int ring_size;
111 unsigned int front_offset;
112 unsigned int back_offset;
113 unsigned int depth_offset;
114 unsigned int overlay_offset;
115 unsigned int overlay_physical;
116 unsigned int w;
117 unsigned int h;
118 unsigned int pitch;
119 unsigned int pitch_bits;
120} drm_i810_init_t;
121
122/* This is the init structure prior to v1.2 */
123typedef struct _drm_i810_pre12_init {
124 drm_i810_init_func_t func;
125 unsigned int mmio_offset;
126 unsigned int buffers_offset;
127 int sarea_priv_offset;
128 unsigned int ring_start;
129 unsigned int ring_end;
130 unsigned int ring_size;
131 unsigned int front_offset;
132 unsigned int back_offset;
133 unsigned int depth_offset;
134 unsigned int w;
135 unsigned int h;
136 unsigned int pitch;
137 unsigned int pitch_bits;
138} drm_i810_pre12_init_t;
139
140/* Warning: If you change the SAREA structure you must change the Xserver
141 * structure as well */
142
143typedef struct _drm_i810_tex_region {
144 unsigned char next, prev; /* indices to form a circular LRU */
145 unsigned char in_use; /* owned by a client, or free? */
146 int age; /* tracked by clients to update local LRU's */
147} drm_i810_tex_region_t;
148
149typedef struct _drm_i810_sarea {
150 unsigned int ContextState[I810_CTX_SETUP_SIZE];
151 unsigned int BufferState[I810_DEST_SETUP_SIZE];
152 unsigned int TexState[2][I810_TEX_SETUP_SIZE];
153 unsigned int dirty;
154
155 unsigned int nbox;
156 struct drm_clip_rect boxes[I810_NR_SAREA_CLIPRECTS];
157
158 /* Maintain an LRU of contiguous regions of texture space. If
159 * you think you own a region of texture memory, and it has an
160 * age different to the one you set, then you are mistaken and
161 * it has been stolen by another client. If global texAge
162 * hasn't changed, there is no need to walk the list.
163 *
164 * These regions can be used as a proxy for the fine-grained
165 * texture information of other clients - by maintaining them
166 * in the same lru which is used to age their own textures,
167 * clients have an approximate lru for the whole of global
168 * texture space, and can make informed decisions as to which
169 * areas to kick out. There is no need to choose whether to
170 * kick out your own texture or someone else's - simply eject
171 * them all in LRU order.
172 */
173
174 drm_i810_tex_region_t texList[I810_NR_TEX_REGIONS + 1];
175 /* Last elt is sentinal */
176 int texAge; /* last time texture was uploaded */
177 int last_enqueue; /* last time a buffer was enqueued */
178 int last_dispatch; /* age of the most recently dispatched buffer */
179 int last_quiescent; /* */
180 int ctxOwner; /* last context to upload state */
181
182 int vertex_prim;
183
184 int pf_enabled; /* is pageflipping allowed? */
185 int pf_active;
186 int pf_current_page; /* which buffer is being displayed? */
187} drm_i810_sarea_t;
188
189/* WARNING: If you change any of these defines, make sure to change the
190 * defines in the Xserver file (xf86drmMga.h)
191 */
192
193/* i810 specific ioctls
194 * The device specific ioctl range is 0x40 to 0x79.
195 */
196#define DRM_I810_INIT 0x00
197#define DRM_I810_VERTEX 0x01
198#define DRM_I810_CLEAR 0x02
199#define DRM_I810_FLUSH 0x03
200#define DRM_I810_GETAGE 0x04
201#define DRM_I810_GETBUF 0x05
202#define DRM_I810_SWAP 0x06
203#define DRM_I810_COPY 0x07
204#define DRM_I810_DOCOPY 0x08
205#define DRM_I810_OV0INFO 0x09
206#define DRM_I810_FSTATUS 0x0a
207#define DRM_I810_OV0FLIP 0x0b
208#define DRM_I810_MC 0x0c
209#define DRM_I810_RSTATUS 0x0d
210#define DRM_I810_FLIP 0x0e
211
212#define DRM_IOCTL_I810_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I810_INIT, drm_i810_init_t)
213#define DRM_IOCTL_I810_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_I810_VERTEX, drm_i810_vertex_t)
214#define DRM_IOCTL_I810_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_I810_CLEAR, drm_i810_clear_t)
215#define DRM_IOCTL_I810_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_I810_FLUSH)
216#define DRM_IOCTL_I810_GETAGE DRM_IO( DRM_COMMAND_BASE + DRM_I810_GETAGE)
217#define DRM_IOCTL_I810_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_I810_GETBUF, drm_i810_dma_t)
218#define DRM_IOCTL_I810_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_I810_SWAP)
219#define DRM_IOCTL_I810_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_I810_COPY, drm_i810_copy_t)
220#define DRM_IOCTL_I810_DOCOPY DRM_IO( DRM_COMMAND_BASE + DRM_I810_DOCOPY)
221#define DRM_IOCTL_I810_OV0INFO DRM_IOR( DRM_COMMAND_BASE + DRM_I810_OV0INFO, drm_i810_overlay_t)
222#define DRM_IOCTL_I810_FSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FSTATUS)
223#define DRM_IOCTL_I810_OV0FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_OV0FLIP)
224#define DRM_IOCTL_I810_MC DRM_IOW( DRM_COMMAND_BASE + DRM_I810_MC, drm_i810_mc_t)
225#define DRM_IOCTL_I810_RSTATUS DRM_IO ( DRM_COMMAND_BASE + DRM_I810_RSTATUS)
226#define DRM_IOCTL_I810_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I810_FLIP)
227
228typedef struct _drm_i810_clear {
229 int clear_color;
230 int clear_depth;
231 int flags;
232} drm_i810_clear_t;
233
234/* These may be placeholders if we have more cliprects than
235 * I810_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
236 * false, indicating that the buffer will be dispatched again with a
237 * new set of cliprects.
238 */
239typedef struct _drm_i810_vertex {
240 int idx; /* buffer index */
241 int used; /* nr bytes in use */
242 int discard; /* client is finished with the buffer? */
243} drm_i810_vertex_t;
244
245typedef struct _drm_i810_copy_t {
246 int idx; /* buffer index */
247 int used; /* nr bytes in use */
248 void *address; /* Address to copy from */
249} drm_i810_copy_t;
250
251#define PR_TRIANGLES (0x0<<18)
252#define PR_TRISTRIP_0 (0x1<<18)
253#define PR_TRISTRIP_1 (0x2<<18)
254#define PR_TRIFAN (0x3<<18)
255#define PR_POLYGON (0x4<<18)
256#define PR_LINES (0x5<<18)
257#define PR_LINESTRIP (0x6<<18)
258#define PR_RECTS (0x7<<18)
259#define PR_MASK (0x7<<18)
260
261typedef struct drm_i810_dma {
262 void *virtual;
263 int request_idx;
264 int request_size;
265 int granted;
266} drm_i810_dma_t;
267
268typedef struct _drm_i810_overlay_t {
269 unsigned int offset; /* Address of the Overlay Regs */
270 unsigned int physical;
271} drm_i810_overlay_t;
272
273typedef struct _drm_i810_mc {
274 int idx; /* buffer index */
275 int used; /* nr bytes in use */
276 int num_blocks; /* number of GFXBlocks */
277 int *length; /* List of lengths for GFXBlocks (FUTURE) */
278 unsigned int last_render; /* Last Render Request */
279} drm_i810_mc_t;
280
281#endif /* _I810_DRM_H_ */
diff --git a/include/drm/i830_drm.h b/include/drm/i830_drm.h
new file mode 100644
index 000000000000..4b00d2dd4f68
--- /dev/null
+++ b/include/drm/i830_drm.h
@@ -0,0 +1,342 @@
1#ifndef _I830_DRM_H_
2#define _I830_DRM_H_
3
4/* WARNING: These defines must be the same as what the Xserver uses.
5 * if you change them, you must change the defines in the Xserver.
6 *
7 * KW: Actually, you can't ever change them because doing so would
8 * break backwards compatibility.
9 */
10
11#ifndef _I830_DEFINES_
12#define _I830_DEFINES_
13
14#define I830_DMA_BUF_ORDER 12
15#define I830_DMA_BUF_SZ (1<<I830_DMA_BUF_ORDER)
16#define I830_DMA_BUF_NR 256
17#define I830_NR_SAREA_CLIPRECTS 8
18
19/* Each region is a minimum of 64k, and there are at most 64 of them.
20 */
21#define I830_NR_TEX_REGIONS 64
22#define I830_LOG_MIN_TEX_REGION_SIZE 16
23
24/* KW: These aren't correct but someone set them to two and then
25 * released the module. Now we can't change them as doing so would
26 * break backwards compatibility.
27 */
28#define I830_TEXTURE_COUNT 2
29#define I830_TEXBLEND_COUNT I830_TEXTURE_COUNT
30
31#define I830_TEXBLEND_SIZE 12 /* (4 args + op) * 2 + COLOR_FACTOR */
32
33#define I830_UPLOAD_CTX 0x1
34#define I830_UPLOAD_BUFFERS 0x2
35#define I830_UPLOAD_CLIPRECTS 0x4
36#define I830_UPLOAD_TEX0_IMAGE 0x100 /* handled clientside */
37#define I830_UPLOAD_TEX0_CUBE 0x200 /* handled clientside */
38#define I830_UPLOAD_TEX1_IMAGE 0x400 /* handled clientside */
39#define I830_UPLOAD_TEX1_CUBE 0x800 /* handled clientside */
40#define I830_UPLOAD_TEX2_IMAGE 0x1000 /* handled clientside */
41#define I830_UPLOAD_TEX2_CUBE 0x2000 /* handled clientside */
42#define I830_UPLOAD_TEX3_IMAGE 0x4000 /* handled clientside */
43#define I830_UPLOAD_TEX3_CUBE 0x8000 /* handled clientside */
44#define I830_UPLOAD_TEX_N_IMAGE(n) (0x100 << (n * 2))
45#define I830_UPLOAD_TEX_N_CUBE(n) (0x200 << (n * 2))
46#define I830_UPLOAD_TEXIMAGE_MASK 0xff00
47#define I830_UPLOAD_TEX0 0x10000
48#define I830_UPLOAD_TEX1 0x20000
49#define I830_UPLOAD_TEX2 0x40000
50#define I830_UPLOAD_TEX3 0x80000
51#define I830_UPLOAD_TEX_N(n) (0x10000 << (n))
52#define I830_UPLOAD_TEX_MASK 0xf0000
53#define I830_UPLOAD_TEXBLEND0 0x100000
54#define I830_UPLOAD_TEXBLEND1 0x200000
55#define I830_UPLOAD_TEXBLEND2 0x400000
56#define I830_UPLOAD_TEXBLEND3 0x800000
57#define I830_UPLOAD_TEXBLEND_N(n) (0x100000 << (n))
58#define I830_UPLOAD_TEXBLEND_MASK 0xf00000
59#define I830_UPLOAD_TEX_PALETTE_N(n) (0x1000000 << (n))
60#define I830_UPLOAD_TEX_PALETTE_SHARED 0x4000000
61#define I830_UPLOAD_STIPPLE 0x8000000
62
63/* Indices into buf.Setup where various bits of state are mirrored per
64 * context and per buffer. These can be fired at the card as a unit,
65 * or in a piecewise fashion as required.
66 */
67
68/* Destbuffer state
69 * - backbuffer linear offset and pitch -- invarient in the current dri
70 * - zbuffer linear offset and pitch -- also invarient
71 * - drawing origin in back and depth buffers.
72 *
73 * Keep the depth/back buffer state here to accommodate private buffers
74 * in the future.
75 */
76
77#define I830_DESTREG_CBUFADDR 0
78#define I830_DESTREG_DBUFADDR 1
79#define I830_DESTREG_DV0 2
80#define I830_DESTREG_DV1 3
81#define I830_DESTREG_SENABLE 4
82#define I830_DESTREG_SR0 5
83#define I830_DESTREG_SR1 6
84#define I830_DESTREG_SR2 7
85#define I830_DESTREG_DR0 8
86#define I830_DESTREG_DR1 9
87#define I830_DESTREG_DR2 10
88#define I830_DESTREG_DR3 11
89#define I830_DESTREG_DR4 12
90#define I830_DEST_SETUP_SIZE 13
91
92/* Context state
93 */
94#define I830_CTXREG_STATE1 0
95#define I830_CTXREG_STATE2 1
96#define I830_CTXREG_STATE3 2
97#define I830_CTXREG_STATE4 3
98#define I830_CTXREG_STATE5 4
99#define I830_CTXREG_IALPHAB 5
100#define I830_CTXREG_STENCILTST 6
101#define I830_CTXREG_ENABLES_1 7
102#define I830_CTXREG_ENABLES_2 8
103#define I830_CTXREG_AA 9
104#define I830_CTXREG_FOGCOLOR 10
105#define I830_CTXREG_BLENDCOLR0 11
106#define I830_CTXREG_BLENDCOLR 12 /* Dword 1 of 2 dword command */
107#define I830_CTXREG_VF 13
108#define I830_CTXREG_VF2 14
109#define I830_CTXREG_MCSB0 15
110#define I830_CTXREG_MCSB1 16
111#define I830_CTX_SETUP_SIZE 17
112
113/* 1.3: Stipple state
114 */
115#define I830_STPREG_ST0 0
116#define I830_STPREG_ST1 1
117#define I830_STP_SETUP_SIZE 2
118
119/* Texture state (per tex unit)
120 */
121
122#define I830_TEXREG_MI0 0 /* GFX_OP_MAP_INFO (6 dwords) */
123#define I830_TEXREG_MI1 1
124#define I830_TEXREG_MI2 2
125#define I830_TEXREG_MI3 3
126#define I830_TEXREG_MI4 4
127#define I830_TEXREG_MI5 5
128#define I830_TEXREG_MF 6 /* GFX_OP_MAP_FILTER */
129#define I830_TEXREG_MLC 7 /* GFX_OP_MAP_LOD_CTL */
130#define I830_TEXREG_MLL 8 /* GFX_OP_MAP_LOD_LIMITS */
131#define I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS */
132#define I830_TEX_SETUP_SIZE 10
133
134#define I830_TEXREG_TM0LI 0 /* load immediate 2 texture map n */
135#define I830_TEXREG_TM0S0 1
136#define I830_TEXREG_TM0S1 2
137#define I830_TEXREG_TM0S2 3
138#define I830_TEXREG_TM0S3 4
139#define I830_TEXREG_TM0S4 5
140#define I830_TEXREG_NOP0 6 /* noop */
141#define I830_TEXREG_NOP1 7 /* noop */
142#define I830_TEXREG_NOP2 8 /* noop */
143#define __I830_TEXREG_MCS 9 /* GFX_OP_MAP_COORD_SETS -- shared */
144#define __I830_TEX_SETUP_SIZE 10
145
146#define I830_FRONT 0x1
147#define I830_BACK 0x2
148#define I830_DEPTH 0x4
149
150#endif /* _I830_DEFINES_ */
151
152typedef struct _drm_i830_init {
153 enum {
154 I830_INIT_DMA = 0x01,
155 I830_CLEANUP_DMA = 0x02
156 } func;
157 unsigned int mmio_offset;
158 unsigned int buffers_offset;
159 int sarea_priv_offset;
160 unsigned int ring_start;
161 unsigned int ring_end;
162 unsigned int ring_size;
163 unsigned int front_offset;
164 unsigned int back_offset;
165 unsigned int depth_offset;
166 unsigned int w;
167 unsigned int h;
168 unsigned int pitch;
169 unsigned int pitch_bits;
170 unsigned int back_pitch;
171 unsigned int depth_pitch;
172 unsigned int cpp;
173} drm_i830_init_t;
174
175/* Warning: If you change the SAREA structure you must change the Xserver
176 * structure as well */
177
178typedef struct _drm_i830_tex_region {
179 unsigned char next, prev; /* indices to form a circular LRU */
180 unsigned char in_use; /* owned by a client, or free? */
181 int age; /* tracked by clients to update local LRU's */
182} drm_i830_tex_region_t;
183
184typedef struct _drm_i830_sarea {
185 unsigned int ContextState[I830_CTX_SETUP_SIZE];
186 unsigned int BufferState[I830_DEST_SETUP_SIZE];
187 unsigned int TexState[I830_TEXTURE_COUNT][I830_TEX_SETUP_SIZE];
188 unsigned int TexBlendState[I830_TEXBLEND_COUNT][I830_TEXBLEND_SIZE];
189 unsigned int TexBlendStateWordsUsed[I830_TEXBLEND_COUNT];
190 unsigned int Palette[2][256];
191 unsigned int dirty;
192
193 unsigned int nbox;
194 struct drm_clip_rect boxes[I830_NR_SAREA_CLIPRECTS];
195
196 /* Maintain an LRU of contiguous regions of texture space. If
197 * you think you own a region of texture memory, and it has an
198 * age different to the one you set, then you are mistaken and
199 * it has been stolen by another client. If global texAge
200 * hasn't changed, there is no need to walk the list.
201 *
202 * These regions can be used as a proxy for the fine-grained
203 * texture information of other clients - by maintaining them
204 * in the same lru which is used to age their own textures,
205 * clients have an approximate lru for the whole of global
206 * texture space, and can make informed decisions as to which
207 * areas to kick out. There is no need to choose whether to
208 * kick out your own texture or someone else's - simply eject
209 * them all in LRU order.
210 */
211
212 drm_i830_tex_region_t texList[I830_NR_TEX_REGIONS + 1];
213 /* Last elt is sentinal */
214 int texAge; /* last time texture was uploaded */
215 int last_enqueue; /* last time a buffer was enqueued */
216 int last_dispatch; /* age of the most recently dispatched buffer */
217 int last_quiescent; /* */
218 int ctxOwner; /* last context to upload state */
219
220 int vertex_prim;
221
222 int pf_enabled; /* is pageflipping allowed? */
223 int pf_active;
224 int pf_current_page; /* which buffer is being displayed? */
225
226 int perf_boxes; /* performance boxes to be displayed */
227
228 /* Here's the state for texunits 2,3:
229 */
230 unsigned int TexState2[I830_TEX_SETUP_SIZE];
231 unsigned int TexBlendState2[I830_TEXBLEND_SIZE];
232 unsigned int TexBlendStateWordsUsed2;
233
234 unsigned int TexState3[I830_TEX_SETUP_SIZE];
235 unsigned int TexBlendState3[I830_TEXBLEND_SIZE];
236 unsigned int TexBlendStateWordsUsed3;
237
238 unsigned int StippleState[I830_STP_SETUP_SIZE];
239} drm_i830_sarea_t;
240
241/* Flags for perf_boxes
242 */
243#define I830_BOX_RING_EMPTY 0x1 /* populated by kernel */
244#define I830_BOX_FLIP 0x2 /* populated by kernel */
245#define I830_BOX_WAIT 0x4 /* populated by kernel & client */
246#define I830_BOX_TEXTURE_LOAD 0x8 /* populated by kernel */
247#define I830_BOX_LOST_CONTEXT 0x10 /* populated by client */
248
249/* I830 specific ioctls
250 * The device specific ioctl range is 0x40 to 0x79.
251 */
252#define DRM_I830_INIT 0x00
253#define DRM_I830_VERTEX 0x01
254#define DRM_I830_CLEAR 0x02
255#define DRM_I830_FLUSH 0x03
256#define DRM_I830_GETAGE 0x04
257#define DRM_I830_GETBUF 0x05
258#define DRM_I830_SWAP 0x06
259#define DRM_I830_COPY 0x07
260#define DRM_I830_DOCOPY 0x08
261#define DRM_I830_FLIP 0x09
262#define DRM_I830_IRQ_EMIT 0x0a
263#define DRM_I830_IRQ_WAIT 0x0b
264#define DRM_I830_GETPARAM 0x0c
265#define DRM_I830_SETPARAM 0x0d
266
267#define DRM_IOCTL_I830_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_INIT, drm_i830_init_t)
268#define DRM_IOCTL_I830_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_VERTEX, drm_i830_vertex_t)
269#define DRM_IOCTL_I830_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_CLEAR, drm_i830_clear_t)
270#define DRM_IOCTL_I830_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLUSH)
271#define DRM_IOCTL_I830_GETAGE DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_GETAGE)
272#define DRM_IOCTL_I830_GETBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETBUF, drm_i830_dma_t)
273#define DRM_IOCTL_I830_SWAP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_SWAP)
274#define DRM_IOCTL_I830_COPY DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_COPY, drm_i830_copy_t)
275#define DRM_IOCTL_I830_DOCOPY DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_DOCOPY)
276#define DRM_IOCTL_I830_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_IOCTL_I830_FLIP)
277#define DRM_IOCTL_I830_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_EMIT, drm_i830_irq_emit_t)
278#define DRM_IOCTL_I830_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_IOCTL_I830_IRQ_WAIT, drm_i830_irq_wait_t)
279#define DRM_IOCTL_I830_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_GETPARAM, drm_i830_getparam_t)
280#define DRM_IOCTL_I830_SETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_IOCTL_I830_SETPARAM, drm_i830_setparam_t)
281
282typedef struct _drm_i830_clear {
283 int clear_color;
284 int clear_depth;
285 int flags;
286 unsigned int clear_colormask;
287 unsigned int clear_depthmask;
288} drm_i830_clear_t;
289
290/* These may be placeholders if we have more cliprects than
291 * I830_NR_SAREA_CLIPRECTS. In that case, the client sets discard to
292 * false, indicating that the buffer will be dispatched again with a
293 * new set of cliprects.
294 */
295typedef struct _drm_i830_vertex {
296 int idx; /* buffer index */
297 int used; /* nr bytes in use */
298 int discard; /* client is finished with the buffer? */
299} drm_i830_vertex_t;
300
301typedef struct _drm_i830_copy_t {
302 int idx; /* buffer index */
303 int used; /* nr bytes in use */
304 void __user *address; /* Address to copy from */
305} drm_i830_copy_t;
306
307typedef struct drm_i830_dma {
308 void __user *virtual;
309 int request_idx;
310 int request_size;
311 int granted;
312} drm_i830_dma_t;
313
314/* 1.3: Userspace can request & wait on irq's:
315 */
316typedef struct drm_i830_irq_emit {
317 int __user *irq_seq;
318} drm_i830_irq_emit_t;
319
320typedef struct drm_i830_irq_wait {
321 int irq_seq;
322} drm_i830_irq_wait_t;
323
324/* 1.3: New ioctl to query kernel params:
325 */
326#define I830_PARAM_IRQ_ACTIVE 1
327
328typedef struct drm_i830_getparam {
329 int param;
330 int __user *value;
331} drm_i830_getparam_t;
332
333/* 1.3: New ioctl to set kernel params:
334 */
335#define I830_SETPARAM_USE_MI_BATCHBUFFER_START 1
336
337typedef struct drm_i830_setparam {
338 int param;
339 int value;
340} drm_i830_setparam_t;
341
342#endif /* _I830_DRM_H_ */
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
new file mode 100644
index 000000000000..05c66cf03a9e
--- /dev/null
+++ b/include/drm/i915_drm.h
@@ -0,0 +1,270 @@
1/*
2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 *
25 */
26
27#ifndef _I915_DRM_H_
28#define _I915_DRM_H_
29
30/* Please note that modifications to all structs defined here are
31 * subject to backwards-compatibility constraints.
32 */
33
34#include "drm.h"
35
36/* Each region is a minimum of 16k, and there are at most 255 of them.
37 */
38#define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
39 * of chars for next/prev indices */
40#define I915_LOG_MIN_TEX_REGION_SIZE 14
41
42typedef struct _drm_i915_init {
43 enum {
44 I915_INIT_DMA = 0x01,
45 I915_CLEANUP_DMA = 0x02,
46 I915_RESUME_DMA = 0x03
47 } func;
48 unsigned int mmio_offset;
49 int sarea_priv_offset;
50 unsigned int ring_start;
51 unsigned int ring_end;
52 unsigned int ring_size;
53 unsigned int front_offset;
54 unsigned int back_offset;
55 unsigned int depth_offset;
56 unsigned int w;
57 unsigned int h;
58 unsigned int pitch;
59 unsigned int pitch_bits;
60 unsigned int back_pitch;
61 unsigned int depth_pitch;
62 unsigned int cpp;
63 unsigned int chipset;
64} drm_i915_init_t;
65
66typedef struct _drm_i915_sarea {
67 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
68 int last_upload; /* last time texture was uploaded */
69 int last_enqueue; /* last time a buffer was enqueued */
70 int last_dispatch; /* age of the most recently dispatched buffer */
71 int ctxOwner; /* last context to upload state */
72 int texAge;
73 int pf_enabled; /* is pageflipping allowed? */
74 int pf_active;
75 int pf_current_page; /* which buffer is being displayed? */
76 int perf_boxes; /* performance boxes to be displayed */
77 int width, height; /* screen size in pixels */
78
79 drm_handle_t front_handle;
80 int front_offset;
81 int front_size;
82
83 drm_handle_t back_handle;
84 int back_offset;
85 int back_size;
86
87 drm_handle_t depth_handle;
88 int depth_offset;
89 int depth_size;
90
91 drm_handle_t tex_handle;
92 int tex_offset;
93 int tex_size;
94 int log_tex_granularity;
95 int pitch;
96 int rotation; /* 0, 90, 180 or 270 */
97 int rotated_offset;
98 int rotated_size;
99 int rotated_pitch;
100 int virtualX, virtualY;
101
102 unsigned int front_tiled;
103 unsigned int back_tiled;
104 unsigned int depth_tiled;
105 unsigned int rotated_tiled;
106 unsigned int rotated2_tiled;
107
108 int pipeA_x;
109 int pipeA_y;
110 int pipeA_w;
111 int pipeA_h;
112 int pipeB_x;
113 int pipeB_y;
114 int pipeB_w;
115 int pipeB_h;
116} drm_i915_sarea_t;
117
118/* Flags for perf_boxes
119 */
120#define I915_BOX_RING_EMPTY 0x1
121#define I915_BOX_FLIP 0x2
122#define I915_BOX_WAIT 0x4
123#define I915_BOX_TEXTURE_LOAD 0x8
124#define I915_BOX_LOST_CONTEXT 0x10
125
126/* I915 specific ioctls
127 * The device specific ioctl range is 0x40 to 0x79.
128 */
129#define DRM_I915_INIT 0x00
130#define DRM_I915_FLUSH 0x01
131#define DRM_I915_FLIP 0x02
132#define DRM_I915_BATCHBUFFER 0x03
133#define DRM_I915_IRQ_EMIT 0x04
134#define DRM_I915_IRQ_WAIT 0x05
135#define DRM_I915_GETPARAM 0x06
136#define DRM_I915_SETPARAM 0x07
137#define DRM_I915_ALLOC 0x08
138#define DRM_I915_FREE 0x09
139#define DRM_I915_INIT_HEAP 0x0a
140#define DRM_I915_CMDBUFFER 0x0b
141#define DRM_I915_DESTROY_HEAP 0x0c
142#define DRM_I915_SET_VBLANK_PIPE 0x0d
143#define DRM_I915_GET_VBLANK_PIPE 0x0e
144#define DRM_I915_VBLANK_SWAP 0x0f
145#define DRM_I915_HWS_ADDR 0x11
146
147#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
148#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
149#define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
150#define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
151#define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
152#define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
153#define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
154#define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
155#define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
156#define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
157#define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
158#define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
159#define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
160#define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
161#define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
162#define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
163
164/* Allow drivers to submit batchbuffers directly to hardware, relying
165 * on the security mechanisms provided by hardware.
166 */
167typedef struct _drm_i915_batchbuffer {
168 int start; /* agp offset */
169 int used; /* nr bytes in use */
170 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
171 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
172 int num_cliprects; /* mulitpass with multiple cliprects? */
173 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
174} drm_i915_batchbuffer_t;
175
176/* As above, but pass a pointer to userspace buffer which can be
177 * validated by the kernel prior to sending to hardware.
178 */
179typedef struct _drm_i915_cmdbuffer {
180 char __user *buf; /* pointer to userspace command buffer */
181 int sz; /* nr bytes in buf */
182 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
183 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
184 int num_cliprects; /* mulitpass with multiple cliprects? */
185 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
186} drm_i915_cmdbuffer_t;
187
188/* Userspace can request & wait on irq's:
189 */
190typedef struct drm_i915_irq_emit {
191 int __user *irq_seq;
192} drm_i915_irq_emit_t;
193
194typedef struct drm_i915_irq_wait {
195 int irq_seq;
196} drm_i915_irq_wait_t;
197
198/* Ioctl to query kernel params:
199 */
200#define I915_PARAM_IRQ_ACTIVE 1
201#define I915_PARAM_ALLOW_BATCHBUFFER 2
202#define I915_PARAM_LAST_DISPATCH 3
203
204typedef struct drm_i915_getparam {
205 int param;
206 int __user *value;
207} drm_i915_getparam_t;
208
209/* Ioctl to set kernel params:
210 */
211#define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
212#define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
213#define I915_SETPARAM_ALLOW_BATCHBUFFER 3
214
215typedef struct drm_i915_setparam {
216 int param;
217 int value;
218} drm_i915_setparam_t;
219
220/* A memory manager for regions of shared memory:
221 */
222#define I915_MEM_REGION_AGP 1
223
224typedef struct drm_i915_mem_alloc {
225 int region;
226 int alignment;
227 int size;
228 int __user *region_offset; /* offset from start of fb or agp */
229} drm_i915_mem_alloc_t;
230
231typedef struct drm_i915_mem_free {
232 int region;
233 int region_offset;
234} drm_i915_mem_free_t;
235
236typedef struct drm_i915_mem_init_heap {
237 int region;
238 int size;
239 int start;
240} drm_i915_mem_init_heap_t;
241
242/* Allow memory manager to be torn down and re-initialized (eg on
243 * rotate):
244 */
245typedef struct drm_i915_mem_destroy_heap {
246 int region;
247} drm_i915_mem_destroy_heap_t;
248
249/* Allow X server to configure which pipes to monitor for vblank signals
250 */
251#define DRM_I915_VBLANK_PIPE_A 1
252#define DRM_I915_VBLANK_PIPE_B 2
253
254typedef struct drm_i915_vblank_pipe {
255 int pipe;
256} drm_i915_vblank_pipe_t;
257
258/* Schedule buffer swap at given vertical blank:
259 */
260typedef struct drm_i915_vblank_swap {
261 drm_drawable_t drawable;
262 enum drm_vblank_seq_type seqtype;
263 unsigned int sequence;
264} drm_i915_vblank_swap_t;
265
266typedef struct drm_i915_hws_addr {
267 uint64_t addr;
268} drm_i915_hws_addr_t;
269
270#endif /* _I915_DRM_H_ */
diff --git a/include/drm/mga_drm.h b/include/drm/mga_drm.h
new file mode 100644
index 000000000000..944b50a5ff24
--- /dev/null
+++ b/include/drm/mga_drm.h
@@ -0,0 +1,417 @@
1/* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 *
31 * Rewritten by:
32 * Gareth Hughes <gareth@valinux.com>
33 */
34
35#ifndef __MGA_DRM_H__
36#define __MGA_DRM_H__
37
38/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the Xserver file (mga_sarea.h)
40 */
41
42#ifndef __MGA_SAREA_DEFINES__
43#define __MGA_SAREA_DEFINES__
44
45/* WARP pipe flags
46 */
47#define MGA_F 0x1 /* fog */
48#define MGA_A 0x2 /* alpha */
49#define MGA_S 0x4 /* specular */
50#define MGA_T2 0x8 /* multitexture */
51
52#define MGA_WARP_TGZ 0
53#define MGA_WARP_TGZF (MGA_F)
54#define MGA_WARP_TGZA (MGA_A)
55#define MGA_WARP_TGZAF (MGA_F|MGA_A)
56#define MGA_WARP_TGZS (MGA_S)
57#define MGA_WARP_TGZSF (MGA_S|MGA_F)
58#define MGA_WARP_TGZSA (MGA_S|MGA_A)
59#define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
60#define MGA_WARP_T2GZ (MGA_T2)
61#define MGA_WARP_T2GZF (MGA_T2|MGA_F)
62#define MGA_WARP_T2GZA (MGA_T2|MGA_A)
63#define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
64#define MGA_WARP_T2GZS (MGA_T2|MGA_S)
65#define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
66#define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
67#define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
68
69#define MGA_MAX_G200_PIPES 8 /* no multitex */
70#define MGA_MAX_G400_PIPES 16
71#define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
72#define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
73
74#define MGA_CARD_TYPE_G200 1
75#define MGA_CARD_TYPE_G400 2
76#define MGA_CARD_TYPE_G450 3 /* not currently used */
77#define MGA_CARD_TYPE_G550 4
78
79#define MGA_FRONT 0x1
80#define MGA_BACK 0x2
81#define MGA_DEPTH 0x4
82
83/* What needs to be changed for the current vertex dma buffer?
84 */
85#define MGA_UPLOAD_CONTEXT 0x1
86#define MGA_UPLOAD_TEX0 0x2
87#define MGA_UPLOAD_TEX1 0x4
88#define MGA_UPLOAD_PIPE 0x8
89#define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
90#define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
91#define MGA_UPLOAD_2D 0x40
92#define MGA_WAIT_AGE 0x80 /* handled client-side */
93#define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
94#if 0
95#define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
96 quiescent */
97#endif
98
99/* 32 buffers of 64k each, total 2 meg.
100 */
101#define MGA_BUFFER_SIZE (1 << 16)
102#define MGA_NUM_BUFFERS 128
103
104/* Keep these small for testing.
105 */
106#define MGA_NR_SAREA_CLIPRECTS 8
107
108/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
109 * regions, subject to a minimum region size of (1<<16) == 64k.
110 *
111 * Clients may subdivide regions internally, but when sharing between
112 * clients, the region size is the minimum granularity.
113 */
114
115#define MGA_CARD_HEAP 0
116#define MGA_AGP_HEAP 1
117#define MGA_NR_TEX_HEAPS 2
118#define MGA_NR_TEX_REGIONS 16
119#define MGA_LOG_MIN_TEX_REGION_SIZE 16
120
121#define DRM_MGA_IDLE_RETRY 2048
122
123#endif /* __MGA_SAREA_DEFINES__ */
124
125/* Setup registers for 3D context
126 */
127typedef struct {
128 unsigned int dstorg;
129 unsigned int maccess;
130 unsigned int plnwt;
131 unsigned int dwgctl;
132 unsigned int alphactrl;
133 unsigned int fogcolor;
134 unsigned int wflag;
135 unsigned int tdualstage0;
136 unsigned int tdualstage1;
137 unsigned int fcol;
138 unsigned int stencil;
139 unsigned int stencilctl;
140} drm_mga_context_regs_t;
141
142/* Setup registers for 2D, X server
143 */
144typedef struct {
145 unsigned int pitch;
146} drm_mga_server_regs_t;
147
148/* Setup registers for each texture unit
149 */
150typedef struct {
151 unsigned int texctl;
152 unsigned int texctl2;
153 unsigned int texfilter;
154 unsigned int texbordercol;
155 unsigned int texorg;
156 unsigned int texwidth;
157 unsigned int texheight;
158 unsigned int texorg1;
159 unsigned int texorg2;
160 unsigned int texorg3;
161 unsigned int texorg4;
162} drm_mga_texture_regs_t;
163
164/* General aging mechanism
165 */
166typedef struct {
167 unsigned int head; /* Position of head pointer */
168 unsigned int wrap; /* Primary DMA wrap count */
169} drm_mga_age_t;
170
171typedef struct _drm_mga_sarea {
172 /* The channel for communication of state information to the kernel
173 * on firing a vertex dma buffer.
174 */
175 drm_mga_context_regs_t context_state;
176 drm_mga_server_regs_t server_state;
177 drm_mga_texture_regs_t tex_state[2];
178 unsigned int warp_pipe;
179 unsigned int dirty;
180 unsigned int vertsize;
181
182 /* The current cliprects, or a subset thereof.
183 */
184 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
185 unsigned int nbox;
186
187 /* Information about the most recently used 3d drawable. The
188 * client fills in the req_* fields, the server fills in the
189 * exported_ fields and puts the cliprects into boxes, above.
190 *
191 * The client clears the exported_drawable field before
192 * clobbering the boxes data.
193 */
194 unsigned int req_drawable; /* the X drawable id */
195 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
196
197 unsigned int exported_drawable;
198 unsigned int exported_index;
199 unsigned int exported_stamp;
200 unsigned int exported_buffers;
201 unsigned int exported_nfront;
202 unsigned int exported_nback;
203 int exported_back_x, exported_front_x, exported_w;
204 int exported_back_y, exported_front_y, exported_h;
205 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
206
207 /* Counters for aging textures and for client-side throttling.
208 */
209 unsigned int status[4];
210 unsigned int last_wrap;
211
212 drm_mga_age_t last_frame;
213 unsigned int last_enqueue; /* last time a buffer was enqueued */
214 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
215 unsigned int last_quiescent; /* */
216
217 /* LRU lists for texture memory in agp space and on the card.
218 */
219 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
220 unsigned int texAge[MGA_NR_TEX_HEAPS];
221
222 /* Mechanism to validate card state.
223 */
224 int ctxOwner;
225} drm_mga_sarea_t;
226
227/* MGA specific ioctls
228 * The device specific ioctl range is 0x40 to 0x79.
229 */
230#define DRM_MGA_INIT 0x00
231#define DRM_MGA_FLUSH 0x01
232#define DRM_MGA_RESET 0x02
233#define DRM_MGA_SWAP 0x03
234#define DRM_MGA_CLEAR 0x04
235#define DRM_MGA_VERTEX 0x05
236#define DRM_MGA_INDICES 0x06
237#define DRM_MGA_ILOAD 0x07
238#define DRM_MGA_BLIT 0x08
239#define DRM_MGA_GETPARAM 0x09
240
241/* 3.2:
242 * ioctls for operating on fences.
243 */
244#define DRM_MGA_SET_FENCE 0x0a
245#define DRM_MGA_WAIT_FENCE 0x0b
246#define DRM_MGA_DMA_BOOTSTRAP 0x0c
247
248#define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
249#define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
250#define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
251#define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
252#define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
253#define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
254#define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
255#define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
256#define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
257#define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
258#define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
259#define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
260#define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
261
262typedef struct _drm_mga_warp_index {
263 int installed;
264 unsigned long phys_addr;
265 int size;
266} drm_mga_warp_index_t;
267
268typedef struct drm_mga_init {
269 enum {
270 MGA_INIT_DMA = 0x01,
271 MGA_CLEANUP_DMA = 0x02
272 } func;
273
274 unsigned long sarea_priv_offset;
275
276 int chipset;
277 int sgram;
278
279 unsigned int maccess;
280
281 unsigned int fb_cpp;
282 unsigned int front_offset, front_pitch;
283 unsigned int back_offset, back_pitch;
284
285 unsigned int depth_cpp;
286 unsigned int depth_offset, depth_pitch;
287
288 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
289 unsigned int texture_size[MGA_NR_TEX_HEAPS];
290
291 unsigned long fb_offset;
292 unsigned long mmio_offset;
293 unsigned long status_offset;
294 unsigned long warp_offset;
295 unsigned long primary_offset;
296 unsigned long buffers_offset;
297} drm_mga_init_t;
298
299typedef struct drm_mga_dma_bootstrap {
300 /**
301 * \name AGP texture region
302 *
303 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
304 * be filled in with the actual AGP texture settings.
305 *
306 * \warning
307 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
308 * is zero, it means that PCI memory (most likely through the use of
309 * an IOMMU) is being used for "AGP" textures.
310 */
311 /*@{ */
312 unsigned long texture_handle; /**< Handle used to map AGP textures. */
313 uint32_t texture_size; /**< Size of the AGP texture region. */
314 /*@} */
315
316 /**
317 * Requested size of the primary DMA region.
318 *
319 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
320 * filled in with the actual AGP mode. If AGP was not available
321 */
322 uint32_t primary_size;
323
324 /**
325 * Requested number of secondary DMA buffers.
326 *
327 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
328 * filled in with the actual number of secondary DMA buffers
329 * allocated. Particularly when PCI DMA is used, this may be
330 * (subtantially) less than the number requested.
331 */
332 uint32_t secondary_bin_count;
333
334 /**
335 * Requested size of each secondary DMA buffer.
336 *
337 * While the kernel \b is free to reduce
338 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
339 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
340 */
341 uint32_t secondary_bin_size;
342
343 /**
344 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
345 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
346 * zero, it means that PCI DMA should be used, even if AGP is
347 * possible.
348 *
349 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
350 * filled in with the actual AGP mode. If AGP was not available
351 * (i.e., PCI DMA was used), this value will be zero.
352 */
353 uint32_t agp_mode;
354
355 /**
356 * Desired AGP GART size, measured in megabytes.
357 */
358 uint8_t agp_size;
359} drm_mga_dma_bootstrap_t;
360
361typedef struct drm_mga_clear {
362 unsigned int flags;
363 unsigned int clear_color;
364 unsigned int clear_depth;
365 unsigned int color_mask;
366 unsigned int depth_mask;
367} drm_mga_clear_t;
368
369typedef struct drm_mga_vertex {
370 int idx; /* buffer to queue */
371 int used; /* bytes in use */
372 int discard; /* client finished with buffer? */
373} drm_mga_vertex_t;
374
375typedef struct drm_mga_indices {
376 int idx; /* buffer to queue */
377 unsigned int start;
378 unsigned int end;
379 int discard; /* client finished with buffer? */
380} drm_mga_indices_t;
381
382typedef struct drm_mga_iload {
383 int idx;
384 unsigned int dstorg;
385 unsigned int length;
386} drm_mga_iload_t;
387
388typedef struct _drm_mga_blit {
389 unsigned int planemask;
390 unsigned int srcorg;
391 unsigned int dstorg;
392 int src_pitch, dst_pitch;
393 int delta_sx, delta_sy;
394 int delta_dx, delta_dy;
395 int height, ydir; /* flip image vertically */
396 int source_pitch, dest_pitch;
397} drm_mga_blit_t;
398
399/* 3.1: An ioctl to get parameters that aren't available to the 3d
400 * client any other way.
401 */
402#define MGA_PARAM_IRQ_NR 1
403
404/* 3.2: Query the actual card type. The DDX only distinguishes between
405 * G200 chips and non-G200 chips, which it calls G400. It turns out that
406 * there are some very sublte differences between the G4x0 chips and the G550
407 * chips. Using this parameter query, a client-side driver can detect the
408 * difference between a G4x0 and a G550.
409 */
410#define MGA_PARAM_CARD_TYPE 2
411
412typedef struct drm_mga_getparam {
413 int param;
414 void __user *value;
415} drm_mga_getparam_t;
416
417#endif
diff --git a/include/drm/r128_drm.h b/include/drm/r128_drm.h
new file mode 100644
index 000000000000..8d8878b55f55
--- /dev/null
+++ b/include/drm/r128_drm.h
@@ -0,0 +1,326 @@
1/* r128_drm.h -- Public header for the r128 driver -*- linux-c -*-
2 * Created: Wed Apr 5 19:24:19 2000 by kevin@precisioninsight.com
3 */
4/*
5 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
6 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
7 * All rights reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Gareth Hughes <gareth@valinux.com>
30 * Kevin E. Martin <martin@valinux.com>
31 */
32
33#ifndef __R128_DRM_H__
34#define __R128_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (r128_sarea.h)
38 */
39#ifndef __R128_SAREA_DEFINES__
40#define __R128_SAREA_DEFINES__
41
42/* What needs to be changed for the current vertex buffer?
43 */
44#define R128_UPLOAD_CONTEXT 0x001
45#define R128_UPLOAD_SETUP 0x002
46#define R128_UPLOAD_TEX0 0x004
47#define R128_UPLOAD_TEX1 0x008
48#define R128_UPLOAD_TEX0IMAGES 0x010
49#define R128_UPLOAD_TEX1IMAGES 0x020
50#define R128_UPLOAD_CORE 0x040
51#define R128_UPLOAD_MASKS 0x080
52#define R128_UPLOAD_WINDOW 0x100
53#define R128_UPLOAD_CLIPRECTS 0x200 /* handled client-side */
54#define R128_REQUIRE_QUIESCENCE 0x400
55#define R128_UPLOAD_ALL 0x7ff
56
57#define R128_FRONT 0x1
58#define R128_BACK 0x2
59#define R128_DEPTH 0x4
60
61/* Primitive types
62 */
63#define R128_POINTS 0x1
64#define R128_LINES 0x2
65#define R128_LINE_STRIP 0x3
66#define R128_TRIANGLES 0x4
67#define R128_TRIANGLE_FAN 0x5
68#define R128_TRIANGLE_STRIP 0x6
69
70/* Vertex/indirect buffer size
71 */
72#define R128_BUFFER_SIZE 16384
73
74/* Byte offsets for indirect buffer data
75 */
76#define R128_INDEX_PRIM_OFFSET 20
77#define R128_HOSTDATA_BLIT_OFFSET 32
78
79/* Keep these small for testing.
80 */
81#define R128_NR_SAREA_CLIPRECTS 12
82
83/* There are 2 heaps (local/AGP). Each region within a heap is a
84 * minimum of 64k, and there are at most 64 of them per heap.
85 */
86#define R128_LOCAL_TEX_HEAP 0
87#define R128_AGP_TEX_HEAP 1
88#define R128_NR_TEX_HEAPS 2
89#define R128_NR_TEX_REGIONS 64
90#define R128_LOG_TEX_GRANULARITY 16
91
92#define R128_NR_CONTEXT_REGS 12
93
94#define R128_MAX_TEXTURE_LEVELS 11
95#define R128_MAX_TEXTURE_UNITS 2
96
97#endif /* __R128_SAREA_DEFINES__ */
98
99typedef struct {
100 /* Context state - can be written in one large chunk */
101 unsigned int dst_pitch_offset_c;
102 unsigned int dp_gui_master_cntl_c;
103 unsigned int sc_top_left_c;
104 unsigned int sc_bottom_right_c;
105 unsigned int z_offset_c;
106 unsigned int z_pitch_c;
107 unsigned int z_sten_cntl_c;
108 unsigned int tex_cntl_c;
109 unsigned int misc_3d_state_cntl_reg;
110 unsigned int texture_clr_cmp_clr_c;
111 unsigned int texture_clr_cmp_msk_c;
112 unsigned int fog_color_c;
113
114 /* Texture state */
115 unsigned int tex_size_pitch_c;
116 unsigned int constant_color_c;
117
118 /* Setup state */
119 unsigned int pm4_vc_fpu_setup;
120 unsigned int setup_cntl;
121
122 /* Mask state */
123 unsigned int dp_write_mask;
124 unsigned int sten_ref_mask_c;
125 unsigned int plane_3d_mask_c;
126
127 /* Window state */
128 unsigned int window_xy_offset;
129
130 /* Core state */
131 unsigned int scale_3d_cntl;
132} drm_r128_context_regs_t;
133
134/* Setup registers for each texture unit
135 */
136typedef struct {
137 unsigned int tex_cntl;
138 unsigned int tex_combine_cntl;
139 unsigned int tex_size_pitch;
140 unsigned int tex_offset[R128_MAX_TEXTURE_LEVELS];
141 unsigned int tex_border_color;
142} drm_r128_texture_regs_t;
143
144typedef struct drm_r128_sarea {
145 /* The channel for communication of state information to the kernel
146 * on firing a vertex buffer.
147 */
148 drm_r128_context_regs_t context_state;
149 drm_r128_texture_regs_t tex_state[R128_MAX_TEXTURE_UNITS];
150 unsigned int dirty;
151 unsigned int vertsize;
152 unsigned int vc_format;
153
154 /* The current cliprects, or a subset thereof.
155 */
156 struct drm_clip_rect boxes[R128_NR_SAREA_CLIPRECTS];
157 unsigned int nbox;
158
159 /* Counters for client-side throttling of rendering clients.
160 */
161 unsigned int last_frame;
162 unsigned int last_dispatch;
163
164 struct drm_tex_region tex_list[R128_NR_TEX_HEAPS][R128_NR_TEX_REGIONS + 1];
165 unsigned int tex_age[R128_NR_TEX_HEAPS];
166 int ctx_owner;
167 int pfAllowPageFlip; /* number of 3d windows (0,1,2 or more) */
168 int pfCurrentPage; /* which buffer is being displayed? */
169} drm_r128_sarea_t;
170
171/* WARNING: If you change any of these defines, make sure to change the
172 * defines in the Xserver file (xf86drmR128.h)
173 */
174
175/* Rage 128 specific ioctls
176 * The device specific ioctl range is 0x40 to 0x79.
177 */
178#define DRM_R128_INIT 0x00
179#define DRM_R128_CCE_START 0x01
180#define DRM_R128_CCE_STOP 0x02
181#define DRM_R128_CCE_RESET 0x03
182#define DRM_R128_CCE_IDLE 0x04
183/* 0x05 not used */
184#define DRM_R128_RESET 0x06
185#define DRM_R128_SWAP 0x07
186#define DRM_R128_CLEAR 0x08
187#define DRM_R128_VERTEX 0x09
188#define DRM_R128_INDICES 0x0a
189#define DRM_R128_BLIT 0x0b
190#define DRM_R128_DEPTH 0x0c
191#define DRM_R128_STIPPLE 0x0d
192/* 0x0e not used */
193#define DRM_R128_INDIRECT 0x0f
194#define DRM_R128_FULLSCREEN 0x10
195#define DRM_R128_CLEAR2 0x11
196#define DRM_R128_GETPARAM 0x12
197#define DRM_R128_FLIP 0x13
198
199#define DRM_IOCTL_R128_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INIT, drm_r128_init_t)
200#define DRM_IOCTL_R128_CCE_START DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_START)
201#define DRM_IOCTL_R128_CCE_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CCE_STOP, drm_r128_cce_stop_t)
202#define DRM_IOCTL_R128_CCE_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_RESET)
203#define DRM_IOCTL_R128_CCE_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_R128_CCE_IDLE)
204/* 0x05 not used */
205#define DRM_IOCTL_R128_RESET DRM_IO( DRM_COMMAND_BASE + DRM_R128_RESET)
206#define DRM_IOCTL_R128_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_R128_SWAP)
207#define DRM_IOCTL_R128_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR, drm_r128_clear_t)
208#define DRM_IOCTL_R128_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_R128_VERTEX, drm_r128_vertex_t)
209#define DRM_IOCTL_R128_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_R128_INDICES, drm_r128_indices_t)
210#define DRM_IOCTL_R128_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_R128_BLIT, drm_r128_blit_t)
211#define DRM_IOCTL_R128_DEPTH DRM_IOW( DRM_COMMAND_BASE + DRM_R128_DEPTH, drm_r128_depth_t)
212#define DRM_IOCTL_R128_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_R128_STIPPLE, drm_r128_stipple_t)
213/* 0x0e not used */
214#define DRM_IOCTL_R128_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_R128_INDIRECT, drm_r128_indirect_t)
215#define DRM_IOCTL_R128_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_R128_FULLSCREEN, drm_r128_fullscreen_t)
216#define DRM_IOCTL_R128_CLEAR2 DRM_IOW( DRM_COMMAND_BASE + DRM_R128_CLEAR2, drm_r128_clear2_t)
217#define DRM_IOCTL_R128_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_R128_GETPARAM, drm_r128_getparam_t)
218#define DRM_IOCTL_R128_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_R128_FLIP)
219
220typedef struct drm_r128_init {
221 enum {
222 R128_INIT_CCE = 0x01,
223 R128_CLEANUP_CCE = 0x02
224 } func;
225 unsigned long sarea_priv_offset;
226 int is_pci;
227 int cce_mode;
228 int cce_secure;
229 int ring_size;
230 int usec_timeout;
231
232 unsigned int fb_bpp;
233 unsigned int front_offset, front_pitch;
234 unsigned int back_offset, back_pitch;
235 unsigned int depth_bpp;
236 unsigned int depth_offset, depth_pitch;
237 unsigned int span_offset;
238
239 unsigned long fb_offset;
240 unsigned long mmio_offset;
241 unsigned long ring_offset;
242 unsigned long ring_rptr_offset;
243 unsigned long buffers_offset;
244 unsigned long agp_textures_offset;
245} drm_r128_init_t;
246
247typedef struct drm_r128_cce_stop {
248 int flush;
249 int idle;
250} drm_r128_cce_stop_t;
251
252typedef struct drm_r128_clear {
253 unsigned int flags;
254 unsigned int clear_color;
255 unsigned int clear_depth;
256 unsigned int color_mask;
257 unsigned int depth_mask;
258} drm_r128_clear_t;
259
260typedef struct drm_r128_vertex {
261 int prim;
262 int idx; /* Index of vertex buffer */
263 int count; /* Number of vertices in buffer */
264 int discard; /* Client finished with buffer? */
265} drm_r128_vertex_t;
266
267typedef struct drm_r128_indices {
268 int prim;
269 int idx;
270 int start;
271 int end;
272 int discard; /* Client finished with buffer? */
273} drm_r128_indices_t;
274
275typedef struct drm_r128_blit {
276 int idx;
277 int pitch;
278 int offset;
279 int format;
280 unsigned short x, y;
281 unsigned short width, height;
282} drm_r128_blit_t;
283
284typedef struct drm_r128_depth {
285 enum {
286 R128_WRITE_SPAN = 0x01,
287 R128_WRITE_PIXELS = 0x02,
288 R128_READ_SPAN = 0x03,
289 R128_READ_PIXELS = 0x04
290 } func;
291 int n;
292 int __user *x;
293 int __user *y;
294 unsigned int __user *buffer;
295 unsigned char __user *mask;
296} drm_r128_depth_t;
297
298typedef struct drm_r128_stipple {
299 unsigned int __user *mask;
300} drm_r128_stipple_t;
301
302typedef struct drm_r128_indirect {
303 int idx;
304 int start;
305 int end;
306 int discard;
307} drm_r128_indirect_t;
308
309typedef struct drm_r128_fullscreen {
310 enum {
311 R128_INIT_FULLSCREEN = 0x01,
312 R128_CLEANUP_FULLSCREEN = 0x02
313 } func;
314} drm_r128_fullscreen_t;
315
316/* 2.3: An ioctl to get parameters that aren't available to the 3d
317 * client any other way.
318 */
319#define R128_PARAM_IRQ_NR 1
320
321typedef struct drm_r128_getparam {
322 int param;
323 void __user *value;
324} drm_r128_getparam_t;
325
326#endif
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
new file mode 100644
index 000000000000..73ff51f12311
--- /dev/null
+++ b/include/drm/radeon_drm.h
@@ -0,0 +1,749 @@
1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 */
32
33#ifndef __RADEON_DRM_H__
34#define __RADEON_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the X server file (radeon_sarea.h)
38 */
39#ifndef __RADEON_SAREA_DEFINES__
40#define __RADEON_SAREA_DEFINES__
41
42/* Old style state flags, required for sarea interface (1.1 and 1.2
43 * clears) and 1.2 drm_vertex2 ioctl.
44 */
45#define RADEON_UPLOAD_CONTEXT 0x00000001
46#define RADEON_UPLOAD_VERTFMT 0x00000002
47#define RADEON_UPLOAD_LINE 0x00000004
48#define RADEON_UPLOAD_BUMPMAP 0x00000008
49#define RADEON_UPLOAD_MASKS 0x00000010
50#define RADEON_UPLOAD_VIEWPORT 0x00000020
51#define RADEON_UPLOAD_SETUP 0x00000040
52#define RADEON_UPLOAD_TCL 0x00000080
53#define RADEON_UPLOAD_MISC 0x00000100
54#define RADEON_UPLOAD_TEX0 0x00000200
55#define RADEON_UPLOAD_TEX1 0x00000400
56#define RADEON_UPLOAD_TEX2 0x00000800
57#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
58#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
59#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
60#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
61#define RADEON_REQUIRE_QUIESCENCE 0x00010000
62#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
63#define RADEON_UPLOAD_ALL 0x003effff
64#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
65
66/* New style per-packet identifiers for use in cmd_buffer ioctl with
67 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
68 * state bits and the packet size:
69 */
70#define RADEON_EMIT_PP_MISC 0 /* context/7 */
71#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
72#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
73#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
74#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
75#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
76#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
77#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
78#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
79#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
80#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
81#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
82#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
83#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
84#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
85#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
86#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
87#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
88#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
89#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
90#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
91#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
92#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
93#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
94#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
95#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
96#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
97#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
98#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
99#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
100#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
101#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
102#define R200_EMIT_VAP_CTL 32 /* vap/1 */
103#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
104#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
105#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
106#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
107#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
108#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
109#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
110#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
111#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
112#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
113#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
114#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
115#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
116#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
117#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
118#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
119#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
120#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
121#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
122#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
123#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
124#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
125#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
126#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
127#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
128#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
129#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
130#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
131#define R200_EMIT_PP_CUBIC_FACES_0 61
132#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
133#define R200_EMIT_PP_CUBIC_FACES_1 63
134#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
135#define R200_EMIT_PP_CUBIC_FACES_2 65
136#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
137#define R200_EMIT_PP_CUBIC_FACES_3 67
138#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
139#define R200_EMIT_PP_CUBIC_FACES_4 69
140#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
141#define R200_EMIT_PP_CUBIC_FACES_5 71
142#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
143#define RADEON_EMIT_PP_TEX_SIZE_0 73
144#define RADEON_EMIT_PP_TEX_SIZE_1 74
145#define RADEON_EMIT_PP_TEX_SIZE_2 75
146#define R200_EMIT_RB3D_BLENDCOLOR 76
147#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
148#define RADEON_EMIT_PP_CUBIC_FACES_0 78
149#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0 79
150#define RADEON_EMIT_PP_CUBIC_FACES_1 80
151#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1 81
152#define RADEON_EMIT_PP_CUBIC_FACES_2 82
153#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2 83
154#define R200_EMIT_PP_TRI_PERF_CNTL 84
155#define R200_EMIT_PP_AFS_0 85
156#define R200_EMIT_PP_AFS_1 86
157#define R200_EMIT_ATF_TFACTOR 87
158#define R200_EMIT_PP_TXCTLALL_0 88
159#define R200_EMIT_PP_TXCTLALL_1 89
160#define R200_EMIT_PP_TXCTLALL_2 90
161#define R200_EMIT_PP_TXCTLALL_3 91
162#define R200_EMIT_PP_TXCTLALL_4 92
163#define R200_EMIT_PP_TXCTLALL_5 93
164#define R200_EMIT_VAP_PVS_CNTL 94
165#define RADEON_MAX_STATE_PACKETS 95
166
167/* Commands understood by cmd_buffer ioctl. More can be added but
168 * obviously these can't be removed or changed:
169 */
170#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
171#define RADEON_CMD_SCALARS 2 /* emit scalar data */
172#define RADEON_CMD_VECTORS 3 /* emit vector data */
173#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
174#define RADEON_CMD_PACKET3 5 /* emit hw packet */
175#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
176#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
177#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
178 * doesn't make the cpu wait, just
179 * the graphics hardware */
180#define RADEON_CMD_VECLINEAR 9 /* another r200 stopgap */
181
182typedef union {
183 int i;
184 struct {
185 unsigned char cmd_type, pad0, pad1, pad2;
186 } header;
187 struct {
188 unsigned char cmd_type, packet_id, pad0, pad1;
189 } packet;
190 struct {
191 unsigned char cmd_type, offset, stride, count;
192 } scalars;
193 struct {
194 unsigned char cmd_type, offset, stride, count;
195 } vectors;
196 struct {
197 unsigned char cmd_type, addr_lo, addr_hi, count;
198 } veclinear;
199 struct {
200 unsigned char cmd_type, buf_idx, pad0, pad1;
201 } dma;
202 struct {
203 unsigned char cmd_type, flags, pad0, pad1;
204 } wait;
205} drm_radeon_cmd_header_t;
206
207#define RADEON_WAIT_2D 0x1
208#define RADEON_WAIT_3D 0x2
209
210/* Allowed parameters for R300_CMD_PACKET3
211 */
212#define R300_CMD_PACKET3_CLEAR 0
213#define R300_CMD_PACKET3_RAW 1
214
215/* Commands understood by cmd_buffer ioctl for R300.
216 * The interface has not been stabilized, so some of these may be removed
217 * and eventually reordered before stabilization.
218 */
219#define R300_CMD_PACKET0 1
220#define R300_CMD_VPU 2 /* emit vertex program upload */
221#define R300_CMD_PACKET3 3 /* emit a packet3 */
222#define R300_CMD_END3D 4 /* emit sequence ending 3d rendering */
223#define R300_CMD_CP_DELAY 5
224#define R300_CMD_DMA_DISCARD 6
225#define R300_CMD_WAIT 7
226# define R300_WAIT_2D 0x1
227# define R300_WAIT_3D 0x2
228/* these two defines are DOING IT WRONG - however
229 * we have userspace which relies on using these.
230 * The wait interface is backwards compat new
231 * code should use the NEW_WAIT defines below
232 * THESE ARE NOT BIT FIELDS
233 */
234# define R300_WAIT_2D_CLEAN 0x3
235# define R300_WAIT_3D_CLEAN 0x4
236
237# define R300_NEW_WAIT_2D_3D 0x3
238# define R300_NEW_WAIT_2D_2D_CLEAN 0x4
239# define R300_NEW_WAIT_3D_3D_CLEAN 0x6
240# define R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN 0x8
241
242#define R300_CMD_SCRATCH 8
243#define R300_CMD_R500FP 9
244
245typedef union {
246 unsigned int u;
247 struct {
248 unsigned char cmd_type, pad0, pad1, pad2;
249 } header;
250 struct {
251 unsigned char cmd_type, count, reglo, reghi;
252 } packet0;
253 struct {
254 unsigned char cmd_type, count, adrlo, adrhi;
255 } vpu;
256 struct {
257 unsigned char cmd_type, packet, pad0, pad1;
258 } packet3;
259 struct {
260 unsigned char cmd_type, packet;
261 unsigned short count; /* amount of packet2 to emit */
262 } delay;
263 struct {
264 unsigned char cmd_type, buf_idx, pad0, pad1;
265 } dma;
266 struct {
267 unsigned char cmd_type, flags, pad0, pad1;
268 } wait;
269 struct {
270 unsigned char cmd_type, reg, n_bufs, flags;
271 } scratch;
272 struct {
273 unsigned char cmd_type, count, adrlo, adrhi_flags;
274 } r500fp;
275} drm_r300_cmd_header_t;
276
277#define RADEON_FRONT 0x1
278#define RADEON_BACK 0x2
279#define RADEON_DEPTH 0x4
280#define RADEON_STENCIL 0x8
281#define RADEON_CLEAR_FASTZ 0x80000000
282#define RADEON_USE_HIERZ 0x40000000
283#define RADEON_USE_COMP_ZBUF 0x20000000
284
285#define R500FP_CONSTANT_TYPE (1 << 1)
286#define R500FP_CONSTANT_CLAMP (1 << 2)
287
288/* Primitive types
289 */
290#define RADEON_POINTS 0x1
291#define RADEON_LINES 0x2
292#define RADEON_LINE_STRIP 0x3
293#define RADEON_TRIANGLES 0x4
294#define RADEON_TRIANGLE_FAN 0x5
295#define RADEON_TRIANGLE_STRIP 0x6
296
297/* Vertex/indirect buffer size
298 */
299#define RADEON_BUFFER_SIZE 65536
300
301/* Byte offsets for indirect buffer data
302 */
303#define RADEON_INDEX_PRIM_OFFSET 20
304
305#define RADEON_SCRATCH_REG_OFFSET 32
306
307#define RADEON_NR_SAREA_CLIPRECTS 12
308
309/* There are 2 heaps (local/GART). Each region within a heap is a
310 * minimum of 64k, and there are at most 64 of them per heap.
311 */
312#define RADEON_LOCAL_TEX_HEAP 0
313#define RADEON_GART_TEX_HEAP 1
314#define RADEON_NR_TEX_HEAPS 2
315#define RADEON_NR_TEX_REGIONS 64
316#define RADEON_LOG_TEX_GRANULARITY 16
317
318#define RADEON_MAX_TEXTURE_LEVELS 12
319#define RADEON_MAX_TEXTURE_UNITS 3
320
321#define RADEON_MAX_SURFACES 8
322
323/* Blits have strict offset rules. All blit offset must be aligned on
324 * a 1K-byte boundary.
325 */
326#define RADEON_OFFSET_SHIFT 10
327#define RADEON_OFFSET_ALIGN (1 << RADEON_OFFSET_SHIFT)
328#define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
329
330#endif /* __RADEON_SAREA_DEFINES__ */
331
332typedef struct {
333 unsigned int red;
334 unsigned int green;
335 unsigned int blue;
336 unsigned int alpha;
337} radeon_color_regs_t;
338
339typedef struct {
340 /* Context state */
341 unsigned int pp_misc; /* 0x1c14 */
342 unsigned int pp_fog_color;
343 unsigned int re_solid_color;
344 unsigned int rb3d_blendcntl;
345 unsigned int rb3d_depthoffset;
346 unsigned int rb3d_depthpitch;
347 unsigned int rb3d_zstencilcntl;
348
349 unsigned int pp_cntl; /* 0x1c38 */
350 unsigned int rb3d_cntl;
351 unsigned int rb3d_coloroffset;
352 unsigned int re_width_height;
353 unsigned int rb3d_colorpitch;
354 unsigned int se_cntl;
355
356 /* Vertex format state */
357 unsigned int se_coord_fmt; /* 0x1c50 */
358
359 /* Line state */
360 unsigned int re_line_pattern; /* 0x1cd0 */
361 unsigned int re_line_state;
362
363 unsigned int se_line_width; /* 0x1db8 */
364
365 /* Bumpmap state */
366 unsigned int pp_lum_matrix; /* 0x1d00 */
367
368 unsigned int pp_rot_matrix_0; /* 0x1d58 */
369 unsigned int pp_rot_matrix_1;
370
371 /* Mask state */
372 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
373 unsigned int rb3d_ropcntl;
374 unsigned int rb3d_planemask;
375
376 /* Viewport state */
377 unsigned int se_vport_xscale; /* 0x1d98 */
378 unsigned int se_vport_xoffset;
379 unsigned int se_vport_yscale;
380 unsigned int se_vport_yoffset;
381 unsigned int se_vport_zscale;
382 unsigned int se_vport_zoffset;
383
384 /* Setup state */
385 unsigned int se_cntl_status; /* 0x2140 */
386
387 /* Misc state */
388 unsigned int re_top_left; /* 0x26c0 */
389 unsigned int re_misc;
390} drm_radeon_context_regs_t;
391
392typedef struct {
393 /* Zbias state */
394 unsigned int se_zbias_factor; /* 0x1dac */
395 unsigned int se_zbias_constant;
396} drm_radeon_context2_regs_t;
397
398/* Setup registers for each texture unit
399 */
400typedef struct {
401 unsigned int pp_txfilter;
402 unsigned int pp_txformat;
403 unsigned int pp_txoffset;
404 unsigned int pp_txcblend;
405 unsigned int pp_txablend;
406 unsigned int pp_tfactor;
407 unsigned int pp_border_color;
408} drm_radeon_texture_regs_t;
409
410typedef struct {
411 unsigned int start;
412 unsigned int finish;
413 unsigned int prim:8;
414 unsigned int stateidx:8;
415 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
416 unsigned int vc_format; /* vertex format */
417} drm_radeon_prim_t;
418
419typedef struct {
420 drm_radeon_context_regs_t context;
421 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
422 drm_radeon_context2_regs_t context2;
423 unsigned int dirty;
424} drm_radeon_state_t;
425
426typedef struct {
427 /* The channel for communication of state information to the
428 * kernel on firing a vertex buffer with either of the
429 * obsoleted vertex/index ioctls.
430 */
431 drm_radeon_context_regs_t context_state;
432 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
433 unsigned int dirty;
434 unsigned int vertsize;
435 unsigned int vc_format;
436
437 /* The current cliprects, or a subset thereof.
438 */
439 struct drm_clip_rect boxes[RADEON_NR_SAREA_CLIPRECTS];
440 unsigned int nbox;
441
442 /* Counters for client-side throttling of rendering clients.
443 */
444 unsigned int last_frame;
445 unsigned int last_dispatch;
446 unsigned int last_clear;
447
448 struct drm_tex_region tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS +
449 1];
450 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
451 int ctx_owner;
452 int pfState; /* number of 3d windows (0,1,2ormore) */
453 int pfCurrentPage; /* which buffer is being displayed? */
454 int crtc2_base; /* CRTC2 frame offset */
455 int tiling_enabled; /* set by drm, read by 2d + 3d clients */
456} drm_radeon_sarea_t;
457
458/* WARNING: If you change any of these defines, make sure to change the
459 * defines in the Xserver file (xf86drmRadeon.h)
460 *
461 * KW: actually it's illegal to change any of this (backwards compatibility).
462 */
463
464/* Radeon specific ioctls
465 * The device specific ioctl range is 0x40 to 0x79.
466 */
467#define DRM_RADEON_CP_INIT 0x00
468#define DRM_RADEON_CP_START 0x01
469#define DRM_RADEON_CP_STOP 0x02
470#define DRM_RADEON_CP_RESET 0x03
471#define DRM_RADEON_CP_IDLE 0x04
472#define DRM_RADEON_RESET 0x05
473#define DRM_RADEON_FULLSCREEN 0x06
474#define DRM_RADEON_SWAP 0x07
475#define DRM_RADEON_CLEAR 0x08
476#define DRM_RADEON_VERTEX 0x09
477#define DRM_RADEON_INDICES 0x0A
478#define DRM_RADEON_NOT_USED
479#define DRM_RADEON_STIPPLE 0x0C
480#define DRM_RADEON_INDIRECT 0x0D
481#define DRM_RADEON_TEXTURE 0x0E
482#define DRM_RADEON_VERTEX2 0x0F
483#define DRM_RADEON_CMDBUF 0x10
484#define DRM_RADEON_GETPARAM 0x11
485#define DRM_RADEON_FLIP 0x12
486#define DRM_RADEON_ALLOC 0x13
487#define DRM_RADEON_FREE 0x14
488#define DRM_RADEON_INIT_HEAP 0x15
489#define DRM_RADEON_IRQ_EMIT 0x16
490#define DRM_RADEON_IRQ_WAIT 0x17
491#define DRM_RADEON_CP_RESUME 0x18
492#define DRM_RADEON_SETPARAM 0x19
493#define DRM_RADEON_SURF_ALLOC 0x1a
494#define DRM_RADEON_SURF_FREE 0x1b
495
496#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
497#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
498#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
499#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESET)
500#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_IDLE)
501#define DRM_IOCTL_RADEON_RESET DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_RESET)
502#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FULLSCREEN, drm_radeon_fullscreen_t)
503#define DRM_IOCTL_RADEON_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_SWAP)
504#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CLEAR, drm_radeon_clear_t)
505#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX, drm_radeon_vertex_t)
506#define DRM_IOCTL_RADEON_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INDICES, drm_radeon_indices_t)
507#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_STIPPLE, drm_radeon_stipple_t)
508#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_INDIRECT, drm_radeon_indirect_t)
509#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_TEXTURE, drm_radeon_texture_t)
510#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_VERTEX2, drm_radeon_vertex2_t)
511#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CMDBUF, drm_radeon_cmd_buffer_t)
512#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GETPARAM, drm_radeon_getparam_t)
513#define DRM_IOCTL_RADEON_FLIP DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_FLIP)
514#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_ALLOC, drm_radeon_mem_alloc_t)
515#define DRM_IOCTL_RADEON_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_FREE, drm_radeon_mem_free_t)
516#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_INIT_HEAP, drm_radeon_mem_init_heap_t)
517#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_IRQ_EMIT, drm_radeon_irq_emit_t)
518#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_IRQ_WAIT, drm_radeon_irq_wait_t)
519#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_RESUME)
520#define DRM_IOCTL_RADEON_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SETPARAM, drm_radeon_setparam_t)
521#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
522#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
523
524typedef struct drm_radeon_init {
525 enum {
526 RADEON_INIT_CP = 0x01,
527 RADEON_CLEANUP_CP = 0x02,
528 RADEON_INIT_R200_CP = 0x03,
529 RADEON_INIT_R300_CP = 0x04
530 } func;
531 unsigned long sarea_priv_offset;
532 int is_pci;
533 int cp_mode;
534 int gart_size;
535 int ring_size;
536 int usec_timeout;
537
538 unsigned int fb_bpp;
539 unsigned int front_offset, front_pitch;
540 unsigned int back_offset, back_pitch;
541 unsigned int depth_bpp;
542 unsigned int depth_offset, depth_pitch;
543
544 unsigned long fb_offset;
545 unsigned long mmio_offset;
546 unsigned long ring_offset;
547 unsigned long ring_rptr_offset;
548 unsigned long buffers_offset;
549 unsigned long gart_textures_offset;
550} drm_radeon_init_t;
551
552typedef struct drm_radeon_cp_stop {
553 int flush;
554 int idle;
555} drm_radeon_cp_stop_t;
556
557typedef struct drm_radeon_fullscreen {
558 enum {
559 RADEON_INIT_FULLSCREEN = 0x01,
560 RADEON_CLEANUP_FULLSCREEN = 0x02
561 } func;
562} drm_radeon_fullscreen_t;
563
564#define CLEAR_X1 0
565#define CLEAR_Y1 1
566#define CLEAR_X2 2
567#define CLEAR_Y2 3
568#define CLEAR_DEPTH 4
569
570typedef union drm_radeon_clear_rect {
571 float f[5];
572 unsigned int ui[5];
573} drm_radeon_clear_rect_t;
574
575typedef struct drm_radeon_clear {
576 unsigned int flags;
577 unsigned int clear_color;
578 unsigned int clear_depth;
579 unsigned int color_mask;
580 unsigned int depth_mask; /* misnamed field: should be stencil */
581 drm_radeon_clear_rect_t __user *depth_boxes;
582} drm_radeon_clear_t;
583
584typedef struct drm_radeon_vertex {
585 int prim;
586 int idx; /* Index of vertex buffer */
587 int count; /* Number of vertices in buffer */
588 int discard; /* Client finished with buffer? */
589} drm_radeon_vertex_t;
590
591typedef struct drm_radeon_indices {
592 int prim;
593 int idx;
594 int start;
595 int end;
596 int discard; /* Client finished with buffer? */
597} drm_radeon_indices_t;
598
599/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
600 * - allows multiple primitives and state changes in a single ioctl
601 * - supports driver change to emit native primitives
602 */
603typedef struct drm_radeon_vertex2 {
604 int idx; /* Index of vertex buffer */
605 int discard; /* Client finished with buffer? */
606 int nr_states;
607 drm_radeon_state_t __user *state;
608 int nr_prims;
609 drm_radeon_prim_t __user *prim;
610} drm_radeon_vertex2_t;
611
612/* v1.3 - obsoletes drm_radeon_vertex2
613 * - allows arbitarily large cliprect list
614 * - allows updating of tcl packet, vector and scalar state
615 * - allows memory-efficient description of state updates
616 * - allows state to be emitted without a primitive
617 * (for clears, ctx switches)
618 * - allows more than one dma buffer to be referenced per ioctl
619 * - supports tcl driver
620 * - may be extended in future versions with new cmd types, packets
621 */
622typedef struct drm_radeon_cmd_buffer {
623 int bufsz;
624 char __user *buf;
625 int nbox;
626 struct drm_clip_rect __user *boxes;
627} drm_radeon_cmd_buffer_t;
628
629typedef struct drm_radeon_tex_image {
630 unsigned int x, y; /* Blit coordinates */
631 unsigned int width, height;
632 const void __user *data;
633} drm_radeon_tex_image_t;
634
635typedef struct drm_radeon_texture {
636 unsigned int offset;
637 int pitch;
638 int format;
639 int width; /* Texture image coordinates */
640 int height;
641 drm_radeon_tex_image_t __user *image;
642} drm_radeon_texture_t;
643
644typedef struct drm_radeon_stipple {
645 unsigned int __user *mask;
646} drm_radeon_stipple_t;
647
648typedef struct drm_radeon_indirect {
649 int idx;
650 int start;
651 int end;
652 int discard;
653} drm_radeon_indirect_t;
654
655/* enum for card type parameters */
656#define RADEON_CARD_PCI 0
657#define RADEON_CARD_AGP 1
658#define RADEON_CARD_PCIE 2
659
660/* 1.3: An ioctl to get parameters that aren't available to the 3d
661 * client any other way.
662 */
663#define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
664#define RADEON_PARAM_LAST_FRAME 2
665#define RADEON_PARAM_LAST_DISPATCH 3
666#define RADEON_PARAM_LAST_CLEAR 4
667/* Added with DRM version 1.6. */
668#define RADEON_PARAM_IRQ_NR 5
669#define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
670/* Added with DRM version 1.8. */
671#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
672#define RADEON_PARAM_STATUS_HANDLE 8
673#define RADEON_PARAM_SAREA_HANDLE 9
674#define RADEON_PARAM_GART_TEX_HANDLE 10
675#define RADEON_PARAM_SCRATCH_OFFSET 11
676#define RADEON_PARAM_CARD_TYPE 12
677#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
678#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
679#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
680
681typedef struct drm_radeon_getparam {
682 int param;
683 void __user *value;
684} drm_radeon_getparam_t;
685
686/* 1.6: Set up a memory manager for regions of shared memory:
687 */
688#define RADEON_MEM_REGION_GART 1
689#define RADEON_MEM_REGION_FB 2
690
691typedef struct drm_radeon_mem_alloc {
692 int region;
693 int alignment;
694 int size;
695 int __user *region_offset; /* offset from start of fb or GART */
696} drm_radeon_mem_alloc_t;
697
698typedef struct drm_radeon_mem_free {
699 int region;
700 int region_offset;
701} drm_radeon_mem_free_t;
702
703typedef struct drm_radeon_mem_init_heap {
704 int region;
705 int size;
706 int start;
707} drm_radeon_mem_init_heap_t;
708
709/* 1.6: Userspace can request & wait on irq's:
710 */
711typedef struct drm_radeon_irq_emit {
712 int __user *irq_seq;
713} drm_radeon_irq_emit_t;
714
715typedef struct drm_radeon_irq_wait {
716 int irq_seq;
717} drm_radeon_irq_wait_t;
718
719/* 1.10: Clients tell the DRM where they think the framebuffer is located in
720 * the card's address space, via a new generic ioctl to set parameters
721 */
722
723typedef struct drm_radeon_setparam {
724 unsigned int param;
725 int64_t value;
726} drm_radeon_setparam_t;
727
728#define RADEON_SETPARAM_FB_LOCATION 1 /* determined framebuffer location */
729#define RADEON_SETPARAM_SWITCH_TILING 2 /* enable/disable color tiling */
730#define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
731#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
732#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
733#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
734/* 1.14: Clients can allocate/free a surface
735 */
736typedef struct drm_radeon_surface_alloc {
737 unsigned int address;
738 unsigned int size;
739 unsigned int flags;
740} drm_radeon_surface_alloc_t;
741
742typedef struct drm_radeon_surface_free {
743 unsigned int address;
744} drm_radeon_surface_free_t;
745
746#define DRM_RADEON_VBLANK_CRTC1 1
747#define DRM_RADEON_VBLANK_CRTC2 2
748
749#endif
diff --git a/include/drm/savage_drm.h b/include/drm/savage_drm.h
new file mode 100644
index 000000000000..8a576ef01821
--- /dev/null
+++ b/include/drm/savage_drm.h
@@ -0,0 +1,210 @@
1/* savage_drm.h -- Public header for the savage driver
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26#ifndef __SAVAGE_DRM_H__
27#define __SAVAGE_DRM_H__
28
29#ifndef __SAVAGE_SAREA_DEFINES__
30#define __SAVAGE_SAREA_DEFINES__
31
32/* 2 heaps (1 for card, 1 for agp), each divided into upto 128
33 * regions, subject to a minimum region size of (1<<16) == 64k.
34 *
35 * Clients may subdivide regions internally, but when sharing between
36 * clients, the region size is the minimum granularity.
37 */
38
39#define SAVAGE_CARD_HEAP 0
40#define SAVAGE_AGP_HEAP 1
41#define SAVAGE_NR_TEX_HEAPS 2
42#define SAVAGE_NR_TEX_REGIONS 16
43#define SAVAGE_LOG_MIN_TEX_REGION_SIZE 16
44
45#endif /* __SAVAGE_SAREA_DEFINES__ */
46
47typedef struct _drm_savage_sarea {
48 /* LRU lists for texture memory in agp space and on the card.
49 */
50 struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS +
51 1];
52 unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
53
54 /* Mechanism to validate card state.
55 */
56 int ctxOwner;
57} drm_savage_sarea_t, *drm_savage_sarea_ptr;
58
59/* Savage-specific ioctls
60 */
61#define DRM_SAVAGE_BCI_INIT 0x00
62#define DRM_SAVAGE_BCI_CMDBUF 0x01
63#define DRM_SAVAGE_BCI_EVENT_EMIT 0x02
64#define DRM_SAVAGE_BCI_EVENT_WAIT 0x03
65
66#define DRM_IOCTL_SAVAGE_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
67#define DRM_IOCTL_SAVAGE_CMDBUF DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
68#define DRM_IOCTL_SAVAGE_EVENT_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
69#define DRM_IOCTL_SAVAGE_EVENT_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
70
71#define SAVAGE_DMA_PCI 1
72#define SAVAGE_DMA_AGP 3
73typedef struct drm_savage_init {
74 enum {
75 SAVAGE_INIT_BCI = 1,
76 SAVAGE_CLEANUP_BCI = 2
77 } func;
78 unsigned int sarea_priv_offset;
79
80 /* some parameters */
81 unsigned int cob_size;
82 unsigned int bci_threshold_lo, bci_threshold_hi;
83 unsigned int dma_type;
84
85 /* frame buffer layout */
86 unsigned int fb_bpp;
87 unsigned int front_offset, front_pitch;
88 unsigned int back_offset, back_pitch;
89 unsigned int depth_bpp;
90 unsigned int depth_offset, depth_pitch;
91
92 /* local textures */
93 unsigned int texture_offset;
94 unsigned int texture_size;
95
96 /* physical locations of non-permanent maps */
97 unsigned long status_offset;
98 unsigned long buffers_offset;
99 unsigned long agp_textures_offset;
100 unsigned long cmd_dma_offset;
101} drm_savage_init_t;
102
103typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
104typedef struct drm_savage_cmdbuf {
105 /* command buffer in client's address space */
106 drm_savage_cmd_header_t __user *cmd_addr;
107 unsigned int size; /* size of the command buffer in 64bit units */
108
109 unsigned int dma_idx; /* DMA buffer index to use */
110 int discard; /* discard DMA buffer when done */
111 /* vertex buffer in client's address space */
112 unsigned int __user *vb_addr;
113 unsigned int vb_size; /* size of client vertex buffer in bytes */
114 unsigned int vb_stride; /* stride of vertices in 32bit words */
115 /* boxes in client's address space */
116 struct drm_clip_rect __user *box_addr;
117 unsigned int nbox; /* number of clipping boxes */
118} drm_savage_cmdbuf_t;
119
120#define SAVAGE_WAIT_2D 0x1 /* wait for 2D idle before updating event tag */
121#define SAVAGE_WAIT_3D 0x2 /* wait for 3D idle before updating event tag */
122#define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
123typedef struct drm_savage_event {
124 unsigned int count;
125 unsigned int flags;
126} drm_savage_event_emit_t, drm_savage_event_wait_t;
127
128/* Commands for the cmdbuf ioctl
129 */
130#define SAVAGE_CMD_STATE 0 /* a range of state registers */
131#define SAVAGE_CMD_DMA_PRIM 1 /* vertices from DMA buffer */
132#define SAVAGE_CMD_VB_PRIM 2 /* vertices from client vertex buffer */
133#define SAVAGE_CMD_DMA_IDX 3 /* indexed vertices from DMA buffer */
134#define SAVAGE_CMD_VB_IDX 4 /* indexed vertices client vertex buffer */
135#define SAVAGE_CMD_CLEAR 5 /* clear buffers */
136#define SAVAGE_CMD_SWAP 6 /* swap buffers */
137
138/* Primitive types
139*/
140#define SAVAGE_PRIM_TRILIST 0 /* triangle list */
141#define SAVAGE_PRIM_TRISTRIP 1 /* triangle strip */
142#define SAVAGE_PRIM_TRIFAN 2 /* triangle fan */
143#define SAVAGE_PRIM_TRILIST_201 3 /* reorder verts for correct flat
144 * shading on s3d */
145
146/* Skip flags (vertex format)
147 */
148#define SAVAGE_SKIP_Z 0x01
149#define SAVAGE_SKIP_W 0x02
150#define SAVAGE_SKIP_C0 0x04
151#define SAVAGE_SKIP_C1 0x08
152#define SAVAGE_SKIP_S0 0x10
153#define SAVAGE_SKIP_T0 0x20
154#define SAVAGE_SKIP_ST0 0x30
155#define SAVAGE_SKIP_S1 0x40
156#define SAVAGE_SKIP_T1 0x80
157#define SAVAGE_SKIP_ST1 0xc0
158#define SAVAGE_SKIP_ALL_S3D 0x3f
159#define SAVAGE_SKIP_ALL_S4 0xff
160
161/* Buffer names for clear command
162 */
163#define SAVAGE_FRONT 0x1
164#define SAVAGE_BACK 0x2
165#define SAVAGE_DEPTH 0x4
166
167/* 64-bit command header
168 */
169union drm_savage_cmd_header {
170 struct {
171 unsigned char cmd; /* command */
172 unsigned char pad0;
173 unsigned short pad1;
174 unsigned short pad2;
175 unsigned short pad3;
176 } cmd; /* generic */
177 struct {
178 unsigned char cmd;
179 unsigned char global; /* need idle engine? */
180 unsigned short count; /* number of consecutive registers */
181 unsigned short start; /* first register */
182 unsigned short pad3;
183 } state; /* SAVAGE_CMD_STATE */
184 struct {
185 unsigned char cmd;
186 unsigned char prim; /* primitive type */
187 unsigned short skip; /* vertex format (skip flags) */
188 unsigned short count; /* number of vertices */
189 unsigned short start; /* first vertex in DMA/vertex buffer */
190 } prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
191 struct {
192 unsigned char cmd;
193 unsigned char prim;
194 unsigned short skip;
195 unsigned short count; /* number of indices that follow */
196 unsigned short pad3;
197 } idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
198 struct {
199 unsigned char cmd;
200 unsigned char pad0;
201 unsigned short pad1;
202 unsigned int flags;
203 } clear0; /* SAVAGE_CMD_CLEAR */
204 struct {
205 unsigned int mask;
206 unsigned int value;
207 } clear1; /* SAVAGE_CMD_CLEAR data */
208};
209
210#endif
diff --git a/include/drm/sis_drm.h b/include/drm/sis_drm.h
new file mode 100644
index 000000000000..30f7b3827466
--- /dev/null
+++ b/include/drm/sis_drm.h
@@ -0,0 +1,67 @@
1/* sis_drv.h -- Private header for sis driver -*- linux-c -*- */
2/*
3 * Copyright 2005 Eric Anholt
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 */
26
27#ifndef __SIS_DRM_H__
28#define __SIS_DRM_H__
29
30/* SiS specific ioctls */
31#define NOT_USED_0_3
32#define DRM_SIS_FB_ALLOC 0x04
33#define DRM_SIS_FB_FREE 0x05
34#define NOT_USED_6_12
35#define DRM_SIS_AGP_INIT 0x13
36#define DRM_SIS_AGP_ALLOC 0x14
37#define DRM_SIS_AGP_FREE 0x15
38#define DRM_SIS_FB_INIT 0x16
39
40#define DRM_IOCTL_SIS_FB_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_FB_ALLOC, drm_sis_mem_t)
41#define DRM_IOCTL_SIS_FB_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_FREE, drm_sis_mem_t)
42#define DRM_IOCTL_SIS_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_INIT, drm_sis_agp_t)
43#define DRM_IOCTL_SIS_AGP_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_SIS_AGP_ALLOC, drm_sis_mem_t)
44#define DRM_IOCTL_SIS_AGP_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_AGP_FREE, drm_sis_mem_t)
45#define DRM_IOCTL_SIS_FB_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_SIS_FB_INIT, drm_sis_fb_t)
46/*
47#define DRM_IOCTL_SIS_FLIP DRM_IOW( 0x48, drm_sis_flip_t)
48#define DRM_IOCTL_SIS_FLIP_INIT DRM_IO( 0x49)
49#define DRM_IOCTL_SIS_FLIP_FINAL DRM_IO( 0x50)
50*/
51
52typedef struct {
53 int context;
54 unsigned int offset;
55 unsigned int size;
56 unsigned long free;
57} drm_sis_mem_t;
58
59typedef struct {
60 unsigned int offset, size;
61} drm_sis_agp_t;
62
63typedef struct {
64 unsigned int offset, size;
65} drm_sis_fb_t;
66
67#endif /* __SIS_DRM_H__ */
diff --git a/include/drm/via_drm.h b/include/drm/via_drm.h
new file mode 100644
index 000000000000..a3b5c102b067
--- /dev/null
+++ b/include/drm/via_drm.h
@@ -0,0 +1,275 @@
1/*
2 * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved.
3 * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sub license,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef _VIA_DRM_H_
25#define _VIA_DRM_H_
26
27/* WARNING: These defines must be the same as what the Xserver uses.
28 * if you change them, you must change the defines in the Xserver.
29 */
30
31#ifndef _VIA_DEFINES_
32#define _VIA_DEFINES_
33
34#ifndef __KERNEL__
35#include "via_drmclient.h"
36#endif
37
38#define VIA_NR_SAREA_CLIPRECTS 8
39#define VIA_NR_XVMC_PORTS 10
40#define VIA_NR_XVMC_LOCKS 5
41#define VIA_MAX_CACHELINE_SIZE 64
42#define XVMCLOCKPTR(saPriv,lockNo) \
43 ((volatile struct drm_hw_lock *)(((((unsigned long) (saPriv)->XvMCLockArea) + \
44 (VIA_MAX_CACHELINE_SIZE - 1)) & \
45 ~(VIA_MAX_CACHELINE_SIZE - 1)) + \
46 VIA_MAX_CACHELINE_SIZE*(lockNo)))
47
48/* Each region is a minimum of 64k, and there are at most 64 of them.
49 */
50#define VIA_NR_TEX_REGIONS 64
51#define VIA_LOG_MIN_TEX_REGION_SIZE 16
52#endif
53
54#define VIA_UPLOAD_TEX0IMAGE 0x1 /* handled clientside */
55#define VIA_UPLOAD_TEX1IMAGE 0x2 /* handled clientside */
56#define VIA_UPLOAD_CTX 0x4
57#define VIA_UPLOAD_BUFFERS 0x8
58#define VIA_UPLOAD_TEX0 0x10
59#define VIA_UPLOAD_TEX1 0x20
60#define VIA_UPLOAD_CLIPRECTS 0x40
61#define VIA_UPLOAD_ALL 0xff
62
63/* VIA specific ioctls */
64#define DRM_VIA_ALLOCMEM 0x00
65#define DRM_VIA_FREEMEM 0x01
66#define DRM_VIA_AGP_INIT 0x02
67#define DRM_VIA_FB_INIT 0x03
68#define DRM_VIA_MAP_INIT 0x04
69#define DRM_VIA_DEC_FUTEX 0x05
70#define NOT_USED
71#define DRM_VIA_DMA_INIT 0x07
72#define DRM_VIA_CMDBUFFER 0x08
73#define DRM_VIA_FLUSH 0x09
74#define DRM_VIA_PCICMD 0x0a
75#define DRM_VIA_CMDBUF_SIZE 0x0b
76#define NOT_USED
77#define DRM_VIA_WAIT_IRQ 0x0d
78#define DRM_VIA_DMA_BLIT 0x0e
79#define DRM_VIA_BLIT_SYNC 0x0f
80
81#define DRM_IOCTL_VIA_ALLOCMEM DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_ALLOCMEM, drm_via_mem_t)
82#define DRM_IOCTL_VIA_FREEMEM DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_FREEMEM, drm_via_mem_t)
83#define DRM_IOCTL_VIA_AGP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_AGP_INIT, drm_via_agp_t)
84#define DRM_IOCTL_VIA_FB_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_FB_INIT, drm_via_fb_t)
85#define DRM_IOCTL_VIA_MAP_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_MAP_INIT, drm_via_init_t)
86#define DRM_IOCTL_VIA_DEC_FUTEX DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_DEC_FUTEX, drm_via_futex_t)
87#define DRM_IOCTL_VIA_DMA_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_VIA_DMA_INIT, drm_via_dma_init_t)
88#define DRM_IOCTL_VIA_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_CMDBUFFER, drm_via_cmdbuffer_t)
89#define DRM_IOCTL_VIA_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_VIA_FLUSH)
90#define DRM_IOCTL_VIA_PCICMD DRM_IOW( DRM_COMMAND_BASE + DRM_VIA_PCICMD, drm_via_cmdbuffer_t)
91#define DRM_IOCTL_VIA_CMDBUF_SIZE DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_CMDBUF_SIZE, \
92 drm_via_cmdbuf_size_t)
93#define DRM_IOCTL_VIA_WAIT_IRQ DRM_IOWR( DRM_COMMAND_BASE + DRM_VIA_WAIT_IRQ, drm_via_irqwait_t)
94#define DRM_IOCTL_VIA_DMA_BLIT DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_DMA_BLIT, drm_via_dmablit_t)
95#define DRM_IOCTL_VIA_BLIT_SYNC DRM_IOW(DRM_COMMAND_BASE + DRM_VIA_BLIT_SYNC, drm_via_blitsync_t)
96
97/* Indices into buf.Setup where various bits of state are mirrored per
98 * context and per buffer. These can be fired at the card as a unit,
99 * or in a piecewise fashion as required.
100 */
101
102#define VIA_TEX_SETUP_SIZE 8
103
104/* Flags for clear ioctl
105 */
106#define VIA_FRONT 0x1
107#define VIA_BACK 0x2
108#define VIA_DEPTH 0x4
109#define VIA_STENCIL 0x8
110#define VIA_MEM_VIDEO 0 /* matches drm constant */
111#define VIA_MEM_AGP 1 /* matches drm constant */
112#define VIA_MEM_SYSTEM 2
113#define VIA_MEM_MIXED 3
114#define VIA_MEM_UNKNOWN 4
115
116typedef struct {
117 uint32_t offset;
118 uint32_t size;
119} drm_via_agp_t;
120
121typedef struct {
122 uint32_t offset;
123 uint32_t size;
124} drm_via_fb_t;
125
126typedef struct {
127 uint32_t context;
128 uint32_t type;
129 uint32_t size;
130 unsigned long index;
131 unsigned long offset;
132} drm_via_mem_t;
133
134typedef struct _drm_via_init {
135 enum {
136 VIA_INIT_MAP = 0x01,
137 VIA_CLEANUP_MAP = 0x02
138 } func;
139
140 unsigned long sarea_priv_offset;
141 unsigned long fb_offset;
142 unsigned long mmio_offset;
143 unsigned long agpAddr;
144} drm_via_init_t;
145
146typedef struct _drm_via_futex {
147 enum {
148 VIA_FUTEX_WAIT = 0x00,
149 VIA_FUTEX_WAKE = 0X01
150 } func;
151 uint32_t ms;
152 uint32_t lock;
153 uint32_t val;
154} drm_via_futex_t;
155
156typedef struct _drm_via_dma_init {
157 enum {
158 VIA_INIT_DMA = 0x01,
159 VIA_CLEANUP_DMA = 0x02,
160 VIA_DMA_INITIALIZED = 0x03
161 } func;
162
163 unsigned long offset;
164 unsigned long size;
165 unsigned long reg_pause_addr;
166} drm_via_dma_init_t;
167
168typedef struct _drm_via_cmdbuffer {
169 char __user *buf;
170 unsigned long size;
171} drm_via_cmdbuffer_t;
172
173/* Warning: If you change the SAREA structure you must change the Xserver
174 * structure as well */
175
176typedef struct _drm_via_tex_region {
177 unsigned char next, prev; /* indices to form a circular LRU */
178 unsigned char inUse; /* owned by a client, or free? */
179 int age; /* tracked by clients to update local LRU's */
180} drm_via_tex_region_t;
181
182typedef struct _drm_via_sarea {
183 unsigned int dirty;
184 unsigned int nbox;
185 struct drm_clip_rect boxes[VIA_NR_SAREA_CLIPRECTS];
186 drm_via_tex_region_t texList[VIA_NR_TEX_REGIONS + 1];
187 int texAge; /* last time texture was uploaded */
188 int ctxOwner; /* last context to upload state */
189 int vertexPrim;
190
191 /*
192 * Below is for XvMC.
193 * We want the lock integers alone on, and aligned to, a cache line.
194 * Therefore this somewhat strange construct.
195 */
196
197 char XvMCLockArea[VIA_MAX_CACHELINE_SIZE * (VIA_NR_XVMC_LOCKS + 1)];
198
199 unsigned int XvMCDisplaying[VIA_NR_XVMC_PORTS];
200 unsigned int XvMCSubPicOn[VIA_NR_XVMC_PORTS];
201 unsigned int XvMCCtxNoGrabbed; /* Last context to hold decoder */
202
203 /* Used by the 3d driver only at this point, for pageflipping:
204 */
205 unsigned int pfCurrentOffset;
206} drm_via_sarea_t;
207
208typedef struct _drm_via_cmdbuf_size {
209 enum {
210 VIA_CMDBUF_SPACE = 0x01,
211 VIA_CMDBUF_LAG = 0x02
212 } func;
213 int wait;
214 uint32_t size;
215} drm_via_cmdbuf_size_t;
216
217typedef enum {
218 VIA_IRQ_ABSOLUTE = 0x0,
219 VIA_IRQ_RELATIVE = 0x1,
220 VIA_IRQ_SIGNAL = 0x10000000,
221 VIA_IRQ_FORCE_SEQUENCE = 0x20000000
222} via_irq_seq_type_t;
223
224#define VIA_IRQ_FLAGS_MASK 0xF0000000
225
226enum drm_via_irqs {
227 drm_via_irq_hqv0 = 0,
228 drm_via_irq_hqv1,
229 drm_via_irq_dma0_dd,
230 drm_via_irq_dma0_td,
231 drm_via_irq_dma1_dd,
232 drm_via_irq_dma1_td,
233 drm_via_irq_num
234};
235
236struct drm_via_wait_irq_request {
237 unsigned irq;
238 via_irq_seq_type_t type;
239 uint32_t sequence;
240 uint32_t signal;
241};
242
243typedef union drm_via_irqwait {
244 struct drm_via_wait_irq_request request;
245 struct drm_wait_vblank_reply reply;
246} drm_via_irqwait_t;
247
248typedef struct drm_via_blitsync {
249 uint32_t sync_handle;
250 unsigned engine;
251} drm_via_blitsync_t;
252
253/* - * Below,"flags" is currently unused but will be used for possible future
254 * extensions like kernel space bounce buffers for bad alignments and
255 * blit engine busy-wait polling for better latency in the absence of
256 * interrupts.
257 */
258
259typedef struct drm_via_dmablit {
260 uint32_t num_lines;
261 uint32_t line_length;
262
263 uint32_t fb_addr;
264 uint32_t fb_stride;
265
266 unsigned char *mem_addr;
267 uint32_t mem_stride;
268
269 uint32_t flags;
270 int to_fb;
271
272 drm_via_blitsync_t sync;
273} drm_via_dmablit_t;
274
275#endif /* _VIA_DRM_H_ */
diff --git a/include/linux/acpi.h b/include/linux/acpi.h
index 41f7ce7edd7a..0601075d09a1 100644
--- a/include/linux/acpi.h
+++ b/include/linux/acpi.h
@@ -82,6 +82,7 @@ char * __acpi_map_table (unsigned long phys_addr, unsigned long size);
82int early_acpi_boot_init(void); 82int early_acpi_boot_init(void);
83int acpi_boot_init (void); 83int acpi_boot_init (void);
84int acpi_boot_table_init (void); 84int acpi_boot_table_init (void);
85int acpi_mps_check (void);
85int acpi_numa_init (void); 86int acpi_numa_init (void);
86 87
87int acpi_table_init (void); 88int acpi_table_init (void);
@@ -250,6 +251,11 @@ static inline int acpi_boot_table_init(void)
250 return 0; 251 return 0;
251} 252}
252 253
254static inline int acpi_mps_check(void)
255{
256 return 0;
257}
258
253static inline int acpi_check_resource_conflict(struct resource *res) 259static inline int acpi_check_resource_conflict(struct resource *res)
254{ 260{
255 return 0; 261 return 0;
diff --git a/include/linux/bio.h b/include/linux/bio.h
index 61c15eaf3fb3..0933a14e6414 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -64,6 +64,7 @@ struct bio_vec {
64 64
65struct bio_set; 65struct bio_set;
66struct bio; 66struct bio;
67struct bio_integrity_payload;
67typedef void (bio_end_io_t) (struct bio *, int); 68typedef void (bio_end_io_t) (struct bio *, int);
68typedef void (bio_destructor_t) (struct bio *); 69typedef void (bio_destructor_t) (struct bio *);
69 70
@@ -112,6 +113,9 @@ struct bio {
112 atomic_t bi_cnt; /* pin count */ 113 atomic_t bi_cnt; /* pin count */
113 114
114 void *bi_private; 115 void *bi_private;
116#if defined(CONFIG_BLK_DEV_INTEGRITY)
117 struct bio_integrity_payload *bi_integrity; /* data integrity */
118#endif
115 119
116 bio_destructor_t *bi_destructor; /* destructor */ 120 bio_destructor_t *bi_destructor; /* destructor */
117}; 121};
@@ -271,6 +275,29 @@ static inline void *bio_data(struct bio *bio)
271 */ 275 */
272#define bio_get(bio) atomic_inc(&(bio)->bi_cnt) 276#define bio_get(bio) atomic_inc(&(bio)->bi_cnt)
273 277
278#if defined(CONFIG_BLK_DEV_INTEGRITY)
279/*
280 * bio integrity payload
281 */
282struct bio_integrity_payload {
283 struct bio *bip_bio; /* parent bio */
284 struct bio_vec *bip_vec; /* integrity data vector */
285
286 sector_t bip_sector; /* virtual start sector */
287
288 void *bip_buf; /* generated integrity data */
289 bio_end_io_t *bip_end_io; /* saved I/O completion fn */
290
291 int bip_error; /* saved I/O error */
292 unsigned int bip_size;
293
294 unsigned short bip_pool; /* pool the ivec came from */
295 unsigned short bip_vcnt; /* # of integrity bio_vecs */
296 unsigned short bip_idx; /* current bip_vec index */
297
298 struct work_struct bip_work; /* I/O completion */
299};
300#endif /* CONFIG_BLK_DEV_INTEGRITY */
274 301
275/* 302/*
276 * A bio_pair is used when we need to split a bio. 303 * A bio_pair is used when we need to split a bio.
@@ -283,10 +310,14 @@ static inline void *bio_data(struct bio *bio)
283 * in bio2.bi_private 310 * in bio2.bi_private
284 */ 311 */
285struct bio_pair { 312struct bio_pair {
286 struct bio bio1, bio2; 313 struct bio bio1, bio2;
287 struct bio_vec bv1, bv2; 314 struct bio_vec bv1, bv2;
288 atomic_t cnt; 315#if defined(CONFIG_BLK_DEV_INTEGRITY)
289 int error; 316 struct bio_integrity_payload bip1, bip2;
317 struct bio_vec iv1, iv2;
318#endif
319 atomic_t cnt;
320 int error;
290}; 321};
291extern struct bio_pair *bio_split(struct bio *bi, mempool_t *pool, 322extern struct bio_pair *bio_split(struct bio *bi, mempool_t *pool,
292 int first_sectors); 323 int first_sectors);
@@ -333,6 +364,39 @@ extern struct bio *bio_copy_user_iov(struct request_queue *, struct sg_iovec *,
333 int, int); 364 int, int);
334extern int bio_uncopy_user(struct bio *); 365extern int bio_uncopy_user(struct bio *);
335void zero_fill_bio(struct bio *bio); 366void zero_fill_bio(struct bio *bio);
367extern struct bio_vec *bvec_alloc_bs(gfp_t, int, unsigned long *, struct bio_set *);
368extern unsigned int bvec_nr_vecs(unsigned short idx);
369
370/*
371 * bio_set is used to allow other portions of the IO system to
372 * allocate their own private memory pools for bio and iovec structures.
373 * These memory pools in turn all allocate from the bio_slab
374 * and the bvec_slabs[].
375 */
376#define BIO_POOL_SIZE 2
377#define BIOVEC_NR_POOLS 6
378
379struct bio_set {
380 mempool_t *bio_pool;
381#if defined(CONFIG_BLK_DEV_INTEGRITY)
382 mempool_t *bio_integrity_pool;
383#endif
384 mempool_t *bvec_pools[BIOVEC_NR_POOLS];
385};
386
387struct biovec_slab {
388 int nr_vecs;
389 char *name;
390 struct kmem_cache *slab;
391};
392
393extern struct bio_set *fs_bio_set;
394
395/*
396 * a small number of entries is fine, not going to be performance critical.
397 * basically we just need to survive
398 */
399#define BIO_SPLIT_ENTRIES 2
336 400
337#ifdef CONFIG_HIGHMEM 401#ifdef CONFIG_HIGHMEM
338/* 402/*
@@ -381,5 +445,63 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx,
381 __bio_kmap_irq((bio), (bio)->bi_idx, (flags)) 445 __bio_kmap_irq((bio), (bio)->bi_idx, (flags))
382#define bio_kunmap_irq(buf,flags) __bio_kunmap_irq(buf, flags) 446#define bio_kunmap_irq(buf,flags) __bio_kunmap_irq(buf, flags)
383 447
448#if defined(CONFIG_BLK_DEV_INTEGRITY)
449
450#define bip_vec_idx(bip, idx) (&(bip->bip_vec[(idx)]))
451#define bip_vec(bip) bip_vec_idx(bip, 0)
452
453#define __bip_for_each_vec(bvl, bip, i, start_idx) \
454 for (bvl = bip_vec_idx((bip), (start_idx)), i = (start_idx); \
455 i < (bip)->bip_vcnt; \
456 bvl++, i++)
457
458#define bip_for_each_vec(bvl, bip, i) \
459 __bip_for_each_vec(bvl, bip, i, (bip)->bip_idx)
460
461static inline int bio_integrity(struct bio *bio)
462{
463#if defined(CONFIG_BLK_DEV_INTEGRITY)
464 return bio->bi_integrity != NULL;
465#else
466 return 0;
467#endif
468}
469
470extern struct bio_integrity_payload *bio_integrity_alloc_bioset(struct bio *, gfp_t, unsigned int, struct bio_set *);
471extern struct bio_integrity_payload *bio_integrity_alloc(struct bio *, gfp_t, unsigned int);
472extern void bio_integrity_free(struct bio *, struct bio_set *);
473extern int bio_integrity_add_page(struct bio *, struct page *, unsigned int, unsigned int);
474extern int bio_integrity_enabled(struct bio *bio);
475extern int bio_integrity_set_tag(struct bio *, void *, unsigned int);
476extern int bio_integrity_get_tag(struct bio *, void *, unsigned int);
477extern int bio_integrity_prep(struct bio *);
478extern void bio_integrity_endio(struct bio *, int);
479extern void bio_integrity_advance(struct bio *, unsigned int);
480extern void bio_integrity_trim(struct bio *, unsigned int, unsigned int);
481extern void bio_integrity_split(struct bio *, struct bio_pair *, int);
482extern int bio_integrity_clone(struct bio *, struct bio *, struct bio_set *);
483extern int bioset_integrity_create(struct bio_set *, int);
484extern void bioset_integrity_free(struct bio_set *);
485extern void bio_integrity_init_slab(void);
486
487#else /* CONFIG_BLK_DEV_INTEGRITY */
488
489#define bio_integrity(a) (0)
490#define bioset_integrity_create(a, b) (0)
491#define bio_integrity_prep(a) (0)
492#define bio_integrity_enabled(a) (0)
493#define bio_integrity_clone(a, b, c) (0)
494#define bioset_integrity_free(a) do { } while (0)
495#define bio_integrity_free(a, b) do { } while (0)
496#define bio_integrity_endio(a, b) do { } while (0)
497#define bio_integrity_advance(a, b) do { } while (0)
498#define bio_integrity_trim(a, b, c) do { } while (0)
499#define bio_integrity_split(a, b, c) do { } while (0)
500#define bio_integrity_set_tag(a, b, c) do { } while (0)
501#define bio_integrity_get_tag(a, b, c) do { } while (0)
502#define bio_integrity_init_slab(a) do { } while (0)
503
504#endif /* CONFIG_BLK_DEV_INTEGRITY */
505
384#endif /* CONFIG_BLOCK */ 506#endif /* CONFIG_BLOCK */
385#endif /* __LINUX_BIO_H */ 507#endif /* __LINUX_BIO_H */
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index d2a1b71e93c3..32a441b05fd5 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -23,7 +23,6 @@
23struct scsi_ioctl_command; 23struct scsi_ioctl_command;
24 24
25struct request_queue; 25struct request_queue;
26typedef struct request_queue request_queue_t __deprecated;
27struct elevator_queue; 26struct elevator_queue;
28typedef struct elevator_queue elevator_t; 27typedef struct elevator_queue elevator_t;
29struct request_pm_state; 28struct request_pm_state;
@@ -34,12 +33,6 @@ struct sg_io_hdr;
34#define BLKDEV_MIN_RQ 4 33#define BLKDEV_MIN_RQ 4
35#define BLKDEV_MAX_RQ 128 /* Default maximum */ 34#define BLKDEV_MAX_RQ 128 /* Default maximum */
36 35
37int put_io_context(struct io_context *ioc);
38void exit_io_context(void);
39struct io_context *get_io_context(gfp_t gfp_flags, int node);
40struct io_context *alloc_io_context(gfp_t gfp_flags, int node);
41void copy_io_context(struct io_context **pdst, struct io_context **psrc);
42
43struct request; 36struct request;
44typedef void (rq_end_io_fn)(struct request *, int); 37typedef void (rq_end_io_fn)(struct request *, int);
45 38
@@ -113,6 +106,7 @@ enum rq_flag_bits {
113 __REQ_ALLOCED, /* request came from our alloc pool */ 106 __REQ_ALLOCED, /* request came from our alloc pool */
114 __REQ_RW_META, /* metadata io request */ 107 __REQ_RW_META, /* metadata io request */
115 __REQ_COPY_USER, /* contains copies of user pages */ 108 __REQ_COPY_USER, /* contains copies of user pages */
109 __REQ_INTEGRITY, /* integrity metadata has been remapped */
116 __REQ_NR_BITS, /* stops here */ 110 __REQ_NR_BITS, /* stops here */
117}; 111};
118 112
@@ -135,6 +129,7 @@ enum rq_flag_bits {
135#define REQ_ALLOCED (1 << __REQ_ALLOCED) 129#define REQ_ALLOCED (1 << __REQ_ALLOCED)
136#define REQ_RW_META (1 << __REQ_RW_META) 130#define REQ_RW_META (1 << __REQ_RW_META)
137#define REQ_COPY_USER (1 << __REQ_COPY_USER) 131#define REQ_COPY_USER (1 << __REQ_COPY_USER)
132#define REQ_INTEGRITY (1 << __REQ_INTEGRITY)
138 133
139#define BLK_MAX_CDB 16 134#define BLK_MAX_CDB 16
140 135
@@ -259,7 +254,14 @@ typedef int (prep_rq_fn) (struct request_queue *, struct request *);
259typedef void (unplug_fn) (struct request_queue *); 254typedef void (unplug_fn) (struct request_queue *);
260 255
261struct bio_vec; 256struct bio_vec;
262typedef int (merge_bvec_fn) (struct request_queue *, struct bio *, struct bio_vec *); 257struct bvec_merge_data {
258 struct block_device *bi_bdev;
259 sector_t bi_sector;
260 unsigned bi_size;
261 unsigned long bi_rw;
262};
263typedef int (merge_bvec_fn) (struct request_queue *, struct bvec_merge_data *,
264 struct bio_vec *);
263typedef void (prepare_flush_fn) (struct request_queue *, struct request *); 265typedef void (prepare_flush_fn) (struct request_queue *, struct request *);
264typedef void (softirq_done_fn)(struct request *); 266typedef void (softirq_done_fn)(struct request *);
265typedef int (dma_drain_needed_fn)(struct request *); 267typedef int (dma_drain_needed_fn)(struct request *);
@@ -426,6 +428,32 @@ static inline void queue_flag_set_unlocked(unsigned int flag,
426 __set_bit(flag, &q->queue_flags); 428 __set_bit(flag, &q->queue_flags);
427} 429}
428 430
431static inline int queue_flag_test_and_clear(unsigned int flag,
432 struct request_queue *q)
433{
434 WARN_ON_ONCE(!queue_is_locked(q));
435
436 if (test_bit(flag, &q->queue_flags)) {
437 __clear_bit(flag, &q->queue_flags);
438 return 1;
439 }
440
441 return 0;
442}
443
444static inline int queue_flag_test_and_set(unsigned int flag,
445 struct request_queue *q)
446{
447 WARN_ON_ONCE(!queue_is_locked(q));
448
449 if (!test_bit(flag, &q->queue_flags)) {
450 __set_bit(flag, &q->queue_flags);
451 return 0;
452 }
453
454 return 1;
455}
456
429static inline void queue_flag_set(unsigned int flag, struct request_queue *q) 457static inline void queue_flag_set(unsigned int flag, struct request_queue *q)
430{ 458{
431 WARN_ON_ONCE(!queue_is_locked(q)); 459 WARN_ON_ONCE(!queue_is_locked(q));
@@ -623,7 +651,6 @@ extern void generic_make_request(struct bio *bio);
623extern void blk_rq_init(struct request_queue *q, struct request *rq); 651extern void blk_rq_init(struct request_queue *q, struct request *rq);
624extern void blk_put_request(struct request *); 652extern void blk_put_request(struct request *);
625extern void __blk_put_request(struct request_queue *, struct request *); 653extern void __blk_put_request(struct request_queue *, struct request *);
626extern void blk_end_sync_rq(struct request *rq, int error);
627extern struct request *blk_get_request(struct request_queue *, int, gfp_t); 654extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
628extern void blk_insert_request(struct request_queue *, struct request *, int, void *); 655extern void blk_insert_request(struct request_queue *, struct request *, int, void *);
629extern void blk_requeue_request(struct request_queue *, struct request *); 656extern void blk_requeue_request(struct request_queue *, struct request *);
@@ -676,7 +703,6 @@ extern int blk_execute_rq(struct request_queue *, struct gendisk *,
676 struct request *, int); 703 struct request *, int);
677extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *, 704extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *,
678 struct request *, int, rq_end_io_fn *); 705 struct request *, int, rq_end_io_fn *);
679extern int blk_verify_command(unsigned char *, int);
680extern void blk_unplug(struct request_queue *q); 706extern void blk_unplug(struct request_queue *q);
681 707
682static inline struct request_queue *bdev_get_queue(struct block_device *bdev) 708static inline struct request_queue *bdev_get_queue(struct block_device *bdev)
@@ -749,6 +775,7 @@ extern void blk_queue_max_segment_size(struct request_queue *, unsigned int);
749extern void blk_queue_hardsect_size(struct request_queue *, unsigned short); 775extern void blk_queue_hardsect_size(struct request_queue *, unsigned short);
750extern void blk_queue_stack_limits(struct request_queue *t, struct request_queue *b); 776extern void blk_queue_stack_limits(struct request_queue *t, struct request_queue *b);
751extern void blk_queue_dma_pad(struct request_queue *, unsigned int); 777extern void blk_queue_dma_pad(struct request_queue *, unsigned int);
778extern void blk_queue_update_dma_pad(struct request_queue *, unsigned int);
752extern int blk_queue_dma_drain(struct request_queue *q, 779extern int blk_queue_dma_drain(struct request_queue *q,
753 dma_drain_needed_fn *dma_drain_needed, 780 dma_drain_needed_fn *dma_drain_needed,
754 void *buf, unsigned int size); 781 void *buf, unsigned int size);
@@ -802,6 +829,15 @@ static inline struct request *blk_map_queue_find_tag(struct blk_queue_tag *bqt,
802 829
803extern int blkdev_issue_flush(struct block_device *, sector_t *); 830extern int blkdev_issue_flush(struct block_device *, sector_t *);
804 831
832/*
833* command filter functions
834*/
835extern int blk_verify_command(struct file *file, unsigned char *cmd);
836extern int blk_cmd_filter_verify_command(struct blk_scsi_cmd_filter *filter,
837 unsigned char *cmd, mode_t *f_mode);
838extern int blk_register_filter(struct gendisk *disk);
839extern void blk_unregister_filter(struct gendisk *disk);
840
805#define MAX_PHYS_SEGMENTS 128 841#define MAX_PHYS_SEGMENTS 128
806#define MAX_HW_SEGMENTS 128 842#define MAX_HW_SEGMENTS 128
807#define SAFE_MAX_SECTORS 255 843#define SAFE_MAX_SECTORS 255
@@ -865,28 +901,116 @@ void kblockd_flush_work(struct work_struct *work);
865#define MODULE_ALIAS_BLOCKDEV_MAJOR(major) \ 901#define MODULE_ALIAS_BLOCKDEV_MAJOR(major) \
866 MODULE_ALIAS("block-major-" __stringify(major) "-*") 902 MODULE_ALIAS("block-major-" __stringify(major) "-*")
867 903
904#if defined(CONFIG_BLK_DEV_INTEGRITY)
868 905
869#else /* CONFIG_BLOCK */ 906#define INTEGRITY_FLAG_READ 2 /* verify data integrity on read */
870/* 907#define INTEGRITY_FLAG_WRITE 4 /* generate data integrity on write */
871 * stubs for when the block layer is configured out
872 */
873#define buffer_heads_over_limit 0
874 908
875static inline long nr_blockdev_pages(void) 909struct blk_integrity_exchg {
910 void *prot_buf;
911 void *data_buf;
912 sector_t sector;
913 unsigned int data_size;
914 unsigned short sector_size;
915 const char *disk_name;
916};
917
918typedef void (integrity_gen_fn) (struct blk_integrity_exchg *);
919typedef int (integrity_vrfy_fn) (struct blk_integrity_exchg *);
920typedef void (integrity_set_tag_fn) (void *, void *, unsigned int);
921typedef void (integrity_get_tag_fn) (void *, void *, unsigned int);
922
923struct blk_integrity {
924 integrity_gen_fn *generate_fn;
925 integrity_vrfy_fn *verify_fn;
926 integrity_set_tag_fn *set_tag_fn;
927 integrity_get_tag_fn *get_tag_fn;
928
929 unsigned short flags;
930 unsigned short tuple_size;
931 unsigned short sector_size;
932 unsigned short tag_size;
933
934 const char *name;
935
936 struct kobject kobj;
937};
938
939extern int blk_integrity_register(struct gendisk *, struct blk_integrity *);
940extern void blk_integrity_unregister(struct gendisk *);
941extern int blk_integrity_compare(struct block_device *, struct block_device *);
942extern int blk_rq_map_integrity_sg(struct request *, struct scatterlist *);
943extern int blk_rq_count_integrity_sg(struct request *);
944
945static inline unsigned short blk_integrity_tuple_size(struct blk_integrity *bi)
876{ 946{
947 if (bi)
948 return bi->tuple_size;
949
877 return 0; 950 return 0;
878} 951}
879 952
880static inline void exit_io_context(void) 953static inline struct blk_integrity *bdev_get_integrity(struct block_device *bdev)
881{ 954{
955 return bdev->bd_disk->integrity;
882} 956}
883 957
884struct io_context; 958static inline unsigned int bdev_get_tag_size(struct block_device *bdev)
885static inline int put_io_context(struct io_context *ioc)
886{ 959{
887 return 1; 960 struct blk_integrity *bi = bdev_get_integrity(bdev);
961
962 if (bi)
963 return bi->tag_size;
964
965 return 0;
966}
967
968static inline int bdev_integrity_enabled(struct block_device *bdev, int rw)
969{
970 struct blk_integrity *bi = bdev_get_integrity(bdev);
971
972 if (bi == NULL)
973 return 0;
974
975 if (rw == READ && bi->verify_fn != NULL &&
976 (bi->flags & INTEGRITY_FLAG_READ))
977 return 1;
978
979 if (rw == WRITE && bi->generate_fn != NULL &&
980 (bi->flags & INTEGRITY_FLAG_WRITE))
981 return 1;
982
983 return 0;
888} 984}
889 985
986static inline int blk_integrity_rq(struct request *rq)
987{
988 return bio_integrity(rq->bio);
989}
990
991#else /* CONFIG_BLK_DEV_INTEGRITY */
992
993#define blk_integrity_rq(rq) (0)
994#define blk_rq_count_integrity_sg(a) (0)
995#define blk_rq_map_integrity_sg(a, b) (0)
996#define bdev_get_integrity(a) (0)
997#define bdev_get_tag_size(a) (0)
998#define blk_integrity_compare(a, b) (0)
999#define blk_integrity_register(a, b) (0)
1000#define blk_integrity_unregister(a) do { } while (0);
1001
1002#endif /* CONFIG_BLK_DEV_INTEGRITY */
1003
1004#else /* CONFIG_BLOCK */
1005/*
1006 * stubs for when the block layer is configured out
1007 */
1008#define buffer_heads_over_limit 0
1009
1010static inline long nr_blockdev_pages(void)
1011{
1012 return 0;
1013}
890 1014
891#endif /* CONFIG_BLOCK */ 1015#endif /* CONFIG_BLOCK */
892 1016
diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h
index e3ef903aae88..d084b8d227a5 100644
--- a/include/linux/blktrace_api.h
+++ b/include/linux/blktrace_api.h
@@ -129,6 +129,7 @@ struct blk_trace {
129 u32 dev; 129 u32 dev;
130 struct dentry *dir; 130 struct dentry *dir;
131 struct dentry *dropped_file; 131 struct dentry *dropped_file;
132 struct dentry *msg_file;
132 atomic_t dropped; 133 atomic_t dropped;
133}; 134};
134 135
diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h
index 686895bacd9d..a1d9b79078ea 100644
--- a/include/linux/bootmem.h
+++ b/include/linux/bootmem.h
@@ -84,6 +84,8 @@ extern int reserve_bootmem(unsigned long addr, unsigned long size, int flags);
84 __alloc_bootmem_low(x, PAGE_SIZE, 0) 84 __alloc_bootmem_low(x, PAGE_SIZE, 0)
85#endif /* !CONFIG_HAVE_ARCH_BOOTMEM_NODE */ 85#endif /* !CONFIG_HAVE_ARCH_BOOTMEM_NODE */
86 86
87extern int reserve_bootmem_generic(unsigned long addr, unsigned long size,
88 int flags);
87extern unsigned long free_all_bootmem(void); 89extern unsigned long free_all_bootmem(void);
88extern unsigned long free_all_bootmem_node(pg_data_t *pgdat); 90extern unsigned long free_all_bootmem_node(pg_data_t *pgdat);
89extern void *__alloc_bootmem_node(pg_data_t *pgdat, 91extern void *__alloc_bootmem_node(pg_data_t *pgdat,
diff --git a/include/linux/console.h b/include/linux/console.h
index a4f27fbdf549..248e6e3b9b73 100644
--- a/include/linux/console.h
+++ b/include/linux/console.h
@@ -108,6 +108,8 @@ struct console {
108 struct console *next; 108 struct console *next;
109}; 109};
110 110
111extern int console_set_on_cmdline;
112
111extern int add_preferred_console(char *name, int idx, char *options); 113extern int add_preferred_console(char *name, int idx, char *options);
112extern int update_console_cmdline(char *name, int idx, char *name_new, int idx_new, char *options); 114extern int update_console_cmdline(char *name, int idx, char *name_new, int idx_new, char *options);
113extern void register_console(struct console *); 115extern void register_console(struct console *);
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index 425824bd49f3..c43dc47fdf75 100644
--- a/include/linux/crypto.h
+++ b/include/linux/crypto.h
@@ -30,15 +30,17 @@
30 */ 30 */
31#define CRYPTO_ALG_TYPE_MASK 0x0000000f 31#define CRYPTO_ALG_TYPE_MASK 0x0000000f
32#define CRYPTO_ALG_TYPE_CIPHER 0x00000001 32#define CRYPTO_ALG_TYPE_CIPHER 0x00000001
33#define CRYPTO_ALG_TYPE_DIGEST 0x00000002 33#define CRYPTO_ALG_TYPE_COMPRESS 0x00000002
34#define CRYPTO_ALG_TYPE_HASH 0x00000003 34#define CRYPTO_ALG_TYPE_AEAD 0x00000003
35#define CRYPTO_ALG_TYPE_BLKCIPHER 0x00000004 35#define CRYPTO_ALG_TYPE_BLKCIPHER 0x00000004
36#define CRYPTO_ALG_TYPE_ABLKCIPHER 0x00000005 36#define CRYPTO_ALG_TYPE_ABLKCIPHER 0x00000005
37#define CRYPTO_ALG_TYPE_GIVCIPHER 0x00000006 37#define CRYPTO_ALG_TYPE_GIVCIPHER 0x00000006
38#define CRYPTO_ALG_TYPE_COMPRESS 0x00000008 38#define CRYPTO_ALG_TYPE_DIGEST 0x00000008
39#define CRYPTO_ALG_TYPE_AEAD 0x00000009 39#define CRYPTO_ALG_TYPE_HASH 0x00000009
40#define CRYPTO_ALG_TYPE_AHASH 0x0000000a
40 41
41#define CRYPTO_ALG_TYPE_HASH_MASK 0x0000000e 42#define CRYPTO_ALG_TYPE_HASH_MASK 0x0000000e
43#define CRYPTO_ALG_TYPE_AHASH_MASK 0x0000000c
42#define CRYPTO_ALG_TYPE_BLKCIPHER_MASK 0x0000000c 44#define CRYPTO_ALG_TYPE_BLKCIPHER_MASK 0x0000000c
43 45
44#define CRYPTO_ALG_LARVAL 0x00000010 46#define CRYPTO_ALG_LARVAL 0x00000010
@@ -102,6 +104,7 @@ struct crypto_async_request;
102struct crypto_aead; 104struct crypto_aead;
103struct crypto_blkcipher; 105struct crypto_blkcipher;
104struct crypto_hash; 106struct crypto_hash;
107struct crypto_ahash;
105struct crypto_tfm; 108struct crypto_tfm;
106struct crypto_type; 109struct crypto_type;
107struct aead_givcrypt_request; 110struct aead_givcrypt_request;
@@ -131,6 +134,16 @@ struct ablkcipher_request {
131 void *__ctx[] CRYPTO_MINALIGN_ATTR; 134 void *__ctx[] CRYPTO_MINALIGN_ATTR;
132}; 135};
133 136
137struct ahash_request {
138 struct crypto_async_request base;
139
140 unsigned int nbytes;
141 struct scatterlist *src;
142 u8 *result;
143
144 void *__ctx[] CRYPTO_MINALIGN_ATTR;
145};
146
134/** 147/**
135 * struct aead_request - AEAD request 148 * struct aead_request - AEAD request
136 * @base: Common attributes for async crypto requests 149 * @base: Common attributes for async crypto requests
@@ -195,6 +208,17 @@ struct ablkcipher_alg {
195 unsigned int ivsize; 208 unsigned int ivsize;
196}; 209};
197 210
211struct ahash_alg {
212 int (*init)(struct ahash_request *req);
213 int (*update)(struct ahash_request *req);
214 int (*final)(struct ahash_request *req);
215 int (*digest)(struct ahash_request *req);
216 int (*setkey)(struct crypto_ahash *tfm, const u8 *key,
217 unsigned int keylen);
218
219 unsigned int digestsize;
220};
221
198struct aead_alg { 222struct aead_alg {
199 int (*setkey)(struct crypto_aead *tfm, const u8 *key, 223 int (*setkey)(struct crypto_aead *tfm, const u8 *key,
200 unsigned int keylen); 224 unsigned int keylen);
@@ -272,6 +296,7 @@ struct compress_alg {
272#define cra_cipher cra_u.cipher 296#define cra_cipher cra_u.cipher
273#define cra_digest cra_u.digest 297#define cra_digest cra_u.digest
274#define cra_hash cra_u.hash 298#define cra_hash cra_u.hash
299#define cra_ahash cra_u.ahash
275#define cra_compress cra_u.compress 300#define cra_compress cra_u.compress
276 301
277struct crypto_alg { 302struct crypto_alg {
@@ -298,6 +323,7 @@ struct crypto_alg {
298 struct cipher_alg cipher; 323 struct cipher_alg cipher;
299 struct digest_alg digest; 324 struct digest_alg digest;
300 struct hash_alg hash; 325 struct hash_alg hash;
326 struct ahash_alg ahash;
301 struct compress_alg compress; 327 struct compress_alg compress;
302 } cra_u; 328 } cra_u;
303 329
@@ -383,6 +409,18 @@ struct hash_tfm {
383 unsigned int digestsize; 409 unsigned int digestsize;
384}; 410};
385 411
412struct ahash_tfm {
413 int (*init)(struct ahash_request *req);
414 int (*update)(struct ahash_request *req);
415 int (*final)(struct ahash_request *req);
416 int (*digest)(struct ahash_request *req);
417 int (*setkey)(struct crypto_ahash *tfm, const u8 *key,
418 unsigned int keylen);
419
420 unsigned int digestsize;
421 unsigned int reqsize;
422};
423
386struct compress_tfm { 424struct compress_tfm {
387 int (*cot_compress)(struct crypto_tfm *tfm, 425 int (*cot_compress)(struct crypto_tfm *tfm,
388 const u8 *src, unsigned int slen, 426 const u8 *src, unsigned int slen,
@@ -397,6 +435,7 @@ struct compress_tfm {
397#define crt_blkcipher crt_u.blkcipher 435#define crt_blkcipher crt_u.blkcipher
398#define crt_cipher crt_u.cipher 436#define crt_cipher crt_u.cipher
399#define crt_hash crt_u.hash 437#define crt_hash crt_u.hash
438#define crt_ahash crt_u.ahash
400#define crt_compress crt_u.compress 439#define crt_compress crt_u.compress
401 440
402struct crypto_tfm { 441struct crypto_tfm {
@@ -409,6 +448,7 @@ struct crypto_tfm {
409 struct blkcipher_tfm blkcipher; 448 struct blkcipher_tfm blkcipher;
410 struct cipher_tfm cipher; 449 struct cipher_tfm cipher;
411 struct hash_tfm hash; 450 struct hash_tfm hash;
451 struct ahash_tfm ahash;
412 struct compress_tfm compress; 452 struct compress_tfm compress;
413 } crt_u; 453 } crt_u;
414 454
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index d982eb89c77d..98202c672fde 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -3,6 +3,7 @@
3 3
4#include <asm/atomic.h> 4#include <asm/atomic.h>
5#include <linux/list.h> 5#include <linux/list.h>
6#include <linux/rculist.h>
6#include <linux/spinlock.h> 7#include <linux/spinlock.h>
7#include <linux/cache.h> 8#include <linux/cache.h>
8#include <linux/rcupdate.h> 9#include <linux/rcupdate.h>
diff --git a/include/linux/delay.h b/include/linux/delay.h
index 54552d21296e..fd832c6d419e 100644
--- a/include/linux/delay.h
+++ b/include/linux/delay.h
@@ -41,6 +41,7 @@ static inline void ndelay(unsigned long x)
41#define ndelay(x) ndelay(x) 41#define ndelay(x) ndelay(x)
42#endif 42#endif
43 43
44extern unsigned long lpj_fine;
44void calibrate_delay(void); 45void calibrate_delay(void);
45void msleep(unsigned int msecs); 46void msleep(unsigned int msecs);
46unsigned long msleep_interruptible(unsigned int msecs); 47unsigned long msleep_interruptible(unsigned int msecs);
diff --git a/include/linux/efi.h b/include/linux/efi.h
index a5f359a7ad0e..807373d467f7 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -287,7 +287,6 @@ efi_guid_unparse(efi_guid_t *guid, char *out)
287extern void efi_init (void); 287extern void efi_init (void);
288extern void *efi_get_pal_addr (void); 288extern void *efi_get_pal_addr (void);
289extern void efi_map_pal_code (void); 289extern void efi_map_pal_code (void);
290extern void efi_map_memmap(void);
291extern void efi_memmap_walk (efi_freemem_callback_t callback, void *arg); 290extern void efi_memmap_walk (efi_freemem_callback_t callback, void *arg);
292extern void efi_gettimeofday (struct timespec *ts); 291extern void efi_gettimeofday (struct timespec *ts);
293extern void efi_enter_virtual_mode (void); /* switch EFI to virtual mode, if possible */ 292extern void efi_enter_virtual_mode (void); /* switch EFI to virtual mode, if possible */
@@ -295,14 +294,11 @@ extern u64 efi_get_iobase (void);
295extern u32 efi_mem_type (unsigned long phys_addr); 294extern u32 efi_mem_type (unsigned long phys_addr);
296extern u64 efi_mem_attributes (unsigned long phys_addr); 295extern u64 efi_mem_attributes (unsigned long phys_addr);
297extern u64 efi_mem_attribute (unsigned long phys_addr, unsigned long size); 296extern u64 efi_mem_attribute (unsigned long phys_addr, unsigned long size);
298extern int efi_mem_attribute_range (unsigned long phys_addr, unsigned long size,
299 u64 attr);
300extern int __init efi_uart_console_only (void); 297extern int __init efi_uart_console_only (void);
301extern void efi_initialize_iomem_resources(struct resource *code_resource, 298extern void efi_initialize_iomem_resources(struct resource *code_resource,
302 struct resource *data_resource, struct resource *bss_resource); 299 struct resource *data_resource, struct resource *bss_resource);
303extern unsigned long efi_get_time(void); 300extern unsigned long efi_get_time(void);
304extern int efi_set_rtc_mmss(unsigned long nowtime); 301extern int efi_set_rtc_mmss(unsigned long nowtime);
305extern int is_available_memory(efi_memory_desc_t * md);
306extern struct efi_memory_map memmap; 302extern struct efi_memory_map memmap;
307 303
308/** 304/**
diff --git a/include/linux/firmware-map.h b/include/linux/firmware-map.h
new file mode 100644
index 000000000000..acbdbcc16051
--- /dev/null
+++ b/include/linux/firmware-map.h
@@ -0,0 +1,74 @@
1/*
2 * include/linux/firmware-map.h:
3 * Copyright (C) 2008 SUSE LINUX Products GmbH
4 * by Bernhard Walle <bwalle@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License v2.0 as published by
8 * the Free Software Foundation
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16#ifndef _LINUX_FIRMWARE_MAP_H
17#define _LINUX_FIRMWARE_MAP_H
18
19#include <linux/list.h>
20#include <linux/kobject.h>
21
22/*
23 * provide a dummy interface if CONFIG_FIRMWARE_MEMMAP is disabled
24 */
25#ifdef CONFIG_FIRMWARE_MEMMAP
26
27/**
28 * Adds a firmware mapping entry. This function uses kmalloc() for memory
29 * allocation. Use firmware_map_add_early() if you want to use the bootmem
30 * allocator.
31 *
32 * That function must be called before late_initcall.
33 *
34 * @start: Start of the memory range.
35 * @end: End of the memory range (inclusive).
36 * @type: Type of the memory range.
37 *
38 * Returns 0 on success, or -ENOMEM if no memory could be allocated.
39 */
40int firmware_map_add(resource_size_t start, resource_size_t end,
41 const char *type);
42
43/**
44 * Adds a firmware mapping entry. This function uses the bootmem allocator
45 * for memory allocation. Use firmware_map_add() if you want to use kmalloc().
46 *
47 * That function must be called before late_initcall.
48 *
49 * @start: Start of the memory range.
50 * @end: End of the memory range (inclusive).
51 * @type: Type of the memory range.
52 *
53 * Returns 0 on success, or -ENOMEM if no memory could be allocated.
54 */
55int firmware_map_add_early(resource_size_t start, resource_size_t end,
56 const char *type);
57
58#else /* CONFIG_FIRMWARE_MEMMAP */
59
60static inline int firmware_map_add(resource_size_t start, resource_size_t end,
61 const char *type)
62{
63 return 0;
64}
65
66static inline int firmware_map_add_early(resource_size_t start,
67 resource_size_t end, const char *type)
68{
69 return 0;
70}
71
72#endif /* CONFIG_FIRMWARE_MEMMAP */
73
74#endif /* _LINUX_FIRMWARE_MAP_H */
diff --git a/include/linux/firmware.h b/include/linux/firmware.h
index 6c7eff2ebada..c8ecf5b2a207 100644
--- a/include/linux/firmware.h
+++ b/include/linux/firmware.h
@@ -1,18 +1,39 @@
1#ifndef _LINUX_FIRMWARE_H 1#ifndef _LINUX_FIRMWARE_H
2#define _LINUX_FIRMWARE_H 2#define _LINUX_FIRMWARE_H
3
3#include <linux/module.h> 4#include <linux/module.h>
4#include <linux/types.h> 5#include <linux/types.h>
6#include <linux/compiler.h>
7
5#define FIRMWARE_NAME_MAX 30 8#define FIRMWARE_NAME_MAX 30
6#define FW_ACTION_NOHOTPLUG 0 9#define FW_ACTION_NOHOTPLUG 0
7#define FW_ACTION_HOTPLUG 1 10#define FW_ACTION_HOTPLUG 1
8 11
9struct firmware { 12struct firmware {
10 size_t size; 13 size_t size;
11 u8 *data; 14 const u8 *data;
12}; 15};
13 16
14struct device; 17struct device;
15 18
19struct builtin_fw {
20 char *name;
21 void *data;
22 unsigned long size;
23};
24
25/* We have to play tricks here much like stringify() to get the
26 __COUNTER__ macro to be expanded as we want it */
27#define __fw_concat1(x, y) x##y
28#define __fw_concat(x, y) __fw_concat1(x, y)
29
30#define DECLARE_BUILTIN_FIRMWARE(name, blob) \
31 DECLARE_BUILTIN_FIRMWARE_SIZE(name, &(blob), sizeof(blob))
32
33#define DECLARE_BUILTIN_FIRMWARE_SIZE(name, blob, size) \
34 static const struct builtin_fw __fw_concat(__builtin_fw,__COUNTER__) \
35 __used __section(.builtin_fw) = { name, blob, size }
36
16#if defined(CONFIG_FW_LOADER) || (defined(CONFIG_FW_LOADER_MODULE) && defined(MODULE)) 37#if defined(CONFIG_FW_LOADER) || (defined(CONFIG_FW_LOADER_MODULE) && defined(MODULE))
17int request_firmware(const struct firmware **fw, const char *name, 38int request_firmware(const struct firmware **fw, const char *name,
18 struct device *device); 39 struct device *device);
diff --git a/include/linux/fs.h b/include/linux/fs.h
index d8e2762ed14d..52e510a0aec2 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -1740,6 +1740,8 @@ extern int wait_on_page_writeback_range(struct address_space *mapping,
1740 pgoff_t start, pgoff_t end); 1740 pgoff_t start, pgoff_t end);
1741extern int __filemap_fdatawrite_range(struct address_space *mapping, 1741extern int __filemap_fdatawrite_range(struct address_space *mapping,
1742 loff_t start, loff_t end, int sync_mode); 1742 loff_t start, loff_t end, int sync_mode);
1743extern int filemap_fdatawrite_range(struct address_space *mapping,
1744 loff_t start, loff_t end);
1743 1745
1744extern long do_fsync(struct file *file, int datasync); 1746extern long do_fsync(struct file *file, int datasync);
1745extern void sync_supers(void); 1747extern void sync_supers(void);
@@ -1870,7 +1872,8 @@ extern void
1870file_ra_state_init(struct file_ra_state *ra, struct address_space *mapping); 1872file_ra_state_init(struct file_ra_state *ra, struct address_space *mapping);
1871extern loff_t no_llseek(struct file *file, loff_t offset, int origin); 1873extern loff_t no_llseek(struct file *file, loff_t offset, int origin);
1872extern loff_t generic_file_llseek(struct file *file, loff_t offset, int origin); 1874extern loff_t generic_file_llseek(struct file *file, loff_t offset, int origin);
1873extern loff_t remote_llseek(struct file *file, loff_t offset, int origin); 1875extern loff_t generic_file_llseek_unlocked(struct file *file, loff_t offset,
1876 int origin);
1874extern int generic_file_open(struct inode * inode, struct file * filp); 1877extern int generic_file_open(struct inode * inode, struct file * filp);
1875extern int nonseekable_open(struct inode * inode, struct file * filp); 1878extern int nonseekable_open(struct inode * inode, struct file * filp);
1876 1879
diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
new file mode 100644
index 000000000000..f368d041e02d
--- /dev/null
+++ b/include/linux/ftrace.h
@@ -0,0 +1,144 @@
1#ifndef _LINUX_FTRACE_H
2#define _LINUX_FTRACE_H
3
4#ifdef CONFIG_FTRACE
5
6#include <linux/linkage.h>
7#include <linux/fs.h>
8
9extern int ftrace_enabled;
10extern int
11ftrace_enable_sysctl(struct ctl_table *table, int write,
12 struct file *filp, void __user *buffer, size_t *lenp,
13 loff_t *ppos);
14
15typedef void (*ftrace_func_t)(unsigned long ip, unsigned long parent_ip);
16
17struct ftrace_ops {
18 ftrace_func_t func;
19 struct ftrace_ops *next;
20};
21
22/*
23 * The ftrace_ops must be a static and should also
24 * be read_mostly. These functions do modify read_mostly variables
25 * so use them sparely. Never free an ftrace_op or modify the
26 * next pointer after it has been registered. Even after unregistering
27 * it, the next pointer may still be used internally.
28 */
29int register_ftrace_function(struct ftrace_ops *ops);
30int unregister_ftrace_function(struct ftrace_ops *ops);
31void clear_ftrace_function(void);
32
33extern void ftrace_stub(unsigned long a0, unsigned long a1);
34
35#else /* !CONFIG_FTRACE */
36# define register_ftrace_function(ops) do { } while (0)
37# define unregister_ftrace_function(ops) do { } while (0)
38# define clear_ftrace_function(ops) do { } while (0)
39#endif /* CONFIG_FTRACE */
40
41#ifdef CONFIG_DYNAMIC_FTRACE
42# define FTRACE_HASHBITS 10
43# define FTRACE_HASHSIZE (1<<FTRACE_HASHBITS)
44
45enum {
46 FTRACE_FL_FREE = (1 << 0),
47 FTRACE_FL_FAILED = (1 << 1),
48 FTRACE_FL_FILTER = (1 << 2),
49 FTRACE_FL_ENABLED = (1 << 3),
50 FTRACE_FL_NOTRACE = (1 << 4),
51 FTRACE_FL_CONVERTED = (1 << 5),
52 FTRACE_FL_FROZEN = (1 << 6),
53};
54
55struct dyn_ftrace {
56 struct hlist_node node;
57 unsigned long ip; /* address of mcount call-site */
58 unsigned long flags;
59};
60
61int ftrace_force_update(void);
62void ftrace_set_filter(unsigned char *buf, int len, int reset);
63
64/* defined in arch */
65extern int ftrace_ip_converted(unsigned long ip);
66extern unsigned char *ftrace_nop_replace(void);
67extern unsigned char *ftrace_call_replace(unsigned long ip, unsigned long addr);
68extern int ftrace_dyn_arch_init(void *data);
69extern int ftrace_mcount_set(unsigned long *data);
70extern int ftrace_modify_code(unsigned long ip, unsigned char *old_code,
71 unsigned char *new_code);
72extern int ftrace_update_ftrace_func(ftrace_func_t func);
73extern void ftrace_caller(void);
74extern void ftrace_call(void);
75extern void mcount_call(void);
76
77extern int skip_trace(unsigned long ip);
78
79void ftrace_disable_daemon(void);
80void ftrace_enable_daemon(void);
81
82#else
83# define skip_trace(ip) ({ 0; })
84# define ftrace_force_update() ({ 0; })
85# define ftrace_set_filter(buf, len, reset) do { } while (0)
86# define ftrace_disable_daemon() do { } while (0)
87# define ftrace_enable_daemon() do { } while (0)
88#endif /* CONFIG_DYNAMIC_FTRACE */
89
90/* totally disable ftrace - can not re-enable after this */
91void ftrace_kill(void);
92void ftrace_kill_atomic(void);
93
94static inline void tracer_disable(void)
95{
96#ifdef CONFIG_FTRACE
97 ftrace_enabled = 0;
98#endif
99}
100
101#ifdef CONFIG_FRAME_POINTER
102/* TODO: need to fix this for ARM */
103# define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
104# define CALLER_ADDR1 ((unsigned long)__builtin_return_address(1))
105# define CALLER_ADDR2 ((unsigned long)__builtin_return_address(2))
106# define CALLER_ADDR3 ((unsigned long)__builtin_return_address(3))
107# define CALLER_ADDR4 ((unsigned long)__builtin_return_address(4))
108# define CALLER_ADDR5 ((unsigned long)__builtin_return_address(5))
109# define CALLER_ADDR6 ((unsigned long)__builtin_return_address(6))
110#else
111# define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
112# define CALLER_ADDR1 0UL
113# define CALLER_ADDR2 0UL
114# define CALLER_ADDR3 0UL
115# define CALLER_ADDR4 0UL
116# define CALLER_ADDR5 0UL
117# define CALLER_ADDR6 0UL
118#endif
119
120#ifdef CONFIG_IRQSOFF_TRACER
121 extern void time_hardirqs_on(unsigned long a0, unsigned long a1);
122 extern void time_hardirqs_off(unsigned long a0, unsigned long a1);
123#else
124# define time_hardirqs_on(a0, a1) do { } while (0)
125# define time_hardirqs_off(a0, a1) do { } while (0)
126#endif
127
128#ifdef CONFIG_PREEMPT_TRACER
129 extern void trace_preempt_on(unsigned long a0, unsigned long a1);
130 extern void trace_preempt_off(unsigned long a0, unsigned long a1);
131#else
132# define trace_preempt_on(a0, a1) do { } while (0)
133# define trace_preempt_off(a0, a1) do { } while (0)
134#endif
135
136#ifdef CONFIG_TRACING
137extern void
138ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3);
139#else
140static inline void
141ftrace_special(unsigned long arg1, unsigned long arg2, unsigned long arg3) { }
142#endif
143
144#endif /* _LINUX_FTRACE_H */
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index ae7aec3cabee..e8787417f65a 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -110,6 +110,14 @@ struct hd_struct {
110#define GENHD_FL_SUPPRESS_PARTITION_INFO 32 110#define GENHD_FL_SUPPRESS_PARTITION_INFO 32
111#define GENHD_FL_FAIL 64 111#define GENHD_FL_FAIL 64
112 112
113#define BLK_SCSI_MAX_CMDS (256)
114#define BLK_SCSI_CMD_PER_LONG (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
115
116struct blk_scsi_cmd_filter {
117 unsigned long read_ok[BLK_SCSI_CMD_PER_LONG];
118 unsigned long write_ok[BLK_SCSI_CMD_PER_LONG];
119 struct kobject kobj;
120};
113 121
114struct gendisk { 122struct gendisk {
115 int major; /* major number of driver */ 123 int major; /* major number of driver */
@@ -120,6 +128,7 @@ struct gendisk {
120 struct hd_struct **part; /* [indexed by minor] */ 128 struct hd_struct **part; /* [indexed by minor] */
121 struct block_device_operations *fops; 129 struct block_device_operations *fops;
122 struct request_queue *queue; 130 struct request_queue *queue;
131 struct blk_scsi_cmd_filter cmd_filter;
123 void *private_data; 132 void *private_data;
124 sector_t capacity; 133 sector_t capacity;
125 134
@@ -141,6 +150,9 @@ struct gendisk {
141 struct disk_stats dkstats; 150 struct disk_stats dkstats;
142#endif 151#endif
143 struct work_struct async_notify; 152 struct work_struct async_notify;
153#ifdef CONFIG_BLK_DEV_INTEGRITY
154 struct blk_integrity *integrity;
155#endif
144}; 156};
145 157
146/* 158/*
diff --git a/include/linux/i2c-algo-pcf.h b/include/linux/i2c-algo-pcf.h
index 77afbb60fd11..0177d280f733 100644
--- a/include/linux/i2c-algo-pcf.h
+++ b/include/linux/i2c-algo-pcf.h
@@ -33,9 +33,11 @@ struct i2c_algo_pcf_data {
33 int (*getclock) (void *data); 33 int (*getclock) (void *data);
34 void (*waitforpin) (void); 34 void (*waitforpin) (void);
35 35
36 /* local settings */ 36 /* Multi-master lost arbitration back-off delay (msecs)
37 int udelay; 37 * This should be set by the bus adapter or knowledgable client
38 int timeout; 38 * if bus is multi-mastered, else zero
39 */
40 unsigned long lab_mdelay;
39}; 41};
40 42
41int i2c_pcf_add_bus(struct i2c_adapter *); 43int i2c_pcf_add_bus(struct i2c_adapter *);
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 580acc93903e..ef13b7c66df3 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -91,8 +91,6 @@
91#define I2C_DRIVERID_M52790 95 /* Mitsubishi M52790SP/FP AV switch */ 91#define I2C_DRIVERID_M52790 95 /* Mitsubishi M52790SP/FP AV switch */
92#define I2C_DRIVERID_CS5345 96 /* cs5345 audio processor */ 92#define I2C_DRIVERID_CS5345 96 /* cs5345 audio processor */
93 93
94#define I2C_DRIVERID_I2CDEV 900
95
96#define I2C_DRIVERID_OV7670 1048 /* Omnivision 7670 camera */ 94#define I2C_DRIVERID_OV7670 1048 /* Omnivision 7670 camera */
97 95
98/* 96/*
@@ -111,7 +109,6 @@
111#define I2C_HW_B_RIVA 0x010010 /* Riva based graphics cards */ 109#define I2C_HW_B_RIVA 0x010010 /* Riva based graphics cards */
112#define I2C_HW_B_IOC 0x010011 /* IOC bit-wiggling */ 110#define I2C_HW_B_IOC 0x010011 /* IOC bit-wiggling */
113#define I2C_HW_B_IXP2000 0x010016 /* GPIO on IXP2000 systems */ 111#define I2C_HW_B_IXP2000 0x010016 /* GPIO on IXP2000 systems */
114#define I2C_HW_B_S3VIA 0x010018 /* S3Via ProSavage adapter */
115#define I2C_HW_B_ZR36067 0x010019 /* Zoran-36057/36067 based boards */ 112#define I2C_HW_B_ZR36067 0x010019 /* Zoran-36057/36067 based boards */
116#define I2C_HW_B_PCILYNX 0x01001a /* TI PCILynx I2C adapter */ 113#define I2C_HW_B_PCILYNX 0x01001a /* TI PCILynx I2C adapter */
117#define I2C_HW_B_CX2388x 0x01001b /* connexant 2388x based tv cards */ 114#define I2C_HW_B_CX2388x 0x01001b /* connexant 2388x based tv cards */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 8dc730132192..08be0d21864c 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -35,6 +35,8 @@
35#include <linux/sched.h> /* for completion */ 35#include <linux/sched.h> /* for completion */
36#include <linux/mutex.h> 36#include <linux/mutex.h>
37 37
38extern struct bus_type i2c_bus_type;
39
38/* --- General options ------------------------------------------------ */ 40/* --- General options ------------------------------------------------ */
39 41
40struct i2c_msg; 42struct i2c_msg;
@@ -43,6 +45,7 @@ struct i2c_adapter;
43struct i2c_client; 45struct i2c_client;
44struct i2c_driver; 46struct i2c_driver;
45union i2c_smbus_data; 47union i2c_smbus_data;
48struct i2c_board_info;
46 49
47/* 50/*
48 * The master routines are the ones normally used to transmit data to devices 51 * The master routines are the ones normally used to transmit data to devices
@@ -69,9 +72,8 @@ extern s32 i2c_smbus_xfer (struct i2c_adapter * adapter, u16 addr,
69 union i2c_smbus_data * data); 72 union i2c_smbus_data * data);
70 73
71/* Now follow the 'nice' access routines. These also document the calling 74/* Now follow the 'nice' access routines. These also document the calling
72 conventions of smbus_access. */ 75 conventions of i2c_smbus_xfer. */
73 76
74extern s32 i2c_smbus_write_quick(struct i2c_client * client, u8 value);
75extern s32 i2c_smbus_read_byte(struct i2c_client * client); 77extern s32 i2c_smbus_read_byte(struct i2c_client * client);
76extern s32 i2c_smbus_write_byte(struct i2c_client * client, u8 value); 78extern s32 i2c_smbus_write_byte(struct i2c_client * client, u8 value);
77extern s32 i2c_smbus_read_byte_data(struct i2c_client * client, u8 command); 79extern s32 i2c_smbus_read_byte_data(struct i2c_client * client, u8 command);
@@ -93,15 +95,33 @@ extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client,
93 u8 command, u8 length, 95 u8 command, u8 length,
94 const u8 *values); 96 const u8 *values);
95 97
96/* 98/**
97 * A driver is capable of handling one or more physical devices present on 99 * struct i2c_driver - represent an I2C device driver
98 * I2C adapters. This information is used to inform the driver of adapter 100 * @class: What kind of i2c device we instantiate (for detect)
99 * events. 101 * @detect: Callback for device detection
102 * @address_data: The I2C addresses to probe, ignore or force (for detect)
103 * @clients: List of detected clients we created (for i2c-core use only)
100 * 104 *
101 * The driver.owner field should be set to the module owner of this driver. 105 * The driver.owner field should be set to the module owner of this driver.
102 * The driver.name field should be set to the name of this driver. 106 * The driver.name field should be set to the name of this driver.
107 *
108 * For automatic device detection, both @detect and @address_data must
109 * be defined. @class should also be set, otherwise only devices forced
110 * with module parameters will be created. The detect function must
111 * fill at least the name field of the i2c_board_info structure it is
112 * handed upon successful detection, and possibly also the flags field.
113 *
114 * If @detect is missing, the driver will still work fine for enumerated
115 * devices. Detected devices simply won't be supported. This is expected
116 * for the many I2C/SMBus devices which can't be detected reliably, and
117 * the ones which can always be enumerated in practice.
118 *
119 * The i2c_client structure which is handed to the @detect callback is
120 * not a real i2c_client. It is initialized just enough so that you can
121 * call i2c_smbus_read_byte_data and friends on it. Don't do anything
122 * else with it. In particular, calling dev_dbg and friends on it is
123 * not allowed.
103 */ 124 */
104
105struct i2c_driver { 125struct i2c_driver {
106 int id; 126 int id;
107 unsigned int class; 127 unsigned int class;
@@ -141,6 +161,11 @@ struct i2c_driver {
141 161
142 struct device_driver driver; 162 struct device_driver driver;
143 const struct i2c_device_id *id_table; 163 const struct i2c_device_id *id_table;
164
165 /* Device detection callback for automatic device creation */
166 int (*detect)(struct i2c_client *, int kind, struct i2c_board_info *);
167 const struct i2c_client_address_data *address_data;
168 struct list_head clients;
144}; 169};
145#define to_i2c_driver(d) container_of(d, struct i2c_driver, driver) 170#define to_i2c_driver(d) container_of(d, struct i2c_driver, driver)
146 171
@@ -156,6 +181,7 @@ struct i2c_driver {
156 * @dev: Driver model device node for the slave. 181 * @dev: Driver model device node for the slave.
157 * @irq: indicates the IRQ generated by this device (if any) 182 * @irq: indicates the IRQ generated by this device (if any)
158 * @list: list of active/busy clients (DEPRECATED) 183 * @list: list of active/busy clients (DEPRECATED)
184 * @detected: member of an i2c_driver.clients list
159 * @released: used to synchronize client releases & detaches and references 185 * @released: used to synchronize client releases & detaches and references
160 * 186 *
161 * An i2c_client identifies a single device (i.e. chip) connected to an 187 * An i2c_client identifies a single device (i.e. chip) connected to an
@@ -173,6 +199,7 @@ struct i2c_client {
173 struct device dev; /* the device structure */ 199 struct device dev; /* the device structure */
174 int irq; /* irq issued by device */ 200 int irq; /* irq issued by device */
175 struct list_head list; /* DEPRECATED */ 201 struct list_head list; /* DEPRECATED */
202 struct list_head detected;
176 struct completion released; 203 struct completion released;
177}; 204};
178#define to_i2c_client(d) container_of(d, struct i2c_client, dev) 205#define to_i2c_client(d) container_of(d, struct i2c_client, dev)
@@ -350,10 +377,11 @@ static inline void i2c_set_adapdata (struct i2c_adapter *dev, void *data)
350#define I2C_CLASS_HWMON (1<<0) /* lm_sensors, ... */ 377#define I2C_CLASS_HWMON (1<<0) /* lm_sensors, ... */
351#define I2C_CLASS_TV_ANALOG (1<<1) /* bttv + friends */ 378#define I2C_CLASS_TV_ANALOG (1<<1) /* bttv + friends */
352#define I2C_CLASS_TV_DIGITAL (1<<2) /* dvb cards */ 379#define I2C_CLASS_TV_DIGITAL (1<<2) /* dvb cards */
353#define I2C_CLASS_DDC (1<<3) /* i2c-matroxfb ? */ 380#define I2C_CLASS_DDC (1<<3) /* DDC bus on graphics adapters */
354#define I2C_CLASS_CAM_ANALOG (1<<4) /* camera with analog CCD */ 381#define I2C_CLASS_CAM_ANALOG (1<<4) /* camera with analog CCD */
355#define I2C_CLASS_CAM_DIGITAL (1<<5) /* most webcams */ 382#define I2C_CLASS_CAM_DIGITAL (1<<5) /* most webcams */
356#define I2C_CLASS_SOUND (1<<6) /* sound devices */ 383#define I2C_CLASS_SOUND (1<<6) /* sound devices */
384#define I2C_CLASS_SPD (1<<7) /* SPD EEPROMs and similar */
357#define I2C_CLASS_ALL (UINT_MAX) /* all of the above */ 385#define I2C_CLASS_ALL (UINT_MAX) /* all of the above */
358 386
359/* i2c_client_address_data is the struct for holding default client 387/* i2c_client_address_data is the struct for holding default client
@@ -537,7 +565,7 @@ union i2c_smbus_data {
537 /* and one more for user-space compatibility */ 565 /* and one more for user-space compatibility */
538}; 566};
539 567
540/* smbus_access read or write markers */ 568/* i2c_smbus_xfer read or write markers */
541#define I2C_SMBUS_READ 1 569#define I2C_SMBUS_READ 1
542#define I2C_SMBUS_WRITE 0 570#define I2C_SMBUS_WRITE 0
543 571
diff --git a/include/linux/i2c/at24.h b/include/linux/i2c/at24.h
new file mode 100644
index 000000000000..f6edd522a929
--- /dev/null
+++ b/include/linux/i2c/at24.h
@@ -0,0 +1,28 @@
1#ifndef _LINUX_AT24_H
2#define _LINUX_AT24_H
3
4#include <linux/types.h>
5
6/*
7 * As seen through Linux I2C, differences between the most common types of I2C
8 * memory include:
9 * - How much memory is available (usually specified in bit)?
10 * - What write page size does it support?
11 * - Special flags (16 bit addresses, read_only, world readable...)?
12 *
13 * If you set up a custom eeprom type, please double-check the parameters.
14 * Especially page_size needs extra care, as you risk data loss if your value
15 * is bigger than what the chip actually supports!
16 */
17
18struct at24_platform_data {
19 u32 byte_len; /* size (sum of all addr) */
20 u16 page_size; /* for writes */
21 u8 flags;
22#define AT24_FLAG_ADDR16 0x80 /* address pointer is 16 bit */
23#define AT24_FLAG_READONLY 0x40 /* sysfs-entry will be read-only */
24#define AT24_FLAG_IRUGO 0x20 /* sysfs-entry will be world-readable */
25#define AT24_FLAG_TAKE8ADDR 0x10 /* take always 8 addresses (24c00) */
26};
27
28#endif /* _LINUX_AT24_H */
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 9918772bf274..ac4eeb2932ef 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -189,6 +189,21 @@ static inline void ide_std_init_ports(hw_regs_t *hw,
189 hw->io_ports.ctl_addr = ctl_addr; 189 hw->io_ports.ctl_addr = ctl_addr;
190} 190}
191 191
192/* for IDE PCI controllers in legacy mode, temporary */
193static inline int __ide_default_irq(unsigned long base)
194{
195 switch (base) {
196#ifdef CONFIG_IA64
197 case 0x1f0: return isa_irq_to_vector(14);
198 case 0x170: return isa_irq_to_vector(15);
199#else
200 case 0x1f0: return 14;
201 case 0x170: return 15;
202#endif
203 }
204 return 0;
205}
206
192#include <asm/ide.h> 207#include <asm/ide.h>
193 208
194#if !defined(MAX_HWIFS) || defined(CONFIG_EMBEDDED) 209#if !defined(MAX_HWIFS) || defined(CONFIG_EMBEDDED)
@@ -349,7 +364,6 @@ typedef struct ide_drive_s {
349 u8 wcache; /* status of write cache */ 364 u8 wcache; /* status of write cache */
350 u8 acoustic; /* acoustic management */ 365 u8 acoustic; /* acoustic management */
351 u8 media; /* disk, cdrom, tape, floppy, ... */ 366 u8 media; /* disk, cdrom, tape, floppy, ... */
352 u8 ctl; /* "normal" value for Control register */
353 u8 ready_stat; /* min status value for drive ready */ 367 u8 ready_stat; /* min status value for drive ready */
354 u8 mult_count; /* current multiple sector setting */ 368 u8 mult_count; /* current multiple sector setting */
355 u8 mult_req; /* requested multiple sector setting */ 369 u8 mult_req; /* requested multiple sector setting */
@@ -478,7 +492,7 @@ typedef struct hwif_s {
478 void (*ide_dma_clear_irq)(ide_drive_t *drive); 492 void (*ide_dma_clear_irq)(ide_drive_t *drive);
479 493
480 void (*OUTB)(u8 addr, unsigned long port); 494 void (*OUTB)(u8 addr, unsigned long port);
481 void (*OUTBSYNC)(ide_drive_t *drive, u8 addr, unsigned long port); 495 void (*OUTBSYNC)(struct hwif_s *hwif, u8 addr, unsigned long port);
482 496
483 u8 (*INB)(unsigned long port); 497 u8 (*INB)(unsigned long port);
484 498
@@ -517,7 +531,6 @@ typedef struct hwif_s {
517 unsigned serialized : 1; /* serialized all channel operation */ 531 unsigned serialized : 1; /* serialized all channel operation */
518 unsigned sharing_irq: 1; /* 1 = sharing irq with another hwif */ 532 unsigned sharing_irq: 1; /* 1 = sharing irq with another hwif */
519 unsigned sg_mapped : 1; /* sg_table and sg_nents are ready */ 533 unsigned sg_mapped : 1; /* sg_table and sg_nents are ready */
520 unsigned mmio : 1; /* host uses MMIO */
521 534
522 struct device gendev; 535 struct device gendev;
523 struct device *portdev; 536 struct device *portdev;
@@ -589,12 +602,13 @@ enum {
589 PC_FLAG_SUPPRESS_ERROR = (1 << 1), 602 PC_FLAG_SUPPRESS_ERROR = (1 << 1),
590 PC_FLAG_WAIT_FOR_DSC = (1 << 2), 603 PC_FLAG_WAIT_FOR_DSC = (1 << 2),
591 PC_FLAG_DMA_OK = (1 << 3), 604 PC_FLAG_DMA_OK = (1 << 3),
592 PC_FLAG_DMA_RECOMMENDED = (1 << 4), 605 PC_FLAG_DMA_IN_PROGRESS = (1 << 4),
593 PC_FLAG_DMA_IN_PROGRESS = (1 << 5), 606 PC_FLAG_DMA_ERROR = (1 << 5),
594 PC_FLAG_DMA_ERROR = (1 << 6), 607 PC_FLAG_WRITING = (1 << 6),
595 PC_FLAG_WRITING = (1 << 7),
596 /* command timed out */ 608 /* command timed out */
597 PC_FLAG_TIMEDOUT = (1 << 8), 609 PC_FLAG_TIMEDOUT = (1 << 7),
610 PC_FLAG_ZIP_DRIVE = (1 << 8),
611 PC_FLAG_DRQ_INTERRUPT = (1 << 9),
598}; 612};
599 613
600struct ide_atapi_pc { 614struct ide_atapi_pc {
@@ -627,8 +641,8 @@ struct ide_atapi_pc {
627 * to change/removal later. 641 * to change/removal later.
628 */ 642 */
629 u8 pc_buf[256]; 643 u8 pc_buf[256];
630 void (*idefloppy_callback) (ide_drive_t *); 644
631 ide_startstop_t (*idetape_callback) (ide_drive_t *); 645 void (*callback)(ide_drive_t *);
632 646
633 /* idetape only */ 647 /* idetape only */
634 struct idetape_bh *bh; 648 struct idetape_bh *bh;
@@ -798,10 +812,6 @@ int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsig
798#ifndef _IDE_C 812#ifndef _IDE_C
799extern ide_hwif_t ide_hwifs[]; /* master data repository */ 813extern ide_hwif_t ide_hwifs[]; /* master data repository */
800#endif 814#endif
801extern int ide_noacpi;
802extern int ide_acpigtf;
803extern int ide_acpionboot;
804extern int noautodma;
805 815
806extern int ide_vlb_clk; 816extern int ide_vlb_clk;
807extern int ide_pci_clk; 817extern int ide_pci_clk;
@@ -842,25 +852,12 @@ int ide_wait_stat(ide_startstop_t *, ide_drive_t *, u8, u8, unsigned long);
842 852
843extern ide_startstop_t ide_do_reset (ide_drive_t *); 853extern ide_startstop_t ide_do_reset (ide_drive_t *);
844 854
845extern void ide_init_drive_cmd (struct request *rq); 855extern void ide_do_drive_cmd(ide_drive_t *, struct request *);
846
847/*
848 * "action" parameter type for ide_do_drive_cmd() below.
849 */
850typedef enum {
851 ide_wait, /* insert rq at end of list, and wait for it */
852 ide_preempt, /* insert rq in front of current request */
853 ide_head_wait, /* insert rq in front of current request and wait for it */
854 ide_end /* insert rq at end of list, but don't wait for it */
855} ide_action_t;
856
857extern int ide_do_drive_cmd(ide_drive_t *, struct request *, ide_action_t);
858 856
859extern void ide_end_drive_cmd(ide_drive_t *, u8, u8); 857extern void ide_end_drive_cmd(ide_drive_t *, u8, u8);
860 858
861enum { 859enum {
862 IDE_TFLAG_LBA48 = (1 << 0), 860 IDE_TFLAG_LBA48 = (1 << 0),
863 IDE_TFLAG_NO_SELECT_MASK = (1 << 1),
864 IDE_TFLAG_FLAGGED = (1 << 2), 861 IDE_TFLAG_FLAGGED = (1 << 2),
865 IDE_TFLAG_OUT_DATA = (1 << 3), 862 IDE_TFLAG_OUT_DATA = (1 << 3),
866 IDE_TFLAG_OUT_HOB_FEATURE = (1 << 4), 863 IDE_TFLAG_OUT_HOB_FEATURE = (1 << 4),
@@ -965,11 +962,23 @@ typedef struct ide_task_s {
965void ide_tf_dump(const char *, struct ide_taskfile *); 962void ide_tf_dump(const char *, struct ide_taskfile *);
966 963
967extern void SELECT_DRIVE(ide_drive_t *); 964extern void SELECT_DRIVE(ide_drive_t *);
965void SELECT_MASK(ide_drive_t *, int);
968 966
969extern int drive_is_ready(ide_drive_t *); 967extern int drive_is_ready(ide_drive_t *);
970 968
971void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8); 969void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8);
972 970
971ide_startstop_t ide_pc_intr(ide_drive_t *drive, struct ide_atapi_pc *pc,
972 ide_handler_t *handler, unsigned int timeout, ide_expiry_t *expiry,
973 void (*update_buffers)(ide_drive_t *, struct ide_atapi_pc *),
974 void (*retry_pc)(ide_drive_t *), void (*dsc_handle)(ide_drive_t *),
975 void (*io_buffers)(ide_drive_t *, struct ide_atapi_pc *, unsigned int,
976 int));
977ide_startstop_t ide_transfer_pc(ide_drive_t *, struct ide_atapi_pc *,
978 ide_handler_t *, unsigned int, ide_expiry_t *);
979ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_atapi_pc *,
980 ide_handler_t *, unsigned int, ide_expiry_t *);
981
973ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *); 982ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *);
974 983
975void task_end_request(ide_drive_t *, struct request *, u8); 984void task_end_request(ide_drive_t *, struct request *, u8);
@@ -981,8 +990,6 @@ int ide_taskfile_ioctl(ide_drive_t *, unsigned int, unsigned long);
981int ide_cmd_ioctl(ide_drive_t *, unsigned int, unsigned long); 990int ide_cmd_ioctl(ide_drive_t *, unsigned int, unsigned long);
982int ide_task_ioctl(ide_drive_t *, unsigned int, unsigned long); 991int ide_task_ioctl(ide_drive_t *, unsigned int, unsigned long);
983 992
984extern int system_bus_clock(void);
985
986extern int ide_driveid_update(ide_drive_t *); 993extern int ide_driveid_update(ide_drive_t *);
987extern int ide_config_drive_speed(ide_drive_t *, u8); 994extern int ide_config_drive_speed(ide_drive_t *, u8);
988extern u8 eighty_ninty_three (ide_drive_t *); 995extern u8 eighty_ninty_three (ide_drive_t *);
@@ -1334,7 +1341,8 @@ static inline void ide_set_irq(ide_drive_t *drive, int on)
1334{ 1341{
1335 ide_hwif_t *hwif = drive->hwif; 1342 ide_hwif_t *hwif = drive->hwif;
1336 1343
1337 hwif->OUTB(drive->ctl | (on ? 0 : 2), hwif->io_ports.ctl_addr); 1344 hwif->OUTBSYNC(hwif, ATA_DEVCTL_OBS | (on ? 0 : 2),
1345 hwif->io_ports.ctl_addr);
1338} 1346}
1339 1347
1340static inline u8 ide_read_status(ide_drive_t *drive) 1348static inline u8 ide_read_status(ide_drive_t *drive)
diff --git a/include/linux/ihex.h b/include/linux/ihex.h
new file mode 100644
index 000000000000..2baace2788a7
--- /dev/null
+++ b/include/linux/ihex.h
@@ -0,0 +1,74 @@
1/*
2 * Compact binary representation of ihex records. Some devices need their
3 * firmware loaded in strange orders rather than a single big blob, but
4 * actually parsing ihex-as-text within the kernel seems silly. Thus,...
5 */
6
7#ifndef __LINUX_IHEX_H__
8#define __LINUX_IHEX_H__
9
10#include <linux/types.h>
11#include <linux/firmware.h>
12#include <linux/device.h>
13
14/* Intel HEX files actually limit the length to 256 bytes, but we have
15 drivers which would benefit from using separate records which are
16 longer than that, so we extend to 16 bits of length */
17struct ihex_binrec {
18 __be32 addr;
19 __be16 len;
20 uint8_t data[0];
21} __attribute__((aligned(4)));
22
23/* Find the next record, taking into account the 4-byte alignment */
24static inline const struct ihex_binrec *
25ihex_next_binrec(const struct ihex_binrec *rec)
26{
27 int next = ((be16_to_cpu(rec->len) + 5) & ~3) - 2;
28 rec = (void *)&rec->data[next];
29
30 return be16_to_cpu(rec->len) ? rec : NULL;
31}
32
33/* Check that ihex_next_binrec() won't take us off the end of the image... */
34static inline int ihex_validate_fw(const struct firmware *fw)
35{
36 const struct ihex_binrec *rec;
37 size_t ofs = 0;
38
39 while (ofs <= fw->size - sizeof(*rec)) {
40 rec = (void *)&fw->data[ofs];
41
42 /* Zero length marks end of records */
43 if (!be16_to_cpu(rec->len))
44 return 0;
45
46 /* Point to next record... */
47 ofs += (sizeof(*rec) + be16_to_cpu(rec->len) + 3) & ~3;
48 }
49 return -EINVAL;
50}
51
52/* Request firmware and validate it so that we can trust we won't
53 * run off the end while reading records... */
54static inline int request_ihex_firmware(const struct firmware **fw,
55 const char *fw_name,
56 struct device *dev)
57{
58 const struct firmware *lfw;
59 int ret;
60
61 ret = request_firmware(&lfw, fw_name, dev);
62 if (ret)
63 return ret;
64 ret = ihex_validate_fw(lfw);
65 if (ret) {
66 dev_err(dev, "Firmware \"%s\" not valid IHEX records\n",
67 fw_name);
68 release_firmware(lfw);
69 return ret;
70 }
71 *fw = lfw;
72 return 0;
73}
74#endif /* __LINUX_IHEX_H__ */
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index f1fc7470d26c..62aa4f895abe 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -104,8 +104,11 @@ extern void enable_irq(unsigned int irq);
104 104
105#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) 105#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS)
106 106
107extern cpumask_t irq_default_affinity;
108
107extern int irq_set_affinity(unsigned int irq, cpumask_t cpumask); 109extern int irq_set_affinity(unsigned int irq, cpumask_t cpumask);
108extern int irq_can_set_affinity(unsigned int irq); 110extern int irq_can_set_affinity(unsigned int irq);
111extern int irq_select_affinity(unsigned int irq);
109 112
110#else /* CONFIG_SMP */ 113#else /* CONFIG_SMP */
111 114
@@ -119,6 +122,8 @@ static inline int irq_can_set_affinity(unsigned int irq)
119 return 0; 122 return 0;
120} 123}
121 124
125static inline int irq_select_affinity(unsigned int irq) { return 0; }
126
122#endif /* CONFIG_SMP && CONFIG_GENERIC_HARDIRQS */ 127#endif /* CONFIG_SMP && CONFIG_GENERIC_HARDIRQS */
123 128
124#ifdef CONFIG_GENERIC_HARDIRQS 129#ifdef CONFIG_GENERIC_HARDIRQS
@@ -285,12 +290,11 @@ enum
285struct softirq_action 290struct softirq_action
286{ 291{
287 void (*action)(struct softirq_action *); 292 void (*action)(struct softirq_action *);
288 void *data;
289}; 293};
290 294
291asmlinkage void do_softirq(void); 295asmlinkage void do_softirq(void);
292asmlinkage void __do_softirq(void); 296asmlinkage void __do_softirq(void);
293extern void open_softirq(int nr, void (*action)(struct softirq_action*), void *data); 297extern void open_softirq(int nr, void (*action)(struct softirq_action *));
294extern void softirq_init(void); 298extern void softirq_init(void);
295#define __raise_softirq_irqoff(nr) do { or_softirq_pending(1UL << (nr)); } while (0) 299#define __raise_softirq_irqoff(nr) do { or_softirq_pending(1UL << (nr)); } while (0)
296extern void raise_softirq_irqoff(unsigned int nr); 300extern void raise_softirq_irqoff(unsigned int nr);
diff --git a/include/linux/iocontext.h b/include/linux/iocontext.h
index 2b7a1187cb29..08b987bccf89 100644
--- a/include/linux/iocontext.h
+++ b/include/linux/iocontext.h
@@ -99,4 +99,22 @@ static inline struct io_context *ioc_task_link(struct io_context *ioc)
99 return NULL; 99 return NULL;
100} 100}
101 101
102#ifdef CONFIG_BLOCK
103int put_io_context(struct io_context *ioc);
104void exit_io_context(void);
105struct io_context *get_io_context(gfp_t gfp_flags, int node);
106struct io_context *alloc_io_context(gfp_t gfp_flags, int node);
107void copy_io_context(struct io_context **pdst, struct io_context **psrc);
108#else
109static inline void exit_io_context(void)
110{
111}
112
113struct io_context;
114static inline int put_io_context(struct io_context *ioc)
115{
116 return 1;
117}
118#endif
119
102#endif 120#endif
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 552e0ec269c9..8ccb462ea42c 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -244,15 +244,6 @@ static inline void set_balance_irq_affinity(unsigned int irq, cpumask_t mask)
244} 244}
245#endif 245#endif
246 246
247#ifdef CONFIG_AUTO_IRQ_AFFINITY
248extern int select_smp_affinity(unsigned int irq);
249#else
250static inline int select_smp_affinity(unsigned int irq)
251{
252 return 1;
253}
254#endif
255
256extern int no_irq_affinity; 247extern int no_irq_affinity;
257 248
258static inline int irq_balancing_disabled(unsigned int irq) 249static inline int irq_balancing_disabled(unsigned int irq)
diff --git a/include/linux/irqflags.h b/include/linux/irqflags.h
index e600c4e9b8c5..2b1c2e58566e 100644
--- a/include/linux/irqflags.h
+++ b/include/linux/irqflags.h
@@ -12,10 +12,10 @@
12#define _LINUX_TRACE_IRQFLAGS_H 12#define _LINUX_TRACE_IRQFLAGS_H
13 13
14#ifdef CONFIG_TRACE_IRQFLAGS 14#ifdef CONFIG_TRACE_IRQFLAGS
15 extern void trace_hardirqs_on(void);
16 extern void trace_hardirqs_off(void);
17 extern void trace_softirqs_on(unsigned long ip); 15 extern void trace_softirqs_on(unsigned long ip);
18 extern void trace_softirqs_off(unsigned long ip); 16 extern void trace_softirqs_off(unsigned long ip);
17 extern void trace_hardirqs_on(void);
18 extern void trace_hardirqs_off(void);
19# define trace_hardirq_context(p) ((p)->hardirq_context) 19# define trace_hardirq_context(p) ((p)->hardirq_context)
20# define trace_softirq_context(p) ((p)->softirq_context) 20# define trace_softirq_context(p) ((p)->softirq_context)
21# define trace_hardirqs_enabled(p) ((p)->hardirqs_enabled) 21# define trace_hardirqs_enabled(p) ((p)->hardirqs_enabled)
@@ -41,6 +41,15 @@
41# define INIT_TRACE_IRQFLAGS 41# define INIT_TRACE_IRQFLAGS
42#endif 42#endif
43 43
44#if defined(CONFIG_IRQSOFF_TRACER) || \
45 defined(CONFIG_PREEMPT_TRACER)
46 extern void stop_critical_timings(void);
47 extern void start_critical_timings(void);
48#else
49# define stop_critical_timings() do { } while (0)
50# define start_critical_timings() do { } while (0)
51#endif
52
44#ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT 53#ifdef CONFIG_TRACE_IRQFLAGS_SUPPORT
45 54
46#include <asm/irqflags.h> 55#include <asm/irqflags.h>
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index d147f0f90360..3dd209007098 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -168,6 +168,8 @@ struct commit_header {
168 unsigned char h_chksum_size; 168 unsigned char h_chksum_size;
169 unsigned char h_padding[2]; 169 unsigned char h_padding[2];
170 __be32 h_chksum[JBD2_CHECKSUM_BYTES]; 170 __be32 h_chksum[JBD2_CHECKSUM_BYTES];
171 __be64 h_commit_sec;
172 __be32 h_commit_nsec;
171}; 173};
172 174
173/* 175/*
@@ -379,6 +381,38 @@ static inline void jbd_unlock_bh_journal_head(struct buffer_head *bh)
379 bit_spin_unlock(BH_JournalHead, &bh->b_state); 381 bit_spin_unlock(BH_JournalHead, &bh->b_state);
380} 382}
381 383
384/* Flags in jbd_inode->i_flags */
385#define __JI_COMMIT_RUNNING 0
386/* Commit of the inode data in progress. We use this flag to protect us from
387 * concurrent deletion of inode. We cannot use reference to inode for this
388 * since we cannot afford doing last iput() on behalf of kjournald
389 */
390#define JI_COMMIT_RUNNING (1 << __JI_COMMIT_RUNNING)
391
392/**
393 * struct jbd_inode is the structure linking inodes in ordered mode
394 * present in a transaction so that we can sync them during commit.
395 */
396struct jbd2_inode {
397 /* Which transaction does this inode belong to? Either the running
398 * transaction or the committing one. [j_list_lock] */
399 transaction_t *i_transaction;
400
401 /* Pointer to the running transaction modifying inode's data in case
402 * there is already a committing transaction touching it. [j_list_lock] */
403 transaction_t *i_next_transaction;
404
405 /* List of inodes in the i_transaction [j_list_lock] */
406 struct list_head i_list;
407
408 /* VFS inode this inode belongs to [constant during the lifetime
409 * of the structure] */
410 struct inode *i_vfs_inode;
411
412 /* Flags of inode [j_list_lock] */
413 unsigned int i_flags;
414};
415
382struct jbd2_revoke_table_s; 416struct jbd2_revoke_table_s;
383 417
384/** 418/**
@@ -509,24 +543,12 @@ struct transaction_s
509 struct journal_head *t_reserved_list; 543 struct journal_head *t_reserved_list;
510 544
511 /* 545 /*
512 * Doubly-linked circular list of all buffers under writeout during
513 * commit [j_list_lock]
514 */
515 struct journal_head *t_locked_list;
516
517 /*
518 * Doubly-linked circular list of all metadata buffers owned by this 546 * Doubly-linked circular list of all metadata buffers owned by this
519 * transaction [j_list_lock] 547 * transaction [j_list_lock]
520 */ 548 */
521 struct journal_head *t_buffers; 549 struct journal_head *t_buffers;
522 550
523 /* 551 /*
524 * Doubly-linked circular list of all data buffers still to be
525 * flushed before this transaction can be committed [j_list_lock]
526 */
527 struct journal_head *t_sync_datalist;
528
529 /*
530 * Doubly-linked circular list of all forget buffers (superseded 552 * Doubly-linked circular list of all forget buffers (superseded
531 * buffers which we can un-checkpoint once this transaction commits) 553 * buffers which we can un-checkpoint once this transaction commits)
532 * [j_list_lock] 554 * [j_list_lock]
@@ -565,6 +587,12 @@ struct transaction_s
565 struct journal_head *t_log_list; 587 struct journal_head *t_log_list;
566 588
567 /* 589 /*
590 * List of inodes whose data we've modified in data=ordered mode.
591 * [j_list_lock]
592 */
593 struct list_head t_inode_list;
594
595 /*
568 * Protects info related to handles 596 * Protects info related to handles
569 */ 597 */
570 spinlock_t t_handle_lock; 598 spinlock_t t_handle_lock;
@@ -1004,7 +1032,6 @@ extern int jbd2_journal_extend (handle_t *, int nblocks);
1004extern int jbd2_journal_get_write_access(handle_t *, struct buffer_head *); 1032extern int jbd2_journal_get_write_access(handle_t *, struct buffer_head *);
1005extern int jbd2_journal_get_create_access (handle_t *, struct buffer_head *); 1033extern int jbd2_journal_get_create_access (handle_t *, struct buffer_head *);
1006extern int jbd2_journal_get_undo_access(handle_t *, struct buffer_head *); 1034extern int jbd2_journal_get_undo_access(handle_t *, struct buffer_head *);
1007extern int jbd2_journal_dirty_data (handle_t *, struct buffer_head *);
1008extern int jbd2_journal_dirty_metadata (handle_t *, struct buffer_head *); 1035extern int jbd2_journal_dirty_metadata (handle_t *, struct buffer_head *);
1009extern void jbd2_journal_release_buffer (handle_t *, struct buffer_head *); 1036extern void jbd2_journal_release_buffer (handle_t *, struct buffer_head *);
1010extern int jbd2_journal_forget (handle_t *, struct buffer_head *); 1037extern int jbd2_journal_forget (handle_t *, struct buffer_head *);
@@ -1044,6 +1071,10 @@ extern void jbd2_journal_ack_err (journal_t *);
1044extern int jbd2_journal_clear_err (journal_t *); 1071extern int jbd2_journal_clear_err (journal_t *);
1045extern int jbd2_journal_bmap(journal_t *, unsigned long, unsigned long long *); 1072extern int jbd2_journal_bmap(journal_t *, unsigned long, unsigned long long *);
1046extern int jbd2_journal_force_commit(journal_t *); 1073extern int jbd2_journal_force_commit(journal_t *);
1074extern int jbd2_journal_file_inode(handle_t *handle, struct jbd2_inode *inode);
1075extern int jbd2_journal_begin_ordered_truncate(struct jbd2_inode *inode, loff_t new_size);
1076extern void jbd2_journal_init_jbd_inode(struct jbd2_inode *jinode, struct inode *inode);
1077extern void jbd2_journal_release_jbd_inode(journal_t *journal, struct jbd2_inode *jinode);
1047 1078
1048/* 1079/*
1049 * journal_head management 1080 * journal_head management
@@ -1179,15 +1210,13 @@ static inline int jbd_space_needed(journal_t *journal)
1179 1210
1180/* journaling buffer types */ 1211/* journaling buffer types */
1181#define BJ_None 0 /* Not journaled */ 1212#define BJ_None 0 /* Not journaled */
1182#define BJ_SyncData 1 /* Normal data: flush before commit */ 1213#define BJ_Metadata 1 /* Normal journaled metadata */
1183#define BJ_Metadata 2 /* Normal journaled metadata */ 1214#define BJ_Forget 2 /* Buffer superseded by this transaction */
1184#define BJ_Forget 3 /* Buffer superseded by this transaction */ 1215#define BJ_IO 3 /* Buffer is for temporary IO use */
1185#define BJ_IO 4 /* Buffer is for temporary IO use */ 1216#define BJ_Shadow 4 /* Buffer contents being shadowed to the log */
1186#define BJ_Shadow 5 /* Buffer contents being shadowed to the log */ 1217#define BJ_LogCtl 5 /* Buffer contains log descriptors */
1187#define BJ_LogCtl 6 /* Buffer contains log descriptors */ 1218#define BJ_Reserved 6 /* Buffer is reserved for access by journal */
1188#define BJ_Reserved 7 /* Buffer is reserved for access by journal */ 1219#define BJ_Types 7
1189#define BJ_Locked 8 /* Locked for I/O during commit */
1190#define BJ_Types 9
1191 1220
1192extern int jbd_blocks_per_page(struct inode *inode); 1221extern int jbd_blocks_per_page(struct inode *inode);
1193 1222
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 2e70006c7fa8..f9cd7a513f9c 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -187,9 +187,6 @@ asmlinkage int vprintk(const char *fmt, va_list args)
187 __attribute__ ((format (printf, 1, 0))); 187 __attribute__ ((format (printf, 1, 0)));
188asmlinkage int printk(const char * fmt, ...) 188asmlinkage int printk(const char * fmt, ...)
189 __attribute__ ((format (printf, 1, 2))) __cold; 189 __attribute__ ((format (printf, 1, 2))) __cold;
190extern int log_buf_get_len(void);
191extern int log_buf_read(int idx);
192extern int log_buf_copy(char *dest, int idx, int len);
193 190
194extern int printk_ratelimit_jiffies; 191extern int printk_ratelimit_jiffies;
195extern int printk_ratelimit_burst; 192extern int printk_ratelimit_burst;
@@ -205,9 +202,6 @@ static inline int vprintk(const char *s, va_list args) { return 0; }
205static inline int printk(const char *s, ...) 202static inline int printk(const char *s, ...)
206 __attribute__ ((format (printf, 1, 2))); 203 __attribute__ ((format (printf, 1, 2)));
207static inline int __cold printk(const char *s, ...) { return 0; } 204static inline int __cold printk(const char *s, ...) { return 0; }
208static inline int log_buf_get_len(void) { return 0; }
209static inline int log_buf_read(int idx) { return 0; }
210static inline int log_buf_copy(char *dest, int idx, int len) { return 0; }
211static inline int printk_ratelimit(void) { return 0; } 205static inline int printk_ratelimit(void) { return 0; }
212static inline int __printk_ratelimit(int ratelimit_jiffies, \ 206static inline int __printk_ratelimit(int ratelimit_jiffies, \
213 int ratelimit_burst) { return 0; } 207 int ratelimit_burst) { return 0; }
@@ -216,7 +210,7 @@ static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \
216 { return false; } 210 { return false; }
217#endif 211#endif
218 212
219extern void __attribute__((format(printf, 1, 2))) 213extern void asmlinkage __attribute__((format(printf, 1, 2)))
220 early_printk(const char *fmt, ...); 214 early_printk(const char *fmt, ...);
221 215
222unsigned long int_sqrt(unsigned long); 216unsigned long int_sqrt(unsigned long);
diff --git a/include/linux/kernel_stat.h b/include/linux/kernel_stat.h
index e8ffce898bf9..cf9f40a91c9c 100644
--- a/include/linux/kernel_stat.h
+++ b/include/linux/kernel_stat.h
@@ -1,11 +1,11 @@
1#ifndef _LINUX_KERNEL_STAT_H 1#ifndef _LINUX_KERNEL_STAT_H
2#define _LINUX_KERNEL_STAT_H 2#define _LINUX_KERNEL_STAT_H
3 3
4#include <asm/irq.h>
5#include <linux/smp.h> 4#include <linux/smp.h>
6#include <linux/threads.h> 5#include <linux/threads.h>
7#include <linux/percpu.h> 6#include <linux/percpu.h>
8#include <linux/cpumask.h> 7#include <linux/cpumask.h>
8#include <asm/irq.h>
9#include <asm/cputime.h> 9#include <asm/cputime.h>
10 10
11/* 11/*
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 1036631ff4fa..04a3556bdea6 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -259,6 +259,10 @@ void recycle_rp_inst(struct kretprobe_instance *ri, struct hlist_head *head);
259struct jprobe; 259struct jprobe;
260struct kretprobe; 260struct kretprobe;
261 261
262static inline struct kprobe *get_kprobe(void *addr)
263{
264 return NULL;
265}
262static inline struct kprobe *kprobe_running(void) 266static inline struct kprobe *kprobe_running(void)
263{ 267{
264 return NULL; 268 return NULL;
diff --git a/include/linux/libata.h b/include/linux/libata.h
index e57e5d08312d..5b247b8a6b3b 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -27,6 +27,7 @@
27#define __LINUX_LIBATA_H__ 27#define __LINUX_LIBATA_H__
28 28
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/jiffies.h>
30#include <linux/interrupt.h> 31#include <linux/interrupt.h>
31#include <linux/dma-mapping.h> 32#include <linux/dma-mapping.h>
32#include <linux/scatterlist.h> 33#include <linux/scatterlist.h>
@@ -115,7 +116,7 @@ enum {
115 /* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */ 116 /* tag ATA_MAX_QUEUE - 1 is reserved for internal commands */
116 ATA_MAX_QUEUE = 32, 117 ATA_MAX_QUEUE = 32,
117 ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1, 118 ATA_TAG_INTERNAL = ATA_MAX_QUEUE - 1,
118 ATA_SHORT_PAUSE = (HZ >> 6) + 1, 119 ATA_SHORT_PAUSE = 16,
119 120
120 ATAPI_MAX_DRAIN = 16 << 10, 121 ATAPI_MAX_DRAIN = 16 << 10,
121 122
@@ -168,6 +169,7 @@ enum {
168 ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB, 169 ATA_LFLAG_ASSUME_CLASS = ATA_LFLAG_ASSUME_ATA | ATA_LFLAG_ASSUME_SEMB,
169 ATA_LFLAG_NO_RETRY = (1 << 5), /* don't retry this link */ 170 ATA_LFLAG_NO_RETRY = (1 << 5), /* don't retry this link */
170 ATA_LFLAG_DISABLED = (1 << 6), /* link is disabled */ 171 ATA_LFLAG_DISABLED = (1 << 6), /* link is disabled */
172 ATA_LFLAG_SW_ACTIVITY = (1 << 7), /* keep activity stats */
171 173
172 /* struct ata_port flags */ 174 /* struct ata_port flags */
173 ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */ 175 ATA_FLAG_SLAVE_POSS = (1 << 0), /* host supports slave dev */
@@ -190,6 +192,10 @@ enum {
190 ATA_FLAG_AN = (1 << 18), /* controller supports AN */ 192 ATA_FLAG_AN = (1 << 18), /* controller supports AN */
191 ATA_FLAG_PMP = (1 << 19), /* controller supports PMP */ 193 ATA_FLAG_PMP = (1 << 19), /* controller supports PMP */
192 ATA_FLAG_IPM = (1 << 20), /* driver can handle IPM */ 194 ATA_FLAG_IPM = (1 << 20), /* driver can handle IPM */
195 ATA_FLAG_EM = (1 << 21), /* driver supports enclosure
196 * management */
197 ATA_FLAG_SW_ACTIVITY = (1 << 22), /* driver supports sw activity
198 * led */
193 199
194 /* The following flag belongs to ap->pflags but is kept in 200 /* The following flag belongs to ap->pflags but is kept in
195 * ap->flags because it's referenced in many LLDs and will be 201 * ap->flags because it's referenced in many LLDs and will be
@@ -234,17 +240,16 @@ enum {
234 /* bits 24:31 of host->flags are reserved for LLD specific flags */ 240 /* bits 24:31 of host->flags are reserved for LLD specific flags */
235 241
236 /* various lengths of time */ 242 /* various lengths of time */
237 ATA_TMOUT_BOOT = 30 * HZ, /* heuristic */ 243 ATA_TMOUT_BOOT = 30000, /* heuristic */
238 ATA_TMOUT_BOOT_QUICK = 7 * HZ, /* heuristic */ 244 ATA_TMOUT_BOOT_QUICK = 7000, /* heuristic */
239 ATA_TMOUT_INTERNAL = 30 * HZ, 245 ATA_TMOUT_INTERNAL_QUICK = 5000,
240 ATA_TMOUT_INTERNAL_QUICK = 5 * HZ,
241 246
242 /* FIXME: GoVault needs 2s but we can't afford that without 247 /* FIXME: GoVault needs 2s but we can't afford that without
243 * parallel probing. 800ms is enough for iVDR disk 248 * parallel probing. 800ms is enough for iVDR disk
244 * HHD424020F7SV00. Increase to 2secs when parallel probing 249 * HHD424020F7SV00. Increase to 2secs when parallel probing
245 * is in place. 250 * is in place.
246 */ 251 */
247 ATA_TMOUT_FF_WAIT = 4 * HZ / 5, 252 ATA_TMOUT_FF_WAIT = 800,
248 253
249 /* Spec mandates to wait for ">= 2ms" before checking status 254 /* Spec mandates to wait for ">= 2ms" before checking status
250 * after reset. We wait 150ms, because that was the magic 255 * after reset. We wait 150ms, because that was the magic
@@ -256,14 +261,14 @@ enum {
256 * 261 *
257 * Old drivers/ide uses the 2mS rule and then waits for ready. 262 * Old drivers/ide uses the 2mS rule and then waits for ready.
258 */ 263 */
259 ATA_WAIT_AFTER_RESET_MSECS = 150, 264 ATA_WAIT_AFTER_RESET = 150,
260 265
261 /* If PMP is supported, we have to do follow-up SRST. As some 266 /* If PMP is supported, we have to do follow-up SRST. As some
262 * PMPs don't send D2H Reg FIS after hardreset, LLDs are 267 * PMPs don't send D2H Reg FIS after hardreset, LLDs are
263 * advised to wait only for the following duration before 268 * advised to wait only for the following duration before
264 * doing SRST. 269 * doing SRST.
265 */ 270 */
266 ATA_TMOUT_PMP_SRST_WAIT = 1 * HZ, 271 ATA_TMOUT_PMP_SRST_WAIT = 1000,
267 272
268 /* ATA bus states */ 273 /* ATA bus states */
269 BUS_UNKNOWN = 0, 274 BUS_UNKNOWN = 0,
@@ -340,6 +345,11 @@ enum {
340 345
341 SATA_PMP_RW_TIMEOUT = 3000, /* PMP read/write timeout */ 346 SATA_PMP_RW_TIMEOUT = 3000, /* PMP read/write timeout */
342 347
348 /* This should match the actual table size of
349 * ata_eh_cmd_timeout_table in libata-eh.c.
350 */
351 ATA_EH_CMD_TIMEOUT_TABLE_SIZE = 5,
352
343 /* Horkage types. May be set by libata or controller on drives 353 /* Horkage types. May be set by libata or controller on drives
344 (some horkage may be drive/controller pair dependant */ 354 (some horkage may be drive/controller pair dependant */
345 355
@@ -441,6 +451,15 @@ enum link_pm {
441 MEDIUM_POWER, 451 MEDIUM_POWER,
442}; 452};
443extern struct device_attribute dev_attr_link_power_management_policy; 453extern struct device_attribute dev_attr_link_power_management_policy;
454extern struct device_attribute dev_attr_em_message_type;
455extern struct device_attribute dev_attr_em_message;
456extern struct device_attribute dev_attr_sw_activity;
457
458enum sw_activity {
459 OFF,
460 BLINK_ON,
461 BLINK_OFF,
462};
444 463
445#ifdef CONFIG_ATA_SFF 464#ifdef CONFIG_ATA_SFF
446struct ata_ioports { 465struct ata_ioports {
@@ -597,10 +616,14 @@ struct ata_eh_info {
597struct ata_eh_context { 616struct ata_eh_context {
598 struct ata_eh_info i; 617 struct ata_eh_info i;
599 int tries[ATA_MAX_DEVICES]; 618 int tries[ATA_MAX_DEVICES];
619 int cmd_timeout_idx[ATA_MAX_DEVICES]
620 [ATA_EH_CMD_TIMEOUT_TABLE_SIZE];
600 unsigned int classes[ATA_MAX_DEVICES]; 621 unsigned int classes[ATA_MAX_DEVICES];
601 unsigned int did_probe_mask; 622 unsigned int did_probe_mask;
602 unsigned int saved_ncq_enabled; 623 unsigned int saved_ncq_enabled;
603 u8 saved_xfer_mode[ATA_MAX_DEVICES]; 624 u8 saved_xfer_mode[ATA_MAX_DEVICES];
625 /* timestamp for the last reset attempt or success */
626 unsigned long last_reset;
604}; 627};
605 628
606struct ata_acpi_drive 629struct ata_acpi_drive
@@ -692,6 +715,7 @@ struct ata_port {
692 struct timer_list fastdrain_timer; 715 struct timer_list fastdrain_timer;
693 unsigned long fastdrain_cnt; 716 unsigned long fastdrain_cnt;
694 717
718 int em_message_type;
695 void *private_data; 719 void *private_data;
696 720
697#ifdef CONFIG_ATA_ACPI 721#ifdef CONFIG_ATA_ACPI
@@ -783,6 +807,12 @@ struct ata_port_operations {
783 u8 (*bmdma_status)(struct ata_port *ap); 807 u8 (*bmdma_status)(struct ata_port *ap);
784#endif /* CONFIG_ATA_SFF */ 808#endif /* CONFIG_ATA_SFF */
785 809
810 ssize_t (*em_show)(struct ata_port *ap, char *buf);
811 ssize_t (*em_store)(struct ata_port *ap, const char *message,
812 size_t size);
813 ssize_t (*sw_activity_show)(struct ata_device *dev, char *buf);
814 ssize_t (*sw_activity_store)(struct ata_device *dev,
815 enum sw_activity val);
786 /* 816 /*
787 * Obsolete 817 * Obsolete
788 */ 818 */
@@ -895,8 +925,7 @@ extern void ata_host_resume(struct ata_host *host);
895#endif 925#endif
896extern int ata_ratelimit(void); 926extern int ata_ratelimit(void);
897extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val, 927extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
898 unsigned long interval_msec, 928 unsigned long interval, unsigned long timeout);
899 unsigned long timeout_msec);
900extern int atapi_cmd_type(u8 opcode); 929extern int atapi_cmd_type(u8 opcode);
901extern void ata_tf_to_fis(const struct ata_taskfile *tf, 930extern void ata_tf_to_fis(const struct ata_taskfile *tf,
902 u8 pmp, int is_cmd, u8 *fis); 931 u8 pmp, int is_cmd, u8 *fis);
@@ -1389,6 +1418,12 @@ static inline int ata_check_ready(u8 status)
1389 return 0; 1418 return 0;
1390} 1419}
1391 1420
1421static inline unsigned long ata_deadline(unsigned long from_jiffies,
1422 unsigned long timeout_msecs)
1423{
1424 return from_jiffies + msecs_to_jiffies(timeout_msecs);
1425}
1426
1392 1427
1393/************************************************************************** 1428/**************************************************************************
1394 * PMP - drivers/ata/libata-pmp.c 1429 * PMP - drivers/ata/libata-pmp.c
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 2119610b24f8..56ba37394656 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -1,8 +1,11 @@
1#ifndef _LINUX_LINKAGE_H 1#ifndef _LINUX_LINKAGE_H
2#define _LINUX_LINKAGE_H 2#define _LINUX_LINKAGE_H
3 3
4#include <linux/compiler.h>
4#include <asm/linkage.h> 5#include <asm/linkage.h>
5 6
7#define notrace __attribute__((no_instrument_function))
8
6#ifdef __cplusplus 9#ifdef __cplusplus
7#define CPP_ASMLINKAGE extern "C" 10#define CPP_ASMLINKAGE extern "C"
8#else 11#else
@@ -17,6 +20,9 @@
17# define asmregparm 20# define asmregparm
18#endif 21#endif
19 22
23#define __page_aligned_data __section(.data.page_aligned) __aligned(PAGE_SIZE)
24#define __page_aligned_bss __section(.bss.page_aligned) __aligned(PAGE_SIZE)
25
20/* 26/*
21 * This is used by architectures to keep arguments on the stack 27 * This is used by architectures to keep arguments on the stack
22 * untouched by the compiler by keeping them live until the end. 28 * untouched by the compiler by keeping them live until the end.
diff --git a/include/linux/list.h b/include/linux/list.h
index 08cf4f651889..139ec41d9c2e 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -85,65 +85,6 @@ static inline void list_add_tail(struct list_head *new, struct list_head *head)
85} 85}
86 86
87/* 87/*
88 * Insert a new entry between two known consecutive entries.
89 *
90 * This is only for internal list manipulation where we know
91 * the prev/next entries already!
92 */
93static inline void __list_add_rcu(struct list_head * new,
94 struct list_head * prev, struct list_head * next)
95{
96 new->next = next;
97 new->prev = prev;
98 smp_wmb();
99 next->prev = new;
100 prev->next = new;
101}
102
103/**
104 * list_add_rcu - add a new entry to rcu-protected list
105 * @new: new entry to be added
106 * @head: list head to add it after
107 *
108 * Insert a new entry after the specified head.
109 * This is good for implementing stacks.
110 *
111 * The caller must take whatever precautions are necessary
112 * (such as holding appropriate locks) to avoid racing
113 * with another list-mutation primitive, such as list_add_rcu()
114 * or list_del_rcu(), running on this same list.
115 * However, it is perfectly legal to run concurrently with
116 * the _rcu list-traversal primitives, such as
117 * list_for_each_entry_rcu().
118 */
119static inline void list_add_rcu(struct list_head *new, struct list_head *head)
120{
121 __list_add_rcu(new, head, head->next);
122}
123
124/**
125 * list_add_tail_rcu - add a new entry to rcu-protected list
126 * @new: new entry to be added
127 * @head: list head to add it before
128 *
129 * Insert a new entry before the specified head.
130 * This is useful for implementing queues.
131 *
132 * The caller must take whatever precautions are necessary
133 * (such as holding appropriate locks) to avoid racing
134 * with another list-mutation primitive, such as list_add_tail_rcu()
135 * or list_del_rcu(), running on this same list.
136 * However, it is perfectly legal to run concurrently with
137 * the _rcu list-traversal primitives, such as
138 * list_for_each_entry_rcu().
139 */
140static inline void list_add_tail_rcu(struct list_head *new,
141 struct list_head *head)
142{
143 __list_add_rcu(new, head->prev, head);
144}
145
146/*
147 * Delete a list entry by making the prev/next entries 88 * Delete a list entry by making the prev/next entries
148 * point to each other. 89 * point to each other.
149 * 90 *
@@ -174,36 +115,6 @@ extern void list_del(struct list_head *entry);
174#endif 115#endif
175 116
176/** 117/**
177 * list_del_rcu - deletes entry from list without re-initialization
178 * @entry: the element to delete from the list.
179 *
180 * Note: list_empty() on entry does not return true after this,
181 * the entry is in an undefined state. It is useful for RCU based
182 * lockfree traversal.
183 *
184 * In particular, it means that we can not poison the forward
185 * pointers that may still be used for walking the list.
186 *
187 * The caller must take whatever precautions are necessary
188 * (such as holding appropriate locks) to avoid racing
189 * with another list-mutation primitive, such as list_del_rcu()
190 * or list_add_rcu(), running on this same list.
191 * However, it is perfectly legal to run concurrently with
192 * the _rcu list-traversal primitives, such as
193 * list_for_each_entry_rcu().
194 *
195 * Note that the caller is not permitted to immediately free
196 * the newly deleted entry. Instead, either synchronize_rcu()
197 * or call_rcu() must be used to defer freeing until an RCU
198 * grace period has elapsed.
199 */
200static inline void list_del_rcu(struct list_head *entry)
201{
202 __list_del(entry->prev, entry->next);
203 entry->prev = LIST_POISON2;
204}
205
206/**
207 * list_replace - replace old entry by new one 118 * list_replace - replace old entry by new one
208 * @old : the element to be replaced 119 * @old : the element to be replaced
209 * @new : the new element to insert 120 * @new : the new element to insert
@@ -227,25 +138,6 @@ static inline void list_replace_init(struct list_head *old,
227} 138}
228 139
229/** 140/**
230 * list_replace_rcu - replace old entry by new one
231 * @old : the element to be replaced
232 * @new : the new element to insert
233 *
234 * The @old entry will be replaced with the @new entry atomically.
235 * Note: @old should not be empty.
236 */
237static inline void list_replace_rcu(struct list_head *old,
238 struct list_head *new)
239{
240 new->next = old->next;
241 new->prev = old->prev;
242 smp_wmb();
243 new->next->prev = new;
244 new->prev->next = new;
245 old->prev = LIST_POISON2;
246}
247
248/**
249 * list_del_init - deletes entry from list and reinitialize it. 141 * list_del_init - deletes entry from list and reinitialize it.
250 * @entry: the element to delete from the list. 142 * @entry: the element to delete from the list.
251 */ 143 */
@@ -369,62 +261,6 @@ static inline void list_splice_init(struct list_head *list,
369} 261}
370 262
371/** 263/**
372 * list_splice_init_rcu - splice an RCU-protected list into an existing list.
373 * @list: the RCU-protected list to splice
374 * @head: the place in the list to splice the first list into
375 * @sync: function to sync: synchronize_rcu(), synchronize_sched(), ...
376 *
377 * @head can be RCU-read traversed concurrently with this function.
378 *
379 * Note that this function blocks.
380 *
381 * Important note: the caller must take whatever action is necessary to
382 * prevent any other updates to @head. In principle, it is possible
383 * to modify the list as soon as sync() begins execution.
384 * If this sort of thing becomes necessary, an alternative version
385 * based on call_rcu() could be created. But only if -really-
386 * needed -- there is no shortage of RCU API members.
387 */
388static inline void list_splice_init_rcu(struct list_head *list,
389 struct list_head *head,
390 void (*sync)(void))
391{
392 struct list_head *first = list->next;
393 struct list_head *last = list->prev;
394 struct list_head *at = head->next;
395
396 if (list_empty(head))
397 return;
398
399 /* "first" and "last" tracking list, so initialize it. */
400
401 INIT_LIST_HEAD(list);
402
403 /*
404 * At this point, the list body still points to the source list.
405 * Wait for any readers to finish using the list before splicing
406 * the list body into the new list. Any new readers will see
407 * an empty list.
408 */
409
410 sync();
411
412 /*
413 * Readers are finished with the source list, so perform splice.
414 * The order is important if the new list is global and accessible
415 * to concurrent RCU readers. Note that RCU readers are not
416 * permitted to traverse the prev pointers without excluding
417 * this function.
418 */
419
420 last->next = at;
421 smp_wmb();
422 head->next = first;
423 first->prev = head;
424 at->prev = last;
425}
426
427/**
428 * list_entry - get the struct for this entry 264 * list_entry - get the struct for this entry
429 * @ptr: the &struct list_head pointer. 265 * @ptr: the &struct list_head pointer.
430 * @type: the type of the struct this is embedded in. 266 * @type: the type of the struct this is embedded in.
@@ -629,57 +465,6 @@ static inline void list_splice_init_rcu(struct list_head *list,
629 &pos->member != (head); \ 465 &pos->member != (head); \
630 pos = n, n = list_entry(n->member.prev, typeof(*n), member)) 466 pos = n, n = list_entry(n->member.prev, typeof(*n), member))
631 467
632/**
633 * list_for_each_rcu - iterate over an rcu-protected list
634 * @pos: the &struct list_head to use as a loop cursor.
635 * @head: the head for your list.
636 *
637 * This list-traversal primitive may safely run concurrently with
638 * the _rcu list-mutation primitives such as list_add_rcu()
639 * as long as the traversal is guarded by rcu_read_lock().
640 */
641#define list_for_each_rcu(pos, head) \
642 for (pos = rcu_dereference((head)->next); \
643 prefetch(pos->next), pos != (head); \
644 pos = rcu_dereference(pos->next))
645
646#define __list_for_each_rcu(pos, head) \
647 for (pos = rcu_dereference((head)->next); \
648 pos != (head); \
649 pos = rcu_dereference(pos->next))
650
651/**
652 * list_for_each_entry_rcu - iterate over rcu list of given type
653 * @pos: the type * to use as a loop cursor.
654 * @head: the head for your list.
655 * @member: the name of the list_struct within the struct.
656 *
657 * This list-traversal primitive may safely run concurrently with
658 * the _rcu list-mutation primitives such as list_add_rcu()
659 * as long as the traversal is guarded by rcu_read_lock().
660 */
661#define list_for_each_entry_rcu(pos, head, member) \
662 for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \
663 prefetch(pos->member.next), &pos->member != (head); \
664 pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member))
665
666
667/**
668 * list_for_each_continue_rcu
669 * @pos: the &struct list_head to use as a loop cursor.
670 * @head: the head for your list.
671 *
672 * Iterate over an rcu-protected list, continuing after current point.
673 *
674 * This list-traversal primitive may safely run concurrently with
675 * the _rcu list-mutation primitives such as list_add_rcu()
676 * as long as the traversal is guarded by rcu_read_lock().
677 */
678#define list_for_each_continue_rcu(pos, head) \
679 for ((pos) = rcu_dereference((pos)->next); \
680 prefetch((pos)->next), (pos) != (head); \
681 (pos) = rcu_dereference((pos)->next))
682
683/* 468/*
684 * Double linked lists with a single pointer list head. 469 * Double linked lists with a single pointer list head.
685 * Mostly useful for hash tables where the two pointer list head is 470 * Mostly useful for hash tables where the two pointer list head is
@@ -730,31 +515,6 @@ static inline void hlist_del(struct hlist_node *n)
730 n->pprev = LIST_POISON2; 515 n->pprev = LIST_POISON2;
731} 516}
732 517
733/**
734 * hlist_del_rcu - deletes entry from hash list without re-initialization
735 * @n: the element to delete from the hash list.
736 *
737 * Note: list_unhashed() on entry does not return true after this,
738 * the entry is in an undefined state. It is useful for RCU based
739 * lockfree traversal.
740 *
741 * In particular, it means that we can not poison the forward
742 * pointers that may still be used for walking the hash list.
743 *
744 * The caller must take whatever precautions are necessary
745 * (such as holding appropriate locks) to avoid racing
746 * with another list-mutation primitive, such as hlist_add_head_rcu()
747 * or hlist_del_rcu(), running on this same list.
748 * However, it is perfectly legal to run concurrently with
749 * the _rcu list-traversal primitives, such as
750 * hlist_for_each_entry().
751 */
752static inline void hlist_del_rcu(struct hlist_node *n)
753{
754 __hlist_del(n);
755 n->pprev = LIST_POISON2;
756}
757
758static inline void hlist_del_init(struct hlist_node *n) 518static inline void hlist_del_init(struct hlist_node *n)
759{ 519{
760 if (!hlist_unhashed(n)) { 520 if (!hlist_unhashed(n)) {
@@ -763,27 +523,6 @@ static inline void hlist_del_init(struct hlist_node *n)
763 } 523 }
764} 524}
765 525
766/**
767 * hlist_replace_rcu - replace old entry by new one
768 * @old : the element to be replaced
769 * @new : the new element to insert
770 *
771 * The @old entry will be replaced with the @new entry atomically.
772 */
773static inline void hlist_replace_rcu(struct hlist_node *old,
774 struct hlist_node *new)
775{
776 struct hlist_node *next = old->next;
777
778 new->next = next;
779 new->pprev = old->pprev;
780 smp_wmb();
781 if (next)
782 new->next->pprev = &new->next;
783 *new->pprev = new;
784 old->pprev = LIST_POISON2;
785}
786
787static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h) 526static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
788{ 527{
789 struct hlist_node *first = h->first; 528 struct hlist_node *first = h->first;
@@ -794,38 +533,6 @@ static inline void hlist_add_head(struct hlist_node *n, struct hlist_head *h)
794 n->pprev = &h->first; 533 n->pprev = &h->first;
795} 534}
796 535
797
798/**
799 * hlist_add_head_rcu
800 * @n: the element to add to the hash list.
801 * @h: the list to add to.
802 *
803 * Description:
804 * Adds the specified element to the specified hlist,
805 * while permitting racing traversals.
806 *
807 * The caller must take whatever precautions are necessary
808 * (such as holding appropriate locks) to avoid racing
809 * with another list-mutation primitive, such as hlist_add_head_rcu()
810 * or hlist_del_rcu(), running on this same list.
811 * However, it is perfectly legal to run concurrently with
812 * the _rcu list-traversal primitives, such as
813 * hlist_for_each_entry_rcu(), used to prevent memory-consistency
814 * problems on Alpha CPUs. Regardless of the type of CPU, the
815 * list-traversal primitive must be guarded by rcu_read_lock().
816 */
817static inline void hlist_add_head_rcu(struct hlist_node *n,
818 struct hlist_head *h)
819{
820 struct hlist_node *first = h->first;
821 n->next = first;
822 n->pprev = &h->first;
823 smp_wmb();
824 if (first)
825 first->pprev = &n->next;
826 h->first = n;
827}
828
829/* next must be != NULL */ 536/* next must be != NULL */
830static inline void hlist_add_before(struct hlist_node *n, 537static inline void hlist_add_before(struct hlist_node *n,
831 struct hlist_node *next) 538 struct hlist_node *next)
@@ -847,63 +554,6 @@ static inline void hlist_add_after(struct hlist_node *n,
847 next->next->pprev = &next->next; 554 next->next->pprev = &next->next;
848} 555}
849 556
850/**
851 * hlist_add_before_rcu
852 * @n: the new element to add to the hash list.
853 * @next: the existing element to add the new element before.
854 *
855 * Description:
856 * Adds the specified element to the specified hlist
857 * before the specified node while permitting racing traversals.
858 *
859 * The caller must take whatever precautions are necessary
860 * (such as holding appropriate locks) to avoid racing
861 * with another list-mutation primitive, such as hlist_add_head_rcu()
862 * or hlist_del_rcu(), running on this same list.
863 * However, it is perfectly legal to run concurrently with
864 * the _rcu list-traversal primitives, such as
865 * hlist_for_each_entry_rcu(), used to prevent memory-consistency
866 * problems on Alpha CPUs.
867 */
868static inline void hlist_add_before_rcu(struct hlist_node *n,
869 struct hlist_node *next)
870{
871 n->pprev = next->pprev;
872 n->next = next;
873 smp_wmb();
874 next->pprev = &n->next;
875 *(n->pprev) = n;
876}
877
878/**
879 * hlist_add_after_rcu
880 * @prev: the existing element to add the new element after.
881 * @n: the new element to add to the hash list.
882 *
883 * Description:
884 * Adds the specified element to the specified hlist
885 * after the specified node while permitting racing traversals.
886 *
887 * The caller must take whatever precautions are necessary
888 * (such as holding appropriate locks) to avoid racing
889 * with another list-mutation primitive, such as hlist_add_head_rcu()
890 * or hlist_del_rcu(), running on this same list.
891 * However, it is perfectly legal to run concurrently with
892 * the _rcu list-traversal primitives, such as
893 * hlist_for_each_entry_rcu(), used to prevent memory-consistency
894 * problems on Alpha CPUs.
895 */
896static inline void hlist_add_after_rcu(struct hlist_node *prev,
897 struct hlist_node *n)
898{
899 n->next = prev->next;
900 n->pprev = &prev->next;
901 smp_wmb();
902 prev->next = n;
903 if (n->next)
904 n->next->pprev = &n->next;
905}
906
907#define hlist_entry(ptr, type, member) container_of(ptr,type,member) 557#define hlist_entry(ptr, type, member) container_of(ptr,type,member)
908 558
909#define hlist_for_each(pos, head) \ 559#define hlist_for_each(pos, head) \
@@ -964,21 +614,4 @@ static inline void hlist_add_after_rcu(struct hlist_node *prev,
964 ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \ 614 ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
965 pos = n) 615 pos = n)
966 616
967/**
968 * hlist_for_each_entry_rcu - iterate over rcu list of given type
969 * @tpos: the type * to use as a loop cursor.
970 * @pos: the &struct hlist_node to use as a loop cursor.
971 * @head: the head for your list.
972 * @member: the name of the hlist_node within the struct.
973 *
974 * This list-traversal primitive may safely run concurrently with
975 * the _rcu list-mutation primitives such as hlist_add_head_rcu()
976 * as long as the traversal is guarded by rcu_read_lock().
977 */
978#define hlist_for_each_entry_rcu(tpos, pos, head, member) \
979 for (pos = rcu_dereference((head)->first); \
980 pos && ({ prefetch(pos->next); 1;}) && \
981 ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1;}); \
982 pos = rcu_dereference(pos->next))
983
984#endif 617#endif
diff --git a/include/linux/lm_interface.h b/include/linux/lm_interface.h
index f274997bc283..2ed8fa1b762b 100644
--- a/include/linux/lm_interface.h
+++ b/include/linux/lm_interface.h
@@ -122,11 +122,9 @@ typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
122 */ 122 */
123 123
124#define LM_OUT_ST_MASK 0x00000003 124#define LM_OUT_ST_MASK 0x00000003
125#define LM_OUT_CACHEABLE 0x00000004
126#define LM_OUT_CANCELED 0x00000008 125#define LM_OUT_CANCELED 0x00000008
127#define LM_OUT_ASYNC 0x00000080 126#define LM_OUT_ASYNC 0x00000080
128#define LM_OUT_ERROR 0x00000100 127#define LM_OUT_ERROR 0x00000100
129#define LM_OUT_CONV_DEADLK 0x00000200
130 128
131/* 129/*
132 * lm_callback_t types 130 * lm_callback_t types
@@ -138,9 +136,6 @@ typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
138 * LM_CB_NEED_RECOVERY 136 * LM_CB_NEED_RECOVERY
139 * The given journal needs to be recovered. 137 * The given journal needs to be recovered.
140 * 138 *
141 * LM_CB_DROPLOCKS
142 * Reduce the number of cached locks.
143 *
144 * LM_CB_ASYNC 139 * LM_CB_ASYNC
145 * The given lock has been granted. 140 * The given lock has been granted.
146 */ 141 */
@@ -149,7 +144,6 @@ typedef void (*lm_callback_t) (void *ptr, unsigned int type, void *data);
149#define LM_CB_NEED_D 258 144#define LM_CB_NEED_D 258
150#define LM_CB_NEED_S 259 145#define LM_CB_NEED_S 259
151#define LM_CB_NEED_RECOVERY 260 146#define LM_CB_NEED_RECOVERY 260
152#define LM_CB_DROPLOCKS 261
153#define LM_CB_ASYNC 262 147#define LM_CB_ASYNC 262
154 148
155/* 149/*
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 4c4d236ded18..2486eb4edbf1 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -182,6 +182,9 @@ struct lock_list {
182 * We record lock dependency chains, so that we can cache them: 182 * We record lock dependency chains, so that we can cache them:
183 */ 183 */
184struct lock_chain { 184struct lock_chain {
185 u8 irq_context;
186 u8 depth;
187 u16 base;
185 struct list_head entry; 188 struct list_head entry;
186 u64 chain_key; 189 u64 chain_key;
187}; 190};
@@ -276,14 +279,6 @@ extern void lockdep_init_map(struct lockdep_map *lock, const char *name,
276 (lock)->dep_map.key, sub) 279 (lock)->dep_map.key, sub)
277 280
278/* 281/*
279 * To initialize a lockdep_map statically use this macro.
280 * Note that _name must not be NULL.
281 */
282#define STATIC_LOCKDEP_MAP_INIT(_name, _key) \
283 { .name = (_name), .key = (void *)(_key), }
284
285
286/*
287 * Acquire a lock. 282 * Acquire a lock.
288 * 283 *
289 * Values for "read": 284 * Values for "read":
diff --git a/include/linux/marker.h b/include/linux/marker.h
index 430f6adf9762..1290653f9241 100644
--- a/include/linux/marker.h
+++ b/include/linux/marker.h
@@ -44,8 +44,8 @@ struct marker {
44 */ 44 */
45 char state; /* Marker state. */ 45 char state; /* Marker state. */
46 char ptype; /* probe type : 0 : single, 1 : multi */ 46 char ptype; /* probe type : 0 : single, 1 : multi */
47 void (*call)(const struct marker *mdata, /* Probe wrapper */ 47 /* Probe wrapper */
48 void *call_private, const char *fmt, ...); 48 void (*call)(const struct marker *mdata, void *call_private, ...);
49 struct marker_probe_closure single; 49 struct marker_probe_closure single;
50 struct marker_probe_closure *multi; 50 struct marker_probe_closure *multi;
51} __attribute__((aligned(8))); 51} __attribute__((aligned(8)));
@@ -58,8 +58,12 @@ struct marker {
58 * Make sure the alignment of the structure in the __markers section will 58 * Make sure the alignment of the structure in the __markers section will
59 * not add unwanted padding between the beginning of the section and the 59 * not add unwanted padding between the beginning of the section and the
60 * structure. Force alignment to the same alignment as the section start. 60 * structure. Force alignment to the same alignment as the section start.
61 *
62 * The "generic" argument controls which marker enabling mechanism must be used.
63 * If generic is true, a variable read is used.
64 * If generic is false, immediate values are used.
61 */ 65 */
62#define __trace_mark(name, call_private, format, args...) \ 66#define __trace_mark(generic, name, call_private, format, args...) \
63 do { \ 67 do { \
64 static const char __mstrtab_##name[] \ 68 static const char __mstrtab_##name[] \
65 __attribute__((section("__markers_strings"))) \ 69 __attribute__((section("__markers_strings"))) \
@@ -72,15 +76,14 @@ struct marker {
72 __mark_check_format(format, ## args); \ 76 __mark_check_format(format, ## args); \
73 if (unlikely(__mark_##name.state)) { \ 77 if (unlikely(__mark_##name.state)) { \
74 (*__mark_##name.call) \ 78 (*__mark_##name.call) \
75 (&__mark_##name, call_private, \ 79 (&__mark_##name, call_private, ## args);\
76 format, ## args); \
77 } \ 80 } \
78 } while (0) 81 } while (0)
79 82
80extern void marker_update_probe_range(struct marker *begin, 83extern void marker_update_probe_range(struct marker *begin,
81 struct marker *end); 84 struct marker *end);
82#else /* !CONFIG_MARKERS */ 85#else /* !CONFIG_MARKERS */
83#define __trace_mark(name, call_private, format, args...) \ 86#define __trace_mark(generic, name, call_private, format, args...) \
84 __mark_check_format(format, ## args) 87 __mark_check_format(format, ## args)
85static inline void marker_update_probe_range(struct marker *begin, 88static inline void marker_update_probe_range(struct marker *begin,
86 struct marker *end) 89 struct marker *end)
@@ -88,15 +91,30 @@ static inline void marker_update_probe_range(struct marker *begin,
88#endif /* CONFIG_MARKERS */ 91#endif /* CONFIG_MARKERS */
89 92
90/** 93/**
91 * trace_mark - Marker 94 * trace_mark - Marker using code patching
92 * @name: marker name, not quoted. 95 * @name: marker name, not quoted.
93 * @format: format string 96 * @format: format string
94 * @args...: variable argument list 97 * @args...: variable argument list
95 * 98 *
96 * Places a marker. 99 * Places a marker using optimized code patching technique (imv_read())
100 * to be enabled when immediate values are present.
97 */ 101 */
98#define trace_mark(name, format, args...) \ 102#define trace_mark(name, format, args...) \
99 __trace_mark(name, NULL, format, ## args) 103 __trace_mark(0, name, NULL, format, ## args)
104
105/**
106 * _trace_mark - Marker using variable read
107 * @name: marker name, not quoted.
108 * @format: format string
109 * @args...: variable argument list
110 *
111 * Places a marker using a standard memory read (_imv_read()) to be
112 * enabled. Should be used for markers in code paths where instruction
113 * modification based enabling is not welcome. (__init and __exit functions,
114 * lockdep, some traps, printk).
115 */
116#define _trace_mark(name, format, args...) \
117 __trace_mark(1, name, NULL, format, ## args)
100 118
101/** 119/**
102 * MARK_NOARGS - Format string for a marker with no argument. 120 * MARK_NOARGS - Format string for a marker with no argument.
@@ -117,9 +135,9 @@ static inline void __printf(1, 2) ___mark_check_format(const char *fmt, ...)
117extern marker_probe_func __mark_empty_function; 135extern marker_probe_func __mark_empty_function;
118 136
119extern void marker_probe_cb(const struct marker *mdata, 137extern void marker_probe_cb(const struct marker *mdata,
120 void *call_private, const char *fmt, ...); 138 void *call_private, ...);
121extern void marker_probe_cb_noarg(const struct marker *mdata, 139extern void marker_probe_cb_noarg(const struct marker *mdata,
122 void *call_private, const char *fmt, ...); 140 void *call_private, ...);
123 141
124/* 142/*
125 * Connect a probe to a marker. 143 * Connect a probe to a marker.
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index a744383d16e9..81b3dd5206e0 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -398,7 +398,8 @@ int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_waterm
398int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 398int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
399int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 399int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
400 400
401int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); 401int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
402 int block_mcast_loopback);
402int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]); 403int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
403 404
404int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 405int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 586a943cab01..cf1cd3a2ed78 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -998,8 +998,8 @@ extern void free_area_init_node(int nid, pg_data_t *pgdat,
998extern void free_area_init_nodes(unsigned long *max_zone_pfn); 998extern void free_area_init_nodes(unsigned long *max_zone_pfn);
999extern void add_active_range(unsigned int nid, unsigned long start_pfn, 999extern void add_active_range(unsigned int nid, unsigned long start_pfn,
1000 unsigned long end_pfn); 1000 unsigned long end_pfn);
1001extern void shrink_active_range(unsigned int nid, unsigned long old_end_pfn, 1001extern void remove_active_range(unsigned int nid, unsigned long start_pfn,
1002 unsigned long new_end_pfn); 1002 unsigned long end_pfn);
1003extern void push_node_boundaries(unsigned int nid, unsigned long start_pfn, 1003extern void push_node_boundaries(unsigned int nid, unsigned long start_pfn,
1004 unsigned long end_pfn); 1004 unsigned long end_pfn);
1005extern void remove_all_active_ranges(void); 1005extern void remove_all_active_ranges(void);
@@ -1011,6 +1011,8 @@ extern unsigned long find_min_pfn_with_active_regions(void);
1011extern unsigned long find_max_pfn_with_active_regions(void); 1011extern unsigned long find_max_pfn_with_active_regions(void);
1012extern void free_bootmem_with_active_regions(int nid, 1012extern void free_bootmem_with_active_regions(int nid,
1013 unsigned long max_low_pfn); 1013 unsigned long max_low_pfn);
1014typedef int (*work_fn_t)(unsigned long, unsigned long, void *);
1015extern void work_with_active_regions(int nid, work_fn_t work_fn, void *data);
1014extern void sparse_memory_present_with_active_regions(int nid); 1016extern void sparse_memory_present_with_active_regions(int nid);
1015#ifndef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID 1017#ifndef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID
1016extern int early_pfn_to_nid(unsigned long pfn); 1018extern int early_pfn_to_nid(unsigned long pfn);
@@ -1024,6 +1026,7 @@ extern void mem_init(void);
1024extern void show_mem(void); 1026extern void show_mem(void);
1025extern void si_meminfo(struct sysinfo * val); 1027extern void si_meminfo(struct sysinfo * val);
1026extern void si_meminfo_node(struct sysinfo *val, int nid); 1028extern void si_meminfo_node(struct sysinfo *val, int nid);
1029extern int after_bootmem;
1027 1030
1028#ifdef CONFIG_NUMA 1031#ifdef CONFIG_NUMA
1029extern void setup_per_cpu_pageset(void); 1032extern void setup_per_cpu_pageset(void);
diff --git a/include/linux/mmiotrace.h b/include/linux/mmiotrace.h
new file mode 100644
index 000000000000..61d19e1b7a0b
--- /dev/null
+++ b/include/linux/mmiotrace.h
@@ -0,0 +1,85 @@
1#ifndef MMIOTRACE_H
2#define MMIOTRACE_H
3
4#include <linux/types.h>
5#include <linux/list.h>
6
7struct kmmio_probe;
8struct pt_regs;
9
10typedef void (*kmmio_pre_handler_t)(struct kmmio_probe *,
11 struct pt_regs *, unsigned long addr);
12typedef void (*kmmio_post_handler_t)(struct kmmio_probe *,
13 unsigned long condition, struct pt_regs *);
14
15struct kmmio_probe {
16 struct list_head list; /* kmmio internal list */
17 unsigned long addr; /* start location of the probe point */
18 unsigned long len; /* length of the probe region */
19 kmmio_pre_handler_t pre_handler; /* Called before addr is executed. */
20 kmmio_post_handler_t post_handler; /* Called after addr is executed */
21 void *private;
22};
23
24/* kmmio is active by some kmmio_probes? */
25static inline int is_kmmio_active(void)
26{
27 extern unsigned int kmmio_count;
28 return kmmio_count;
29}
30
31extern int register_kmmio_probe(struct kmmio_probe *p);
32extern void unregister_kmmio_probe(struct kmmio_probe *p);
33
34/* Called from page fault handler. */
35extern int kmmio_handler(struct pt_regs *regs, unsigned long addr);
36
37/* Called from ioremap.c */
38#ifdef CONFIG_MMIOTRACE
39extern void mmiotrace_ioremap(resource_size_t offset, unsigned long size,
40 void __iomem *addr);
41extern void mmiotrace_iounmap(volatile void __iomem *addr);
42#else
43static inline void mmiotrace_ioremap(resource_size_t offset,
44 unsigned long size, void __iomem *addr)
45{
46}
47
48static inline void mmiotrace_iounmap(volatile void __iomem *addr)
49{
50}
51#endif /* CONFIG_MMIOTRACE_HOOKS */
52
53enum mm_io_opcode {
54 MMIO_READ = 0x1, /* struct mmiotrace_rw */
55 MMIO_WRITE = 0x2, /* struct mmiotrace_rw */
56 MMIO_PROBE = 0x3, /* struct mmiotrace_map */
57 MMIO_UNPROBE = 0x4, /* struct mmiotrace_map */
58 MMIO_MARKER = 0x5, /* raw char data */
59 MMIO_UNKNOWN_OP = 0x6, /* struct mmiotrace_rw */
60};
61
62struct mmiotrace_rw {
63 resource_size_t phys; /* PCI address of register */
64 unsigned long value;
65 unsigned long pc; /* optional program counter */
66 int map_id;
67 unsigned char opcode; /* one of MMIO_{READ,WRITE,UNKNOWN_OP} */
68 unsigned char width; /* size of register access in bytes */
69};
70
71struct mmiotrace_map {
72 resource_size_t phys; /* base address in PCI space */
73 unsigned long virt; /* base virtual address */
74 unsigned long len; /* mapping size */
75 int map_id;
76 unsigned char opcode; /* MMIO_PROBE or MMIO_UNPROBE */
77};
78
79/* in kernel/trace/trace_mmiotrace.c */
80extern void enable_mmiotrace(void);
81extern void disable_mmiotrace(void);
82extern void mmio_trace_rw(struct mmiotrace_rw *rw);
83extern void mmio_trace_mapping(struct mmiotrace_map *map);
84
85#endif /* MMIOTRACE_H */
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index 69b2342d5ebb..c4db5827963d 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -159,6 +159,15 @@ struct ap_device_id {
159 159
160#define AP_DEVICE_ID_MATCH_DEVICE_TYPE 0x01 160#define AP_DEVICE_ID_MATCH_DEVICE_TYPE 0x01
161 161
162/* s390 css bus devices (subchannels) */
163struct css_device_id {
164 __u8 match_flags;
165 __u8 type; /* subchannel type */
166 __u16 pad2;
167 __u32 pad3;
168 kernel_ulong_t driver_data;
169};
170
162#define ACPI_ID_LEN 16 /* only 9 bytes needed here, 16 bytes are used */ 171#define ACPI_ID_LEN 16 /* only 9 bytes needed here, 16 bytes are used */
163 /* to workaround crosscompile issues */ 172 /* to workaround crosscompile issues */
164 173
diff --git a/include/linux/mpage.h b/include/linux/mpage.h
index 068a0c9946af..5c42821da2d1 100644
--- a/include/linux/mpage.h
+++ b/include/linux/mpage.h
@@ -11,11 +11,21 @@
11 */ 11 */
12#ifdef CONFIG_BLOCK 12#ifdef CONFIG_BLOCK
13 13
14struct mpage_data {
15 struct bio *bio;
16 sector_t last_block_in_bio;
17 get_block_t *get_block;
18 unsigned use_writepage;
19};
20
14struct writeback_control; 21struct writeback_control;
15 22
23struct bio *mpage_bio_submit(int rw, struct bio *bio);
16int mpage_readpages(struct address_space *mapping, struct list_head *pages, 24int mpage_readpages(struct address_space *mapping, struct list_head *pages,
17 unsigned nr_pages, get_block_t get_block); 25 unsigned nr_pages, get_block_t get_block);
18int mpage_readpage(struct page *page, get_block_t get_block); 26int mpage_readpage(struct page *page, get_block_t get_block);
27int __mpage_writepage(struct page *page, struct writeback_control *wbc,
28 void *data);
19int mpage_writepages(struct address_space *mapping, 29int mpage_writepages(struct address_space *mapping,
20 struct writeback_control *wbc, get_block_t get_block); 30 struct writeback_control *wbc, get_block_t get_block);
21int mpage_writepage(struct page *page, get_block_t *get_block, 31int mpage_writepage(struct page *page, get_block_t *get_block,
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index f31debfac926..0d2a4e7012aa 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -157,6 +157,7 @@ PAGEFLAG(Active, active) __CLEARPAGEFLAG(Active, active)
157__PAGEFLAG(Slab, slab) 157__PAGEFLAG(Slab, slab)
158PAGEFLAG(Checked, owner_priv_1) /* Used by some filesystems */ 158PAGEFLAG(Checked, owner_priv_1) /* Used by some filesystems */
159PAGEFLAG(Pinned, owner_priv_1) TESTSCFLAG(Pinned, owner_priv_1) /* Xen */ 159PAGEFLAG(Pinned, owner_priv_1) TESTSCFLAG(Pinned, owner_priv_1) /* Xen */
160PAGEFLAG(SavePinned, dirty); /* Xen */
160PAGEFLAG(Reserved, reserved) __CLEARPAGEFLAG(Reserved, reserved) 161PAGEFLAG(Reserved, reserved) __CLEARPAGEFLAG(Reserved, reserved)
161PAGEFLAG(Private, private) __CLEARPAGEFLAG(Private, private) 162PAGEFLAG(Private, private) __CLEARPAGEFLAG(Private, private)
162 __SETPAGEFLAG(Private, private) 163 __SETPAGEFLAG(Private, private)
diff --git a/include/linux/pageblock-flags.h b/include/linux/pageblock-flags.h
index e875905f7b12..e8c06122be36 100644
--- a/include/linux/pageblock-flags.h
+++ b/include/linux/pageblock-flags.h
@@ -25,13 +25,11 @@
25 25
26#include <linux/types.h> 26#include <linux/types.h>
27 27
28/* Macro to aid the definition of ranges of bits */
29#define PB_range(name, required_bits) \
30 name, name ## _end = (name + required_bits) - 1
31
32/* Bit indices that affect a whole block of pages */ 28/* Bit indices that affect a whole block of pages */
33enum pageblock_bits { 29enum pageblock_bits {
34 PB_range(PB_migrate, 3), /* 3 bits required for migrate types */ 30 PB_migrate,
31 PB_migrate_end = PB_migrate + 3 - 1,
32 /* 3 bits required for migrate types */
35 NR_PAGEBLOCK_BITS 33 NR_PAGEBLOCK_BITS
36}; 34};
37 35
diff --git a/include/linux/percpu_counter.h b/include/linux/percpu_counter.h
index 9007ccdfc112..208388835357 100644
--- a/include/linux/percpu_counter.h
+++ b/include/linux/percpu_counter.h
@@ -35,7 +35,7 @@ int percpu_counter_init_irq(struct percpu_counter *fbc, s64 amount);
35void percpu_counter_destroy(struct percpu_counter *fbc); 35void percpu_counter_destroy(struct percpu_counter *fbc);
36void percpu_counter_set(struct percpu_counter *fbc, s64 amount); 36void percpu_counter_set(struct percpu_counter *fbc, s64 amount);
37void __percpu_counter_add(struct percpu_counter *fbc, s64 amount, s32 batch); 37void __percpu_counter_add(struct percpu_counter *fbc, s64 amount, s32 batch);
38s64 __percpu_counter_sum(struct percpu_counter *fbc); 38s64 __percpu_counter_sum(struct percpu_counter *fbc, int set);
39 39
40static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount) 40static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount)
41{ 41{
@@ -44,13 +44,19 @@ static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount)
44 44
45static inline s64 percpu_counter_sum_positive(struct percpu_counter *fbc) 45static inline s64 percpu_counter_sum_positive(struct percpu_counter *fbc)
46{ 46{
47 s64 ret = __percpu_counter_sum(fbc); 47 s64 ret = __percpu_counter_sum(fbc, 0);
48 return ret < 0 ? 0 : ret; 48 return ret < 0 ? 0 : ret;
49} 49}
50 50
51static inline s64 percpu_counter_sum_and_set(struct percpu_counter *fbc)
52{
53 return __percpu_counter_sum(fbc, 1);
54}
55
56
51static inline s64 percpu_counter_sum(struct percpu_counter *fbc) 57static inline s64 percpu_counter_sum(struct percpu_counter *fbc)
52{ 58{
53 return __percpu_counter_sum(fbc); 59 return __percpu_counter_sum(fbc, 0);
54} 60}
55 61
56static inline s64 percpu_counter_read(struct percpu_counter *fbc) 62static inline s64 percpu_counter_read(struct percpu_counter *fbc)
diff --git a/include/linux/preempt.h b/include/linux/preempt.h
index 23f0c54175cd..72b1a10a59b6 100644
--- a/include/linux/preempt.h
+++ b/include/linux/preempt.h
@@ -10,7 +10,7 @@
10#include <linux/linkage.h> 10#include <linux/linkage.h>
11#include <linux/list.h> 11#include <linux/list.h>
12 12
13#ifdef CONFIG_DEBUG_PREEMPT 13#if defined(CONFIG_DEBUG_PREEMPT) || defined(CONFIG_PREEMPT_TRACER)
14 extern void add_preempt_count(int val); 14 extern void add_preempt_count(int val);
15 extern void sub_preempt_count(int val); 15 extern void sub_preempt_count(int val);
16#else 16#else
@@ -52,6 +52,34 @@ do { \
52 preempt_check_resched(); \ 52 preempt_check_resched(); \
53} while (0) 53} while (0)
54 54
55/* For debugging and tracer internals only! */
56#define add_preempt_count_notrace(val) \
57 do { preempt_count() += (val); } while (0)
58#define sub_preempt_count_notrace(val) \
59 do { preempt_count() -= (val); } while (0)
60#define inc_preempt_count_notrace() add_preempt_count_notrace(1)
61#define dec_preempt_count_notrace() sub_preempt_count_notrace(1)
62
63#define preempt_disable_notrace() \
64do { \
65 inc_preempt_count_notrace(); \
66 barrier(); \
67} while (0)
68
69#define preempt_enable_no_resched_notrace() \
70do { \
71 barrier(); \
72 dec_preempt_count_notrace(); \
73} while (0)
74
75/* preempt_check_resched is OK to trace */
76#define preempt_enable_notrace() \
77do { \
78 preempt_enable_no_resched_notrace(); \
79 barrier(); \
80 preempt_check_resched(); \
81} while (0)
82
55#else 83#else
56 84
57#define preempt_disable() do { } while (0) 85#define preempt_disable() do { } while (0)
@@ -59,6 +87,10 @@ do { \
59#define preempt_enable() do { } while (0) 87#define preempt_enable() do { } while (0)
60#define preempt_check_resched() do { } while (0) 88#define preempt_check_resched() do { } while (0)
61 89
90#define preempt_disable_notrace() do { } while (0)
91#define preempt_enable_no_resched_notrace() do { } while (0)
92#define preempt_enable_notrace() do { } while (0)
93
62#endif 94#endif
63 95
64#ifdef CONFIG_PREEMPT_NOTIFIERS 96#ifdef CONFIG_PREEMPT_NOTIFIERS
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h
index f98501ba557e..c6f5f9dd0cee 100644
--- a/include/linux/ptrace.h
+++ b/include/linux/ptrace.h
@@ -95,8 +95,12 @@ extern void __ptrace_link(struct task_struct *child,
95 struct task_struct *new_parent); 95 struct task_struct *new_parent);
96extern void __ptrace_unlink(struct task_struct *child); 96extern void __ptrace_unlink(struct task_struct *child);
97extern void ptrace_untrace(struct task_struct *child); 97extern void ptrace_untrace(struct task_struct *child);
98extern int ptrace_may_attach(struct task_struct *task); 98#define PTRACE_MODE_READ 1
99extern int __ptrace_may_attach(struct task_struct *task); 99#define PTRACE_MODE_ATTACH 2
100/* Returns 0 on success, -errno on denial. */
101extern int __ptrace_may_access(struct task_struct *task, unsigned int mode);
102/* Returns true on success, false on denial. */
103extern bool ptrace_may_access(struct task_struct *task, unsigned int mode);
100 104
101static inline int ptrace_reparented(struct task_struct *child) 105static inline int ptrace_reparented(struct task_struct *child)
102{ 106{
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
new file mode 100644
index 000000000000..3945f803d514
--- /dev/null
+++ b/include/linux/pwm.h
@@ -0,0 +1,31 @@
1#ifndef __LINUX_PWM_H
2#define __LINUX_PWM_H
3
4struct pwm_device;
5
6/*
7 * pwm_request - request a PWM device
8 */
9struct pwm_device *pwm_request(int pwm_id, const char *label);
10
11/*
12 * pwm_free - free a PWM device
13 */
14void pwm_free(struct pwm_device *pwm);
15
16/*
17 * pwm_config - change a PWM device configuration
18 */
19int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns);
20
21/*
22 * pwm_enable - start a PWM output toggling
23 */
24int pwm_enable(struct pwm_device *pwm);
25
26/*
27 * pwm_disable - stop a PWM output toggling
28 */
29void pwm_disable(struct pwm_device *pwm);
30
31#endif /* __ASM_ARCH_PWM_H */
diff --git a/include/linux/pwm_backlight.h b/include/linux/pwm_backlight.h
new file mode 100644
index 000000000000..7a9754c96775
--- /dev/null
+++ b/include/linux/pwm_backlight.h
@@ -0,0 +1,17 @@
1/*
2 * Generic PWM backlight driver data - see drivers/video/backlight/pwm_bl.c
3 */
4#ifndef __LINUX_PWM_BACKLIGHT_H
5#define __LINUX_PWM_BACKLIGHT_H
6
7struct platform_pwm_backlight_data {
8 int pwm_id;
9 unsigned int max_brightness;
10 unsigned int dft_brightness;
11 unsigned int pwm_period_ns;
12 int (*init)(struct device *dev);
13 int (*notify)(int brightness);
14 void (*exit)(struct device *dev);
15};
16
17#endif
diff --git a/include/linux/rcuclassic.h b/include/linux/rcuclassic.h
index b3aa05baab8a..8c774905dcfe 100644
--- a/include/linux/rcuclassic.h
+++ b/include/linux/rcuclassic.h
@@ -151,7 +151,10 @@ extern struct lockdep_map rcu_lock_map;
151 151
152#define __synchronize_sched() synchronize_rcu() 152#define __synchronize_sched() synchronize_rcu()
153 153
154#define call_rcu_sched(head, func) call_rcu(head, func)
155
154extern void __rcu_init(void); 156extern void __rcu_init(void);
157#define rcu_init_sched() do { } while (0)
155extern void rcu_check_callbacks(int cpu, int user); 158extern void rcu_check_callbacks(int cpu, int user);
156extern void rcu_restart_cpu(int cpu); 159extern void rcu_restart_cpu(int cpu);
157 160
diff --git a/include/linux/rculist.h b/include/linux/rculist.h
index bde4586f4382..b0f39be08b6c 100644
--- a/include/linux/rculist.h
+++ b/include/linux/rculist.h
@@ -1,6 +1,373 @@
1#ifndef _LINUX_RCULIST_H 1#ifndef _LINUX_RCULIST_H
2#define _LINUX_RCULIST_H 2#define _LINUX_RCULIST_H
3 3
4#ifdef __KERNEL__
5
6/*
7 * RCU-protected list version
8 */
4#include <linux/list.h> 9#include <linux/list.h>
10#include <linux/rcupdate.h>
11
12/*
13 * Insert a new entry between two known consecutive entries.
14 *
15 * This is only for internal list manipulation where we know
16 * the prev/next entries already!
17 */
18static inline void __list_add_rcu(struct list_head *new,
19 struct list_head *prev, struct list_head *next)
20{
21 new->next = next;
22 new->prev = prev;
23 rcu_assign_pointer(prev->next, new);
24 next->prev = new;
25}
26
27/**
28 * list_add_rcu - add a new entry to rcu-protected list
29 * @new: new entry to be added
30 * @head: list head to add it after
31 *
32 * Insert a new entry after the specified head.
33 * This is good for implementing stacks.
34 *
35 * The caller must take whatever precautions are necessary
36 * (such as holding appropriate locks) to avoid racing
37 * with another list-mutation primitive, such as list_add_rcu()
38 * or list_del_rcu(), running on this same list.
39 * However, it is perfectly legal to run concurrently with
40 * the _rcu list-traversal primitives, such as
41 * list_for_each_entry_rcu().
42 */
43static inline void list_add_rcu(struct list_head *new, struct list_head *head)
44{
45 __list_add_rcu(new, head, head->next);
46}
47
48/**
49 * list_add_tail_rcu - add a new entry to rcu-protected list
50 * @new: new entry to be added
51 * @head: list head to add it before
52 *
53 * Insert a new entry before the specified head.
54 * This is useful for implementing queues.
55 *
56 * The caller must take whatever precautions are necessary
57 * (such as holding appropriate locks) to avoid racing
58 * with another list-mutation primitive, such as list_add_tail_rcu()
59 * or list_del_rcu(), running on this same list.
60 * However, it is perfectly legal to run concurrently with
61 * the _rcu list-traversal primitives, such as
62 * list_for_each_entry_rcu().
63 */
64static inline void list_add_tail_rcu(struct list_head *new,
65 struct list_head *head)
66{
67 __list_add_rcu(new, head->prev, head);
68}
69
70/**
71 * list_del_rcu - deletes entry from list without re-initialization
72 * @entry: the element to delete from the list.
73 *
74 * Note: list_empty() on entry does not return true after this,
75 * the entry is in an undefined state. It is useful for RCU based
76 * lockfree traversal.
77 *
78 * In particular, it means that we can not poison the forward
79 * pointers that may still be used for walking the list.
80 *
81 * The caller must take whatever precautions are necessary
82 * (such as holding appropriate locks) to avoid racing
83 * with another list-mutation primitive, such as list_del_rcu()
84 * or list_add_rcu(), running on this same list.
85 * However, it is perfectly legal to run concurrently with
86 * the _rcu list-traversal primitives, such as
87 * list_for_each_entry_rcu().
88 *
89 * Note that the caller is not permitted to immediately free
90 * the newly deleted entry. Instead, either synchronize_rcu()
91 * or call_rcu() must be used to defer freeing until an RCU
92 * grace period has elapsed.
93 */
94static inline void list_del_rcu(struct list_head *entry)
95{
96 __list_del(entry->prev, entry->next);
97 entry->prev = LIST_POISON2;
98}
99
100/**
101 * list_replace_rcu - replace old entry by new one
102 * @old : the element to be replaced
103 * @new : the new element to insert
104 *
105 * The @old entry will be replaced with the @new entry atomically.
106 * Note: @old should not be empty.
107 */
108static inline void list_replace_rcu(struct list_head *old,
109 struct list_head *new)
110{
111 new->next = old->next;
112 new->prev = old->prev;
113 rcu_assign_pointer(new->prev->next, new);
114 new->next->prev = new;
115 old->prev = LIST_POISON2;
116}
117
118/**
119 * list_splice_init_rcu - splice an RCU-protected list into an existing list.
120 * @list: the RCU-protected list to splice
121 * @head: the place in the list to splice the first list into
122 * @sync: function to sync: synchronize_rcu(), synchronize_sched(), ...
123 *
124 * @head can be RCU-read traversed concurrently with this function.
125 *
126 * Note that this function blocks.
127 *
128 * Important note: the caller must take whatever action is necessary to
129 * prevent any other updates to @head. In principle, it is possible
130 * to modify the list as soon as sync() begins execution.
131 * If this sort of thing becomes necessary, an alternative version
132 * based on call_rcu() could be created. But only if -really-
133 * needed -- there is no shortage of RCU API members.
134 */
135static inline void list_splice_init_rcu(struct list_head *list,
136 struct list_head *head,
137 void (*sync)(void))
138{
139 struct list_head *first = list->next;
140 struct list_head *last = list->prev;
141 struct list_head *at = head->next;
142
143 if (list_empty(head))
144 return;
145
146 /* "first" and "last" tracking list, so initialize it. */
147
148 INIT_LIST_HEAD(list);
149
150 /*
151 * At this point, the list body still points to the source list.
152 * Wait for any readers to finish using the list before splicing
153 * the list body into the new list. Any new readers will see
154 * an empty list.
155 */
156
157 sync();
158
159 /*
160 * Readers are finished with the source list, so perform splice.
161 * The order is important if the new list is global and accessible
162 * to concurrent RCU readers. Note that RCU readers are not
163 * permitted to traverse the prev pointers without excluding
164 * this function.
165 */
166
167 last->next = at;
168 rcu_assign_pointer(head->next, first);
169 first->prev = head;
170 at->prev = last;
171}
172
173/**
174 * list_for_each_rcu - iterate over an rcu-protected list
175 * @pos: the &struct list_head to use as a loop cursor.
176 * @head: the head for your list.
177 *
178 * This list-traversal primitive may safely run concurrently with
179 * the _rcu list-mutation primitives such as list_add_rcu()
180 * as long as the traversal is guarded by rcu_read_lock().
181 */
182#define list_for_each_rcu(pos, head) \
183 for (pos = rcu_dereference((head)->next); \
184 prefetch(pos->next), pos != (head); \
185 pos = rcu_dereference(pos->next))
186
187#define __list_for_each_rcu(pos, head) \
188 for (pos = rcu_dereference((head)->next); \
189 pos != (head); \
190 pos = rcu_dereference(pos->next))
191
192/**
193 * list_for_each_entry_rcu - iterate over rcu list of given type
194 * @pos: the type * to use as a loop cursor.
195 * @head: the head for your list.
196 * @member: the name of the list_struct within the struct.
197 *
198 * This list-traversal primitive may safely run concurrently with
199 * the _rcu list-mutation primitives such as list_add_rcu()
200 * as long as the traversal is guarded by rcu_read_lock().
201 */
202#define list_for_each_entry_rcu(pos, head, member) \
203 for (pos = list_entry(rcu_dereference((head)->next), typeof(*pos), member); \
204 prefetch(pos->member.next), &pos->member != (head); \
205 pos = list_entry(rcu_dereference(pos->member.next), typeof(*pos), member))
206
207
208/**
209 * list_for_each_continue_rcu
210 * @pos: the &struct list_head to use as a loop cursor.
211 * @head: the head for your list.
212 *
213 * Iterate over an rcu-protected list, continuing after current point.
214 *
215 * This list-traversal primitive may safely run concurrently with
216 * the _rcu list-mutation primitives such as list_add_rcu()
217 * as long as the traversal is guarded by rcu_read_lock().
218 */
219#define list_for_each_continue_rcu(pos, head) \
220 for ((pos) = rcu_dereference((pos)->next); \
221 prefetch((pos)->next), (pos) != (head); \
222 (pos) = rcu_dereference((pos)->next))
223
224/**
225 * hlist_del_rcu - deletes entry from hash list without re-initialization
226 * @n: the element to delete from the hash list.
227 *
228 * Note: list_unhashed() on entry does not return true after this,
229 * the entry is in an undefined state. It is useful for RCU based
230 * lockfree traversal.
231 *
232 * In particular, it means that we can not poison the forward
233 * pointers that may still be used for walking the hash list.
234 *
235 * The caller must take whatever precautions are necessary
236 * (such as holding appropriate locks) to avoid racing
237 * with another list-mutation primitive, such as hlist_add_head_rcu()
238 * or hlist_del_rcu(), running on this same list.
239 * However, it is perfectly legal to run concurrently with
240 * the _rcu list-traversal primitives, such as
241 * hlist_for_each_entry().
242 */
243static inline void hlist_del_rcu(struct hlist_node *n)
244{
245 __hlist_del(n);
246 n->pprev = LIST_POISON2;
247}
248
249/**
250 * hlist_replace_rcu - replace old entry by new one
251 * @old : the element to be replaced
252 * @new : the new element to insert
253 *
254 * The @old entry will be replaced with the @new entry atomically.
255 */
256static inline void hlist_replace_rcu(struct hlist_node *old,
257 struct hlist_node *new)
258{
259 struct hlist_node *next = old->next;
260
261 new->next = next;
262 new->pprev = old->pprev;
263 rcu_assign_pointer(*new->pprev, new);
264 if (next)
265 new->next->pprev = &new->next;
266 old->pprev = LIST_POISON2;
267}
268
269/**
270 * hlist_add_head_rcu
271 * @n: the element to add to the hash list.
272 * @h: the list to add to.
273 *
274 * Description:
275 * Adds the specified element to the specified hlist,
276 * while permitting racing traversals.
277 *
278 * The caller must take whatever precautions are necessary
279 * (such as holding appropriate locks) to avoid racing
280 * with another list-mutation primitive, such as hlist_add_head_rcu()
281 * or hlist_del_rcu(), running on this same list.
282 * However, it is perfectly legal to run concurrently with
283 * the _rcu list-traversal primitives, such as
284 * hlist_for_each_entry_rcu(), used to prevent memory-consistency
285 * problems on Alpha CPUs. Regardless of the type of CPU, the
286 * list-traversal primitive must be guarded by rcu_read_lock().
287 */
288static inline void hlist_add_head_rcu(struct hlist_node *n,
289 struct hlist_head *h)
290{
291 struct hlist_node *first = h->first;
292
293 n->next = first;
294 n->pprev = &h->first;
295 rcu_assign_pointer(h->first, n);
296 if (first)
297 first->pprev = &n->next;
298}
299
300/**
301 * hlist_add_before_rcu
302 * @n: the new element to add to the hash list.
303 * @next: the existing element to add the new element before.
304 *
305 * Description:
306 * Adds the specified element to the specified hlist
307 * before the specified node while permitting racing traversals.
308 *
309 * The caller must take whatever precautions are necessary
310 * (such as holding appropriate locks) to avoid racing
311 * with another list-mutation primitive, such as hlist_add_head_rcu()
312 * or hlist_del_rcu(), running on this same list.
313 * However, it is perfectly legal to run concurrently with
314 * the _rcu list-traversal primitives, such as
315 * hlist_for_each_entry_rcu(), used to prevent memory-consistency
316 * problems on Alpha CPUs.
317 */
318static inline void hlist_add_before_rcu(struct hlist_node *n,
319 struct hlist_node *next)
320{
321 n->pprev = next->pprev;
322 n->next = next;
323 rcu_assign_pointer(*(n->pprev), n);
324 next->pprev = &n->next;
325}
326
327/**
328 * hlist_add_after_rcu
329 * @prev: the existing element to add the new element after.
330 * @n: the new element to add to the hash list.
331 *
332 * Description:
333 * Adds the specified element to the specified hlist
334 * after the specified node while permitting racing traversals.
335 *
336 * The caller must take whatever precautions are necessary
337 * (such as holding appropriate locks) to avoid racing
338 * with another list-mutation primitive, such as hlist_add_head_rcu()
339 * or hlist_del_rcu(), running on this same list.
340 * However, it is perfectly legal to run concurrently with
341 * the _rcu list-traversal primitives, such as
342 * hlist_for_each_entry_rcu(), used to prevent memory-consistency
343 * problems on Alpha CPUs.
344 */
345static inline void hlist_add_after_rcu(struct hlist_node *prev,
346 struct hlist_node *n)
347{
348 n->next = prev->next;
349 n->pprev = &prev->next;
350 rcu_assign_pointer(prev->next, n);
351 if (n->next)
352 n->next->pprev = &n->next;
353}
354
355/**
356 * hlist_for_each_entry_rcu - iterate over rcu list of given type
357 * @tpos: the type * to use as a loop cursor.
358 * @pos: the &struct hlist_node to use as a loop cursor.
359 * @head: the head for your list.
360 * @member: the name of the hlist_node within the struct.
361 *
362 * This list-traversal primitive may safely run concurrently with
363 * the _rcu list-mutation primitives such as hlist_add_head_rcu()
364 * as long as the traversal is guarded by rcu_read_lock().
365 */
366#define hlist_for_each_entry_rcu(tpos, pos, head, member) \
367 for (pos = rcu_dereference((head)->first); \
368 pos && ({ prefetch(pos->next); 1; }) && \
369 ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); \
370 pos = rcu_dereference(pos->next))
5 371
6#endif /* _LINUX_RCULIST_H */ 372#endif /* __KERNEL__ */
373#endif
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index d42dbec06083..e8b4039cfb2f 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -40,6 +40,7 @@
40#include <linux/cpumask.h> 40#include <linux/cpumask.h>
41#include <linux/seqlock.h> 41#include <linux/seqlock.h>
42#include <linux/lockdep.h> 42#include <linux/lockdep.h>
43#include <linux/completion.h>
43 44
44/** 45/**
45 * struct rcu_head - callback structure for use with RCU 46 * struct rcu_head - callback structure for use with RCU
@@ -168,6 +169,27 @@ struct rcu_head {
168 (p) = (v); \ 169 (p) = (v); \
169 }) 170 })
170 171
172/* Infrastructure to implement the synchronize_() primitives. */
173
174struct rcu_synchronize {
175 struct rcu_head head;
176 struct completion completion;
177};
178
179extern void wakeme_after_rcu(struct rcu_head *head);
180
181#define synchronize_rcu_xxx(name, func) \
182void name(void) \
183{ \
184 struct rcu_synchronize rcu; \
185 \
186 init_completion(&rcu.completion); \
187 /* Will wake me after RCU finished. */ \
188 func(&rcu.head, wakeme_after_rcu); \
189 /* Wait for it. */ \
190 wait_for_completion(&rcu.completion); \
191}
192
171/** 193/**
172 * synchronize_sched - block until all CPUs have exited any non-preemptive 194 * synchronize_sched - block until all CPUs have exited any non-preemptive
173 * kernel code sequences. 195 * kernel code sequences.
@@ -224,8 +246,8 @@ extern void call_rcu_bh(struct rcu_head *head,
224/* Exported common interfaces */ 246/* Exported common interfaces */
225extern void synchronize_rcu(void); 247extern void synchronize_rcu(void);
226extern void rcu_barrier(void); 248extern void rcu_barrier(void);
227extern long rcu_batches_completed(void); 249extern void rcu_barrier_bh(void);
228extern long rcu_batches_completed_bh(void); 250extern void rcu_barrier_sched(void);
229 251
230/* Internal to kernel */ 252/* Internal to kernel */
231extern void rcu_init(void); 253extern void rcu_init(void);
diff --git a/include/linux/rcupreempt.h b/include/linux/rcupreempt.h
index 8a05c7e20bc4..f04b64eca636 100644
--- a/include/linux/rcupreempt.h
+++ b/include/linux/rcupreempt.h
@@ -40,10 +40,39 @@
40#include <linux/cpumask.h> 40#include <linux/cpumask.h>
41#include <linux/seqlock.h> 41#include <linux/seqlock.h>
42 42
43#define rcu_qsctr_inc(cpu) 43struct rcu_dyntick_sched {
44 int dynticks;
45 int dynticks_snap;
46 int sched_qs;
47 int sched_qs_snap;
48 int sched_dynticks_snap;
49};
50
51DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched);
52
53static inline void rcu_qsctr_inc(int cpu)
54{
55 struct rcu_dyntick_sched *rdssp = &per_cpu(rcu_dyntick_sched, cpu);
56
57 rdssp->sched_qs++;
58}
44#define rcu_bh_qsctr_inc(cpu) 59#define rcu_bh_qsctr_inc(cpu)
45#define call_rcu_bh(head, rcu) call_rcu(head, rcu) 60#define call_rcu_bh(head, rcu) call_rcu(head, rcu)
46 61
62/**
63 * call_rcu_sched - Queue RCU callback for invocation after sched grace period.
64 * @head: structure to be used for queueing the RCU updates.
65 * @func: actual update function to be invoked after the grace period
66 *
67 * The update function will be invoked some time after a full
68 * synchronize_sched()-style grace period elapses, in other words after
69 * all currently executing preempt-disabled sections of code (including
70 * hardirq handlers, NMI handlers, and local_irq_save() blocks) have
71 * completed.
72 */
73extern void call_rcu_sched(struct rcu_head *head,
74 void (*func)(struct rcu_head *head));
75
47extern void __rcu_read_lock(void) __acquires(RCU); 76extern void __rcu_read_lock(void) __acquires(RCU);
48extern void __rcu_read_unlock(void) __releases(RCU); 77extern void __rcu_read_unlock(void) __releases(RCU);
49extern int rcu_pending(int cpu); 78extern int rcu_pending(int cpu);
@@ -55,6 +84,7 @@ extern int rcu_needs_cpu(int cpu);
55extern void __synchronize_sched(void); 84extern void __synchronize_sched(void);
56 85
57extern void __rcu_init(void); 86extern void __rcu_init(void);
87extern void rcu_init_sched(void);
58extern void rcu_check_callbacks(int cpu, int user); 88extern void rcu_check_callbacks(int cpu, int user);
59extern void rcu_restart_cpu(int cpu); 89extern void rcu_restart_cpu(int cpu);
60extern long rcu_batches_completed(void); 90extern long rcu_batches_completed(void);
@@ -81,20 +111,20 @@ extern struct rcupreempt_trace *rcupreempt_trace_cpu(int cpu);
81struct softirq_action; 111struct softirq_action;
82 112
83#ifdef CONFIG_NO_HZ 113#ifdef CONFIG_NO_HZ
84DECLARE_PER_CPU(long, dynticks_progress_counter); 114DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched);
85 115
86static inline void rcu_enter_nohz(void) 116static inline void rcu_enter_nohz(void)
87{ 117{
88 smp_mb(); /* CPUs seeing ++ must see prior RCU read-side crit sects */ 118 smp_mb(); /* CPUs seeing ++ must see prior RCU read-side crit sects */
89 __get_cpu_var(dynticks_progress_counter)++; 119 __get_cpu_var(rcu_dyntick_sched).dynticks++;
90 WARN_ON(__get_cpu_var(dynticks_progress_counter) & 0x1); 120 WARN_ON(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1);
91} 121}
92 122
93static inline void rcu_exit_nohz(void) 123static inline void rcu_exit_nohz(void)
94{ 124{
95 __get_cpu_var(dynticks_progress_counter)++;
96 smp_mb(); /* CPUs seeing ++ must see later RCU read-side crit sects */ 125 smp_mb(); /* CPUs seeing ++ must see later RCU read-side crit sects */
97 WARN_ON(!(__get_cpu_var(dynticks_progress_counter) & 0x1)); 126 __get_cpu_var(rcu_dyntick_sched).dynticks++;
127 WARN_ON(!(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1));
98} 128}
99 129
100#else /* CONFIG_NO_HZ */ 130#else /* CONFIG_NO_HZ */
diff --git a/include/linux/resume-trace.h b/include/linux/resume-trace.h
index f3f4f28c6960..c9ba2fdf807d 100644
--- a/include/linux/resume-trace.h
+++ b/include/linux/resume-trace.h
@@ -8,7 +8,7 @@ extern int pm_trace_enabled;
8 8
9struct device; 9struct device;
10extern void set_trace_device(struct device *); 10extern void set_trace_device(struct device *);
11extern void generate_resume_trace(void *tracedata, unsigned int user); 11extern void generate_resume_trace(const void *tracedata, unsigned int user);
12 12
13#define TRACE_DEVICE(dev) do { \ 13#define TRACE_DEVICE(dev) do { \
14 if (pm_trace_enabled) \ 14 if (pm_trace_enabled) \
diff --git a/include/linux/sched.h b/include/linux/sched.h
index c5d3f847ca8d..21349173d148 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -134,7 +134,6 @@ extern unsigned long nr_running(void);
134extern unsigned long nr_uninterruptible(void); 134extern unsigned long nr_uninterruptible(void);
135extern unsigned long nr_active(void); 135extern unsigned long nr_active(void);
136extern unsigned long nr_iowait(void); 136extern unsigned long nr_iowait(void);
137extern unsigned long weighted_cpuload(const int cpu);
138 137
139struct seq_file; 138struct seq_file;
140struct cfs_rq; 139struct cfs_rq;
@@ -246,6 +245,8 @@ extern asmlinkage void schedule_tail(struct task_struct *prev);
246extern void init_idle(struct task_struct *idle, int cpu); 245extern void init_idle(struct task_struct *idle, int cpu);
247extern void init_idle_bootup_task(struct task_struct *idle); 246extern void init_idle_bootup_task(struct task_struct *idle);
248 247
248extern int runqueue_is_locked(void);
249
249extern cpumask_t nohz_cpu_mask; 250extern cpumask_t nohz_cpu_mask;
250#if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ) 251#if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ)
251extern int select_nohz_load_balancer(int cpu); 252extern int select_nohz_load_balancer(int cpu);
@@ -784,6 +785,8 @@ struct sched_domain {
784 unsigned int balance_interval; /* initialise to 1. units in ms. */ 785 unsigned int balance_interval; /* initialise to 1. units in ms. */
785 unsigned int nr_balance_failed; /* initialise to 0 */ 786 unsigned int nr_balance_failed; /* initialise to 0 */
786 787
788 u64 last_update;
789
787#ifdef CONFIG_SCHEDSTATS 790#ifdef CONFIG_SCHEDSTATS
788 /* load_balance() stats */ 791 /* load_balance() stats */
789 unsigned int lb_count[CPU_MAX_IDLE_TYPES]; 792 unsigned int lb_count[CPU_MAX_IDLE_TYPES];
@@ -823,23 +826,6 @@ extern int arch_reinit_sched_domains(void);
823 826
824#endif /* CONFIG_SMP */ 827#endif /* CONFIG_SMP */
825 828
826/*
827 * A runqueue laden with a single nice 0 task scores a weighted_cpuload of
828 * SCHED_LOAD_SCALE. This function returns 1 if any cpu is laden with a
829 * task of nice 0 or enough lower priority tasks to bring up the
830 * weighted_cpuload
831 */
832static inline int above_background_load(void)
833{
834 unsigned long cpu;
835
836 for_each_online_cpu(cpu) {
837 if (weighted_cpuload(cpu) >= SCHED_LOAD_SCALE)
838 return 1;
839 }
840 return 0;
841}
842
843struct io_context; /* See blkdev.h */ 829struct io_context; /* See blkdev.h */
844#define NGROUPS_SMALL 32 830#define NGROUPS_SMALL 32
845#define NGROUPS_PER_BLOCK ((unsigned int)(PAGE_SIZE / sizeof(gid_t))) 831#define NGROUPS_PER_BLOCK ((unsigned int)(PAGE_SIZE / sizeof(gid_t)))
@@ -921,8 +907,8 @@ struct sched_class {
921 void (*set_cpus_allowed)(struct task_struct *p, 907 void (*set_cpus_allowed)(struct task_struct *p,
922 const cpumask_t *newmask); 908 const cpumask_t *newmask);
923 909
924 void (*join_domain)(struct rq *rq); 910 void (*rq_online)(struct rq *rq);
925 void (*leave_domain)(struct rq *rq); 911 void (*rq_offline)(struct rq *rq);
926 912
927 void (*switched_from) (struct rq *this_rq, struct task_struct *task, 913 void (*switched_from) (struct rq *this_rq, struct task_struct *task,
928 int running); 914 int running);
@@ -1039,6 +1025,7 @@ struct task_struct {
1039#endif 1025#endif
1040 1026
1041 int prio, static_prio, normal_prio; 1027 int prio, static_prio, normal_prio;
1028 unsigned int rt_priority;
1042 const struct sched_class *sched_class; 1029 const struct sched_class *sched_class;
1043 struct sched_entity se; 1030 struct sched_entity se;
1044 struct sched_rt_entity rt; 1031 struct sched_rt_entity rt;
@@ -1122,7 +1109,6 @@ struct task_struct {
1122 int __user *set_child_tid; /* CLONE_CHILD_SETTID */ 1109 int __user *set_child_tid; /* CLONE_CHILD_SETTID */
1123 int __user *clear_child_tid; /* CLONE_CHILD_CLEARTID */ 1110 int __user *clear_child_tid; /* CLONE_CHILD_CLEARTID */
1124 1111
1125 unsigned int rt_priority;
1126 cputime_t utime, stime, utimescaled, stimescaled; 1112 cputime_t utime, stime, utimescaled, stimescaled;
1127 cputime_t gtime; 1113 cputime_t gtime;
1128 cputime_t prev_utime, prev_stime; 1114 cputime_t prev_utime, prev_stime;
@@ -1141,12 +1127,12 @@ struct task_struct {
1141 gid_t gid,egid,sgid,fsgid; 1127 gid_t gid,egid,sgid,fsgid;
1142 struct group_info *group_info; 1128 struct group_info *group_info;
1143 kernel_cap_t cap_effective, cap_inheritable, cap_permitted, cap_bset; 1129 kernel_cap_t cap_effective, cap_inheritable, cap_permitted, cap_bset;
1144 unsigned securebits;
1145 struct user_struct *user; 1130 struct user_struct *user;
1131 unsigned securebits;
1146#ifdef CONFIG_KEYS 1132#ifdef CONFIG_KEYS
1133 unsigned char jit_keyring; /* default keyring to attach requested keys to */
1147 struct key *request_key_auth; /* assumed request_key authority */ 1134 struct key *request_key_auth; /* assumed request_key authority */
1148 struct key *thread_keyring; /* keyring private to this thread */ 1135 struct key *thread_keyring; /* keyring private to this thread */
1149 unsigned char jit_keyring; /* default keyring to attach requested keys to */
1150#endif 1136#endif
1151 char comm[TASK_COMM_LEN]; /* executable name excluding path 1137 char comm[TASK_COMM_LEN]; /* executable name excluding path
1152 - access with [gs]et_task_comm (which lock 1138 - access with [gs]et_task_comm (which lock
@@ -1233,8 +1219,8 @@ struct task_struct {
1233# define MAX_LOCK_DEPTH 48UL 1219# define MAX_LOCK_DEPTH 48UL
1234 u64 curr_chain_key; 1220 u64 curr_chain_key;
1235 int lockdep_depth; 1221 int lockdep_depth;
1236 struct held_lock held_locks[MAX_LOCK_DEPTH];
1237 unsigned int lockdep_recursion; 1222 unsigned int lockdep_recursion;
1223 struct held_lock held_locks[MAX_LOCK_DEPTH];
1238#endif 1224#endif
1239 1225
1240/* journalling filesystem info */ 1226/* journalling filesystem info */
@@ -1262,10 +1248,6 @@ struct task_struct {
1262 u64 acct_vm_mem1; /* accumulated virtual memory usage */ 1248 u64 acct_vm_mem1; /* accumulated virtual memory usage */
1263 cputime_t acct_stimexpd;/* stime since last update */ 1249 cputime_t acct_stimexpd;/* stime since last update */
1264#endif 1250#endif
1265#ifdef CONFIG_NUMA
1266 struct mempolicy *mempolicy;
1267 short il_next;
1268#endif
1269#ifdef CONFIG_CPUSETS 1251#ifdef CONFIG_CPUSETS
1270 nodemask_t mems_allowed; 1252 nodemask_t mems_allowed;
1271 int cpuset_mems_generation; 1253 int cpuset_mems_generation;
@@ -1285,6 +1267,10 @@ struct task_struct {
1285 struct list_head pi_state_list; 1267 struct list_head pi_state_list;
1286 struct futex_pi_state *pi_state_cache; 1268 struct futex_pi_state *pi_state_cache;
1287#endif 1269#endif
1270#ifdef CONFIG_NUMA
1271 struct mempolicy *mempolicy;
1272 short il_next;
1273#endif
1288 atomic_t fs_excl; /* holding fs exclusive resources */ 1274 atomic_t fs_excl; /* holding fs exclusive resources */
1289 struct rcu_head rcu; 1275 struct rcu_head rcu;
1290 1276
@@ -1504,6 +1490,7 @@ static inline void put_task_struct(struct task_struct *t)
1504#define PF_SWAPWRITE 0x00800000 /* Allowed to write to swap */ 1490#define PF_SWAPWRITE 0x00800000 /* Allowed to write to swap */
1505#define PF_SPREAD_PAGE 0x01000000 /* Spread page cache over cpuset */ 1491#define PF_SPREAD_PAGE 0x01000000 /* Spread page cache over cpuset */
1506#define PF_SPREAD_SLAB 0x02000000 /* Spread some slab caches over cpuset */ 1492#define PF_SPREAD_SLAB 0x02000000 /* Spread some slab caches over cpuset */
1493#define PF_THREAD_BOUND 0x04000000 /* Thread bound to specific cpu */
1507#define PF_MEMPOLICY 0x10000000 /* Non-default NUMA mempolicy */ 1494#define PF_MEMPOLICY 0x10000000 /* Non-default NUMA mempolicy */
1508#define PF_MUTEX_TESTER 0x20000000 /* Thread belongs to the rt mutex tester */ 1495#define PF_MUTEX_TESTER 0x20000000 /* Thread belongs to the rt mutex tester */
1509#define PF_FREEZER_SKIP 0x40000000 /* Freezer should not count it as freezeable */ 1496#define PF_FREEZER_SKIP 0x40000000 /* Freezer should not count it as freezeable */
@@ -1573,13 +1560,28 @@ static inline void sched_clock_idle_sleep_event(void)
1573static inline void sched_clock_idle_wakeup_event(u64 delta_ns) 1560static inline void sched_clock_idle_wakeup_event(u64 delta_ns)
1574{ 1561{
1575} 1562}
1576#else 1563
1564#ifdef CONFIG_NO_HZ
1565static inline void sched_clock_tick_stop(int cpu)
1566{
1567}
1568
1569static inline void sched_clock_tick_start(int cpu)
1570{
1571}
1572#endif
1573
1574#else /* CONFIG_HAVE_UNSTABLE_SCHED_CLOCK */
1577extern void sched_clock_init(void); 1575extern void sched_clock_init(void);
1578extern u64 sched_clock_cpu(int cpu); 1576extern u64 sched_clock_cpu(int cpu);
1579extern void sched_clock_tick(void); 1577extern void sched_clock_tick(void);
1580extern void sched_clock_idle_sleep_event(void); 1578extern void sched_clock_idle_sleep_event(void);
1581extern void sched_clock_idle_wakeup_event(u64 delta_ns); 1579extern void sched_clock_idle_wakeup_event(u64 delta_ns);
1580#ifdef CONFIG_NO_HZ
1581extern void sched_clock_tick_stop(int cpu);
1582extern void sched_clock_tick_start(int cpu);
1582#endif 1583#endif
1584#endif /* CONFIG_HAVE_UNSTABLE_SCHED_CLOCK */
1583 1585
1584/* 1586/*
1585 * For kernel-internal use: high-speed (but slightly incorrect) per-cpu 1587 * For kernel-internal use: high-speed (but slightly incorrect) per-cpu
@@ -1622,6 +1624,7 @@ extern unsigned int sysctl_sched_child_runs_first;
1622extern unsigned int sysctl_sched_features; 1624extern unsigned int sysctl_sched_features;
1623extern unsigned int sysctl_sched_migration_cost; 1625extern unsigned int sysctl_sched_migration_cost;
1624extern unsigned int sysctl_sched_nr_migrate; 1626extern unsigned int sysctl_sched_nr_migrate;
1627extern unsigned int sysctl_sched_shares_ratelimit;
1625 1628
1626int sched_nr_latency_handler(struct ctl_table *table, int write, 1629int sched_nr_latency_handler(struct ctl_table *table, int write,
1627 struct file *file, void __user *buffer, size_t *length, 1630 struct file *file, void __user *buffer, size_t *length,
@@ -1655,6 +1658,8 @@ extern int can_nice(const struct task_struct *p, const int nice);
1655extern int task_curr(const struct task_struct *p); 1658extern int task_curr(const struct task_struct *p);
1656extern int idle_cpu(int cpu); 1659extern int idle_cpu(int cpu);
1657extern int sched_setscheduler(struct task_struct *, int, struct sched_param *); 1660extern int sched_setscheduler(struct task_struct *, int, struct sched_param *);
1661extern int sched_setscheduler_nocheck(struct task_struct *, int,
1662 struct sched_param *);
1658extern struct task_struct *idle_task(int cpu); 1663extern struct task_struct *idle_task(int cpu);
1659extern struct task_struct *curr_task(int cpu); 1664extern struct task_struct *curr_task(int cpu);
1660extern void set_curr_task(int cpu, struct task_struct *p); 1665extern void set_curr_task(int cpu, struct task_struct *p);
@@ -2131,6 +2136,18 @@ static inline void arch_pick_mmap_layout(struct mm_struct *mm)
2131} 2136}
2132#endif 2137#endif
2133 2138
2139#ifdef CONFIG_TRACING
2140extern void
2141__trace_special(void *__tr, void *__data,
2142 unsigned long arg1, unsigned long arg2, unsigned long arg3);
2143#else
2144static inline void
2145__trace_special(void *__tr, void *__data,
2146 unsigned long arg1, unsigned long arg2, unsigned long arg3)
2147{
2148}
2149#endif
2150
2134extern long sched_setaffinity(pid_t pid, const cpumask_t *new_mask); 2151extern long sched_setaffinity(pid_t pid, const cpumask_t *new_mask);
2135extern long sched_getaffinity(pid_t pid, cpumask_t *mask); 2152extern long sched_getaffinity(pid_t pid, cpumask_t *mask);
2136 2153
@@ -2225,6 +2242,8 @@ static inline void mm_init_owner(struct mm_struct *mm, struct task_struct *p)
2225} 2242}
2226#endif /* CONFIG_MM_OWNER */ 2243#endif /* CONFIG_MM_OWNER */
2227 2244
2245#define TASK_STATE_TO_CHAR_STR "RSDTtZX"
2246
2228#endif /* __KERNEL__ */ 2247#endif /* __KERNEL__ */
2229 2248
2230#endif 2249#endif
diff --git a/include/linux/security.h b/include/linux/security.h
index 50737c70e78e..31c8851ec5d0 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -46,7 +46,8 @@ struct audit_krule;
46 */ 46 */
47extern int cap_capable(struct task_struct *tsk, int cap); 47extern int cap_capable(struct task_struct *tsk, int cap);
48extern int cap_settime(struct timespec *ts, struct timezone *tz); 48extern int cap_settime(struct timespec *ts, struct timezone *tz);
49extern int cap_ptrace(struct task_struct *parent, struct task_struct *child); 49extern int cap_ptrace(struct task_struct *parent, struct task_struct *child,
50 unsigned int mode);
50extern int cap_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); 51extern int cap_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
51extern int cap_capset_check(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); 52extern int cap_capset_check(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
52extern void cap_capset_set(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted); 53extern void cap_capset_set(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
@@ -79,6 +80,7 @@ struct xfrm_selector;
79struct xfrm_policy; 80struct xfrm_policy;
80struct xfrm_state; 81struct xfrm_state;
81struct xfrm_user_sec_ctx; 82struct xfrm_user_sec_ctx;
83struct seq_file;
82 84
83extern int cap_netlink_send(struct sock *sk, struct sk_buff *skb); 85extern int cap_netlink_send(struct sock *sk, struct sk_buff *skb);
84extern int cap_netlink_recv(struct sk_buff *skb, int cap); 86extern int cap_netlink_recv(struct sk_buff *skb, int cap);
@@ -289,10 +291,6 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
289 * Update module state after a successful pivot. 291 * Update module state after a successful pivot.
290 * @old_path contains the path for the old root. 292 * @old_path contains the path for the old root.
291 * @new_path contains the path for the new root. 293 * @new_path contains the path for the new root.
292 * @sb_get_mnt_opts:
293 * Get the security relevant mount options used for a superblock
294 * @sb the superblock to get security mount options from
295 * @opts binary data structure containing all lsm mount data
296 * @sb_set_mnt_opts: 294 * @sb_set_mnt_opts:
297 * Set the security relevant mount options used for a superblock 295 * Set the security relevant mount options used for a superblock
298 * @sb the superblock to set security mount options for 296 * @sb the superblock to set security mount options for
@@ -1170,6 +1168,7 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
1170 * attributes would be changed by the execve. 1168 * attributes would be changed by the execve.
1171 * @parent contains the task_struct structure for parent process. 1169 * @parent contains the task_struct structure for parent process.
1172 * @child contains the task_struct structure for child process. 1170 * @child contains the task_struct structure for child process.
1171 * @mode contains the PTRACE_MODE flags indicating the form of access.
1173 * Return 0 if permission is granted. 1172 * Return 0 if permission is granted.
1174 * @capget: 1173 * @capget:
1175 * Get the @effective, @inheritable, and @permitted capability sets for 1174 * Get the @effective, @inheritable, and @permitted capability sets for
@@ -1240,11 +1239,6 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
1240 * @pages contains the number of pages. 1239 * @pages contains the number of pages.
1241 * Return 0 if permission is granted. 1240 * Return 0 if permission is granted.
1242 * 1241 *
1243 * @register_security:
1244 * allow module stacking.
1245 * @name contains the name of the security module being stacked.
1246 * @ops contains a pointer to the struct security_operations of the module to stack.
1247 *
1248 * @secid_to_secctx: 1242 * @secid_to_secctx:
1249 * Convert secid to security context. 1243 * Convert secid to security context.
1250 * @secid contains the security ID. 1244 * @secid contains the security ID.
@@ -1295,7 +1289,8 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
1295struct security_operations { 1289struct security_operations {
1296 char name[SECURITY_NAME_MAX + 1]; 1290 char name[SECURITY_NAME_MAX + 1];
1297 1291
1298 int (*ptrace) (struct task_struct *parent, struct task_struct *child); 1292 int (*ptrace) (struct task_struct *parent, struct task_struct *child,
1293 unsigned int mode);
1299 int (*capget) (struct task_struct *target, 1294 int (*capget) (struct task_struct *target,
1300 kernel_cap_t *effective, 1295 kernel_cap_t *effective,
1301 kernel_cap_t *inheritable, kernel_cap_t *permitted); 1296 kernel_cap_t *inheritable, kernel_cap_t *permitted);
@@ -1328,6 +1323,7 @@ struct security_operations {
1328 void (*sb_free_security) (struct super_block *sb); 1323 void (*sb_free_security) (struct super_block *sb);
1329 int (*sb_copy_data) (char *orig, char *copy); 1324 int (*sb_copy_data) (char *orig, char *copy);
1330 int (*sb_kern_mount) (struct super_block *sb, void *data); 1325 int (*sb_kern_mount) (struct super_block *sb, void *data);
1326 int (*sb_show_options) (struct seq_file *m, struct super_block *sb);
1331 int (*sb_statfs) (struct dentry *dentry); 1327 int (*sb_statfs) (struct dentry *dentry);
1332 int (*sb_mount) (char *dev_name, struct path *path, 1328 int (*sb_mount) (char *dev_name, struct path *path,
1333 char *type, unsigned long flags, void *data); 1329 char *type, unsigned long flags, void *data);
@@ -1343,8 +1339,6 @@ struct security_operations {
1343 struct path *new_path); 1339 struct path *new_path);
1344 void (*sb_post_pivotroot) (struct path *old_path, 1340 void (*sb_post_pivotroot) (struct path *old_path,
1345 struct path *new_path); 1341 struct path *new_path);
1346 int (*sb_get_mnt_opts) (const struct super_block *sb,
1347 struct security_mnt_opts *opts);
1348 int (*sb_set_mnt_opts) (struct super_block *sb, 1342 int (*sb_set_mnt_opts) (struct super_block *sb,
1349 struct security_mnt_opts *opts); 1343 struct security_mnt_opts *opts);
1350 void (*sb_clone_mnt_opts) (const struct super_block *oldsb, 1344 void (*sb_clone_mnt_opts) (const struct super_block *oldsb,
@@ -1472,10 +1466,6 @@ struct security_operations {
1472 int (*netlink_send) (struct sock *sk, struct sk_buff *skb); 1466 int (*netlink_send) (struct sock *sk, struct sk_buff *skb);
1473 int (*netlink_recv) (struct sk_buff *skb, int cap); 1467 int (*netlink_recv) (struct sk_buff *skb, int cap);
1474 1468
1475 /* allow module stacking */
1476 int (*register_security) (const char *name,
1477 struct security_operations *ops);
1478
1479 void (*d_instantiate) (struct dentry *dentry, struct inode *inode); 1469 void (*d_instantiate) (struct dentry *dentry, struct inode *inode);
1480 1470
1481 int (*getprocattr) (struct task_struct *p, char *name, char **value); 1471 int (*getprocattr) (struct task_struct *p, char *name, char **value);
@@ -1565,7 +1555,6 @@ struct security_operations {
1565extern int security_init(void); 1555extern int security_init(void);
1566extern int security_module_enable(struct security_operations *ops); 1556extern int security_module_enable(struct security_operations *ops);
1567extern int register_security(struct security_operations *ops); 1557extern int register_security(struct security_operations *ops);
1568extern int mod_reg_security(const char *name, struct security_operations *ops);
1569extern struct dentry *securityfs_create_file(const char *name, mode_t mode, 1558extern struct dentry *securityfs_create_file(const char *name, mode_t mode,
1570 struct dentry *parent, void *data, 1559 struct dentry *parent, void *data,
1571 const struct file_operations *fops); 1560 const struct file_operations *fops);
@@ -1573,7 +1562,8 @@ extern struct dentry *securityfs_create_dir(const char *name, struct dentry *par
1573extern void securityfs_remove(struct dentry *dentry); 1562extern void securityfs_remove(struct dentry *dentry);
1574 1563
1575/* Security operations */ 1564/* Security operations */
1576int security_ptrace(struct task_struct *parent, struct task_struct *child); 1565int security_ptrace(struct task_struct *parent, struct task_struct *child,
1566 unsigned int mode);
1577int security_capget(struct task_struct *target, 1567int security_capget(struct task_struct *target,
1578 kernel_cap_t *effective, 1568 kernel_cap_t *effective,
1579 kernel_cap_t *inheritable, 1569 kernel_cap_t *inheritable,
@@ -1606,6 +1596,7 @@ int security_sb_alloc(struct super_block *sb);
1606void security_sb_free(struct super_block *sb); 1596void security_sb_free(struct super_block *sb);
1607int security_sb_copy_data(char *orig, char *copy); 1597int security_sb_copy_data(char *orig, char *copy);
1608int security_sb_kern_mount(struct super_block *sb, void *data); 1598int security_sb_kern_mount(struct super_block *sb, void *data);
1599int security_sb_show_options(struct seq_file *m, struct super_block *sb);
1609int security_sb_statfs(struct dentry *dentry); 1600int security_sb_statfs(struct dentry *dentry);
1610int security_sb_mount(char *dev_name, struct path *path, 1601int security_sb_mount(char *dev_name, struct path *path,
1611 char *type, unsigned long flags, void *data); 1602 char *type, unsigned long flags, void *data);
@@ -1617,8 +1608,6 @@ void security_sb_post_remount(struct vfsmount *mnt, unsigned long flags, void *d
1617void security_sb_post_addmount(struct vfsmount *mnt, struct path *mountpoint); 1608void security_sb_post_addmount(struct vfsmount *mnt, struct path *mountpoint);
1618int security_sb_pivotroot(struct path *old_path, struct path *new_path); 1609int security_sb_pivotroot(struct path *old_path, struct path *new_path);
1619void security_sb_post_pivotroot(struct path *old_path, struct path *new_path); 1610void security_sb_post_pivotroot(struct path *old_path, struct path *new_path);
1620int security_sb_get_mnt_opts(const struct super_block *sb,
1621 struct security_mnt_opts *opts);
1622int security_sb_set_mnt_opts(struct super_block *sb, struct security_mnt_opts *opts); 1611int security_sb_set_mnt_opts(struct super_block *sb, struct security_mnt_opts *opts);
1623void security_sb_clone_mnt_opts(const struct super_block *oldsb, 1612void security_sb_clone_mnt_opts(const struct super_block *oldsb,
1624 struct super_block *newsb); 1613 struct super_block *newsb);
@@ -1755,9 +1744,11 @@ static inline int security_init(void)
1755 return 0; 1744 return 0;
1756} 1745}
1757 1746
1758static inline int security_ptrace(struct task_struct *parent, struct task_struct *child) 1747static inline int security_ptrace(struct task_struct *parent,
1748 struct task_struct *child,
1749 unsigned int mode)
1759{ 1750{
1760 return cap_ptrace(parent, child); 1751 return cap_ptrace(parent, child, mode);
1761} 1752}
1762 1753
1763static inline int security_capget(struct task_struct *target, 1754static inline int security_capget(struct task_struct *target,
@@ -1881,6 +1872,12 @@ static inline int security_sb_kern_mount(struct super_block *sb, void *data)
1881 return 0; 1872 return 0;
1882} 1873}
1883 1874
1875static inline int security_sb_show_options(struct seq_file *m,
1876 struct super_block *sb)
1877{
1878 return 0;
1879}
1880
1884static inline int security_sb_statfs(struct dentry *dentry) 1881static inline int security_sb_statfs(struct dentry *dentry)
1885{ 1882{
1886 return 0; 1883 return 0;
@@ -1927,12 +1924,6 @@ static inline int security_sb_pivotroot(struct path *old_path,
1927static inline void security_sb_post_pivotroot(struct path *old_path, 1924static inline void security_sb_post_pivotroot(struct path *old_path,
1928 struct path *new_path) 1925 struct path *new_path)
1929{ } 1926{ }
1930static inline int security_sb_get_mnt_opts(const struct super_block *sb,
1931 struct security_mnt_opts *opts)
1932{
1933 security_init_mnt_opts(opts);
1934 return 0;
1935}
1936 1927
1937static inline int security_sb_set_mnt_opts(struct super_block *sb, 1928static inline int security_sb_set_mnt_opts(struct super_block *sb,
1938 struct security_mnt_opts *opts) 1929 struct security_mnt_opts *opts)
diff --git a/include/linux/smp.h b/include/linux/smp.h
index 55232ccf9cfd..48262f86c969 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -7,9 +7,18 @@
7 */ 7 */
8 8
9#include <linux/errno.h> 9#include <linux/errno.h>
10#include <linux/list.h>
11#include <linux/cpumask.h>
10 12
11extern void cpu_idle(void); 13extern void cpu_idle(void);
12 14
15struct call_single_data {
16 struct list_head list;
17 void (*func) (void *info);
18 void *info;
19 unsigned int flags;
20};
21
13#ifdef CONFIG_SMP 22#ifdef CONFIG_SMP
14 23
15#include <linux/preempt.h> 24#include <linux/preempt.h>
@@ -52,15 +61,34 @@ extern void smp_cpus_done(unsigned int max_cpus);
52/* 61/*
53 * Call a function on all other processors 62 * Call a function on all other processors
54 */ 63 */
55int smp_call_function(void(*func)(void *info), void *info, int retry, int wait); 64int smp_call_function(void(*func)(void *info), void *info, int wait);
56 65int smp_call_function_mask(cpumask_t mask, void(*func)(void *info), void *info,
66 int wait);
57int smp_call_function_single(int cpuid, void (*func) (void *info), void *info, 67int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
58 int retry, int wait); 68 int wait);
69void __smp_call_function_single(int cpuid, struct call_single_data *data);
70
71/*
72 * Generic and arch helpers
73 */
74#ifdef CONFIG_USE_GENERIC_SMP_HELPERS
75void generic_smp_call_function_single_interrupt(void);
76void generic_smp_call_function_interrupt(void);
77void init_call_single_data(void);
78void ipi_call_lock(void);
79void ipi_call_unlock(void);
80void ipi_call_lock_irq(void);
81void ipi_call_unlock_irq(void);
82#else
83static inline void init_call_single_data(void)
84{
85}
86#endif
59 87
60/* 88/*
61 * Call a function on all processors 89 * Call a function on all processors
62 */ 90 */
63int on_each_cpu(void (*func) (void *info), void *info, int retry, int wait); 91int on_each_cpu(void (*func) (void *info), void *info, int wait);
64 92
65#define MSG_ALL_BUT_SELF 0x8000 /* Assume <32768 CPU's */ 93#define MSG_ALL_BUT_SELF 0x8000 /* Assume <32768 CPU's */
66#define MSG_ALL 0x8001 94#define MSG_ALL 0x8001
@@ -90,9 +118,9 @@ static inline int up_smp_call_function(void (*func)(void *), void *info)
90{ 118{
91 return 0; 119 return 0;
92} 120}
93#define smp_call_function(func, info, retry, wait) \ 121#define smp_call_function(func, info, wait) \
94 (up_smp_call_function(func, info)) 122 (up_smp_call_function(func, info))
95#define on_each_cpu(func,info,retry,wait) \ 123#define on_each_cpu(func,info,wait) \
96 ({ \ 124 ({ \
97 local_irq_disable(); \ 125 local_irq_disable(); \
98 func(info); \ 126 func(info); \
@@ -102,7 +130,7 @@ static inline int up_smp_call_function(void (*func)(void *), void *info)
102static inline void smp_send_reschedule(int cpu) { } 130static inline void smp_send_reschedule(int cpu) { }
103#define num_booting_cpus() 1 131#define num_booting_cpus() 1
104#define smp_prepare_boot_cpu() do {} while (0) 132#define smp_prepare_boot_cpu() do {} while (0)
105#define smp_call_function_single(cpuid, func, info, retry, wait) \ 133#define smp_call_function_single(cpuid, func, info, wait) \
106({ \ 134({ \
107 WARN_ON(cpuid != 0); \ 135 WARN_ON(cpuid != 0); \
108 local_irq_disable(); \ 136 local_irq_disable(); \
@@ -112,7 +140,9 @@ static inline void smp_send_reschedule(int cpu) { }
112}) 140})
113#define smp_call_function_mask(mask, func, info, wait) \ 141#define smp_call_function_mask(mask, func, info, wait) \
114 (up_smp_call_function(func, info)) 142 (up_smp_call_function(func, info))
115 143static inline void init_call_single_data(void)
144{
145}
116#endif /* !SMP */ 146#endif /* !SMP */
117 147
118/* 148/*
diff --git a/include/linux/smp_lock.h b/include/linux/smp_lock.h
index aab3a4cff4e1..813be59bf345 100644
--- a/include/linux/smp_lock.h
+++ b/include/linux/smp_lock.h
@@ -27,11 +27,24 @@ static inline int reacquire_kernel_lock(struct task_struct *task)
27extern void __lockfunc lock_kernel(void) __acquires(kernel_lock); 27extern void __lockfunc lock_kernel(void) __acquires(kernel_lock);
28extern void __lockfunc unlock_kernel(void) __releases(kernel_lock); 28extern void __lockfunc unlock_kernel(void) __releases(kernel_lock);
29 29
30/*
31 * Various legacy drivers don't really need the BKL in a specific
32 * function, but they *do* need to know that the BKL became available.
33 * This function just avoids wrapping a bunch of lock/unlock pairs
34 * around code which doesn't really need it.
35 */
36static inline void cycle_kernel_lock(void)
37{
38 lock_kernel();
39 unlock_kernel();
40}
41
30#else 42#else
31 43
32#define lock_kernel() do { } while(0) 44#define lock_kernel() do { } while(0)
33#define unlock_kernel() do { } while(0) 45#define unlock_kernel() do { } while(0)
34#define release_kernel_lock(task) do { } while(0) 46#define release_kernel_lock(task) do { } while(0)
47#define cycle_kernel_lock() do { } while(0)
35#define reacquire_kernel_lock(task) 0 48#define reacquire_kernel_lock(task) 0
36#define kernel_locked() 1 49#define kernel_locked() 1
37 50
diff --git a/include/linux/topology.h b/include/linux/topology.h
index 24f3d2282e11..2158fc0d5a56 100644
--- a/include/linux/topology.h
+++ b/include/linux/topology.h
@@ -179,4 +179,17 @@ void arch_update_cpu_topology(void);
179#endif 179#endif
180#endif /* CONFIG_NUMA */ 180#endif /* CONFIG_NUMA */
181 181
182#ifndef topology_physical_package_id
183#define topology_physical_package_id(cpu) ((void)(cpu), -1)
184#endif
185#ifndef topology_core_id
186#define topology_core_id(cpu) ((void)(cpu), 0)
187#endif
188#ifndef topology_thread_siblings
189#define topology_thread_siblings(cpu) cpumask_of_cpu(cpu)
190#endif
191#ifndef topology_core_siblings
192#define topology_core_siblings(cpu) cpumask_of_cpu(cpu)
193#endif
194
182#endif /* _LINUX_TOPOLOGY_H */ 195#endif /* _LINUX_TOPOLOGY_H */
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index f462439cc288..12b15c561a1f 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -63,6 +63,7 @@ struct writeback_control {
63 unsigned for_writepages:1; /* This is a writepages() call */ 63 unsigned for_writepages:1; /* This is a writepages() call */
64 unsigned range_cyclic:1; /* range_start is cyclic */ 64 unsigned range_cyclic:1; /* range_start is cyclic */
65 unsigned more_io:1; /* more io to be dispatched */ 65 unsigned more_io:1; /* more io to be dispatched */
66 unsigned range_cont:1;
66}; 67};
67 68
68/* 69/*
@@ -105,6 +106,8 @@ extern int vm_highmem_is_dirtyable;
105extern int block_dump; 106extern int block_dump;
106extern int laptop_mode; 107extern int laptop_mode;
107 108
109extern unsigned long determine_dirtyable_memory(void);
110
108extern int dirty_ratio_handler(struct ctl_table *table, int write, 111extern int dirty_ratio_handler(struct ctl_table *table, int write,
109 struct file *filp, void __user *buffer, size_t *lenp, 112 struct file *filp, void __user *buffer, size_t *lenp,
110 loff_t *ppos); 113 loff_t *ppos);
diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h
index 2ca6bae88721..fb0c215a3051 100644
--- a/include/linux/xfrm.h
+++ b/include/linux/xfrm.h
@@ -339,6 +339,7 @@ struct xfrm_usersa_info {
339#define XFRM_STATE_NOPMTUDISC 4 339#define XFRM_STATE_NOPMTUDISC 4
340#define XFRM_STATE_WILDRECV 8 340#define XFRM_STATE_WILDRECV 8
341#define XFRM_STATE_ICMP 16 341#define XFRM_STATE_ICMP 16
342#define XFRM_STATE_AF_UNSPEC 32
342}; 343};
343 344
344struct xfrm_usersa_id { 345struct xfrm_usersa_id {
diff --git a/include/pcmcia/bulkmem.h b/include/pcmcia/bulkmem.h
deleted file mode 100644
index 6bc7472293b2..000000000000
--- a/include/pcmcia/bulkmem.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/*
2 * bulkmem.h -- Definitions for bulk memory services
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * The initial developer of the original code is David A. Hinds
9 * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
10 * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
11 *
12 * (C) 1999 David A. Hinds
13 */
14
15#ifndef _LINUX_BULKMEM_H
16#define _LINUX_BULKMEM_H
17
18/* For GetFirstRegion and GetNextRegion */
19typedef struct region_info_t {
20 u_int Attributes;
21 u_int CardOffset;
22 u_int RegionSize;
23 u_int AccessSpeed;
24 u_int BlockSize;
25 u_int PartMultiple;
26 u_char JedecMfr, JedecInfo;
27 memory_handle_t next;
28} region_info_t;
29
30#define REGION_TYPE 0x0001
31#define REGION_TYPE_CM 0x0000
32#define REGION_TYPE_AM 0x0001
33#define REGION_PREFETCH 0x0008
34#define REGION_CACHEABLE 0x0010
35#define REGION_BAR_MASK 0xe000
36#define REGION_BAR_SHIFT 13
37
38int pcmcia_get_first_region(struct pcmcia_device *handle, region_info_t *rgn);
39int pcmcia_get_next_region(struct pcmcia_device *handle, region_info_t *rgn);
40
41#endif /* _LINUX_BULKMEM_H */
diff --git a/include/pcmcia/cistpl.h b/include/pcmcia/cistpl.h
index d3bbb19caf81..e2e10c1e9a06 100644
--- a/include/pcmcia/cistpl.h
+++ b/include/pcmcia/cistpl.h
@@ -595,7 +595,7 @@ int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function, tuple
595int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple); 595int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple);
596int pccard_parse_tuple(tuple_t *tuple, cisparse_t *parse); 596int pccard_parse_tuple(tuple_t *tuple, cisparse_t *parse);
597 597
598int pccard_validate_cis(struct pcmcia_socket *s, unsigned int function, cisinfo_t *info); 598int pccard_validate_cis(struct pcmcia_socket *s, unsigned int function, unsigned int *count);
599 599
600/* ... but use these wrappers instead */ 600/* ... but use these wrappers instead */
601#define pcmcia_get_first_tuple(p_dev, tuple) \ 601#define pcmcia_get_first_tuple(p_dev, tuple) \
diff --git a/include/pcmcia/cs.h b/include/pcmcia/cs.h
index 87a260e3699e..45d84b275789 100644
--- a/include/pcmcia/cs.h
+++ b/include/pcmcia/cs.h
@@ -373,9 +373,6 @@ struct pcmcia_socket;
373 373
374int pcmcia_access_configuration_register(struct pcmcia_device *p_dev, conf_reg_t *reg); 374int pcmcia_access_configuration_register(struct pcmcia_device *p_dev, conf_reg_t *reg);
375int pcmcia_get_configuration_info(struct pcmcia_device *p_dev, config_info_t *config); 375int pcmcia_get_configuration_info(struct pcmcia_device *p_dev, config_info_t *config);
376int pcmcia_get_first_window(window_handle_t *win, win_req_t *req);
377int pcmcia_get_next_window(window_handle_t *win, win_req_t *req);
378int pcmcia_get_status(struct pcmcia_device *p_dev, cs_status_t *status);
379int pcmcia_get_mem_page(window_handle_t win, memreq_t *req); 376int pcmcia_get_mem_page(window_handle_t win, memreq_t *req);
380int pcmcia_map_mem_page(window_handle_t win, memreq_t *req); 377int pcmcia_map_mem_page(window_handle_t win, memreq_t *req);
381int pcmcia_modify_configuration(struct pcmcia_device *p_dev, modconf_t *mod); 378int pcmcia_modify_configuration(struct pcmcia_device *p_dev, modconf_t *mod);
diff --git a/include/pcmcia/cs_types.h b/include/pcmcia/cs_types.h
index 9a6bcc4952f0..f402a0f435b4 100644
--- a/include/pcmcia/cs_types.h
+++ b/include/pcmcia/cs_types.h
@@ -21,7 +21,8 @@
21#include <sys/types.h> 21#include <sys/types.h>
22#endif 22#endif
23 23
24#if defined(__arm__) || defined(__mips__) || defined(__avr32__) 24#if defined(__arm__) || defined(__mips__) || defined(__avr32__) || \
25 defined(__bfin__)
25/* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */ 26/* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */
26typedef u_int ioaddr_t; 27typedef u_int ioaddr_t;
27#else 28#else
@@ -33,9 +34,6 @@ typedef u_int event_t;
33typedef u_char cisdata_t; 34typedef u_char cisdata_t;
34typedef u_short page_t; 35typedef u_short page_t;
35 36
36struct pcmcia_device;
37typedef struct pcmcia_device *client_handle_t;
38
39struct window_t; 37struct window_t;
40typedef struct window_t *window_handle_t; 38typedef struct window_t *window_handle_t;
41 39
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index f047a1fd64f8..b316027c853d 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -20,7 +20,6 @@
20#include <linux/mod_devicetable.h> 20#include <linux/mod_devicetable.h>
21#endif 21#endif
22 22
23#include <pcmcia/bulkmem.h>
24#include <pcmcia/cs_types.h> 23#include <pcmcia/cs_types.h>
25#include <pcmcia/device_id.h> 24#include <pcmcia/device_id.h>
26 25
@@ -51,6 +50,24 @@ typedef struct mtd_info_t {
51 u_int CardOffset; 50 u_int CardOffset;
52} mtd_info_t; 51} mtd_info_t;
53 52
53typedef struct region_info_t {
54 u_int Attributes;
55 u_int CardOffset;
56 u_int RegionSize;
57 u_int AccessSpeed;
58 u_int BlockSize;
59 u_int PartMultiple;
60 u_char JedecMfr, JedecInfo;
61 memory_handle_t next;
62} region_info_t;
63#define REGION_TYPE 0x0001
64#define REGION_TYPE_CM 0x0000
65#define REGION_TYPE_AM 0x0001
66#define REGION_PREFETCH 0x0008
67#define REGION_CACHEABLE 0x0010
68#define REGION_BAR_MASK 0xe000
69#define REGION_BAR_SHIFT 13
70
54typedef union ds_ioctl_arg_t { 71typedef union ds_ioctl_arg_t {
55 adjust_t adjust; 72 adjust_t adjust;
56 config_info_t config; 73 config_info_t config;
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index f95dca077c1c..ed919dd9bb5c 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -21,7 +21,6 @@
21 21
22#include <pcmcia/cs_types.h> 22#include <pcmcia/cs_types.h>
23#include <pcmcia/cs.h> 23#include <pcmcia/cs.h>
24#include <pcmcia/bulkmem.h>
25#ifdef CONFIG_CARDBUS 24#ifdef CONFIG_CARDBUS
26#include <linux/pci.h> 25#include <linux/pci.h>
27#endif 26#endif
@@ -136,8 +135,14 @@ struct pccard_resource_ops {
136 struct resource* (*find_mem) (unsigned long base, unsigned long num, 135 struct resource* (*find_mem) (unsigned long base, unsigned long num,
137 unsigned long align, int low, 136 unsigned long align, int low,
138 struct pcmcia_socket *s); 137 struct pcmcia_socket *s);
139 int (*adjust_resource) (struct pcmcia_socket *s, 138 int (*add_io) (struct pcmcia_socket *s,
140 adjust_t *adj); 139 unsigned int action,
140 unsigned long r_start,
141 unsigned long r_end);
142 int (*add_mem) (struct pcmcia_socket *s,
143 unsigned int action,
144 unsigned long r_start,
145 unsigned long r_end);
141 int (*init) (struct pcmcia_socket *s); 146 int (*init) (struct pcmcia_socket *s);
142 void (*exit) (struct pcmcia_socket *s); 147 void (*exit) (struct pcmcia_socket *s);
143}; 148};
@@ -245,7 +250,6 @@ struct pcmcia_socket {
245 250
246 struct task_struct *thread; 251 struct task_struct *thread;
247 struct completion thread_done; 252 struct completion thread_done;
248 wait_queue_head_t thread_wait;
249 spinlock_t thread_lock; /* protects thread_events */ 253 spinlock_t thread_lock; /* protects thread_events */
250 unsigned int thread_events; 254 unsigned int thread_events;
251 255
diff --git a/include/pcmcia/version.h b/include/pcmcia/version.h
deleted file mode 100644
index 5ad9c5e198b6..000000000000
--- a/include/pcmcia/version.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/* version.h 1.94 2000/10/03 17:55:48 (David Hinds) */
2
3/* This file will be removed, please don't include it */
diff --git a/include/rdma/ib_addr.h b/include/rdma/ib_addr.h
index c36750ff6ae8..483057b2f4b4 100644
--- a/include/rdma/ib_addr.h
+++ b/include/rdma/ib_addr.h
@@ -2,29 +2,33 @@
2 * Copyright (c) 2005 Voltaire Inc. All rights reserved. 2 * Copyright (c) 2005 Voltaire Inc. All rights reserved.
3 * Copyright (c) 2005 Intel Corporation. All rights reserved. 3 * Copyright (c) 2005 Intel Corporation. All rights reserved.
4 * 4 *
5 * This Software is licensed under one of the following licenses: 5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
6 * 10 *
7 * 1) under the terms of the "Common Public License 1.0" a copy of which is 11 * Redistribution and use in source and binary forms, with or
8 * available from the Open Source Initiative, see 12 * without modification, are permitted provided that the following
9 * http://www.opensource.org/licenses/cpl.php. 13 * conditions are met:
10 * 14 *
11 * 2) under the terms of the "The BSD License" a copy of which is 15 * - Redistributions of source code must retain the above
12 * available from the Open Source Initiative, see 16 * copyright notice, this list of conditions and the following
13 * http://www.opensource.org/licenses/bsd-license.php. 17 * disclaimer.
14 * 18 *
15 * 3) under the terms of the "GNU General Public License (GPL) Version 2" a 19 * - Redistributions in binary form must reproduce the above
16 * copy of which is available from the Open Source Initiative, see 20 * copyright notice, this list of conditions and the following
17 * http://www.opensource.org/licenses/gpl-license.php. 21 * disclaimer in the documentation and/or other materials
18 * 22 * provided with the distribution.
19 * Licensee has the right to choose one of the above licenses.
20 *
21 * Redistributions of source code must retain the above copyright
22 * notice and one of the license notices.
23 *
24 * Redistributions in binary form must reproduce both the above copyright
25 * notice, one of the license notices in the documentation
26 * and/or other materials provided with the distribution.
27 * 23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
28 */ 32 */
29 33
30#if !defined(IB_ADDR_H) 34#if !defined(IB_ADDR_H)
@@ -57,6 +61,7 @@ struct rdma_dev_addr {
57 unsigned char dst_dev_addr[MAX_ADDR_LEN]; 61 unsigned char dst_dev_addr[MAX_ADDR_LEN];
58 unsigned char broadcast[MAX_ADDR_LEN]; 62 unsigned char broadcast[MAX_ADDR_LEN];
59 enum rdma_node_type dev_type; 63 enum rdma_node_type dev_type;
64 struct net_device *src_dev;
60}; 65};
61 66
62/** 67/**
diff --git a/include/rdma/ib_cache.h b/include/rdma/ib_cache.h
index f179d233ffc3..00a2b8ec327f 100644
--- a/include/rdma/ib_cache.h
+++ b/include/rdma/ib_cache.h
@@ -30,8 +30,6 @@
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE. 32 * SOFTWARE.
33 *
34 * $Id: ib_cache.h 1349 2004-12-16 21:09:43Z roland $
35 */ 33 */
36 34
37#ifndef _IB_CACHE_H 35#ifndef _IB_CACHE_H
diff --git a/include/rdma/ib_cm.h b/include/rdma/ib_cm.h
index a627c8682d2f..ec7c6d99ed3f 100644
--- a/include/rdma/ib_cm.h
+++ b/include/rdma/ib_cm.h
@@ -31,8 +31,6 @@
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE. 33 * SOFTWARE.
34 *
35 * $Id: ib_cm.h 4311 2005-12-05 18:42:01Z sean.hefty $
36 */ 34 */
37#if !defined(IB_CM_H) 35#if !defined(IB_CM_H)
38#define IB_CM_H 36#define IB_CM_H
diff --git a/include/rdma/ib_fmr_pool.h b/include/rdma/ib_fmr_pool.h
index 00dadbf94e1d..f62b842e6596 100644
--- a/include/rdma/ib_fmr_pool.h
+++ b/include/rdma/ib_fmr_pool.h
@@ -29,8 +29,6 @@
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE. 31 * SOFTWARE.
32 *
33 * $Id: ib_fmr_pool.h 2730 2005-06-28 16:43:03Z sean.hefty $
34 */ 32 */
35 33
36#if !defined(IB_FMR_POOL_H) 34#if !defined(IB_FMR_POOL_H)
@@ -61,7 +59,7 @@ struct ib_fmr_pool_param {
61 int pool_size; 59 int pool_size;
62 int dirty_watermark; 60 int dirty_watermark;
63 void (*flush_function)(struct ib_fmr_pool *pool, 61 void (*flush_function)(struct ib_fmr_pool *pool,
64 void * arg); 62 void *arg);
65 void *flush_arg; 63 void *flush_arg;
66 unsigned cache:1; 64 unsigned cache:1;
67}; 65};
diff --git a/include/rdma/ib_mad.h b/include/rdma/ib_mad.h
index 7228c056b9e9..5f6c40fffcf4 100644
--- a/include/rdma/ib_mad.h
+++ b/include/rdma/ib_mad.h
@@ -32,11 +32,9 @@
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE. 34 * SOFTWARE.
35 *
36 * $Id: ib_mad.h 5596 2006-03-03 01:00:07Z sean.hefty $
37 */ 35 */
38 36
39#if !defined( IB_MAD_H ) 37#if !defined(IB_MAD_H)
40#define IB_MAD_H 38#define IB_MAD_H
41 39
42#include <linux/list.h> 40#include <linux/list.h>
@@ -194,8 +192,7 @@ struct ib_vendor_mad {
194 u8 data[IB_MGMT_VENDOR_DATA]; 192 u8 data[IB_MGMT_VENDOR_DATA];
195}; 193};
196 194
197struct ib_class_port_info 195struct ib_class_port_info {
198{
199 u8 base_version; 196 u8 base_version;
200 u8 class_version; 197 u8 class_version;
201 __be16 capability_mask; 198 __be16 capability_mask;
@@ -614,11 +611,11 @@ int ib_process_mad_wc(struct ib_mad_agent *mad_agent,
614 * any class specific header, and MAD data area. 611 * any class specific header, and MAD data area.
615 * If @rmpp_active is set, the RMPP header will be initialized for sending. 612 * If @rmpp_active is set, the RMPP header will be initialized for sending.
616 */ 613 */
617struct ib_mad_send_buf * ib_create_send_mad(struct ib_mad_agent *mad_agent, 614struct ib_mad_send_buf *ib_create_send_mad(struct ib_mad_agent *mad_agent,
618 u32 remote_qpn, u16 pkey_index, 615 u32 remote_qpn, u16 pkey_index,
619 int rmpp_active, 616 int rmpp_active,
620 int hdr_len, int data_len, 617 int hdr_len, int data_len,
621 gfp_t gfp_mask); 618 gfp_t gfp_mask);
622 619
623/** 620/**
624 * ib_is_mad_class_rmpp - returns whether given management class 621 * ib_is_mad_class_rmpp - returns whether given management class
diff --git a/include/rdma/ib_pack.h b/include/rdma/ib_pack.h
index f926020d6331..d7fc45c4eba9 100644
--- a/include/rdma/ib_pack.h
+++ b/include/rdma/ib_pack.h
@@ -28,8 +28,6 @@
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE. 30 * SOFTWARE.
31 *
32 * $Id: ib_pack.h 1349 2004-12-16 21:09:43Z roland $
33 */ 31 */
34 32
35#ifndef IB_PACK_H 33#ifndef IB_PACK_H
diff --git a/include/rdma/ib_sa.h b/include/rdma/ib_sa.h
index 942692b0b92e..3841c1aff692 100644
--- a/include/rdma/ib_sa.h
+++ b/include/rdma/ib_sa.h
@@ -30,8 +30,6 @@
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE. 32 * SOFTWARE.
33 *
34 * $Id: ib_sa.h 2811 2005-07-06 18:11:43Z halr $
35 */ 33 */
36 34
37#ifndef IB_SA_H 35#ifndef IB_SA_H
diff --git a/include/rdma/ib_smi.h b/include/rdma/ib_smi.h
index f29af135ba83..aaca0878668f 100644
--- a/include/rdma/ib_smi.h
+++ b/include/rdma/ib_smi.h
@@ -32,11 +32,9 @@
32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 32 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 33 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * SOFTWARE. 34 * SOFTWARE.
35 *
36 * $Id: ib_smi.h 1389 2004-12-27 22:56:47Z roland $
37 */ 35 */
38 36
39#if !defined( IB_SMI_H ) 37#if !defined(IB_SMI_H)
40#define IB_SMI_H 38#define IB_SMI_H
41 39
42#include <rdma/ib_mad.h> 40#include <rdma/ib_mad.h>
diff --git a/include/rdma/ib_user_cm.h b/include/rdma/ib_user_cm.h
index 37650afb982c..bd3d380781e0 100644
--- a/include/rdma/ib_user_cm.h
+++ b/include/rdma/ib_user_cm.h
@@ -29,8 +29,6 @@
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE. 31 * SOFTWARE.
32 *
33 * $Id: ib_user_cm.h 4019 2005-11-11 00:33:09Z sean.hefty $
34 */ 32 */
35 33
36#ifndef IB_USER_CM_H 34#ifndef IB_USER_CM_H
diff --git a/include/rdma/ib_user_mad.h b/include/rdma/ib_user_mad.h
index 29d2c7205a90..d6fce1cbdb90 100644
--- a/include/rdma/ib_user_mad.h
+++ b/include/rdma/ib_user_mad.h
@@ -29,8 +29,6 @@
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE. 31 * SOFTWARE.
32 *
33 * $Id: ib_user_mad.h 2814 2005-07-06 19:14:09Z halr $
34 */ 32 */
35 33
36#ifndef IB_USER_MAD_H 34#ifndef IB_USER_MAD_H
diff --git a/include/rdma/ib_user_verbs.h b/include/rdma/ib_user_verbs.h
index 8d65bf0a625b..a17f77106149 100644
--- a/include/rdma/ib_user_verbs.h
+++ b/include/rdma/ib_user_verbs.h
@@ -31,8 +31,6 @@
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE. 33 * SOFTWARE.
34 *
35 * $Id: ib_user_verbs.h 4019 2005-11-11 00:33:09Z sean.hefty $
36 */ 34 */
37 35
38#ifndef IB_USER_VERBS_H 36#ifndef IB_USER_VERBS_H
@@ -291,7 +289,10 @@ struct ib_uverbs_wc {
291 __u32 opcode; 289 __u32 opcode;
292 __u32 vendor_err; 290 __u32 vendor_err;
293 __u32 byte_len; 291 __u32 byte_len;
294 __u32 imm_data; 292 union {
293 __u32 imm_data;
294 __u32 invalidate_rkey;
295 } ex;
295 __u32 qp_num; 296 __u32 qp_num;
296 __u32 src_qp; 297 __u32 src_qp;
297 __u32 wc_flags; 298 __u32 wc_flags;
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index 31d30b1852e8..90b529f7a154 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -34,8 +34,6 @@
34 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 34 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
35 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 35 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 * SOFTWARE. 36 * SOFTWARE.
37 *
38 * $Id: ib_verbs.h 1349 2004-12-16 21:09:43Z roland $
39 */ 37 */
40 38
41#if !defined(IB_VERBS_H) 39#if !defined(IB_VERBS_H)
@@ -93,7 +91,7 @@ enum ib_device_cap_flags {
93 IB_DEVICE_RC_RNR_NAK_GEN = (1<<12), 91 IB_DEVICE_RC_RNR_NAK_GEN = (1<<12),
94 IB_DEVICE_SRQ_RESIZE = (1<<13), 92 IB_DEVICE_SRQ_RESIZE = (1<<13),
95 IB_DEVICE_N_NOTIFY_CQ = (1<<14), 93 IB_DEVICE_N_NOTIFY_CQ = (1<<14),
96 IB_DEVICE_ZERO_STAG = (1<<15), 94 IB_DEVICE_LOCAL_DMA_LKEY = (1<<15),
97 IB_DEVICE_RESERVED = (1<<16), /* old SEND_W_INV */ 95 IB_DEVICE_RESERVED = (1<<16), /* old SEND_W_INV */
98 IB_DEVICE_MEM_WINDOW = (1<<17), 96 IB_DEVICE_MEM_WINDOW = (1<<17),
99 /* 97 /*
@@ -105,6 +103,8 @@ enum ib_device_cap_flags {
105 */ 103 */
106 IB_DEVICE_UD_IP_CSUM = (1<<18), 104 IB_DEVICE_UD_IP_CSUM = (1<<18),
107 IB_DEVICE_UD_TSO = (1<<19), 105 IB_DEVICE_UD_TSO = (1<<19),
106 IB_DEVICE_MEM_MGT_EXTENSIONS = (1<<21),
107 IB_DEVICE_BLOCK_MULTICAST_LOOPBACK = (1<<22),
108}; 108};
109 109
110enum ib_atomic_cap { 110enum ib_atomic_cap {
@@ -150,6 +150,7 @@ struct ib_device_attr {
150 int max_srq; 150 int max_srq;
151 int max_srq_wr; 151 int max_srq_wr;
152 int max_srq_sge; 152 int max_srq_sge;
153 unsigned int max_fast_reg_page_list_len;
153 u16 max_pkeys; 154 u16 max_pkeys;
154 u8 local_ca_ack_delay; 155 u8 local_ca_ack_delay;
155}; 156};
@@ -226,6 +227,57 @@ static inline int ib_width_enum_to_int(enum ib_port_width width)
226 } 227 }
227} 228}
228 229
230struct ib_protocol_stats {
231 /* TBD... */
232};
233
234struct iw_protocol_stats {
235 u64 ipInReceives;
236 u64 ipInHdrErrors;
237 u64 ipInTooBigErrors;
238 u64 ipInNoRoutes;
239 u64 ipInAddrErrors;
240 u64 ipInUnknownProtos;
241 u64 ipInTruncatedPkts;
242 u64 ipInDiscards;
243 u64 ipInDelivers;
244 u64 ipOutForwDatagrams;
245 u64 ipOutRequests;
246 u64 ipOutDiscards;
247 u64 ipOutNoRoutes;
248 u64 ipReasmTimeout;
249 u64 ipReasmReqds;
250 u64 ipReasmOKs;
251 u64 ipReasmFails;
252 u64 ipFragOKs;
253 u64 ipFragFails;
254 u64 ipFragCreates;
255 u64 ipInMcastPkts;
256 u64 ipOutMcastPkts;
257 u64 ipInBcastPkts;
258 u64 ipOutBcastPkts;
259
260 u64 tcpRtoAlgorithm;
261 u64 tcpRtoMin;
262 u64 tcpRtoMax;
263 u64 tcpMaxConn;
264 u64 tcpActiveOpens;
265 u64 tcpPassiveOpens;
266 u64 tcpAttemptFails;
267 u64 tcpEstabResets;
268 u64 tcpCurrEstab;
269 u64 tcpInSegs;
270 u64 tcpOutSegs;
271 u64 tcpRetransSegs;
272 u64 tcpInErrs;
273 u64 tcpOutRsts;
274};
275
276union rdma_protocol_stats {
277 struct ib_protocol_stats ib;
278 struct iw_protocol_stats iw;
279};
280
229struct ib_port_attr { 281struct ib_port_attr {
230 enum ib_port_state state; 282 enum ib_port_state state;
231 enum ib_mtu max_mtu; 283 enum ib_mtu max_mtu;
@@ -413,6 +465,8 @@ enum ib_wc_opcode {
413 IB_WC_FETCH_ADD, 465 IB_WC_FETCH_ADD,
414 IB_WC_BIND_MW, 466 IB_WC_BIND_MW,
415 IB_WC_LSO, 467 IB_WC_LSO,
468 IB_WC_LOCAL_INV,
469 IB_WC_FAST_REG_MR,
416/* 470/*
417 * Set value of IB_WC_RECV so consumers can test if a completion is a 471 * Set value of IB_WC_RECV so consumers can test if a completion is a
418 * receive by testing (opcode & IB_WC_RECV). 472 * receive by testing (opcode & IB_WC_RECV).
@@ -423,7 +477,8 @@ enum ib_wc_opcode {
423 477
424enum ib_wc_flags { 478enum ib_wc_flags {
425 IB_WC_GRH = 1, 479 IB_WC_GRH = 1,
426 IB_WC_WITH_IMM = (1<<1) 480 IB_WC_WITH_IMM = (1<<1),
481 IB_WC_WITH_INVALIDATE = (1<<2),
427}; 482};
428 483
429struct ib_wc { 484struct ib_wc {
@@ -433,7 +488,10 @@ struct ib_wc {
433 u32 vendor_err; 488 u32 vendor_err;
434 u32 byte_len; 489 u32 byte_len;
435 struct ib_qp *qp; 490 struct ib_qp *qp;
436 __be32 imm_data; 491 union {
492 __be32 imm_data;
493 u32 invalidate_rkey;
494 } ex;
437 u32 src_qp; 495 u32 src_qp;
438 int wc_flags; 496 int wc_flags;
439 u16 pkey_index; 497 u16 pkey_index;
@@ -498,7 +556,8 @@ enum ib_qp_type {
498}; 556};
499 557
500enum ib_qp_create_flags { 558enum ib_qp_create_flags {
501 IB_QP_CREATE_IPOIB_UD_LSO = 1 << 0, 559 IB_QP_CREATE_IPOIB_UD_LSO = 1 << 0,
560 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK = 1 << 1,
502}; 561};
503 562
504struct ib_qp_init_attr { 563struct ib_qp_init_attr {
@@ -627,6 +686,9 @@ enum ib_wr_opcode {
627 IB_WR_ATOMIC_FETCH_AND_ADD, 686 IB_WR_ATOMIC_FETCH_AND_ADD,
628 IB_WR_LSO, 687 IB_WR_LSO,
629 IB_WR_SEND_WITH_INV, 688 IB_WR_SEND_WITH_INV,
689 IB_WR_RDMA_READ_WITH_INV,
690 IB_WR_LOCAL_INV,
691 IB_WR_FAST_REG_MR,
630}; 692};
631 693
632enum ib_send_flags { 694enum ib_send_flags {
@@ -643,6 +705,12 @@ struct ib_sge {
643 u32 lkey; 705 u32 lkey;
644}; 706};
645 707
708struct ib_fast_reg_page_list {
709 struct ib_device *device;
710 u64 *page_list;
711 unsigned int max_page_list_len;
712};
713
646struct ib_send_wr { 714struct ib_send_wr {
647 struct ib_send_wr *next; 715 struct ib_send_wr *next;
648 u64 wr_id; 716 u64 wr_id;
@@ -675,6 +743,15 @@ struct ib_send_wr {
675 u16 pkey_index; /* valid for GSI only */ 743 u16 pkey_index; /* valid for GSI only */
676 u8 port_num; /* valid for DR SMPs on switch only */ 744 u8 port_num; /* valid for DR SMPs on switch only */
677 } ud; 745 } ud;
746 struct {
747 u64 iova_start;
748 struct ib_fast_reg_page_list *page_list;
749 unsigned int page_shift;
750 unsigned int page_list_len;
751 u32 length;
752 int access_flags;
753 u32 rkey;
754 } fast_reg;
678 } wr; 755 } wr;
679}; 756};
680 757
@@ -777,7 +854,7 @@ struct ib_cq {
777 struct ib_uobject *uobject; 854 struct ib_uobject *uobject;
778 ib_comp_handler comp_handler; 855 ib_comp_handler comp_handler;
779 void (*event_handler)(struct ib_event *, void *); 856 void (*event_handler)(struct ib_event *, void *);
780 void * cq_context; 857 void *cq_context;
781 int cqe; 858 int cqe;
782 atomic_t usecnt; /* count number of work queues */ 859 atomic_t usecnt; /* count number of work queues */
783}; 860};
@@ -883,7 +960,7 @@ struct ib_dma_mapping_ops {
883 void (*sync_single_for_cpu)(struct ib_device *dev, 960 void (*sync_single_for_cpu)(struct ib_device *dev,
884 u64 dma_handle, 961 u64 dma_handle,
885 size_t size, 962 size_t size,
886 enum dma_data_direction dir); 963 enum dma_data_direction dir);
887 void (*sync_single_for_device)(struct ib_device *dev, 964 void (*sync_single_for_device)(struct ib_device *dev,
888 u64 dma_handle, 965 u64 dma_handle,
889 size_t size, 966 size_t size,
@@ -919,6 +996,8 @@ struct ib_device {
919 996
920 struct iw_cm_verbs *iwcm; 997 struct iw_cm_verbs *iwcm;
921 998
999 int (*get_protocol_stats)(struct ib_device *device,
1000 union rdma_protocol_stats *stats);
922 int (*query_device)(struct ib_device *device, 1001 int (*query_device)(struct ib_device *device,
923 struct ib_device_attr *device_attr); 1002 struct ib_device_attr *device_attr);
924 int (*query_port)(struct ib_device *device, 1003 int (*query_port)(struct ib_device *device,
@@ -1013,6 +1092,11 @@ struct ib_device {
1013 int (*query_mr)(struct ib_mr *mr, 1092 int (*query_mr)(struct ib_mr *mr,
1014 struct ib_mr_attr *mr_attr); 1093 struct ib_mr_attr *mr_attr);
1015 int (*dereg_mr)(struct ib_mr *mr); 1094 int (*dereg_mr)(struct ib_mr *mr);
1095 struct ib_mr * (*alloc_fast_reg_mr)(struct ib_pd *pd,
1096 int max_page_list_len);
1097 struct ib_fast_reg_page_list * (*alloc_fast_reg_page_list)(struct ib_device *device,
1098 int page_list_len);
1099 void (*free_fast_reg_page_list)(struct ib_fast_reg_page_list *page_list);
1016 int (*rereg_phys_mr)(struct ib_mr *mr, 1100 int (*rereg_phys_mr)(struct ib_mr *mr,
1017 int mr_rereg_mask, 1101 int mr_rereg_mask,
1018 struct ib_pd *pd, 1102 struct ib_pd *pd,
@@ -1065,6 +1149,7 @@ struct ib_device {
1065 1149
1066 char node_desc[64]; 1150 char node_desc[64];
1067 __be64 node_guid; 1151 __be64 node_guid;
1152 u32 local_dma_lkey;
1068 u8 node_type; 1153 u8 node_type;
1069 u8 phys_port_cnt; 1154 u8 phys_port_cnt;
1070}; 1155};
@@ -1807,6 +1892,54 @@ int ib_query_mr(struct ib_mr *mr, struct ib_mr_attr *mr_attr);
1807int ib_dereg_mr(struct ib_mr *mr); 1892int ib_dereg_mr(struct ib_mr *mr);
1808 1893
1809/** 1894/**
1895 * ib_alloc_fast_reg_mr - Allocates memory region usable with the
1896 * IB_WR_FAST_REG_MR send work request.
1897 * @pd: The protection domain associated with the region.
1898 * @max_page_list_len: requested max physical buffer list length to be
1899 * used with fast register work requests for this MR.
1900 */
1901struct ib_mr *ib_alloc_fast_reg_mr(struct ib_pd *pd, int max_page_list_len);
1902
1903/**
1904 * ib_alloc_fast_reg_page_list - Allocates a page list array
1905 * @device - ib device pointer.
1906 * @page_list_len - size of the page list array to be allocated.
1907 *
1908 * This allocates and returns a struct ib_fast_reg_page_list * and a
1909 * page_list array that is at least page_list_len in size. The actual
1910 * size is returned in max_page_list_len. The caller is responsible
1911 * for initializing the contents of the page_list array before posting
1912 * a send work request with the IB_WC_FAST_REG_MR opcode.
1913 *
1914 * The page_list array entries must be translated using one of the
1915 * ib_dma_*() functions just like the addresses passed to
1916 * ib_map_phys_fmr(). Once the ib_post_send() is issued, the struct
1917 * ib_fast_reg_page_list must not be modified by the caller until the
1918 * IB_WC_FAST_REG_MR work request completes.
1919 */
1920struct ib_fast_reg_page_list *ib_alloc_fast_reg_page_list(
1921 struct ib_device *device, int page_list_len);
1922
1923/**
1924 * ib_free_fast_reg_page_list - Deallocates a previously allocated
1925 * page list array.
1926 * @page_list - struct ib_fast_reg_page_list pointer to be deallocated.
1927 */
1928void ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list);
1929
1930/**
1931 * ib_update_fast_reg_key - updates the key portion of the fast_reg MR
1932 * R_Key and L_Key.
1933 * @mr - struct ib_mr pointer to be updated.
1934 * @newkey - new key to be used.
1935 */
1936static inline void ib_update_fast_reg_key(struct ib_mr *mr, u8 newkey)
1937{
1938 mr->lkey = (mr->lkey & 0xffffff00) | newkey;
1939 mr->rkey = (mr->rkey & 0xffffff00) | newkey;
1940}
1941
1942/**
1810 * ib_alloc_mw - Allocates a memory window. 1943 * ib_alloc_mw - Allocates a memory window.
1811 * @pd: The protection domain associated with the memory window. 1944 * @pd: The protection domain associated with the memory window.
1812 */ 1945 */
diff --git a/include/rdma/iw_cm.h b/include/rdma/iw_cm.h
index aeefa9b740dc..cbb822e8d791 100644
--- a/include/rdma/iw_cm.h
+++ b/include/rdma/iw_cm.h
@@ -62,7 +62,7 @@ struct iw_cm_event {
62 struct sockaddr_in remote_addr; 62 struct sockaddr_in remote_addr;
63 void *private_data; 63 void *private_data;
64 u8 private_data_len; 64 u8 private_data_len;
65 void* provider_data; 65 void *provider_data;
66}; 66};
67 67
68/** 68/**
diff --git a/include/rdma/rdma_cm.h b/include/rdma/rdma_cm.h
index 010f876f41d8..22bb2e7bab1a 100644
--- a/include/rdma/rdma_cm.h
+++ b/include/rdma/rdma_cm.h
@@ -2,29 +2,33 @@
2 * Copyright (c) 2005 Voltaire Inc. All rights reserved. 2 * Copyright (c) 2005 Voltaire Inc. All rights reserved.
3 * Copyright (c) 2005 Intel Corporation. All rights reserved. 3 * Copyright (c) 2005 Intel Corporation. All rights reserved.
4 * 4 *
5 * This Software is licensed under one of the following licenses: 5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
6 * 10 *
7 * 1) under the terms of the "Common Public License 1.0" a copy of which is 11 * Redistribution and use in source and binary forms, with or
8 * available from the Open Source Initiative, see 12 * without modification, are permitted provided that the following
9 * http://www.opensource.org/licenses/cpl.php. 13 * conditions are met:
10 * 14 *
11 * 2) under the terms of the "The BSD License" a copy of which is 15 * - Redistributions of source code must retain the above
12 * available from the Open Source Initiative, see 16 * copyright notice, this list of conditions and the following
13 * http://www.opensource.org/licenses/bsd-license.php. 17 * disclaimer.
14 * 18 *
15 * 3) under the terms of the "GNU General Public License (GPL) Version 2" a 19 * - Redistributions in binary form must reproduce the above
16 * copy of which is available from the Open Source Initiative, see 20 * copyright notice, this list of conditions and the following
17 * http://www.opensource.org/licenses/gpl-license.php. 21 * disclaimer in the documentation and/or other materials
18 * 22 * provided with the distribution.
19 * Licensee has the right to choose one of the above licenses.
20 *
21 * Redistributions of source code must retain the above copyright
22 * notice and one of the license notices.
23 *
24 * Redistributions in binary form must reproduce both the above copyright
25 * notice, one of the license notices in the documentation
26 * and/or other materials provided with the distribution.
27 * 23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
28 */ 32 */
29 33
30#if !defined(RDMA_CM_H) 34#if !defined(RDMA_CM_H)
@@ -57,11 +61,11 @@ enum rdma_cm_event_type {
57}; 61};
58 62
59enum rdma_port_space { 63enum rdma_port_space {
60 RDMA_PS_SDP = 0x0001, 64 RDMA_PS_SDP = 0x0001,
61 RDMA_PS_IPOIB= 0x0002, 65 RDMA_PS_IPOIB = 0x0002,
62 RDMA_PS_TCP = 0x0106, 66 RDMA_PS_TCP = 0x0106,
63 RDMA_PS_UDP = 0x0111, 67 RDMA_PS_UDP = 0x0111,
64 RDMA_PS_SCTP = 0x0183 68 RDMA_PS_SCTP = 0x0183
65}; 69};
66 70
67struct rdma_addr { 71struct rdma_addr {
diff --git a/include/rdma/rdma_cm_ib.h b/include/rdma/rdma_cm_ib.h
index 950424b38f16..2389c3b45404 100644
--- a/include/rdma/rdma_cm_ib.h
+++ b/include/rdma/rdma_cm_ib.h
@@ -1,29 +1,33 @@
1/* 1/*
2 * Copyright (c) 2006 Intel Corporation. All rights reserved. 2 * Copyright (c) 2006 Intel Corporation. All rights reserved.
3 * 3 *
4 * This Software is licensed under one of the following licenses: 4 * This software is available to you under a choice of one of two
5 * 5 * licenses. You may choose to be licensed under the terms of the GNU
6 * 1) under the terms of the "Common Public License 1.0" a copy of which is 6 * General Public License (GPL) Version 2, available from the file
7 * available from the Open Source Initiative, see 7 * COPYING in the main directory of this source tree, or the
8 * http://www.opensource.org/licenses/cpl.php. 8 * OpenIB.org BSD license below:
9 * 9 *
10 * 2) under the terms of the "The BSD License" a copy of which is 10 * Redistribution and use in source and binary forms, with or
11 * available from the Open Source Initiative, see 11 * without modification, are permitted provided that the following
12 * http://www.opensource.org/licenses/bsd-license.php. 12 * conditions are met:
13 * 13 *
14 * 3) under the terms of the "GNU General Public License (GPL) Version 2" a 14 * - Redistributions of source code must retain the above
15 * copy of which is available from the Open Source Initiative, see 15 * copyright notice, this list of conditions and the following
16 * http://www.opensource.org/licenses/gpl-license.php. 16 * disclaimer.
17 * 17 *
18 * Licensee has the right to choose one of the above licenses. 18 * - Redistributions in binary form must reproduce the above
19 * 19 * copyright notice, this list of conditions and the following
20 * Redistributions of source code must retain the above copyright 20 * disclaimer in the documentation and/or other materials
21 * notice and one of the license notices. 21 * provided with the distribution.
22 * 22 *
23 * Redistributions in binary form must reproduce both the above copyright 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * notice, one of the license notices in the documentation 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * and/or other materials provided with the distribution. 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
27 */ 31 */
28 32
29#if !defined(RDMA_CM_IB_H) 33#if !defined(RDMA_CM_IB_H)
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index f6a9fe0ef09c..00b78763a1bf 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -134,6 +134,7 @@ struct scsi_device {
134 unsigned no_start_on_add:1; /* do not issue start on add */ 134 unsigned no_start_on_add:1; /* do not issue start on add */
135 unsigned allow_restart:1; /* issue START_UNIT in error handler */ 135 unsigned allow_restart:1; /* issue START_UNIT in error handler */
136 unsigned manage_start_stop:1; /* Let HLD (sd) manage start/stop */ 136 unsigned manage_start_stop:1; /* Let HLD (sd) manage start/stop */
137 unsigned start_stop_pwr_cond:1; /* Set power cond. in START_STOP_UNIT */
137 unsigned no_uld_attach:1; /* disable connecting to upper level drivers */ 138 unsigned no_uld_attach:1; /* disable connecting to upper level drivers */
138 unsigned select_no_atn:1; 139 unsigned select_no_atn:1;
139 unsigned fix_capacity:1; /* READ_CAPACITY is too high by 1 */ 140 unsigned fix_capacity:1; /* READ_CAPACITY is too high by 1 */
diff --git a/include/sound/ad1843.h b/include/sound/ad1843.h
new file mode 100644
index 000000000000..b236a9d1d6e4
--- /dev/null
+++ b/include/sound/ad1843.h
@@ -0,0 +1,46 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org>
7 * Copyright 2008 Thomas Bogendoerfer <tsbogend@franken.de>
8 */
9
10#ifndef __SOUND_AD1843_H
11#define __SOUND_AD1843_H
12
13struct snd_ad1843 {
14 void *chip;
15 int (*read)(void *chip, int reg);
16 int (*write)(void *chip, int reg, int val);
17};
18
19#define AD1843_GAIN_RECLEV 0
20#define AD1843_GAIN_LINE 1
21#define AD1843_GAIN_LINE_2 2
22#define AD1843_GAIN_MIC 3
23#define AD1843_GAIN_PCM_0 4
24#define AD1843_GAIN_PCM_1 5
25#define AD1843_GAIN_SIZE (AD1843_GAIN_PCM_1+1)
26
27int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id);
28int ad1843_get_gain(struct snd_ad1843 *ad1843, int id);
29int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval);
30int ad1843_get_recsrc(struct snd_ad1843 *ad1843);
31int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc);
32void ad1843_setup_dac(struct snd_ad1843 *ad1843,
33 unsigned int id,
34 unsigned int framerate,
35 snd_pcm_format_t fmt,
36 unsigned int channels);
37void ad1843_shutdown_dac(struct snd_ad1843 *ad1843,
38 unsigned int id);
39void ad1843_setup_adc(struct snd_ad1843 *ad1843,
40 unsigned int framerate,
41 snd_pcm_format_t fmt,
42 unsigned int channels);
43void ad1843_shutdown_adc(struct snd_ad1843 *ad1843);
44int ad1843_init(struct snd_ad1843 *ad1843);
45
46#endif /* __SOUND_AD1843_H */
diff --git a/include/sound/control.h b/include/sound/control.h
index 3dc1291f52db..4721b4bba053 100644
--- a/include/sound/control.h
+++ b/include/sound/control.h
@@ -129,9 +129,6 @@ int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn);
129#define snd_ctl_unregister_ioctl_compat(fcn) 129#define snd_ctl_unregister_ioctl_compat(fcn)
130#endif 130#endif
131 131
132int snd_ctl_elem_read(struct snd_card *card, struct snd_ctl_elem_value *control);
133int snd_ctl_elem_write(struct snd_card *card, struct snd_ctl_file *file, struct snd_ctl_elem_value *control);
134
135static inline unsigned int snd_ctl_get_ioffnum(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) 132static inline unsigned int snd_ctl_get_ioffnum(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id)
136{ 133{
137 return id->numid - kctl->id.numid; 134 return id->numid - kctl->id.numid;
diff --git a/include/sound/core.h b/include/sound/core.h
index 695ee53488a3..558b96284bd2 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -412,13 +412,13 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
412 412
413#endif /* CONFIG_SND_DEBUG */ 413#endif /* CONFIG_SND_DEBUG */
414 414
415#ifdef CONFIG_SND_DEBUG_DETECT 415#ifdef CONFIG_SND_DEBUG_VERBOSE
416/** 416/**
417 * snd_printdd - debug printk 417 * snd_printdd - debug printk
418 * @format: format string 418 * @format: format string
419 * 419 *
420 * Works like snd_printk() for debugging purposes. 420 * Works like snd_printk() for debugging purposes.
421 * Ignored when CONFIG_SND_DEBUG_DETECT is not set. 421 * Ignored when CONFIG_SND_DEBUG_VERBOSE is not set.
422 */ 422 */
423#define snd_printdd(format, args...) snd_printk(format, ##args) 423#define snd_printdd(format, args...) snd_printk(format, ##args)
424#else 424#else
@@ -442,7 +442,7 @@ struct snd_pci_quirk {
442 unsigned short subvendor; /* PCI subvendor ID */ 442 unsigned short subvendor; /* PCI subvendor ID */
443 unsigned short subdevice; /* PCI subdevice ID */ 443 unsigned short subdevice; /* PCI subdevice ID */
444 int value; /* value */ 444 int value; /* value */
445#ifdef CONFIG_SND_DEBUG_DETECT 445#ifdef CONFIG_SND_DEBUG_VERBOSE
446 const char *name; /* name of the device (optional) */ 446 const char *name; /* name of the device (optional) */
447#endif 447#endif
448}; 448};
@@ -450,7 +450,7 @@ struct snd_pci_quirk {
450#define _SND_PCI_QUIRK_ID(vend,dev) \ 450#define _SND_PCI_QUIRK_ID(vend,dev) \
451 .subvendor = (vend), .subdevice = (dev) 451 .subvendor = (vend), .subdevice = (dev)
452#define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)} 452#define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)}
453#ifdef CONFIG_SND_DEBUG_DETECT 453#ifdef CONFIG_SND_DEBUG_VERBOSE
454#define SND_PCI_QUIRK(vend,dev,xname,val) \ 454#define SND_PCI_QUIRK(vend,dev,xname,val) \
455 {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)} 455 {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)}
456#else 456#else
diff --git a/include/sound/cs4231-regs.h b/include/sound/cs4231-regs.h
index e8d1f3e31f9e..92647532c454 100644
--- a/include/sound/cs4231-regs.h
+++ b/include/sound/cs4231-regs.h
@@ -177,4 +177,12 @@
177#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ 177#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */
178#define CS4236_VERSION 0x9c /* chip version and ID */ 178#define CS4236_VERSION 0x9c /* chip version and ID */
179 179
180/* definitions for extended registers - OPTI93X */
181#define OPTi931_AUX_LEFT_INPUT 0x10
182#define OPTi931_AUX_RIGHT_INPUT 0x11
183#define OPTi93X_MIC_LEFT_INPUT 0x14
184#define OPTi93X_MIC_RIGHT_INPUT 0x15
185#define OPTi93X_OUT_LEFT 0x16
186#define OPTi93X_OUT_RIGHT 0x17
187
180#endif /* __SOUND_CS4231_REGS_H */ 188#endif /* __SOUND_CS4231_REGS_H */
diff --git a/include/sound/cs4231.h b/include/sound/cs4231.h
index 66055d702aa3..f0785f9f4ae4 100644
--- a/include/sound/cs4231.h
+++ b/include/sound/cs4231.h
@@ -58,6 +58,7 @@
58/* compatible, but clones */ 58/* compatible, but clones */
59#define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */ 59#define CS4231_HW_INTERWAVE 0x1000 /* InterWave chip */
60#define CS4231_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */ 60#define CS4231_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */
61#define CS4231_HW_OPTI93X 0x1102 /* Opti 930/931/933 */
61 62
62/* defines for codec.hwshare */ 63/* defines for codec.hwshare */
63#define CS4231_HWSHARE_IRQ (1<<0) 64#define CS4231_HWSHARE_IRQ (1<<0)
@@ -120,6 +121,8 @@ unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg);
120void snd_cs4231_mce_up(struct snd_cs4231 *chip); 121void snd_cs4231_mce_up(struct snd_cs4231 *chip);
121void snd_cs4231_mce_down(struct snd_cs4231 *chip); 122void snd_cs4231_mce_down(struct snd_cs4231 *chip);
122 123
124void snd_cs4231_overrange(struct snd_cs4231 *chip);
125
123irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id); 126irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id);
124 127
125const char *snd_cs4231_chip_id(struct snd_cs4231 *chip); 128const char *snd_cs4231_chip_id(struct snd_cs4231 *chip);
diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h
index 7b7b9b13b4dd..10ee28eac018 100644
--- a/include/sound/emu10k1.h
+++ b/include/sound/emu10k1.h
@@ -1670,6 +1670,7 @@ struct snd_emu_chip_details {
1670 unsigned char spi_dac; /* SPI interface for DAC */ 1670 unsigned char spi_dac; /* SPI interface for DAC */
1671 unsigned char i2c_adc; /* I2C interface for ADC */ 1671 unsigned char i2c_adc; /* I2C interface for ADC */
1672 unsigned char adc_1361t; /* Use Philips 1361T ADC */ 1672 unsigned char adc_1361t; /* Use Philips 1361T ADC */
1673 unsigned char invert_shared_spdif; /* analog/digital switch inverted */
1673 const char *driver; 1674 const char *driver;
1674 const char *name; 1675 const char *name;
1675 const char *id; /* for backward compatibility - can be NULL if not needed */ 1676 const char *id; /* for backward compatibility - can be NULL if not needed */
diff --git a/include/sound/seq_kernel.h b/include/sound/seq_kernel.h
index f023c1b97f8c..3d9afb6a8c9c 100644
--- a/include/sound/seq_kernel.h
+++ b/include/sound/seq_kernel.h
@@ -105,7 +105,7 @@ int snd_seq_event_port_attach(int client, struct snd_seq_port_callback *pcbp,
105 int cap, int type, int midi_channels, int midi_voices, char *portname); 105 int cap, int type, int midi_channels, int midi_voices, char *portname);
106int snd_seq_event_port_detach(int client, int port); 106int snd_seq_event_port_detach(int client, int port);
107 107
108#ifdef CONFIG_KMOD 108#ifdef CONFIG_MODULES
109void snd_seq_autoload_lock(void); 109void snd_seq_autoload_lock(void);
110void snd_seq_autoload_unlock(void); 110void snd_seq_autoload_unlock(void);
111#else 111#else
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index a105b01e06d5..3030fdc6981d 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -130,6 +130,13 @@
130{ .id = snd_soc_dapm_adc, .name = wname, .sname = stname, .reg = wreg, \ 130{ .id = snd_soc_dapm_adc, .name = wname, .sname = stname, .reg = wreg, \
131 .shift = wshift, .invert = winvert} 131 .shift = wshift, .invert = winvert}
132 132
133/* generic register modifier widget */
134#define SND_SOC_DAPM_REG(wid, wname, wreg, wshift, wmask, won_val, woff_val) \
135{ .id = wid, .name = wname, .kcontrols = NULL, .num_kcontrols = 0, \
136 .reg = -((wreg) + 1), .shift = wshift, .mask = wmask, \
137 .on_val = won_val, .off_val = woff_val, .event = dapm_reg_event, \
138 .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD}
139
133/* dapm kcontrol types */ 140/* dapm kcontrol types */
134#define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \ 141#define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \
135{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 142{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
@@ -193,6 +200,7 @@ struct snd_soc_dapm_widget;
193enum snd_soc_dapm_type; 200enum snd_soc_dapm_type;
194struct snd_soc_dapm_path; 201struct snd_soc_dapm_path;
195struct snd_soc_dapm_pin; 202struct snd_soc_dapm_pin;
203struct snd_soc_dapm_route;
196 204
197/* dapm controls */ 205/* dapm controls */
198int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, 206int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol,
@@ -205,25 +213,32 @@ int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol,
205 struct snd_ctl_elem_value *ucontrol); 213 struct snd_ctl_elem_value *ucontrol);
206int snd_soc_dapm_new_control(struct snd_soc_codec *codec, 214int snd_soc_dapm_new_control(struct snd_soc_codec *codec,
207 const struct snd_soc_dapm_widget *widget); 215 const struct snd_soc_dapm_widget *widget);
216int snd_soc_dapm_new_controls(struct snd_soc_codec *codec,
217 const struct snd_soc_dapm_widget *widget,
218 int num);
208 219
209/* dapm path setup */ 220/* dapm path setup */
210int snd_soc_dapm_connect_input(struct snd_soc_codec *codec, 221int __deprecated snd_soc_dapm_connect_input(struct snd_soc_codec *codec,
211 const char *sink_name, const char *control_name, const char *src_name); 222 const char *sink_name, const char *control_name, const char *src_name);
212int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec); 223int snd_soc_dapm_new_widgets(struct snd_soc_codec *codec);
213void snd_soc_dapm_free(struct snd_soc_device *socdev); 224void snd_soc_dapm_free(struct snd_soc_device *socdev);
225int snd_soc_dapm_add_routes(struct snd_soc_codec *codec,
226 const struct snd_soc_dapm_route *route, int num);
214 227
215/* dapm events */ 228/* dapm events */
216int snd_soc_dapm_stream_event(struct snd_soc_codec *codec, char *stream, 229int snd_soc_dapm_stream_event(struct snd_soc_codec *codec, char *stream,
217 int event); 230 int event);
218int snd_soc_dapm_device_event(struct snd_soc_device *socdev, int event); 231int snd_soc_dapm_set_bias_level(struct snd_soc_device *socdev,
232 enum snd_soc_bias_level level);
219 233
220/* dapm sys fs - used by the core */ 234/* dapm sys fs - used by the core */
221int snd_soc_dapm_sys_add(struct device *dev); 235int snd_soc_dapm_sys_add(struct device *dev);
222 236
223/* dapm audio endpoint control */ 237/* dapm audio pin control and status */
224int snd_soc_dapm_set_endpoint(struct snd_soc_codec *codec, 238int snd_soc_dapm_enable_pin(struct snd_soc_codec *codec, char *pin);
225 char *pin, int status); 239int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, char *pin);
226int snd_soc_dapm_sync_endpoints(struct snd_soc_codec *codec); 240int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin);
241int snd_soc_dapm_sync(struct snd_soc_codec *codec);
227 242
228/* dapm widget types */ 243/* dapm widget types */
229enum snd_soc_dapm_type { 244enum snd_soc_dapm_type {
@@ -245,6 +260,18 @@ enum snd_soc_dapm_type {
245 snd_soc_dapm_post, /* machine specific post widget - exec last */ 260 snd_soc_dapm_post, /* machine specific post widget - exec last */
246}; 261};
247 262
263/*
264 * DAPM audio route definition.
265 *
266 * Defines an audio route originating at source via control and finishing
267 * at sink.
268 */
269struct snd_soc_dapm_route {
270 const char *sink;
271 const char *control;
272 const char *source;
273};
274
248/* dapm audio path between two widgets */ 275/* dapm audio path between two widgets */
249struct snd_soc_dapm_path { 276struct snd_soc_dapm_path {
250 char *name; 277 char *name;
@@ -277,6 +304,9 @@ struct snd_soc_dapm_widget {
277 unsigned char shift; /* bits to shift */ 304 unsigned char shift; /* bits to shift */
278 unsigned int saved_value; /* widget saved value */ 305 unsigned int saved_value; /* widget saved value */
279 unsigned int value; /* widget current value */ 306 unsigned int value; /* widget current value */
307 unsigned int mask; /* non-shifted mask */
308 unsigned int on_val; /* on state value */
309 unsigned int off_val; /* off state value */
280 unsigned char power:1; /* block power status */ 310 unsigned char power:1; /* block power status */
281 unsigned char invert:1; /* invert the power bit */ 311 unsigned char invert:1; /* invert the power bit */
282 unsigned char active:1; /* active stream on DAC, ADC's */ 312 unsigned char active:1; /* active stream on DAC, ADC's */
diff --git a/include/sound/soc.h b/include/sound/soc.h
index d3c8c033dff8..1890d87c5204 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -73,6 +73,15 @@
73 .get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \ 73 .get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \
74 .private_value = (reg_left) | ((shift) << 8) | \ 74 .private_value = (reg_left) | ((shift) << 8) | \
75 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) } 75 ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
76#define SOC_DOUBLE_S8_TLV(xname, reg, min, max, tlv_array) \
77{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
78 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
79 SNDRV_CTL_ELEM_ACCESS_READWRITE, \
80 .tlv.p = (tlv_array), \
81 .info = snd_soc_info_volsw_s8, .get = snd_soc_get_volsw_s8, \
82 .put = snd_soc_put_volsw_s8, \
83 .private_value = (reg) | (((signed char)max) << 16) | \
84 (((signed char)min) << 24) }
76#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xtexts) \ 85#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xtexts) \
77{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ 86{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \
78 .mask = xmask, .texts = xtexts } 87 .mask = xmask, .texts = xtexts }
@@ -91,6 +100,15 @@
91 .info = snd_soc_info_volsw, \ 100 .info = snd_soc_info_volsw, \
92 .get = xhandler_get, .put = xhandler_put, \ 101 .get = xhandler_get, .put = xhandler_put, \
93 .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) } 102 .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) }
103#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmask, xinvert,\
104 xhandler_get, xhandler_put, tlv_array) \
105{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
106 .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
107 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
108 .tlv.p = (tlv_array), \
109 .info = snd_soc_info_volsw, \
110 .get = xhandler_get, .put = xhandler_put, \
111 .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) }
94#define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \ 112#define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \
95{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 113{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
96 .info = snd_soc_info_bool_ext, \ 114 .info = snd_soc_info_bool_ext, \
@@ -103,6 +121,24 @@
103 .private_value = (unsigned long)&xenum } 121 .private_value = (unsigned long)&xenum }
104 122
105/* 123/*
124 * Bias levels
125 *
126 * @ON: Bias is fully on for audio playback and capture operations.
127 * @PREPARE: Prepare for audio operations. Called before DAPM switching for
128 * stream start and stop operations.
129 * @STANDBY: Low power standby state when no playback/capture operations are
130 * in progress. NOTE: The transition time between STANDBY and ON
131 * should be as fast as possible and no longer than 10ms.
132 * @OFF: Power Off. No restrictions on transition times.
133 */
134enum snd_soc_bias_level {
135 SND_SOC_BIAS_ON,
136 SND_SOC_BIAS_PREPARE,
137 SND_SOC_BIAS_STANDBY,
138 SND_SOC_BIAS_OFF,
139};
140
141/*
106 * Digital Audio Interface (DAI) types 142 * Digital Audio Interface (DAI) types
107 */ 143 */
108#define SND_SOC_DAI_AC97 0x1 144#define SND_SOC_DAI_AC97 0x1
@@ -185,8 +221,7 @@ struct snd_soc_pcm_stream;
185struct snd_soc_ops; 221struct snd_soc_ops;
186struct snd_soc_dai_mode; 222struct snd_soc_dai_mode;
187struct snd_soc_pcm_runtime; 223struct snd_soc_pcm_runtime;
188struct snd_soc_codec_dai; 224struct snd_soc_dai;
189struct snd_soc_cpu_dai;
190struct snd_soc_codec; 225struct snd_soc_codec;
191struct snd_soc_machine_config; 226struct snd_soc_machine_config;
192struct soc_enum; 227struct soc_enum;
@@ -221,6 +256,27 @@ int snd_soc_new_ac97_codec(struct snd_soc_codec *codec,
221 struct snd_ac97_bus_ops *ops, int num); 256 struct snd_ac97_bus_ops *ops, int num);
222void snd_soc_free_ac97_codec(struct snd_soc_codec *codec); 257void snd_soc_free_ac97_codec(struct snd_soc_codec *codec);
223 258
259/* Digital Audio Interface clocking API.*/
260int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
261 unsigned int freq, int dir);
262
263int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai,
264 int div_id, int div);
265
266int snd_soc_dai_set_pll(struct snd_soc_dai *dai,
267 int pll_id, unsigned int freq_in, unsigned int freq_out);
268
269/* Digital Audio interface formatting */
270int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt);
271
272int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai,
273 unsigned int mask, int slots);
274
275int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate);
276
277/* Digital Audio Interface mute */
278int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute);
279
224/* 280/*
225 *Controls 281 *Controls
226 */ 282 */
@@ -249,6 +305,12 @@ int snd_soc_get_volsw_2r(struct snd_kcontrol *kcontrol,
249 struct snd_ctl_elem_value *ucontrol); 305 struct snd_ctl_elem_value *ucontrol);
250int snd_soc_put_volsw_2r(struct snd_kcontrol *kcontrol, 306int snd_soc_put_volsw_2r(struct snd_kcontrol *kcontrol,
251 struct snd_ctl_elem_value *ucontrol); 307 struct snd_ctl_elem_value *ucontrol);
308int snd_soc_info_volsw_s8(struct snd_kcontrol *kcontrol,
309 struct snd_ctl_elem_info *uinfo);
310int snd_soc_get_volsw_s8(struct snd_kcontrol *kcontrol,
311 struct snd_ctl_elem_value *ucontrol);
312int snd_soc_put_volsw_s8(struct snd_kcontrol *kcontrol,
313 struct snd_ctl_elem_value *ucontrol);
252 314
253/* SoC PCM stream information */ 315/* SoC PCM stream information */
254struct snd_soc_pcm_stream { 316struct snd_soc_pcm_stream {
@@ -272,87 +334,45 @@ struct snd_soc_ops {
272 int (*trigger)(struct snd_pcm_substream *, int); 334 int (*trigger)(struct snd_pcm_substream *, int);
273}; 335};
274 336
275/* ASoC codec DAI ops */ 337/* ASoC DAI ops */
276struct snd_soc_codec_ops { 338struct snd_soc_dai_ops {
277 /* codec DAI clocking configuration */ 339 /* DAI clocking configuration */
278 int (*set_sysclk)(struct snd_soc_codec_dai *codec_dai, 340 int (*set_sysclk)(struct snd_soc_dai *dai,
279 int clk_id, unsigned int freq, int dir); 341 int clk_id, unsigned int freq, int dir);
280 int (*set_pll)(struct snd_soc_codec_dai *codec_dai, 342 int (*set_pll)(struct snd_soc_dai *dai,
281 int pll_id, unsigned int freq_in, unsigned int freq_out); 343 int pll_id, unsigned int freq_in, unsigned int freq_out);
282 int (*set_clkdiv)(struct snd_soc_codec_dai *codec_dai, 344 int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div);
283 int div_id, int div);
284 345
285 /* CPU DAI format configuration */ 346 /* DAI format configuration */
286 int (*set_fmt)(struct snd_soc_codec_dai *codec_dai, 347 int (*set_fmt)(struct snd_soc_dai *dai, unsigned int fmt);
287 unsigned int fmt); 348 int (*set_tdm_slot)(struct snd_soc_dai *dai,
288 int (*set_tdm_slot)(struct snd_soc_codec_dai *codec_dai,
289 unsigned int mask, int slots); 349 unsigned int mask, int slots);
290 int (*set_tristate)(struct snd_soc_codec_dai *, int tristate); 350 int (*set_tristate)(struct snd_soc_dai *dai, int tristate);
291 351
292 /* digital mute */ 352 /* digital mute */
293 int (*digital_mute)(struct snd_soc_codec_dai *, int mute); 353 int (*digital_mute)(struct snd_soc_dai *dai, int mute);
294};
295
296/* ASoC cpu DAI ops */
297struct snd_soc_cpu_ops {
298 /* CPU DAI clocking configuration */
299 int (*set_sysclk)(struct snd_soc_cpu_dai *cpu_dai,
300 int clk_id, unsigned int freq, int dir);
301 int (*set_clkdiv)(struct snd_soc_cpu_dai *cpu_dai,
302 int div_id, int div);
303 int (*set_pll)(struct snd_soc_cpu_dai *cpu_dai,
304 int pll_id, unsigned int freq_in, unsigned int freq_out);
305
306 /* CPU DAI format configuration */
307 int (*set_fmt)(struct snd_soc_cpu_dai *cpu_dai,
308 unsigned int fmt);
309 int (*set_tdm_slot)(struct snd_soc_cpu_dai *cpu_dai,
310 unsigned int mask, int slots);
311 int (*set_tristate)(struct snd_soc_cpu_dai *, int tristate);
312};
313
314/* SoC Codec DAI */
315struct snd_soc_codec_dai {
316 char *name;
317 int id;
318 unsigned char type;
319
320 /* DAI capabilities */
321 struct snd_soc_pcm_stream playback;
322 struct snd_soc_pcm_stream capture;
323
324 /* DAI runtime info */
325 struct snd_soc_codec *codec;
326 unsigned int active;
327 unsigned char pop_wait:1;
328
329 /* ops */
330 struct snd_soc_ops ops;
331 struct snd_soc_codec_ops dai_ops;
332
333 /* DAI private data */
334 void *private_data;
335}; 354};
336 355
337/* SoC CPU DAI */ 356/* SoC DAI (Digital Audio Interface) */
338struct snd_soc_cpu_dai { 357struct snd_soc_dai {
339
340 /* DAI description */ 358 /* DAI description */
341 char *name; 359 char *name;
342 unsigned int id; 360 unsigned int id;
343 unsigned char type; 361 unsigned char type;
344 362
345 /* DAI callbacks */ 363 /* DAI callbacks */
346 int (*probe)(struct platform_device *pdev); 364 int (*probe)(struct platform_device *pdev,
347 void (*remove)(struct platform_device *pdev); 365 struct snd_soc_dai *dai);
366 void (*remove)(struct platform_device *pdev,
367 struct snd_soc_dai *dai);
348 int (*suspend)(struct platform_device *pdev, 368 int (*suspend)(struct platform_device *pdev,
349 struct snd_soc_cpu_dai *cpu_dai); 369 struct snd_soc_dai *dai);
350 int (*resume)(struct platform_device *pdev, 370 int (*resume)(struct platform_device *pdev,
351 struct snd_soc_cpu_dai *cpu_dai); 371 struct snd_soc_dai *dai);
352 372
353 /* ops */ 373 /* ops */
354 struct snd_soc_ops ops; 374 struct snd_soc_ops ops;
355 struct snd_soc_cpu_ops dai_ops; 375 struct snd_soc_dai_ops dai_ops;
356 376
357 /* DAI capabilities */ 377 /* DAI capabilities */
358 struct snd_soc_pcm_stream capture; 378 struct snd_soc_pcm_stream capture;
@@ -360,7 +380,9 @@ struct snd_soc_cpu_dai {
360 380
361 /* DAI runtime info */ 381 /* DAI runtime info */
362 struct snd_pcm_runtime *runtime; 382 struct snd_pcm_runtime *runtime;
363 unsigned char active:1; 383 struct snd_soc_codec *codec;
384 unsigned int active;
385 unsigned char pop_wait:1;
364 void *dma_data; 386 void *dma_data;
365 387
366 /* DAI private data */ 388 /* DAI private data */
@@ -374,7 +396,8 @@ struct snd_soc_codec {
374 struct mutex mutex; 396 struct mutex mutex;
375 397
376 /* callbacks */ 398 /* callbacks */
377 int (*dapm_event)(struct snd_soc_codec *codec, int event); 399 int (*set_bias_level)(struct snd_soc_codec *,
400 enum snd_soc_bias_level level);
378 401
379 /* runtime */ 402 /* runtime */
380 struct snd_card *card; 403 struct snd_card *card;
@@ -396,12 +419,12 @@ struct snd_soc_codec {
396 /* dapm */ 419 /* dapm */
397 struct list_head dapm_widgets; 420 struct list_head dapm_widgets;
398 struct list_head dapm_paths; 421 struct list_head dapm_paths;
399 unsigned int dapm_state; 422 enum snd_soc_bias_level bias_level;
400 unsigned int suspend_dapm_state; 423 enum snd_soc_bias_level suspend_bias_level;
401 struct delayed_work delayed_work; 424 struct delayed_work delayed_work;
402 425
403 /* codec DAI's */ 426 /* codec DAI's */
404 struct snd_soc_codec_dai *dai; 427 struct snd_soc_dai *dai;
405 unsigned int num_dai; 428 unsigned int num_dai;
406}; 429};
407 430
@@ -420,12 +443,12 @@ struct snd_soc_platform {
420 int (*probe)(struct platform_device *pdev); 443 int (*probe)(struct platform_device *pdev);
421 int (*remove)(struct platform_device *pdev); 444 int (*remove)(struct platform_device *pdev);
422 int (*suspend)(struct platform_device *pdev, 445 int (*suspend)(struct platform_device *pdev,
423 struct snd_soc_cpu_dai *cpu_dai); 446 struct snd_soc_dai *dai);
424 int (*resume)(struct platform_device *pdev, 447 int (*resume)(struct platform_device *pdev,
425 struct snd_soc_cpu_dai *cpu_dai); 448 struct snd_soc_dai *dai);
426 449
427 /* pcm creation and destruction */ 450 /* pcm creation and destruction */
428 int (*pcm_new)(struct snd_card *, struct snd_soc_codec_dai *, 451 int (*pcm_new)(struct snd_card *, struct snd_soc_dai *,
429 struct snd_pcm *); 452 struct snd_pcm *);
430 void (*pcm_free)(struct snd_pcm *); 453 void (*pcm_free)(struct snd_pcm *);
431 454
@@ -439,8 +462,8 @@ struct snd_soc_dai_link {
439 char *stream_name; /* Stream name */ 462 char *stream_name; /* Stream name */
440 463
441 /* DAI */ 464 /* DAI */
442 struct snd_soc_codec_dai *codec_dai; 465 struct snd_soc_dai *codec_dai;
443 struct snd_soc_cpu_dai *cpu_dai; 466 struct snd_soc_dai *cpu_dai;
444 467
445 /* machine stream operations */ 468 /* machine stream operations */
446 struct snd_soc_ops *ops; 469 struct snd_soc_ops *ops;
@@ -467,7 +490,8 @@ struct snd_soc_machine {
467 int (*resume_post)(struct platform_device *pdev); 490 int (*resume_post)(struct platform_device *pdev);
468 491
469 /* callbacks */ 492 /* callbacks */
470 int (*dapm_event)(struct snd_soc_machine *, int event); 493 int (*set_bias_level)(struct snd_soc_machine *,
494 enum snd_soc_bias_level level);
471 495
472 /* CPU <--> Codec DAI links */ 496 /* CPU <--> Codec DAI links */
473 struct snd_soc_dai_link *dai_link; 497 struct snd_soc_dai_link *dai_link;
@@ -482,6 +506,7 @@ struct snd_soc_device {
482 struct snd_soc_codec *codec; 506 struct snd_soc_codec *codec;
483 struct snd_soc_codec_device *codec_dev; 507 struct snd_soc_codec_device *codec_dev;
484 struct delayed_work delayed_work; 508 struct delayed_work delayed_work;
509 struct work_struct deferred_resume_work;
485 void *codec_data; 510 void *codec_data;
486}; 511};
487 512
diff --git a/include/sound/uda1341.h b/include/sound/uda1341.h
index 2e564bfb37fe..110d5dc3a2be 100644
--- a/include/sound/uda1341.h
+++ b/include/sound/uda1341.h
@@ -15,8 +15,6 @@
15 * features support 15 * features support
16 */ 16 */
17 17
18/* $Id: uda1341.h,v 1.8 2005/11/17 14:17:21 tiwai Exp $ */
19
20#define UDA1341_ALSA_NAME "snd-uda1341" 18#define UDA1341_ALSA_NAME "snd-uda1341"
21 19
22/* 20/*
diff --git a/include/sound/version.h b/include/sound/version.h
index ed6fb2eb1eac..6b78aff273a8 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
1/* include/version.h. Generated by alsa/ksync script. */ 1/* include/version.h */
2#define CONFIG_SND_VERSION "1.0.16" 2#define CONFIG_SND_VERSION "1.0.17"
3#define CONFIG_SND_DATE "" 3#define CONFIG_SND_DATE ""
diff --git a/include/xen/events.h b/include/xen/events.h
index acd8e062c85f..67c4436554a9 100644
--- a/include/xen/events.h
+++ b/include/xen/events.h
@@ -32,6 +32,7 @@ void unbind_from_irqhandler(unsigned int irq, void *dev_id);
32 32
33void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector); 33void xen_send_IPI_one(unsigned int cpu, enum ipi_vector vector);
34int resend_irq_on_evtchn(unsigned int irq); 34int resend_irq_on_evtchn(unsigned int irq);
35void rebind_evtchn_irq(int evtchn, int irq);
35 36
36static inline void notify_remote_via_evtchn(int port) 37static inline void notify_remote_via_evtchn(int port)
37{ 38{
@@ -40,4 +41,7 @@ static inline void notify_remote_via_evtchn(int port)
40} 41}
41 42
42extern void notify_remote_via_irq(int irq); 43extern void notify_remote_via_irq(int irq);
44
45extern void xen_irq_resume(void);
46
43#endif /* _XEN_EVENTS_H */ 47#endif /* _XEN_EVENTS_H */
diff --git a/include/xen/grant_table.h b/include/xen/grant_table.h
index 466204846121..a40f1cd91be1 100644
--- a/include/xen/grant_table.h
+++ b/include/xen/grant_table.h
@@ -51,6 +51,9 @@ struct gnttab_free_callback {
51 u16 count; 51 u16 count;
52}; 52};
53 53
54int gnttab_suspend(void);
55int gnttab_resume(void);
56
54int gnttab_grant_foreign_access(domid_t domid, unsigned long frame, 57int gnttab_grant_foreign_access(domid_t domid, unsigned long frame,
55 int readonly); 58 int readonly);
56 59
diff --git a/include/xen/hvc-console.h b/include/xen/hvc-console.h
index 21c0ecfd786d..98b79bc404dd 100644
--- a/include/xen/hvc-console.h
+++ b/include/xen/hvc-console.h
@@ -3,4 +3,13 @@
3 3
4extern struct console xenboot_console; 4extern struct console xenboot_console;
5 5
6#ifdef CONFIG_HVC_XEN
7void xen_console_resume(void);
8#else
9static inline void xen_console_resume(void) { }
10#endif
11
12void xen_raw_console_write(const char *str);
13void xen_raw_printk(const char *fmt, ...);
14
6#endif /* XEN_HVC_CONSOLE_H */ 15#endif /* XEN_HVC_CONSOLE_H */
diff --git a/include/xen/interface/elfnote.h b/include/xen/interface/elfnote.h
index a64d3df5bd95..7a8262c375cc 100644
--- a/include/xen/interface/elfnote.h
+++ b/include/xen/interface/elfnote.h
@@ -120,6 +120,26 @@
120 */ 120 */
121#define XEN_ELFNOTE_BSD_SYMTAB 11 121#define XEN_ELFNOTE_BSD_SYMTAB 11
122 122
123/*
124 * The lowest address the hypervisor hole can begin at (numeric).
125 *
126 * This must not be set higher than HYPERVISOR_VIRT_START. Its presence
127 * also indicates to the hypervisor that the kernel can deal with the
128 * hole starting at a higher address.
129 */
130#define XEN_ELFNOTE_HV_START_LOW 12
131
132/*
133 * List of maddr_t-sized mask/value pairs describing how to recognize
134 * (non-present) L1 page table entries carrying valid MFNs (numeric).
135 */
136#define XEN_ELFNOTE_L1_MFN_VALID 13
137
138/*
139 * Whether or not the guest supports cooperative suspend cancellation.
140 */
141#define XEN_ELFNOTE_SUSPEND_CANCEL 14
142
123#endif /* __XEN_PUBLIC_ELFNOTE_H__ */ 143#endif /* __XEN_PUBLIC_ELFNOTE_H__ */
124 144
125/* 145/*
diff --git a/include/xen/interface/features.h b/include/xen/interface/features.h
index d73228d16488..f51b6413b054 100644
--- a/include/xen/interface/features.h
+++ b/include/xen/interface/features.h
@@ -38,6 +38,9 @@
38 */ 38 */
39#define XENFEAT_pae_pgdir_above_4gb 4 39#define XENFEAT_pae_pgdir_above_4gb 4
40 40
41/* x86: Does this Xen host support the MMU_PT_UPDATE_PRESERVE_AD hypercall? */
42#define XENFEAT_mmu_pt_update_preserve_ad 5
43
41#define XENFEAT_NR_SUBMAPS 1 44#define XENFEAT_NR_SUBMAPS 1
42 45
43#endif /* __XEN_PUBLIC_FEATURES_H__ */ 46#endif /* __XEN_PUBLIC_FEATURES_H__ */
diff --git a/include/xen/interface/io/fbif.h b/include/xen/interface/io/fbif.h
index 5a934dd7796d..974a51ed9165 100644
--- a/include/xen/interface/io/fbif.h
+++ b/include/xen/interface/io/fbif.h
@@ -49,11 +49,27 @@ struct xenfb_update {
49 int32_t height; /* rect height */ 49 int32_t height; /* rect height */
50}; 50};
51 51
52/*
53 * Framebuffer resize notification event
54 * Capable backend sets feature-resize in xenstore.
55 */
56#define XENFB_TYPE_RESIZE 3
57
58struct xenfb_resize {
59 uint8_t type; /* XENFB_TYPE_RESIZE */
60 int32_t width; /* width in pixels */
61 int32_t height; /* height in pixels */
62 int32_t stride; /* stride in bytes */
63 int32_t depth; /* depth in bits */
64 int32_t offset; /* start offset within framebuffer */
65};
66
52#define XENFB_OUT_EVENT_SIZE 40 67#define XENFB_OUT_EVENT_SIZE 40
53 68
54union xenfb_out_event { 69union xenfb_out_event {
55 uint8_t type; 70 uint8_t type;
56 struct xenfb_update update; 71 struct xenfb_update update;
72 struct xenfb_resize resize;
57 char pad[XENFB_OUT_EVENT_SIZE]; 73 char pad[XENFB_OUT_EVENT_SIZE];
58}; 74};
59 75
@@ -105,15 +121,18 @@ struct xenfb_page {
105 * Each directory page holds PAGE_SIZE / sizeof(*pd) 121 * Each directory page holds PAGE_SIZE / sizeof(*pd)
106 * framebuffer pages, and can thus map up to PAGE_SIZE * 122 * framebuffer pages, and can thus map up to PAGE_SIZE *
107 * PAGE_SIZE / sizeof(*pd) bytes. With PAGE_SIZE == 4096 and 123 * PAGE_SIZE / sizeof(*pd) bytes. With PAGE_SIZE == 4096 and
108 * sizeof(unsigned long) == 4, that's 4 Megs. Two directory 124 * sizeof(unsigned long) == 4/8, that's 4 Megs 32 bit and 2
109 * pages should be enough for a while. 125 * Megs 64 bit. 256 directories give enough room for a 512
126 * Meg framebuffer with a max resolution of 12,800x10,240.
127 * Should be enough for a while with room leftover for
128 * expansion.
110 */ 129 */
111 unsigned long pd[2]; 130 unsigned long pd[256];
112}; 131};
113 132
114/* 133/*
115 * Wart: xenkbd needs to know resolution. Put it here until a better 134 * Wart: xenkbd needs to know default resolution. Put it here until a
116 * solution is found, but don't leak it to the backend. 135 * better solution is found, but don't leak it to the backend.
117 */ 136 */
118#ifdef __KERNEL__ 137#ifdef __KERNEL__
119#define XENFB_WIDTH 800 138#define XENFB_WIDTH 800
diff --git a/include/xen/interface/io/kbdif.h b/include/xen/interface/io/kbdif.h
index fb97f4284ffd..8066c7849fbe 100644
--- a/include/xen/interface/io/kbdif.h
+++ b/include/xen/interface/io/kbdif.h
@@ -49,6 +49,7 @@ struct xenkbd_motion {
49 uint8_t type; /* XENKBD_TYPE_MOTION */ 49 uint8_t type; /* XENKBD_TYPE_MOTION */
50 int32_t rel_x; /* relative X motion */ 50 int32_t rel_x; /* relative X motion */
51 int32_t rel_y; /* relative Y motion */ 51 int32_t rel_y; /* relative Y motion */
52 int32_t rel_z; /* relative Z motion (wheel) */
52}; 53};
53 54
54struct xenkbd_key { 55struct xenkbd_key {
@@ -61,6 +62,7 @@ struct xenkbd_position {
61 uint8_t type; /* XENKBD_TYPE_POS */ 62 uint8_t type; /* XENKBD_TYPE_POS */
62 int32_t abs_x; /* absolute X position (in FB pixels) */ 63 int32_t abs_x; /* absolute X position (in FB pixels) */
63 int32_t abs_y; /* absolute Y position (in FB pixels) */ 64 int32_t abs_y; /* absolute Y position (in FB pixels) */
65 int32_t rel_z; /* relative Z motion (wheel) */
64}; 66};
65 67
66#define XENKBD_IN_EVENT_SIZE 40 68#define XENKBD_IN_EVENT_SIZE 40
diff --git a/include/xen/interface/memory.h b/include/xen/interface/memory.h
index da768469aa92..af36ead16817 100644
--- a/include/xen/interface/memory.h
+++ b/include/xen/interface/memory.h
@@ -29,7 +29,7 @@ struct xen_memory_reservation {
29 * OUT: GMFN bases of extents that were allocated 29 * OUT: GMFN bases of extents that were allocated
30 * (NB. This command also updates the mach_to_phys translation table) 30 * (NB. This command also updates the mach_to_phys translation table)
31 */ 31 */
32 ulong extent_start; 32 GUEST_HANDLE(ulong) extent_start;
33 33
34 /* Number of extents, and size/alignment of each (2^extent_order pages). */ 34 /* Number of extents, and size/alignment of each (2^extent_order pages). */
35 unsigned long nr_extents; 35 unsigned long nr_extents;
@@ -50,6 +50,7 @@ struct xen_memory_reservation {
50 domid_t domid; 50 domid_t domid;
51 51
52}; 52};
53DEFINE_GUEST_HANDLE_STRUCT(xen_memory_reservation);
53 54
54/* 55/*
55 * Returns the maximum machine frame number of mapped RAM in this system. 56 * Returns the maximum machine frame number of mapped RAM in this system.
@@ -85,7 +86,7 @@ struct xen_machphys_mfn_list {
85 * any large discontiguities in the machine address space, 2MB gaps in 86 * any large discontiguities in the machine address space, 2MB gaps in
86 * the machphys table will be represented by an MFN base of zero. 87 * the machphys table will be represented by an MFN base of zero.
87 */ 88 */
88 ulong extent_start; 89 GUEST_HANDLE(ulong) extent_start;
89 90
90 /* 91 /*
91 * Number of extents written to the above array. This will be smaller 92 * Number of extents written to the above array. This will be smaller
@@ -93,6 +94,7 @@ struct xen_machphys_mfn_list {
93 */ 94 */
94 unsigned int nr_extents; 95 unsigned int nr_extents;
95}; 96};
97DEFINE_GUEST_HANDLE_STRUCT(xen_machphys_mfn_list);
96 98
97/* 99/*
98 * Sets the GPFN at which a particular page appears in the specified guest's 100 * Sets the GPFN at which a particular page appears in the specified guest's
@@ -115,6 +117,7 @@ struct xen_add_to_physmap {
115 /* GPFN where the source mapping page should appear. */ 117 /* GPFN where the source mapping page should appear. */
116 unsigned long gpfn; 118 unsigned long gpfn;
117}; 119};
120DEFINE_GUEST_HANDLE_STRUCT(xen_add_to_physmap);
118 121
119/* 122/*
120 * Translates a list of domain-specific GPFNs into MFNs. Returns a -ve error 123 * Translates a list of domain-specific GPFNs into MFNs. Returns a -ve error
@@ -129,13 +132,14 @@ struct xen_translate_gpfn_list {
129 unsigned long nr_gpfns; 132 unsigned long nr_gpfns;
130 133
131 /* List of GPFNs to translate. */ 134 /* List of GPFNs to translate. */
132 ulong gpfn_list; 135 GUEST_HANDLE(ulong) gpfn_list;
133 136
134 /* 137 /*
135 * Output list to contain MFN translations. May be the same as the input 138 * Output list to contain MFN translations. May be the same as the input
136 * list (in which case each input GPFN is overwritten with the output MFN). 139 * list (in which case each input GPFN is overwritten with the output MFN).
137 */ 140 */
138 ulong mfn_list; 141 GUEST_HANDLE(ulong) mfn_list;
139}; 142};
143DEFINE_GUEST_HANDLE_STRUCT(xen_translate_gpfn_list);
140 144
141#endif /* __XEN_PUBLIC_MEMORY_H__ */ 145#endif /* __XEN_PUBLIC_MEMORY_H__ */
diff --git a/include/xen/interface/xen.h b/include/xen/interface/xen.h
index 819a0331cda9..2befa3e2f1bc 100644
--- a/include/xen/interface/xen.h
+++ b/include/xen/interface/xen.h
@@ -114,9 +114,14 @@
114 * ptr[:2] -- Machine address within the frame whose mapping to modify. 114 * ptr[:2] -- Machine address within the frame whose mapping to modify.
115 * The frame must belong to the FD, if one is specified. 115 * The frame must belong to the FD, if one is specified.
116 * val -- Value to write into the mapping entry. 116 * val -- Value to write into the mapping entry.
117 *
118 * ptr[1:0] == MMU_PT_UPDATE_PRESERVE_AD:
119 * As MMU_NORMAL_PT_UPDATE above, but A/D bits currently in the PTE are ORed
120 * with those in @val.
117 */ 121 */
118#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */ 122#define MMU_NORMAL_PT_UPDATE 0 /* checked '*ptr = val'. ptr is MA. */
119#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */ 123#define MMU_MACHPHYS_UPDATE 1 /* ptr = MA of frame to modify entry for */
124#define MMU_PT_UPDATE_PRESERVE_AD 2 /* atomically: *ptr = val | (*ptr&(A|D)) */
120 125
121/* 126/*
122 * MMU EXTENDED OPERATIONS 127 * MMU EXTENDED OPERATIONS
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index 10ddfe0142d0..a706d6a78960 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -5,4 +5,10 @@
5 5
6DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu); 6DECLARE_PER_CPU(struct vcpu_info *, xen_vcpu);
7 7
8void xen_pre_suspend(void);
9void xen_post_suspend(int suspend_cancelled);
10
11void xen_mm_pin_all(void);
12void xen_mm_unpin_all(void);
13
8#endif /* INCLUDE_XEN_OPS_H */ 14#endif /* INCLUDE_XEN_OPS_H */