Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/async_tx: (24 commits)
  I/OAT: I/OAT version 3.0 support
  I/OAT: tcp_dma_copybreak default value dependent on I/OAT version
  I/OAT: Add watchdog/reset functionality to ioatdma
  iop_adma: cleanup iop_chan_xor_slot_count
  iop_adma: document how to calculate the minimum descriptor pool size
  iop_adma: directly reclaim descriptors on allocation failure
  async_tx: make async_tx_test_ack a boolean routine
  async_tx: remove depend_tx from async_tx_sync_epilog
  async_tx: export async_tx_quiesce
  async_tx: fix handling of the "out of descriptor" condition in async_xor
  async_tx: ensure the xor destination buffer remains dma-mapped
  async_tx: list_for_each_entry_rcu() cleanup
  dmaengine: Driver for the Synopsys DesignWare DMA controller
  dmaengine: Add slave DMA interface
  dmaengine: add DMA_COMPL_SKIP_{SRC,DEST}_UNMAP flags to control dma unmap
  dmaengine: Add dma_client parameter to device_alloc_chan_resources
  dmatest: Simple DMA memcpy test client
  dmaengine: DMA engine driver for Marvell XOR engine
  iop-adma: fix platform driver hotplug/coldplug
  dmaengine: track the number of clients using a channel
  ...

Fixed up conflict in drivers/dca/dca-sysfs.c manually

9 files changed, 194 insertions, 29 deletions

diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h
index 90d14ee564f5..ef4f5da2029f 100644
--- a/include/asm-arm/arch-iop13xx/adma.h
+++ b/include/asm-arm/arch-iop13xx/adma.h
@@ -198,17 +198,13 @@ iop_chan_memset_slot_count(size_t len, int *slots_per_op)
 static inline int
 iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
 {
-        int num_slots;
-        /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
-         * (1 source => 8 bytes) (1 slot => 32 bytes)
-         */
-        num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
-        if (((src_cnt - 1) << 3) & 0x1f)
-                num_slots++;
-
-        *slots_per_op = num_slots;
-
-        return num_slots;
+        static const char slot_count_table[] = { 1, 2, 2, 2,
+                                                 2, 3, 3, 3,
+                                                 3, 4, 4, 4,
+                                                 4, 5, 5, 5,
+                                                };
+        *slots_per_op = slot_count_table[src_cnt - 1];
+        return *slots_per_op;
 }
 
 #define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h
index a32b86ac62aa..af64676650a2 100644
--- a/include/asm-arm/hardware/iop3xx-adma.h
+++ b/include/asm-arm/hardware/iop3xx-adma.h
@@ -260,7 +260,7 @@ static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
 static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
                                         int *slots_per_op)
 {
-        static const int slot_count_table[] = { 0,
+        static const char slot_count_table[] = {
                                                 1, 1, 1, 1, /* 01 - 04 */
                                                 2, 2, 2, 2, /* 05 - 08 */
                                                 4, 4, 4, 4, /* 09 - 12 */
@@ -270,7 +270,7 @@ static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
                                                 8, 8, 8, 8, /* 25 - 28 */
                                                 8, 8, 8, 8, /* 29 - 32 */
                                               };
-        *slots_per_op = slot_count_table[src_cnt];
+        *slots_per_op = slot_count_table[src_cnt - 1];
         return *slots_per_op;
 }
 
diff --git a/include/asm-arm/plat-orion/mv_xor.h b/include/asm-arm/plat-orion/mv_xor.h
new file mode 100644
index 000000000000..c349e8ff5cc0
--- /dev/null
+++ b/include/asm-arm/plat-orion/mv_xor.h
@@ -0,0 +1,28 @@
+/*
+ * Marvell XOR platform device data definition file.
+ */
+
+#ifndef __ASM_PLAT_ORION_MV_XOR_H
+#define __ASM_PLAT_ORION_MV_XOR_H
+
+#include <linux/dmaengine.h>
+#include <linux/mbus.h>
+
+#define MV_XOR_SHARED_NAME      "mv_xor_shared"
+#define MV_XOR_NAME             "mv_xor"
+
+struct mbus_dram_target_info;
+
+struct mv_xor_platform_shared_data {
+        struct mbus_dram_target_info    *dram;
+};
+
+struct mv_xor_platform_data {
+        struct platform_device          *shared;
+        int                             hw_id;
+        dma_cap_mask_t                  cap_mask;
+        size_t                          pool_size;
+};
+
+
+#endif
diff --git a/include/asm-avr32/arch-at32ap/at32ap700x.h b/include/asm-avr32/arch-at32ap/at32ap700x.h
index 31e48b0e7324..d18a3053be0d 100644
--- a/include/asm-avr32/arch-at32ap/at32ap700x.h
+++ b/include/asm-avr32/arch-at32ap/at32ap700x.h
@@ -30,4 +30,20 @@
 #define GPIO_PIN_PD(N)  (GPIO_PIOD_BASE + (N))
 #define GPIO_PIN_PE(N)  (GPIO_PIOE_BASE + (N))
 
+
+/*
+ * DMAC peripheral hardware handshaking interfaces, used with dw_dmac
+ */
+#define DMAC_MCI_RX             0
+#define DMAC_MCI_TX             1
+#define DMAC_DAC_TX             2
+#define DMAC_AC97_A_RX          3
+#define DMAC_AC97_A_TX          4
+#define DMAC_AC97_B_RX          5
+#define DMAC_AC97_B_TX          6
+#define DMAC_DMAREQ_0           7
+#define DMAC_DMAREQ_1           8
+#define DMAC_DMAREQ_2           9
+#define DMAC_DMAREQ_3           10
+
 #endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/include/linux/async_tx.h b/include/linux/async_tx.h
index eb640f0acfac..0f50d4cc4360 100644
--- a/include/linux/async_tx.h
+++ b/include/linux/async_tx.h
@@ -101,21 +101,14 @@ async_tx_find_channel(struct dma_async_tx_descriptor *depend_tx,
 
 /**
  * async_tx_sync_epilog - actions to take if an operation is run synchronously
- * @flags: async_tx flags
- * @depend_tx: transaction depends on depend_tx
  * @cb_fn: function to call when the transaction completes
  * @cb_fn_param: parameter to pass to the callback routine
  */
 static inline void
-async_tx_sync_epilog(unsigned long flags,
-        struct dma_async_tx_descriptor *depend_tx,
-        dma_async_tx_callback cb_fn, void *cb_fn_param)
+async_tx_sync_epilog(dma_async_tx_callback cb_fn, void *cb_fn_param)
 {
         if (cb_fn)
                 cb_fn(cb_fn_param);
-
-        if (depend_tx && (flags & ASYNC_TX_DEP_ACK))
-                async_tx_ack(depend_tx);
 }
 
 void
@@ -152,4 +145,6 @@ struct dma_async_tx_descriptor *
 async_trigger_callback(enum async_tx_flags flags,
         struct dma_async_tx_descriptor *depend_tx,
         dma_async_tx_callback cb_fn, void *cb_fn_param);
+
+void async_tx_quiesce(struct dma_async_tx_descriptor **tx);
 #endif /* _ASYNC_TX_H_ */
diff --git a/include/linux/dca.h b/include/linux/dca.h
index af61cd1f37e9..b00a753eda53 100644
--- a/include/linux/dca.h
+++ b/include/linux/dca.h
@@ -10,6 +10,7 @@ void dca_unregister_notify(struct notifier_block *nb);
 #define DCA_PROVIDER_REMOVE  0x0002
 
 struct dca_provider {
+        struct list_head        node;
         struct dca_ops          *ops;
         struct device           *cd;
         int                      id;
@@ -18,7 +19,9 @@ struct dca_provider {
 struct dca_ops {
         int     (*add_requester)    (struct dca_provider *, struct device *);
         int     (*remove_requester) (struct dca_provider *, struct device *);
-        u8      (*get_tag)          (struct dca_provider *, int cpu);
+        u8      (*get_tag)          (struct dca_provider *, struct device *,
+                                     int cpu);
+        int     (*dev_managed)      (struct dca_provider *, struct device *);
 };
 
 struct dca_provider *alloc_dca_provider(struct dca_ops *ops, int priv_size);
@@ -32,9 +35,11 @@ static inline void *dca_priv(struct dca_provider *dca)
 }
 
 /* Requester API */
+#define DCA_GET_TAG_TWO_ARGS
 int dca_add_requester(struct device *dev);
 int dca_remove_requester(struct device *dev);
 u8 dca_get_tag(int cpu);
+u8 dca3_get_tag(struct device *dev, int cpu);
 
 /* internal stuff */
 int __init dca_sysfs_init(void);
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index d08a5c5eb928..adb0b084eb5a 100644
--- a/include/linux/dmaengine.h
+++ b/include/linux/dmaengine.h
@@ -89,10 +89,23 @@ enum dma_transaction_type {
         DMA_MEMSET,
         DMA_MEMCPY_CRC32C,
         DMA_INTERRUPT,
+        DMA_SLAVE,
 };
 
 /* last transaction type for creation of the capabilities mask */
-#define DMA_TX_TYPE_END (DMA_INTERRUPT + 1)
+#define DMA_TX_TYPE_END (DMA_SLAVE + 1)
+
+/**
+ * enum dma_slave_width - DMA slave register access width.
+ * @DMA_SLAVE_WIDTH_8BIT: Do 8-bit slave register accesses
+ * @DMA_SLAVE_WIDTH_16BIT: Do 16-bit slave register accesses
+ * @DMA_SLAVE_WIDTH_32BIT: Do 32-bit slave register accesses
+ */
+enum dma_slave_width {
+        DMA_SLAVE_WIDTH_8BIT,
+        DMA_SLAVE_WIDTH_16BIT,
+        DMA_SLAVE_WIDTH_32BIT,
+};
 
 /**
  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
@@ -102,10 +115,14 @@ enum dma_transaction_type {
  * @DMA_CTRL_ACK - the descriptor cannot be reused until the client
  *      acknowledges receipt, i.e. has has a chance to establish any
  *      dependency chains
+ * @DMA_COMPL_SKIP_SRC_UNMAP - set to disable dma-unmapping the source buffer(s)
+ * @DMA_COMPL_SKIP_DEST_UNMAP - set to disable dma-unmapping the destination(s)
  */
 enum dma_ctrl_flags {
         DMA_PREP_INTERRUPT = (1 << 0),
         DMA_CTRL_ACK = (1 << 1),
+        DMA_COMPL_SKIP_SRC_UNMAP = (1 << 2),
+        DMA_COMPL_SKIP_DEST_UNMAP = (1 << 3),
 };
 
 /**
@@ -115,6 +132,32 @@ enum dma_ctrl_flags {
 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
 
 /**
+ * struct dma_slave - Information about a DMA slave
+ * @dev: device acting as DMA slave
+ * @dma_dev: required DMA master device. If non-NULL, the client can not be
+ *      bound to other masters than this.
+ * @tx_reg: physical address of data register used for
+ *      memory-to-peripheral transfers
+ * @rx_reg: physical address of data register used for
+ *      peripheral-to-memory transfers
+ * @reg_width: peripheral register width
+ *
+ * If dma_dev is non-NULL, the client can not be bound to other DMA
+ * masters than the one corresponding to this device. The DMA master
+ * driver may use this to determine if there is controller-specific
+ * data wrapped around this struct. Drivers of platform code that sets
+ * the dma_dev field must therefore make sure to use an appropriate
+ * controller-specific dma slave structure wrapping this struct.
+ */
+struct dma_slave {
+        struct device           *dev;
+        struct device           *dma_dev;
+        dma_addr_t              tx_reg;
+        dma_addr_t              rx_reg;
+        enum dma_slave_width    reg_width;
+};
+
+/**
  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
  * @refcount: local_t used for open-coded "bigref" counting
  * @memcpy_count: transaction counter
@@ -139,6 +182,7 @@ struct dma_chan_percpu {
  * @rcu: the DMA channel's RCU head
  * @device_node: used to add this to the device chan list
  * @local: per-cpu pointer to a struct dma_chan_percpu
+ * @client-count: how many clients are using this channel
  */
 struct dma_chan {
         struct dma_device *device;
@@ -154,6 +198,7 @@ struct dma_chan {
 
         struct list_head device_node;
         struct dma_chan_percpu *local;
+        int client_count;
 };
 
 #define to_dma_chan(p) container_of(p, struct dma_chan, dev)
@@ -202,11 +247,14 @@ typedef enum dma_state_client (*dma_event_callback) (struct dma_client *client,
  * @event_callback: func ptr to call when something happens
  * @cap_mask: only return channels that satisfy the requested capabilities
  *  a value of zero corresponds to any capability
+ * @slave: data for preparing slave transfer. Must be non-NULL iff the
+ *  DMA_SLAVE capability is requested.
  * @global_node: list_head for global dma_client_list
  */
 struct dma_client {
         dma_event_callback      event_callback;
         dma_cap_mask_t          cap_mask;
+        struct dma_slave        *slave;
         struct list_head        global_node;
 };
 
@@ -263,6 +311,8 @@ struct dma_async_tx_descriptor {
  * @device_prep_dma_zero_sum: prepares a zero_sum operation
  * @device_prep_dma_memset: prepares a memset operation
  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
+ * @device_prep_slave_sg: prepares a slave dma operation
+ * @device_terminate_all: terminate all pending operations
  * @device_issue_pending: push pending transactions to hardware
  */
 struct dma_device {
@@ -279,7 +329,8 @@ struct dma_device {
         int dev_id;
         struct device *dev;
 
-        int (*device_alloc_chan_resources)(struct dma_chan *chan);
+        int (*device_alloc_chan_resources)(struct dma_chan *chan,
+                        struct dma_client *client);
         void (*device_free_chan_resources)(struct dma_chan *chan);
 
         struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
@@ -297,6 +348,12 @@ struct dma_device {
         struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
                 struct dma_chan *chan, unsigned long flags);
 
+        struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
+                struct dma_chan *chan, struct scatterlist *sgl,
+                unsigned int sg_len, enum dma_data_direction direction,
+                unsigned long flags);
+        void (*device_terminate_all)(struct dma_chan *chan);
+
         enum dma_status (*device_is_tx_complete)(struct dma_chan *chan,
                         dma_cookie_t cookie, dma_cookie_t *last,
                         dma_cookie_t *used);
@@ -318,16 +375,14 @@ dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
         struct dma_chan *chan);
 
-static inline void
-async_tx_ack(struct dma_async_tx_descriptor *tx)
+static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
 {
         tx->flags |= DMA_CTRL_ACK;
 }
 
-static inline int
-async_tx_test_ack(struct dma_async_tx_descriptor *tx)
+static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
 {
-        return tx->flags & DMA_CTRL_ACK;
+        return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
 }
 
 #define first_dma_cap(mask) __first_dma_cap(&(mask))
diff --git a/include/linux/dw_dmac.h b/include/linux/dw_dmac.h
new file mode 100644
index 000000000000..04d217b442bf
--- /dev/null
+++ b/include/linux/dw_dmac.h
@@ -0,0 +1,62 @@
+/*
+ * Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
+ * AVR32 systems.)
+ *
+ * Copyright (C) 2007 Atmel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef DW_DMAC_H
+#define DW_DMAC_H
+
+#include <linux/dmaengine.h>
+
+/**
+ * struct dw_dma_platform_data - Controller configuration parameters
+ * @nr_channels: Number of channels supported by hardware (max 8)
+ */
+struct dw_dma_platform_data {
+        unsigned int    nr_channels;
+};
+
+/**
+ * struct dw_dma_slave - Controller-specific information about a slave
+ * @slave: Generic information about the slave
+ * @ctl_lo: Platform-specific initializer for the CTL_LO register
+ * @cfg_hi: Platform-specific initializer for the CFG_HI register
+ * @cfg_lo: Platform-specific initializer for the CFG_LO register
+ */
+struct dw_dma_slave {
+        struct dma_slave        slave;
+        u32                     cfg_hi;
+        u32                     cfg_lo;
+};
+
+/* Platform-configurable bits in CFG_HI */
+#define DWC_CFGH_FCMODE         (1 << 0)
+#define DWC_CFGH_FIFO_MODE      (1 << 1)
+#define DWC_CFGH_PROTCTL(x)     ((x) << 2)
+#define DWC_CFGH_SRC_PER(x)     ((x) << 7)
+#define DWC_CFGH_DST_PER(x)     ((x) << 11)
+
+/* Platform-configurable bits in CFG_LO */
+#define DWC_CFGL_PRIO(x)        ((x) << 5)      /* priority */
+#define DWC_CFGL_LOCK_CH_XFER   (0 << 12)       /* scope of LOCK_CH */
+#define DWC_CFGL_LOCK_CH_BLOCK  (1 << 12)
+#define DWC_CFGL_LOCK_CH_XACT   (2 << 12)
+#define DWC_CFGL_LOCK_BUS_XFER  (0 << 14)       /* scope of LOCK_BUS */
+#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
+#define DWC_CFGL_LOCK_BUS_XACT  (2 << 14)
+#define DWC_CFGL_LOCK_CH        (1 << 15)       /* channel lockout */
+#define DWC_CFGL_LOCK_BUS       (1 << 16)       /* busmaster lockout */
+#define DWC_CFGL_HS_DST_POL     (1 << 18)       /* dst handshake active low */
+#define DWC_CFGL_HS_SRC_POL     (1 << 19)       /* src handshake active low */
+
+static inline struct dw_dma_slave *to_dw_dma_slave(struct dma_slave *slave)
+{
+        return container_of(slave, struct dw_dma_slave, slave);
+}
+
+#endif /* DW_DMAC_H */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index d8507eb394cf..119ae7b8f028 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2371,6 +2371,14 @@
 #define PCI_DEVICE_ID_INTEL_ICH9_7      0x2916
 #define PCI_DEVICE_ID_INTEL_ICH9_8      0x2918
 #define PCI_DEVICE_ID_INTEL_82855PM_HB  0x3340
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG4   0x3429
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG5   0x342a
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG6   0x342b
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG7   0x342c
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG0   0x3430
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG1   0x3431
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG2   0x3432
+#define PCI_DEVICE_ID_INTEL_IOAT_TBG3   0x3433
 #define PCI_DEVICE_ID_INTEL_82830_HB    0x3575
 #define PCI_DEVICE_ID_INTEL_82830_CGC   0x3577
 #define PCI_DEVICE_ID_INTEL_82855GM_HB  0x3580