aboutsummaryrefslogtreecommitdiffstats
path: root/include
diff options
context:
space:
mode:
authorLennert Buytenhek <buytenh@wantstofly.org>2006-03-28 15:00:40 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-28 15:00:40 -0500
commit23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa (patch)
tree56636558e8cdeee0739e7d8c82d66ffe625340b3 /include
parentde4533a04eb4f66dbef71f59a9c118256b886823 (diff)
[ARM] 3377/2: add support for intel xsc3 core
Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/cacheflush.h8
-rw-r--r--include/asm-arm/domain.h18
-rw-r--r--include/asm-arm/page.h9
-rw-r--r--include/asm-arm/proc-fns.h8
-rw-r--r--include/asm-arm/system.h19
5 files changed, 62 insertions, 0 deletions
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
index 09e19a783a51..746be56b1b70 100644
--- a/include/asm-arm/cacheflush.h
+++ b/include/asm-arm/cacheflush.h
@@ -71,6 +71,14 @@
71# endif 71# endif
72#endif 72#endif
73 73
74#if defined(CONFIG_CPU_XSC3)
75# ifdef _CACHE
76# define MULTI_CACHE 1
77# else
78# define _CACHE xsc3
79# endif
80#endif
81
74#if defined(CONFIG_CPU_V6) 82#if defined(CONFIG_CPU_V6)
75//# ifdef _CACHE 83//# ifdef _CACHE
76# define MULTI_CACHE 1 84# define MULTI_CACHE 1
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
index da1d960387d9..f8ea2de4848e 100644
--- a/include/asm-arm/domain.h
+++ b/include/asm-arm/domain.h
@@ -16,11 +16,29 @@
16 * DOMAIN_IO - domain 2 includes all IO only 16 * DOMAIN_IO - domain 2 includes all IO only
17 * DOMAIN_USER - domain 1 includes all user memory only 17 * DOMAIN_USER - domain 1 includes all user memory only
18 * DOMAIN_KERNEL - domain 0 includes all kernel memory only 18 * DOMAIN_KERNEL - domain 0 includes all kernel memory only
19 *
20 * The domain numbering depends on whether we support 36 physical
21 * address for I/O or not. Addresses above the 32 bit boundary can
22 * only be mapped using supersections and supersections can only
23 * be set for domain 0. We could just default to DOMAIN_IO as zero,
24 * but there may be systems with supersection support and no 36-bit
25 * addressing. In such cases, we want to map system memory with
26 * supersections to reduce TLB misses and footprint.
27 *
28 * 36-bit addressing and supersections are only available on
29 * CPUs based on ARMv6+ or the Intel XSC3 core.
19 */ 30 */
31#ifndef CONFIG_IO_36
20#define DOMAIN_KERNEL 0 32#define DOMAIN_KERNEL 0
21#define DOMAIN_TABLE 0 33#define DOMAIN_TABLE 0
22#define DOMAIN_USER 1 34#define DOMAIN_USER 1
23#define DOMAIN_IO 2 35#define DOMAIN_IO 2
36#else
37#define DOMAIN_KERNEL 2
38#define DOMAIN_TABLE 2
39#define DOMAIN_USER 1
40#define DOMAIN_IO 0
41#endif
24 42
25/* 43/*
26 * Domain types 44 * Domain types
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
index 416320d95419..a404d2bf0c68 100644
--- a/include/asm-arm/page.h
+++ b/include/asm-arm/page.h
@@ -40,6 +40,7 @@
40 * v4wb - ARMv4 with writeback cache, without minicache 40 * v4wb - ARMv4 with writeback cache, without minicache
41 * v4_mc - ARMv4 with minicache 41 * v4_mc - ARMv4 with minicache
42 * xscale - Xscale 42 * xscale - Xscale
43 * xsc3 - XScalev3
43 */ 44 */
44#undef _USER 45#undef _USER
45#undef MULTI_USER 46#undef MULTI_USER
@@ -84,6 +85,14 @@
84# endif 85# endif
85#endif 86#endif
86 87
88#ifdef CONFIG_CPU_XSC3
89# ifdef _USER
90# define MULTI_USER 1
91# else
92# define _USER xsc3_mc
93# endif
94#endif
95
87#ifdef CONFIG_CPU_COPY_V6 96#ifdef CONFIG_CPU_COPY_V6
88# define MULTI_USER 1 97# define MULTI_USER 1
89#endif 98#endif
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
index 7bef2bf6be51..106045edb862 100644
--- a/include/asm-arm/proc-fns.h
+++ b/include/asm-arm/proc-fns.h
@@ -138,6 +138,14 @@
138# define CPU_NAME cpu_xscale 138# define CPU_NAME cpu_xscale
139# endif 139# endif
140# endif 140# endif
141# ifdef CONFIG_CPU_XSC3
142# ifdef CPU_NAME
143# undef MULTI_CPU
144# define MULTI_CPU
145# else
146# define CPU_NAME cpu_xsc3
147# endif
148# endif
141# ifdef CONFIG_CPU_V6 149# ifdef CONFIG_CPU_V6
142# ifdef CPU_NAME 150# ifdef CPU_NAME
143# undef MULTI_CPU 151# undef MULTI_CPU
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index ec91d1ff032a..95b3abf4851b 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -108,6 +108,25 @@ extern void __show_regs(struct pt_regs *);
108extern int cpu_architecture(void); 108extern int cpu_architecture(void);
109extern void cpu_init(void); 109extern void cpu_init(void);
110 110
111/*
112 * Intel's XScale3 core supports some v6 features (supersections, L2)
113 * but advertises itself as v5 as it does not support the v6 ISA. For
114 * this reason, we need a way to explicitly test for this type of CPU.
115 */
116#ifndef CONFIG_CPU_XSC3
117#define cpu_is_xsc3() 0
118#else
119static inline int cpu_is_xsc3(void)
120{
121 extern unsigned int processor_id;
122
123 if ((processor_id & 0xffffe000) == 0x69056000)
124 return 1;
125
126 return 0;
127}
128#endif
129
111#define set_cr(x) \ 130#define set_cr(x) \
112 __asm__ __volatile__( \ 131 __asm__ __volatile__( \
113 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \ 132 "mcr p15, 0, %0, c1, c0, 0 @ set CR" \