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authorBryan Wu <bryan.wu@analog.com>2007-05-21 06:09:31 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-05-21 12:50:23 -0400
commit19381f024b01413d83cec1655c3fc4c9c09ae274 (patch)
tree4ba1d63900e031c97130638c2d678aaf15c3d37e /include
parentc09c4e006590210001ced90d59e62182bfd396f9 (diff)
Blackfin arch: update blackfin header files to latest one in VDSP.
a) add new processor BF52x/BF54x header files b) update blackfin BF533/BF537/BF561 header files to latest one in VDSP. c) scrub watchdog/rtc masks from headers as we dont need/want them (too generic and the drivers dont use them) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Roy Huang <roy.huang@analog.com> Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF522.h46
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF525.h461
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF527.h626
-rw-r--r--include/asm-blackfin/mach-bf527/cdefBF52x_base.h1187
-rw-r--r--include/asm-blackfin/mach-bf527/defBF522.h42
-rw-r--r--include/asm-blackfin/mach-bf527/defBF525.h713
-rw-r--r--include/asm-blackfin/mach-bf527/defBF527.h1089
-rw-r--r--include/asm-blackfin/mach-bf527/defBF52x_base.h2009
-rw-r--r--include/asm-blackfin/mach-bf533/cdefBF532.h30
-rw-r--r--include/asm-blackfin/mach-bf533/defBF532.h207
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h8
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h90
-rw-r--r--include/asm-blackfin/mach-bf537/defBF537.h8
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF542.h590
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF544.h978
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF548.h1610
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF549.h1896
-rw-r--r--include/asm-blackfin/mach-bf548/cdefBF54x_base.h2722
-rw-r--r--include/asm-blackfin/mach-bf548/defBF542.h1206
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h766
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h1966
-rw-r--r--include/asm-blackfin/mach-bf548/defBF549.h3472
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h4902
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h105
24 files changed, 26559 insertions, 170 deletions
diff --git a/include/asm-blackfin/mach-bf527/cdefBF522.h b/include/asm-blackfin/mach-bf527/cdefBF522.h
new file mode 100644
index 000000000000..52c06494b886
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF522.h
@@ -0,0 +1,46 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf522.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF522_H
33#define _CDEF_BF522_H
34
35/* include all Core registers and bit definitions */
36#include "defBF522.h"
37
38/* include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46#endif /* _CDEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF525.h b/include/asm-blackfin/mach-bf527/cdefBF525.h
new file mode 100644
index 000000000000..2cc67e4b4d86
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF525.h
@@ -0,0 +1,461 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf525.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF525_H
33#define _CDEF_BF525_H
34
35/* include all Core registers and bit definitions */
36#include "defBF525.h"
37
38/* include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
47
48/* USB Control Registers */
49
50#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
51#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
52#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
53#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
54#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
55#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
56#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
57#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
58#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
59#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
60#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
61#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
62#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
63#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
64#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
65#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
66#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
67#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
68#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
69#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
70#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
71#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
72#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
73#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
74#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
75#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
76
77/* USB Packet Control Registers */
78
79#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
80#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
81#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
82#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
83#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
84#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
85#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
86#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
87#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
88#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
89#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
90#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
91#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
92#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
93#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
94#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
95#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
96#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
97#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
98#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
99#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
100#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
101#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
102#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
103#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
104#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
105
106/* USB Endpoint FIFO Registers */
107
108#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
109#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
110#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
111#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
112#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
113#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
114#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
115#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
116#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
117#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
118#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
119#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
120#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
121#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
122#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
123#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
124
125/* USB OTG Control Registers */
126
127#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
128#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
129#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
130#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
131#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
132#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
133
134/* USB Phy Control Registers */
135
136#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
137#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
138#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
139#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
140#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
141#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
142#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
143#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
144#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
145#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
146
147/* (APHY_CNTRL is for ADI usage only) */
148
149#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
150#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
151
152/* (APHY_CALIB is for ADI usage only) */
153
154#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
155#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
156
157#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
158#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
159
160/* (PHY_TEST is for ADI usage only) */
161
162#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
163#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
164
165#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
166#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
167#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
168#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
169
170/* USB Endpoint 0 Control Registers */
171
172#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
173#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
174#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
175#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
176#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
177#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
178#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
179#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
180#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
181#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
182#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
183#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
184#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
185#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
186#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
187#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
188#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
189#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
190#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
191#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
192
193/* USB Endpoint 1 Control Registers */
194
195#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
196#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
197#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
198#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
199#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
200#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
201#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
202#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
203#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
204#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
205#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
206#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
207#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
208#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
209#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
210#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
211#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
212#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
213#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
214#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
215
216/* USB Endpoint 2 Control Registers */
217
218#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
219#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
220#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
221#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
222#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
223#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
224#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
225#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
226#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
227#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
228#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
229#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
230#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
231#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
232#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
233#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
234#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
235#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
236#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
237#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
238
239/* USB Endpoint 3 Control Registers */
240
241#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
242#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
243#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
244#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
245#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
246#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
247#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
248#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
249#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
250#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
251#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
252#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
253#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
254#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
255#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
256#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
257#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
258#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
259#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
260#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
261
262/* USB Endpoint 4 Control Registers */
263
264#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
265#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
266#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
267#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
268#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
269#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
270#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
271#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
272#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
273#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
274#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
275#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
276#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
277#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
278#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
279#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
280#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
281#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
282#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
283#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
284
285/* USB Endpoint 5 Control Registers */
286
287#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
288#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
289#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
290#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
291#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
292#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
293#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
294#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
295#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
296#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
297#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
298#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
299#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
300#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
301#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
302#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
303#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
304#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
305#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
306#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
307
308/* USB Endpoint 6 Control Registers */
309
310#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
311#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
312#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
313#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
314#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
315#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
316#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
317#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
318#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
319#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
320#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
321#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
322#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
323#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
324#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
325#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
326#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
327#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
328#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
329#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
330
331/* USB Endpoint 7 Control Registers */
332
333#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
334#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
335#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
336#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
337#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
338#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
339#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
340#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
341#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
342#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
343#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
344#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
345#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
346#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
347#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
348#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
349#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
350#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
351#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
352#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
353
354#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
355#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
356
357/* USB Channel 0 Config Registers */
358
359#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
360#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
361#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
362#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
363#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
364#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
365#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
366#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
367#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
368#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
369
370/* USB Channel 1 Config Registers */
371
372#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
373#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
374#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
375#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
376#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
377#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
378#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
379#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
380#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
381#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
382
383/* USB Channel 2 Config Registers */
384
385#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
386#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
387#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
388#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
389#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
390#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
391#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
392#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
393#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
394#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
395
396/* USB Channel 3 Config Registers */
397
398#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
399#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
400#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
401#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
402#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
403#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
404#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
405#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
406#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
407#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
408
409/* USB Channel 4 Config Registers */
410
411#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
412#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
413#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
414#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
415#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
416#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
417#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
418#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
419#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
420#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
421
422/* USB Channel 5 Config Registers */
423
424#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
425#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
426#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
427#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
428#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
429#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
430#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
431#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
432#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
433#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
434
435/* USB Channel 6 Config Registers */
436
437#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
438#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
439#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
440#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
441#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
442#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
443#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
444#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
445#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
446#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
447
448/* USB Channel 7 Config Registers */
449
450#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
451#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
452#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
453#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
454#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
455#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
456#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
457#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
458#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
459#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
460
461#endif /* _CDEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF527.h b/include/asm-blackfin/mach-bf527/cdefBF527.h
new file mode 100644
index 000000000000..5bd1a8601743
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF527.h
@@ -0,0 +1,626 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefbf527.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description: system mmr register map
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 *
14 * Bugs: Enter bugs at http://blackfin.uclinux.org/
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2, or (at your option)
19 * any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; see the file COPYING.
28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */
31
32#ifndef _CDEF_BF527_H
33#define _CDEF_BF527_H
34
35/* include all Core registers and bit definitions */
36#include "defBF527.h"
37
38/* include core specific register pointer definitions */
39#include <asm/mach-common/cdef_LPBlackfin.h>
40
41/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
42
43/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
44#include "cdefBF52x_base.h"
45
46/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
47
48/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
49
50#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
51#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
52#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
53#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
54#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
55#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
56#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
57#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
58#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
59#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
60#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
61#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
62#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
63#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
64#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
65#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
66#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
67#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
68#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
69#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
70#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
71#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
72#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
73#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
74#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
75#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
76#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
77#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
78#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
79#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
80#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
81#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
82#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
83#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
84#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
85#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
86#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
87#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
88
89#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
90#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
91#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
92#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
93#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
94#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
95#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
96#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
97#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
98#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
99#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
100#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
101#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
102#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
103#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
104#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
105
106#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
107#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
108#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
109#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
110#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
111#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
112#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
113#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
114#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
115#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
116
117#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
118#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
119#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
120#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
121#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
122#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
123#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
124#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
125#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
126#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
127#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
128#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
129#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
130#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
131#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
132#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
133#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
134#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
135#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
136#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
137#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
138#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
139#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
140#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
141#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
142#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
143#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
144#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
145#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
146#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
147#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
148#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
149#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
150#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
151#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
152#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
153#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
154#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
155#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
156#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
157#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
158#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
159#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
160#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
161#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
162#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
163#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
164#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
165
166#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
167#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
168#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
169#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
170#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
171#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
172#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
173#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
174#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
175#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
176#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
177#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
178#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
179#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
180#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
181#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
182#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
183#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
184#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
185#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
186#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
187#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
188#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
189#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
190#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
191#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
192#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
193#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
194#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
195#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
196#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
197#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
198#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
199#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
200#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
201#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
202#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
203#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
204#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
205#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
206#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
207#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
208#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
209#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
210#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
211#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
212
213/* USB Control Registers */
214
215#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
216#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
217#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
218#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
219#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
220#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
221#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
222#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
223#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
224#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
225#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
226#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
227#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
228#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
229#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
230#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
231#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
232#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
233#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
234#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
235#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
236#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
237#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
238#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
239#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
240#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
241
242/* USB Packet Control Registers */
243
244#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
245#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
246#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
247#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
248#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
249#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
250#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
251#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
252#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
253#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
254#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
255#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
256#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
257#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
258#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
259#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
260#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
261#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
262#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
263#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
264#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
265#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
266#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
267#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
268#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
269#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
270
271/* USB Endpoint FIFO Registers */
272
273#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
274#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
275#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
276#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
277#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
278#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
279#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
280#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
281#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
282#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
283#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
284#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
285#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
286#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
287#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
288#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
289
290/* USB OTG Control Registers */
291
292#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
293#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
294#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
295#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
296#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
297#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
298
299/* USB Phy Control Registers */
300
301#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
302#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
303#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
304#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
305#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
306#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
307#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
308#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
309#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
310#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
311
312/* (APHY_CNTRL is for ADI usage only) */
313
314#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
315#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
316
317/* (APHY_CALIB is for ADI usage only) */
318
319#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
320#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
321
322#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
323#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
324
325/* (PHY_TEST is for ADI usage only) */
326
327#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
328#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
329
330#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
331#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
332#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
333#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
334
335/* USB Endpoint 0 Control Registers */
336
337#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
338#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
339#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
340#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
341#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
342#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
343#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
344#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
345#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
346#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
347#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
348#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
349#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
350#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
351#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
352#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
353#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
354#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
355#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
356#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
357
358/* USB Endpoint 1 Control Registers */
359
360#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
361#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
362#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
363#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
364#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
365#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
366#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
367#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
368#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
369#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
370#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
371#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
372#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
373#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
374#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
375#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
376#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
377#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
378#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
379#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
380
381/* USB Endpoint 2 Control Registers */
382
383#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
384#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
385#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
386#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
387#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
388#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
389#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
390#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
391#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
392#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
393#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
394#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
395#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
396#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
397#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
398#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
399#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
400#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
401#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
402#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
403
404/* USB Endpoint 3 Control Registers */
405
406#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
407#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
408#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
409#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
410#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
411#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
412#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
413#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
414#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
415#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
416#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
417#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
418#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
419#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
420#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
421#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
422#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
423#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
424#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
425#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
426
427/* USB Endpoint 4 Control Registers */
428
429#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
430#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
431#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
432#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
433#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
434#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
435#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
436#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
437#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
438#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
439#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
440#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
441#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
442#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
443#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
444#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
445#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
446#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
447#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
448#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
449
450/* USB Endpoint 5 Control Registers */
451
452#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
453#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
454#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
455#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
456#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
457#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
458#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
459#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
460#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
461#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
462#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
463#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
464#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
465#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
466#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
467#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
468#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
469#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
470#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
471#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
472
473/* USB Endpoint 6 Control Registers */
474
475#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
476#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
477#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
478#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
479#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
480#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
481#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
482#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
483#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
484#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
485#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
486#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
487#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
488#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
489#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
490#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
491#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
492#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
493#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
494#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
495
496/* USB Endpoint 7 Control Registers */
497
498#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
499#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
500#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
501#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
502#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
503#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
504#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
505#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
506#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
507#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
508#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
509#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
510#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
511#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
512#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
513#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
514#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
515#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
516#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
517#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
518
519#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
520#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
521
522/* USB Channel 0 Config Registers */
523
524#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
525#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
526#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
527#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
528#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
529#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
530#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
531#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
532#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
533#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
534
535/* USB Channel 1 Config Registers */
536
537#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
538#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
539#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
540#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
541#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
542#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
543#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
544#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
545#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
546#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
547
548/* USB Channel 2 Config Registers */
549
550#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
551#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
552#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
553#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
554#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
555#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
556#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
557#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
558#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
559#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
560
561/* USB Channel 3 Config Registers */
562
563#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
564#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
565#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
566#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
567#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
568#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
569#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
570#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
571#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
572#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
573
574/* USB Channel 4 Config Registers */
575
576#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
577#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
578#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
579#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
580#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
581#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
582#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
583#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
584#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
585#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
586
587/* USB Channel 5 Config Registers */
588
589#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
590#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
591#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
592#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
593#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
594#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
595#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
596#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
597#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
598#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
599
600/* USB Channel 6 Config Registers */
601
602#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
603#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
604#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
605#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
606#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
607#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
608#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
609#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
610#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
611#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
612
613/* USB Channel 7 Config Registers */
614
615#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
616#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
617#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
618#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
619#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
620#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
621#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
622#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
623#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
624#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
625
626#endif /* _CDEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
new file mode 100644
index 000000000000..5f801a0ef797
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
@@ -0,0 +1,1187 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/cdefBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF52X_H
32
33#include "defBF52x_base.h"
34
35/* ==== begin from cdefBF534.h ==== */
36
37/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
38#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
39#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
40#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
41#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
42#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
43#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
44#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
45#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
46#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
47#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
48#define bfin_read_CHIPID() bfin_read16(CHIPID)
49#define bfin_write_CHIPID(val) bfin_write16(CHIPID, val)
50
51
52/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
53#define bfin_read_SWRST() bfin_read16(SWRST)
54#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
55#define bfin_read_SYSCR() bfin_read16(SYSCR)
56#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
57
58#define bfin_read_SIC_RVECT() bfin_read32(SIC_RVECT)
59#define bfin_write_SIC_RVECT(val) bfin_write32(SIC_RVECT, val)
60#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
61#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
62/* legacy register name (below) provided for backwards code compatibility */
63#define bfin_read_SIC_IMASK() bfin_read32(SIC_IMASK)
64#define bfin_write_SIC_IMASK(val) bfin_write32(SIC_IMASK, val)
65
66#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
67#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
68#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
69#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
70#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
71#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
72#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
73#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
74
75#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
76#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
77/* legacy register name (below) provided for backwards code compatibility */
78#define bfin_read_SIC_ISR() bfin_read32(SIC_ISR)
79#define bfin_write_SIC_ISR(val) bfin_write32(SIC_ISR, val)
80
81#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
82#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
83/* legacy register name (below) provided for backwards code compatibility */
84#define bfin_read_SIC_IWR() bfin_read32(SIC_IWR)
85#define bfin_write_SIC_IWR(val) bfin_write32(SIC_IWR, val)
86
87/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
88
89#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
90#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
91#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
92#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
93#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
94#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
95#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
96#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
97#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
98#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
99#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
100#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
101#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
102#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
103
104/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
105#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
106#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
107#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
108#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
109#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
110#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
111
112
113/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
114#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
115#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
116#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
117#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
118#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
119#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
120#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
121#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
122#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
123#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
124#define bfin_read_RTC_FAST() bfin_read16(RTC_FAST)
125#define bfin_write_RTC_FAST(val) bfin_write16(RTC_FAST, val)
126#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
127#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
128
129
130/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
131#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
132#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
133#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
134#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
135#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
136#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
137#define bfin_read_UART0_IER() bfin_read16(UART0_IER)
138#define bfin_write_UART0_IER(val) bfin_write16(UART0_IER, val)
139#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
140#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
141#define bfin_read_UART0_IIR() bfin_read16(UART0_IIR)
142#define bfin_write_UART0_IIR(val) bfin_write16(UART0_IIR, val)
143#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
144#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
145#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
146#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
147#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
148#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
149#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
150#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
151#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
152#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
153#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
154#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
155
156
157/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
158#define bfin_read_SPI_CTL() bfin_read16(SPI_CTL)
159#define bfin_write_SPI_CTL(val) bfin_write16(SPI_CTL, val)
160#define bfin_read_SPI_FLG() bfin_read16(SPI_FLG)
161#define bfin_write_SPI_FLG(val) bfin_write16(SPI_FLG, val)
162#define bfin_read_SPI_STAT() bfin_read16(SPI_STAT)
163#define bfin_write_SPI_STAT(val) bfin_write16(SPI_STAT, val)
164#define bfin_read_SPI_TDBR() bfin_read16(SPI_TDBR)
165#define bfin_write_SPI_TDBR(val) bfin_write16(SPI_TDBR, val)
166#define bfin_read_SPI_RDBR() bfin_read16(SPI_RDBR)
167#define bfin_write_SPI_RDBR(val) bfin_write16(SPI_RDBR, val)
168#define bfin_read_SPI_BAUD() bfin_read16(SPI_BAUD)
169#define bfin_write_SPI_BAUD(val) bfin_write16(SPI_BAUD, val)
170#define bfin_read_SPI_SHADOW() bfin_read16(SPI_SHADOW)
171#define bfin_write_SPI_SHADOW(val) bfin_write16(SPI_SHADOW, val)
172
173
174/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
175#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
176#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
177#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
178#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
179#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
180#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
181#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
182#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
183
184#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
185#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
186#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
187#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
188#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
189#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
190#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
191#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
192
193#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
194#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
195#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
196#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
197#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
198#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
199#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
200#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
201
202#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
203#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
204#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
205#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
206#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
207#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
208#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
209#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
210
211#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
212#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
213#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
214#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
215#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
216#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
217#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
218#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
219
220#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
221#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
222#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
223#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
224#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
225#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
226#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
227#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
228
229#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
230#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
231#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
232#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
233#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
234#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
235#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
236#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
237
238#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
239#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
240#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
241#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
242#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
243#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
244#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
245#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
246
247#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
248#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
249#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
250#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
251#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
252#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
253
254
255/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
256#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
257#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
258#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
259#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
260#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
261#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
262#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
263#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
264#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
265#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
266#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
267#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
268#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
269#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
270#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
271#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
272#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
273#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
274#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
275#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
276#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
277#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
278#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
279#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
280#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
281#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
282#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
283#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
284#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
285#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
286#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
287#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
288#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
289#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
290
291
292/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
293#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
294#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
295#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
296#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
297#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
298#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
299#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
300#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
301#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
302#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
303#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
304#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
305#define bfin_read_SPORT0_TX32() bfin_read32(SPORT0_TX32)
306#define bfin_write_SPORT0_TX32(val) bfin_write32(SPORT0_TX32, val)
307#define bfin_read_SPORT0_RX32() bfin_read32(SPORT0_RX32)
308#define bfin_write_SPORT0_RX32(val) bfin_write32(SPORT0_RX32, val)
309#define bfin_read_SPORT0_TX16() bfin_read16(SPORT0_TX16)
310#define bfin_write_SPORT0_TX16(val) bfin_write16(SPORT0_TX16, val)
311#define bfin_read_SPORT0_RX16() bfin_read16(SPORT0_RX16)
312#define bfin_write_SPORT0_RX16(val) bfin_write16(SPORT0_RX16, val)
313#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
314#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
315#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
316#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
317#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
318#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
319#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
320#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
321#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
322#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
323#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
324#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
325#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
326#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
327#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
328#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
329#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
330#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
331#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
332#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
333#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
334#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
335#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
336#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
337#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
338#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
339#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
340#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
341#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
342#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
343#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
344#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
345
346
347/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
348#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
349#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
350#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
351#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
352#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
353#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
354#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
355#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
356#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
357#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
358#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
359#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
360#define bfin_read_SPORT1_TX32() bfin_read32(SPORT1_TX32)
361#define bfin_write_SPORT1_TX32(val) bfin_write32(SPORT1_TX32, val)
362#define bfin_read_SPORT1_RX32() bfin_read32(SPORT1_RX32)
363#define bfin_write_SPORT1_RX32(val) bfin_write32(SPORT1_RX32, val)
364#define bfin_read_SPORT1_TX16() bfin_read16(SPORT1_TX16)
365#define bfin_write_SPORT1_TX16(val) bfin_write16(SPORT1_TX16, val)
366#define bfin_read_SPORT1_RX16() bfin_read16(SPORT1_RX16)
367#define bfin_write_SPORT1_RX16(val) bfin_write16(SPORT1_RX16, val)
368#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
369#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
370#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
371#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
372#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
373#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
374#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
375#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
376#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
377#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
378#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
379#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
380#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
381#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
382#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
383#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
384#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
385#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
386#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
387#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
388#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
389#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
390#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
391#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
392#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
393#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
394#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
395#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
396#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
397#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
398#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
399#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
400
401
402/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
403#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
404#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
405#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
406#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
407#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
408#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
409#define bfin_read_EBIU_SDGCTL() bfin_read32(EBIU_SDGCTL)
410#define bfin_write_EBIU_SDGCTL(val) bfin_write32(EBIU_SDGCTL, val)
411#define bfin_read_EBIU_SDBCTL() bfin_read16(EBIU_SDBCTL)
412#define bfin_write_EBIU_SDBCTL(val) bfin_write16(EBIU_SDBCTL, val)
413#define bfin_read_EBIU_SDRRC() bfin_read16(EBIU_SDRRC)
414#define bfin_write_EBIU_SDRRC(val) bfin_write16(EBIU_SDRRC, val)
415#define bfin_read_EBIU_SDSTAT() bfin_read16(EBIU_SDSTAT)
416#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT, val)
417
418
419/* DMA Traffic Control Registers */
420#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
421#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
422#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
423#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
424
425/* Alternate deprecated register names (below) provided for backwards code compatibility */
426#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
427#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER, val)
428#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
429#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT, val)
430
431/* DMA Controller */
432#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
433#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
434#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
435#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
436#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
437#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
438#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
439#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
440#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
441#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
442#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
443#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
444#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
445#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
446#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
447#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
448#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
449#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
450#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
451#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
452#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
453#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
454#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
455#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
456#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
457#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
458
459#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
460#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
461#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
462#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
463#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
464#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
465#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
466#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
467#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
468#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
469#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
470#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
471#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
472#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
473#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
474#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
475#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
476#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
477#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
478#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
479#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
480#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
481#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
482#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
483#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
484#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
485
486#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
487#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
488#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
489#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
490#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
491#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
492#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
493#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
494#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
495#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
496#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
497#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
498#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
499#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
500#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
501#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
502#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
503#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
504#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
505#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
506#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
507#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
508#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
509#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
510#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
511#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
512
513#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
514#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
515#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
516#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
517#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
518#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
519#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
520#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
521#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
522#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
523#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
524#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
525#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
526#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
527#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
528#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
529#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
530#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
531#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
532#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
533#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
534#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
535#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
536#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
537#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
538#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
539
540#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
541#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
542#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
543#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
544#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
545#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
546#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
547#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
548#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
549#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
550#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
551#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
552#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
553#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
554#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
555#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
556#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
557#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
558#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
559#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
560#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
561#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
562#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
563#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
564#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
565#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
566
567#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
568#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
569#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
570#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
571#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
572#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
573#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
574#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
575#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
576#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
577#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
578#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
579#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
580#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
581#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
582#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
583#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
584#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
585#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
586#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
587#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
588#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
589#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
590#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
591#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
592#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
593
594#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
595#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
596#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
597#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
598#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
599#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
600#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
601#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
602#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
603#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
604#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
605#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
606#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
607#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
608#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
609#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
610#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
611#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
612#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
613#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
614#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
615#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
616#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
617#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
618#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
619#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
620
621#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
622#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
623#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
624#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
625#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
626#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
627#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
628#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
629#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
630#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
631#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
632#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
633#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
634#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
635#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
636#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
637#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
638#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
639#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
640#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
641#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
642#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
643#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
644#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
645#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
646#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
647
648#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
649#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
650#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
651#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR, val)
652#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
653#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR, val)
654#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
655#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
656#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
657#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
658#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
659#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
660#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
661#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
662#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
663#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR, val)
664#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
665#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR, val)
666#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
667#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
668#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
669#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
670#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
671#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
672#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
673#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
674
675#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
676#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
677#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
678#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR, val)
679#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
680#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR, val)
681#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
682#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
683#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
684#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
685#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
686#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
687#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
688#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
689#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
690#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR, val)
691#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
692#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR, val)
693#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
694#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
695#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
696#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
697#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
698#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
699#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
700#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
701
702#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
703#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
704#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
705#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR, val)
706#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
707#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR, val)
708#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
709#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
710#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
711#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
712#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
713#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
714#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
715#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
716#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
717#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR, val)
718#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
719#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR, val)
720#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
721#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
722#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
723#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
724#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
725#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
726#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
727#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
728
729#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
730#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
731#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
732#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR, val)
733#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
734#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR, val)
735#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
736#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
737#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
738#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
739#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
740#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
741#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
742#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
743#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
744#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR, val)
745#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
746#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR, val)
747#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
748#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
749#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
750#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
751#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
752#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
753#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
754#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
755
756#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
757#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
758#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
759#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
760#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
761#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
762#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
763#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
764#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
765#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
766#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
767#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
768#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
769#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
770#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
771#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
772#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
773#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
774#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
775#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
776#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
777#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
778#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
779#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
780#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
781#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
782
783#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
784#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
785#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
786#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
787#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
788#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
789#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
790#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
791#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
792#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
793#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
794#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
795#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
796#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
797#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
798#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
799#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
800#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
801#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
802#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
803#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
804#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
805#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
806#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
807#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
808#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
809
810#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
811#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
812#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
813#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
814#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
815#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
816#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
817#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
818#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
819#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
820#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
821#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
822#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
823#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
824#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
825#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
826#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
827#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
828#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
829#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
830#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
831#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
832#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
833#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
834#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
835#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
836
837#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
838#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
839#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
840#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
841#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
842#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
843#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
844#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
845#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
846#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
847#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
848#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
849#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
850#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
851#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
852#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
853#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
854#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
855#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
856#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
857#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
858#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
859#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
860#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
861#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
862#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
863
864
865/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
866#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
867#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
868#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
869#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
870#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
871#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
872#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
873#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
874#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
875#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
876
877
878/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
879#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
880#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
881#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
882#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
883#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
884#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
885#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
886#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
887#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
888#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
889#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
890#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
891#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
892#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
893#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
894#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
895#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
896#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
897#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
898#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
899#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
900#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
901#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
902#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
903#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
904#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
905#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
906#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
907#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
908#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
909#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
910#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
911
912
913/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
914#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
915#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
916#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
917#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
918#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
919#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
920#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
921#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
922#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
923#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
924#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
925#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
926#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
927#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
928#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
929#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
930#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
931#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
932#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
933#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
934#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
935#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
936#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
937#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
938#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
939#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
940#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
941#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
942#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
943#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
944#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
945#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
946#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
947#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
948
949
950/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
951#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
952#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
953#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
954#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
955#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
956#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
957#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
958#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
959#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
960#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
961#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
962#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
963#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
964#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
965#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
966#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
967#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
968#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
969#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
970#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
971#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
972#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
973#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
974#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
975#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
976#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
977#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
978#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
979#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
980#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
981#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
982#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
983#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
984#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
985
986
987/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
988#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
989#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
990#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
991#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
992#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
993#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
994#define bfin_read_UART1_IER() bfin_read16(UART1_IER)
995#define bfin_write_UART1_IER(val) bfin_write16(UART1_IER, val)
996#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
997#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
998#define bfin_read_UART1_IIR() bfin_read16(UART1_IIR)
999#define bfin_write_UART1_IIR(val) bfin_write16(UART1_IIR, val)
1000#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1001#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1002#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1003#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1004#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1005#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1006#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1007#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1008#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1009#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1010#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1011#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1012
1013/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
1014
1015/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
1016#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1017#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1018#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1019#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1020#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1021#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1022#define bfin_read_PORT_MUX() bfin_read16(PORT_MUX)
1023#define bfin_write_PORT_MUX(val) bfin_write16(PORT_MUX, val)
1024
1025
1026/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
1027#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1028#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1029#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1030#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1031#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1032#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1033#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1034#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1035#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1036#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1037#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1038#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1039#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1040#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1041
1042#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1043#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1044#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1045#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1046#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1047#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1048#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1049#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1050#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1051#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1052#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1053#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1054#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1055#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1056
1057/* ==== end from cdefBF534.h ==== */
1058
1059/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
1060
1061#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
1062#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
1063#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
1064#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
1065#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
1066#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
1067
1068#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
1069#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
1070#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
1071#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
1072#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
1073#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
1074#define bfin_read_PORTF_SLEW() bfin_read16(PORTF_SLEW)
1075#define bfin_write_PORTF_SLEW(val) bfin_write16(PORTF_SLEW, val)
1076#define bfin_read_PORTG_SLEW() bfin_read16(PORTG_SLEW)
1077#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
1078#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
1079#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
1080#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
1081#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
1082#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
1083#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
1084#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
1085#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
1086#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
1087#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
1088#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
1089#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
1090#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
1091#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
1092
1093/* HOST Port Registers */
1094
1095#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1096#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1097#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1098#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1099#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1100#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1101
1102/* Counter Registers */
1103
1104#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
1105#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
1106#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
1107#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
1108#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
1109#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
1110#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
1111#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
1112#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
1113#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
1114#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
1115#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
1116#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
1117#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
1118#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
1119#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
1120
1121/* OTP/FUSE Registers */
1122
1123#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
1124#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
1125#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
1126#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
1127#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
1128#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
1129#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
1130#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
1131
1132/* Security Registers */
1133
1134#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
1135#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
1136#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
1137#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
1138#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
1139#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
1140
1141/* OTP Read/Write Data Buffer Registers */
1142
1143#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
1144#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
1145#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
1146#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
1147#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
1148#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
1149#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
1150#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
1151
1152/* NFC Registers */
1153
1154#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
1155#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
1156#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
1157#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
1158#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
1159#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
1160#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
1161#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
1162#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
1163#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
1164#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
1165#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
1166#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
1167#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
1168#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
1169#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
1170#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
1171#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
1172#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
1173#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
1174#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
1175#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
1176#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
1177#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
1178#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
1179#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
1180#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
1181#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
1182#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
1183#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
1184#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
1185#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
1186
1187#endif /* _CDEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF522.h b/include/asm-blackfin/mach-bf527/defBF522.h
new file mode 100644
index 000000000000..9671d8f2c5ef
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF522.h
@@ -0,0 +1,42 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF522.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF522_H
32#define _DEF_BF522_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42#endif /* _DEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF525.h b/include/asm-blackfin/mach-bf527/defBF525.h
new file mode 100644
index 000000000000..6a375a084acc
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF525.h
@@ -0,0 +1,713 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF525.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF525_H
32#define _DEF_BF525_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include "defBF52x_base.h"
41
42/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
43
44/* USB Control Registers */
45
46#define USB_FADDR 0xffc03800 /* Function address register */
47#define USB_POWER 0xffc03804 /* Power management register */
48#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
49#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
50#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
51#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
52#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
53#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
54#define USB_FRAME 0xffc03820 /* USB frame number */
55#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
56#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
57#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
58#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
59
60/* USB Packet Control Registers */
61
62#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
63#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
64#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
65#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
66#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
67#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
68#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
69#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
70#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
71#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
72#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
73#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
74#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
75
76/* USB Endpoint FIFO Registers */
77
78#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
79#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
80#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
81#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
82#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
83#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
84#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
85#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
86
87/* USB OTG Control Registers */
88
89#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
90#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
91#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
92
93/* USB Phy Control Registers */
94
95#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
96#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
97#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
98#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
99#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
100
101/* (APHY_CNTRL is for ADI usage only) */
102
103#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
104
105/* (APHY_CALIB is for ADI usage only) */
106
107#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
108
109#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
110
111/* (PHY_TEST is for ADI usage only) */
112
113#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
114
115#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
116#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
117
118/* USB Endpoint 0 Control Registers */
119
120#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
121#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
122#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
123#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
124#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
125#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
126#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
127#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
128#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
129#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
130
131/* USB Endpoint 1 Control Registers */
132
133#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
134#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
135#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
136#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
137#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
138#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
139#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
140#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
141#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
142#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
143
144/* USB Endpoint 2 Control Registers */
145
146#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
147#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
148#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
149#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
150#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
151#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
152#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
153#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
154#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
155#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
156
157/* USB Endpoint 3 Control Registers */
158
159#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
160#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
161#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
162#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
163#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
164#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
165#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
166#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
167#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
168#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
169
170/* USB Endpoint 4 Control Registers */
171
172#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
173#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
174#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
175#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
176#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
177#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
178#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
179#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
180#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
181#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
182
183/* USB Endpoint 5 Control Registers */
184
185#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
186#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
187#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
188#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
189#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
190#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
191#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
192#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
193#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
194#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
195
196/* USB Endpoint 6 Control Registers */
197
198#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
199#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
200#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
201#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
202#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
203#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
204#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
205#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
206#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
207#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
208
209/* USB Endpoint 7 Control Registers */
210
211#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
212#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
213#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
214#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
215#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
216#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
217#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
218#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
219#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
220#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
221
222#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
223
224/* USB Channel 0 Config Registers */
225
226#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
227#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
228#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
229#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
230#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
231
232/* USB Channel 1 Config Registers */
233
234#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
235#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
236#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
237#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
238#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
239
240/* USB Channel 2 Config Registers */
241
242#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
243#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
244#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
245#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
246#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
247
248/* USB Channel 3 Config Registers */
249
250#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
251#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
252#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
253#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
254#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
255
256/* USB Channel 4 Config Registers */
257
258#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
259#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
260#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
261#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
262#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
263
264/* USB Channel 5 Config Registers */
265
266#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
267#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
268#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
269#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
270#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
271
272/* USB Channel 6 Config Registers */
273
274#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
275#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
276#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
277#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
278#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
279
280/* USB Channel 7 Config Registers */
281
282#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
283#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
284#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
285#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
286#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
287
288/* Bit masks for USB_FADDR */
289
290#define FUNCTION_ADDRESS 0x7f /* Function address */
291
292/* Bit masks for USB_POWER */
293
294#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
295#define nENABLE_SUSPENDM 0x0
296#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
297#define nSUSPEND_MODE 0x0
298#define RESUME_MODE 0x4 /* DMA Mode */
299#define nRESUME_MODE 0x0
300#define RESET 0x8 /* Reset indicator */
301#define nRESET 0x0
302#define HS_MODE 0x10 /* High Speed mode indicator */
303#define nHS_MODE 0x0
304#define HS_ENABLE 0x20 /* high Speed Enable */
305#define nHS_ENABLE 0x0
306#define SOFT_CONN 0x40 /* Soft connect */
307#define nSOFT_CONN 0x0
308#define ISO_UPDATE 0x80 /* Isochronous update */
309#define nISO_UPDATE 0x0
310
311/* Bit masks for USB_INTRTX */
312
313#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
314#define nEP0_TX 0x0
315#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
316#define nEP1_TX 0x0
317#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
318#define nEP2_TX 0x0
319#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
320#define nEP3_TX 0x0
321#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
322#define nEP4_TX 0x0
323#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
324#define nEP5_TX 0x0
325#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
326#define nEP6_TX 0x0
327#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
328#define nEP7_TX 0x0
329
330/* Bit masks for USB_INTRRX */
331
332#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
333#define nEP1_RX 0x0
334#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
335#define nEP2_RX 0x0
336#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
337#define nEP3_RX 0x0
338#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
339#define nEP4_RX 0x0
340#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
341#define nEP5_RX 0x0
342#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
343#define nEP6_RX 0x0
344#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
345#define nEP7_RX 0x0
346
347/* Bit masks for USB_INTRTXE */
348
349#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
350#define nEP0_TX_E 0x0
351#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
352#define nEP1_TX_E 0x0
353#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
354#define nEP2_TX_E 0x0
355#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
356#define nEP3_TX_E 0x0
357#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
358#define nEP4_TX_E 0x0
359#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
360#define nEP5_TX_E 0x0
361#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
362#define nEP6_TX_E 0x0
363#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
364#define nEP7_TX_E 0x0
365
366/* Bit masks for USB_INTRRXE */
367
368#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
369#define nEP1_RX_E 0x0
370#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
371#define nEP2_RX_E 0x0
372#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
373#define nEP3_RX_E 0x0
374#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
375#define nEP4_RX_E 0x0
376#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
377#define nEP5_RX_E 0x0
378#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
379#define nEP6_RX_E 0x0
380#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
381#define nEP7_RX_E 0x0
382
383/* Bit masks for USB_INTRUSB */
384
385#define SUSPEND_B 0x1 /* Suspend indicator */
386#define nSUSPEND_B 0x0
387#define RESUME_B 0x2 /* Resume indicator */
388#define nRESUME_B 0x0
389#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
390#define nRESET_OR_BABLE_B 0x0
391#define SOF_B 0x8 /* Start of frame */
392#define nSOF_B 0x0
393#define CONN_B 0x10 /* Connection indicator */
394#define nCONN_B 0x0
395#define DISCON_B 0x20 /* Disconnect indicator */
396#define nDISCON_B 0x0
397#define SESSION_REQ_B 0x40 /* Session Request */
398#define nSESSION_REQ_B 0x0
399#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
400#define nVBUS_ERROR_B 0x0
401
402/* Bit masks for USB_INTRUSBE */
403
404#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
405#define nSUSPEND_BE 0x0
406#define RESUME_BE 0x2 /* Resume indicator int enable */
407#define nRESUME_BE 0x0
408#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
409#define nRESET_OR_BABLE_BE 0x0
410#define SOF_BE 0x8 /* Start of frame int enable */
411#define nSOF_BE 0x0
412#define CONN_BE 0x10 /* Connection indicator int enable */
413#define nCONN_BE 0x0
414#define DISCON_BE 0x20 /* Disconnect indicator int enable */
415#define nDISCON_BE 0x0
416#define SESSION_REQ_BE 0x40 /* Session Request int enable */
417#define nSESSION_REQ_BE 0x0
418#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
419#define nVBUS_ERROR_BE 0x0
420
421/* Bit masks for USB_FRAME */
422
423#define FRAME_NUMBER 0x7ff /* Frame number */
424
425/* Bit masks for USB_INDEX */
426
427#define SELECTED_ENDPOINT 0xf /* selected endpoint */
428
429/* Bit masks for USB_GLOBAL_CTL */
430
431#define GLOBAL_ENA 0x1 /* enables USB module */
432#define nGLOBAL_ENA 0x0
433#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
434#define nEP1_TX_ENA 0x0
435#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
436#define nEP2_TX_ENA 0x0
437#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
438#define nEP3_TX_ENA 0x0
439#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
440#define nEP4_TX_ENA 0x0
441#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
442#define nEP5_TX_ENA 0x0
443#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
444#define nEP6_TX_ENA 0x0
445#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
446#define nEP7_TX_ENA 0x0
447#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
448#define nEP1_RX_ENA 0x0
449#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
450#define nEP2_RX_ENA 0x0
451#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
452#define nEP3_RX_ENA 0x0
453#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
454#define nEP4_RX_ENA 0x0
455#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
456#define nEP5_RX_ENA 0x0
457#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
458#define nEP6_RX_ENA 0x0
459#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
460#define nEP7_RX_ENA 0x0
461
462/* Bit masks for USB_OTG_DEV_CTL */
463
464#define SESSION 0x1 /* session indicator */
465#define nSESSION 0x0
466#define HOST_REQ 0x2 /* Host negotiation request */
467#define nHOST_REQ 0x0
468#define HOST_MODE 0x4 /* indicates USBDRC is a host */
469#define nHOST_MODE 0x0
470#define VBUS0 0x8 /* Vbus level indicator[0] */
471#define nVBUS0 0x0
472#define VBUS1 0x10 /* Vbus level indicator[1] */
473#define nVBUS1 0x0
474#define LSDEV 0x20 /* Low-speed indicator */
475#define nLSDEV 0x0
476#define FSDEV 0x40 /* Full or High-speed indicator */
477#define nFSDEV 0x0
478#define B_DEVICE 0x80 /* A' or 'B' device indicator */
479#define nB_DEVICE 0x0
480
481/* Bit masks for USB_OTG_VBUS_IRQ */
482
483#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
484#define nDRIVE_VBUS_ON 0x0
485#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
486#define nDRIVE_VBUS_OFF 0x0
487#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
488#define nCHRG_VBUS_START 0x0
489#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
490#define nCHRG_VBUS_END 0x0
491#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
492#define nDISCHRG_VBUS_START 0x0
493#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
494#define nDISCHRG_VBUS_END 0x0
495
496/* Bit masks for USB_OTG_VBUS_MASK */
497
498#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
499#define nDRIVE_VBUS_ON_ENA 0x0
500#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
501#define nDRIVE_VBUS_OFF_ENA 0x0
502#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
503#define nCHRG_VBUS_START_ENA 0x0
504#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
505#define nCHRG_VBUS_END_ENA 0x0
506#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
507#define nDISCHRG_VBUS_START_ENA 0x0
508#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
509#define nDISCHRG_VBUS_END_ENA 0x0
510
511/* Bit masks for USB_CSR0 */
512
513#define RXPKTRDY 0x1 /* data packet receive indicator */
514#define nRXPKTRDY 0x0
515#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
516#define nTXPKTRDY 0x0
517#define STALL_SENT 0x4 /* STALL handshake sent */
518#define nSTALL_SENT 0x0
519#define DATAEND 0x8 /* Data end indicator */
520#define nDATAEND 0x0
521#define SETUPEND 0x10 /* Setup end */
522#define nSETUPEND 0x0
523#define SENDSTALL 0x20 /* Send STALL handshake */
524#define nSENDSTALL 0x0
525#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
526#define nSERVICED_RXPKTRDY 0x0
527#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
528#define nSERVICED_SETUPEND 0x0
529#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
530#define nFLUSHFIFO 0x0
531#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
532#define nSTALL_RECEIVED_H 0x0
533#define SETUPPKT_H 0x8 /* send Setup token host mode */
534#define nSETUPPKT_H 0x0
535#define ERROR_H 0x10 /* timeout error indicator host mode */
536#define nERROR_H 0x0
537#define REQPKT_H 0x20 /* Request an IN transaction host mode */
538#define nREQPKT_H 0x0
539#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
540#define nSTATUSPKT_H 0x0
541#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
542#define nNAK_TIMEOUT_H 0x0
543
544/* Bit masks for USB_COUNT0 */
545
546#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
547
548/* Bit masks for USB_NAKLIMIT0 */
549
550#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
551
552/* Bit masks for USB_TX_MAX_PACKET */
553
554#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
555
556/* Bit masks for USB_RX_MAX_PACKET */
557
558#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
559
560/* Bit masks for USB_TXCSR */
561
562#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
563#define nTXPKTRDY_T 0x0
564#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
565#define nFIFO_NOT_EMPTY_T 0x0
566#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
567#define nUNDERRUN_T 0x0
568#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
569#define nFLUSHFIFO_T 0x0
570#define STALL_SEND_T 0x10 /* issue a Stall handshake */
571#define nSTALL_SEND_T 0x0
572#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
573#define nSTALL_SENT_T 0x0
574#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
575#define nCLEAR_DATATOGGLE_T 0x0
576#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
577#define nINCOMPTX_T 0x0
578#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
579#define nDMAREQMODE_T 0x0
580#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
581#define nFORCE_DATATOGGLE_T 0x0
582#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
583#define nDMAREQ_ENA_T 0x0
584#define ISO_T 0x4000 /* enable Isochronous transfers */
585#define nISO_T 0x0
586#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
587#define nAUTOSET_T 0x0
588#define ERROR_TH 0x4 /* error condition host mode */
589#define nERROR_TH 0x0
590#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
591#define nSTALL_RECEIVED_TH 0x0
592#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
593#define nNAK_TIMEOUT_TH 0x0
594
595/* Bit masks for USB_TXCOUNT */
596
597#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
598
599/* Bit masks for USB_RXCSR */
600
601#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
602#define nRXPKTRDY_R 0x0
603#define FIFO_FULL_R 0x2 /* FIFO not empty */
604#define nFIFO_FULL_R 0x0
605#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
606#define nOVERRUN_R 0x0
607#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
608#define nDATAERROR_R 0x0
609#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
610#define nFLUSHFIFO_R 0x0
611#define STALL_SEND_R 0x20 /* issue a Stall handshake */
612#define nSTALL_SEND_R 0x0
613#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
614#define nSTALL_SENT_R 0x0
615#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
616#define nCLEAR_DATATOGGLE_R 0x0
617#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
618#define nINCOMPRX_R 0x0
619#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
620#define nDMAREQMODE_R 0x0
621#define DISNYET_R 0x1000 /* disable Nyet handshakes */
622#define nDISNYET_R 0x0
623#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
624#define nDMAREQ_ENA_R 0x0
625#define ISO_R 0x4000 /* enable Isochronous transfers */
626#define nISO_R 0x0
627#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
628#define nAUTOCLEAR_R 0x0
629#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
630#define nERROR_RH 0x0
631#define REQPKT_RH 0x20 /* request an IN transaction host mode */
632#define nREQPKT_RH 0x0
633#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
634#define nSTALL_RECEIVED_RH 0x0
635#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
636#define nINCOMPRX_RH 0x0
637#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
638#define nDMAREQMODE_RH 0x0
639#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
640#define nAUTOREQ_RH 0x0
641
642/* Bit masks for USB_RXCOUNT */
643
644#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
645
646/* Bit masks for USB_TXTYPE */
647
648#define TARGET_EP_NO_T 0xf /* EP number */
649#define PROTOCOL_T 0xc /* transfer type */
650
651/* Bit masks for USB_TXINTERVAL */
652
653#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
654
655/* Bit masks for USB_RXTYPE */
656
657#define TARGET_EP_NO_R 0xf /* EP number */
658#define PROTOCOL_R 0xc /* transfer type */
659
660/* Bit masks for USB_RXINTERVAL */
661
662#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
663
664/* Bit masks for USB_DMA_INTERRUPT */
665
666#define DMA0_INT 0x1 /* DMA0 pending interrupt */
667#define nDMA0_INT 0x0
668#define DMA1_INT 0x2 /* DMA1 pending interrupt */
669#define nDMA1_INT 0x0
670#define DMA2_INT 0x4 /* DMA2 pending interrupt */
671#define nDMA2_INT 0x0
672#define DMA3_INT 0x8 /* DMA3 pending interrupt */
673#define nDMA3_INT 0x0
674#define DMA4_INT 0x10 /* DMA4 pending interrupt */
675#define nDMA4_INT 0x0
676#define DMA5_INT 0x20 /* DMA5 pending interrupt */
677#define nDMA5_INT 0x0
678#define DMA6_INT 0x40 /* DMA6 pending interrupt */
679#define nDMA6_INT 0x0
680#define DMA7_INT 0x80 /* DMA7 pending interrupt */
681#define nDMA7_INT 0x0
682
683/* Bit masks for USB_DMAxCONTROL */
684
685#define DMA_ENA 0x1 /* DMA enable */
686#define nDMA_ENA 0x0
687#define DIRECTION 0x2 /* direction of DMA transfer */
688#define nDIRECTION 0x0
689#define MODE 0x4 /* DMA Bus error */
690#define nMODE 0x0
691#define INT_ENA 0x8 /* Interrupt enable */
692#define nINT_ENA 0x0
693#define EPNUM 0xf0 /* EP number */
694#define BUSERROR 0x100 /* DMA Bus error */
695#define nBUSERROR 0x0
696
697/* Bit masks for USB_DMAxADDRHIGH */
698
699#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
700
701/* Bit masks for USB_DMAxADDRLOW */
702
703#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
704
705/* Bit masks for USB_DMAxCOUNTHIGH */
706
707#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
708
709/* Bit masks for USB_DMAxCOUNTLOW */
710
711#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
712
713#endif /* _DEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
new file mode 100644
index 000000000000..2be3293f9e26
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF527.h
@@ -0,0 +1,1089 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF527.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF527_H
32#define _DEF_BF527_H
33
34/* Include all Core registers and bit definitions */
35#include <def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
38
39/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
40#include <defBF52x_base.h>
41
42/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
43/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
44
45#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
46#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
47#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
48#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
49#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
50#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
51#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
52#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
53#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
54#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
55#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
56#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
57#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
58#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
59#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
60#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
61#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
62#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
63#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
64
65#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
66#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
67#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
68#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
69#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
70#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
71#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
72#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
73
74#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
75#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
76#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
77#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
78#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
79
80#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
81#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
82#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
83#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
84#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
85#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
86#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
87#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
88#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
89#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
90#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
91#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
92#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
93#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
94#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
95#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
96#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
97#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
98#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
99#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
100#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
101#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
102#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
103#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
104
105#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
106#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
107#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
108#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
109#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
110#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
111#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
112#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
113#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
114#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
115#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
116#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
117#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
118#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
119#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
120#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
121#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
122#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
123#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
124#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
125#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
126#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
127#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
128
129/* Listing for IEEE-Supported Count Registers */
130
131#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
132#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
133#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
134#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
135#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
136#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
137#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
138#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
139#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
140#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
141#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
142#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
143#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
144#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
145#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
146#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
147#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
148#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
149#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
150#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
151#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
152#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
153#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
154#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
155
156#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
157#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
158#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
159#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
160#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
161#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
162#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
163#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
164#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
165#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
166#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
167#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
168#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
169#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
170#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
171#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
172#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
173#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
174#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
175#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
176#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
177#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
178#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
179
180/***********************************************************************************
181** System MMR Register Bits And Macros
182**
183** Disclaimer: All macros are intended to make C and Assembly code more readable.
184** Use these macros carefully, as any that do left shifts for field
185** depositing will result in the lower order bits being destroyed. Any
186** macro that shifts left to properly position the bit-field should be
187** used as part of an OR to initialize a register and NOT as a dynamic
188** modifier UNLESS the lower order bits are saved and ORed back in when
189** the macro is used.
190*************************************************************************************/
191
192/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
193
194/* EMAC_OPMODE Masks */
195
196#define RE 0x00000001 /* Receiver Enable */
197#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
198#define HU 0x00000010 /* Hash Filter Unicast Address */
199#define HM 0x00000020 /* Hash Filter Multicast Address */
200#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
201#define PR 0x00000080 /* Promiscuous Mode Enable */
202#define IFE 0x00000100 /* Inverse Filtering Enable */
203#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
204#define PBF 0x00000400 /* Pass Bad Frames Enable */
205#define PSF 0x00000800 /* Pass Short Frames Enable */
206#define RAF 0x00001000 /* Receive-All Mode */
207#define TE 0x00010000 /* Transmitter Enable */
208#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
209#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
210#define DC 0x00080000 /* Deferral Check */
211#define BOLMT 0x00300000 /* Back-Off Limit */
212#define BOLMT_10 0x00000000 /* 10-bit range */
213#define BOLMT_8 0x00100000 /* 8-bit range */
214#define BOLMT_4 0x00200000 /* 4-bit range */
215#define BOLMT_1 0x00300000 /* 1-bit range */
216#define DRTY 0x00400000 /* Disable TX Retry On Collision */
217#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
218#define RMII 0x01000000 /* RMII/MII* Mode */
219#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
220#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
221#define LB 0x08000000 /* Internal Loopback Enable */
222#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
223
224/* EMAC_STAADD Masks */
225
226#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
227#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
228#define STADISPRE 0x00000004 /* Disable Preamble Generation */
229#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
230#define REGAD 0x000007C0 /* STA Register Address */
231#define PHYAD 0x0000F800 /* PHY Device Address */
232
233#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
234#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
235
236/* EMAC_STADAT Mask */
237
238#define STADATA 0x0000FFFF /* Station Management Data */
239
240/* EMAC_FLC Masks */
241
242#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
243#define FLCE 0x00000002 /* Flow Control Enable */
244#define PCF 0x00000004 /* Pass Control Frames */
245#define BKPRSEN 0x00000008 /* Enable Backpressure */
246#define FLCPAUSE 0xFFFF0000 /* Pause Time */
247
248#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
249
250/* EMAC_WKUP_CTL Masks */
251
252#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
253#define MPKE 0x00000002 /* Magic Packet Enable */
254#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
255#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
256#define MPKS 0x00000020 /* Magic Packet Received Status */
257#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
258
259/* EMAC_WKUP_FFCMD Masks */
260
261#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
262#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
263#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
264#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
265#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
266#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
267#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
268#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
269
270/* EMAC_WKUP_FFOFF Masks */
271
272#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
273#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
274#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
275#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
276
277#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
278#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
279#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
280#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
281/* Set ALL Offsets */
282#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
283
284/* EMAC_WKUP_FFCRC0 Masks */
285
286#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
287#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
288
289#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
290#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
291
292/* EMAC_WKUP_FFCRC1 Masks */
293
294#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
295#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
296
297#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
298#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
299
300/* EMAC_SYSCTL Masks */
301
302#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
303#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
304#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
305#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
306
307#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
308
309/* EMAC_SYSTAT Masks */
310
311#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
312#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
313#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
314#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
315#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
316#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
317#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
318#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
319
320/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
321
322#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
323#define RX_COMP 0x00001000 /* RX Frame Complete */
324#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
325#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
326#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
327#define RX_CRC 0x00010000 /* RX Frame CRC Error */
328#define RX_LEN 0x00020000 /* RX Frame Length Error */
329#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
330#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
331#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
332#define RX_PHY 0x00200000 /* RX Frame PHY Error */
333#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
334#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
335#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
336#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
337#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
338#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
339#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
340#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
341#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
342#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
343
344/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
345
346#define TX_COMP 0x00000001 /* TX Frame Complete */
347#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
348#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
349#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
350#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
351#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
352#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
353#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
354#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
355#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
356#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
357#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
358#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
359#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
360#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
361
362/* EMAC_MMC_CTL Masks */
363#define RSTC 0x00000001 /* Reset All Counters */
364#define CROLL 0x00000002 /* Counter Roll-Over Enable */
365#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
366#define MMCE 0x00000008 /* Enable MMC Counter Operation */
367
368/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
369#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
370#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
371#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
372#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
373#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
374#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
375#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
376#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
377#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
378#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
379#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
380#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
381#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
382#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
383#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
384#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
385#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
386#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
387#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
388#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
389#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
390#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
391#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
392#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
393
394/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
395
396#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
397#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
398#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
399#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
400#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
401#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
402#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
403#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
404#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
405#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
406#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
407#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
408#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
409#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
410#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
411#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
412#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
413#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
414#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
415#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
416#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
417#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
418#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
419
420/* USB Control Registers */
421
422#define USB_FADDR 0xffc03800 /* Function address register */
423#define USB_POWER 0xffc03804 /* Power management register */
424#define USB_INTRTX 0xffc03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
425#define USB_INTRRX 0xffc0380c /* Interrupt register for Rx endpoints 1 to 7 */
426#define USB_INTRTXE 0xffc03810 /* Interrupt enable register for IntrTx */
427#define USB_INTRRXE 0xffc03814 /* Interrupt enable register for IntrRx */
428#define USB_INTRUSB 0xffc03818 /* Interrupt register for common USB interrupts */
429#define USB_INTRUSBE 0xffc0381c /* Interrupt enable register for IntrUSB */
430#define USB_FRAME 0xffc03820 /* USB frame number */
431#define USB_INDEX 0xffc03824 /* Index register for selecting the indexed endpoint registers */
432#define USB_TESTMODE 0xffc03828 /* Enabled USB 20 test modes */
433#define USB_GLOBINTR 0xffc0382c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
434#define USB_GLOBAL_CTL 0xffc03830 /* Global Clock Control for the core */
435
436/* USB Packet Control Registers */
437
438#define USB_TX_MAX_PACKET 0xffc03840 /* Maximum packet size for Host Tx endpoint */
439#define USB_CSR0 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
440#define USB_TXCSR 0xffc03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
441#define USB_RX_MAX_PACKET 0xffc03848 /* Maximum packet size for Host Rx endpoint */
442#define USB_RXCSR 0xffc0384c /* Control Status register for Host Rx endpoint */
443#define USB_COUNT0 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
444#define USB_RXCOUNT 0xffc03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
445#define USB_TXTYPE 0xffc03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
446#define USB_NAKLIMIT0 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
447#define USB_TXINTERVAL 0xffc03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
448#define USB_RXTYPE 0xffc0385c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
449#define USB_RXINTERVAL 0xffc03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
450#define USB_TXCOUNT 0xffc03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
451
452/* USB Endpoint FIFO Registers */
453
454#define USB_EP0_FIFO 0xffc03880 /* Endpoint 0 FIFO */
455#define USB_EP1_FIFO 0xffc03888 /* Endpoint 1 FIFO */
456#define USB_EP2_FIFO 0xffc03890 /* Endpoint 2 FIFO */
457#define USB_EP3_FIFO 0xffc03898 /* Endpoint 3 FIFO */
458#define USB_EP4_FIFO 0xffc038a0 /* Endpoint 4 FIFO */
459#define USB_EP5_FIFO 0xffc038a8 /* Endpoint 5 FIFO */
460#define USB_EP6_FIFO 0xffc038b0 /* Endpoint 6 FIFO */
461#define USB_EP7_FIFO 0xffc038b8 /* Endpoint 7 FIFO */
462
463/* USB OTG Control Registers */
464
465#define USB_OTG_DEV_CTL 0xffc03900 /* OTG Device Control Register */
466#define USB_OTG_VBUS_IRQ 0xffc03904 /* OTG VBUS Control Interrupts */
467#define USB_OTG_VBUS_MASK 0xffc03908 /* VBUS Control Interrupt Enable */
468
469/* USB Phy Control Registers */
470
471#define USB_LINKINFO 0xffc03948 /* Enables programming of some PHY-side delays */
472#define USB_VPLEN 0xffc0394c /* Determines duration of VBUS pulse for VBUS charging */
473#define USB_HS_EOF1 0xffc03950 /* Time buffer for High-Speed transactions */
474#define USB_FS_EOF1 0xffc03954 /* Time buffer for Full-Speed transactions */
475#define USB_LS_EOF1 0xffc03958 /* Time buffer for Low-Speed transactions */
476
477/* (APHY_CNTRL is for ADI usage only) */
478
479#define USB_APHY_CNTRL 0xffc039e0 /* Register that increases visibility of Analog PHY */
480
481/* (APHY_CALIB is for ADI usage only) */
482
483#define USB_APHY_CALIB 0xffc039e4 /* Register used to set some calibration values */
484
485#define USB_APHY_CNTRL2 0xffc039e8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
486
487/* (PHY_TEST is for ADI usage only) */
488
489#define USB_PHY_TEST 0xffc039ec /* Used for reducing simulation time and simplifies FIFO testability */
490
491#define USB_PLLOSC_CTRL 0xffc039f0 /* Used to program different parameters for USB PLL and Oscillator */
492#define USB_SRP_CLKDIV 0xffc039f4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
493
494/* USB Endpoint 0 Control Registers */
495
496#define USB_EP_NI0_TXMAXP 0xffc03a00 /* Maximum packet size for Host Tx endpoint0 */
497#define USB_EP_NI0_TXCSR 0xffc03a04 /* Control Status register for endpoint 0 */
498#define USB_EP_NI0_RXMAXP 0xffc03a08 /* Maximum packet size for Host Rx endpoint0 */
499#define USB_EP_NI0_RXCSR 0xffc03a0c /* Control Status register for Host Rx endpoint0 */
500#define USB_EP_NI0_RXCOUNT 0xffc03a10 /* Number of bytes received in endpoint 0 FIFO */
501#define USB_EP_NI0_TXTYPE 0xffc03a14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
502#define USB_EP_NI0_TXINTERVAL 0xffc03a18 /* Sets the NAK response timeout on Endpoint 0 */
503#define USB_EP_NI0_RXTYPE 0xffc03a1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
504#define USB_EP_NI0_RXINTERVAL 0xffc03a20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
505#define USB_EP_NI0_TXCOUNT 0xffc03a28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
506
507/* USB Endpoint 1 Control Registers */
508
509#define USB_EP_NI1_TXMAXP 0xffc03a40 /* Maximum packet size for Host Tx endpoint1 */
510#define USB_EP_NI1_TXCSR 0xffc03a44 /* Control Status register for endpoint1 */
511#define USB_EP_NI1_RXMAXP 0xffc03a48 /* Maximum packet size for Host Rx endpoint1 */
512#define USB_EP_NI1_RXCSR 0xffc03a4c /* Control Status register for Host Rx endpoint1 */
513#define USB_EP_NI1_RXCOUNT 0xffc03a50 /* Number of bytes received in endpoint1 FIFO */
514#define USB_EP_NI1_TXTYPE 0xffc03a54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
515#define USB_EP_NI1_TXINTERVAL 0xffc03a58 /* Sets the NAK response timeout on Endpoint1 */
516#define USB_EP_NI1_RXTYPE 0xffc03a5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
517#define USB_EP_NI1_RXINTERVAL 0xffc03a60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
518#define USB_EP_NI1_TXCOUNT 0xffc03a68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
519
520/* USB Endpoint 2 Control Registers */
521
522#define USB_EP_NI2_TXMAXP 0xffc03a80 /* Maximum packet size for Host Tx endpoint2 */
523#define USB_EP_NI2_TXCSR 0xffc03a84 /* Control Status register for endpoint2 */
524#define USB_EP_NI2_RXMAXP 0xffc03a88 /* Maximum packet size for Host Rx endpoint2 */
525#define USB_EP_NI2_RXCSR 0xffc03a8c /* Control Status register for Host Rx endpoint2 */
526#define USB_EP_NI2_RXCOUNT 0xffc03a90 /* Number of bytes received in endpoint2 FIFO */
527#define USB_EP_NI2_TXTYPE 0xffc03a94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
528#define USB_EP_NI2_TXINTERVAL 0xffc03a98 /* Sets the NAK response timeout on Endpoint2 */
529#define USB_EP_NI2_RXTYPE 0xffc03a9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
530#define USB_EP_NI2_RXINTERVAL 0xffc03aa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
531#define USB_EP_NI2_TXCOUNT 0xffc03aa8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
532
533/* USB Endpoint 3 Control Registers */
534
535#define USB_EP_NI3_TXMAXP 0xffc03ac0 /* Maximum packet size for Host Tx endpoint3 */
536#define USB_EP_NI3_TXCSR 0xffc03ac4 /* Control Status register for endpoint3 */
537#define USB_EP_NI3_RXMAXP 0xffc03ac8 /* Maximum packet size for Host Rx endpoint3 */
538#define USB_EP_NI3_RXCSR 0xffc03acc /* Control Status register for Host Rx endpoint3 */
539#define USB_EP_NI3_RXCOUNT 0xffc03ad0 /* Number of bytes received in endpoint3 FIFO */
540#define USB_EP_NI3_TXTYPE 0xffc03ad4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
541#define USB_EP_NI3_TXINTERVAL 0xffc03ad8 /* Sets the NAK response timeout on Endpoint3 */
542#define USB_EP_NI3_RXTYPE 0xffc03adc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
543#define USB_EP_NI3_RXINTERVAL 0xffc03ae0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
544#define USB_EP_NI3_TXCOUNT 0xffc03ae8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
545
546/* USB Endpoint 4 Control Registers */
547
548#define USB_EP_NI4_TXMAXP 0xffc03b00 /* Maximum packet size for Host Tx endpoint4 */
549#define USB_EP_NI4_TXCSR 0xffc03b04 /* Control Status register for endpoint4 */
550#define USB_EP_NI4_RXMAXP 0xffc03b08 /* Maximum packet size for Host Rx endpoint4 */
551#define USB_EP_NI4_RXCSR 0xffc03b0c /* Control Status register for Host Rx endpoint4 */
552#define USB_EP_NI4_RXCOUNT 0xffc03b10 /* Number of bytes received in endpoint4 FIFO */
553#define USB_EP_NI4_TXTYPE 0xffc03b14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
554#define USB_EP_NI4_TXINTERVAL 0xffc03b18 /* Sets the NAK response timeout on Endpoint4 */
555#define USB_EP_NI4_RXTYPE 0xffc03b1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
556#define USB_EP_NI4_RXINTERVAL 0xffc03b20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
557#define USB_EP_NI4_TXCOUNT 0xffc03b28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
558
559/* USB Endpoint 5 Control Registers */
560
561#define USB_EP_NI5_TXMAXP 0xffc03b40 /* Maximum packet size for Host Tx endpoint5 */
562#define USB_EP_NI5_TXCSR 0xffc03b44 /* Control Status register for endpoint5 */
563#define USB_EP_NI5_RXMAXP 0xffc03b48 /* Maximum packet size for Host Rx endpoint5 */
564#define USB_EP_NI5_RXCSR 0xffc03b4c /* Control Status register for Host Rx endpoint5 */
565#define USB_EP_NI5_RXCOUNT 0xffc03b50 /* Number of bytes received in endpoint5 FIFO */
566#define USB_EP_NI5_TXTYPE 0xffc03b54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
567#define USB_EP_NI5_TXINTERVAL 0xffc03b58 /* Sets the NAK response timeout on Endpoint5 */
568#define USB_EP_NI5_RXTYPE 0xffc03b5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
569#define USB_EP_NI5_RXINTERVAL 0xffc03b60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
570#define USB_EP_NI5_TXCOUNT 0xffc03b68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
571
572/* USB Endpoint 6 Control Registers */
573
574#define USB_EP_NI6_TXMAXP 0xffc03b80 /* Maximum packet size for Host Tx endpoint6 */
575#define USB_EP_NI6_TXCSR 0xffc03b84 /* Control Status register for endpoint6 */
576#define USB_EP_NI6_RXMAXP 0xffc03b88 /* Maximum packet size for Host Rx endpoint6 */
577#define USB_EP_NI6_RXCSR 0xffc03b8c /* Control Status register for Host Rx endpoint6 */
578#define USB_EP_NI6_RXCOUNT 0xffc03b90 /* Number of bytes received in endpoint6 FIFO */
579#define USB_EP_NI6_TXTYPE 0xffc03b94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
580#define USB_EP_NI6_TXINTERVAL 0xffc03b98 /* Sets the NAK response timeout on Endpoint6 */
581#define USB_EP_NI6_RXTYPE 0xffc03b9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
582#define USB_EP_NI6_RXINTERVAL 0xffc03ba0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
583#define USB_EP_NI6_TXCOUNT 0xffc03ba8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
584
585/* USB Endpoint 7 Control Registers */
586
587#define USB_EP_NI7_TXMAXP 0xffc03bc0 /* Maximum packet size for Host Tx endpoint7 */
588#define USB_EP_NI7_TXCSR 0xffc03bc4 /* Control Status register for endpoint7 */
589#define USB_EP_NI7_RXMAXP 0xffc03bc8 /* Maximum packet size for Host Rx endpoint7 */
590#define USB_EP_NI7_RXCSR 0xffc03bcc /* Control Status register for Host Rx endpoint7 */
591#define USB_EP_NI7_RXCOUNT 0xffc03bd0 /* Number of bytes received in endpoint7 FIFO */
592#define USB_EP_NI7_TXTYPE 0xffc03bd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
593#define USB_EP_NI7_TXINTERVAL 0xffc03bd8 /* Sets the NAK response timeout on Endpoint7 */
594#define USB_EP_NI7_RXTYPE 0xffc03bdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
595#define USB_EP_NI7_RXINTERVAL 0xffc03bf0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
596#define USB_EP_NI7_TXCOUNT 0xffc03bf8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
597
598#define USB_DMA_INTERRUPT 0xffc03c00 /* Indicates pending interrupts for the DMA channels */
599
600/* USB Channel 0 Config Registers */
601
602#define USB_DMA0CONTROL 0xffc03c04 /* DMA master channel 0 configuration */
603#define USB_DMA0ADDRLOW 0xffc03c08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
604#define USB_DMA0ADDRHIGH 0xffc03c0c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
605#define USB_DMA0COUNTLOW 0xffc03c10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
606#define USB_DMA0COUNTHIGH 0xffc03c14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
607
608/* USB Channel 1 Config Registers */
609
610#define USB_DMA1CONTROL 0xffc03c24 /* DMA master channel 1 configuration */
611#define USB_DMA1ADDRLOW 0xffc03c28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
612#define USB_DMA1ADDRHIGH 0xffc03c2c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
613#define USB_DMA1COUNTLOW 0xffc03c30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
614#define USB_DMA1COUNTHIGH 0xffc03c34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
615
616/* USB Channel 2 Config Registers */
617
618#define USB_DMA2CONTROL 0xffc03c44 /* DMA master channel 2 configuration */
619#define USB_DMA2ADDRLOW 0xffc03c48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
620#define USB_DMA2ADDRHIGH 0xffc03c4c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
621#define USB_DMA2COUNTLOW 0xffc03c50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
622#define USB_DMA2COUNTHIGH 0xffc03c54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
623
624/* USB Channel 3 Config Registers */
625
626#define USB_DMA3CONTROL 0xffc03c64 /* DMA master channel 3 configuration */
627#define USB_DMA3ADDRLOW 0xffc03c68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
628#define USB_DMA3ADDRHIGH 0xffc03c6c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
629#define USB_DMA3COUNTLOW 0xffc03c70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
630#define USB_DMA3COUNTHIGH 0xffc03c74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
631
632/* USB Channel 4 Config Registers */
633
634#define USB_DMA4CONTROL 0xffc03c84 /* DMA master channel 4 configuration */
635#define USB_DMA4ADDRLOW 0xffc03c88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
636#define USB_DMA4ADDRHIGH 0xffc03c8c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
637#define USB_DMA4COUNTLOW 0xffc03c90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
638#define USB_DMA4COUNTHIGH 0xffc03c94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
639
640/* USB Channel 5 Config Registers */
641
642#define USB_DMA5CONTROL 0xffc03ca4 /* DMA master channel 5 configuration */
643#define USB_DMA5ADDRLOW 0xffc03ca8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
644#define USB_DMA5ADDRHIGH 0xffc03cac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
645#define USB_DMA5COUNTLOW 0xffc03cb0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
646#define USB_DMA5COUNTHIGH 0xffc03cb4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
647
648/* USB Channel 6 Config Registers */
649
650#define USB_DMA6CONTROL 0xffc03cc4 /* DMA master channel 6 configuration */
651#define USB_DMA6ADDRLOW 0xffc03cc8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
652#define USB_DMA6ADDRHIGH 0xffc03ccc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
653#define USB_DMA6COUNTLOW 0xffc03cd0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
654#define USB_DMA6COUNTHIGH 0xffc03cd4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
655
656/* USB Channel 7 Config Registers */
657
658#define USB_DMA7CONTROL 0xffc03ce4 /* DMA master channel 7 configuration */
659#define USB_DMA7ADDRLOW 0xffc03ce8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
660#define USB_DMA7ADDRHIGH 0xffc03cec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
661#define USB_DMA7COUNTLOW 0xffc03cf0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
662#define USB_DMA7COUNTHIGH 0xffc03cf4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
663
664/* Bit masks for USB_FADDR */
665
666#define FUNCTION_ADDRESS 0x7f /* Function address */
667
668/* Bit masks for USB_POWER */
669
670#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
671#define nENABLE_SUSPENDM 0x0
672#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
673#define nSUSPEND_MODE 0x0
674#define RESUME_MODE 0x4 /* DMA Mode */
675#define nRESUME_MODE 0x0
676#define RESET 0x8 /* Reset indicator */
677#define nRESET 0x0
678#define HS_MODE 0x10 /* High Speed mode indicator */
679#define nHS_MODE 0x0
680#define HS_ENABLE 0x20 /* high Speed Enable */
681#define nHS_ENABLE 0x0
682#define SOFT_CONN 0x40 /* Soft connect */
683#define nSOFT_CONN 0x0
684#define ISO_UPDATE 0x80 /* Isochronous update */
685#define nISO_UPDATE 0x0
686
687/* Bit masks for USB_INTRTX */
688
689#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
690#define nEP0_TX 0x0
691#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
692#define nEP1_TX 0x0
693#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
694#define nEP2_TX 0x0
695#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
696#define nEP3_TX 0x0
697#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
698#define nEP4_TX 0x0
699#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
700#define nEP5_TX 0x0
701#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
702#define nEP6_TX 0x0
703#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
704#define nEP7_TX 0x0
705
706/* Bit masks for USB_INTRRX */
707
708#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
709#define nEP1_RX 0x0
710#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
711#define nEP2_RX 0x0
712#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
713#define nEP3_RX 0x0
714#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
715#define nEP4_RX 0x0
716#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
717#define nEP5_RX 0x0
718#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
719#define nEP6_RX 0x0
720#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
721#define nEP7_RX 0x0
722
723/* Bit masks for USB_INTRTXE */
724
725#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
726#define nEP0_TX_E 0x0
727#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
728#define nEP1_TX_E 0x0
729#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
730#define nEP2_TX_E 0x0
731#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
732#define nEP3_TX_E 0x0
733#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
734#define nEP4_TX_E 0x0
735#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
736#define nEP5_TX_E 0x0
737#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
738#define nEP6_TX_E 0x0
739#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
740#define nEP7_TX_E 0x0
741
742/* Bit masks for USB_INTRRXE */
743
744#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
745#define nEP1_RX_E 0x0
746#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
747#define nEP2_RX_E 0x0
748#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
749#define nEP3_RX_E 0x0
750#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
751#define nEP4_RX_E 0x0
752#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
753#define nEP5_RX_E 0x0
754#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
755#define nEP6_RX_E 0x0
756#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
757#define nEP7_RX_E 0x0
758
759/* Bit masks for USB_INTRUSB */
760
761#define SUSPEND_B 0x1 /* Suspend indicator */
762#define nSUSPEND_B 0x0
763#define RESUME_B 0x2 /* Resume indicator */
764#define nRESUME_B 0x0
765#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
766#define nRESET_OR_BABLE_B 0x0
767#define SOF_B 0x8 /* Start of frame */
768#define nSOF_B 0x0
769#define CONN_B 0x10 /* Connection indicator */
770#define nCONN_B 0x0
771#define DISCON_B 0x20 /* Disconnect indicator */
772#define nDISCON_B 0x0
773#define SESSION_REQ_B 0x40 /* Session Request */
774#define nSESSION_REQ_B 0x0
775#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
776#define nVBUS_ERROR_B 0x0
777
778/* Bit masks for USB_INTRUSBE */
779
780#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
781#define nSUSPEND_BE 0x0
782#define RESUME_BE 0x2 /* Resume indicator int enable */
783#define nRESUME_BE 0x0
784#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
785#define nRESET_OR_BABLE_BE 0x0
786#define SOF_BE 0x8 /* Start of frame int enable */
787#define nSOF_BE 0x0
788#define CONN_BE 0x10 /* Connection indicator int enable */
789#define nCONN_BE 0x0
790#define DISCON_BE 0x20 /* Disconnect indicator int enable */
791#define nDISCON_BE 0x0
792#define SESSION_REQ_BE 0x40 /* Session Request int enable */
793#define nSESSION_REQ_BE 0x0
794#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
795#define nVBUS_ERROR_BE 0x0
796
797/* Bit masks for USB_FRAME */
798
799#define FRAME_NUMBER 0x7ff /* Frame number */
800
801/* Bit masks for USB_INDEX */
802
803#define SELECTED_ENDPOINT 0xf /* selected endpoint */
804
805/* Bit masks for USB_GLOBAL_CTL */
806
807#define GLOBAL_ENA 0x1 /* enables USB module */
808#define nGLOBAL_ENA 0x0
809#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
810#define nEP1_TX_ENA 0x0
811#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
812#define nEP2_TX_ENA 0x0
813#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
814#define nEP3_TX_ENA 0x0
815#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
816#define nEP4_TX_ENA 0x0
817#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
818#define nEP5_TX_ENA 0x0
819#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
820#define nEP6_TX_ENA 0x0
821#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
822#define nEP7_TX_ENA 0x0
823#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
824#define nEP1_RX_ENA 0x0
825#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
826#define nEP2_RX_ENA 0x0
827#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
828#define nEP3_RX_ENA 0x0
829#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
830#define nEP4_RX_ENA 0x0
831#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
832#define nEP5_RX_ENA 0x0
833#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
834#define nEP6_RX_ENA 0x0
835#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
836#define nEP7_RX_ENA 0x0
837
838/* Bit masks for USB_OTG_DEV_CTL */
839
840#define SESSION 0x1 /* session indicator */
841#define nSESSION 0x0
842#define HOST_REQ 0x2 /* Host negotiation request */
843#define nHOST_REQ 0x0
844#define HOST_MODE 0x4 /* indicates USBDRC is a host */
845#define nHOST_MODE 0x0
846#define VBUS0 0x8 /* Vbus level indicator[0] */
847#define nVBUS0 0x0
848#define VBUS1 0x10 /* Vbus level indicator[1] */
849#define nVBUS1 0x0
850#define LSDEV 0x20 /* Low-speed indicator */
851#define nLSDEV 0x0
852#define FSDEV 0x40 /* Full or High-speed indicator */
853#define nFSDEV 0x0
854#define B_DEVICE 0x80 /* A' or 'B' device indicator */
855#define nB_DEVICE 0x0
856
857/* Bit masks for USB_OTG_VBUS_IRQ */
858
859#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
860#define nDRIVE_VBUS_ON 0x0
861#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
862#define nDRIVE_VBUS_OFF 0x0
863#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
864#define nCHRG_VBUS_START 0x0
865#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
866#define nCHRG_VBUS_END 0x0
867#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
868#define nDISCHRG_VBUS_START 0x0
869#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
870#define nDISCHRG_VBUS_END 0x0
871
872/* Bit masks for USB_OTG_VBUS_MASK */
873
874#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
875#define nDRIVE_VBUS_ON_ENA 0x0
876#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
877#define nDRIVE_VBUS_OFF_ENA 0x0
878#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
879#define nCHRG_VBUS_START_ENA 0x0
880#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
881#define nCHRG_VBUS_END_ENA 0x0
882#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
883#define nDISCHRG_VBUS_START_ENA 0x0
884#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
885#define nDISCHRG_VBUS_END_ENA 0x0
886
887/* Bit masks for USB_CSR0 */
888
889#define RXPKTRDY 0x1 /* data packet receive indicator */
890#define nRXPKTRDY 0x0
891#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
892#define nTXPKTRDY 0x0
893#define STALL_SENT 0x4 /* STALL handshake sent */
894#define nSTALL_SENT 0x0
895#define DATAEND 0x8 /* Data end indicator */
896#define nDATAEND 0x0
897#define SETUPEND 0x10 /* Setup end */
898#define nSETUPEND 0x0
899#define SENDSTALL 0x20 /* Send STALL handshake */
900#define nSENDSTALL 0x0
901#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
902#define nSERVICED_RXPKTRDY 0x0
903#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
904#define nSERVICED_SETUPEND 0x0
905#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
906#define nFLUSHFIFO 0x0
907#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
908#define nSTALL_RECEIVED_H 0x0
909#define SETUPPKT_H 0x8 /* send Setup token host mode */
910#define nSETUPPKT_H 0x0
911#define ERROR_H 0x10 /* timeout error indicator host mode */
912#define nERROR_H 0x0
913#define REQPKT_H 0x20 /* Request an IN transaction host mode */
914#define nREQPKT_H 0x0
915#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
916#define nSTATUSPKT_H 0x0
917#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
918#define nNAK_TIMEOUT_H 0x0
919
920/* Bit masks for USB_COUNT0 */
921
922#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
923
924/* Bit masks for USB_NAKLIMIT0 */
925
926#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
927
928/* Bit masks for USB_TX_MAX_PACKET */
929
930#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
931
932/* Bit masks for USB_RX_MAX_PACKET */
933
934#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
935
936/* Bit masks for USB_TXCSR */
937
938#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
939#define nTXPKTRDY_T 0x0
940#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
941#define nFIFO_NOT_EMPTY_T 0x0
942#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
943#define nUNDERRUN_T 0x0
944#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
945#define nFLUSHFIFO_T 0x0
946#define STALL_SEND_T 0x10 /* issue a Stall handshake */
947#define nSTALL_SEND_T 0x0
948#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
949#define nSTALL_SENT_T 0x0
950#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
951#define nCLEAR_DATATOGGLE_T 0x0
952#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
953#define nINCOMPTX_T 0x0
954#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
955#define nDMAREQMODE_T 0x0
956#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
957#define nFORCE_DATATOGGLE_T 0x0
958#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
959#define nDMAREQ_ENA_T 0x0
960#define ISO_T 0x4000 /* enable Isochronous transfers */
961#define nISO_T 0x0
962#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
963#define nAUTOSET_T 0x0
964#define ERROR_TH 0x4 /* error condition host mode */
965#define nERROR_TH 0x0
966#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
967#define nSTALL_RECEIVED_TH 0x0
968#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
969#define nNAK_TIMEOUT_TH 0x0
970
971/* Bit masks for USB_TXCOUNT */
972
973#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
974
975/* Bit masks for USB_RXCSR */
976
977#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
978#define nRXPKTRDY_R 0x0
979#define FIFO_FULL_R 0x2 /* FIFO not empty */
980#define nFIFO_FULL_R 0x0
981#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
982#define nOVERRUN_R 0x0
983#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
984#define nDATAERROR_R 0x0
985#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
986#define nFLUSHFIFO_R 0x0
987#define STALL_SEND_R 0x20 /* issue a Stall handshake */
988#define nSTALL_SEND_R 0x0
989#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
990#define nSTALL_SENT_R 0x0
991#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
992#define nCLEAR_DATATOGGLE_R 0x0
993#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
994#define nINCOMPRX_R 0x0
995#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
996#define nDMAREQMODE_R 0x0
997#define DISNYET_R 0x1000 /* disable Nyet handshakes */
998#define nDISNYET_R 0x0
999#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1000#define nDMAREQ_ENA_R 0x0
1001#define ISO_R 0x4000 /* enable Isochronous transfers */
1002#define nISO_R 0x0
1003#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1004#define nAUTOCLEAR_R 0x0
1005#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1006#define nERROR_RH 0x0
1007#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1008#define nREQPKT_RH 0x0
1009#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1010#define nSTALL_RECEIVED_RH 0x0
1011#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1012#define nINCOMPRX_RH 0x0
1013#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1014#define nDMAREQMODE_RH 0x0
1015#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1016#define nAUTOREQ_RH 0x0
1017
1018/* Bit masks for USB_RXCOUNT */
1019
1020#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1021
1022/* Bit masks for USB_TXTYPE */
1023
1024#define TARGET_EP_NO_T 0xf /* EP number */
1025#define PROTOCOL_T 0xc /* transfer type */
1026
1027/* Bit masks for USB_TXINTERVAL */
1028
1029#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1030
1031/* Bit masks for USB_RXTYPE */
1032
1033#define TARGET_EP_NO_R 0xf /* EP number */
1034#define PROTOCOL_R 0xc /* transfer type */
1035
1036/* Bit masks for USB_RXINTERVAL */
1037
1038#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1039
1040/* Bit masks for USB_DMA_INTERRUPT */
1041
1042#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1043#define nDMA0_INT 0x0
1044#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1045#define nDMA1_INT 0x0
1046#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1047#define nDMA2_INT 0x0
1048#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1049#define nDMA3_INT 0x0
1050#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1051#define nDMA4_INT 0x0
1052#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1053#define nDMA5_INT 0x0
1054#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1055#define nDMA6_INT 0x0
1056#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1057#define nDMA7_INT 0x0
1058
1059/* Bit masks for USB_DMAxCONTROL */
1060
1061#define DMA_ENA 0x1 /* DMA enable */
1062#define nDMA_ENA 0x0
1063#define DIRECTION 0x2 /* direction of DMA transfer */
1064#define nDIRECTION 0x0
1065#define MODE 0x4 /* DMA Bus error */
1066#define nMODE 0x0
1067#define INT_ENA 0x8 /* Interrupt enable */
1068#define nINT_ENA 0x0
1069#define EPNUM 0xf0 /* EP number */
1070#define BUSERROR 0x100 /* DMA Bus error */
1071#define nBUSERROR 0x0
1072
1073/* Bit masks for USB_DMAxADDRHIGH */
1074
1075#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1076
1077/* Bit masks for USB_DMAxADDRLOW */
1078
1079#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1080
1081/* Bit masks for USB_DMAxCOUNTHIGH */
1082
1083#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1084
1085/* Bit masks for USB_DMAxCOUNTLOW */
1086
1087#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1088
1089#endif /* _DEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
new file mode 100644
index 000000000000..0b2fb5036ed0
--- /dev/null
+++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h
@@ -0,0 +1,2009 @@
1/*
2 * File: include/asm-blackfin/mach-bf527/defBF52x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF52X_H
32#define _DEF_BF52X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x */
37/* ************************************************************** */
38
39/* ==== begin from defBF534.h ==== */
40
41/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
42#define PLL_CTL 0xFFC00000 /* PLL Control Register */
43#define PLL_DIV 0xFFC00004 /* PLL Divide Register */
44#define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register */
45#define PLL_STAT 0xFFC0000C /* PLL Status Register */
46#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count Register */
47#define CHIPID 0xFFC00014 /* Device ID Register */
48
49
50/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
51#define SWRST 0xFFC00100 /* Software Reset Register */
52#define SYSCR 0xFFC00104 /* System Configuration Register */
53#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
54
55#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
56#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
57#define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
58#define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
59#define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
60#define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
61#define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
62
63/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
64#define SIC_IMASK1 0xFFC0014C /* Interrupt Mask register of SIC2 */
65#define SIC_IAR4 0xFFC00150 /* Interrupt Assignment register4 */
66#define SIC_IAR5 0xFFC00154 /* Interrupt Assignment register5 */
67#define SIC_IAR6 0xFFC00158 /* Interrupt Assignment register6 */
68#define SIC_IAR7 0xFFC0015C /* Interrupt Assignment register7 */
69#define SIC_ISR1 0xFFC00160 /* Interrupt Statur register */
70#define SIC_IWR1 0xFFC00164 /* Interrupt Wakeup register */
71
72
73/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
74#define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
75#define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
76#define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
77
78
79/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
80#define RTC_STAT 0xFFC00300 /* RTC Status Register */
81#define RTC_ICTL 0xFFC00304 /* RTC Interrupt Control Register */
82#define RTC_ISTAT 0xFFC00308 /* RTC Interrupt Status Register */
83#define RTC_SWCNT 0xFFC0030C /* RTC Stopwatch Count Register */
84#define RTC_ALARM 0xFFC00310 /* RTC Alarm Time Register */
85#define RTC_FAST 0xFFC00314 /* RTC Prescaler Enable Register */
86#define RTC_PREN 0xFFC00314 /* RTC Prescaler Enable Alternate Macro */
87
88
89/* UART0 Controller (0xFFC00400 - 0xFFC004FF) */
90#define UART0_THR 0xFFC00400 /* Transmit Holding register */
91#define UART0_RBR 0xFFC00400 /* Receive Buffer register */
92#define UART0_DLL 0xFFC00400 /* Divisor Latch (Low-Byte) */
93#define UART0_IER 0xFFC00404 /* Interrupt Enable Register */
94#define UART0_DLH 0xFFC00404 /* Divisor Latch (High-Byte) */
95#define UART0_IIR 0xFFC00408 /* Interrupt Identification Register */
96#define UART0_LCR 0xFFC0040C /* Line Control Register */
97#define UART0_MCR 0xFFC00410 /* Modem Control Register */
98#define UART0_LSR 0xFFC00414 /* Line Status Register */
99#define UART0_MSR 0xFFC00418 /* Modem Status Register */
100#define UART0_SCR 0xFFC0041C /* SCR Scratch Register */
101#define UART0_GCTL 0xFFC00424 /* Global Control Register */
102
103
104/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
105#define SPI_CTL 0xFFC00500 /* SPI Control Register */
106#define SPI_FLG 0xFFC00504 /* SPI Flag register */
107#define SPI_STAT 0xFFC00508 /* SPI Status register */
108#define SPI_TDBR 0xFFC0050C /* SPI Transmit Data Buffer Register */
109#define SPI_RDBR 0xFFC00510 /* SPI Receive Data Buffer Register */
110#define SPI_BAUD 0xFFC00514 /* SPI Baud rate Register */
111#define SPI_SHADOW 0xFFC00518 /* SPI_RDBR Shadow Register */
112
113
114/* TIMER0-7 Registers (0xFFC00600 - 0xFFC006FF) */
115#define TIMER0_CONFIG 0xFFC00600 /* Timer 0 Configuration Register */
116#define TIMER0_COUNTER 0xFFC00604 /* Timer 0 Counter Register */
117#define TIMER0_PERIOD 0xFFC00608 /* Timer 0 Period Register */
118#define TIMER0_WIDTH 0xFFC0060C /* Timer 0 Width Register */
119
120#define TIMER1_CONFIG 0xFFC00610 /* Timer 1 Configuration Register */
121#define TIMER1_COUNTER 0xFFC00614 /* Timer 1 Counter Register */
122#define TIMER1_PERIOD 0xFFC00618 /* Timer 1 Period Register */
123#define TIMER1_WIDTH 0xFFC0061C /* Timer 1 Width Register */
124
125#define TIMER2_CONFIG 0xFFC00620 /* Timer 2 Configuration Register */
126#define TIMER2_COUNTER 0xFFC00624 /* Timer 2 Counter Register */
127#define TIMER2_PERIOD 0xFFC00628 /* Timer 2 Period Register */
128#define TIMER2_WIDTH 0xFFC0062C /* Timer 2 Width Register */
129
130#define TIMER3_CONFIG 0xFFC00630 /* Timer 3 Configuration Register */
131#define TIMER3_COUNTER 0xFFC00634 /* Timer 3 Counter Register */
132#define TIMER3_PERIOD 0xFFC00638 /* Timer 3 Period Register */
133#define TIMER3_WIDTH 0xFFC0063C /* Timer 3 Width Register */
134
135#define TIMER4_CONFIG 0xFFC00640 /* Timer 4 Configuration Register */
136#define TIMER4_COUNTER 0xFFC00644 /* Timer 4 Counter Register */
137#define TIMER4_PERIOD 0xFFC00648 /* Timer 4 Period Register */
138#define TIMER4_WIDTH 0xFFC0064C /* Timer 4 Width Register */
139
140#define TIMER5_CONFIG 0xFFC00650 /* Timer 5 Configuration Register */
141#define TIMER5_COUNTER 0xFFC00654 /* Timer 5 Counter Register */
142#define TIMER5_PERIOD 0xFFC00658 /* Timer 5 Period Register */
143#define TIMER5_WIDTH 0xFFC0065C /* Timer 5 Width Register */
144
145#define TIMER6_CONFIG 0xFFC00660 /* Timer 6 Configuration Register */
146#define TIMER6_COUNTER 0xFFC00664 /* Timer 6 Counter Register */
147#define TIMER6_PERIOD 0xFFC00668 /* Timer 6 Period Register */
148#define TIMER6_WIDTH 0xFFC0066C /* Timer 6 Width Register */
149
150#define TIMER7_CONFIG 0xFFC00670 /* Timer 7 Configuration Register */
151#define TIMER7_COUNTER 0xFFC00674 /* Timer 7 Counter Register */
152#define TIMER7_PERIOD 0xFFC00678 /* Timer 7 Period Register */
153#define TIMER7_WIDTH 0xFFC0067C /* Timer 7 Width Register */
154
155#define TIMER_ENABLE 0xFFC00680 /* Timer Enable Register */
156#define TIMER_DISABLE 0xFFC00684 /* Timer Disable Register */
157#define TIMER_STATUS 0xFFC00688 /* Timer Status Register */
158
159
160/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF) */
161#define PORTFIO 0xFFC00700 /* Port F I/O Pin State Specify Register */
162#define PORTFIO_CLEAR 0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
163#define PORTFIO_SET 0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
164#define PORTFIO_TOGGLE 0xFFC0070C /* Port F I/O Pin State Toggle Register */
165#define PORTFIO_MASKA 0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
166#define PORTFIO_MASKA_CLEAR 0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
167#define PORTFIO_MASKA_SET 0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
168#define PORTFIO_MASKA_TOGGLE 0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
169#define PORTFIO_MASKB 0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
170#define PORTFIO_MASKB_CLEAR 0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
171#define PORTFIO_MASKB_SET 0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
172#define PORTFIO_MASKB_TOGGLE 0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
173#define PORTFIO_DIR 0xFFC00730 /* Port F I/O Direction Register */
174#define PORTFIO_POLAR 0xFFC00734 /* Port F I/O Source Polarity Register */
175#define PORTFIO_EDGE 0xFFC00738 /* Port F I/O Source Sensitivity Register */
176#define PORTFIO_BOTH 0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
177#define PORTFIO_INEN 0xFFC00740 /* Port F I/O Input Enable Register */
178
179
180/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
181#define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
182#define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
183#define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
184#define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
185#define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
186#define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
187#define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
188#define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
189#define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
190#define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
191#define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
192#define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
193#define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
194#define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
195#define SPORT0_MTCS0 0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
196#define SPORT0_MTCS1 0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
197#define SPORT0_MTCS2 0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
198#define SPORT0_MTCS3 0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
199#define SPORT0_MRCS0 0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
200#define SPORT0_MRCS1 0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
201#define SPORT0_MRCS2 0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
202#define SPORT0_MRCS3 0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
203
204
205/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
206#define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
207#define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
208#define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
209#define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
210#define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
211#define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
212#define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
213#define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
214#define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
215#define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
216#define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
217#define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
218#define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
219#define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
220#define SPORT1_MTCS0 0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
221#define SPORT1_MTCS1 0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
222#define SPORT1_MTCS2 0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
223#define SPORT1_MTCS3 0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
224#define SPORT1_MRCS0 0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
225#define SPORT1_MRCS1 0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
226#define SPORT1_MRCS2 0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
227#define SPORT1_MRCS3 0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
228
229
230/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
231#define EBIU_AMGCTL 0xFFC00A00 /* Asynchronous Memory Global Control Register */
232#define EBIU_AMBCTL0 0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
233#define EBIU_AMBCTL1 0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
234#define EBIU_SDGCTL 0xFFC00A10 /* SDRAM Global Control Register */
235#define EBIU_SDBCTL 0xFFC00A14 /* SDRAM Bank Control Register */
236#define EBIU_SDRRC 0xFFC00A18 /* SDRAM Refresh Rate Control Register */
237#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
238
239
240/* DMA Traffic Control Registers */
241#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
242#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
243
244/* Alternate deprecated register names (below) provided for backwards code compatibility */
245#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
246#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
247
248/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
249#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
250#define DMA0_START_ADDR 0xFFC00C04 /* DMA Channel 0 Start Address Register */
251#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
252#define DMA0_X_COUNT 0xFFC00C10 /* DMA Channel 0 X Count Register */
253#define DMA0_X_MODIFY 0xFFC00C14 /* DMA Channel 0 X Modify Register */
254#define DMA0_Y_COUNT 0xFFC00C18 /* DMA Channel 0 Y Count Register */
255#define DMA0_Y_MODIFY 0xFFC00C1C /* DMA Channel 0 Y Modify Register */
256#define DMA0_CURR_DESC_PTR 0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
257#define DMA0_CURR_ADDR 0xFFC00C24 /* DMA Channel 0 Current Address Register */
258#define DMA0_IRQ_STATUS 0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
259#define DMA0_PERIPHERAL_MAP 0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
260#define DMA0_CURR_X_COUNT 0xFFC00C30 /* DMA Channel 0 Current X Count Register */
261#define DMA0_CURR_Y_COUNT 0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
262
263#define DMA1_NEXT_DESC_PTR 0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
264#define DMA1_START_ADDR 0xFFC00C44 /* DMA Channel 1 Start Address Register */
265#define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
266#define DMA1_X_COUNT 0xFFC00C50 /* DMA Channel 1 X Count Register */
267#define DMA1_X_MODIFY 0xFFC00C54 /* DMA Channel 1 X Modify Register */
268#define DMA1_Y_COUNT 0xFFC00C58 /* DMA Channel 1 Y Count Register */
269#define DMA1_Y_MODIFY 0xFFC00C5C /* DMA Channel 1 Y Modify Register */
270#define DMA1_CURR_DESC_PTR 0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
271#define DMA1_CURR_ADDR 0xFFC00C64 /* DMA Channel 1 Current Address Register */
272#define DMA1_IRQ_STATUS 0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
273#define DMA1_PERIPHERAL_MAP 0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
274#define DMA1_CURR_X_COUNT 0xFFC00C70 /* DMA Channel 1 Current X Count Register */
275#define DMA1_CURR_Y_COUNT 0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
276
277#define DMA2_NEXT_DESC_PTR 0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
278#define DMA2_START_ADDR 0xFFC00C84 /* DMA Channel 2 Start Address Register */
279#define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
280#define DMA2_X_COUNT 0xFFC00C90 /* DMA Channel 2 X Count Register */
281#define DMA2_X_MODIFY 0xFFC00C94 /* DMA Channel 2 X Modify Register */
282#define DMA2_Y_COUNT 0xFFC00C98 /* DMA Channel 2 Y Count Register */
283#define DMA2_Y_MODIFY 0xFFC00C9C /* DMA Channel 2 Y Modify Register */
284#define DMA2_CURR_DESC_PTR 0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
285#define DMA2_CURR_ADDR 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
286#define DMA2_IRQ_STATUS 0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
287#define DMA2_PERIPHERAL_MAP 0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
288#define DMA2_CURR_X_COUNT 0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
289#define DMA2_CURR_Y_COUNT 0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
290
291#define DMA3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
292#define DMA3_START_ADDR 0xFFC00CC4 /* DMA Channel 3 Start Address Register */
293#define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
294#define DMA3_X_COUNT 0xFFC00CD0 /* DMA Channel 3 X Count Register */
295#define DMA3_X_MODIFY 0xFFC00CD4 /* DMA Channel 3 X Modify Register */
296#define DMA3_Y_COUNT 0xFFC00CD8 /* DMA Channel 3 Y Count Register */
297#define DMA3_Y_MODIFY 0xFFC00CDC /* DMA Channel 3 Y Modify Register */
298#define DMA3_CURR_DESC_PTR 0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
299#define DMA3_CURR_ADDR 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
300#define DMA3_IRQ_STATUS 0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
301#define DMA3_PERIPHERAL_MAP 0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
302#define DMA3_CURR_X_COUNT 0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
303#define DMA3_CURR_Y_COUNT 0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
304
305#define DMA4_NEXT_DESC_PTR 0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
306#define DMA4_START_ADDR 0xFFC00D04 /* DMA Channel 4 Start Address Register */
307#define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
308#define DMA4_X_COUNT 0xFFC00D10 /* DMA Channel 4 X Count Register */
309#define DMA4_X_MODIFY 0xFFC00D14 /* DMA Channel 4 X Modify Register */
310#define DMA4_Y_COUNT 0xFFC00D18 /* DMA Channel 4 Y Count Register */
311#define DMA4_Y_MODIFY 0xFFC00D1C /* DMA Channel 4 Y Modify Register */
312#define DMA4_CURR_DESC_PTR 0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
313#define DMA4_CURR_ADDR 0xFFC00D24 /* DMA Channel 4 Current Address Register */
314#define DMA4_IRQ_STATUS 0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
315#define DMA4_PERIPHERAL_MAP 0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
316#define DMA4_CURR_X_COUNT 0xFFC00D30 /* DMA Channel 4 Current X Count Register */
317#define DMA4_CURR_Y_COUNT 0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
318
319#define DMA5_NEXT_DESC_PTR 0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
320#define DMA5_START_ADDR 0xFFC00D44 /* DMA Channel 5 Start Address Register */
321#define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
322#define DMA5_X_COUNT 0xFFC00D50 /* DMA Channel 5 X Count Register */
323#define DMA5_X_MODIFY 0xFFC00D54 /* DMA Channel 5 X Modify Register */
324#define DMA5_Y_COUNT 0xFFC00D58 /* DMA Channel 5 Y Count Register */
325#define DMA5_Y_MODIFY 0xFFC00D5C /* DMA Channel 5 Y Modify Register */
326#define DMA5_CURR_DESC_PTR 0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
327#define DMA5_CURR_ADDR 0xFFC00D64 /* DMA Channel 5 Current Address Register */
328#define DMA5_IRQ_STATUS 0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
329#define DMA5_PERIPHERAL_MAP 0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
330#define DMA5_CURR_X_COUNT 0xFFC00D70 /* DMA Channel 5 Current X Count Register */
331#define DMA5_CURR_Y_COUNT 0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
332
333#define DMA6_NEXT_DESC_PTR 0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
334#define DMA6_START_ADDR 0xFFC00D84 /* DMA Channel 6 Start Address Register */
335#define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
336#define DMA6_X_COUNT 0xFFC00D90 /* DMA Channel 6 X Count Register */
337#define DMA6_X_MODIFY 0xFFC00D94 /* DMA Channel 6 X Modify Register */
338#define DMA6_Y_COUNT 0xFFC00D98 /* DMA Channel 6 Y Count Register */
339#define DMA6_Y_MODIFY 0xFFC00D9C /* DMA Channel 6 Y Modify Register */
340#define DMA6_CURR_DESC_PTR 0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
341#define DMA6_CURR_ADDR 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
342#define DMA6_IRQ_STATUS 0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
343#define DMA6_PERIPHERAL_MAP 0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
344#define DMA6_CURR_X_COUNT 0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
345#define DMA6_CURR_Y_COUNT 0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
346
347#define DMA7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
348#define DMA7_START_ADDR 0xFFC00DC4 /* DMA Channel 7 Start Address Register */
349#define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
350#define DMA7_X_COUNT 0xFFC00DD0 /* DMA Channel 7 X Count Register */
351#define DMA7_X_MODIFY 0xFFC00DD4 /* DMA Channel 7 X Modify Register */
352#define DMA7_Y_COUNT 0xFFC00DD8 /* DMA Channel 7 Y Count Register */
353#define DMA7_Y_MODIFY 0xFFC00DDC /* DMA Channel 7 Y Modify Register */
354#define DMA7_CURR_DESC_PTR 0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
355#define DMA7_CURR_ADDR 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
356#define DMA7_IRQ_STATUS 0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
357#define DMA7_PERIPHERAL_MAP 0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
358#define DMA7_CURR_X_COUNT 0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
359#define DMA7_CURR_Y_COUNT 0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
360
361#define DMA8_NEXT_DESC_PTR 0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
362#define DMA8_START_ADDR 0xFFC00E04 /* DMA Channel 8 Start Address Register */
363#define DMA8_CONFIG 0xFFC00E08 /* DMA Channel 8 Configuration Register */
364#define DMA8_X_COUNT 0xFFC00E10 /* DMA Channel 8 X Count Register */
365#define DMA8_X_MODIFY 0xFFC00E14 /* DMA Channel 8 X Modify Register */
366#define DMA8_Y_COUNT 0xFFC00E18 /* DMA Channel 8 Y Count Register */
367#define DMA8_Y_MODIFY 0xFFC00E1C /* DMA Channel 8 Y Modify Register */
368#define DMA8_CURR_DESC_PTR 0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
369#define DMA8_CURR_ADDR 0xFFC00E24 /* DMA Channel 8 Current Address Register */
370#define DMA8_IRQ_STATUS 0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
371#define DMA8_PERIPHERAL_MAP 0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
372#define DMA8_CURR_X_COUNT 0xFFC00E30 /* DMA Channel 8 Current X Count Register */
373#define DMA8_CURR_Y_COUNT 0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
374
375#define DMA9_NEXT_DESC_PTR 0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
376#define DMA9_START_ADDR 0xFFC00E44 /* DMA Channel 9 Start Address Register */
377#define DMA9_CONFIG 0xFFC00E48 /* DMA Channel 9 Configuration Register */
378#define DMA9_X_COUNT 0xFFC00E50 /* DMA Channel 9 X Count Register */
379#define DMA9_X_MODIFY 0xFFC00E54 /* DMA Channel 9 X Modify Register */
380#define DMA9_Y_COUNT 0xFFC00E58 /* DMA Channel 9 Y Count Register */
381#define DMA9_Y_MODIFY 0xFFC00E5C /* DMA Channel 9 Y Modify Register */
382#define DMA9_CURR_DESC_PTR 0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
383#define DMA9_CURR_ADDR 0xFFC00E64 /* DMA Channel 9 Current Address Register */
384#define DMA9_IRQ_STATUS 0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
385#define DMA9_PERIPHERAL_MAP 0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
386#define DMA9_CURR_X_COUNT 0xFFC00E70 /* DMA Channel 9 Current X Count Register */
387#define DMA9_CURR_Y_COUNT 0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
388
389#define DMA10_NEXT_DESC_PTR 0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
390#define DMA10_START_ADDR 0xFFC00E84 /* DMA Channel 10 Start Address Register */
391#define DMA10_CONFIG 0xFFC00E88 /* DMA Channel 10 Configuration Register */
392#define DMA10_X_COUNT 0xFFC00E90 /* DMA Channel 10 X Count Register */
393#define DMA10_X_MODIFY 0xFFC00E94 /* DMA Channel 10 X Modify Register */
394#define DMA10_Y_COUNT 0xFFC00E98 /* DMA Channel 10 Y Count Register */
395#define DMA10_Y_MODIFY 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
396#define DMA10_CURR_DESC_PTR 0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
397#define DMA10_CURR_ADDR 0xFFC00EA4 /* DMA Channel 10 Current Address Register */
398#define DMA10_IRQ_STATUS 0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
399#define DMA10_PERIPHERAL_MAP 0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
400#define DMA10_CURR_X_COUNT 0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
401#define DMA10_CURR_Y_COUNT 0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
402
403#define DMA11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
404#define DMA11_START_ADDR 0xFFC00EC4 /* DMA Channel 11 Start Address Register */
405#define DMA11_CONFIG 0xFFC00EC8 /* DMA Channel 11 Configuration Register */
406#define DMA11_X_COUNT 0xFFC00ED0 /* DMA Channel 11 X Count Register */
407#define DMA11_X_MODIFY 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
408#define DMA11_Y_COUNT 0xFFC00ED8 /* DMA Channel 11 Y Count Register */
409#define DMA11_Y_MODIFY 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
410#define DMA11_CURR_DESC_PTR 0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
411#define DMA11_CURR_ADDR 0xFFC00EE4 /* DMA Channel 11 Current Address Register */
412#define DMA11_IRQ_STATUS 0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
413#define DMA11_PERIPHERAL_MAP 0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
414#define DMA11_CURR_X_COUNT 0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
415#define DMA11_CURR_Y_COUNT 0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
416
417#define MDMA_D0_NEXT_DESC_PTR 0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
418#define MDMA_D0_START_ADDR 0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
419#define MDMA_D0_CONFIG 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
420#define MDMA_D0_X_COUNT 0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
421#define MDMA_D0_X_MODIFY 0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
422#define MDMA_D0_Y_COUNT 0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
423#define MDMA_D0_Y_MODIFY 0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
424#define MDMA_D0_CURR_DESC_PTR 0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
425#define MDMA_D0_CURR_ADDR 0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
426#define MDMA_D0_IRQ_STATUS 0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
427#define MDMA_D0_PERIPHERAL_MAP 0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
428#define MDMA_D0_CURR_X_COUNT 0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
429#define MDMA_D0_CURR_Y_COUNT 0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
430
431#define MDMA_S0_NEXT_DESC_PTR 0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
432#define MDMA_S0_START_ADDR 0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
433#define MDMA_S0_CONFIG 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
434#define MDMA_S0_X_COUNT 0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
435#define MDMA_S0_X_MODIFY 0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
436#define MDMA_S0_Y_COUNT 0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
437#define MDMA_S0_Y_MODIFY 0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
438#define MDMA_S0_CURR_DESC_PTR 0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
439#define MDMA_S0_CURR_ADDR 0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
440#define MDMA_S0_IRQ_STATUS 0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
441#define MDMA_S0_PERIPHERAL_MAP 0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
442#define MDMA_S0_CURR_X_COUNT 0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
443#define MDMA_S0_CURR_Y_COUNT 0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
444
445#define MDMA_D1_NEXT_DESC_PTR 0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
446#define MDMA_D1_START_ADDR 0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
447#define MDMA_D1_CONFIG 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
448#define MDMA_D1_X_COUNT 0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
449#define MDMA_D1_X_MODIFY 0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
450#define MDMA_D1_Y_COUNT 0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
451#define MDMA_D1_Y_MODIFY 0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
452#define MDMA_D1_CURR_DESC_PTR 0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
453#define MDMA_D1_CURR_ADDR 0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
454#define MDMA_D1_IRQ_STATUS 0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
455#define MDMA_D1_PERIPHERAL_MAP 0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
456#define MDMA_D1_CURR_X_COUNT 0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
457#define MDMA_D1_CURR_Y_COUNT 0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
458
459#define MDMA_S1_NEXT_DESC_PTR 0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
460#define MDMA_S1_START_ADDR 0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
461#define MDMA_S1_CONFIG 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
462#define MDMA_S1_X_COUNT 0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
463#define MDMA_S1_X_MODIFY 0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
464#define MDMA_S1_Y_COUNT 0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
465#define MDMA_S1_Y_MODIFY 0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
466#define MDMA_S1_CURR_DESC_PTR 0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
467#define MDMA_S1_CURR_ADDR 0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
468#define MDMA_S1_IRQ_STATUS 0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
469#define MDMA_S1_PERIPHERAL_MAP 0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
470#define MDMA_S1_CURR_X_COUNT 0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
471#define MDMA_S1_CURR_Y_COUNT 0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
472
473
474/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF) */
475#define PPI_CONTROL 0xFFC01000 /* PPI Control Register */
476#define PPI_STATUS 0xFFC01004 /* PPI Status Register */
477#define PPI_COUNT 0xFFC01008 /* PPI Transfer Count Register */
478#define PPI_DELAY 0xFFC0100C /* PPI Delay Count Register */
479#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
480
481
482/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
483#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
484#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
485#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
486#define TWI_SLAVE_STAT 0xFFC0140C /* Slave Mode Status Register */
487#define TWI_SLAVE_ADDR 0xFFC01410 /* Slave Mode Address Register */
488#define TWI_MASTER_CTL 0xFFC01414 /* Master Mode Control Register */
489#define TWI_MASTER_STAT 0xFFC01418 /* Master Mode Status Register */
490#define TWI_MASTER_ADDR 0xFFC0141C /* Master Mode Address Register */
491#define TWI_INT_STAT 0xFFC01420 /* TWI Interrupt Status Register */
492#define TWI_INT_MASK 0xFFC01424 /* TWI Master Interrupt Mask Register */
493#define TWI_FIFO_CTL 0xFFC01428 /* FIFO Control Register */
494#define TWI_FIFO_STAT 0xFFC0142C /* FIFO Status Register */
495#define TWI_XMT_DATA8 0xFFC01480 /* FIFO Transmit Data Single Byte Register */
496#define TWI_XMT_DATA16 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
497#define TWI_RCV_DATA8 0xFFC01488 /* FIFO Receive Data Single Byte Register */
498#define TWI_RCV_DATA16 0xFFC0148C /* FIFO Receive Data Double Byte Register */
499
500
501/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF) */
502#define PORTGIO 0xFFC01500 /* Port G I/O Pin State Specify Register */
503#define PORTGIO_CLEAR 0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
504#define PORTGIO_SET 0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
505#define PORTGIO_TOGGLE 0xFFC0150C /* Port G I/O Pin State Toggle Register */
506#define PORTGIO_MASKA 0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
507#define PORTGIO_MASKA_CLEAR 0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
508#define PORTGIO_MASKA_SET 0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
509#define PORTGIO_MASKA_TOGGLE 0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
510#define PORTGIO_MASKB 0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
511#define PORTGIO_MASKB_CLEAR 0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
512#define PORTGIO_MASKB_SET 0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
513#define PORTGIO_MASKB_TOGGLE 0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
514#define PORTGIO_DIR 0xFFC01530 /* Port G I/O Direction Register */
515#define PORTGIO_POLAR 0xFFC01534 /* Port G I/O Source Polarity Register */
516#define PORTGIO_EDGE 0xFFC01538 /* Port G I/O Source Sensitivity Register */
517#define PORTGIO_BOTH 0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
518#define PORTGIO_INEN 0xFFC01540 /* Port G I/O Input Enable Register */
519
520
521/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF) */
522#define PORTHIO 0xFFC01700 /* Port H I/O Pin State Specify Register */
523#define PORTHIO_CLEAR 0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
524#define PORTHIO_SET 0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
525#define PORTHIO_TOGGLE 0xFFC0170C /* Port H I/O Pin State Toggle Register */
526#define PORTHIO_MASKA 0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
527#define PORTHIO_MASKA_CLEAR 0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
528#define PORTHIO_MASKA_SET 0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
529#define PORTHIO_MASKA_TOGGLE 0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
530#define PORTHIO_MASKB 0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
531#define PORTHIO_MASKB_CLEAR 0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
532#define PORTHIO_MASKB_SET 0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
533#define PORTHIO_MASKB_TOGGLE 0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
534#define PORTHIO_DIR 0xFFC01730 /* Port H I/O Direction Register */
535#define PORTHIO_POLAR 0xFFC01734 /* Port H I/O Source Polarity Register */
536#define PORTHIO_EDGE 0xFFC01738 /* Port H I/O Source Sensitivity Register */
537#define PORTHIO_BOTH 0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
538#define PORTHIO_INEN 0xFFC01740 /* Port H I/O Input Enable Register */
539
540
541/* UART1 Controller (0xFFC02000 - 0xFFC020FF) */
542#define UART1_THR 0xFFC02000 /* Transmit Holding register */
543#define UART1_RBR 0xFFC02000 /* Receive Buffer register */
544#define UART1_DLL 0xFFC02000 /* Divisor Latch (Low-Byte) */
545#define UART1_IER 0xFFC02004 /* Interrupt Enable Register */
546#define UART1_DLH 0xFFC02004 /* Divisor Latch (High-Byte) */
547#define UART1_IIR 0xFFC02008 /* Interrupt Identification Register */
548#define UART1_LCR 0xFFC0200C /* Line Control Register */
549#define UART1_MCR 0xFFC02010 /* Modem Control Register */
550#define UART1_LSR 0xFFC02014 /* Line Status Register */
551#define UART1_MSR 0xFFC02018 /* Modem Status Register */
552#define UART1_SCR 0xFFC0201C /* SCR Scratch Register */
553#define UART1_GCTL 0xFFC02024 /* Global Control Register */
554
555
556/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
557
558/* Pin Control Registers (0xFFC03200 - 0xFFC032FF) */
559#define PORTF_FER 0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
560#define PORTG_FER 0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
561#define PORTH_FER 0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
562#define BFIN_PORT_MUX 0xFFC0320C /* Port Multiplexer Control Register */
563
564
565/* Handshake MDMA Registers (0xFFC03300 - 0xFFC033FF) */
566#define HMDMA0_CONTROL 0xFFC03300 /* Handshake MDMA0 Control Register */
567#define HMDMA0_ECINIT 0xFFC03304 /* HMDMA0 Initial Edge Count Register */
568#define HMDMA0_BCINIT 0xFFC03308 /* HMDMA0 Initial Block Count Register */
569#define HMDMA0_ECURGENT 0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
570#define HMDMA0_ECOVERFLOW 0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
571#define HMDMA0_ECOUNT 0xFFC03314 /* HMDMA0 Current Edge Count Register */
572#define HMDMA0_BCOUNT 0xFFC03318 /* HMDMA0 Current Block Count Register */
573
574#define HMDMA1_CONTROL 0xFFC03340 /* Handshake MDMA1 Control Register */
575#define HMDMA1_ECINIT 0xFFC03344 /* HMDMA1 Initial Edge Count Register */
576#define HMDMA1_BCINIT 0xFFC03348 /* HMDMA1 Initial Block Count Register */
577#define HMDMA1_ECURGENT 0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
578#define HMDMA1_ECOVERFLOW 0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
579#define HMDMA1_ECOUNT 0xFFC03354 /* HMDMA1 Current Edge Count Register */
580#define HMDMA1_BCOUNT 0xFFC03358 /* HMDMA1 Current Block Count Register */
581
582/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
583#define PORTF_MUX 0xFFC03210 /* Port F mux control */
584#define PORTG_MUX 0xFFC03214 /* Port G mux control */
585#define PORTH_MUX 0xFFC03218 /* Port H mux control */
586#define PORTF_DRIVE 0xFFC03220 /* Port F drive strength control */
587#define PORTG_DRIVE 0xFFC03224 /* Port G drive strength control */
588#define PORTH_DRIVE 0xFFC03228 /* Port H drive strength control */
589#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
590#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
591#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
592#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
593#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
594#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
595#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
596#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
597#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
598
599
600/***********************************************************************************
601** System MMR Register Bits And Macros
602**
603** Disclaimer: All macros are intended to make C and Assembly code more readable.
604** Use these macros carefully, as any that do left shifts for field
605** depositing will result in the lower order bits being destroyed. Any
606** macro that shifts left to properly position the bit-field should be
607** used as part of an OR to initialize a register and NOT as a dynamic
608** modifier UNLESS the lower order bits are saved and ORed back in when
609** the macro is used.
610*************************************************************************************/
611/*
612** ********************* PLL AND RESET MASKS ****************************************/
613/* PLL_CTL Masks */
614#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
615#define PLL_OFF 0x0002 /* PLL Not Powered */
616#define STOPCK 0x0008 /* Core Clock Off */
617#define PDWN 0x0020 /* Enter Deep Sleep Mode */
618#define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
619#define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
620#define BYPASS 0x0100 /* Bypass the PLL */
621#define MSEL 0x7E00 /* Multiplier Select For CCLK/VCO Factors */
622/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
623#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
624
625/* PLL_DIV Masks */
626#define SSEL 0x000F /* System Select */
627#define CSEL 0x0030 /* Core Select */
628#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
629#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
630#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
631#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
632/* PLL_DIV Macros */
633#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
634
635/* VR_CTL Masks */
636#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
637#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
638#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
639#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
640#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
641
642#define GAIN 0x000C /* Voltage Level Gain */
643#define GAIN_5 0x0000 /* GAIN = 5 */
644#define GAIN_10 0x0004 /* GAIN = 10 */
645#define GAIN_20 0x0008 /* GAIN = 20 */
646#define GAIN_50 0x000C /* GAIN = 50 */
647
648#define VLEV 0x00F0 /* Internal Voltage Level */
649#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
650#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
651#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
652#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
653#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
654#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
655#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
656#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
657#define VLEV_125 0x00E0 /* VLEV = 1.25 V (-5% - +10% Accuracy) */
658#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
659
660#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
661#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
662#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
663#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
664#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
665#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
666
667/* PLL_STAT Masks */
668#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
669#define FULL_ON 0x0002 /* Processor In Full On Mode */
670#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
671#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
672
673/* CHIPID Masks */
674#define CHIPID_VERSION 0xF0000000
675#define CHIPID_FAMILY 0x0FFFF000
676#define CHIPID_MANUFACTURE 0x00000FFE
677
678/* SWRST Masks */
679#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
680#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
681#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
682#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
683#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
684
685/* SYSCR Masks */
686#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
687#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
688
689
690/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
691/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK */
692#define IRQ_PLL_WAKEUP 0x00000001 /* PLL Wakeup Interrupt */
693
694#define IRQ_ERROR1 0x00000002 /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
695#define IRQ_ERROR2 0x00000004 /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
696#define IRQ_RTC 0x00000008 /* Real Time Clock Interrupt */
697#define IRQ_DMA0 0x00000010 /* DMA Channel 0 (PPI) Interrupt */
698#define IRQ_DMA3 0x00000020 /* DMA Channel 3 (SPORT0 RX) Interrupt */
699#define IRQ_DMA4 0x00000040 /* DMA Channel 4 (SPORT0 TX) Interrupt */
700#define IRQ_DMA5 0x00000080 /* DMA Channel 5 (SPORT1 RX) Interrupt */
701
702#define IRQ_DMA6 0x00000100 /* DMA Channel 6 (SPORT1 TX) Interrupt */
703#define IRQ_TWI 0x00000200 /* TWI Interrupt */
704#define IRQ_DMA7 0x00000400 /* DMA Channel 7 (SPI) Interrupt */
705#define IRQ_DMA8 0x00000800 /* DMA Channel 8 (UART0 RX) Interrupt */
706#define IRQ_DMA9 0x00001000 /* DMA Channel 9 (UART0 TX) Interrupt */
707#define IRQ_DMA10 0x00002000 /* DMA Channel 10 (UART1 RX) Interrupt */
708#define IRQ_DMA11 0x00004000 /* DMA Channel 11 (UART1 TX) Interrupt */
709#define IRQ_CAN_RX 0x00008000 /* CAN Receive Interrupt */
710
711#define IRQ_CAN_TX 0x00010000 /* CAN Transmit Interrupt */
712#define IRQ_DMA1 0x00020000 /* DMA Channel 1 (Ethernet RX) Interrupt */
713#define IRQ_PFA_PORTH 0x00020000 /* PF Port H (PF47:32) Interrupt A */
714#define IRQ_DMA2 0x00040000 /* DMA Channel 2 (Ethernet TX) Interrupt */
715#define IRQ_PFB_PORTH 0x00040000 /* PF Port H (PF47:32) Interrupt B */
716#define IRQ_TIMER0 0x00080000 /* Timer 0 Interrupt */
717#define IRQ_TIMER1 0x00100000 /* Timer 1 Interrupt */
718#define IRQ_TIMER2 0x00200000 /* Timer 2 Interrupt */
719#define IRQ_TIMER3 0x00400000 /* Timer 3 Interrupt */
720#define IRQ_TIMER4 0x00800000 /* Timer 4 Interrupt */
721
722#define IRQ_TIMER5 0x01000000 /* Timer 5 Interrupt */
723#define IRQ_TIMER6 0x02000000 /* Timer 6 Interrupt */
724#define IRQ_TIMER7 0x04000000 /* Timer 7 Interrupt */
725#define IRQ_PFA_PORTFG 0x08000000 /* PF Ports F&G (PF31:0) Interrupt A */
726#define IRQ_PFB_PORTF 0x80000000 /* PF Port F (PF15:0) Interrupt B */
727#define IRQ_DMA12 0x20000000 /* DMA Channels 12 (MDMA1 Source) RX Interrupt */
728#define IRQ_DMA13 0x20000000 /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
729#define IRQ_DMA14 0x40000000 /* DMA Channels 14 (MDMA0 Source) RX Interrupt */
730#define IRQ_DMA15 0x40000000 /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
731#define IRQ_WDOG 0x80000000 /* Software Watchdog Timer Interrupt */
732#define IRQ_PFB_PORTG 0x10000000 /* PF Port G (PF31:16) Interrupt B */
733
734/* SIC_IAR0 Macros */
735#define P0_IVG(x) (((x)&0xF)-7) /* Peripheral #0 assigned IVG #x */
736#define P1_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #1 assigned IVG #x */
737#define P2_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #2 assigned IVG #x */
738#define P3_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #3 assigned IVG #x */
739#define P4_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #4 assigned IVG #x */
740#define P5_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #5 assigned IVG #x */
741#define P6_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #6 assigned IVG #x */
742#define P7_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #7 assigned IVG #x */
743
744/* SIC_IAR1 Macros */
745#define P8_IVG(x) (((x)&0xF)-7) /* Peripheral #8 assigned IVG #x */
746#define P9_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #9 assigned IVG #x */
747#define P10_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #10 assigned IVG #x */
748#define P11_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #11 assigned IVG #x */
749#define P12_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #12 assigned IVG #x */
750#define P13_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #13 assigned IVG #x */
751#define P14_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #14 assigned IVG #x */
752#define P15_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #15 assigned IVG #x */
753
754/* SIC_IAR2 Macros */
755#define P16_IVG(x) (((x)&0xF)-7) /* Peripheral #16 assigned IVG #x */
756#define P17_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #17 assigned IVG #x */
757#define P18_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #18 assigned IVG #x */
758#define P19_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #19 assigned IVG #x */
759#define P20_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #20 assigned IVG #x */
760#define P21_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #21 assigned IVG #x */
761#define P22_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #22 assigned IVG #x */
762#define P23_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #23 assigned IVG #x */
763
764/* SIC_IAR3 Macros */
765#define P24_IVG(x) (((x)&0xF)-7) /* Peripheral #24 assigned IVG #x */
766#define P25_IVG(x) (((x)&0xF)-7) << 0x4 /* Peripheral #25 assigned IVG #x */
767#define P26_IVG(x) (((x)&0xF)-7) << 0x8 /* Peripheral #26 assigned IVG #x */
768#define P27_IVG(x) (((x)&0xF)-7) << 0xC /* Peripheral #27 assigned IVG #x */
769#define P28_IVG(x) (((x)&0xF)-7) << 0x10 /* Peripheral #28 assigned IVG #x */
770#define P29_IVG(x) (((x)&0xF)-7) << 0x14 /* Peripheral #29 assigned IVG #x */
771#define P30_IVG(x) (((x)&0xF)-7) << 0x18 /* Peripheral #30 assigned IVG #x */
772#define P31_IVG(x) (((x)&0xF)-7) << 0x1C /* Peripheral #31 assigned IVG #x */
773
774
775/* SIC_IMASK Masks */
776#define SIC_UNMASK_ALL 0x00000000 /* Unmask all peripheral interrupts */
777#define SIC_MASK_ALL 0xFFFFFFFF /* Mask all peripheral interrupts */
778#define SIC_MASK(x) (1 << ((x)&0x1F)) /* Mask Peripheral #x interrupt */
779#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Unmask Peripheral #x interrupt */
780
781/* SIC_IWR Masks */
782#define IWR_DISABLE_ALL 0x00000000 /* Wakeup Disable all peripherals */
783#define IWR_ENABLE_ALL 0xFFFFFFFF /* Wakeup Enable all peripherals */
784#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
785#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
786
787
788/* ********* WATCHDOG TIMER MASKS ******************** */
789
790/* Watchdog Timer WDOG_CTL Register Masks */
791
792#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
793#define WDEV_RESET 0x0000 /* generate reset event on roll over */
794#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
795#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
796#define WDEV_NONE 0x0006 /* no event on roll over */
797#define WDEN 0x0FF0 /* enable watchdog */
798#define WDDIS 0x0AD0 /* disable watchdog */
799#define WDRO 0x8000 /* watchdog rolled over latch */
800
801/* depreciated WDOG_CTL Register Masks for legacy code */
802
803
804#define ICTL WDEV
805#define ENABLE_RESET WDEV_RESET
806#define WDOG_RESET WDEV_RESET
807#define ENABLE_NMI WDEV_NMI
808#define WDOG_NMI WDEV_NMI
809#define ENABLE_GPI WDEV_GPI
810#define WDOG_GPI WDEV_GPI
811#define DISABLE_EVT WDEV_NONE
812#define WDOG_NONE WDEV_NONE
813
814#define TMR_EN WDEN
815#define TMR_DIS WDDIS
816#define TRO WDRO
817#define ICTL_P0 0x01
818 #define ICTL_P1 0x02
819#define TRO_P 0x0F
820
821
822
823/* *************** REAL TIME CLOCK MASKS **************************/
824/* RTC_STAT and RTC_ALARM Masks */
825#define RTC_SEC 0x0000003F /* Real-Time Clock Seconds */
826#define RTC_MIN 0x00000FC0 /* Real-Time Clock Minutes */
827#define RTC_HR 0x0001F000 /* Real-Time Clock Hours */
828#define RTC_DAY 0xFFFE0000 /* Real-Time Clock Days */
829
830/* RTC_ALARM Macro z=day y=hr x=min w=sec */
831#define SET_ALARM(z,y,x,w) ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
832
833/* RTC_ICTL and RTC_ISTAT Masks */
834#define STOPWATCH 0x0001 /* Stopwatch Interrupt Enable */
835#define ALARM 0x0002 /* Alarm Interrupt Enable */
836#define SECOND 0x0004 /* Seconds (1 Hz) Interrupt Enable */
837#define MINUTE 0x0008 /* Minutes Interrupt Enable */
838#define HOUR 0x0010 /* Hours Interrupt Enable */
839#define DAY 0x0020 /* 24 Hours (Days) Interrupt Enable */
840#define DAY_ALARM 0x0040 /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable */
841#define WRITE_PENDING 0x4000 /* Write Pending Status */
842#define WRITE_COMPLETE 0x8000 /* Write Complete Interrupt Enable */
843
844/* RTC_FAST / RTC_PREN Mask */
845#define PREN 0x0001 /* Enable Prescaler, RTC Runs @1 Hz */
846
847
848/* ************** UART CONTROLLER MASKS *************************/
849/* UARTx_LCR Masks */
850#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
851#define STB 0x04 /* Stop Bits */
852#define PEN 0x08 /* Parity Enable */
853#define EPS 0x10 /* Even Parity Select */
854#define STP 0x20 /* Stick Parity */
855#define SB 0x40 /* Set Break */
856#define DLAB 0x80 /* Divisor Latch Access */
857
858/* UARTx_MCR Mask */
859#define LOOP_ENA 0x10 /* Loopback Mode Enable */
860#define LOOP_ENA_P 0x04
861
862/* UARTx_LSR Masks */
863#define DR 0x01 /* Data Ready */
864#define OE 0x02 /* Overrun Error */
865#define PE 0x04 /* Parity Error */
866#define FE 0x08 /* Framing Error */
867#define BI 0x10 /* Break Interrupt */
868#define THRE 0x20 /* THR Empty */
869#define TEMT 0x40 /* TSR and UART_THR Empty */
870
871/* UARTx_IER Masks */
872#define ERBFI 0x01 /* Enable Receive Buffer Full Interrupt */
873#define ETBEI 0x02 /* Enable Transmit Buffer Empty Interrupt */
874#define ELSI 0x04 /* Enable RX Status Interrupt */
875
876/* UARTx_IIR Masks */
877#define NINT 0x01 /* Pending Interrupt */
878#define IIR_TX_READY 0x02 /* UART_THR empty */
879#define IIR_RX_READY 0x04 /* Receive data ready */
880#define IIR_LINE_CHANGE 0x06 /* Receive line status */
881#define IIR_STATUS 0x06 /* Highest Priority Pending Interrupt */
882
883/* UARTx_GCTL Masks */
884#define UCEN 0x01 /* Enable UARTx Clocks */
885#define IREN 0x02 /* Enable IrDA Mode */
886#define TPOLC 0x04 /* IrDA TX Polarity Change */
887#define RPOLC 0x08 /* IrDA RX Polarity Change */
888#define FPE 0x10 /* Force Parity Error On Transmit */
889#define FFE 0x20 /* Force Framing Error On Transmit */
890
891
892/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
893/* SPI_CTL Masks */
894#define TIMOD 0x0003 /* Transfer Initiate Mode */
895#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
896#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
897#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
898#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
899#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
900#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
901#define PSSE 0x0010 /* Slave-Select Input Enable */
902#define EMISO 0x0020 /* Enable MISO As Output */
903#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
904#define LSBF 0x0200 /* LSB First */
905#define CPHA 0x0400 /* Clock Phase */
906#define CPOL 0x0800 /* Clock Polarity */
907#define MSTR 0x1000 /* Master/Slave* */
908#define WOM 0x2000 /* Write Open Drain Master */
909#define SPE 0x4000 /* SPI Enable */
910
911/* SPI_FLG Masks */
912#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
913#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
914#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
915#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
916#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
917#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
918#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
919#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
920#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
921#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
922#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
923#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
924#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
925#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
926
927/* SPI_STAT Masks */
928#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
929#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
930#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
931#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
932#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
933#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
934#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
935
936
937/* **************** GENERAL PURPOSE TIMER MASKS **********************/
938/* TIMER_ENABLE Masks */
939#define TIMEN0 0x0001 /* Enable Timer 0 */
940#define TIMEN1 0x0002 /* Enable Timer 1 */
941#define TIMEN2 0x0004 /* Enable Timer 2 */
942#define TIMEN3 0x0008 /* Enable Timer 3 */
943#define TIMEN4 0x0010 /* Enable Timer 4 */
944#define TIMEN5 0x0020 /* Enable Timer 5 */
945#define TIMEN6 0x0040 /* Enable Timer 6 */
946#define TIMEN7 0x0080 /* Enable Timer 7 */
947
948/* TIMER_DISABLE Masks */
949#define TIMDIS0 TIMEN0 /* Disable Timer 0 */
950#define TIMDIS1 TIMEN1 /* Disable Timer 1 */
951#define TIMDIS2 TIMEN2 /* Disable Timer 2 */
952#define TIMDIS3 TIMEN3 /* Disable Timer 3 */
953#define TIMDIS4 TIMEN4 /* Disable Timer 4 */
954#define TIMDIS5 TIMEN5 /* Disable Timer 5 */
955#define TIMDIS6 TIMEN6 /* Disable Timer 6 */
956#define TIMDIS7 TIMEN7 /* Disable Timer 7 */
957
958/* TIMER_STATUS Masks */
959#define TIMIL0 0x00000001 /* Timer 0 Interrupt */
960#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
961#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
962#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
963#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
964#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
965#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
966#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
967#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
968#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
969#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
970#define TRUN3 0x00008000 /* Timer 3 Slave Enable Status */
971#define TIMIL4 0x00010000 /* Timer 4 Interrupt */
972#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
973#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
974#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
975#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
976#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
977#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
978#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
979#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
980#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
981#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
982#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
983
984/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
985#define TOVL_ERR0 TOVF_ERR0
986#define TOVL_ERR1 TOVF_ERR1
987#define TOVL_ERR2 TOVF_ERR2
988#define TOVL_ERR3 TOVF_ERR3
989#define TOVL_ERR4 TOVF_ERR4
990#define TOVL_ERR5 TOVF_ERR5
991#define TOVL_ERR6 TOVF_ERR6
992#define TOVL_ERR7 TOVF_ERR7
993
994/* TIMERx_CONFIG Masks */
995#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
996#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
997#define EXT_CLK 0x0003 /* External Clock Mode */
998#define PULSE_HI 0x0004 /* Action Pulse (Positive/Negative*) */
999#define PERIOD_CNT 0x0008 /* Period Count */
1000#define IRQ_ENA 0x0010 /* Interrupt Request Enable */
1001#define TIN_SEL 0x0020 /* Timer Input Select */
1002#define OUT_DIS 0x0040 /* Output Pad Disable */
1003#define CLK_SEL 0x0080 /* Timer Clock Select */
1004#define TOGGLE_HI 0x0100 /* PWM_OUT PULSE_HI Toggle Mode */
1005#define EMU_RUN 0x0200 /* Emulation Behavior Select */
1006#define ERR_TYP 0xC000 /* Error Type */
1007
1008
1009/* ****************** GPIO PORTS F, G, H MASKS ***********************/
1010/* General Purpose IO (0xFFC00700 - 0xFFC007FF) Masks */
1011/* Port F Masks */
1012#define PF0 0x0001
1013#define PF1 0x0002
1014#define PF2 0x0004
1015#define PF3 0x0008
1016#define PF4 0x0010
1017#define PF5 0x0020
1018#define PF6 0x0040
1019#define PF7 0x0080
1020#define PF8 0x0100
1021#define PF9 0x0200
1022#define PF10 0x0400
1023#define PF11 0x0800
1024#define PF12 0x1000
1025#define PF13 0x2000
1026#define PF14 0x4000
1027#define PF15 0x8000
1028
1029/* Port G Masks */
1030#define PG0 0x0001
1031#define PG1 0x0002
1032#define PG2 0x0004
1033#define PG3 0x0008
1034#define PG4 0x0010
1035#define PG5 0x0020
1036#define PG6 0x0040
1037#define PG7 0x0080
1038#define PG8 0x0100
1039#define PG9 0x0200
1040#define PG10 0x0400
1041#define PG11 0x0800
1042#define PG12 0x1000
1043#define PG13 0x2000
1044#define PG14 0x4000
1045#define PG15 0x8000
1046
1047/* Port H Masks */
1048#define PH0 0x0001
1049#define PH1 0x0002
1050#define PH2 0x0004
1051#define PH3 0x0008
1052#define PH4 0x0010
1053#define PH5 0x0020
1054#define PH6 0x0040
1055#define PH7 0x0080
1056#define PH8 0x0100
1057#define PH9 0x0200
1058#define PH10 0x0400
1059#define PH11 0x0800
1060#define PH12 0x1000
1061#define PH13 0x2000
1062#define PH14 0x4000
1063#define PH15 0x8000
1064
1065
1066/* ******************* SERIAL PORT MASKS **************************************/
1067/* SPORTx_TCR1 Masks */
1068#define TSPEN 0x0001 /* Transmit Enable */
1069#define ITCLK 0x0002 /* Internal Transmit Clock Select */
1070#define DTYPE_NORM 0x0004 /* Data Format Normal */
1071#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1072#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1073#define TLSBIT 0x0010 /* Transmit Bit Order */
1074#define ITFS 0x0200 /* Internal Transmit Frame Sync Select */
1075#define TFSR 0x0400 /* Transmit Frame Sync Required Select */
1076#define DITFS 0x0800 /* Data-Independent Transmit Frame Sync Select */
1077#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
1078#define LATFS 0x2000 /* Late Transmit Frame Sync Select */
1079#define TCKFE 0x4000 /* Clock Falling Edge Select */
1080
1081/* SPORTx_TCR2 Masks and Macro */
1082#define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
1083#define TXSE 0x0100 /* TX Secondary Enable */
1084#define TSFSE 0x0200 /* Transmit Stereo Frame Sync Enable */
1085#define TRFST 0x0400 /* Left/Right Order (1 = Right Channel 1st) */
1086
1087/* SPORTx_RCR1 Masks */
1088#define RSPEN 0x0001 /* Receive Enable */
1089#define IRCLK 0x0002 /* Internal Receive Clock Select */
1090#define DTYPE_NORM 0x0004 /* Data Format Normal */
1091#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
1092#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
1093#define RLSBIT 0x0010 /* Receive Bit Order */
1094#define IRFS 0x0200 /* Internal Receive Frame Sync Select */
1095#define RFSR 0x0400 /* Receive Frame Sync Required Select */
1096#define LRFS 0x1000 /* Low Receive Frame Sync Select */
1097#define LARFS 0x2000 /* Late Receive Frame Sync Select */
1098#define RCKFE 0x4000 /* Clock Falling Edge Select */
1099
1100/* SPORTx_RCR2 Masks */
1101#define SLEN(x) ((x)&0x1F) /* SPORT RX Word Length (2 - 31) */
1102#define RXSE 0x0100 /* RX Secondary Enable */
1103#define RSFSE 0x0200 /* RX Stereo Frame Sync Enable */
1104#define RRFST 0x0400 /* Right-First Data Order */
1105
1106/* SPORTx_STAT Masks */
1107#define RXNE 0x0001 /* Receive FIFO Not Empty Status */
1108#define RUVF 0x0002 /* Sticky Receive Underflow Status */
1109#define ROVF 0x0004 /* Sticky Receive Overflow Status */
1110#define TXF 0x0008 /* Transmit FIFO Full Status */
1111#define TUVF 0x0010 /* Sticky Transmit Underflow Status */
1112#define TOVF 0x0020 /* Sticky Transmit Overflow Status */
1113#define TXHRE 0x0040 /* Transmit Hold Register Empty */
1114
1115/* SPORTx_MCMC1 Macros */
1116#define SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
1117
1118/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits */
1119#define SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
1120
1121/* SPORTx_MCMC2 Masks */
1122#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
1123#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
1124#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
1125#define MCDTXPE 0x0004 /* Multichannel DMA Transmit Packing */
1126#define MCDRXPE 0x0008 /* Multichannel DMA Receive Packing */
1127#define MCMEN 0x0010 /* Multichannel Frame Mode Enable */
1128#define FSDR 0x0080 /* Multichannel Frame Sync to Data Relationship */
1129#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
1130#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
1131#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
1132#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
1133#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
1134#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
1135#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
1136#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
1137#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
1138#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
1139#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
1140#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
1141#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
1142#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
1143#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
1144#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
1145
1146
1147/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS *************************/
1148/* EBIU_AMGCTL Masks */
1149#define AMCKEN 0x0001 /* Enable CLKOUT */
1150#define AMBEN_NONE 0x0000 /* All Banks Disabled */
1151#define AMBEN_B0 0x0002 /* Enable Async Memory Bank 0 only */
1152#define AMBEN_B0_B1 0x0004 /* Enable Async Memory Banks 0 & 1 only */
1153#define AMBEN_B0_B1_B2 0x0006 /* Enable Async Memory Banks 0, 1, and 2 */
1154#define AMBEN_ALL 0x0008 /* Enable Async Memory Banks (all) 0, 1, 2, and 3 */
1155
1156/* EBIU_AMBCTL0 Masks */
1157#define B0RDYEN 0x00000001 /* Bank 0 (B0) RDY Enable */
1158#define B0RDYPOL 0x00000002 /* B0 RDY Active High */
1159#define B0TT_1 0x00000004 /* B0 Transition Time (Read to Write) = 1 cycle */
1160#define B0TT_2 0x00000008 /* B0 Transition Time (Read to Write) = 2 cycles */
1161#define B0TT_3 0x0000000C /* B0 Transition Time (Read to Write) = 3 cycles */
1162#define B0TT_4 0x00000000 /* B0 Transition Time (Read to Write) = 4 cycles */
1163#define B0ST_1 0x00000010 /* B0 Setup Time (AOE to Read/Write) = 1 cycle */
1164#define B0ST_2 0x00000020 /* B0 Setup Time (AOE to Read/Write) = 2 cycles */
1165#define B0ST_3 0x00000030 /* B0 Setup Time (AOE to Read/Write) = 3 cycles */
1166#define B0ST_4 0x00000000 /* B0 Setup Time (AOE to Read/Write) = 4 cycles */
1167#define B0HT_1 0x00000040 /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1168#define B0HT_2 0x00000080 /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1169#define B0HT_3 0x000000C0 /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1170#define B0HT_0 0x00000000 /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1171#define B0RAT_1 0x00000100 /* B0 Read Access Time = 1 cycle */
1172#define B0RAT_2 0x00000200 /* B0 Read Access Time = 2 cycles */
1173#define B0RAT_3 0x00000300 /* B0 Read Access Time = 3 cycles */
1174#define B0RAT_4 0x00000400 /* B0 Read Access Time = 4 cycles */
1175#define B0RAT_5 0x00000500 /* B0 Read Access Time = 5 cycles */
1176#define B0RAT_6 0x00000600 /* B0 Read Access Time = 6 cycles */
1177#define B0RAT_7 0x00000700 /* B0 Read Access Time = 7 cycles */
1178#define B0RAT_8 0x00000800 /* B0 Read Access Time = 8 cycles */
1179#define B0RAT_9 0x00000900 /* B0 Read Access Time = 9 cycles */
1180#define B0RAT_10 0x00000A00 /* B0 Read Access Time = 10 cycles */
1181#define B0RAT_11 0x00000B00 /* B0 Read Access Time = 11 cycles */
1182#define B0RAT_12 0x00000C00 /* B0 Read Access Time = 12 cycles */
1183#define B0RAT_13 0x00000D00 /* B0 Read Access Time = 13 cycles */
1184#define B0RAT_14 0x00000E00 /* B0 Read Access Time = 14 cycles */
1185#define B0RAT_15 0x00000F00 /* B0 Read Access Time = 15 cycles */
1186#define B0WAT_1 0x00001000 /* B0 Write Access Time = 1 cycle */
1187#define B0WAT_2 0x00002000 /* B0 Write Access Time = 2 cycles */
1188#define B0WAT_3 0x00003000 /* B0 Write Access Time = 3 cycles */
1189#define B0WAT_4 0x00004000 /* B0 Write Access Time = 4 cycles */
1190#define B0WAT_5 0x00005000 /* B0 Write Access Time = 5 cycles */
1191#define B0WAT_6 0x00006000 /* B0 Write Access Time = 6 cycles */
1192#define B0WAT_7 0x00007000 /* B0 Write Access Time = 7 cycles */
1193#define B0WAT_8 0x00008000 /* B0 Write Access Time = 8 cycles */
1194#define B0WAT_9 0x00009000 /* B0 Write Access Time = 9 cycles */
1195#define B0WAT_10 0x0000A000 /* B0 Write Access Time = 10 cycles */
1196#define B0WAT_11 0x0000B000 /* B0 Write Access Time = 11 cycles */
1197#define B0WAT_12 0x0000C000 /* B0 Write Access Time = 12 cycles */
1198#define B0WAT_13 0x0000D000 /* B0 Write Access Time = 13 cycles */
1199#define B0WAT_14 0x0000E000 /* B0 Write Access Time = 14 cycles */
1200#define B0WAT_15 0x0000F000 /* B0 Write Access Time = 15 cycles */
1201
1202#define B1RDYEN 0x00010000 /* Bank 1 (B1) RDY Enable */
1203#define B1RDYPOL 0x00020000 /* B1 RDY Active High */
1204#define B1TT_1 0x00040000 /* B1 Transition Time (Read to Write) = 1 cycle */
1205#define B1TT_2 0x00080000 /* B1 Transition Time (Read to Write) = 2 cycles */
1206#define B1TT_3 0x000C0000 /* B1 Transition Time (Read to Write) = 3 cycles */
1207#define B1TT_4 0x00000000 /* B1 Transition Time (Read to Write) = 4 cycles */
1208#define B1ST_1 0x00100000 /* B1 Setup Time (AOE to Read/Write) = 1 cycle */
1209#define B1ST_2 0x00200000 /* B1 Setup Time (AOE to Read/Write) = 2 cycles */
1210#define B1ST_3 0x00300000 /* B1 Setup Time (AOE to Read/Write) = 3 cycles */
1211#define B1ST_4 0x00000000 /* B1 Setup Time (AOE to Read/Write) = 4 cycles */
1212#define B1HT_1 0x00400000 /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1213#define B1HT_2 0x00800000 /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1214#define B1HT_3 0x00C00000 /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1215#define B1HT_0 0x00000000 /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1216#define B1RAT_1 0x01000000 /* B1 Read Access Time = 1 cycle */
1217#define B1RAT_2 0x02000000 /* B1 Read Access Time = 2 cycles */
1218#define B1RAT_3 0x03000000 /* B1 Read Access Time = 3 cycles */
1219#define B1RAT_4 0x04000000 /* B1 Read Access Time = 4 cycles */
1220#define B1RAT_5 0x05000000 /* B1 Read Access Time = 5 cycles */
1221#define B1RAT_6 0x06000000 /* B1 Read Access Time = 6 cycles */
1222#define B1RAT_7 0x07000000 /* B1 Read Access Time = 7 cycles */
1223#define B1RAT_8 0x08000000 /* B1 Read Access Time = 8 cycles */
1224#define B1RAT_9 0x09000000 /* B1 Read Access Time = 9 cycles */
1225#define B1RAT_10 0x0A000000 /* B1 Read Access Time = 10 cycles */
1226#define B1RAT_11 0x0B000000 /* B1 Read Access Time = 11 cycles */
1227#define B1RAT_12 0x0C000000 /* B1 Read Access Time = 12 cycles */
1228#define B1RAT_13 0x0D000000 /* B1 Read Access Time = 13 cycles */
1229#define B1RAT_14 0x0E000000 /* B1 Read Access Time = 14 cycles */
1230#define B1RAT_15 0x0F000000 /* B1 Read Access Time = 15 cycles */
1231#define B1WAT_1 0x10000000 /* B1 Write Access Time = 1 cycle */
1232#define B1WAT_2 0x20000000 /* B1 Write Access Time = 2 cycles */
1233#define B1WAT_3 0x30000000 /* B1 Write Access Time = 3 cycles */
1234#define B1WAT_4 0x40000000 /* B1 Write Access Time = 4 cycles */
1235#define B1WAT_5 0x50000000 /* B1 Write Access Time = 5 cycles */
1236#define B1WAT_6 0x60000000 /* B1 Write Access Time = 6 cycles */
1237#define B1WAT_7 0x70000000 /* B1 Write Access Time = 7 cycles */
1238#define B1WAT_8 0x80000000 /* B1 Write Access Time = 8 cycles */
1239#define B1WAT_9 0x90000000 /* B1 Write Access Time = 9 cycles */
1240#define B1WAT_10 0xA0000000 /* B1 Write Access Time = 10 cycles */
1241#define B1WAT_11 0xB0000000 /* B1 Write Access Time = 11 cycles */
1242#define B1WAT_12 0xC0000000 /* B1 Write Access Time = 12 cycles */
1243#define B1WAT_13 0xD0000000 /* B1 Write Access Time = 13 cycles */
1244#define B1WAT_14 0xE0000000 /* B1 Write Access Time = 14 cycles */
1245#define B1WAT_15 0xF0000000 /* B1 Write Access Time = 15 cycles */
1246
1247/* EBIU_AMBCTL1 Masks */
1248#define B2RDYEN 0x00000001 /* Bank 2 (B2) RDY Enable */
1249#define B2RDYPOL 0x00000002 /* B2 RDY Active High */
1250#define B2TT_1 0x00000004 /* B2 Transition Time (Read to Write) = 1 cycle */
1251#define B2TT_2 0x00000008 /* B2 Transition Time (Read to Write) = 2 cycles */
1252#define B2TT_3 0x0000000C /* B2 Transition Time (Read to Write) = 3 cycles */
1253#define B2TT_4 0x00000000 /* B2 Transition Time (Read to Write) = 4 cycles */
1254#define B2ST_1 0x00000010 /* B2 Setup Time (AOE to Read/Write) = 1 cycle */
1255#define B2ST_2 0x00000020 /* B2 Setup Time (AOE to Read/Write) = 2 cycles */
1256#define B2ST_3 0x00000030 /* B2 Setup Time (AOE to Read/Write) = 3 cycles */
1257#define B2ST_4 0x00000000 /* B2 Setup Time (AOE to Read/Write) = 4 cycles */
1258#define B2HT_1 0x00000040 /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1259#define B2HT_2 0x00000080 /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1260#define B2HT_3 0x000000C0 /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1261#define B2HT_0 0x00000000 /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1262#define B2RAT_1 0x00000100 /* B2 Read Access Time = 1 cycle */
1263#define B2RAT_2 0x00000200 /* B2 Read Access Time = 2 cycles */
1264#define B2RAT_3 0x00000300 /* B2 Read Access Time = 3 cycles */
1265#define B2RAT_4 0x00000400 /* B2 Read Access Time = 4 cycles */
1266#define B2RAT_5 0x00000500 /* B2 Read Access Time = 5 cycles */
1267#define B2RAT_6 0x00000600 /* B2 Read Access Time = 6 cycles */
1268#define B2RAT_7 0x00000700 /* B2 Read Access Time = 7 cycles */
1269#define B2RAT_8 0x00000800 /* B2 Read Access Time = 8 cycles */
1270#define B2RAT_9 0x00000900 /* B2 Read Access Time = 9 cycles */
1271#define B2RAT_10 0x00000A00 /* B2 Read Access Time = 10 cycles */
1272#define B2RAT_11 0x00000B00 /* B2 Read Access Time = 11 cycles */
1273#define B2RAT_12 0x00000C00 /* B2 Read Access Time = 12 cycles */
1274#define B2RAT_13 0x00000D00 /* B2 Read Access Time = 13 cycles */
1275#define B2RAT_14 0x00000E00 /* B2 Read Access Time = 14 cycles */
1276#define B2RAT_15 0x00000F00 /* B2 Read Access Time = 15 cycles */
1277#define B2WAT_1 0x00001000 /* B2 Write Access Time = 1 cycle */
1278#define B2WAT_2 0x00002000 /* B2 Write Access Time = 2 cycles */
1279#define B2WAT_3 0x00003000 /* B2 Write Access Time = 3 cycles */
1280#define B2WAT_4 0x00004000 /* B2 Write Access Time = 4 cycles */
1281#define B2WAT_5 0x00005000 /* B2 Write Access Time = 5 cycles */
1282#define B2WAT_6 0x00006000 /* B2 Write Access Time = 6 cycles */
1283#define B2WAT_7 0x00007000 /* B2 Write Access Time = 7 cycles */
1284#define B2WAT_8 0x00008000 /* B2 Write Access Time = 8 cycles */
1285#define B2WAT_9 0x00009000 /* B2 Write Access Time = 9 cycles */
1286#define B2WAT_10 0x0000A000 /* B2 Write Access Time = 10 cycles */
1287#define B2WAT_11 0x0000B000 /* B2 Write Access Time = 11 cycles */
1288#define B2WAT_12 0x0000C000 /* B2 Write Access Time = 12 cycles */
1289#define B2WAT_13 0x0000D000 /* B2 Write Access Time = 13 cycles */
1290#define B2WAT_14 0x0000E000 /* B2 Write Access Time = 14 cycles */
1291#define B2WAT_15 0x0000F000 /* B2 Write Access Time = 15 cycles */
1292
1293#define B3RDYEN 0x00010000 /* Bank 3 (B3) RDY Enable */
1294#define B3RDYPOL 0x00020000 /* B3 RDY Active High */
1295#define B3TT_1 0x00040000 /* B3 Transition Time (Read to Write) = 1 cycle */
1296#define B3TT_2 0x00080000 /* B3 Transition Time (Read to Write) = 2 cycles */
1297#define B3TT_3 0x000C0000 /* B3 Transition Time (Read to Write) = 3 cycles */
1298#define B3TT_4 0x00000000 /* B3 Transition Time (Read to Write) = 4 cycles */
1299#define B3ST_1 0x00100000 /* B3 Setup Time (AOE to Read/Write) = 1 cycle */
1300#define B3ST_2 0x00200000 /* B3 Setup Time (AOE to Read/Write) = 2 cycles */
1301#define B3ST_3 0x00300000 /* B3 Setup Time (AOE to Read/Write) = 3 cycles */
1302#define B3ST_4 0x00000000 /* B3 Setup Time (AOE to Read/Write) = 4 cycles */
1303#define B3HT_1 0x00400000 /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle */
1304#define B3HT_2 0x00800000 /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles */
1305#define B3HT_3 0x00C00000 /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles */
1306#define B3HT_0 0x00000000 /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles */
1307#define B3RAT_1 0x01000000 /* B3 Read Access Time = 1 cycle */
1308#define B3RAT_2 0x02000000 /* B3 Read Access Time = 2 cycles */
1309#define B3RAT_3 0x03000000 /* B3 Read Access Time = 3 cycles */
1310#define B3RAT_4 0x04000000 /* B3 Read Access Time = 4 cycles */
1311#define B3RAT_5 0x05000000 /* B3 Read Access Time = 5 cycles */
1312#define B3RAT_6 0x06000000 /* B3 Read Access Time = 6 cycles */
1313#define B3RAT_7 0x07000000 /* B3 Read Access Time = 7 cycles */
1314#define B3RAT_8 0x08000000 /* B3 Read Access Time = 8 cycles */
1315#define B3RAT_9 0x09000000 /* B3 Read Access Time = 9 cycles */
1316#define B3RAT_10 0x0A000000 /* B3 Read Access Time = 10 cycles */
1317#define B3RAT_11 0x0B000000 /* B3 Read Access Time = 11 cycles */
1318#define B3RAT_12 0x0C000000 /* B3 Read Access Time = 12 cycles */
1319#define B3RAT_13 0x0D000000 /* B3 Read Access Time = 13 cycles */
1320#define B3RAT_14 0x0E000000 /* B3 Read Access Time = 14 cycles */
1321#define B3RAT_15 0x0F000000 /* B3 Read Access Time = 15 cycles */
1322#define B3WAT_1 0x10000000 /* B3 Write Access Time = 1 cycle */
1323#define B3WAT_2 0x20000000 /* B3 Write Access Time = 2 cycles */
1324#define B3WAT_3 0x30000000 /* B3 Write Access Time = 3 cycles */
1325#define B3WAT_4 0x40000000 /* B3 Write Access Time = 4 cycles */
1326#define B3WAT_5 0x50000000 /* B3 Write Access Time = 5 cycles */
1327#define B3WAT_6 0x60000000 /* B3 Write Access Time = 6 cycles */
1328#define B3WAT_7 0x70000000 /* B3 Write Access Time = 7 cycles */
1329#define B3WAT_8 0x80000000 /* B3 Write Access Time = 8 cycles */
1330#define B3WAT_9 0x90000000 /* B3 Write Access Time = 9 cycles */
1331#define B3WAT_10 0xA0000000 /* B3 Write Access Time = 10 cycles */
1332#define B3WAT_11 0xB0000000 /* B3 Write Access Time = 11 cycles */
1333#define B3WAT_12 0xC0000000 /* B3 Write Access Time = 12 cycles */
1334#define B3WAT_13 0xD0000000 /* B3 Write Access Time = 13 cycles */
1335#define B3WAT_14 0xE0000000 /* B3 Write Access Time = 14 cycles */
1336#define B3WAT_15 0xF0000000 /* B3 Write Access Time = 15 cycles */
1337
1338
1339/* ********************** SDRAM CONTROLLER MASKS **********************************************/
1340/* EBIU_SDGCTL Masks */
1341#define SCTLE 0x00000001 /* Enable SDRAM Signals */
1342#define CL_2 0x00000008 /* SDRAM CAS Latency = 2 cycles */
1343#define CL_3 0x0000000C /* SDRAM CAS Latency = 3 cycles */
1344#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1345#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1346#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1347#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1348#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1349#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
1350#define TRAS_4 0x00000100 /* SDRAM tRAS = 4 cycles */
1351#define TRAS_5 0x00000140 /* SDRAM tRAS = 5 cycles */
1352#define TRAS_6 0x00000180 /* SDRAM tRAS = 6 cycles */
1353#define TRAS_7 0x000001C0 /* SDRAM tRAS = 7 cycles */
1354#define TRAS_8 0x00000200 /* SDRAM tRAS = 8 cycles */
1355#define TRAS_9 0x00000240 /* SDRAM tRAS = 9 cycles */
1356#define TRAS_10 0x00000280 /* SDRAM tRAS = 10 cycles */
1357#define TRAS_11 0x000002C0 /* SDRAM tRAS = 11 cycles */
1358#define TRAS_12 0x00000300 /* SDRAM tRAS = 12 cycles */
1359#define TRAS_13 0x00000340 /* SDRAM tRAS = 13 cycles */
1360#define TRAS_14 0x00000380 /* SDRAM tRAS = 14 cycles */
1361#define TRAS_15 0x000003C0 /* SDRAM tRAS = 15 cycles */
1362#define TRP_1 0x00000800 /* SDRAM tRP = 1 cycle */
1363#define TRP_2 0x00001000 /* SDRAM tRP = 2 cycles */
1364#define TRP_3 0x00001800 /* SDRAM tRP = 3 cycles */
1365#define TRP_4 0x00002000 /* SDRAM tRP = 4 cycles */
1366#define TRP_5 0x00002800 /* SDRAM tRP = 5 cycles */
1367#define TRP_6 0x00003000 /* SDRAM tRP = 6 cycles */
1368#define TRP_7 0x00003800 /* SDRAM tRP = 7 cycles */
1369#define TRCD_1 0x00008000 /* SDRAM tRCD = 1 cycle */
1370#define TRCD_2 0x00010000 /* SDRAM tRCD = 2 cycles */
1371#define TRCD_3 0x00018000 /* SDRAM tRCD = 3 cycles */
1372#define TRCD_4 0x00020000 /* SDRAM tRCD = 4 cycles */
1373#define TRCD_5 0x00028000 /* SDRAM tRCD = 5 cycles */
1374#define TRCD_6 0x00030000 /* SDRAM tRCD = 6 cycles */
1375#define TRCD_7 0x00038000 /* SDRAM tRCD = 7 cycles */
1376#define TWR_1 0x00080000 /* SDRAM tWR = 1 cycle */
1377#define TWR_2 0x00100000 /* SDRAM tWR = 2 cycles */
1378#define TWR_3 0x00180000 /* SDRAM tWR = 3 cycles */
1379#define PUPSD 0x00200000 /* Power-Up Start Delay (15 SCLK Cycles Delay) */
1380#define PSM 0x00400000 /* Power-Up Sequence (Mode Register Before/After* Refresh) */
1381#define PSS 0x00800000 /* Enable Power-Up Sequence on Next SDRAM Access */
1382#define SRFS 0x01000000 /* Enable SDRAM Self-Refresh Mode */
1383#define EBUFE 0x02000000 /* Enable External Buffering Timing */
1384#define FBBRW 0x04000000 /* Enable Fast Back-To-Back Read To Write */
1385#define EMREN 0x10000000 /* Extended Mode Register Enable */
1386#define TCSR 0x20000000 /* Temp-Compensated Self-Refresh Value (85/45* Deg C) */
1387#define CDDBG 0x40000000 /* Tristate SDRAM Controls During Bus Grant */
1388
1389/* EBIU_SDBCTL Masks */
1390#define EBE 0x0001 /* Enable SDRAM External Bank */
1391#define EBSZ_16 0x0000 /* SDRAM External Bank Size = 16MB */
1392#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1393#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1394#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1395#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1396#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1397#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1398#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1399#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
1400#define EBCAW_11 0x0030 /* SDRAM External Bank Column Address Width = 11 Bits */
1401
1402/* EBIU_SDSTAT Masks */
1403#define SDCI 0x0001 /* SDRAM Controller Idle */
1404#define SDSRA 0x0002 /* SDRAM Self-Refresh Active */
1405#define SDPUA 0x0004 /* SDRAM Power-Up Active */
1406#define SDRS 0x0008 /* SDRAM Will Power-Up On Next Access */
1407#define SDEASE 0x0010 /* SDRAM EAB Sticky Error Status */
1408#define BGSTAT 0x0020 /* Bus Grant Status */
1409
1410
1411/* ************************** DMA CONTROLLER MASKS ********************************/
1412/* DMAx_CONFIG, MDMA_yy_CONFIG Masks */
1413#define DMAEN 0x0001 /* DMA Channel Enable */
1414#define WNR 0x0002 /* Channel Direction (W/R*) */
1415#define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
1416#define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
1417#define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
1418#define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
1419#define RESTART 0x0020 /* DMA Buffer Clear */
1420#define DI_SEL 0x0040 /* Data Interrupt Timing Select */
1421#define DI_EN 0x0080 /* Data Interrupt Enable */
1422#define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
1423#define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
1424#define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
1425#define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
1426#define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
1427#define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
1428#define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
1429#define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
1430#define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
1431#define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
1432#define NDSIZE 0x0900 /* Next Descriptor Size */
1433#define DMAFLOW 0x7000 /* Flow Control */
1434#define DMAFLOW_STOP 0x0000 /* Stop Mode */
1435#define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
1436#define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
1437#define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
1438#define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
1439
1440/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
1441#define CTYPE 0x0040 /* DMA Channel Type Indicator (Memory/Peripheral*) */
1442#define PMAP 0xF000 /* Peripheral Mapped To This Channel */
1443#define PMAP_PPI 0x0000 /* PPI Port DMA */
1444#define PMAP_EMACRX 0x1000 /* Ethernet Receive DMA */
1445#define PMAP_EMACTX 0x2000 /* Ethernet Transmit DMA */
1446#define PMAP_SPORT0RX 0x3000 /* SPORT0 Receive DMA */
1447#define PMAP_SPORT0TX 0x4000 /* SPORT0 Transmit DMA */
1448#define PMAP_SPORT1RX 0x5000 /* SPORT1 Receive DMA */
1449#define PMAP_SPORT1TX 0x6000 /* SPORT1 Transmit DMA */
1450#define PMAP_SPI 0x7000 /* SPI Port DMA */
1451#define PMAP_UART0RX 0x8000 /* UART0 Port Receive DMA */
1452#define PMAP_UART0TX 0x9000 /* UART0 Port Transmit DMA */
1453#define PMAP_UART1RX 0xA000 /* UART1 Port Receive DMA */
1454#define PMAP_UART1TX 0xB000 /* UART1 Port Transmit DMA */
1455
1456/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
1457#define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
1458#define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
1459#define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
1460#define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
1461
1462
1463/* ************ PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
1464/* PPI_CONTROL Masks */
1465#define PORT_EN 0x0001 /* PPI Port Enable */
1466#define PORT_DIR 0x0002 /* PPI Port Direction */
1467#define XFR_TYPE 0x000C /* PPI Transfer Type */
1468#define PORT_CFG 0x0030 /* PPI Port Configuration */
1469#define FLD_SEL 0x0040 /* PPI Active Field Select */
1470#define PACK_EN 0x0080 /* PPI Packing Mode */
1471#define DMA32 0x0100 /* PPI 32-bit DMA Enable */
1472#define SKIP_EN 0x0200 /* PPI Skip Element Enable */
1473#define SKIP_EO 0x0400 /* PPI Skip Even/Odd Elements */
1474#define DLEN_8 0x0000 /* Data Length = 8 Bits */
1475#define DLEN_10 0x0800 /* Data Length = 10 Bits */
1476#define DLEN_11 0x1000 /* Data Length = 11 Bits */
1477#define DLEN_12 0x1800 /* Data Length = 12 Bits */
1478#define DLEN_13 0x2000 /* Data Length = 13 Bits */
1479#define DLEN_14 0x2800 /* Data Length = 14 Bits */
1480#define DLEN_15 0x3000 /* Data Length = 15 Bits */
1481#define DLEN_16 0x3800 /* Data Length = 16 Bits */
1482#define DLENGTH 0x3800 /* PPI Data Length */
1483#define POLC 0x4000 /* PPI Clock Polarity */
1484#define POLS 0x8000 /* PPI Frame Sync Polarity */
1485
1486/* PPI_STATUS Masks */
1487#define FLD 0x0400 /* Field Indicator */
1488#define FT_ERR 0x0800 /* Frame Track Error */
1489#define OVR 0x1000 /* FIFO Overflow Error */
1490#define UNDR 0x2000 /* FIFO Underrun Error */
1491#define ERR_DET 0x4000 /* Error Detected Indicator */
1492#define ERR_NCOR 0x8000 /* Error Not Corrected Indicator */
1493
1494
1495/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ***********************/
1496/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
1497#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
1498#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
1499
1500/* TWI_PRESCALE Masks */
1501#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
1502#define TWI_ENA 0x0080 /* TWI Enable */
1503#define SCCB 0x0200 /* SCCB Compatibility Enable */
1504
1505/* TWI_SLAVE_CTRL Masks */
1506#define SEN 0x0001 /* Slave Enable */
1507#define SADD_LEN 0x0002 /* Slave Address Length */
1508#define STDVAL 0x0004 /* Slave Transmit Data Valid */
1509#define NAK 0x0008 /* NAK/ACK* Generated At Conclusion Of Transfer */
1510#define GEN 0x0010 /* General Call Adrress Matching Enabled */
1511
1512/* TWI_SLAVE_STAT Masks */
1513#define SDIR 0x0001 /* Slave Transfer Direction (Transmit/Receive*) */
1514#define GCALL 0x0002 /* General Call Indicator */
1515
1516/* TWI_MASTER_CTRL Masks */
1517#define MEN 0x0001 /* Master Mode Enable */
1518#define MADD_LEN 0x0002 /* Master Address Length */
1519#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
1520#define FAST 0x0008 /* Use Fast Mode Timing Specs */
1521#define STOP 0x0010 /* Issue Stop Condition */
1522#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
1523#define DCNT 0x3FC0 /* Data Bytes To Transfer */
1524#define SDAOVR 0x4000 /* Serial Data Override */
1525#define SCLOVR 0x8000 /* Serial Clock Override */
1526
1527/* TWI_MASTER_STAT Masks */
1528#define MPROG 0x0001 /* Master Transfer In Progress */
1529#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
1530#define ANAK 0x0004 /* Address Not Acknowledged */
1531#define DNAK 0x0008 /* Data Not Acknowledged */
1532#define BUFRDERR 0x0010 /* Buffer Read Error */
1533#define BUFWRERR 0x0020 /* Buffer Write Error */
1534#define SDASEN 0x0040 /* Serial Data Sense */
1535#define SCLSEN 0x0080 /* Serial Clock Sense */
1536#define BUSBUSY 0x0100 /* Bus Busy Indicator */
1537
1538/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
1539#define SINIT 0x0001 /* Slave Transfer Initiated */
1540#define SCOMP 0x0002 /* Slave Transfer Complete */
1541#define SERR 0x0004 /* Slave Transfer Error */
1542#define SOVF 0x0008 /* Slave Overflow */
1543#define MCOMP 0x0010 /* Master Transfer Complete */
1544#define MERR 0x0020 /* Master Transfer Error */
1545#define XMTSERV 0x0040 /* Transmit FIFO Service */
1546#define RCVSERV 0x0080 /* Receive FIFO Service */
1547
1548/* TWI_FIFO_CTRL Masks */
1549#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
1550#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
1551#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
1552#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
1553
1554/* TWI_FIFO_STAT Masks */
1555#define XMTSTAT 0x0003 /* Transmit FIFO Status */
1556#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
1557#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
1558#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
1559
1560#define RCVSTAT 0x000C /* Receive FIFO Status */
1561#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
1562#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
1563#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
1564
1565
1566/* Omit CAN masks from defBF534.h */
1567
1568/* ******************* PIN CONTROL REGISTER MASKS ************************/
1569/* PORT_MUX Masks */
1570#define PJSE 0x0001 /* Port J SPI/SPORT Enable */
1571#define PJSE_SPORT 0x0000 /* Enable TFS0/DT0PRI */
1572#define PJSE_SPI 0x0001 /* Enable SPI_SSEL3:2 */
1573
1574#define PJCE(x) (((x)&0x3)<<1) /* Port J CAN/SPI/SPORT Enable */
1575#define PJCE_SPORT 0x0000 /* Enable DR0SEC/DT0SEC */
1576#define PJCE_CAN 0x0002 /* Enable CAN RX/TX */
1577#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
1578
1579#define PFDE 0x0008 /* Port F DMA Request Enable */
1580#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
1581#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
1582
1583#define PFTE 0x0010 /* Port F Timer Enable */
1584#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
1585#define PFTE_TIMER 0x0010 /* Enable TMR7:6 */
1586
1587#define PFS6E 0x0020 /* Port F SPI SSEL 6 Enable */
1588#define PFS6E_TIMER 0x0000 /* Enable TMR5 */
1589#define PFS6E_SPI 0x0020 /* Enable SPI_SSEL6 */
1590
1591#define PFS5E 0x0040 /* Port F SPI SSEL 5 Enable */
1592#define PFS5E_TIMER 0x0000 /* Enable TMR4 */
1593#define PFS5E_SPI 0x0040 /* Enable SPI_SSEL5 */
1594
1595#define PFS4E 0x0080 /* Port F SPI SSEL 4 Enable */
1596#define PFS4E_TIMER 0x0000 /* Enable TMR3 */
1597#define PFS4E_SPI 0x0080 /* Enable SPI_SSEL4 */
1598
1599#define PFFE 0x0100 /* Port F PPI Frame Sync Enable */
1600#define PFFE_TIMER 0x0000 /* Enable TMR2 */
1601#define PFFE_PPI 0x0100 /* Enable PPI FS3 */
1602
1603#define PGSE 0x0200 /* Port G SPORT1 Secondary Enable */
1604#define PGSE_PPI 0x0000 /* Enable PPI D9:8 */
1605#define PGSE_SPORT 0x0200 /* Enable DR1SEC/DT1SEC */
1606
1607#define PGRE 0x0400 /* Port G SPORT1 Receive Enable */
1608#define PGRE_PPI 0x0000 /* Enable PPI D12:10 */
1609#define PGRE_SPORT 0x0400 /* Enable DR1PRI/RFS1/RSCLK1 */
1610
1611#define PGTE 0x0800 /* Port G SPORT1 Transmit Enable */
1612#define PGTE_PPI 0x0000 /* Enable PPI D15:13 */
1613#define PGTE_SPORT 0x0800 /* Enable DT1PRI/TFS1/TSCLK1 */
1614
1615
1616/* ****************** HANDSHAKE DMA (HDMA) MASKS *********************/
1617/* HDMAx_CTL Masks */
1618#define HMDMAEN 0x0001 /* Enable Handshake DMA 0/1 */
1619#define REP 0x0002 /* HDMA Request Polarity */
1620#define UTE 0x0004 /* Urgency Threshold Enable */
1621#define OIE 0x0010 /* Overflow Interrupt Enable */
1622#define BDIE 0x0020 /* Block Done Interrupt Enable */
1623#define MBDI 0x0040 /* Mask Block Done IRQ If Pending ECNT */
1624#define DRQ 0x0300 /* HDMA Request Type */
1625#define DRQ_NONE 0x0000 /* No Request */
1626#define DRQ_SINGLE 0x0100 /* Channels Request Single */
1627#define DRQ_MULTI 0x0200 /* Channels Request Multi (Default) */
1628#define DRQ_URGENT 0x0300 /* Channels Request Multi Urgent */
1629#define RBC 0x1000 /* Reload BCNT With IBCNT */
1630#define PS 0x2000 /* HDMA Pin Status */
1631#define OI 0x4000 /* Overflow Interrupt Generated */
1632#define BDI 0x8000 /* Block Done Interrupt Generated */
1633
1634/* entry addresses of the user-callable Boot ROM functions */
1635
1636#define _BOOTROM_RESET 0xEF000000
1637#define _BOOTROM_FINAL_INIT 0xEF000002
1638#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
1639#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
1640#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
1641#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
1642#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
1643#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
1644#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
1645
1646/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1647#define PGDE_UART PFDE_UART
1648#define PGDE_DMA PFDE_DMA
1649#define CKELOW SCKELOW
1650
1651/* ==== end from defBF534.h ==== */
1652
1653/* HOST Port Registers */
1654
1655#define HOST_CONTROL 0xffc03400 /* HOST Control Register */
1656#define HOST_STATUS 0xffc03404 /* HOST Status Register */
1657#define HOST_TIMEOUT 0xffc03408 /* HOST Acknowledge Mode Timeout Register */
1658
1659/* Counter Registers */
1660
1661#define CNT_CONFIG 0xffc03500 /* Configuration Register */
1662#define CNT_IMASK 0xffc03504 /* Interrupt Mask Register */
1663#define CNT_STATUS 0xffc03508 /* Status Register */
1664#define CNT_COMMAND 0xffc0350c /* Command Register */
1665#define CNT_DEBOUNCE 0xffc03510 /* Debounce Register */
1666#define CNT_COUNTER 0xffc03514 /* Counter Register */
1667#define CNT_MAX 0xffc03518 /* Maximal Count Register */
1668#define CNT_MIN 0xffc0351c /* Minimal Count Register */
1669
1670/* OTP/FUSE Registers */
1671
1672#define OTP_CONTROL 0xffc03600 /* OTP/Fuse Control Register */
1673#define OTP_BEN 0xffc03604 /* OTP/Fuse Byte Enable */
1674#define OTP_STATUS 0xffc03608 /* OTP/Fuse Status */
1675#define OTP_TIMING 0xffc0360c /* OTP/Fuse Access Timing */
1676
1677/* Security Registers */
1678
1679#define SECURE_SYSSWT 0xffc03620 /* Secure System Switches */
1680#define SECURE_CONTROL 0xffc03624 /* Secure Control */
1681#define SECURE_STATUS 0xffc03628 /* Secure Status */
1682
1683/* OTP Read/Write Data Buffer Registers */
1684
1685#define OTP_DATA0 0xffc03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1686#define OTP_DATA1 0xffc03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1687#define OTP_DATA2 0xffc03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1688#define OTP_DATA3 0xffc0368c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1689
1690/* NFC Registers */
1691
1692#define NFC_CTL 0xffc03700 /* NAND Control Register */
1693#define NFC_STAT 0xffc03704 /* NAND Status Register */
1694#define NFC_IRQSTAT 0xffc03708 /* NAND Interrupt Status Register */
1695#define NFC_IRQMASK 0xffc0370c /* NAND Interrupt Mask Register */
1696#define NFC_ECC0 0xffc03710 /* NAND ECC Register 0 */
1697#define NFC_ECC1 0xffc03714 /* NAND ECC Register 1 */
1698#define NFC_ECC2 0xffc03718 /* NAND ECC Register 2 */
1699#define NFC_ECC3 0xffc0371c /* NAND ECC Register 3 */
1700#define NFC_COUNT 0xffc03720 /* NAND ECC Count Register */
1701#define NFC_RST 0xffc03724 /* NAND ECC Reset Register */
1702#define NFC_PGCTL 0xffc03728 /* NAND Page Control Register */
1703#define NFC_READ 0xffc0372c /* NAND Read Data Register */
1704#define NFC_ADDR 0xffc03740 /* NAND Address Register */
1705#define NFC_CMD 0xffc03744 /* NAND Command Register */
1706#define NFC_DATA_WR 0xffc03748 /* NAND Data Write Register */
1707#define NFC_DATA_RD 0xffc0374c /* NAND Data Read Register */
1708
1709/* ********************************************************** */
1710/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1711/* and MULTI BIT READ MACROS */
1712/* ********************************************************** */
1713
1714/* Bit masks for HOST_CONTROL */
1715
1716#define HOST_EN 0x1 /* Host Enable */
1717#define nHOST_EN 0x0
1718#define HOST_END 0x2 /* Host Endianess */
1719#define nHOST_END 0x0
1720#define DATA_SIZE 0x4 /* Data Size */
1721#define nDATA_SIZE 0x0
1722#define HOST_RST 0x8 /* Host Reset */
1723#define nHOST_RST 0x0
1724#define HRDY_OVR 0x20 /* Host Ready Override */
1725#define nHRDY_OVR 0x0
1726#define INT_MODE 0x40 /* Interrupt Mode */
1727#define nINT_MODE 0x0
1728#define BT_EN 0x80 /* Bus Timeout Enable */
1729#define nBT_EN 0x0
1730#define EHW 0x100 /* Enable Host Write */
1731#define nEHW 0x0
1732#define EHR 0x200 /* Enable Host Read */
1733#define nEHR 0x0
1734#define BDR 0x400 /* Burst DMA Requests */
1735#define nBDR 0x0
1736
1737/* Bit masks for HOST_STATUS */
1738
1739#define READY 0x1 /* DMA Ready */
1740#define nREADY 0x0
1741#define FIFOFULL 0x2 /* FIFO Full */
1742#define nFIFOFULL 0x0
1743#define FIFOEMPTY 0x4 /* FIFO Empty */
1744#define nFIFOEMPTY 0x0
1745#define COMPLETE 0x8 /* DMA Complete */
1746#define nCOMPLETE 0x0
1747#define HSHK 0x10 /* Host Handshake */
1748#define nHSHK 0x0
1749#define TIMEOUT 0x20 /* Host Timeout */
1750#define nTIMEOUT 0x0
1751#define HIRQ 0x40 /* Host Interrupt Request */
1752#define nHIRQ 0x0
1753#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1754#define nALLOW_CNFG 0x0
1755#define DMA_DIR 0x100 /* DMA Direction */
1756#define nDMA_DIR 0x0
1757#define BTE 0x200 /* Bus Timeout Enabled */
1758#define nBTE 0x0
1759#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */
1760#define nHOSTRD_DONE 0x0
1761
1762/* Bit masks for HOST_TIMEOUT */
1763
1764#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1765
1766/* Bit masks for CNT_CONFIG */
1767
1768#define CNTE 0x1 /* Counter Enable */
1769#define nCNTE 0x0
1770#define DEBE 0x2 /* Debounce Enable */
1771#define nDEBE 0x0
1772#define CDGINV 0x10 /* CDG Pin Polarity Invert */
1773#define nCDGINV 0x0
1774#define CUDINV 0x20 /* CUD Pin Polarity Invert */
1775#define nCUDINV 0x0
1776#define CZMINV 0x40 /* CZM Pin Polarity Invert */
1777#define nCZMINV 0x0
1778#define CNTMODE 0x700 /* Counter Operating Mode */
1779#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
1780#define nZMZC 0x0
1781#define BNDMODE 0x3000 /* Boundary register Mode */
1782#define INPDIS 0x8000 /* CUG and CDG Input Disable */
1783#define nINPDIS 0x0
1784
1785/* Bit masks for CNT_IMASK */
1786
1787#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
1788#define nICIE 0x0
1789#define UCIE 0x2 /* Up count Interrupt Enable */
1790#define nUCIE 0x0
1791#define DCIE 0x4 /* Down count Interrupt Enable */
1792#define nDCIE 0x0
1793#define MINCIE 0x8 /* Min Count Interrupt Enable */
1794#define nMINCIE 0x0
1795#define MAXCIE 0x10 /* Max Count Interrupt Enable */
1796#define nMAXCIE 0x0
1797#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
1798#define nCOV31IE 0x0
1799#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
1800#define nCOV15IE 0x0
1801#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
1802#define nCZEROIE 0x0
1803#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
1804#define nCZMIE 0x0
1805#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
1806#define nCZMEIE 0x0
1807#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
1808#define nCZMZIE 0x0
1809
1810/* Bit masks for CNT_STATUS */
1811
1812#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
1813#define nICII 0x0
1814#define UCII 0x2 /* Up count Interrupt Identifier */
1815#define nUCII 0x0
1816#define DCII 0x4 /* Down count Interrupt Identifier */
1817#define nDCII 0x0
1818#define MINCII 0x8 /* Min Count Interrupt Identifier */
1819#define nMINCII 0x0
1820#define MAXCII 0x10 /* Max Count Interrupt Identifier */
1821#define nMAXCII 0x0
1822#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
1823#define nCOV31II 0x0
1824#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
1825#define nCOV15II 0x0
1826#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
1827#define nCZEROII 0x0
1828#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
1829#define nCZMII 0x0
1830#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
1831#define nCZMEII 0x0
1832#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
1833#define nCZMZII 0x0
1834
1835/* Bit masks for CNT_COMMAND */
1836
1837#define W1LCNT 0xf /* Load Counter Register */
1838#define W1LMIN 0xf0 /* Load Min Register */
1839#define W1LMAX 0xf00 /* Load Max Register */
1840#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
1841#define nW1ZMONCE 0x0
1842
1843/* Bit masks for CNT_DEBOUNCE */
1844
1845#define DPRESCALE 0xf /* Load Counter Register */
1846
1847/* Bit masks for OTP_CONTROL */
1848
1849#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
1850#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
1851#define nFIEN 0x0
1852#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
1853#define nFTESTDEC 0x0
1854#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
1855#define nFWRTEST 0x0
1856#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
1857#define nFRDEN 0x0
1858#define FWREN 0x8000 /* OTP/Fuse Write Enable */
1859#define nFWREN 0x0
1860
1861/* Bit masks for OTP_BEN */
1862
1863#define FBEN 0xffff /* OTP/Fuse Byte Enable */
1864
1865/* Bit masks for OTP_STATUS */
1866
1867#define FCOMP 0x1 /* OTP/Fuse Access Complete */
1868#define nFCOMP 0x0
1869#define FERROR 0x2 /* OTP/Fuse Access Error */
1870#define nFERROR 0x0
1871#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
1872#define nMMRGLOAD 0x0
1873#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
1874#define nMMRGLOCK 0x0
1875#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
1876#define nFPGMEN 0x0
1877
1878/* Bit masks for OTP_TIMING */
1879
1880#define USECDIV 0xff /* Micro Second Divider */
1881#define READACC 0x7f00 /* Read Access Time */
1882#define CPUMPRL 0x38000 /* Charge Pump Release Time */
1883#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
1884#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
1885#define PGMTIME 0xff000000 /* Program Time */
1886
1887/* Bit masks for SECURE_SYSSWT */
1888
1889#define EMUDABL 0x1 /* Emulation Disable. */
1890#define nEMUDABL 0x0
1891#define RSTDABL 0x2 /* Reset Disable */
1892#define nRSTDABL 0x0
1893#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
1894#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
1895#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
1896#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
1897#define nDMA0OVR 0x0
1898#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
1899#define nDMA1OVR 0x0
1900#define EMUOVR 0x4000 /* Emulation Override */
1901#define nEMUOVR 0x0
1902#define OTPSEN 0x8000 /* OTP Secrets Enable. */
1903#define nOTPSEN 0x0
1904#define L2DABL 0x70000 /* L2 Memory Disable. */
1905
1906/* Bit masks for SECURE_CONTROL */
1907
1908#define SECURE0 0x1 /* SECURE 0 */
1909#define nSECURE0 0x0
1910#define SECURE1 0x2 /* SECURE 1 */
1911#define nSECURE1 0x0
1912#define SECURE2 0x4 /* SECURE 2 */
1913#define nSECURE2 0x0
1914#define SECURE3 0x8 /* SECURE 3 */
1915#define nSECURE3 0x0
1916
1917/* Bit masks for SECURE_STATUS */
1918
1919#define SECMODE 0x3 /* Secured Mode Control State */
1920#define NMI 0x4 /* Non Maskable Interrupt */
1921#define nNMI 0x0
1922#define AFVALID 0x8 /* Authentication Firmware Valid */
1923#define nAFVALID 0x0
1924#define AFEXIT 0x10 /* Authentication Firmware Exit */
1925#define nAFEXIT 0x0
1926#define SECSTAT 0xe0 /* Secure Status */
1927
1928/* Bit masks for NFC_CTL */
1929
1930#define WR_DLY 0xf /* Write Strobe Delay */
1931#define RD_DLY 0xf0 /* Read Strobe Delay */
1932#define NWIDTH 0x100 /* NAND Data Width */
1933#define nNWIDTH 0x0
1934#define PG_SIZE 0x200 /* Page Size */
1935#define nPG_SIZE 0x0
1936
1937/* Bit masks for NFC_STAT */
1938
1939#define NBUSY 0x1 /* Not Busy */
1940#define nNBUSY 0x0
1941#define WB_FULL 0x2 /* Write Buffer Full */
1942#define nWB_FULL 0x0
1943#define PG_WR_STAT 0x4 /* Page Write Pending */
1944#define nPG_WR_STAT 0x0
1945#define PG_RD_STAT 0x8 /* Page Read Pending */
1946#define nPG_RD_STAT 0x0
1947#define WB_EMPTY 0x10 /* Write Buffer Empty */
1948#define nWB_EMPTY 0x0
1949
1950/* Bit masks for NFC_IRQSTAT */
1951
1952#define NBUSYIRQ 0x1 /* Not Busy IRQ */
1953#define nNBUSYIRQ 0x0
1954#define WB_OVF 0x2 /* Write Buffer Overflow */
1955#define nWB_OVF 0x0
1956#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
1957#define nWB_EDGE 0x0
1958#define RD_RDY 0x8 /* Read Data Ready */
1959#define nRD_RDY 0x0
1960#define WR_DONE 0x10 /* Page Write Done */
1961#define nWR_DONE 0x0
1962
1963/* Bit masks for NFC_IRQMASK */
1964
1965#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
1966#define nMASK_BUSYIRQ 0x0
1967#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
1968#define nMASK_WBOVF 0x0
1969#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
1970#define nMASK_WBEMPTY 0x0
1971#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
1972#define nMASK_RDRDY 0x0
1973#define MASK_WRDONE 0x10 /* Mask Write Done */
1974#define nMASK_WRDONE 0x0
1975
1976/* Bit masks for NFC_RST */
1977
1978#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
1979#define nECC_RST 0x0
1980
1981/* Bit masks for NFC_PGCTL */
1982
1983#define PG_RD_START 0x1 /* Page Read Start */
1984#define nPG_RD_START 0x0
1985#define PG_WR_START 0x2 /* Page Write Start */
1986#define nPG_WR_START 0x0
1987
1988/* Bit masks for NFC_ECC0 */
1989
1990#define ECC0 0x7ff /* Parity Calculation Result0 */
1991
1992/* Bit masks for NFC_ECC1 */
1993
1994#define ECC1 0x7ff /* Parity Calculation Result1 */
1995
1996/* Bit masks for NFC_ECC2 */
1997
1998#define ECC2 0x7ff /* Parity Calculation Result2 */
1999
2000/* Bit masks for NFC_ECC3 */
2001
2002#define ECC3 0x7ff /* Parity Calculation Result3 */
2003
2004/* Bit masks for NFC_COUNT */
2005
2006#define ECCCNT 0x3ff /* Transfer Count */
2007
2008
2009#endif /* _DEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
index 521bdb4d297d..74f967b235e2 100644
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -51,10 +51,6 @@
51#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT) 51#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
52#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val) 52#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT,val)
53#define bfin_read_CHIPID() bfin_read32(CHIPID) 53#define bfin_read_CHIPID() bfin_read32(CHIPID)
54#define bfin_read_SWRST() bfin_read16(SWRST)
55#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
56#define bfin_read_SYSCR() bfin_read16(SYSCR)
57#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
58#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV) 54#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
59#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val) 55#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
60#define bfin_read_VR_CTL() bfin_read16(VR_CTL) 56#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
@@ -78,6 +74,10 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
78} 74}
79 75
80/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */ 76/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
77#define bfin_read_SWRST() bfin_read16(SWRST)
78#define bfin_write_SWRST(val) bfin_write16(SWRST,val)
79#define bfin_read_SYSCR() bfin_read16(SYSCR)
80#define bfin_write_SYSCR(val) bfin_write16(SYSCR,val)
81#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0) 81#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
82#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val) 82#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0,val)
83#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1) 83#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
@@ -117,6 +117,18 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
117#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN) 117#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
118#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val) 118#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN,val)
119 119
120/* DMA Traffic controls */
121#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
122#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
123#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
124#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
125
126/* Alternate deprecated register names (below) provided for backwards code compatibility */
127#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
128#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
129#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
130#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
131
120/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */ 132/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
121#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR) 133#define bfin_read_FIO_DIR() bfin_read16(FIO_DIR)
122#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val) 134#define bfin_write_FIO_DIR(val) bfin_write16(FIO_DIR,val)
@@ -153,16 +165,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
153#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T) 165#define bfin_read_FIO_MASKB_T() bfin_read16(FIO_MASKB_T)
154#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val) 166#define bfin_write_FIO_MASKB_T(val) bfin_write16(FIO_MASKB_T,val)
155 167
156/* DMA Traffic controls */
157#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
158#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
159#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
160#define bfin_write_DMA_TCCNT(val) bfin_write16(DMA_TCCNT,val)
161#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
162#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
163#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
164#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
165
166/* DMA Controller */ 168/* DMA Controller */
167#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG) 169#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
168#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val) 170#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG,val)
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index b240a082aa09..6a3cf93f8b57 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -46,11 +46,7 @@
46 46
47#ifndef _DEF_BF532_H 47#ifndef _DEF_BF532_H
48#define _DEF_BF532_H 48#define _DEF_BF532_H
49/* 49
50#if !defined(__ADSPLPBLACKFIN__)
51#warning defBF532.h should only be included for 532 compatible chips
52#endif
53*/
54/* include all Core registers and bit definitions */ 50/* include all Core registers and bit definitions */
55#include <asm/mach-common/def_LPBlackfin.h> 51#include <asm/mach-common/def_LPBlackfin.h>
56 52
@@ -65,10 +61,10 @@
65#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */ 61#define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
66#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */ 62#define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
67#define CHIPID 0xFFC00014 /* Chip ID Register */ 63#define CHIPID 0xFFC00014 /* Chip ID Register */
68#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
69#define SYSCR 0xFFC00104 /* System Configuration registe */
70 64
71/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */ 65/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
66#define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
67#define SYSCR 0xFFC00104 /* System Configuration registe */
72#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */ 68#define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
73#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */ 69#define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
74#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */ 70#define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
@@ -218,11 +214,13 @@
218#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 214#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
219 215
220/* DMA Traffic controls */ 216/* DMA Traffic controls */
221#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */ 217#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 218#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
225 219
220/* Alternate deprecated register names (below) provided for backwards code compatibility */
221#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
222#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
223
226/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 224/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
227#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */ 225#define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
228#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 226#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -407,14 +405,25 @@
407/* ********************* PLL AND RESET MASKS ************************ */ 405/* ********************* PLL AND RESET MASKS ************************ */
408 406
409/* PLL_CTL Masks */ 407/* PLL_CTL Masks */
410#define PLL_CLKIN 0x00000000 /* Pass CLKIN to PLL */ 408#define PLL_CLKIN 0x0000 /* Pass CLKIN to PLL */
411#define PLL_CLKIN_DIV2 0x00000001 /* Pass CLKIN/2 to PLL */ 409#define PLL_CLKIN_DIV2 0x0001 /* Pass CLKIN/2 to PLL */
412#define PLL_OFF 0x00000002 /* Shut off PLL clocks */ 410#define DF 0x0001 /* 0: PLL = CLKIN, 1: PLL = CLKIN/2 */
413#define STOPCK_OFF 0x00000008 /* Core clock off */ 411#define PLL_OFF 0x0002 /* Shut off PLL clocks */
414#define PDWN 0x00000020 /* Put the PLL in a Deep Sleep state */ 412#define STOPCK_OFF 0x0008 /* Core clock off */
415#define BYPASS 0x00000100 /* Bypass the PLL */ 413#define STOPCK 0x0008 /* Core Clock Off */
414#define PDWN 0x0020 /* Put the PLL in a Deep Sleep state */
415#if !defined(__ADSPBF538__)
416/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
417# define IN_DELAY 0x0040 /* Add 200ps Delay To EBIU Input Latches */
418# define OUT_DELAY 0x0080 /* Add 200ps Delay To EBIU Output Signals */
419#endif
420#define BYPASS 0x0100 /* Bypass the PLL */
421/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits) */
422#define SET_MSEL(x) (((x)&0x3F) << 0x9) /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL */
416 423
417/* PLL_DIV Masks */ 424/* PLL_DIV Masks */
425#define SSEL 0x000F /* System Select */
426#define CSEL 0x0030 /* Core Select */
418 427
419#define SCLK_DIV(x) (x) /* SCLK = VCO / x */ 428#define SCLK_DIV(x) (x) /* SCLK = VCO / x */
420 429
@@ -422,6 +431,8 @@
422#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */ 431#define CCLK_DIV2 0x00000010 /* CCLK = VCO / 2 */
423#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */ 432#define CCLK_DIV4 0x00000020 /* CCLK = VCO / 4 */
424#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */ 433#define CCLK_DIV8 0x00000030 /* CCLK = VCO / 8 */
434/* PLL_DIV Macros */
435#define SET_SSEL(x) ((x)&0xF) /* Set SSEL = 0-15 --> SCLK = VCO/SSEL */
425 436
426/* PLL_STAT Masks */ 437/* PLL_STAT Masks */
427#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 438#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
@@ -429,13 +440,47 @@
429#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */ 440#define ACTIVE_PLLDISABLED 0x0004 /* Processor In Active Mode With PLL Disabled */
430#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 441#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
431 442
443/* VR_CTL Masks */
444#define FREQ 0x0003 /* Switching Oscillator Frequency For Regulator */
445#define HIBERNATE 0x0000 /* Powerdown/Bypass On-Board Regulation */
446#define FREQ_333 0x0001 /* Switching Frequency Is 333 kHz */
447#define FREQ_667 0x0002 /* Switching Frequency Is 667 kHz */
448#define FREQ_1000 0x0003 /* Switching Frequency Is 1 MHz */
449
450#define GAIN 0x000C /* Voltage Level Gain */
451#define GAIN_5 0x0000 /* GAIN = 5 */
452#define GAIN_10 0x0004 /* GAIN = 10 */
453#define GAIN_20 0x0008 /* GAIN = 20 */
454#define GAIN_50 0x000C /* GAIN = 50 */
455
456#define VLEV 0x00F0 /* Internal Voltage Level */
457#define VLEV_085 0x0060 /* VLEV = 0.85 V (-5% - +10% Accuracy) */
458#define VLEV_090 0x0070 /* VLEV = 0.90 V (-5% - +10% Accuracy) */
459#define VLEV_095 0x0080 /* VLEV = 0.95 V (-5% - +10% Accuracy) */
460#define VLEV_100 0x0090 /* VLEV = 1.00 V (-5% - +10% Accuracy) */
461#define VLEV_105 0x00A0 /* VLEV = 1.05 V (-5% - +10% Accuracy) */
462#define VLEV_110 0x00B0 /* VLEV = 1.10 V (-5% - +10% Accuracy) */
463#define VLEV_115 0x00C0 /* VLEV = 1.15 V (-5% - +10% Accuracy) */
464#define VLEV_120 0x00D0 /* VLEV = 1.20 V (-5% - +10% Accuracy) */
465
466#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
467#define SCKELOW 0x8000 /* Do Not Drive SCKE High During Reset After Hibernate */
468
432/* CHIPID Masks */ 469/* CHIPID Masks */
433#define CHIPID_VERSION 0xF0000000 470#define CHIPID_VERSION 0xF0000000
434#define CHIPID_FAMILY 0x0FFFF000 471#define CHIPID_FAMILY 0x0FFFF000
435#define CHIPID_MANUFACTURE 0x00000FFE 472#define CHIPID_MANUFACTURE 0x00000FFE
436 473
437/* SWRST Mask */ 474/* SWRST Mask */
438#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ 475#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
476#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
477#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
478#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
479#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
480
481/* SYSCR Masks */
482#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */
483#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
439 484
440/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 485/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
441 486
@@ -483,23 +528,6 @@
483#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 528#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
484#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 529#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
485 530
486/* ********* WATCHDOG TIMER MASKS ********************8 */
487
488/* Watchdog Timer WDOG_CTL Register */
489#define ICTL(x) ((x<<1) & 0x0006)
490#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
491#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
492#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
493#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
494
495#define TMR_EN 0x0000
496#define TMR_DIS 0x0AD0
497#define TRO 0x8000
498
499#define ICTL_P0 0x01
500#define ICTL_P1 0x02
501#define TRO_P 0x0F
502
503/* ***************************** UART CONTROLLER MASKS ********************** */ 531/* ***************************** UART CONTROLLER MASKS ********************** */
504 532
505/* UART_LCR Register */ 533/* UART_LCR Register */
@@ -583,6 +611,9 @@
583#define TSPEN 0x0001 /* TX enable */ 611#define TSPEN 0x0001 /* TX enable */
584#define ITCLK 0x0002 /* Internal TX Clock Select */ 612#define ITCLK 0x0002 /* Internal TX Clock Select */
585#define TDTYPE 0x000C /* TX Data Formatting Select */ 613#define TDTYPE 0x000C /* TX Data Formatting Select */
614#define DTYPE_NORM 0x0000 /* Data Format Normal */
615#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
616#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
586#define TLSBIT 0x0010 /* TX Bit Order */ 617#define TLSBIT 0x0010 /* TX Bit Order */
587#define ITFS 0x0200 /* Internal TX Frame Sync Select */ 618#define ITFS 0x0200 /* Internal TX Frame Sync Select */
588#define TFSR 0x0400 /* TX Frame Sync Required Select */ 619#define TFSR 0x0400 /* TX Frame Sync Required Select */
@@ -592,7 +623,12 @@
592#define TCKFE 0x4000 /* TX Clock Falling Edge Select */ 623#define TCKFE 0x4000 /* TX Clock Falling Edge Select */
593 624
594/* SPORTx_TCR2 Masks */ 625/* SPORTx_TCR2 Masks */
595#define SLEN 0x001F /*TX Word Length */ 626#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
627 defined(__ADSPBF533__)
628# define SLEN 0x001F /*TX Word Length */
629#else
630# define SLEN(x) ((x)&0x1F) /* SPORT TX Word Length (2 - 31) */
631#endif
596#define TXSE 0x0100 /*TX Secondary Enable */ 632#define TXSE 0x0100 /*TX Secondary Enable */
597#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */ 633#define TSFSE 0x0200 /*TX Stereo Frame Sync Enable */
598#define TRFST 0x0400 /*TX Right-First Data Order */ 634#define TRFST 0x0400 /*TX Right-First Data Order */
@@ -601,8 +637,9 @@
601#define RSPEN 0x0001 /* RX enable */ 637#define RSPEN 0x0001 /* RX enable */
602#define IRCLK 0x0002 /* Internal RX Clock Select */ 638#define IRCLK 0x0002 /* Internal RX Clock Select */
603#define RDTYPE 0x000C /* RX Data Formatting Select */ 639#define RDTYPE 0x000C /* RX Data Formatting Select */
604#define RULAW 0x0008 /* u-Law enable */ 640#define DTYPE_NORM 0x0000 /* no companding */
605#define RALAW 0x000C /* A-Law enable */ 641#define DTYPE_ULAW 0x0008 /* Compand Using u-Law */
642#define DTYPE_ALAW 0x000C /* Compand Using A-Law */
606#define RLSBIT 0x0010 /* RX Bit Order */ 643#define RLSBIT 0x0010 /* RX Bit Order */
607#define IRFS 0x0200 /* Internal RX Frame Sync Select */ 644#define IRFS 0x0200 /* Internal RX Frame Sync Select */
608#define RFSR 0x0400 /* RX Frame Sync Required Select */ 645#define RFSR 0x0400 /* RX Frame Sync Required Select */
@@ -611,7 +648,7 @@
611#define RCKFE 0x4000 /* RX Clock Falling Edge Select */ 648#define RCKFE 0x4000 /* RX Clock Falling Edge Select */
612 649
613/* SPORTx_RCR2 Masks */ 650/* SPORTx_RCR2 Masks */
614#define SLEN 0x001F /*RX Word Length */ 651/* SLEN defined above */
615#define RXSE 0x0100 /*RX Secondary Enable */ 652#define RXSE 0x0100 /*RX Secondary Enable */
616#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */ 653#define RSFSE 0x0200 /*RX Stereo Frame Sync Enable */
617#define RRFST 0x0400 /*Right-First Data Order */ 654#define RRFST 0x0400 /*Right-First Data Order */
@@ -628,14 +665,37 @@
628/*SPORTx_MCMC1 Masks */ 665/*SPORTx_MCMC1 Masks */
629#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */ 666#define SP_WSIZE 0x0000F000 /*Multichannel Window Size Field */
630#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */ 667#define SP_WOFF 0x000003FF /*Multichannel Window Offset Field */
668/* SPORTx_MCMC1 Macros */
669#define SET_SP_WOFF(x) ((x) & 0x3FF) /* Multichannel Window Offset Field */
670/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits */
671#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC) /* Multichannel Window Size = (x/8)-1 */
631 672
632/*SPORTx_MCMC2 Masks */ 673/*SPORTx_MCMC2 Masks */
633#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */ 674#define MCCRM 0x00000003 /*Multichannel Clock Recovery Mode */
634#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */ 675#define REC_BYPASS 0x0000 /* Bypass Mode (No Clock Recovery) */
635#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */ 676#define REC_2FROM4 0x0002 /* Recover 2 MHz Clock from 4 MHz Clock */
636#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */ 677#define REC_8FROM16 0x0003 /* Recover 8 MHz Clock from 16 MHz Clock */
637#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */ 678#define MCDTXPE 0x00000004 /*Multichannel DMA Transmit Packing */
638#define MFD 0x0000F000 /*Multichannel Frame Delay */ 679#define MCDRXPE 0x00000008 /*Multichannel DMA Receive Packing */
680#define MCMEN 0x00000010 /*Multichannel Frame Mode Enable */
681#define FSDR 0x00000080 /*Multichannel Frame Sync to Data Relationship */
682#define MFD 0x0000F000 /*Multichannel Frame Delay */
683#define MFD_0 0x0000 /* Multichannel Frame Delay = 0 */
684#define MFD_1 0x1000 /* Multichannel Frame Delay = 1 */
685#define MFD_2 0x2000 /* Multichannel Frame Delay = 2 */
686#define MFD_3 0x3000 /* Multichannel Frame Delay = 3 */
687#define MFD_4 0x4000 /* Multichannel Frame Delay = 4 */
688#define MFD_5 0x5000 /* Multichannel Frame Delay = 5 */
689#define MFD_6 0x6000 /* Multichannel Frame Delay = 6 */
690#define MFD_7 0x7000 /* Multichannel Frame Delay = 7 */
691#define MFD_8 0x8000 /* Multichannel Frame Delay = 8 */
692#define MFD_9 0x9000 /* Multichannel Frame Delay = 9 */
693#define MFD_10 0xA000 /* Multichannel Frame Delay = 10 */
694#define MFD_11 0xB000 /* Multichannel Frame Delay = 11 */
695#define MFD_12 0xC000 /* Multichannel Frame Delay = 12 */
696#define MFD_13 0xD000 /* Multichannel Frame Delay = 13 */
697#define MFD_14 0xE000 /* Multichannel Frame Delay = 14 */
698#define MFD_15 0xF000 /* Multichannel Frame Delay = 15 */
639 699
640/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */ 700/* ********* PARALLEL PERIPHERAL INTERFACE (PPI) MASKS **************** */
641 701
@@ -660,6 +720,8 @@
660#define DLEN_16 0x3800 /* Data Length = 16 Bits */ 720#define DLEN_16 0x3800 /* Data Length = 16 Bits */
661#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */ 721#define DLEN(x) (((x-9) & 0x07) << 11) /* PPI Data Length (only works for x=10-->x=16) */
662#define POL 0x0000C000 /* PPI Signal Polarities */ 722#define POL 0x0000C000 /* PPI Signal Polarities */
723#define POLC 0x4000 /* PPI Clock Polarity */
724#define POLS 0x8000 /* PPI Frame Sync Polarity */
663 725
664/* PPI_STATUS Masks */ 726/* PPI_STATUS Masks */
665#define FLD 0x00000400 /* Field Indicator */ 727#define FLD 0x00000400 /* Field Indicator */
@@ -729,6 +791,15 @@
729#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */ 791#define PCAPRD 0x00000800 /* DMA Read Operation Indicator */
730#define PMAP 0x00007000 /* DMA Peripheral Map Field */ 792#define PMAP 0x00007000 /* DMA Peripheral Map Field */
731 793
794#define PMAP_PPI 0x0000 /* PMAP PPI Port DMA */
795#define PMAP_SPORT0RX 0x1000 /* PMAP SPORT0 Receive DMA */
796#define PMAP_SPORT0TX 0x2000 /* PMAP SPORT0 Transmit DMA */
797#define PMAP_SPORT1RX 0x3000 /* PMAP SPORT1 Receive DMA */
798#define PMAP_SPORT1TX 0x4000 /* PMAP SPORT1 Transmit DMA */
799#define PMAP_SPI 0x5000 /* PMAP SPI DMA */
800#define PMAP_UARTRX 0x6000 /* PMAP UART Receive DMA */
801#define PMAP_UARTTX 0x7000 /* PMAP UART Transmit DMA */
802
732/* ************* GENERAL PURPOSE TIMER MASKS ******************** */ 803/* ************* GENERAL PURPOSE TIMER MASKS ******************** */
733 804
734/* PWM Timer bit definitions */ 805/* PWM Timer bit definitions */
@@ -755,9 +826,9 @@
755#define TIMIL0 0x0001 826#define TIMIL0 0x0001
756#define TIMIL1 0x0002 827#define TIMIL1 0x0002
757#define TIMIL2 0x0004 828#define TIMIL2 0x0004
758#define TOVL_ERR0 0x0010 829#define TOVF_ERR0 0x0010 /* Timer 0 Counter Overflow */
759#define TOVL_ERR1 0x0020 830#define TOVF_ERR1 0x0020 /* Timer 1 Counter Overflow */
760#define TOVL_ERR2 0x0040 831#define TOVF_ERR2 0x0040 /* Timer 2 Counter Overflow */
761#define TRUN0 0x1000 832#define TRUN0 0x1000
762#define TRUN1 0x2000 833#define TRUN1 0x2000
763#define TRUN2 0x4000 834#define TRUN2 0x4000
@@ -765,13 +836,21 @@
765#define TIMIL0_P 0x00 836#define TIMIL0_P 0x00
766#define TIMIL1_P 0x01 837#define TIMIL1_P 0x01
767#define TIMIL2_P 0x02 838#define TIMIL2_P 0x02
768#define TOVL_ERR0_P 0x04 839#define TOVF_ERR0_P 0x04
769#define TOVL_ERR1_P 0x05 840#define TOVF_ERR1_P 0x05
770#define TOVL_ERR2_P 0x06 841#define TOVF_ERR2_P 0x06
771#define TRUN0_P 0x0C 842#define TRUN0_P 0x0C
772#define TRUN1_P 0x0D 843#define TRUN1_P 0x0D
773#define TRUN2_P 0x0E 844#define TRUN2_P 0x0E
774 845
846/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
847#define TOVL_ERR0 TOVF_ERR0
848#define TOVL_ERR1 TOVF_ERR1
849#define TOVL_ERR2 TOVF_ERR2
850#define TOVL_ERR0_P TOVF_ERR0_P
851#define TOVL_ERR1_P TOVF_ERR1_P
852#define TOVL_ERR2_P TOVF_ERR2_P
853
775/* TIMERx_CONFIG Registers */ 854/* TIMERx_CONFIG Registers */
776#define PWM_OUT 0x0001 855#define PWM_OUT 0x0001
777#define WDTH_CAP 0x0002 856#define WDTH_CAP 0x0002
@@ -841,6 +920,10 @@
841 920
842/* SPI_CTL Masks */ 921/* SPI_CTL Masks */
843#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */ 922#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
923#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
924#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
925#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
926#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
844#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */ 927#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
845#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */ 928#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
846#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */ 929#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
@@ -894,10 +977,20 @@
894#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */ 977#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
895#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */ 978#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
896 979
980/* SPIx_FLG Masks */
981#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
982#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
983#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
984#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
985#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
986#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
987#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
988
897/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 989/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
898 990
899/* AMGCTL Masks */ 991/* AMGCTL Masks */
900#define AMCKEN 0x00000001 /* Enable CLKOUT */ 992#define AMCKEN 0x00000001 /* Enable CLKOUT */
993#define AMBEN_NONE 0x00000000 /* All Banks Disabled */
901#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */ 994#define AMBEN_B0 0x00000002 /* Enable Asynchronous Memory Bank 0 only */
902#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */ 995#define AMBEN_B0_B1 0x00000004 /* Enable Asynchronous Memory Banks 0 & 1 only */
903#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */ 996#define AMBEN_B0_B1_B2 0x00000006 /* Enable Asynchronous Memory Banks 0, 1, and 2 */
@@ -1097,6 +1190,9 @@
1097#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */ 1190#define CL_3 0x0000000C /* SDRAM CAS latency = 3 cycles */
1098#define PFE 0x00000010 /* Enable SDRAM prefetch */ 1191#define PFE 0x00000010 /* Enable SDRAM prefetch */
1099#define PFP 0x00000020 /* Prefetch has priority over AMC requests */ 1192#define PFP 0x00000020 /* Prefetch has priority over AMC requests */
1193#define PASR_ALL 0x00000000 /* All 4 SDRAM Banks Refreshed In Self-Refresh */
1194#define PASR_B0_B1 0x00000010 /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh */
1195#define PASR_B0 0x00000020 /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh */
1100#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */ 1196#define TRAS_1 0x00000040 /* SDRAM tRAS = 1 cycle */
1101#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */ 1197#define TRAS_2 0x00000080 /* SDRAM tRAS = 2 cycles */
1102#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */ 1198#define TRAS_3 0x000000C0 /* SDRAM tRAS = 3 cycles */
@@ -1158,18 +1254,5 @@
1158#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1254#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1159#define BGSTAT 0x00000020 /* Bus granted */ 1255#define BGSTAT 0x00000020 /* Bus granted */
1160 1256
1161/*VR_CTL Masks*/
1162#define WAKE 0x100
1163#define VLEV_6 0x60
1164#define VLEV_7 0x70
1165#define VLEV_8 0x80
1166#define VLEV_9 0x90
1167#define VLEV_10 0xA0
1168#define VLEV_11 0xB0
1169#define VLEV_12 0xC0
1170#define VLEV_13 0xD0
1171#define VLEV_14 0xE0
1172#define VLEV_15 0xF0
1173#define FREQ_3 0x03
1174 1257
1175#endif /* _DEF_BF532_H */ 1258#endif /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index d4d3663c1100..84e58fa73dce 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -399,6 +399,12 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
399#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val) 399#define bfin_write_EBIU_SDSTAT(val) bfin_write16(EBIU_SDSTAT,val)
400 400
401/* DMA Traffic Control Registers */ 401/* DMA Traffic Control Registers */
402#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
403#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER,val)
404#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
405#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT,val)
406
407/* Alternate deprecated register names (below) provided for backwards code compatibility */
402#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER) 408#define bfin_read_DMA_TCPER() bfin_read16(DMA_TCPER)
403#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val) 409#define bfin_write_DMA_TCPER(val) bfin_write16(DMA_TCPER,val)
404#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT) 410#define bfin_read_DMA_TCCNT() bfin_read16(DMA_TCCNT)
@@ -1075,8 +1081,6 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
1075#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val) 1081#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC,val)
1076#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF) 1082#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
1077#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val) 1083#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF,val)
1078#define bfin_read_CAN_SFCMVER2() bfin_read16(CAN_SFCMVER2)
1079#define bfin_write_CAN_SFCMVER2(val) bfin_write16(CAN_SFCMVER2,val)
1080 1084
1081/* Mailbox Acceptance Masks */ 1085/* Mailbox Acceptance Masks */
1082#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L) 1086#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index e605e9709004..1859f2fee5a7 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -216,8 +216,12 @@
216#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */ 216#define EBIU_SDSTAT 0xFFC00A1C /* SDRAM Status Register */
217 217
218/* DMA Traffic Control Registers */ 218/* DMA Traffic Control Registers */
219#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */ 219#define DMA_TC_PER 0xFFC00B0C /* Traffic Control Periods Register */
220#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */ 220#define DMA_TC_CNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221
222/* Alternate deprecated register names (below) provided for backwards code compatibility */
223#define DMA_TCPER 0xFFC00B0C /* Traffic Control Periods Register */
224#define DMA_TCCNT 0xFFC00B10 /* Traffic Control Current Counts Register */
221 225
222/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */ 226/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
223#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */ 227#define DMA0_NEXT_DESC_PTR 0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
@@ -563,7 +567,7 @@
563#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */ 567#define CAN_GIF 0xFFC02A9C /* Global Interrupt Flag Register */
564#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */ 568#define CAN_CONTROL 0xFFC02AA0 /* Master Control Register */
565#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */ 569#define CAN_INTR 0xFFC02AA4 /* Interrupt Pending Register */
566#define CAN_SFCMVER 0xFFC02AA8 /* Version Code Register */ 570
567#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */ 571#define CAN_MBTD 0xFFC02AAC /* Mailbox Temporary Disable Feature */
568#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */ 572#define CAN_EWR 0xFFC02AB0 /* Programmable Warning Level */
569#define CAN_ESR 0xFFC02AB4 /* Error Status Register */ 573#define CAN_ESR 0xFFC02AB4 /* Error Status Register */
@@ -1026,10 +1030,11 @@
1026#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */ 1030#define VLEV_130 0x00F0 /* VLEV = 1.30 V (-5% - +10% Accuracy) */
1027 1031
1028#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */ 1032#define WAKE 0x0100 /* Enable RTC/Reset Wakeup From Hibernate */
1029#define PHYWE 0x0200 /* Enable PHY Wakeup From Hibernate */ 1033#define CANWE 0x0200 /* Enable CAN Wakeup From Hibernate */
1030#define CANWE 0x0400 /* Enable CAN Wakeup From Hibernate */ 1034#define PHYWE 0x0400 /* Enable PHY Wakeup From Hibernate */
1031#define PHYCLKOE 0x4000 /* PHY Clock Output Enable */ 1035#define CLKBUFOE 0x4000 /* CLKIN Buffer Output Enable */
1032#define CKELOW 0x8000 /* Enable Drive CKE Low During Reset */ 1036#define PHYCLKOE CLKBUFOE /* Alternative legacy name for the above */
1037#define SCKELOW 0x8000 /* Enable Drive CKE Low During Reset */
1033 1038
1034/* PLL_STAT Masks */ 1039/* PLL_STAT Masks */
1035#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */ 1040#define ACTIVE_PLLENABLED 0x0001 /* Processor In Active Mode With PLL Enabled */
@@ -1050,7 +1055,7 @@
1050#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ 1055#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
1051 1056
1052/* SYSCR Masks */ 1057/* SYSCR Masks */
1053#define BMODE 0x0006 /* Boot Mode - Latched During HW Reset From Mode Pins */ 1058#define BMODE 0x0007 /* Boot Mode - Latched During HW Reset From Mode Pins */
1054#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */ 1059#define NOBOOT 0x0010 /* Execute From L1 or ASYNC Bank 0 When BMODE = 0 */
1055 1060
1056/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/ 1061/* ************* SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
@@ -1107,19 +1112,9 @@
1107#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */ 1112#define IWR_ENABLE(x) (1 << ((x)&0x1F)) /* Wakeup Enable Peripheral #x */
1108#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */ 1113#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << ((x)&0x1F))) /* Wakeup Disable Peripheral #x */
1109 1114
1110/* *************** WATCHDOG TIMER MASKS *******************************************/
1111/* WDOG_CTL Masks */
1112#define WDOG_RESET 0x0000 /* Generate Reset Event */
1113#define WDOG_NMI 0x0002 /* Generate Non-Maskable Interrupt (NMI) Event */
1114#define WDOG_GPI 0x0004 /* Generate General Purpose (GP) Interrupt */
1115#define WDOG_NONE 0x0006 /* Disable Watchdog Timer Interrupts */
1116#define TMR_EN 0x0FF0 /* Watchdog Counter Enable */
1117#define TMR_DIS 0x0AD0 /* Watchdog Counter Disable */
1118#define TRO 0x8000 /* Watchdog Expired */
1119
1120/* ************** UART CONTROLLER MASKS *************************/ 1115/* ************** UART CONTROLLER MASKS *************************/
1121/* UARTx_LCR Masks */ 1116/* UARTx_LCR Masks */
1122#define WLS(x) ((((x)&0x3)-5) & 0x03) /* Word Length Select */ 1117#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
1123#define STB 0x04 /* Stop Bits */ 1118#define STB 0x04 /* Stop Bits */
1124#define PEN 0x08 /* Parity Enable */ 1119#define PEN 0x08 /* Parity Enable */
1125#define EPS 0x10 /* Even Parity Select */ 1120#define EPS 0x10 /* Even Parity Select */
@@ -1128,8 +1123,8 @@
1128#define DLAB 0x80 /* Divisor Latch Access */ 1123#define DLAB 0x80 /* Divisor Latch Access */
1129 1124
1130/* UARTx_MCR Mask */ 1125/* UARTx_MCR Mask */
1131#define LOOP 0x10 /* Loopback Mode Enable */ 1126#define LOOP_ENA 0x10 /* Loopback Mode Enable */
1132 1127#define LOOP_ENA_P 0x04
1133/* UARTx_LSR Masks */ 1128/* UARTx_LSR Masks */
1134#define DR 0x01 /* Data Ready */ 1129#define DR 0x01 /* Data Ready */
1135#define OE 0x02 /* Overrun Error */ 1130#define OE 0x02 /* Overrun Error */
@@ -1229,10 +1224,10 @@
1229#define TIMIL1 0x00000002 /* Timer 1 Interrupt */ 1224#define TIMIL1 0x00000002 /* Timer 1 Interrupt */
1230#define TIMIL2 0x00000004 /* Timer 2 Interrupt */ 1225#define TIMIL2 0x00000004 /* Timer 2 Interrupt */
1231#define TIMIL3 0x00000008 /* Timer 3 Interrupt */ 1226#define TIMIL3 0x00000008 /* Timer 3 Interrupt */
1232#define TOVL_ERR0 0x00000010 /* Timer 0 Counter Overflow */ 1227#define TOVF_ERR0 0x00000010 /* Timer 0 Counter Overflow */
1233#define TOVL_ERR1 0x00000020 /* Timer 1 Counter Overflow */ 1228#define TOVF_ERR1 0x00000020 /* Timer 1 Counter Overflow */
1234#define TOVL_ERR2 0x00000040 /* Timer 2 Counter Overflow */ 1229#define TOVF_ERR2 0x00000040 /* Timer 2 Counter Overflow */
1235#define TOVL_ERR3 0x00000080 /* Timer 3 Counter Overflow */ 1230#define TOVF_ERR3 0x00000080 /* Timer 3 Counter Overflow */
1236#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */ 1231#define TRUN0 0x00001000 /* Timer 0 Slave Enable Status */
1237#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */ 1232#define TRUN1 0x00002000 /* Timer 1 Slave Enable Status */
1238#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */ 1233#define TRUN2 0x00004000 /* Timer 2 Slave Enable Status */
@@ -1241,15 +1236,24 @@
1241#define TIMIL5 0x00020000 /* Timer 5 Interrupt */ 1236#define TIMIL5 0x00020000 /* Timer 5 Interrupt */
1242#define TIMIL6 0x00040000 /* Timer 6 Interrupt */ 1237#define TIMIL6 0x00040000 /* Timer 6 Interrupt */
1243#define TIMIL7 0x00080000 /* Timer 7 Interrupt */ 1238#define TIMIL7 0x00080000 /* Timer 7 Interrupt */
1244#define TOVL_ERR4 0x00100000 /* Timer 4 Counter Overflow */ 1239#define TOVF_ERR4 0x00100000 /* Timer 4 Counter Overflow */
1245#define TOVL_ERR5 0x00200000 /* Timer 5 Counter Overflow */ 1240#define TOVF_ERR5 0x00200000 /* Timer 5 Counter Overflow */
1246#define TOVL_ERR6 0x00400000 /* Timer 6 Counter Overflow */ 1241#define TOVF_ERR6 0x00400000 /* Timer 6 Counter Overflow */
1247#define TOVL_ERR7 0x00800000 /* Timer 7 Counter Overflow */ 1242#define TOVF_ERR7 0x00800000 /* Timer 7 Counter Overflow */
1248#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */ 1243#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
1249#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */ 1244#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
1250#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */ 1245#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
1251#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */ 1246#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
1252 1247
1248/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1249#define TOVL_ERR0 TOVF_ERR0
1250#define TOVL_ERR1 TOVF_ERR1
1251#define TOVL_ERR2 TOVF_ERR2
1252#define TOVL_ERR3 TOVF_ERR3
1253#define TOVL_ERR4 TOVF_ERR4
1254#define TOVL_ERR5 TOVF_ERR5
1255#define TOVL_ERR6 TOVF_ERR6
1256#define TOVL_ERR7 TOVF_ERR7
1253/* TIMERx_CONFIG Masks */ 1257/* TIMERx_CONFIG Masks */
1254#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */ 1258#define PWM_OUT 0x0001 /* Pulse-Width Modulation Output Mode */
1255#define WDTH_CAP 0x0002 /* Width Capture Input Mode */ 1259#define WDTH_CAP 0x0002 /* Width Capture Input Mode */
@@ -1647,6 +1651,8 @@
1647#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */ 1651#define EBSZ_32 0x0002 /* SDRAM External Bank Size = 32MB */
1648#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */ 1652#define EBSZ_64 0x0004 /* SDRAM External Bank Size = 64MB */
1649#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */ 1653#define EBSZ_128 0x0006 /* SDRAM External Bank Size = 128MB */
1654#define EBSZ_256 0x0008 /* SDRAM External Bank Size = 256MB */
1655#define EBSZ_512 0x000A /* SDRAM External Bank Size = 512MB */
1650#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */ 1656#define EBCAW_8 0x0000 /* SDRAM External Bank Column Address Width = 8 Bits */
1651#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */ 1657#define EBCAW_9 0x0010 /* SDRAM External Bank Column Address Width = 9 Bits */
1652#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */ 1658#define EBCAW_10 0x0020 /* SDRAM External Bank Column Address Width = 10 Bits */
@@ -1859,8 +1865,10 @@
1859#define TXECNT 0xFF00 /* Transmit Error Counter */ 1865#define TXECNT 0xFF00 /* Transmit Error Counter */
1860 1866
1861/* CAN_INTR Masks */ 1867/* CAN_INTR Masks */
1862#define MBRIF 0x0001 /* Mailbox Receive Interrupt */ 1868#define MBRIRQ 0x0001 /* Mailbox Receive Interrupt */
1863#define MBTIF 0x0002 /* Mailbox Transmit Interrupt */ 1869#define MBRIF MBRIRQ /* legacy */
1870#define MBTIRQ 0x0002 /* Mailbox Transmit Interrupt */
1871#define MBTIF MBTIRQ /* legacy */
1864#define GIRQ 0x0004 /* Global Interrupt */ 1872#define GIRQ 0x0004 /* Global Interrupt */
1865#define SMACK 0x0008 /* Sleep Mode Acknowledge */ 1873#define SMACK 0x0008 /* Sleep Mode Acknowledge */
1866#define CANTX 0x0040 /* CAN TX Bus Value */ 1874#define CANTX 0x0040 /* CAN TX Bus Value */
@@ -2445,8 +2453,8 @@
2445#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */ 2453#define PJCE_SPI 0x0004 /* Enable SPI_SSEL7 */
2446 2454
2447#define PFDE 0x0008 /* Port F DMA Request Enable */ 2455#define PFDE 0x0008 /* Port F DMA Request Enable */
2448#define PGDE_UART 0x0000 /* Enable UART0 RX/TX */ 2456#define PFDE_UART 0x0000 /* Enable UART0 RX/TX */
2449#define PGDE_DMA 0x0008 /* Enable DMAR1:0 */ 2457#define PFDE_DMA 0x0008 /* Enable DMAR1:0 */
2450 2458
2451#define PFTE 0x0010 /* Port F Timer Enable */ 2459#define PFTE 0x0010 /* Port F Timer Enable */
2452#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */ 2460#define PFTE_UART 0x0000 /* Enable UART1 RX/TX */
@@ -2498,4 +2506,20 @@
2498#define OI 0x4000 /* Overflow Interrupt Generated */ 2506#define OI 0x4000 /* Overflow Interrupt Generated */
2499#define BDI 0x8000 /* Block Done Interrupt Generated */ 2507#define BDI 0x8000 /* Block Done Interrupt Generated */
2500 2508
2509/* entry addresses of the user-callable Boot ROM functions */
2510
2511#define _BOOTROM_RESET 0xEF000000
2512#define _BOOTROM_FINAL_INIT 0xEF000002
2513#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
2514#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008
2515#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A
2516#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C
2517#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
2518#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
2519#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
2520
2521/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
2522#define PGDE_UART PFDE_UART
2523#define PGDE_DMA PFDE_DMA
2524#define CKELOW SCKELOW
2501#endif /* _DEF_BF534_H */ 2525#endif /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
index 26f9c02eb73c..3f455909c418 100644
--- a/include/asm-blackfin/mach-bf537/defBF537.h
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -32,12 +32,12 @@
32#ifndef _DEF_BF537_H 32#ifndef _DEF_BF537_H
33#define _DEF_BF537_H 33#define _DEF_BF537_H
34 34
35/*include all Core registers and bit definitions*/ 35/* Include all Core registers and bit definitions*/
36#include "defBF537.h"
37
38/*include core specific register pointer definitions*/
39#include <asm/mach-common/cdef_LPBlackfin.h> 36#include <asm/mach-common/cdef_LPBlackfin.h>
40 37
38/* Include all MMR and bit defines common to BF534 */
39#include "defBF534.h"
40
41/************************************************************************************ 41/************************************************************************************
42** Define EMAC Section Unique to BF536/BF537 42** Define EMAC Section Unique to BF536/BF537
43*************************************************************************************/ 43*************************************************************************************/
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
new file mode 100644
index 000000000000..308b33ab5311
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF542.h
@@ -0,0 +1,590 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF542_H
32#define _CDEF_BF542_H
33
34/* include all Core registers and bit definitions */
35#include "defBF542.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
46
47/* ATAPI Registers */
48
49#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
50#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
51#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
52#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
53#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
54#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
55#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
56#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
57#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
58#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
59#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
60#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
61#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
62#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
63#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
64#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
65#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
66#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
67#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
68#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
69#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
70#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
71#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
72#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
73#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
74#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
75#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
76#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
77#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
78#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
79#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
80#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
81#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
82#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
83#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
84#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
85#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
86#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
87#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
88#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
89#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
90#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
91#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
92#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
93#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
94#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
95#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
96#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
97#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
98#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
99
100/* SDH Registers */
101
102#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
103#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
104#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
105#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
106#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
107#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
108#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
109#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
110#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
111#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
112#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
113#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
114#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
115#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
116#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
117#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
118#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
119#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
120#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
121#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
122#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
123#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
124#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
125#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
126#define bfin_read_SDH_DATA_CNT() fin_read16(SDH_DATA_CNT)
127#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
128#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
129#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
130#define bfin_read_SDH_STATUS_CLR() fin_read16(SDH_STATUS_CLR)
131#define bfin_write_SDH_STATUS_CLR(val) fin_write16(SDH_STATUS_CLR, val)
132#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
133#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
134#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
135#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
136#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
137#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
138#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
139#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
140#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
141#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
142#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
143#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
144#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
145#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
146#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
147#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
148#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
149#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
150#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
151#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
152#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
153#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
154#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
155#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
156#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
157#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
158#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
159#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
160#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
161#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
162#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
163#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
164
165/* USB Control Registers */
166
167#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
168#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
169#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
170#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
171#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
172#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
173#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
174#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
175#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
176#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
177#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
178#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
179#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
180#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
181#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
182#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
183#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
184#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
185#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
186#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
187#define bfin_read_USB_TESTMODE() fin_read16(USB_TESTMODE)
188#define bfin_write_USB_TESTMODE(val) fin_write16(USB_TESTMODE, val)
189#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
190#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
191#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
192#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
193
194/* USB Packet Control Registers */
195
196#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
197#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
198#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
199#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
200#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
201#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
202#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
203#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
204#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
205#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
206#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
207#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
208#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
209#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
210#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
211#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
212#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
213#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
214#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
215#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
216#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
217#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
218#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
219#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
220#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
221#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
222
223/* USB Endbfin_read_()oint FIFO Registers */
224
225#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
226#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
227#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
228#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
229#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
230#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
231#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
232#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
233#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
234#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
235#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
236#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
237#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
238#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
239#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
240#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
241
242/* USB OTG Control Registers */
243
244#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
245#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
246#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
247#define bfin_write_USB_OTG_VBUS_IRQ(val) fin_write16(USB_OTG_VBUS_IRQ, val)
248#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
249#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
250
251/* USB Phy Control Registers */
252
253#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
254#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
255#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
256#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
257#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
258#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
259#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
260#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
261#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
262#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
263
264/* (APHY_CNTRL is for ADI usage only) */
265
266#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
267#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
268
269/* (APHY_CALIB is for ADI usage only) */
270
271#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
272#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
273#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
274#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
275
276/* (PHY_TEST is for ADI usage only) */
277
278#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
279#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
280#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
281#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
282#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
283#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
284
285/* USB Endbfin_read_()oint 0 Control Registers */
286
287#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
288#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
289#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
290#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
291#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
292#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
293#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
294#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
295#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
296#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
297#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
298#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
299#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
300#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
301#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
302#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
303#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
304#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
305
306/* USB Endbfin_read_()oint 1 Control Registers */
307
308#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
309#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
310#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
311#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
312#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
313#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
314#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
315#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
316#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
317#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
318#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
319#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
320#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
321#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
322#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
323#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
324#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
325#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
326#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
327#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
328
329/* USB Endbfin_read_()oint 2 Control Registers */
330
331#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
332#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
333#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
334#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
335#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
336#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
337#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
338#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
339#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
340#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
341#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
342#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
343#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
344#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
345#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
346#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
347#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
348#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
349#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
350#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
351
352/* USB Endbfin_read_()oint 3 Control Registers */
353
354#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
355#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
356#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
357#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
358#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
359#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
360#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
361#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
362#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
363#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
364#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
365#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
366#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
367#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
368#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
369#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
370#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
371#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
372#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
373#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
374
375/* USB Endbfin_read_()oint 4 Control Registers */
376
377#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
378#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
379#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
380#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
381#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
382#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
383#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
384#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
385#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
386#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
387#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
388#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
389#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
390#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
391#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
392#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
393#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
394#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
395#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
396#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
397
398/* USB Endbfin_read_()oint 5 Control Registers */
399
400#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
401#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
402#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
403#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
404#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
405#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
406#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
407#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
408#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
409#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
410#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
411#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
412#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
413#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
414#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
415#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
416#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
417#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
418#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
419#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
420
421/* USB Endbfin_read_()oint 6 Control Registers */
422
423#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
424#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
425#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
426#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
427#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
428#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
429#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
430#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
431#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
432#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
433#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
434#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
435#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
436#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
437#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
438#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
439#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
440#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
441#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
442#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
443
444/* USB Endbfin_read_()oint 7 Control Registers */
445
446#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
447#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
448#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
449#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
450#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
451#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
452#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
453#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
454#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
455#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
456#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
457#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
458#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
459#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
460#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
461#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
462#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
463#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
464#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
465#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
466#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
467#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
468#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
469#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
470
471/* USB Channel 0 Config Registers */
472
473#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
474#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
475#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
476#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
477#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
478#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
479#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
480#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
481#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
482#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
483
484/* USB Channel 1 Config Registers */
485
486#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
487#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
488#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
489#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
490#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
491#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
492#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
493#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
494#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
495#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
496
497/* USB Channel 2 Config Registers */
498
499#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
500#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
501#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
502#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
503#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
504#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
505#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
506#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
507#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
508#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
509
510/* USB Channel 3 Config Registers */
511
512#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
513#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
514#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
515#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
516#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
517#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
518#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
519#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
520#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
521#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
522
523/* USB Channel 4 Config Registers */
524
525#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
526#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
527#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
528#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
529#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
530#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
531#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
532#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
533#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
534#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
535
536/* USB Channel 5 Config Registers */
537
538#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
539#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
540#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
541#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
542#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
543#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
544#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
545#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
546#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
547#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
548
549/* USB Channel 6 Config Registers */
550
551#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
552#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
553#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
554#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
555#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
556#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
557#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
558#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
559#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
560#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
561
562/* USB Channel 7 Config Registers */
563
564#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
565#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
566#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
567#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
568#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
569#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
570#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
571#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
572#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
573#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
574
575/* Keybfin_read_()ad Registers */
576
577#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
578#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
579#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
580#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
581#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
582#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
583#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
584#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
585#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
586#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
587#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
588#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
589
590#endif /* _CDEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
new file mode 100644
index 000000000000..7a2d177c8dc2
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF544.h
@@ -0,0 +1,978 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF544.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF544_H
32#define _CDEF_BF544_H
33
34/* include all Core registers and bit definitions */
35#include "defBF544.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* EPPI0 Registers */
84
85#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
86#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
87#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
88#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
89#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
90#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
91#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
92#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
93#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
94#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
95#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
96#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
97#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
98#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
99#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
100#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
101#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
102#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
103#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
104#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
105#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
106#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
107#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
108#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
109#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
110#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
111#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
112#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
113
114/* Two Wire Interface Registers (TWI1) */
115
116#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
117#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
118#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
119#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
120#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
121#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
122#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
123#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
124#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
125#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
126#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
127#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
128#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
129#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
130#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
131#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
132#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
133#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
134#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
135#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
136#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
137#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
138#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
139#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
140#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
141#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
142#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
143#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
144#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
145#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
146#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
147#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
148
149/* CAN Controller 1 Config 1 Registers */
150
151#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
152#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
153#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
154#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
155#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
156#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
157#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
158#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
159#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
160#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
161#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
162#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
163#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
164#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
165#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
166#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
167#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
168#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
169#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
170#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
171#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
172#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
173#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
174#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
175#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
176#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
177
178/* CAN Controller 1 Config 2 Registers */
179
180#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
181#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
182#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
183#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
184#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
185#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
186#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
187#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
188#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
189#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
190#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
191#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
192#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
193#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
194#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
195#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
196#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
197#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
198#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
199#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
200#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
201#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
202#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
203#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
204#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
205#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
206
207/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
208
209#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
210#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
211#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
212#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
213#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
214#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
215#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
216#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
217#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
218#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
219#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
220#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
221#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
222#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
223#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
224#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
225#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
226#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
227#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
228#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
229#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
230#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
231#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
232#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
233#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
234#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
235#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
236#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
237#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
238#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
239#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
240#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
241
242/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
243
244#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
245#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
246#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
247#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
248#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
249#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
250#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
251#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
252#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
253#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
254#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
255#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
256#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
257#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
258#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
259#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
260#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
261#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
262#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
263#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
264#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
265#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
266#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
267#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
268#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
269#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
270#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
271#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
272#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
273#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
274#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
275#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
276#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
277#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
278#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
279#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
280#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
281#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
282#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
283#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
284#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
285#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
286#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
287#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
288#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
289#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
290#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
291#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
292#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
293#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
294#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
295#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
296#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
297#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
298#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
299#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
300#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
301#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
302#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
303#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
304#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
305#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
306#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
307#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
308
309/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
310
311#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
312#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
313#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
314#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
315#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
316#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
317#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
318#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
319#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
320#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
321#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
322#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
323#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
324#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
325#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
326#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
327#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
328#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
329#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
330#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
331#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
332#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
333#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
334#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
335#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
336#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
337#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
338#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
339#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
340#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
341#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
342#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
343#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
344#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
345#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
346#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
347#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
348#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
349#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
350#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
351#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
352#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
353#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
354#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
355#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
356#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
357#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
358#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
359#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
360#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
361#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
362#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
363#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
364#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
365#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
366#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
367#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
368#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
369#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
370#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
371#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
372#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
373#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
374#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
375
376/* CAN Controller 1 Mailbox Data Registers */
377
378#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
379#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
380#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
381#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
382#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
383#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
384#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
385#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
386#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
387#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
388#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
389#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
390#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
391#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
392#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
393#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
394#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
395#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
396#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
397#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
398#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
399#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
400#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
401#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
402#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
403#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
404#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
405#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
406#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
407#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
408#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
409#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
410#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
411#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
412#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
413#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
414#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
415#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
416#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
417#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
418#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
419#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
420#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
421#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
422#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
423#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
424#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
425#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
426#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
427#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
428#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
429#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
430#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
431#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
432#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
433#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
434#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
435#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
436#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
437#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
438#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
439#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
440#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
441#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
442#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
443#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
444#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
445#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
446#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
447#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
448#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
449#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
450#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
451#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
452#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
453#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
454#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
455#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
456#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
457#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
458#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
459#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
460#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
461#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
462#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
463#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
464#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
465#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
466#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
467#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
468#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
469#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
470#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
471#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
472#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
473#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
474#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
475#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
476#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
477#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
478#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
479#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
480#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
481#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
482#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
483#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
484#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
485#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
486#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
487#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
488#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
489#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
490#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
491#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
492#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
493#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
494#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
495#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
496#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
497#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
498#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
499#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
500#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
501#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
502#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
503#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
504#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
505#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
506#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
507#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
508#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
509#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
510#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
511#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
512#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
513#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
514#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
515#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
516#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
517#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
518#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
519#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
520#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
521#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
522#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
523#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
524#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
525#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
526#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
527#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
528#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
529#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
530#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
531#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
532#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
533#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
534#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
535#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
536#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
537#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
538#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
539#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
540#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
541#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
542#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
543#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
544#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
545#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
546#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
547#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
548#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
549#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
550#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
551#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
552#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
553#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
554#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
555#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
556#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
557#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
558#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
559#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
560#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
561#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
562#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
563#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
564#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
565#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
566#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
567#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
568#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
569#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
570#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
571#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
572#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
573#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
574#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
575#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
576#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
577#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
578#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
579#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
580#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
581#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
582#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
583#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
584#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
585#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
586#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
587#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
588#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
589#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
590#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
591#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
592#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
593#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
594#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
595#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
596#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
597#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
598#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
599#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
600#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
601#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
602#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
603#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
604#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
605#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
606#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
607#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
608#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
609#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
610#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
611#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
612#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
613#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
614#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
615#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
616#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
617#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
618#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
619#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
620#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
621#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
622#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
623#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
624#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
625#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
626#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
627#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
628#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
629#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
630#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
631#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
632#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
633#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
634
635/* CAN Controller 1 Mailbox Data Registers */
636
637#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
638#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
639#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
640#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
641#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
642#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
643#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
644#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
645#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
646#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
647#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
648#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
649#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
650#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
651#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
652#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
653#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
654#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
655#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
656#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
657#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
658#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
659#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
660#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
661#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
662#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
663#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
664#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
665#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
666#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
667#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
668#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
669#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
670#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
671#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
672#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
673#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
674#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
675#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
676#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
677#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
678#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
679#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
680#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
681#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
682#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
683#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
684#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
685#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
686#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
687#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
688#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
689#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
690#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
691#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
692#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
693#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
694#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
695#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
696#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
697#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
698#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
699#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
700#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
701#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
702#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
703#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
704#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
705#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
706#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
707#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
708#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
709#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
710#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
711#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
712#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
713#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
714#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
715#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
716#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
717#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
718#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
719#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
720#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
721#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
722#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
723#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
724#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
725#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
726#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
727#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
728#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
729#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
730#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
731#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
732#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
733#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
734#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
735#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
736#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
737#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
738#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
739#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
740#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
741#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
742#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
743#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
744#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
745#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
746#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
747#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
748#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
749#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
750#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
751#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
752#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
753#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
754#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
755#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
756#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
757#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
758#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
759#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
760#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
761#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
762#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
763#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
764#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
765#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
766#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
767#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
768#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
769#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
770#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
771#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
772#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
773#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
774#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
775#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
776#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
777#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
778#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
779#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
780#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
781#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
782#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
783#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
784#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
785#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
786#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
787#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
788#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
789#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
790#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
791#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
792#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
793#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
794#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
795#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
796#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
797#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
798#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
799#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
800#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
801#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
802#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
803#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
804#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
805#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
806#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
807#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
808#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
809#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
810#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
811#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
812#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
813#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
814#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
815#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
816#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
817#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
818#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
819#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
820#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
821#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
822#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
823#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
824#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
825#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
826#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
827#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
828#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
829#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
830#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
831#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
832#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
833#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
834#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
835#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
836#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
837#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
838#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
839#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
840#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
841#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
842#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
843#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
844#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
845#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
846#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
847#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
848#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
849#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
850#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
851#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
852#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
853#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
854#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
855#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
856#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
857#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
858#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
859#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
860#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
861#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
862#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
863#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
864#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
865#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
866#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
867#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
868#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
869#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
870#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
871#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
872#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
873#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
874#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
875#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
876#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
877#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
878#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
879#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
880#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
881#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
882#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
883#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
884#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
885#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
886#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
887#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
888#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
889#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
890#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
891#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
892#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
893
894/* HOST Port Registers */
895
896#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
897#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
898#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
899#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
900#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
901#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
902
903/* Pixel Combfin_read_()ositor (PIXC) Registers */
904
905#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
906#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
907#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
908#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
909#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
910#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
911#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
912#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
913#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
914#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
915#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
916#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
917#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
918#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
919#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
920#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
921#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
922#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
923#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
924#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
925#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
926#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
927#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
928#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
929#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
930#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
931#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
932#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
933#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
934#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
935#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
936#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
937#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
938#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
939#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
940#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
941#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
942#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
943
944/* Handshake MDMA 0 Registers */
945
946#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
947#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
948#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
949#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
950#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
951#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
952#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
953#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
954#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
955#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
956#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
957#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
958#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
959#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
960
961/* Handshake MDMA 1 Registers */
962
963#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
964#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
965#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
966#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
967#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
968#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
969#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
970#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
971#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
972#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
973#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
974#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
975#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
976#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
977
978#endif /* _CDEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
new file mode 100644
index 000000000000..674be0216bff
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF548.h
@@ -0,0 +1,1610 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF548_H
32#define _CDEF_BF548_H
33
34/* include all Core registers and bit definitions */
35#include "defBF548.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */
222
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
224#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
225#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
226#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
227#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
228#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
229#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
230#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
231#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
232#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
233#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
234#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
235#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
236#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
237
238/* CAN Controller 1 Config 1 Registers */
239
240#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
241#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
242#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
243#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
244#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
245#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
246#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
247#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
248#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
249#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
250#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
251#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
252#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
253#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
254#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
255#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
256#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
257#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
258#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
259#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
260#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
261#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
262#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
263#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
264#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
265#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
266
267/* CAN Controller 1 Config 2 Registers */
268
269#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
270#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
271#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
272#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
273#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
274#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
275#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
276#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
277#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
278#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
279#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
280#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
281#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
282#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
283#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
284#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
285#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
286#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
287#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
288#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
289#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
290#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
291#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
292#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
293#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
294#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
295
296/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
297
298#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
299#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
300#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
301#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
302#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
303#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
304#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
305#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
306#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
307#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
308#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
309#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
310#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
311#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
312#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
313#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
314#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
315#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
316#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
317#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
318#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
319#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
320#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
321#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
322#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
323#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
324#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
325#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
326#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
327#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
328#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
329#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
330
331/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
332
333#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
334#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
335#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
336#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
337#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
338#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
339#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
340#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
341#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
342#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
343#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
344#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
345#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
346#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
347#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
348#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
349#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
350#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
351#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
352#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
353#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
354#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
355#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
356#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
357#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
358#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
359#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
360#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
361#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
362#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
363#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
364#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
365#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
366#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
367#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
368#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
369#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
370#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
371#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
372#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
373#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
374#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
375#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
376#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
377#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
378#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
379#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
380#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
381#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
382#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
383#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
384#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
385#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
386#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
387#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
388#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
389#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
390#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
391#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
392#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
393#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
394#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
395#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
396#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
397
398/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
399
400#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
401#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
402#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
403#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
404#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
405#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
406#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
407#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
408#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
409#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
410#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
411#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
412#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
413#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
414#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
415#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
416#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
417#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
418#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
419#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
420#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
421#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
422#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
423#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
424#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
425#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
426#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
427#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
428#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
429#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
430#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
431#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
432#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
433#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
434#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
435#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
436#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
437#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
438#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
439#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
440#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
441#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
442#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
443#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
444#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
445#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
446#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
447#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
448#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
449#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
450#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
451#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
452#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
453#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
454#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
455#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
456#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
457#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
458#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
459#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
460#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
461#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
462#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
463#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
464
465/* CAN Controller 1 Mailbox Data Registers */
466
467#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
468#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
469#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
470#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
471#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
472#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
473#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
474#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
475#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
476#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
477#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
478#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
479#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
480#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
481#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
482#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
483#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
484#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
485#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
486#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
487#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
488#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
489#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
490#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
491#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
492#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
493#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
494#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
495#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
496#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
497#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
498#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
499#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
500#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
501#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
502#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
503#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
504#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
505#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
506#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
507#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
508#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
509#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
510#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
511#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
512#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
513#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
514#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
515#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
516#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
517#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
518#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
519#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
520#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
521#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
522#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
523#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
524#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
525#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
526#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
527#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
528#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
529#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
530#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
531#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
532#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
533#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
534#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
535#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
536#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
537#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
538#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
539#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
540#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
541#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
542#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
543#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
544#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
545#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
546#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
547#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
548#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
549#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
550#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
551#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
552#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
553#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
554#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
555#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
556#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
557#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
558#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
559#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
560#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
561#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
562#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
563#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
564#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
565#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
566#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
567#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
568#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
569#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
570#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
571#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
572#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
573#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
574#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
575#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
576#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
577#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
578#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
579#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
580#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
581#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
582#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
583#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
584#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
585#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
586#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
587#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
588#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
589#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
590#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
591#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
592#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
593#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
594#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
595#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
596#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
597#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
598#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
599#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
600#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
601#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
602#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
603#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
604#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
605#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
606#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
607#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
608#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
609#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
610#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
611#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
612#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
613#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
614#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
615#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
616#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
617#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
618#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
619#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
620#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
621#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
622#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
623#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
624#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
625#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
626#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
627#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
628#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
629#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
630#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
631#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
632#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
633#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
634#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
635#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
636#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
637#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
638#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
639#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
640#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
641#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
642#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
643#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
644#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
645#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
646#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
647#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
648#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
649#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
650#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
651#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
652#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
653#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
654#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
655#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
656#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
657#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
658#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
659#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
660#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
661#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
662#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
663#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
664#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
665#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
666#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
667#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
668#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
669#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
670#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
671#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
672#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
673#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
674#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
675#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
676#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
677#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
678#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
679#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
680#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
681#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
682#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
683#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
684#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
685#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
686#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
687#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
688#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
689#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
690#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
691#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
692#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
693#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
694#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
695#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
696#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
697#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
698#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
699#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
700#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
701#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
702#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
703#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
704#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
705#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
706#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
707#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
708#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
709#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
710#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
711#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
712#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
713#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
714#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
715#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
716#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
717#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
718#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
719#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
720#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
721#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
722#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
723
724/* CAN Controller 1 Mailbox Data Registers */
725
726#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
727#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
728#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
729#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
730#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
731#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
732#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
733#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
734#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
735#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
736#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
737#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
738#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
739#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
740#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
741#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
742#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
743#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
744#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
745#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
746#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
747#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
748#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
749#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
750#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
751#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
752#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
753#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
754#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
755#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
756#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
757#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
758#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
759#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
760#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
761#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
762#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
763#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
764#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
765#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
766#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
767#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
768#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
769#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
770#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
771#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
772#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
773#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
774#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
775#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
776#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
777#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
778#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
779#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
780#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
781#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
782#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
783#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
784#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
785#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
786#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
787#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
788#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
789#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
790#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
791#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
792#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
793#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
794#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
795#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
796#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
797#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
798#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
799#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
800#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
801#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
802#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
803#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
804#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
805#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
806#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
807#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
808#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
809#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
810#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
811#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
812#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
813#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
814#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
815#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
816#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
817#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
818#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
819#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
820#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
821#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
822#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
823#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
824#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
825#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
826#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
827#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
828#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
829#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
830#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
831#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
832#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
833#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
834#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
835#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
836#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
837#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
838#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
839#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
840#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
841#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
842#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
843#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
844#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
845#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
846#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
847#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
848#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
849#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
850#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
851#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
852#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
853#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
854#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
855#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
856#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
857#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
858#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
859#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
860#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
861#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
862#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
863#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
864#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
865#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
866#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
867#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
868#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
869#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
870#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
871#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
872#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
873#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
874#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
875#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
876#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
877#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
878#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
879#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
880#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
881#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
882#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
883#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
884#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
885#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
886#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
887#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
888#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
889#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
890#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
891#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
892#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
893#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
894#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
895#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
896#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
897#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
898#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
899#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
900#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
901#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
902#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
903#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
904#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
905#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
906#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
907#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
908#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
909#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
910#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
911#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
912#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
913#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
914#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
915#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
916#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
917#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
918#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
919#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
920#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
921#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
922#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
923#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
924#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
925#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
926#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
927#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
928#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
929#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
930#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
931#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
932#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
933#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
934#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
935#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
936#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
937#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
938#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
939#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
940#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
941#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
942#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
943#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
944#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
945#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
946#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
947#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
948#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
949#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
950#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
951#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
952#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
953#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
954#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
955#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
956#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
957#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
958#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
959#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
960#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
961#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
962#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
963#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
964#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
965#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
966#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
967#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
968#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
969#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
970#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
971#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
972#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
973#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
974#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
975#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
976#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
977#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
978#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
979#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
980#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
981#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
982
983/* ATAPI Registers */
984
985#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
986#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
987#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
988#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
989#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
990#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
991#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
992#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
993#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
994#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
995#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
996#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
997#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
998#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
999#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
1000#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
1001#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
1002#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
1003#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
1004#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
1005#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
1006#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
1007#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
1008#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
1009#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
1010#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
1011#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
1012#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
1013#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
1014#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
1015#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
1016#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
1017#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
1018#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
1019#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
1020#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
1021#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
1022#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
1023#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
1024#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
1025#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
1026#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
1027#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
1028#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
1029#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
1030#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
1031#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
1032#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1033#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1034#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1035
1036/* SDH Registers */
1037
1038#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1039#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1040#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1041#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1042#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1043#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1044#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1045#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1046#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1047#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1048#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1049#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1050#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1051#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1052#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1053#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1054#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1055#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1056#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1057#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1058#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1059#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1060#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1061#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1062#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1063#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1064#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1065#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1066#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1067#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1068#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1069#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1070#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1071#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1072#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1073#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1074#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1075#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1076#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1077#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1078#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1079#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1080#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1081#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1082#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1083#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1084#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1085#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1086#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1087#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1088#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1089#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1090#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1091#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1092#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1093#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1094#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1095#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1096#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1097#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1098#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1099#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1100
1101/* HOST Port Registers */
1102
1103#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1104#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1105#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1106#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1107#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1108#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1109
1110/* USB Control Registers */
1111
1112#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1113#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1114#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1115#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1116#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1117#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1118#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1119#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1120#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1121#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1122#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1123#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1124#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1125#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1126#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1127#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1128#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1129#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1130#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1131#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1132#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1133#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1134#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1135#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1136#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1137#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1138
1139/* USB Packet Control Registers */
1140
1141#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1142#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1143#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1144#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1145#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1146#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1147#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1148#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1149#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1150#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1151#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1152#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1153#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1154#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1155#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1156#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1157#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1158#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1159#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1160#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1161#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1162#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1163#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1164#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1165#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1166#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1167
1168/* USB Endbfin_read_()oint FIFO Registers */
1169
1170#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1171#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1172#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1173#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1174#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1175#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1176#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1177#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1178#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1179#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1180#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1181#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1182#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1183#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1184#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1185#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1186
1187/* USB OTG Control Registers */
1188
1189#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1190#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1191#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1192#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1193#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1194#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1195
1196/* USB Phy Control Registers */
1197
1198#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1199#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1200#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1201#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1202#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1203#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1204#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1205#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1206#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1207#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1208
1209/* (APHY_CNTRL is for ADI usage only) */
1210
1211#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1212#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1213
1214/* (APHY_CALIB is for ADI usage only) */
1215
1216#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1217#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1218#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1219#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1220
1221/* (PHY_TEST is for ADI usage only) */
1222
1223#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1224#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1225#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1226#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1227#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1228#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1229
1230/* USB Endbfin_read_()oint 0 Control Registers */
1231
1232#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1233#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1234#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1235#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1236#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1237#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1238#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1239#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1240#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1241#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1242#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1243#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1244#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1245#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1246#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1247#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1248#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1249#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1250
1251/* USB Endbfin_read_()oint 1 Control Registers */
1252
1253#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1254#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1255#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1256#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1257#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1258#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1259#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1260#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1261#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1262#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1263#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1264#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1265#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1266#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1267#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1268#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1269#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1270#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1271#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1272#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1273
1274/* USB Endbfin_read_()oint 2 Control Registers */
1275
1276#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1277#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1278#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1279#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1280#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1281#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1282#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1283#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1284#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1285#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1286#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1287#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1288#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1289#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1290#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1291#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1292#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1293#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1294#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1295#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1296
1297/* USB Endbfin_read_()oint 3 Control Registers */
1298
1299#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1300#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1301#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1302#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1303#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1304#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1305#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1306#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1307#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1308#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1309#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1310#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1311#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1312#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1313#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1314#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1315#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1316#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1317#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1318#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1319
1320/* USB Endbfin_read_()oint 4 Control Registers */
1321
1322#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1323#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1324#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1325#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1326#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1327#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1328#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1329#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1330#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1331#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1332#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1333#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1334#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1335#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1336#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1337#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1338#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1339#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1340#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1341#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1342
1343/* USB Endbfin_read_()oint 5 Control Registers */
1344
1345#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1346#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1347#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1348#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1349#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1350#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1351#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1352#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1353#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1354#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1355#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1356#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1357#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1358#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1359#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1360#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1361#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1362#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1363#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1364#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1365
1366/* USB Endbfin_read_()oint 6 Control Registers */
1367
1368#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1369#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1370#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1371#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1372#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1373#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1374#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1375#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1376#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1377#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1378#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1379#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1380#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1381#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1382#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1383#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1384#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1385#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1386#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1387#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1388
1389/* USB Endbfin_read_()oint 7 Control Registers */
1390
1391#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1392#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1393#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1394#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1395#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1396#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1397#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1398#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1399#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1400#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1401#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1402#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1403#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1404#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1405#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1406#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1407#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1408#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1409#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1410#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1411#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1412#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1413#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1414#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1415
1416/* USB Channel 0 Config Registers */
1417
1418#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1419#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1420#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1421#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1422#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1423#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1424#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1425#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1426#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1427#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1428
1429/* USB Channel 1 Config Registers */
1430
1431#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1432#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1433#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1434#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1435#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1436#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1437#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1438#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1439#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1440#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1441
1442/* USB Channel 2 Config Registers */
1443
1444#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1445#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1446#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1447#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1448#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1449#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1450#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1451#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1452#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1453#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1454
1455/* USB Channel 3 Config Registers */
1456
1457#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1458#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1459#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1460#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1461#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1462#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1463#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1464#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1465#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1466#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1467
1468/* USB Channel 4 Config Registers */
1469
1470#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1471#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1472#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1473#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1474#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1475#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1476#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1477#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1478#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1479#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1480
1481/* USB Channel 5 Config Registers */
1482
1483#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1484#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1485#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1486#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1487#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1488#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1489#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1490#define bfin_write_USB_DMA5COUNTLOW(val) bfin_write16(USB_DMA5COUNTLOW, val)
1491#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1492#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1493
1494/* USB Channel 6 Config Registers */
1495
1496#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1497#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1498#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1499#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1500#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1501#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1502#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1503#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1504#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1505#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1506
1507/* USB Channel 7 Config Registers */
1508
1509#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1510#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1511#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1512#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1513#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1514#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1515#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1516#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1517#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1518#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1519
1520/* Keybfin_read_()ad Registers */
1521
1522#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1523#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1524#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1525#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1526#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1527#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1528#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1529#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1530#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1531#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1532#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1533#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1534
1535/* Pixel Combfin_read_()ositor (PIXC) Registers */
1536
1537#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1538#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1539#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1540#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1541#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1542#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1543#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1544#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1545#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1546#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1547#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1548#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1549#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1550#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1551#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1552#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1553#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1554#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1555#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1556#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1557#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1558#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1559#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1560#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1561#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1562#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1563#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1564#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1565#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1566#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1567#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1568#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1569#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1570#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1571#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1572#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1573#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1574#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1575
1576/* Handshake MDMA 0 Registers */
1577
1578#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1579#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1580#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1581#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1582#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1583#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1584#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1585#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1586#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1587#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1588#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1589#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1590#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1591#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1592
1593/* Handshake MDMA 1 Registers */
1594
1595#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1596#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1597#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1598#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1599#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1600#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1601#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1602#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1603#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1604#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1605#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1606#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1607#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1608#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1609
1610#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
new file mode 100644
index 000000000000..2ab5b7c00820
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF549.h
@@ -0,0 +1,1896 @@
1/*
2 * File: include/asm-blackfin/mach-bf549/cdefBF549.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF549_H
32#define _CDEF_BF549_H
33
34/* include all Core registers and bit definitions */
35#include "defBF549.h"
36
37/* include core sbfin_read_()ecific register pointer definitions */
38#include <asm/mach-common/cdef_LPBlackfin.h>
39
40/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
41
42/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
43#include "cdefBF54x_base.h"
44
45/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
46
47/* Timer Registers */
48
49#define bfin_read_TIMER8_CONFIG() bfin_read16(TIMER8_CONFIG)
50#define bfin_write_TIMER8_CONFIG(val) bfin_write16(TIMER8_CONFIG, val)
51#define bfin_read_TIMER8_COUNTER() bfin_read32(TIMER8_COUNTER)
52#define bfin_write_TIMER8_COUNTER(val) bfin_write32(TIMER8_COUNTER, val)
53#define bfin_read_TIMER8_PERIOD() bfin_read32(TIMER8_PERIOD)
54#define bfin_write_TIMER8_PERIOD(val) bfin_write32(TIMER8_PERIOD, val)
55#define bfin_read_TIMER8_WIDTH() bfin_read32(TIMER8_WIDTH)
56#define bfin_write_TIMER8_WIDTH(val) bfin_write32(TIMER8_WIDTH, val)
57#define bfin_read_TIMER9_CONFIG() bfin_read16(TIMER9_CONFIG)
58#define bfin_write_TIMER9_CONFIG(val) bfin_write16(TIMER9_CONFIG, val)
59#define bfin_read_TIMER9_COUNTER() bfin_read32(TIMER9_COUNTER)
60#define bfin_write_TIMER9_COUNTER(val) bfin_write32(TIMER9_COUNTER, val)
61#define bfin_read_TIMER9_PERIOD() bfin_read32(TIMER9_PERIOD)
62#define bfin_write_TIMER9_PERIOD(val) bfin_write32(TIMER9_PERIOD, val)
63#define bfin_read_TIMER9_WIDTH() bfin_read32(TIMER9_WIDTH)
64#define bfin_write_TIMER9_WIDTH(val) bfin_write32(TIMER9_WIDTH, val)
65#define bfin_read_TIMER10_CONFIG() bfin_read16(TIMER10_CONFIG)
66#define bfin_write_TIMER10_CONFIG(val) bfin_write16(TIMER10_CONFIG, val)
67#define bfin_read_TIMER10_COUNTER() bfin_read32(TIMER10_COUNTER)
68#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
69#define bfin_read_TIMER10_PERIOD() bfin_read32(TIMER10_PERIOD)
70#define bfin_write_TIMER10_PERIOD(val) bfin_write32(TIMER10_PERIOD, val)
71#define bfin_read_TIMER10_WIDTH() bfin_read32(TIMER10_WIDTH)
72#define bfin_write_TIMER10_WIDTH(val) bfin_write32(TIMER10_WIDTH, val)
73
74/* Timer Groubfin_read_() of 3 */
75
76#define bfin_read_TIMER_ENABLE1() bfin_read16(TIMER_ENABLE1)
77#define bfin_write_TIMER_ENABLE1(val) bfin_write16(TIMER_ENABLE1, val)
78#define bfin_read_TIMER_DISABLE1() bfin_read16(TIMER_DISABLE1)
79#define bfin_write_TIMER_DISABLE1(val) bfin_write16(TIMER_DISABLE1, val)
80#define bfin_read_TIMER_STATUS1() bfin_read32(TIMER_STATUS1)
81#define bfin_write_TIMER_STATUS1(val) bfin_write32(TIMER_STATUS1, val)
82
83/* SPORT0 Registers */
84
85#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
86#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
87#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
88#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
89#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
90#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
91#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
92#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
93#define bfin_read_SPORT0_TX() bfin_read32(SPORT0_TX)
94#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
95#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
96#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
97#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
98#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
99#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
100#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
101#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
102#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
103#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
104#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
105#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
106#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
107#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
108#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
109#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
110#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
111#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
112#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
113#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
114#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
115#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
116#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
117#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
118#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
119#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
120#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
121#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
122#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
123#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
124#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
125#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
126#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
127#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
128#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
129
130/* EPPI0 Registers */
131
132#define bfin_read_EPPI0_STATUS() bfin_read16(EPPI0_STATUS)
133#define bfin_write_EPPI0_STATUS(val) bfin_write16(EPPI0_STATUS, val)
134#define bfin_read_EPPI0_HCOUNT() bfin_read16(EPPI0_HCOUNT)
135#define bfin_write_EPPI0_HCOUNT(val) bfin_write16(EPPI0_HCOUNT, val)
136#define bfin_read_EPPI0_HDELAY() bfin_read16(EPPI0_HDELAY)
137#define bfin_write_EPPI0_HDELAY(val) bfin_write16(EPPI0_HDELAY, val)
138#define bfin_read_EPPI0_VCOUNT() bfin_read16(EPPI0_VCOUNT)
139#define bfin_write_EPPI0_VCOUNT(val) bfin_write16(EPPI0_VCOUNT, val)
140#define bfin_read_EPPI0_VDELAY() bfin_read16(EPPI0_VDELAY)
141#define bfin_write_EPPI0_VDELAY(val) bfin_write16(EPPI0_VDELAY, val)
142#define bfin_read_EPPI0_FRAME() bfin_read16(EPPI0_FRAME)
143#define bfin_write_EPPI0_FRAME(val) bfin_write16(EPPI0_FRAME, val)
144#define bfin_read_EPPI0_LINE() bfin_read16(EPPI0_LINE)
145#define bfin_write_EPPI0_LINE(val) bfin_write16(EPPI0_LINE, val)
146#define bfin_read_EPPI0_CLKDIV() bfin_read16(EPPI0_CLKDIV)
147#define bfin_write_EPPI0_CLKDIV(val) bfin_write16(EPPI0_CLKDIV, val)
148#define bfin_read_EPPI0_CONTROL() bfin_read32(EPPI0_CONTROL)
149#define bfin_write_EPPI0_CONTROL(val) bfin_write32(EPPI0_CONTROL, val)
150#define bfin_read_EPPI0_FS1W_HBL() bfin_read32(EPPI0_FS1W_HBL)
151#define bfin_write_EPPI0_FS1W_HBL(val) bfin_write32(EPPI0_FS1W_HBL, val)
152#define bfin_read_EPPI0_FS1P_AVPL() bfin_read32(EPPI0_FS1P_AVPL)
153#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
154#define bfin_read_EPPI0_FS2W_LVB() bfin_read32(EPPI0_FS2W_LVB)
155#define bfin_write_EPPI0_FS2W_LVB(val) bfin_write32(EPPI0_FS2W_LVB, val)
156#define bfin_read_EPPI0_FS2P_LAVF() bfin_read32(EPPI0_FS2P_LAVF)
157#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
158#define bfin_read_EPPI0_CLIP() bfin_read32(EPPI0_CLIP)
159#define bfin_write_EPPI0_CLIP(val) bfin_write32(EPPI0_CLIP, val)
160
161/* UART2 Registers */
162
163#define bfin_read_UART2_DLL() bfin_read16(UART2_DLL)
164#define bfin_write_UART2_DLL(val) bfin_write16(UART2_DLL, val)
165#define bfin_read_UART2_DLH() bfin_read16(UART2_DLH)
166#define bfin_write_UART2_DLH(val) bfin_write16(UART2_DLH, val)
167#define bfin_read_UART2_GCTL() bfin_read16(UART2_GCTL)
168#define bfin_write_UART2_GCTL(val) bfin_write16(UART2_GCTL, val)
169#define bfin_read_UART2_LCR() bfin_read16(UART2_LCR)
170#define bfin_write_UART2_LCR(val) bfin_write16(UART2_LCR, val)
171#define bfin_read_UART2_MCR() bfin_read16(UART2_MCR)
172#define bfin_write_UART2_MCR(val) bfin_write16(UART2_MCR, val)
173#define bfin_read_UART2_LSR() bfin_read16(UART2_LSR)
174#define bfin_write_UART2_LSR(val) bfin_write16(UART2_LSR, val)
175#define bfin_read_UART2_MSR() bfin_read16(UART2_MSR)
176#define bfin_write_UART2_MSR(val) bfin_write16(UART2_MSR, val)
177#define bfin_read_UART2_SCR() bfin_read16(UART2_SCR)
178#define bfin_write_UART2_SCR(val) bfin_write16(UART2_SCR, val)
179#define bfin_read_UART2_IER_SET() bfin_read16(UART2_IER_SET)
180#define bfin_write_UART2_IER_SET(val) bfin_write16(UART2_IER_SET, val)
181#define bfin_read_UART2_IER_CLEAR() bfin_read16(UART2_IER_CLEAR)
182#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
183#define bfin_read_UART2_RBR() bfin_read16(UART2_RBR)
184#define bfin_write_UART2_RBR(val) bfin_write16(UART2_RBR, val)
185
186/* Two Wire Interface Registers (TWI1) */
187
188#define bfin_read_TWI1_CLKDIV() bfin_read16(TWI1_CLKDIV)
189#define bfin_write_TWI1_CLKDIV(val) bfin_write16(TWI1_CLKDIV, val)
190#define bfin_read_TWI1_CONTROL() bfin_read16(TWI1_CONTROL)
191#define bfin_write_TWI1_CONTROL(val) bfin_write16(TWI1_CONTROL, val)
192#define bfin_read_TWI1_SLAVE_CTRL() bfin_read16(TWI1_SLAVE_CTRL)
193#define bfin_write_TWI1_SLAVE_CTRL(val) bfin_write16(TWI1_SLAVE_CTRL, val)
194#define bfin_read_TWI1_SLAVE_STAT() bfin_read16(TWI1_SLAVE_STAT)
195#define bfin_write_TWI1_SLAVE_STAT(val) bfin_write16(TWI1_SLAVE_STAT, val)
196#define bfin_read_TWI1_SLAVE_ADDR() bfin_read16(TWI1_SLAVE_ADDR)
197#define bfin_write_TWI1_SLAVE_ADDR(val) bfin_write16(TWI1_SLAVE_ADDR, val)
198#define bfin_read_TWI1_MASTER_CTRL() bfin_read16(TWI1_MASTER_CTRL)
199#define bfin_write_TWI1_MASTER_CTRL(val) bfin_write16(TWI1_MASTER_CTRL, val)
200#define bfin_read_TWI1_MASTER_STAT() bfin_read16(TWI1_MASTER_STAT)
201#define bfin_write_TWI1_MASTER_STAT(val) bfin_write16(TWI1_MASTER_STAT, val)
202#define bfin_read_TWI1_MASTER_ADDR() bfin_read16(TWI1_MASTER_ADDR)
203#define bfin_write_TWI1_MASTER_ADDR(val) bfin_write16(TWI1_MASTER_ADDR, val)
204#define bfin_read_TWI1_INT_STAT() bfin_read16(TWI1_INT_STAT)
205#define bfin_write_TWI1_INT_STAT(val) bfin_write16(TWI1_INT_STAT, val)
206#define bfin_read_TWI1_INT_MASK() bfin_read16(TWI1_INT_MASK)
207#define bfin_write_TWI1_INT_MASK(val) bfin_write16(TWI1_INT_MASK, val)
208#define bfin_read_TWI1_FIFO_CTRL() bfin_read16(TWI1_FIFO_CTRL)
209#define bfin_write_TWI1_FIFO_CTRL(val) bfin_write16(TWI1_FIFO_CTRL, val)
210#define bfin_read_TWI1_FIFO_STAT() bfin_read16(TWI1_FIFO_STAT)
211#define bfin_write_TWI1_FIFO_STAT(val) bfin_write16(TWI1_FIFO_STAT, val)
212#define bfin_read_TWI1_XMT_DATA8() bfin_read16(TWI1_XMT_DATA8)
213#define bfin_write_TWI1_XMT_DATA8(val) bfin_write16(TWI1_XMT_DATA8, val)
214#define bfin_read_TWI1_XMT_DATA16() bfin_read16(TWI1_XMT_DATA16)
215#define bfin_write_TWI1_XMT_DATA16(val) bfin_write16(TWI1_XMT_DATA16, val)
216#define bfin_read_TWI1_RCV_DATA8() bfin_read16(TWI1_RCV_DATA8)
217#define bfin_write_TWI1_RCV_DATA8(val) bfin_write16(TWI1_RCV_DATA8, val)
218#define bfin_read_TWI1_RCV_DATA16() bfin_read16(TWI1_RCV_DATA16)
219#define bfin_write_TWI1_RCV_DATA16(val) bfin_write16(TWI1_RCV_DATA16, val)
220
221/* SPI2 Registers */
222
223#define bfin_read_SPI2_CTL() bfin_read16(SPI2_CTL)
224#define bfin_write_SPI2_CTL(val) bfin_write16(SPI2_CTL, val)
225#define bfin_read_SPI2_FLG() bfin_read16(SPI2_FLG)
226#define bfin_write_SPI2_FLG(val) bfin_write16(SPI2_FLG, val)
227#define bfin_read_SPI2_STAT() bfin_read16(SPI2_STAT)
228#define bfin_write_SPI2_STAT(val) bfin_write16(SPI2_STAT, val)
229#define bfin_read_SPI2_TDBR() bfin_read16(SPI2_TDBR)
230#define bfin_write_SPI2_TDBR(val) bfin_write16(SPI2_TDBR, val)
231#define bfin_read_SPI2_RDBR() bfin_read16(SPI2_RDBR)
232#define bfin_write_SPI2_RDBR(val) bfin_write16(SPI2_RDBR, val)
233#define bfin_read_SPI2_BAUD() bfin_read16(SPI2_BAUD)
234#define bfin_write_SPI2_BAUD(val) bfin_write16(SPI2_BAUD, val)
235#define bfin_read_SPI2_SHADOW() bfin_read16(SPI2_SHADOW)
236#define bfin_write_SPI2_SHADOW(val) bfin_write16(SPI2_SHADOW, val)
237
238/* MXVR Registers */
239
240#define bfin_read_MXVR_CONFIG() bfin_read16(MXVR_CONFIG)
241#define bfin_write_MXVR_CONFIG(val) bfin_write16(MXVR_CONFIG, val)
242#define bfin_read_MXVR_STATE_0() bfin_read32(MXVR_STATE_0)
243#define bfin_write_MXVR_STATE_0(val) bfin_write32(MXVR_STATE_0, val)
244#define bfin_read_MXVR_STATE_1() bfin_read32(MXVR_STATE_1)
245#define bfin_write_MXVR_STATE_1(val) bfin_write32(MXVR_STATE_1, val)
246#define bfin_read_MXVR_INT_STAT_0() bfin_read32(MXVR_INT_STAT_0)
247#define bfin_write_MXVR_INT_STAT_0(val) bfin_write32(MXVR_INT_STAT_0, val)
248#define bfin_read_MXVR_INT_STAT_1() bfin_read32(MXVR_INT_STAT_1)
249#define bfin_write_MXVR_INT_STAT_1(val) bfin_write32(MXVR_INT_STAT_1, val)
250#define bfin_read_MXVR_INT_EN_0() bfin_read32(MXVR_INT_EN_0)
251#define bfin_write_MXVR_INT_EN_0(val) bfin_write32(MXVR_INT_EN_0, val)
252#define bfin_read_MXVR_INT_EN_1() bfin_read32(MXVR_INT_EN_1)
253#define bfin_write_MXVR_INT_EN_1(val) bfin_write32(MXVR_INT_EN_1, val)
254#define bfin_read_MXVR_POSITION() bfin_read16(MXVR_POSITION)
255#define bfin_write_MXVR_POSITION(val) bfin_write16(MXVR_POSITION, val)
256#define bfin_read_MXVR_MAX_POSITION() bfin_read16(MXVR_MAX_POSITION)
257#define bfin_write_MXVR_MAX_POSITION(val) bfin_write16(MXVR_MAX_POSITION, val)
258#define bfin_read_MXVR_DELAY() bfin_read16(MXVR_DELAY)
259#define bfin_write_MXVR_DELAY(val) bfin_write16(MXVR_DELAY, val)
260#define bfin_read_MXVR_MAX_DELAY() bfin_read16(MXVR_MAX_DELAY)
261#define bfin_write_MXVR_MAX_DELAY(val) bfin_write16(MXVR_MAX_DELAY, val)
262#define bfin_read_MXVR_LADDR() bfin_read32(MXVR_LADDR)
263#define bfin_write_MXVR_LADDR(val) bfin_write32(MXVR_LADDR, val)
264#define bfin_read_MXVR_GADDR() bfin_read16(MXVR_GADDR)
265#define bfin_write_MXVR_GADDR(val) bfin_write16(MXVR_GADDR, val)
266#define bfin_read_MXVR_AADDR() bfin_read32(MXVR_AADDR)
267#define bfin_write_MXVR_AADDR(val) bfin_write32(MXVR_AADDR, val)
268
269/* MXVR Allocation Table Registers */
270
271#define bfin_read_MXVR_ALLOC_0() bfin_read32(MXVR_ALLOC_0)
272#define bfin_write_MXVR_ALLOC_0(val) bfin_write32(MXVR_ALLOC_0, val)
273#define bfin_read_MXVR_ALLOC_1() bfin_read32(MXVR_ALLOC_1)
274#define bfin_write_MXVR_ALLOC_1(val) bfin_write32(MXVR_ALLOC_1, val)
275#define bfin_read_MXVR_ALLOC_2() bfin_read32(MXVR_ALLOC_2)
276#define bfin_write_MXVR_ALLOC_2(val) bfin_write32(MXVR_ALLOC_2, val)
277#define bfin_read_MXVR_ALLOC_3() bfin_read32(MXVR_ALLOC_3)
278#define bfin_write_MXVR_ALLOC_3(val) bfin_write32(MXVR_ALLOC_3, val)
279#define bfin_read_MXVR_ALLOC_4() bfin_read32(MXVR_ALLOC_4)
280#define bfin_write_MXVR_ALLOC_4(val) bfin_write32(MXVR_ALLOC_4, val)
281#define bfin_read_MXVR_ALLOC_5() bfin_read32(MXVR_ALLOC_5)
282#define bfin_write_MXVR_ALLOC_5(val) bfin_write32(MXVR_ALLOC_5, val)
283#define bfin_read_MXVR_ALLOC_6() bfin_read32(MXVR_ALLOC_6)
284#define bfin_write_MXVR_ALLOC_6(val) bfin_write32(MXVR_ALLOC_6, val)
285#define bfin_read_MXVR_ALLOC_7() bfin_read32(MXVR_ALLOC_7)
286#define bfin_write_MXVR_ALLOC_7(val) bfin_write32(MXVR_ALLOC_7, val)
287#define bfin_read_MXVR_ALLOC_8() bfin_read32(MXVR_ALLOC_8)
288#define bfin_write_MXVR_ALLOC_8(val) bfin_write32(MXVR_ALLOC_8, val)
289#define bfin_read_MXVR_ALLOC_9() bfin_read32(MXVR_ALLOC_9)
290#define bfin_write_MXVR_ALLOC_9(val) bfin_write32(MXVR_ALLOC_9, val)
291#define bfin_read_MXVR_ALLOC_10() bfin_read32(MXVR_ALLOC_10)
292#define bfin_write_MXVR_ALLOC_10(val) bfin_write32(MXVR_ALLOC_10, val)
293#define bfin_read_MXVR_ALLOC_11() bfin_read32(MXVR_ALLOC_11)
294#define bfin_write_MXVR_ALLOC_11(val) bfin_write32(MXVR_ALLOC_11, val)
295#define bfin_read_MXVR_ALLOC_12() bfin_read32(MXVR_ALLOC_12)
296#define bfin_write_MXVR_ALLOC_12(val) bfin_write32(MXVR_ALLOC_12, val)
297#define bfin_read_MXVR_ALLOC_13() bfin_read32(MXVR_ALLOC_13)
298#define bfin_write_MXVR_ALLOC_13(val) bfin_write32(MXVR_ALLOC_13, val)
299#define bfin_read_MXVR_ALLOC_14() bfin_read32(MXVR_ALLOC_14)
300#define bfin_write_MXVR_ALLOC_14(val) bfin_write32(MXVR_ALLOC_14, val)
301
302/* MXVR Channel Assign Registers */
303
304#define bfin_read_MXVR_SYNC_LCHAN_0() bfin_read32(MXVR_SYNC_LCHAN_0)
305#define bfin_write_MXVR_SYNC_LCHAN_0(val) bfin_write32(MXVR_SYNC_LCHAN_0, val)
306#define bfin_read_MXVR_SYNC_LCHAN_1() bfin_read32(MXVR_SYNC_LCHAN_1)
307#define bfin_write_MXVR_SYNC_LCHAN_1(val) bfin_write32(MXVR_SYNC_LCHAN_1, val)
308#define bfin_read_MXVR_SYNC_LCHAN_2() bfin_read32(MXVR_SYNC_LCHAN_2)
309#define bfin_write_MXVR_SYNC_LCHAN_2(val) bfin_write32(MXVR_SYNC_LCHAN_2, val)
310#define bfin_read_MXVR_SYNC_LCHAN_3() bfin_read32(MXVR_SYNC_LCHAN_3)
311#define bfin_write_MXVR_SYNC_LCHAN_3(val) bfin_write32(MXVR_SYNC_LCHAN_3, val)
312#define bfin_read_MXVR_SYNC_LCHAN_4() bfin_read32(MXVR_SYNC_LCHAN_4)
313#define bfin_write_MXVR_SYNC_LCHAN_4(val) bfin_write32(MXVR_SYNC_LCHAN_4, val)
314#define bfin_read_MXVR_SYNC_LCHAN_5() bfin_read32(MXVR_SYNC_LCHAN_5)
315#define bfin_write_MXVR_SYNC_LCHAN_5(val) bfin_write32(MXVR_SYNC_LCHAN_5, val)
316#define bfin_read_MXVR_SYNC_LCHAN_6() bfin_read32(MXVR_SYNC_LCHAN_6)
317#define bfin_write_MXVR_SYNC_LCHAN_6(val) bfin_write32(MXVR_SYNC_LCHAN_6, val)
318#define bfin_read_MXVR_SYNC_LCHAN_7() bfin_read32(MXVR_SYNC_LCHAN_7)
319#define bfin_write_MXVR_SYNC_LCHAN_7(val) bfin_write32(MXVR_SYNC_LCHAN_7, val)
320
321/* MXVR DMA0 Registers */
322
323#define bfin_read_MXVR_DMA0_CONFIG() bfin_read32(MXVR_DMA0_CONFIG)
324#define bfin_write_MXVR_DMA0_CONFIG(val) bfin_write32(MXVR_DMA0_CONFIG, val)
325#define bfin_read_MXVR_DMA0_START_ADDR() bfin_read32(MXVR_DMA0_START_ADDR)
326#define bfin_write_MXVR_DMA0_START_ADDR(val) bfin_write32(MXVR_DMA0_START_ADDR)
327#define bfin_read_MXVR_DMA0_COUNT() bfin_read16(MXVR_DMA0_COUNT)
328#define bfin_write_MXVR_DMA0_COUNT(val) bfin_write16(MXVR_DMA0_COUNT, val)
329#define bfin_read_MXVR_DMA0_CURR_ADDR() bfin_read32(MXVR_DMA0_CURR_ADDR)
330#define bfin_write_MXVR_DMA0_CURR_ADDR(val) bfin_write32(MXVR_DMA0_CURR_ADDR)
331#define bfin_read_MXVR_DMA0_CURR_COUNT() bfin_read16(MXVR_DMA0_CURR_COUNT)
332#define bfin_write_MXVR_DMA0_CURR_COUNT(val) bfin_write16(MXVR_DMA0_CURR_COUNT, val)
333
334/* MXVR DMA1 Registers */
335
336#define bfin_read_MXVR_DMA1_CONFIG() bfin_read32(MXVR_DMA1_CONFIG)
337#define bfin_write_MXVR_DMA1_CONFIG(val) bfin_write32(MXVR_DMA1_CONFIG, val)
338#define bfin_read_MXVR_DMA1_START_ADDR() bfin_read32(MXVR_DMA1_START_ADDR)
339#define bfin_write_MXVR_DMA1_START_ADDR(val) bfin_write32(MXVR_DMA1_START_ADDR)
340#define bfin_read_MXVR_DMA1_COUNT() bfin_read16(MXVR_DMA1_COUNT)
341#define bfin_write_MXVR_DMA1_COUNT(val) bfin_write16(MXVR_DMA1_COUNT, val)
342#define bfin_read_MXVR_DMA1_CURR_ADDR() bfin_read32(MXVR_DMA1_CURR_ADDR)
343#define bfin_write_MXVR_DMA1_CURR_ADDR(val) bfin_write32(MXVR_DMA1_CURR_ADDR)
344#define bfin_read_MXVR_DMA1_CURR_COUNT() bfin_read16(MXVR_DMA1_CURR_COUNT)
345#define bfin_write_MXVR_DMA1_CURR_COUNT(val) bfin_write16(MXVR_DMA1_CURR_COUNT, val)
346
347/* MXVR DMA2 Registers */
348
349#define bfin_read_MXVR_DMA2_CONFIG() bfin_read32(MXVR_DMA2_CONFIG)
350#define bfin_write_MXVR_DMA2_CONFIG(val) bfin_write32(MXVR_DMA2_CONFIG, val)
351#define bfin_read_MXVR_DMA2_START_ADDR() bfin_read32(MXVR_DMA2_START_ADDR)
352#define bfin_write_MXVR_DMA2_START_ADDR(val) bfin_write32(MXVR_DMA2_START_ADDR)
353#define bfin_read_MXVR_DMA2_COUNT() bfin_read16(MXVR_DMA2_COUNT)
354#define bfin_write_MXVR_DMA2_COUNT(val) bfin_write16(MXVR_DMA2_COUNT, val)
355#define bfin_read_MXVR_DMA2_CURR_ADDR() bfin_read32(MXVR_DMA2_CURR_ADDR)
356#define bfin_write_MXVR_DMA2_CURR_ADDR(val) bfin_write32(MXVR_DMA2_CURR_ADDR)
357#define bfin_read_MXVR_DMA2_CURR_COUNT() bfin_read16(MXVR_DMA2_CURR_COUNT)
358#define bfin_write_MXVR_DMA2_CURR_COUNT(val) bfin_write16(MXVR_DMA2_CURR_COUNT, val)
359
360/* MXVR DMA3 Registers */
361
362#define bfin_read_MXVR_DMA3_CONFIG() bfin_read32(MXVR_DMA3_CONFIG)
363#define bfin_write_MXVR_DMA3_CONFIG(val) bfin_write32(MXVR_DMA3_CONFIG, val)
364#define bfin_read_MXVR_DMA3_START_ADDR() bfin_read32(MXVR_DMA3_START_ADDR)
365#define bfin_write_MXVR_DMA3_START_ADDR(val) bfin_write32(MXVR_DMA3_START_ADDR)
366#define bfin_read_MXVR_DMA3_COUNT() bfin_read16(MXVR_DMA3_COUNT)
367#define bfin_write_MXVR_DMA3_COUNT(val) bfin_write16(MXVR_DMA3_COUNT, val)
368#define bfin_read_MXVR_DMA3_CURR_ADDR() bfin_read32(MXVR_DMA3_CURR_ADDR)
369#define bfin_write_MXVR_DMA3_CURR_ADDR(val) bfin_write32(MXVR_DMA3_CURR_ADDR)
370#define bfin_read_MXVR_DMA3_CURR_COUNT() bfin_read16(MXVR_DMA3_CURR_COUNT)
371#define bfin_write_MXVR_DMA3_CURR_COUNT(val) bfin_write16(MXVR_DMA3_CURR_COUNT, val)
372
373/* MXVR DMA4 Registers */
374
375#define bfin_read_MXVR_DMA4_CONFIG() bfin_read32(MXVR_DMA4_CONFIG)
376#define bfin_write_MXVR_DMA4_CONFIG(val) bfin_write32(MXVR_DMA4_CONFIG, val)
377#define bfin_read_MXVR_DMA4_START_ADDR() bfin_read32(MXVR_DMA4_START_ADDR)
378#define bfin_write_MXVR_DMA4_START_ADDR(val) bfin_write32(MXVR_DMA4_START_ADDR)
379#define bfin_read_MXVR_DMA4_COUNT() bfin_read16(MXVR_DMA4_COUNT)
380#define bfin_write_MXVR_DMA4_COUNT(val) bfin_write16(MXVR_DMA4_COUNT, val)
381#define bfin_read_MXVR_DMA4_CURR_ADDR() bfin_read32(MXVR_DMA4_CURR_ADDR)
382#define bfin_write_MXVR_DMA4_CURR_ADDR(val) bfin_write32(MXVR_DMA4_CURR_ADDR)
383#define bfin_read_MXVR_DMA4_CURR_COUNT() bfin_read16(MXVR_DMA4_CURR_COUNT)
384#define bfin_write_MXVR_DMA4_CURR_COUNT(val) bfin_write16(MXVR_DMA4_CURR_COUNT, val)
385
386/* MXVR DMA5 Registers */
387
388#define bfin_read_MXVR_DMA5_CONFIG() bfin_read32(MXVR_DMA5_CONFIG)
389#define bfin_write_MXVR_DMA5_CONFIG(val) bfin_write32(MXVR_DMA5_CONFIG, val)
390#define bfin_read_MXVR_DMA5_START_ADDR() bfin_read32(MXVR_DMA5_START_ADDR)
391#define bfin_write_MXVR_DMA5_START_ADDR(val) bfin_write32(MXVR_DMA5_START_ADDR)
392#define bfin_read_MXVR_DMA5_COUNT() bfin_read16(MXVR_DMA5_COUNT)
393#define bfin_write_MXVR_DMA5_COUNT(val) bfin_write16(MXVR_DMA5_COUNT, val)
394#define bfin_read_MXVR_DMA5_CURR_ADDR() bfin_read32(MXVR_DMA5_CURR_ADDR)
395#define bfin_write_MXVR_DMA5_CURR_ADDR(val) bfin_write32(MXVR_DMA5_CURR_ADDR)
396#define bfin_read_MXVR_DMA5_CURR_COUNT() bfin_read16(MXVR_DMA5_CURR_COUNT)
397#define bfin_write_MXVR_DMA5_CURR_COUNT(val) bfin_write16(MXVR_DMA5_CURR_COUNT, val)
398
399/* MXVR DMA6 Registers */
400
401#define bfin_read_MXVR_DMA6_CONFIG() bfin_read32(MXVR_DMA6_CONFIG)
402#define bfin_write_MXVR_DMA6_CONFIG(val) bfin_write32(MXVR_DMA6_CONFIG, val)
403#define bfin_read_MXVR_DMA6_START_ADDR() bfin_read32(MXVR_DMA6_START_ADDR)
404#define bfin_write_MXVR_DMA6_START_ADDR(val) bfin_write32(MXVR_DMA6_START_ADDR)
405#define bfin_read_MXVR_DMA6_COUNT() bfin_read16(MXVR_DMA6_COUNT)
406#define bfin_write_MXVR_DMA6_COUNT(val) bfin_write16(MXVR_DMA6_COUNT, val)
407#define bfin_read_MXVR_DMA6_CURR_ADDR() bfin_read32(MXVR_DMA6_CURR_ADDR)
408#define bfin_write_MXVR_DMA6_CURR_ADDR(val) bfin_write32(MXVR_DMA6_CURR_ADDR)
409#define bfin_read_MXVR_DMA6_CURR_COUNT() bfin_read16(MXVR_DMA6_CURR_COUNT)
410#define bfin_write_MXVR_DMA6_CURR_COUNT(val) bfin_write16(MXVR_DMA6_CURR_COUNT, val)
411
412/* MXVR DMA7 Registers */
413
414#define bfin_read_MXVR_DMA7_CONFIG() bfin_read32(MXVR_DMA7_CONFIG)
415#define bfin_write_MXVR_DMA7_CONFIG(val) bfin_write32(MXVR_DMA7_CONFIG, val)
416#define bfin_read_MXVR_DMA7_START_ADDR() bfin_read32(MXVR_DMA7_START_ADDR)
417#define bfin_write_MXVR_DMA7_START_ADDR(val) bfin_write32(MXVR_DMA7_START_ADDR)
418#define bfin_read_MXVR_DMA7_COUNT() bfin_read16(MXVR_DMA7_COUNT)
419#define bfin_write_MXVR_DMA7_COUNT(val) bfin_write16(MXVR_DMA7_COUNT, val)
420#define bfin_read_MXVR_DMA7_CURR_ADDR() bfin_read32(MXVR_DMA7_CURR_ADDR)
421#define bfin_write_MXVR_DMA7_CURR_ADDR(val) bfin_write32(MXVR_DMA7_CURR_ADDR)
422#define bfin_read_MXVR_DMA7_CURR_COUNT() bfin_read16(MXVR_DMA7_CURR_COUNT)
423#define bfin_write_MXVR_DMA7_CURR_COUNT(val) bfin_write16(MXVR_DMA7_CURR_COUNT, val)
424
425/* MXVR Asynch Packet Registers */
426
427#define bfin_read_MXVR_AP_CTL() bfin_read16(MXVR_AP_CTL)
428#define bfin_write_MXVR_AP_CTL(val) bfin_write16(MXVR_AP_CTL, val)
429#define bfin_read_MXVR_APRB_START_ADDR() bfin_read32(MXVR_APRB_START_ADDR)
430#define bfin_write_MXVR_APRB_START_ADDR(val) bfin_write32(MXVR_APRB_START_ADDR)
431#define bfin_read_MXVR_APRB_CURR_ADDR() bfin_read32(MXVR_APRB_CURR_ADDR)
432#define bfin_write_MXVR_APRB_CURR_ADDR(val) bfin_write32(MXVR_APRB_CURR_ADDR)
433#define bfin_read_MXVR_APTB_START_ADDR() bfin_read32(MXVR_APTB_START_ADDR)
434#define bfin_write_MXVR_APTB_START_ADDR(val) bfin_write32(MXVR_APTB_START_ADDR)
435#define bfin_read_MXVR_APTB_CURR_ADDR() bfin_read32(MXVR_APTB_CURR_ADDR)
436#define bfin_write_MXVR_APTB_CURR_ADDR(val) bfin_write32(MXVR_APTB_CURR_ADDR)
437
438/* MXVR Control Message Registers */
439
440#define bfin_read_MXVR_CM_CTL() bfin_read32(MXVR_CM_CTL)
441#define bfin_write_MXVR_CM_CTL(val) bfin_write32(MXVR_CM_CTL, val)
442#define bfin_read_MXVR_CMRB_START_ADDR() bfin_read32(MXVR_CMRB_START_ADDR)
443#define bfin_write_MXVR_CMRB_START_ADDR(val) bfin_write32(MXVR_CMRB_START_ADDR)
444#define bfin_read_MXVR_CMRB_CURR_ADDR() bfin_read32(MXVR_CMRB_CURR_ADDR)
445#define bfin_write_MXVR_CMRB_CURR_ADDR(val) bfin_write32(MXVR_CMRB_CURR_ADDR)
446#define bfin_read_MXVR_CMTB_START_ADDR() bfin_read32(MXVR_CMTB_START_ADDR)
447#define bfin_write_MXVR_CMTB_START_ADDR(val) bfin_write32(MXVR_CMTB_START_ADDR)
448#define bfin_read_MXVR_CMTB_CURR_ADDR() bfin_read32(MXVR_CMTB_CURR_ADDR)
449#define bfin_write_MXVR_CMTB_CURR_ADDR(val) bfin_write32(MXVR_CMTB_CURR_ADDR)
450
451/* MXVR Remote Read Registers */
452
453#define bfin_read_MXVR_RRDB_START_ADDR() bfin_read32(MXVR_RRDB_START_ADDR)
454#define bfin_write_MXVR_RRDB_START_ADDR(val) bfin_write32(MXVR_RRDB_START_ADDR)
455#define bfin_read_MXVR_RRDB_CURR_ADDR() bfin_read32(MXVR_RRDB_CURR_ADDR)
456#define bfin_write_MXVR_RRDB_CURR_ADDR(val) bfin_write32(MXVR_RRDB_CURR_ADDR)
457
458/* MXVR Pattern Data Registers */
459
460#define bfin_read_MXVR_PAT_DATA_0() bfin_read32(MXVR_PAT_DATA_0)
461#define bfin_write_MXVR_PAT_DATA_0(val) bfin_write32(MXVR_PAT_DATA_0, val)
462#define bfin_read_MXVR_PAT_EN_0() bfin_read32(MXVR_PAT_EN_0)
463#define bfin_write_MXVR_PAT_EN_0(val) bfin_write32(MXVR_PAT_EN_0, val)
464#define bfin_read_MXVR_PAT_DATA_1() bfin_read32(MXVR_PAT_DATA_1)
465#define bfin_write_MXVR_PAT_DATA_1(val) bfin_write32(MXVR_PAT_DATA_1, val)
466#define bfin_read_MXVR_PAT_EN_1() bfin_read32(MXVR_PAT_EN_1)
467#define bfin_write_MXVR_PAT_EN_1(val) bfin_write32(MXVR_PAT_EN_1, val)
468
469/* MXVR Frame Counter Registers */
470
471#define bfin_read_MXVR_FRAME_CNT_0() bfin_read16(MXVR_FRAME_CNT_0)
472#define bfin_write_MXVR_FRAME_CNT_0(val) bfin_write16(MXVR_FRAME_CNT_0, val)
473#define bfin_read_MXVR_FRAME_CNT_1() bfin_read16(MXVR_FRAME_CNT_1)
474#define bfin_write_MXVR_FRAME_CNT_1(val) bfin_write16(MXVR_FRAME_CNT_1, val)
475
476/* MXVR Routing Table Registers */
477
478#define bfin_read_MXVR_ROUTING_0() bfin_read32(MXVR_ROUTING_0)
479#define bfin_write_MXVR_ROUTING_0(val) bfin_write32(MXVR_ROUTING_0, val)
480#define bfin_read_MXVR_ROUTING_1() bfin_read32(MXVR_ROUTING_1)
481#define bfin_write_MXVR_ROUTING_1(val) bfin_write32(MXVR_ROUTING_1, val)
482#define bfin_read_MXVR_ROUTING_2() bfin_read32(MXVR_ROUTING_2)
483#define bfin_write_MXVR_ROUTING_2(val) bfin_write32(MXVR_ROUTING_2, val)
484#define bfin_read_MXVR_ROUTING_3() bfin_read32(MXVR_ROUTING_3)
485#define bfin_write_MXVR_ROUTING_3(val) bfin_write32(MXVR_ROUTING_3, val)
486#define bfin_read_MXVR_ROUTING_4() bfin_read32(MXVR_ROUTING_4)
487#define bfin_write_MXVR_ROUTING_4(val) bfin_write32(MXVR_ROUTING_4, val)
488#define bfin_read_MXVR_ROUTING_5() bfin_read32(MXVR_ROUTING_5)
489#define bfin_write_MXVR_ROUTING_5(val) bfin_write32(MXVR_ROUTING_5, val)
490#define bfin_read_MXVR_ROUTING_6() bfin_read32(MXVR_ROUTING_6)
491#define bfin_write_MXVR_ROUTING_6(val) bfin_write32(MXVR_ROUTING_6, val)
492#define bfin_read_MXVR_ROUTING_7() bfin_read32(MXVR_ROUTING_7)
493#define bfin_write_MXVR_ROUTING_7(val) bfin_write32(MXVR_ROUTING_7, val)
494#define bfin_read_MXVR_ROUTING_8() bfin_read32(MXVR_ROUTING_8)
495#define bfin_write_MXVR_ROUTING_8(val) bfin_write32(MXVR_ROUTING_8, val)
496#define bfin_read_MXVR_ROUTING_9() bfin_read32(MXVR_ROUTING_9)
497#define bfin_write_MXVR_ROUTING_9(val) bfin_write32(MXVR_ROUTING_9, val)
498#define bfin_read_MXVR_ROUTING_10() bfin_read32(MXVR_ROUTING_10)
499#define bfin_write_MXVR_ROUTING_10(val) bfin_write32(MXVR_ROUTING_10, val)
500#define bfin_read_MXVR_ROUTING_11() bfin_read32(MXVR_ROUTING_11)
501#define bfin_write_MXVR_ROUTING_11(val) bfin_write32(MXVR_ROUTING_11, val)
502#define bfin_read_MXVR_ROUTING_12() bfin_read32(MXVR_ROUTING_12)
503#define bfin_write_MXVR_ROUTING_12(val) bfin_write32(MXVR_ROUTING_12, val)
504#define bfin_read_MXVR_ROUTING_13() bfin_read32(MXVR_ROUTING_13)
505#define bfin_write_MXVR_ROUTING_13(val) bfin_write32(MXVR_ROUTING_13, val)
506#define bfin_read_MXVR_ROUTING_14() bfin_read32(MXVR_ROUTING_14)
507#define bfin_write_MXVR_ROUTING_14(val) bfin_write32(MXVR_ROUTING_14, val)
508
509/* MXVR Counter-Clock-Control Registers */
510
511#define bfin_read_MXVR_BLOCK_CNT() bfin_read16(MXVR_BLOCK_CNT)
512#define bfin_write_MXVR_BLOCK_CNT(val) bfin_write16(MXVR_BLOCK_CNT, val)
513#define bfin_read_MXVR_CLK_CTL() bfin_read32(MXVR_CLK_CTL)
514#define bfin_write_MXVR_CLK_CTL(val) bfin_write32(MXVR_CLK_CTL, val)
515#define bfin_read_MXVR_CDRPLL_CTL() bfin_read32(MXVR_CDRPLL_CTL)
516#define bfin_write_MXVR_CDRPLL_CTL(val) bfin_write32(MXVR_CDRPLL_CTL, val)
517#define bfin_read_MXVR_FMPLL_CTL() bfin_read32(MXVR_FMPLL_CTL)
518#define bfin_write_MXVR_FMPLL_CTL(val) bfin_write32(MXVR_FMPLL_CTL, val)
519#define bfin_read_MXVR_PIN_CTL() bfin_read16(MXVR_PIN_CTL)
520#define bfin_write_MXVR_PIN_CTL(val) bfin_write16(MXVR_PIN_CTL, val)
521#define bfin_read_MXVR_SCLK_CNT() bfin_read16(MXVR_SCLK_CNT)
522#define bfin_write_MXVR_SCLK_CNT(val) bfin_write16(MXVR_SCLK_CNT, val)
523
524/* CAN Controller 1 Config 1 Registers */
525
526#define bfin_read_CAN1_MC1() bfin_read16(CAN1_MC1)
527#define bfin_write_CAN1_MC1(val) bfin_write16(CAN1_MC1, val)
528#define bfin_read_CAN1_MD1() bfin_read16(CAN1_MD1)
529#define bfin_write_CAN1_MD1(val) bfin_write16(CAN1_MD1, val)
530#define bfin_read_CAN1_TRS1() bfin_read16(CAN1_TRS1)
531#define bfin_write_CAN1_TRS1(val) bfin_write16(CAN1_TRS1, val)
532#define bfin_read_CAN1_TRR1() bfin_read16(CAN1_TRR1)
533#define bfin_write_CAN1_TRR1(val) bfin_write16(CAN1_TRR1, val)
534#define bfin_read_CAN1_TA1() bfin_read16(CAN1_TA1)
535#define bfin_write_CAN1_TA1(val) bfin_write16(CAN1_TA1, val)
536#define bfin_read_CAN1_AA1() bfin_read16(CAN1_AA1)
537#define bfin_write_CAN1_AA1(val) bfin_write16(CAN1_AA1, val)
538#define bfin_read_CAN1_RMP1() bfin_read16(CAN1_RMP1)
539#define bfin_write_CAN1_RMP1(val) bfin_write16(CAN1_RMP1, val)
540#define bfin_read_CAN1_RML1() bfin_read16(CAN1_RML1)
541#define bfin_write_CAN1_RML1(val) bfin_write16(CAN1_RML1, val)
542#define bfin_read_CAN1_MBTIF1() bfin_read16(CAN1_MBTIF1)
543#define bfin_write_CAN1_MBTIF1(val) bfin_write16(CAN1_MBTIF1, val)
544#define bfin_read_CAN1_MBRIF1() bfin_read16(CAN1_MBRIF1)
545#define bfin_write_CAN1_MBRIF1(val) bfin_write16(CAN1_MBRIF1, val)
546#define bfin_read_CAN1_MBIM1() bfin_read16(CAN1_MBIM1)
547#define bfin_write_CAN1_MBIM1(val) bfin_write16(CAN1_MBIM1, val)
548#define bfin_read_CAN1_RFH1() bfin_read16(CAN1_RFH1)
549#define bfin_write_CAN1_RFH1(val) bfin_write16(CAN1_RFH1, val)
550#define bfin_read_CAN1_OPSS1() bfin_read16(CAN1_OPSS1)
551#define bfin_write_CAN1_OPSS1(val) bfin_write16(CAN1_OPSS1, val)
552
553/* CAN Controller 1 Config 2 Registers */
554
555#define bfin_read_CAN1_MC2() bfin_read16(CAN1_MC2)
556#define bfin_write_CAN1_MC2(val) bfin_write16(CAN1_MC2, val)
557#define bfin_read_CAN1_MD2() bfin_read16(CAN1_MD2)
558#define bfin_write_CAN1_MD2(val) bfin_write16(CAN1_MD2, val)
559#define bfin_read_CAN1_TRS2() bfin_read16(CAN1_TRS2)
560#define bfin_write_CAN1_TRS2(val) bfin_write16(CAN1_TRS2, val)
561#define bfin_read_CAN1_TRR2() bfin_read16(CAN1_TRR2)
562#define bfin_write_CAN1_TRR2(val) bfin_write16(CAN1_TRR2, val)
563#define bfin_read_CAN1_TA2() bfin_read16(CAN1_TA2)
564#define bfin_write_CAN1_TA2(val) bfin_write16(CAN1_TA2, val)
565#define bfin_read_CAN1_AA2() bfin_read16(CAN1_AA2)
566#define bfin_write_CAN1_AA2(val) bfin_write16(CAN1_AA2, val)
567#define bfin_read_CAN1_RMP2() bfin_read16(CAN1_RMP2)
568#define bfin_write_CAN1_RMP2(val) bfin_write16(CAN1_RMP2, val)
569#define bfin_read_CAN1_RML2() bfin_read16(CAN1_RML2)
570#define bfin_write_CAN1_RML2(val) bfin_write16(CAN1_RML2, val)
571#define bfin_read_CAN1_MBTIF2() bfin_read16(CAN1_MBTIF2)
572#define bfin_write_CAN1_MBTIF2(val) bfin_write16(CAN1_MBTIF2, val)
573#define bfin_read_CAN1_MBRIF2() bfin_read16(CAN1_MBRIF2)
574#define bfin_write_CAN1_MBRIF2(val) bfin_write16(CAN1_MBRIF2, val)
575#define bfin_read_CAN1_MBIM2() bfin_read16(CAN1_MBIM2)
576#define bfin_write_CAN1_MBIM2(val) bfin_write16(CAN1_MBIM2, val)
577#define bfin_read_CAN1_RFH2() bfin_read16(CAN1_RFH2)
578#define bfin_write_CAN1_RFH2(val) bfin_write16(CAN1_RFH2, val)
579#define bfin_read_CAN1_OPSS2() bfin_read16(CAN1_OPSS2)
580#define bfin_write_CAN1_OPSS2(val) bfin_write16(CAN1_OPSS2, val)
581
582/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
583
584#define bfin_read_CAN1_CLOCK() bfin_read16(CAN1_CLOCK)
585#define bfin_write_CAN1_CLOCK(val) bfin_write16(CAN1_CLOCK, val)
586#define bfin_read_CAN1_TIMING() bfin_read16(CAN1_TIMING)
587#define bfin_write_CAN1_TIMING(val) bfin_write16(CAN1_TIMING, val)
588#define bfin_read_CAN1_DEBUG() bfin_read16(CAN1_DEBUG)
589#define bfin_write_CAN1_DEBUG(val) bfin_write16(CAN1_DEBUG, val)
590#define bfin_read_CAN1_STATUS() bfin_read16(CAN1_STATUS)
591#define bfin_write_CAN1_STATUS(val) bfin_write16(CAN1_STATUS, val)
592#define bfin_read_CAN1_CEC() bfin_read16(CAN1_CEC)
593#define bfin_write_CAN1_CEC(val) bfin_write16(CAN1_CEC, val)
594#define bfin_read_CAN1_GIS() bfin_read16(CAN1_GIS)
595#define bfin_write_CAN1_GIS(val) bfin_write16(CAN1_GIS, val)
596#define bfin_read_CAN1_GIM() bfin_read16(CAN1_GIM)
597#define bfin_write_CAN1_GIM(val) bfin_write16(CAN1_GIM, val)
598#define bfin_read_CAN1_GIF() bfin_read16(CAN1_GIF)
599#define bfin_write_CAN1_GIF(val) bfin_write16(CAN1_GIF, val)
600#define bfin_read_CAN1_CONTROL() bfin_read16(CAN1_CONTROL)
601#define bfin_write_CAN1_CONTROL(val) bfin_write16(CAN1_CONTROL, val)
602#define bfin_read_CAN1_INTR() bfin_read16(CAN1_INTR)
603#define bfin_write_CAN1_INTR(val) bfin_write16(CAN1_INTR, val)
604#define bfin_read_CAN1_MBTD() bfin_read16(CAN1_MBTD)
605#define bfin_write_CAN1_MBTD(val) bfin_write16(CAN1_MBTD, val)
606#define bfin_read_CAN1_EWR() bfin_read16(CAN1_EWR)
607#define bfin_write_CAN1_EWR(val) bfin_write16(CAN1_EWR, val)
608#define bfin_read_CAN1_ESR() bfin_read16(CAN1_ESR)
609#define bfin_write_CAN1_ESR(val) bfin_write16(CAN1_ESR, val)
610#define bfin_read_CAN1_UCCNT() bfin_read16(CAN1_UCCNT)
611#define bfin_write_CAN1_UCCNT(val) bfin_write16(CAN1_UCCNT, val)
612#define bfin_read_CAN1_UCRC() bfin_read16(CAN1_UCRC)
613#define bfin_write_CAN1_UCRC(val) bfin_write16(CAN1_UCRC, val)
614#define bfin_read_CAN1_UCCNF() bfin_read16(CAN1_UCCNF)
615#define bfin_write_CAN1_UCCNF(val) bfin_write16(CAN1_UCCNF, val)
616
617/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
618
619#define bfin_read_CAN1_AM00L() bfin_read16(CAN1_AM00L)
620#define bfin_write_CAN1_AM00L(val) bfin_write16(CAN1_AM00L, val)
621#define bfin_read_CAN1_AM00H() bfin_read16(CAN1_AM00H)
622#define bfin_write_CAN1_AM00H(val) bfin_write16(CAN1_AM00H, val)
623#define bfin_read_CAN1_AM01L() bfin_read16(CAN1_AM01L)
624#define bfin_write_CAN1_AM01L(val) bfin_write16(CAN1_AM01L, val)
625#define bfin_read_CAN1_AM01H() bfin_read16(CAN1_AM01H)
626#define bfin_write_CAN1_AM01H(val) bfin_write16(CAN1_AM01H, val)
627#define bfin_read_CAN1_AM02L() bfin_read16(CAN1_AM02L)
628#define bfin_write_CAN1_AM02L(val) bfin_write16(CAN1_AM02L, val)
629#define bfin_read_CAN1_AM02H() bfin_read16(CAN1_AM02H)
630#define bfin_write_CAN1_AM02H(val) bfin_write16(CAN1_AM02H, val)
631#define bfin_read_CAN1_AM03L() bfin_read16(CAN1_AM03L)
632#define bfin_write_CAN1_AM03L(val) bfin_write16(CAN1_AM03L, val)
633#define bfin_read_CAN1_AM03H() bfin_read16(CAN1_AM03H)
634#define bfin_write_CAN1_AM03H(val) bfin_write16(CAN1_AM03H, val)
635#define bfin_read_CAN1_AM04L() bfin_read16(CAN1_AM04L)
636#define bfin_write_CAN1_AM04L(val) bfin_write16(CAN1_AM04L, val)
637#define bfin_read_CAN1_AM04H() bfin_read16(CAN1_AM04H)
638#define bfin_write_CAN1_AM04H(val) bfin_write16(CAN1_AM04H, val)
639#define bfin_read_CAN1_AM05L() bfin_read16(CAN1_AM05L)
640#define bfin_write_CAN1_AM05L(val) bfin_write16(CAN1_AM05L, val)
641#define bfin_read_CAN1_AM05H() bfin_read16(CAN1_AM05H)
642#define bfin_write_CAN1_AM05H(val) bfin_write16(CAN1_AM05H, val)
643#define bfin_read_CAN1_AM06L() bfin_read16(CAN1_AM06L)
644#define bfin_write_CAN1_AM06L(val) bfin_write16(CAN1_AM06L, val)
645#define bfin_read_CAN1_AM06H() bfin_read16(CAN1_AM06H)
646#define bfin_write_CAN1_AM06H(val) bfin_write16(CAN1_AM06H, val)
647#define bfin_read_CAN1_AM07L() bfin_read16(CAN1_AM07L)
648#define bfin_write_CAN1_AM07L(val) bfin_write16(CAN1_AM07L, val)
649#define bfin_read_CAN1_AM07H() bfin_read16(CAN1_AM07H)
650#define bfin_write_CAN1_AM07H(val) bfin_write16(CAN1_AM07H, val)
651#define bfin_read_CAN1_AM08L() bfin_read16(CAN1_AM08L)
652#define bfin_write_CAN1_AM08L(val) bfin_write16(CAN1_AM08L, val)
653#define bfin_read_CAN1_AM08H() bfin_read16(CAN1_AM08H)
654#define bfin_write_CAN1_AM08H(val) bfin_write16(CAN1_AM08H, val)
655#define bfin_read_CAN1_AM09L() bfin_read16(CAN1_AM09L)
656#define bfin_write_CAN1_AM09L(val) bfin_write16(CAN1_AM09L, val)
657#define bfin_read_CAN1_AM09H() bfin_read16(CAN1_AM09H)
658#define bfin_write_CAN1_AM09H(val) bfin_write16(CAN1_AM09H, val)
659#define bfin_read_CAN1_AM10L() bfin_read16(CAN1_AM10L)
660#define bfin_write_CAN1_AM10L(val) bfin_write16(CAN1_AM10L, val)
661#define bfin_read_CAN1_AM10H() bfin_read16(CAN1_AM10H)
662#define bfin_write_CAN1_AM10H(val) bfin_write16(CAN1_AM10H, val)
663#define bfin_read_CAN1_AM11L() bfin_read16(CAN1_AM11L)
664#define bfin_write_CAN1_AM11L(val) bfin_write16(CAN1_AM11L, val)
665#define bfin_read_CAN1_AM11H() bfin_read16(CAN1_AM11H)
666#define bfin_write_CAN1_AM11H(val) bfin_write16(CAN1_AM11H, val)
667#define bfin_read_CAN1_AM12L() bfin_read16(CAN1_AM12L)
668#define bfin_write_CAN1_AM12L(val) bfin_write16(CAN1_AM12L, val)
669#define bfin_read_CAN1_AM12H() bfin_read16(CAN1_AM12H)
670#define bfin_write_CAN1_AM12H(val) bfin_write16(CAN1_AM12H, val)
671#define bfin_read_CAN1_AM13L() bfin_read16(CAN1_AM13L)
672#define bfin_write_CAN1_AM13L(val) bfin_write16(CAN1_AM13L, val)
673#define bfin_read_CAN1_AM13H() bfin_read16(CAN1_AM13H)
674#define bfin_write_CAN1_AM13H(val) bfin_write16(CAN1_AM13H, val)
675#define bfin_read_CAN1_AM14L() bfin_read16(CAN1_AM14L)
676#define bfin_write_CAN1_AM14L(val) bfin_write16(CAN1_AM14L, val)
677#define bfin_read_CAN1_AM14H() bfin_read16(CAN1_AM14H)
678#define bfin_write_CAN1_AM14H(val) bfin_write16(CAN1_AM14H, val)
679#define bfin_read_CAN1_AM15L() bfin_read16(CAN1_AM15L)
680#define bfin_write_CAN1_AM15L(val) bfin_write16(CAN1_AM15L, val)
681#define bfin_read_CAN1_AM15H() bfin_read16(CAN1_AM15H)
682#define bfin_write_CAN1_AM15H(val) bfin_write16(CAN1_AM15H, val)
683
684/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
685
686#define bfin_read_CAN1_AM16L() bfin_read16(CAN1_AM16L)
687#define bfin_write_CAN1_AM16L(val) bfin_write16(CAN1_AM16L, val)
688#define bfin_read_CAN1_AM16H() bfin_read16(CAN1_AM16H)
689#define bfin_write_CAN1_AM16H(val) bfin_write16(CAN1_AM16H, val)
690#define bfin_read_CAN1_AM17L() bfin_read16(CAN1_AM17L)
691#define bfin_write_CAN1_AM17L(val) bfin_write16(CAN1_AM17L, val)
692#define bfin_read_CAN1_AM17H() bfin_read16(CAN1_AM17H)
693#define bfin_write_CAN1_AM17H(val) bfin_write16(CAN1_AM17H, val)
694#define bfin_read_CAN1_AM18L() bfin_read16(CAN1_AM18L)
695#define bfin_write_CAN1_AM18L(val) bfin_write16(CAN1_AM18L, val)
696#define bfin_read_CAN1_AM18H() bfin_read16(CAN1_AM18H)
697#define bfin_write_CAN1_AM18H(val) bfin_write16(CAN1_AM18H, val)
698#define bfin_read_CAN1_AM19L() bfin_read16(CAN1_AM19L)
699#define bfin_write_CAN1_AM19L(val) bfin_write16(CAN1_AM19L, val)
700#define bfin_read_CAN1_AM19H() bfin_read16(CAN1_AM19H)
701#define bfin_write_CAN1_AM19H(val) bfin_write16(CAN1_AM19H, val)
702#define bfin_read_CAN1_AM20L() bfin_read16(CAN1_AM20L)
703#define bfin_write_CAN1_AM20L(val) bfin_write16(CAN1_AM20L, val)
704#define bfin_read_CAN1_AM20H() bfin_read16(CAN1_AM20H)
705#define bfin_write_CAN1_AM20H(val) bfin_write16(CAN1_AM20H, val)
706#define bfin_read_CAN1_AM21L() bfin_read16(CAN1_AM21L)
707#define bfin_write_CAN1_AM21L(val) bfin_write16(CAN1_AM21L, val)
708#define bfin_read_CAN1_AM21H() bfin_read16(CAN1_AM21H)
709#define bfin_write_CAN1_AM21H(val) bfin_write16(CAN1_AM21H, val)
710#define bfin_read_CAN1_AM22L() bfin_read16(CAN1_AM22L)
711#define bfin_write_CAN1_AM22L(val) bfin_write16(CAN1_AM22L, val)
712#define bfin_read_CAN1_AM22H() bfin_read16(CAN1_AM22H)
713#define bfin_write_CAN1_AM22H(val) bfin_write16(CAN1_AM22H, val)
714#define bfin_read_CAN1_AM23L() bfin_read16(CAN1_AM23L)
715#define bfin_write_CAN1_AM23L(val) bfin_write16(CAN1_AM23L, val)
716#define bfin_read_CAN1_AM23H() bfin_read16(CAN1_AM23H)
717#define bfin_write_CAN1_AM23H(val) bfin_write16(CAN1_AM23H, val)
718#define bfin_read_CAN1_AM24L() bfin_read16(CAN1_AM24L)
719#define bfin_write_CAN1_AM24L(val) bfin_write16(CAN1_AM24L, val)
720#define bfin_read_CAN1_AM24H() bfin_read16(CAN1_AM24H)
721#define bfin_write_CAN1_AM24H(val) bfin_write16(CAN1_AM24H, val)
722#define bfin_read_CAN1_AM25L() bfin_read16(CAN1_AM25L)
723#define bfin_write_CAN1_AM25L(val) bfin_write16(CAN1_AM25L, val)
724#define bfin_read_CAN1_AM25H() bfin_read16(CAN1_AM25H)
725#define bfin_write_CAN1_AM25H(val) bfin_write16(CAN1_AM25H, val)
726#define bfin_read_CAN1_AM26L() bfin_read16(CAN1_AM26L)
727#define bfin_write_CAN1_AM26L(val) bfin_write16(CAN1_AM26L, val)
728#define bfin_read_CAN1_AM26H() bfin_read16(CAN1_AM26H)
729#define bfin_write_CAN1_AM26H(val) bfin_write16(CAN1_AM26H, val)
730#define bfin_read_CAN1_AM27L() bfin_read16(CAN1_AM27L)
731#define bfin_write_CAN1_AM27L(val) bfin_write16(CAN1_AM27L, val)
732#define bfin_read_CAN1_AM27H() bfin_read16(CAN1_AM27H)
733#define bfin_write_CAN1_AM27H(val) bfin_write16(CAN1_AM27H, val)
734#define bfin_read_CAN1_AM28L() bfin_read16(CAN1_AM28L)
735#define bfin_write_CAN1_AM28L(val) bfin_write16(CAN1_AM28L, val)
736#define bfin_read_CAN1_AM28H() bfin_read16(CAN1_AM28H)
737#define bfin_write_CAN1_AM28H(val) bfin_write16(CAN1_AM28H, val)
738#define bfin_read_CAN1_AM29L() bfin_read16(CAN1_AM29L)
739#define bfin_write_CAN1_AM29L(val) bfin_write16(CAN1_AM29L, val)
740#define bfin_read_CAN1_AM29H() bfin_read16(CAN1_AM29H)
741#define bfin_write_CAN1_AM29H(val) bfin_write16(CAN1_AM29H, val)
742#define bfin_read_CAN1_AM30L() bfin_read16(CAN1_AM30L)
743#define bfin_write_CAN1_AM30L(val) bfin_write16(CAN1_AM30L, val)
744#define bfin_read_CAN1_AM30H() bfin_read16(CAN1_AM30H)
745#define bfin_write_CAN1_AM30H(val) bfin_write16(CAN1_AM30H, val)
746#define bfin_read_CAN1_AM31L() bfin_read16(CAN1_AM31L)
747#define bfin_write_CAN1_AM31L(val) bfin_write16(CAN1_AM31L, val)
748#define bfin_read_CAN1_AM31H() bfin_read16(CAN1_AM31H)
749#define bfin_write_CAN1_AM31H(val) bfin_write16(CAN1_AM31H, val)
750
751/* CAN Controller 1 Mailbox Data Registers */
752
753#define bfin_read_CAN1_MB00_DATA0() bfin_read16(CAN1_MB00_DATA0)
754#define bfin_write_CAN1_MB00_DATA0(val) bfin_write16(CAN1_MB00_DATA0, val)
755#define bfin_read_CAN1_MB00_DATA1() bfin_read16(CAN1_MB00_DATA1)
756#define bfin_write_CAN1_MB00_DATA1(val) bfin_write16(CAN1_MB00_DATA1, val)
757#define bfin_read_CAN1_MB00_DATA2() bfin_read16(CAN1_MB00_DATA2)
758#define bfin_write_CAN1_MB00_DATA2(val) bfin_write16(CAN1_MB00_DATA2, val)
759#define bfin_read_CAN1_MB00_DATA3() bfin_read16(CAN1_MB00_DATA3)
760#define bfin_write_CAN1_MB00_DATA3(val) bfin_write16(CAN1_MB00_DATA3, val)
761#define bfin_read_CAN1_MB00_LENGTH() bfin_read16(CAN1_MB00_LENGTH)
762#define bfin_write_CAN1_MB00_LENGTH(val) bfin_write16(CAN1_MB00_LENGTH, val)
763#define bfin_read_CAN1_MB00_TIMESTAMP() bfin_read16(CAN1_MB00_TIMESTAMP)
764#define bfin_write_CAN1_MB00_TIMESTAMP(val) bfin_write16(CAN1_MB00_TIMESTAMP, val)
765#define bfin_read_CAN1_MB00_ID0() bfin_read16(CAN1_MB00_ID0)
766#define bfin_write_CAN1_MB00_ID0(val) bfin_write16(CAN1_MB00_ID0, val)
767#define bfin_read_CAN1_MB00_ID1() bfin_read16(CAN1_MB00_ID1)
768#define bfin_write_CAN1_MB00_ID1(val) bfin_write16(CAN1_MB00_ID1, val)
769#define bfin_read_CAN1_MB01_DATA0() bfin_read16(CAN1_MB01_DATA0)
770#define bfin_write_CAN1_MB01_DATA0(val) bfin_write16(CAN1_MB01_DATA0, val)
771#define bfin_read_CAN1_MB01_DATA1() bfin_read16(CAN1_MB01_DATA1)
772#define bfin_write_CAN1_MB01_DATA1(val) bfin_write16(CAN1_MB01_DATA1, val)
773#define bfin_read_CAN1_MB01_DATA2() bfin_read16(CAN1_MB01_DATA2)
774#define bfin_write_CAN1_MB01_DATA2(val) bfin_write16(CAN1_MB01_DATA2, val)
775#define bfin_read_CAN1_MB01_DATA3() bfin_read16(CAN1_MB01_DATA3)
776#define bfin_write_CAN1_MB01_DATA3(val) bfin_write16(CAN1_MB01_DATA3, val)
777#define bfin_read_CAN1_MB01_LENGTH() bfin_read16(CAN1_MB01_LENGTH)
778#define bfin_write_CAN1_MB01_LENGTH(val) bfin_write16(CAN1_MB01_LENGTH, val)
779#define bfin_read_CAN1_MB01_TIMESTAMP() bfin_read16(CAN1_MB01_TIMESTAMP)
780#define bfin_write_CAN1_MB01_TIMESTAMP(val) bfin_write16(CAN1_MB01_TIMESTAMP, val)
781#define bfin_read_CAN1_MB01_ID0() bfin_read16(CAN1_MB01_ID0)
782#define bfin_write_CAN1_MB01_ID0(val) bfin_write16(CAN1_MB01_ID0, val)
783#define bfin_read_CAN1_MB01_ID1() bfin_read16(CAN1_MB01_ID1)
784#define bfin_write_CAN1_MB01_ID1(val) bfin_write16(CAN1_MB01_ID1, val)
785#define bfin_read_CAN1_MB02_DATA0() bfin_read16(CAN1_MB02_DATA0)
786#define bfin_write_CAN1_MB02_DATA0(val) bfin_write16(CAN1_MB02_DATA0, val)
787#define bfin_read_CAN1_MB02_DATA1() bfin_read16(CAN1_MB02_DATA1)
788#define bfin_write_CAN1_MB02_DATA1(val) bfin_write16(CAN1_MB02_DATA1, val)
789#define bfin_read_CAN1_MB02_DATA2() bfin_read16(CAN1_MB02_DATA2)
790#define bfin_write_CAN1_MB02_DATA2(val) bfin_write16(CAN1_MB02_DATA2, val)
791#define bfin_read_CAN1_MB02_DATA3() bfin_read16(CAN1_MB02_DATA3)
792#define bfin_write_CAN1_MB02_DATA3(val) bfin_write16(CAN1_MB02_DATA3, val)
793#define bfin_read_CAN1_MB02_LENGTH() bfin_read16(CAN1_MB02_LENGTH)
794#define bfin_write_CAN1_MB02_LENGTH(val) bfin_write16(CAN1_MB02_LENGTH, val)
795#define bfin_read_CAN1_MB02_TIMESTAMP() bfin_read16(CAN1_MB02_TIMESTAMP)
796#define bfin_write_CAN1_MB02_TIMESTAMP(val) bfin_write16(CAN1_MB02_TIMESTAMP, val)
797#define bfin_read_CAN1_MB02_ID0() bfin_read16(CAN1_MB02_ID0)
798#define bfin_write_CAN1_MB02_ID0(val) bfin_write16(CAN1_MB02_ID0, val)
799#define bfin_read_CAN1_MB02_ID1() bfin_read16(CAN1_MB02_ID1)
800#define bfin_write_CAN1_MB02_ID1(val) bfin_write16(CAN1_MB02_ID1, val)
801#define bfin_read_CAN1_MB03_DATA0() bfin_read16(CAN1_MB03_DATA0)
802#define bfin_write_CAN1_MB03_DATA0(val) bfin_write16(CAN1_MB03_DATA0, val)
803#define bfin_read_CAN1_MB03_DATA1() bfin_read16(CAN1_MB03_DATA1)
804#define bfin_write_CAN1_MB03_DATA1(val) bfin_write16(CAN1_MB03_DATA1, val)
805#define bfin_read_CAN1_MB03_DATA2() bfin_read16(CAN1_MB03_DATA2)
806#define bfin_write_CAN1_MB03_DATA2(val) bfin_write16(CAN1_MB03_DATA2, val)
807#define bfin_read_CAN1_MB03_DATA3() bfin_read16(CAN1_MB03_DATA3)
808#define bfin_write_CAN1_MB03_DATA3(val) bfin_write16(CAN1_MB03_DATA3, val)
809#define bfin_read_CAN1_MB03_LENGTH() bfin_read16(CAN1_MB03_LENGTH)
810#define bfin_write_CAN1_MB03_LENGTH(val) bfin_write16(CAN1_MB03_LENGTH, val)
811#define bfin_read_CAN1_MB03_TIMESTAMP() bfin_read16(CAN1_MB03_TIMESTAMP)
812#define bfin_write_CAN1_MB03_TIMESTAMP(val) bfin_write16(CAN1_MB03_TIMESTAMP, val)
813#define bfin_read_CAN1_MB03_ID0() bfin_read16(CAN1_MB03_ID0)
814#define bfin_write_CAN1_MB03_ID0(val) bfin_write16(CAN1_MB03_ID0, val)
815#define bfin_read_CAN1_MB03_ID1() bfin_read16(CAN1_MB03_ID1)
816#define bfin_write_CAN1_MB03_ID1(val) bfin_write16(CAN1_MB03_ID1, val)
817#define bfin_read_CAN1_MB04_DATA0() bfin_read16(CAN1_MB04_DATA0)
818#define bfin_write_CAN1_MB04_DATA0(val) bfin_write16(CAN1_MB04_DATA0, val)
819#define bfin_read_CAN1_MB04_DATA1() bfin_read16(CAN1_MB04_DATA1)
820#define bfin_write_CAN1_MB04_DATA1(val) bfin_write16(CAN1_MB04_DATA1, val)
821#define bfin_read_CAN1_MB04_DATA2() bfin_read16(CAN1_MB04_DATA2)
822#define bfin_write_CAN1_MB04_DATA2(val) bfin_write16(CAN1_MB04_DATA2, val)
823#define bfin_read_CAN1_MB04_DATA3() bfin_read16(CAN1_MB04_DATA3)
824#define bfin_write_CAN1_MB04_DATA3(val) bfin_write16(CAN1_MB04_DATA3, val)
825#define bfin_read_CAN1_MB04_LENGTH() bfin_read16(CAN1_MB04_LENGTH)
826#define bfin_write_CAN1_MB04_LENGTH(val) bfin_write16(CAN1_MB04_LENGTH, val)
827#define bfin_read_CAN1_MB04_TIMESTAMP() bfin_read16(CAN1_MB04_TIMESTAMP)
828#define bfin_write_CAN1_MB04_TIMESTAMP(val) bfin_write16(CAN1_MB04_TIMESTAMP, val)
829#define bfin_read_CAN1_MB04_ID0() bfin_read16(CAN1_MB04_ID0)
830#define bfin_write_CAN1_MB04_ID0(val) bfin_write16(CAN1_MB04_ID0, val)
831#define bfin_read_CAN1_MB04_ID1() bfin_read16(CAN1_MB04_ID1)
832#define bfin_write_CAN1_MB04_ID1(val) bfin_write16(CAN1_MB04_ID1, val)
833#define bfin_read_CAN1_MB05_DATA0() bfin_read16(CAN1_MB05_DATA0)
834#define bfin_write_CAN1_MB05_DATA0(val) bfin_write16(CAN1_MB05_DATA0, val)
835#define bfin_read_CAN1_MB05_DATA1() bfin_read16(CAN1_MB05_DATA1)
836#define bfin_write_CAN1_MB05_DATA1(val) bfin_write16(CAN1_MB05_DATA1, val)
837#define bfin_read_CAN1_MB05_DATA2() bfin_read16(CAN1_MB05_DATA2)
838#define bfin_write_CAN1_MB05_DATA2(val) bfin_write16(CAN1_MB05_DATA2, val)
839#define bfin_read_CAN1_MB05_DATA3() bfin_read16(CAN1_MB05_DATA3)
840#define bfin_write_CAN1_MB05_DATA3(val) bfin_write16(CAN1_MB05_DATA3, val)
841#define bfin_read_CAN1_MB05_LENGTH() bfin_read16(CAN1_MB05_LENGTH)
842#define bfin_write_CAN1_MB05_LENGTH(val) bfin_write16(CAN1_MB05_LENGTH, val)
843#define bfin_read_CAN1_MB05_TIMESTAMP() bfin_read16(CAN1_MB05_TIMESTAMP)
844#define bfin_write_CAN1_MB05_TIMESTAMP(val) bfin_write16(CAN1_MB05_TIMESTAMP, val)
845#define bfin_read_CAN1_MB05_ID0() bfin_read16(CAN1_MB05_ID0)
846#define bfin_write_CAN1_MB05_ID0(val) bfin_write16(CAN1_MB05_ID0, val)
847#define bfin_read_CAN1_MB05_ID1() bfin_read16(CAN1_MB05_ID1)
848#define bfin_write_CAN1_MB05_ID1(val) bfin_write16(CAN1_MB05_ID1, val)
849#define bfin_read_CAN1_MB06_DATA0() bfin_read16(CAN1_MB06_DATA0)
850#define bfin_write_CAN1_MB06_DATA0(val) bfin_write16(CAN1_MB06_DATA0, val)
851#define bfin_read_CAN1_MB06_DATA1() bfin_read16(CAN1_MB06_DATA1)
852#define bfin_write_CAN1_MB06_DATA1(val) bfin_write16(CAN1_MB06_DATA1, val)
853#define bfin_read_CAN1_MB06_DATA2() bfin_read16(CAN1_MB06_DATA2)
854#define bfin_write_CAN1_MB06_DATA2(val) bfin_write16(CAN1_MB06_DATA2, val)
855#define bfin_read_CAN1_MB06_DATA3() bfin_read16(CAN1_MB06_DATA3)
856#define bfin_write_CAN1_MB06_DATA3(val) bfin_write16(CAN1_MB06_DATA3, val)
857#define bfin_read_CAN1_MB06_LENGTH() bfin_read16(CAN1_MB06_LENGTH)
858#define bfin_write_CAN1_MB06_LENGTH(val) bfin_write16(CAN1_MB06_LENGTH, val)
859#define bfin_read_CAN1_MB06_TIMESTAMP() bfin_read16(CAN1_MB06_TIMESTAMP)
860#define bfin_write_CAN1_MB06_TIMESTAMP(val) bfin_write16(CAN1_MB06_TIMESTAMP, val)
861#define bfin_read_CAN1_MB06_ID0() bfin_read16(CAN1_MB06_ID0)
862#define bfin_write_CAN1_MB06_ID0(val) bfin_write16(CAN1_MB06_ID0, val)
863#define bfin_read_CAN1_MB06_ID1() bfin_read16(CAN1_MB06_ID1)
864#define bfin_write_CAN1_MB06_ID1(val) bfin_write16(CAN1_MB06_ID1, val)
865#define bfin_read_CAN1_MB07_DATA0() bfin_read16(CAN1_MB07_DATA0)
866#define bfin_write_CAN1_MB07_DATA0(val) bfin_write16(CAN1_MB07_DATA0, val)
867#define bfin_read_CAN1_MB07_DATA1() bfin_read16(CAN1_MB07_DATA1)
868#define bfin_write_CAN1_MB07_DATA1(val) bfin_write16(CAN1_MB07_DATA1, val)
869#define bfin_read_CAN1_MB07_DATA2() bfin_read16(CAN1_MB07_DATA2)
870#define bfin_write_CAN1_MB07_DATA2(val) bfin_write16(CAN1_MB07_DATA2, val)
871#define bfin_read_CAN1_MB07_DATA3() bfin_read16(CAN1_MB07_DATA3)
872#define bfin_write_CAN1_MB07_DATA3(val) bfin_write16(CAN1_MB07_DATA3, val)
873#define bfin_read_CAN1_MB07_LENGTH() bfin_read16(CAN1_MB07_LENGTH)
874#define bfin_write_CAN1_MB07_LENGTH(val) bfin_write16(CAN1_MB07_LENGTH, val)
875#define bfin_read_CAN1_MB07_TIMESTAMP() bfin_read16(CAN1_MB07_TIMESTAMP)
876#define bfin_write_CAN1_MB07_TIMESTAMP(val) bfin_write16(CAN1_MB07_TIMESTAMP, val)
877#define bfin_read_CAN1_MB07_ID0() bfin_read16(CAN1_MB07_ID0)
878#define bfin_write_CAN1_MB07_ID0(val) bfin_write16(CAN1_MB07_ID0, val)
879#define bfin_read_CAN1_MB07_ID1() bfin_read16(CAN1_MB07_ID1)
880#define bfin_write_CAN1_MB07_ID1(val) bfin_write16(CAN1_MB07_ID1, val)
881#define bfin_read_CAN1_MB08_DATA0() bfin_read16(CAN1_MB08_DATA0)
882#define bfin_write_CAN1_MB08_DATA0(val) bfin_write16(CAN1_MB08_DATA0, val)
883#define bfin_read_CAN1_MB08_DATA1() bfin_read16(CAN1_MB08_DATA1)
884#define bfin_write_CAN1_MB08_DATA1(val) bfin_write16(CAN1_MB08_DATA1, val)
885#define bfin_read_CAN1_MB08_DATA2() bfin_read16(CAN1_MB08_DATA2)
886#define bfin_write_CAN1_MB08_DATA2(val) bfin_write16(CAN1_MB08_DATA2, val)
887#define bfin_read_CAN1_MB08_DATA3() bfin_read16(CAN1_MB08_DATA3)
888#define bfin_write_CAN1_MB08_DATA3(val) bfin_write16(CAN1_MB08_DATA3, val)
889#define bfin_read_CAN1_MB08_LENGTH() bfin_read16(CAN1_MB08_LENGTH)
890#define bfin_write_CAN1_MB08_LENGTH(val) bfin_write16(CAN1_MB08_LENGTH, val)
891#define bfin_read_CAN1_MB08_TIMESTAMP() bfin_read16(CAN1_MB08_TIMESTAMP)
892#define bfin_write_CAN1_MB08_TIMESTAMP(val) bfin_write16(CAN1_MB08_TIMESTAMP, val)
893#define bfin_read_CAN1_MB08_ID0() bfin_read16(CAN1_MB08_ID0)
894#define bfin_write_CAN1_MB08_ID0(val) bfin_write16(CAN1_MB08_ID0, val)
895#define bfin_read_CAN1_MB08_ID1() bfin_read16(CAN1_MB08_ID1)
896#define bfin_write_CAN1_MB08_ID1(val) bfin_write16(CAN1_MB08_ID1, val)
897#define bfin_read_CAN1_MB09_DATA0() bfin_read16(CAN1_MB09_DATA0)
898#define bfin_write_CAN1_MB09_DATA0(val) bfin_write16(CAN1_MB09_DATA0, val)
899#define bfin_read_CAN1_MB09_DATA1() bfin_read16(CAN1_MB09_DATA1)
900#define bfin_write_CAN1_MB09_DATA1(val) bfin_write16(CAN1_MB09_DATA1, val)
901#define bfin_read_CAN1_MB09_DATA2() bfin_read16(CAN1_MB09_DATA2)
902#define bfin_write_CAN1_MB09_DATA2(val) bfin_write16(CAN1_MB09_DATA2, val)
903#define bfin_read_CAN1_MB09_DATA3() bfin_read16(CAN1_MB09_DATA3)
904#define bfin_write_CAN1_MB09_DATA3(val) bfin_write16(CAN1_MB09_DATA3, val)
905#define bfin_read_CAN1_MB09_LENGTH() bfin_read16(CAN1_MB09_LENGTH)
906#define bfin_write_CAN1_MB09_LENGTH(val) bfin_write16(CAN1_MB09_LENGTH, val)
907#define bfin_read_CAN1_MB09_TIMESTAMP() bfin_read16(CAN1_MB09_TIMESTAMP)
908#define bfin_write_CAN1_MB09_TIMESTAMP(val) bfin_write16(CAN1_MB09_TIMESTAMP, val)
909#define bfin_read_CAN1_MB09_ID0() bfin_read16(CAN1_MB09_ID0)
910#define bfin_write_CAN1_MB09_ID0(val) bfin_write16(CAN1_MB09_ID0, val)
911#define bfin_read_CAN1_MB09_ID1() bfin_read16(CAN1_MB09_ID1)
912#define bfin_write_CAN1_MB09_ID1(val) bfin_write16(CAN1_MB09_ID1, val)
913#define bfin_read_CAN1_MB10_DATA0() bfin_read16(CAN1_MB10_DATA0)
914#define bfin_write_CAN1_MB10_DATA0(val) bfin_write16(CAN1_MB10_DATA0, val)
915#define bfin_read_CAN1_MB10_DATA1() bfin_read16(CAN1_MB10_DATA1)
916#define bfin_write_CAN1_MB10_DATA1(val) bfin_write16(CAN1_MB10_DATA1, val)
917#define bfin_read_CAN1_MB10_DATA2() bfin_read16(CAN1_MB10_DATA2)
918#define bfin_write_CAN1_MB10_DATA2(val) bfin_write16(CAN1_MB10_DATA2, val)
919#define bfin_read_CAN1_MB10_DATA3() bfin_read16(CAN1_MB10_DATA3)
920#define bfin_write_CAN1_MB10_DATA3(val) bfin_write16(CAN1_MB10_DATA3, val)
921#define bfin_read_CAN1_MB10_LENGTH() bfin_read16(CAN1_MB10_LENGTH)
922#define bfin_write_CAN1_MB10_LENGTH(val) bfin_write16(CAN1_MB10_LENGTH, val)
923#define bfin_read_CAN1_MB10_TIMESTAMP() bfin_read16(CAN1_MB10_TIMESTAMP)
924#define bfin_write_CAN1_MB10_TIMESTAMP(val) bfin_write16(CAN1_MB10_TIMESTAMP, val)
925#define bfin_read_CAN1_MB10_ID0() bfin_read16(CAN1_MB10_ID0)
926#define bfin_write_CAN1_MB10_ID0(val) bfin_write16(CAN1_MB10_ID0, val)
927#define bfin_read_CAN1_MB10_ID1() bfin_read16(CAN1_MB10_ID1)
928#define bfin_write_CAN1_MB10_ID1(val) bfin_write16(CAN1_MB10_ID1, val)
929#define bfin_read_CAN1_MB11_DATA0() bfin_read16(CAN1_MB11_DATA0)
930#define bfin_write_CAN1_MB11_DATA0(val) bfin_write16(CAN1_MB11_DATA0, val)
931#define bfin_read_CAN1_MB11_DATA1() bfin_read16(CAN1_MB11_DATA1)
932#define bfin_write_CAN1_MB11_DATA1(val) bfin_write16(CAN1_MB11_DATA1, val)
933#define bfin_read_CAN1_MB11_DATA2() bfin_read16(CAN1_MB11_DATA2)
934#define bfin_write_CAN1_MB11_DATA2(val) bfin_write16(CAN1_MB11_DATA2, val)
935#define bfin_read_CAN1_MB11_DATA3() bfin_read16(CAN1_MB11_DATA3)
936#define bfin_write_CAN1_MB11_DATA3(val) bfin_write16(CAN1_MB11_DATA3, val)
937#define bfin_read_CAN1_MB11_LENGTH() bfin_read16(CAN1_MB11_LENGTH)
938#define bfin_write_CAN1_MB11_LENGTH(val) bfin_write16(CAN1_MB11_LENGTH, val)
939#define bfin_read_CAN1_MB11_TIMESTAMP() bfin_read16(CAN1_MB11_TIMESTAMP)
940#define bfin_write_CAN1_MB11_TIMESTAMP(val) bfin_write16(CAN1_MB11_TIMESTAMP, val)
941#define bfin_read_CAN1_MB11_ID0() bfin_read16(CAN1_MB11_ID0)
942#define bfin_write_CAN1_MB11_ID0(val) bfin_write16(CAN1_MB11_ID0, val)
943#define bfin_read_CAN1_MB11_ID1() bfin_read16(CAN1_MB11_ID1)
944#define bfin_write_CAN1_MB11_ID1(val) bfin_write16(CAN1_MB11_ID1, val)
945#define bfin_read_CAN1_MB12_DATA0() bfin_read16(CAN1_MB12_DATA0)
946#define bfin_write_CAN1_MB12_DATA0(val) bfin_write16(CAN1_MB12_DATA0, val)
947#define bfin_read_CAN1_MB12_DATA1() bfin_read16(CAN1_MB12_DATA1)
948#define bfin_write_CAN1_MB12_DATA1(val) bfin_write16(CAN1_MB12_DATA1, val)
949#define bfin_read_CAN1_MB12_DATA2() bfin_read16(CAN1_MB12_DATA2)
950#define bfin_write_CAN1_MB12_DATA2(val) bfin_write16(CAN1_MB12_DATA2, val)
951#define bfin_read_CAN1_MB12_DATA3() bfin_read16(CAN1_MB12_DATA3)
952#define bfin_write_CAN1_MB12_DATA3(val) bfin_write16(CAN1_MB12_DATA3, val)
953#define bfin_read_CAN1_MB12_LENGTH() bfin_read16(CAN1_MB12_LENGTH)
954#define bfin_write_CAN1_MB12_LENGTH(val) bfin_write16(CAN1_MB12_LENGTH, val)
955#define bfin_read_CAN1_MB12_TIMESTAMP() bfin_read16(CAN1_MB12_TIMESTAMP)
956#define bfin_write_CAN1_MB12_TIMESTAMP(val) bfin_write16(CAN1_MB12_TIMESTAMP, val)
957#define bfin_read_CAN1_MB12_ID0() bfin_read16(CAN1_MB12_ID0)
958#define bfin_write_CAN1_MB12_ID0(val) bfin_write16(CAN1_MB12_ID0, val)
959#define bfin_read_CAN1_MB12_ID1() bfin_read16(CAN1_MB12_ID1)
960#define bfin_write_CAN1_MB12_ID1(val) bfin_write16(CAN1_MB12_ID1, val)
961#define bfin_read_CAN1_MB13_DATA0() bfin_read16(CAN1_MB13_DATA0)
962#define bfin_write_CAN1_MB13_DATA0(val) bfin_write16(CAN1_MB13_DATA0, val)
963#define bfin_read_CAN1_MB13_DATA1() bfin_read16(CAN1_MB13_DATA1)
964#define bfin_write_CAN1_MB13_DATA1(val) bfin_write16(CAN1_MB13_DATA1, val)
965#define bfin_read_CAN1_MB13_DATA2() bfin_read16(CAN1_MB13_DATA2)
966#define bfin_write_CAN1_MB13_DATA2(val) bfin_write16(CAN1_MB13_DATA2, val)
967#define bfin_read_CAN1_MB13_DATA3() bfin_read16(CAN1_MB13_DATA3)
968#define bfin_write_CAN1_MB13_DATA3(val) bfin_write16(CAN1_MB13_DATA3, val)
969#define bfin_read_CAN1_MB13_LENGTH() bfin_read16(CAN1_MB13_LENGTH)
970#define bfin_write_CAN1_MB13_LENGTH(val) bfin_write16(CAN1_MB13_LENGTH, val)
971#define bfin_read_CAN1_MB13_TIMESTAMP() bfin_read16(CAN1_MB13_TIMESTAMP)
972#define bfin_write_CAN1_MB13_TIMESTAMP(val) bfin_write16(CAN1_MB13_TIMESTAMP, val)
973#define bfin_read_CAN1_MB13_ID0() bfin_read16(CAN1_MB13_ID0)
974#define bfin_write_CAN1_MB13_ID0(val) bfin_write16(CAN1_MB13_ID0, val)
975#define bfin_read_CAN1_MB13_ID1() bfin_read16(CAN1_MB13_ID1)
976#define bfin_write_CAN1_MB13_ID1(val) bfin_write16(CAN1_MB13_ID1, val)
977#define bfin_read_CAN1_MB14_DATA0() bfin_read16(CAN1_MB14_DATA0)
978#define bfin_write_CAN1_MB14_DATA0(val) bfin_write16(CAN1_MB14_DATA0, val)
979#define bfin_read_CAN1_MB14_DATA1() bfin_read16(CAN1_MB14_DATA1)
980#define bfin_write_CAN1_MB14_DATA1(val) bfin_write16(CAN1_MB14_DATA1, val)
981#define bfin_read_CAN1_MB14_DATA2() bfin_read16(CAN1_MB14_DATA2)
982#define bfin_write_CAN1_MB14_DATA2(val) bfin_write16(CAN1_MB14_DATA2, val)
983#define bfin_read_CAN1_MB14_DATA3() bfin_read16(CAN1_MB14_DATA3)
984#define bfin_write_CAN1_MB14_DATA3(val) bfin_write16(CAN1_MB14_DATA3, val)
985#define bfin_read_CAN1_MB14_LENGTH() bfin_read16(CAN1_MB14_LENGTH)
986#define bfin_write_CAN1_MB14_LENGTH(val) bfin_write16(CAN1_MB14_LENGTH, val)
987#define bfin_read_CAN1_MB14_TIMESTAMP() bfin_read16(CAN1_MB14_TIMESTAMP)
988#define bfin_write_CAN1_MB14_TIMESTAMP(val) bfin_write16(CAN1_MB14_TIMESTAMP, val)
989#define bfin_read_CAN1_MB14_ID0() bfin_read16(CAN1_MB14_ID0)
990#define bfin_write_CAN1_MB14_ID0(val) bfin_write16(CAN1_MB14_ID0, val)
991#define bfin_read_CAN1_MB14_ID1() bfin_read16(CAN1_MB14_ID1)
992#define bfin_write_CAN1_MB14_ID1(val) bfin_write16(CAN1_MB14_ID1, val)
993#define bfin_read_CAN1_MB15_DATA0() bfin_read16(CAN1_MB15_DATA0)
994#define bfin_write_CAN1_MB15_DATA0(val) bfin_write16(CAN1_MB15_DATA0, val)
995#define bfin_read_CAN1_MB15_DATA1() bfin_read16(CAN1_MB15_DATA1)
996#define bfin_write_CAN1_MB15_DATA1(val) bfin_write16(CAN1_MB15_DATA1, val)
997#define bfin_read_CAN1_MB15_DATA2() bfin_read16(CAN1_MB15_DATA2)
998#define bfin_write_CAN1_MB15_DATA2(val) bfin_write16(CAN1_MB15_DATA2, val)
999#define bfin_read_CAN1_MB15_DATA3() bfin_read16(CAN1_MB15_DATA3)
1000#define bfin_write_CAN1_MB15_DATA3(val) bfin_write16(CAN1_MB15_DATA3, val)
1001#define bfin_read_CAN1_MB15_LENGTH() bfin_read16(CAN1_MB15_LENGTH)
1002#define bfin_write_CAN1_MB15_LENGTH(val) bfin_write16(CAN1_MB15_LENGTH, val)
1003#define bfin_read_CAN1_MB15_TIMESTAMP() bfin_read16(CAN1_MB15_TIMESTAMP)
1004#define bfin_write_CAN1_MB15_TIMESTAMP(val) bfin_write16(CAN1_MB15_TIMESTAMP, val)
1005#define bfin_read_CAN1_MB15_ID0() bfin_read16(CAN1_MB15_ID0)
1006#define bfin_write_CAN1_MB15_ID0(val) bfin_write16(CAN1_MB15_ID0, val)
1007#define bfin_read_CAN1_MB15_ID1() bfin_read16(CAN1_MB15_ID1)
1008#define bfin_write_CAN1_MB15_ID1(val) bfin_write16(CAN1_MB15_ID1, val)
1009
1010/* CAN Controller 1 Mailbox Data Registers */
1011
1012#define bfin_read_CAN1_MB16_DATA0() bfin_read16(CAN1_MB16_DATA0)
1013#define bfin_write_CAN1_MB16_DATA0(val) bfin_write16(CAN1_MB16_DATA0, val)
1014#define bfin_read_CAN1_MB16_DATA1() bfin_read16(CAN1_MB16_DATA1)
1015#define bfin_write_CAN1_MB16_DATA1(val) bfin_write16(CAN1_MB16_DATA1, val)
1016#define bfin_read_CAN1_MB16_DATA2() bfin_read16(CAN1_MB16_DATA2)
1017#define bfin_write_CAN1_MB16_DATA2(val) bfin_write16(CAN1_MB16_DATA2, val)
1018#define bfin_read_CAN1_MB16_DATA3() bfin_read16(CAN1_MB16_DATA3)
1019#define bfin_write_CAN1_MB16_DATA3(val) bfin_write16(CAN1_MB16_DATA3, val)
1020#define bfin_read_CAN1_MB16_LENGTH() bfin_read16(CAN1_MB16_LENGTH)
1021#define bfin_write_CAN1_MB16_LENGTH(val) bfin_write16(CAN1_MB16_LENGTH, val)
1022#define bfin_read_CAN1_MB16_TIMESTAMP() bfin_read16(CAN1_MB16_TIMESTAMP)
1023#define bfin_write_CAN1_MB16_TIMESTAMP(val) bfin_write16(CAN1_MB16_TIMESTAMP, val)
1024#define bfin_read_CAN1_MB16_ID0() bfin_read16(CAN1_MB16_ID0)
1025#define bfin_write_CAN1_MB16_ID0(val) bfin_write16(CAN1_MB16_ID0, val)
1026#define bfin_read_CAN1_MB16_ID1() bfin_read16(CAN1_MB16_ID1)
1027#define bfin_write_CAN1_MB16_ID1(val) bfin_write16(CAN1_MB16_ID1, val)
1028#define bfin_read_CAN1_MB17_DATA0() bfin_read16(CAN1_MB17_DATA0)
1029#define bfin_write_CAN1_MB17_DATA0(val) bfin_write16(CAN1_MB17_DATA0, val)
1030#define bfin_read_CAN1_MB17_DATA1() bfin_read16(CAN1_MB17_DATA1)
1031#define bfin_write_CAN1_MB17_DATA1(val) bfin_write16(CAN1_MB17_DATA1, val)
1032#define bfin_read_CAN1_MB17_DATA2() bfin_read16(CAN1_MB17_DATA2)
1033#define bfin_write_CAN1_MB17_DATA2(val) bfin_write16(CAN1_MB17_DATA2, val)
1034#define bfin_read_CAN1_MB17_DATA3() bfin_read16(CAN1_MB17_DATA3)
1035#define bfin_write_CAN1_MB17_DATA3(val) bfin_write16(CAN1_MB17_DATA3, val)
1036#define bfin_read_CAN1_MB17_LENGTH() bfin_read16(CAN1_MB17_LENGTH)
1037#define bfin_write_CAN1_MB17_LENGTH(val) bfin_write16(CAN1_MB17_LENGTH, val)
1038#define bfin_read_CAN1_MB17_TIMESTAMP() bfin_read16(CAN1_MB17_TIMESTAMP)
1039#define bfin_write_CAN1_MB17_TIMESTAMP(val) bfin_write16(CAN1_MB17_TIMESTAMP, val)
1040#define bfin_read_CAN1_MB17_ID0() bfin_read16(CAN1_MB17_ID0)
1041#define bfin_write_CAN1_MB17_ID0(val) bfin_write16(CAN1_MB17_ID0, val)
1042#define bfin_read_CAN1_MB17_ID1() bfin_read16(CAN1_MB17_ID1)
1043#define bfin_write_CAN1_MB17_ID1(val) bfin_write16(CAN1_MB17_ID1, val)
1044#define bfin_read_CAN1_MB18_DATA0() bfin_read16(CAN1_MB18_DATA0)
1045#define bfin_write_CAN1_MB18_DATA0(val) bfin_write16(CAN1_MB18_DATA0, val)
1046#define bfin_read_CAN1_MB18_DATA1() bfin_read16(CAN1_MB18_DATA1)
1047#define bfin_write_CAN1_MB18_DATA1(val) bfin_write16(CAN1_MB18_DATA1, val)
1048#define bfin_read_CAN1_MB18_DATA2() bfin_read16(CAN1_MB18_DATA2)
1049#define bfin_write_CAN1_MB18_DATA2(val) bfin_write16(CAN1_MB18_DATA2, val)
1050#define bfin_read_CAN1_MB18_DATA3() bfin_read16(CAN1_MB18_DATA3)
1051#define bfin_write_CAN1_MB18_DATA3(val) bfin_write16(CAN1_MB18_DATA3, val)
1052#define bfin_read_CAN1_MB18_LENGTH() bfin_read16(CAN1_MB18_LENGTH)
1053#define bfin_write_CAN1_MB18_LENGTH(val) bfin_write16(CAN1_MB18_LENGTH, val)
1054#define bfin_read_CAN1_MB18_TIMESTAMP() bfin_read16(CAN1_MB18_TIMESTAMP)
1055#define bfin_write_CAN1_MB18_TIMESTAMP(val) bfin_write16(CAN1_MB18_TIMESTAMP, val)
1056#define bfin_read_CAN1_MB18_ID0() bfin_read16(CAN1_MB18_ID0)
1057#define bfin_write_CAN1_MB18_ID0(val) bfin_write16(CAN1_MB18_ID0, val)
1058#define bfin_read_CAN1_MB18_ID1() bfin_read16(CAN1_MB18_ID1)
1059#define bfin_write_CAN1_MB18_ID1(val) bfin_write16(CAN1_MB18_ID1, val)
1060#define bfin_read_CAN1_MB19_DATA0() bfin_read16(CAN1_MB19_DATA0)
1061#define bfin_write_CAN1_MB19_DATA0(val) bfin_write16(CAN1_MB19_DATA0, val)
1062#define bfin_read_CAN1_MB19_DATA1() bfin_read16(CAN1_MB19_DATA1)
1063#define bfin_write_CAN1_MB19_DATA1(val) bfin_write16(CAN1_MB19_DATA1, val)
1064#define bfin_read_CAN1_MB19_DATA2() bfin_read16(CAN1_MB19_DATA2)
1065#define bfin_write_CAN1_MB19_DATA2(val) bfin_write16(CAN1_MB19_DATA2, val)
1066#define bfin_read_CAN1_MB19_DATA3() bfin_read16(CAN1_MB19_DATA3)
1067#define bfin_write_CAN1_MB19_DATA3(val) bfin_write16(CAN1_MB19_DATA3, val)
1068#define bfin_read_CAN1_MB19_LENGTH() bfin_read16(CAN1_MB19_LENGTH)
1069#define bfin_write_CAN1_MB19_LENGTH(val) bfin_write16(CAN1_MB19_LENGTH, val)
1070#define bfin_read_CAN1_MB19_TIMESTAMP() bfin_read16(CAN1_MB19_TIMESTAMP)
1071#define bfin_write_CAN1_MB19_TIMESTAMP(val) bfin_write16(CAN1_MB19_TIMESTAMP, val)
1072#define bfin_read_CAN1_MB19_ID0() bfin_read16(CAN1_MB19_ID0)
1073#define bfin_write_CAN1_MB19_ID0(val) bfin_write16(CAN1_MB19_ID0, val)
1074#define bfin_read_CAN1_MB19_ID1() bfin_read16(CAN1_MB19_ID1)
1075#define bfin_write_CAN1_MB19_ID1(val) bfin_write16(CAN1_MB19_ID1, val)
1076#define bfin_read_CAN1_MB20_DATA0() bfin_read16(CAN1_MB20_DATA0)
1077#define bfin_write_CAN1_MB20_DATA0(val) bfin_write16(CAN1_MB20_DATA0, val)
1078#define bfin_read_CAN1_MB20_DATA1() bfin_read16(CAN1_MB20_DATA1)
1079#define bfin_write_CAN1_MB20_DATA1(val) bfin_write16(CAN1_MB20_DATA1, val)
1080#define bfin_read_CAN1_MB20_DATA2() bfin_read16(CAN1_MB20_DATA2)
1081#define bfin_write_CAN1_MB20_DATA2(val) bfin_write16(CAN1_MB20_DATA2, val)
1082#define bfin_read_CAN1_MB20_DATA3() bfin_read16(CAN1_MB20_DATA3)
1083#define bfin_write_CAN1_MB20_DATA3(val) bfin_write16(CAN1_MB20_DATA3, val)
1084#define bfin_read_CAN1_MB20_LENGTH() bfin_read16(CAN1_MB20_LENGTH)
1085#define bfin_write_CAN1_MB20_LENGTH(val) bfin_write16(CAN1_MB20_LENGTH, val)
1086#define bfin_read_CAN1_MB20_TIMESTAMP() bfin_read16(CAN1_MB20_TIMESTAMP)
1087#define bfin_write_CAN1_MB20_TIMESTAMP(val) bfin_write16(CAN1_MB20_TIMESTAMP, val)
1088#define bfin_read_CAN1_MB20_ID0() bfin_read16(CAN1_MB20_ID0)
1089#define bfin_write_CAN1_MB20_ID0(val) bfin_write16(CAN1_MB20_ID0, val)
1090#define bfin_read_CAN1_MB20_ID1() bfin_read16(CAN1_MB20_ID1)
1091#define bfin_write_CAN1_MB20_ID1(val) bfin_write16(CAN1_MB20_ID1, val)
1092#define bfin_read_CAN1_MB21_DATA0() bfin_read16(CAN1_MB21_DATA0)
1093#define bfin_write_CAN1_MB21_DATA0(val) bfin_write16(CAN1_MB21_DATA0, val)
1094#define bfin_read_CAN1_MB21_DATA1() bfin_read16(CAN1_MB21_DATA1)
1095#define bfin_write_CAN1_MB21_DATA1(val) bfin_write16(CAN1_MB21_DATA1, val)
1096#define bfin_read_CAN1_MB21_DATA2() bfin_read16(CAN1_MB21_DATA2)
1097#define bfin_write_CAN1_MB21_DATA2(val) bfin_write16(CAN1_MB21_DATA2, val)
1098#define bfin_read_CAN1_MB21_DATA3() bfin_read16(CAN1_MB21_DATA3)
1099#define bfin_write_CAN1_MB21_DATA3(val) bfin_write16(CAN1_MB21_DATA3, val)
1100#define bfin_read_CAN1_MB21_LENGTH() bfin_read16(CAN1_MB21_LENGTH)
1101#define bfin_write_CAN1_MB21_LENGTH(val) bfin_write16(CAN1_MB21_LENGTH, val)
1102#define bfin_read_CAN1_MB21_TIMESTAMP() bfin_read16(CAN1_MB21_TIMESTAMP)
1103#define bfin_write_CAN1_MB21_TIMESTAMP(val) bfin_write16(CAN1_MB21_TIMESTAMP, val)
1104#define bfin_read_CAN1_MB21_ID0() bfin_read16(CAN1_MB21_ID0)
1105#define bfin_write_CAN1_MB21_ID0(val) bfin_write16(CAN1_MB21_ID0, val)
1106#define bfin_read_CAN1_MB21_ID1() bfin_read16(CAN1_MB21_ID1)
1107#define bfin_write_CAN1_MB21_ID1(val) bfin_write16(CAN1_MB21_ID1, val)
1108#define bfin_read_CAN1_MB22_DATA0() bfin_read16(CAN1_MB22_DATA0)
1109#define bfin_write_CAN1_MB22_DATA0(val) bfin_write16(CAN1_MB22_DATA0, val)
1110#define bfin_read_CAN1_MB22_DATA1() bfin_read16(CAN1_MB22_DATA1)
1111#define bfin_write_CAN1_MB22_DATA1(val) bfin_write16(CAN1_MB22_DATA1, val)
1112#define bfin_read_CAN1_MB22_DATA2() bfin_read16(CAN1_MB22_DATA2)
1113#define bfin_write_CAN1_MB22_DATA2(val) bfin_write16(CAN1_MB22_DATA2, val)
1114#define bfin_read_CAN1_MB22_DATA3() bfin_read16(CAN1_MB22_DATA3)
1115#define bfin_write_CAN1_MB22_DATA3(val) bfin_write16(CAN1_MB22_DATA3, val)
1116#define bfin_read_CAN1_MB22_LENGTH() bfin_read16(CAN1_MB22_LENGTH)
1117#define bfin_write_CAN1_MB22_LENGTH(val) bfin_write16(CAN1_MB22_LENGTH, val)
1118#define bfin_read_CAN1_MB22_TIMESTAMP() bfin_read16(CAN1_MB22_TIMESTAMP)
1119#define bfin_write_CAN1_MB22_TIMESTAMP(val) bfin_write16(CAN1_MB22_TIMESTAMP, val)
1120#define bfin_read_CAN1_MB22_ID0() bfin_read16(CAN1_MB22_ID0)
1121#define bfin_write_CAN1_MB22_ID0(val) bfin_write16(CAN1_MB22_ID0, val)
1122#define bfin_read_CAN1_MB22_ID1() bfin_read16(CAN1_MB22_ID1)
1123#define bfin_write_CAN1_MB22_ID1(val) bfin_write16(CAN1_MB22_ID1, val)
1124#define bfin_read_CAN1_MB23_DATA0() bfin_read16(CAN1_MB23_DATA0)
1125#define bfin_write_CAN1_MB23_DATA0(val) bfin_write16(CAN1_MB23_DATA0, val)
1126#define bfin_read_CAN1_MB23_DATA1() bfin_read16(CAN1_MB23_DATA1)
1127#define bfin_write_CAN1_MB23_DATA1(val) bfin_write16(CAN1_MB23_DATA1, val)
1128#define bfin_read_CAN1_MB23_DATA2() bfin_read16(CAN1_MB23_DATA2)
1129#define bfin_write_CAN1_MB23_DATA2(val) bfin_write16(CAN1_MB23_DATA2, val)
1130#define bfin_read_CAN1_MB23_DATA3() bfin_read16(CAN1_MB23_DATA3)
1131#define bfin_write_CAN1_MB23_DATA3(val) bfin_write16(CAN1_MB23_DATA3, val)
1132#define bfin_read_CAN1_MB23_LENGTH() bfin_read16(CAN1_MB23_LENGTH)
1133#define bfin_write_CAN1_MB23_LENGTH(val) bfin_write16(CAN1_MB23_LENGTH, val)
1134#define bfin_read_CAN1_MB23_TIMESTAMP() bfin_read16(CAN1_MB23_TIMESTAMP)
1135#define bfin_write_CAN1_MB23_TIMESTAMP(val) bfin_write16(CAN1_MB23_TIMESTAMP, val)
1136#define bfin_read_CAN1_MB23_ID0() bfin_read16(CAN1_MB23_ID0)
1137#define bfin_write_CAN1_MB23_ID0(val) bfin_write16(CAN1_MB23_ID0, val)
1138#define bfin_read_CAN1_MB23_ID1() bfin_read16(CAN1_MB23_ID1)
1139#define bfin_write_CAN1_MB23_ID1(val) bfin_write16(CAN1_MB23_ID1, val)
1140#define bfin_read_CAN1_MB24_DATA0() bfin_read16(CAN1_MB24_DATA0)
1141#define bfin_write_CAN1_MB24_DATA0(val) bfin_write16(CAN1_MB24_DATA0, val)
1142#define bfin_read_CAN1_MB24_DATA1() bfin_read16(CAN1_MB24_DATA1)
1143#define bfin_write_CAN1_MB24_DATA1(val) bfin_write16(CAN1_MB24_DATA1, val)
1144#define bfin_read_CAN1_MB24_DATA2() bfin_read16(CAN1_MB24_DATA2)
1145#define bfin_write_CAN1_MB24_DATA2(val) bfin_write16(CAN1_MB24_DATA2, val)
1146#define bfin_read_CAN1_MB24_DATA3() bfin_read16(CAN1_MB24_DATA3)
1147#define bfin_write_CAN1_MB24_DATA3(val) bfin_write16(CAN1_MB24_DATA3, val)
1148#define bfin_read_CAN1_MB24_LENGTH() bfin_read16(CAN1_MB24_LENGTH)
1149#define bfin_write_CAN1_MB24_LENGTH(val) bfin_write16(CAN1_MB24_LENGTH, val)
1150#define bfin_read_CAN1_MB24_TIMESTAMP() bfin_read16(CAN1_MB24_TIMESTAMP)
1151#define bfin_write_CAN1_MB24_TIMESTAMP(val) bfin_write16(CAN1_MB24_TIMESTAMP, val)
1152#define bfin_read_CAN1_MB24_ID0() bfin_read16(CAN1_MB24_ID0)
1153#define bfin_write_CAN1_MB24_ID0(val) bfin_write16(CAN1_MB24_ID0, val)
1154#define bfin_read_CAN1_MB24_ID1() bfin_read16(CAN1_MB24_ID1)
1155#define bfin_write_CAN1_MB24_ID1(val) bfin_write16(CAN1_MB24_ID1, val)
1156#define bfin_read_CAN1_MB25_DATA0() bfin_read16(CAN1_MB25_DATA0)
1157#define bfin_write_CAN1_MB25_DATA0(val) bfin_write16(CAN1_MB25_DATA0, val)
1158#define bfin_read_CAN1_MB25_DATA1() bfin_read16(CAN1_MB25_DATA1)
1159#define bfin_write_CAN1_MB25_DATA1(val) bfin_write16(CAN1_MB25_DATA1, val)
1160#define bfin_read_CAN1_MB25_DATA2() bfin_read16(CAN1_MB25_DATA2)
1161#define bfin_write_CAN1_MB25_DATA2(val) bfin_write16(CAN1_MB25_DATA2, val)
1162#define bfin_read_CAN1_MB25_DATA3() bfin_read16(CAN1_MB25_DATA3)
1163#define bfin_write_CAN1_MB25_DATA3(val) bfin_write16(CAN1_MB25_DATA3, val)
1164#define bfin_read_CAN1_MB25_LENGTH() bfin_read16(CAN1_MB25_LENGTH)
1165#define bfin_write_CAN1_MB25_LENGTH(val) bfin_write16(CAN1_MB25_LENGTH, val)
1166#define bfin_read_CAN1_MB25_TIMESTAMP() bfin_read16(CAN1_MB25_TIMESTAMP)
1167#define bfin_write_CAN1_MB25_TIMESTAMP(val) bfin_write16(CAN1_MB25_TIMESTAMP, val)
1168#define bfin_read_CAN1_MB25_ID0() bfin_read16(CAN1_MB25_ID0)
1169#define bfin_write_CAN1_MB25_ID0(val) bfin_write16(CAN1_MB25_ID0, val)
1170#define bfin_read_CAN1_MB25_ID1() bfin_read16(CAN1_MB25_ID1)
1171#define bfin_write_CAN1_MB25_ID1(val) bfin_write16(CAN1_MB25_ID1, val)
1172#define bfin_read_CAN1_MB26_DATA0() bfin_read16(CAN1_MB26_DATA0)
1173#define bfin_write_CAN1_MB26_DATA0(val) bfin_write16(CAN1_MB26_DATA0, val)
1174#define bfin_read_CAN1_MB26_DATA1() bfin_read16(CAN1_MB26_DATA1)
1175#define bfin_write_CAN1_MB26_DATA1(val) bfin_write16(CAN1_MB26_DATA1, val)
1176#define bfin_read_CAN1_MB26_DATA2() bfin_read16(CAN1_MB26_DATA2)
1177#define bfin_write_CAN1_MB26_DATA2(val) bfin_write16(CAN1_MB26_DATA2, val)
1178#define bfin_read_CAN1_MB26_DATA3() bfin_read16(CAN1_MB26_DATA3)
1179#define bfin_write_CAN1_MB26_DATA3(val) bfin_write16(CAN1_MB26_DATA3, val)
1180#define bfin_read_CAN1_MB26_LENGTH() bfin_read16(CAN1_MB26_LENGTH)
1181#define bfin_write_CAN1_MB26_LENGTH(val) bfin_write16(CAN1_MB26_LENGTH, val)
1182#define bfin_read_CAN1_MB26_TIMESTAMP() bfin_read16(CAN1_MB26_TIMESTAMP)
1183#define bfin_write_CAN1_MB26_TIMESTAMP(val) bfin_write16(CAN1_MB26_TIMESTAMP, val)
1184#define bfin_read_CAN1_MB26_ID0() bfin_read16(CAN1_MB26_ID0)
1185#define bfin_write_CAN1_MB26_ID0(val) bfin_write16(CAN1_MB26_ID0, val)
1186#define bfin_read_CAN1_MB26_ID1() bfin_read16(CAN1_MB26_ID1)
1187#define bfin_write_CAN1_MB26_ID1(val) bfin_write16(CAN1_MB26_ID1, val)
1188#define bfin_read_CAN1_MB27_DATA0() bfin_read16(CAN1_MB27_DATA0)
1189#define bfin_write_CAN1_MB27_DATA0(val) bfin_write16(CAN1_MB27_DATA0, val)
1190#define bfin_read_CAN1_MB27_DATA1() bfin_read16(CAN1_MB27_DATA1)
1191#define bfin_write_CAN1_MB27_DATA1(val) bfin_write16(CAN1_MB27_DATA1, val)
1192#define bfin_read_CAN1_MB27_DATA2() bfin_read16(CAN1_MB27_DATA2)
1193#define bfin_write_CAN1_MB27_DATA2(val) bfin_write16(CAN1_MB27_DATA2, val)
1194#define bfin_read_CAN1_MB27_DATA3() bfin_read16(CAN1_MB27_DATA3)
1195#define bfin_write_CAN1_MB27_DATA3(val) bfin_write16(CAN1_MB27_DATA3, val)
1196#define bfin_read_CAN1_MB27_LENGTH() bfin_read16(CAN1_MB27_LENGTH)
1197#define bfin_write_CAN1_MB27_LENGTH(val) bfin_write16(CAN1_MB27_LENGTH, val)
1198#define bfin_read_CAN1_MB27_TIMESTAMP() bfin_read16(CAN1_MB27_TIMESTAMP)
1199#define bfin_write_CAN1_MB27_TIMESTAMP(val) bfin_write16(CAN1_MB27_TIMESTAMP, val)
1200#define bfin_read_CAN1_MB27_ID0() bfin_read16(CAN1_MB27_ID0)
1201#define bfin_write_CAN1_MB27_ID0(val) bfin_write16(CAN1_MB27_ID0, val)
1202#define bfin_read_CAN1_MB27_ID1() bfin_read16(CAN1_MB27_ID1)
1203#define bfin_write_CAN1_MB27_ID1(val) bfin_write16(CAN1_MB27_ID1, val)
1204#define bfin_read_CAN1_MB28_DATA0() bfin_read16(CAN1_MB28_DATA0)
1205#define bfin_write_CAN1_MB28_DATA0(val) bfin_write16(CAN1_MB28_DATA0, val)
1206#define bfin_read_CAN1_MB28_DATA1() bfin_read16(CAN1_MB28_DATA1)
1207#define bfin_write_CAN1_MB28_DATA1(val) bfin_write16(CAN1_MB28_DATA1, val)
1208#define bfin_read_CAN1_MB28_DATA2() bfin_read16(CAN1_MB28_DATA2)
1209#define bfin_write_CAN1_MB28_DATA2(val) bfin_write16(CAN1_MB28_DATA2, val)
1210#define bfin_read_CAN1_MB28_DATA3() bfin_read16(CAN1_MB28_DATA3)
1211#define bfin_write_CAN1_MB28_DATA3(val) bfin_write16(CAN1_MB28_DATA3, val)
1212#define bfin_read_CAN1_MB28_LENGTH() bfin_read16(CAN1_MB28_LENGTH)
1213#define bfin_write_CAN1_MB28_LENGTH(val) bfin_write16(CAN1_MB28_LENGTH, val)
1214#define bfin_read_CAN1_MB28_TIMESTAMP() bfin_read16(CAN1_MB28_TIMESTAMP)
1215#define bfin_write_CAN1_MB28_TIMESTAMP(val) bfin_write16(CAN1_MB28_TIMESTAMP, val)
1216#define bfin_read_CAN1_MB28_ID0() bfin_read16(CAN1_MB28_ID0)
1217#define bfin_write_CAN1_MB28_ID0(val) bfin_write16(CAN1_MB28_ID0, val)
1218#define bfin_read_CAN1_MB28_ID1() bfin_read16(CAN1_MB28_ID1)
1219#define bfin_write_CAN1_MB28_ID1(val) bfin_write16(CAN1_MB28_ID1, val)
1220#define bfin_read_CAN1_MB29_DATA0() bfin_read16(CAN1_MB29_DATA0)
1221#define bfin_write_CAN1_MB29_DATA0(val) bfin_write16(CAN1_MB29_DATA0, val)
1222#define bfin_read_CAN1_MB29_DATA1() bfin_read16(CAN1_MB29_DATA1)
1223#define bfin_write_CAN1_MB29_DATA1(val) bfin_write16(CAN1_MB29_DATA1, val)
1224#define bfin_read_CAN1_MB29_DATA2() bfin_read16(CAN1_MB29_DATA2)
1225#define bfin_write_CAN1_MB29_DATA2(val) bfin_write16(CAN1_MB29_DATA2, val)
1226#define bfin_read_CAN1_MB29_DATA3() bfin_read16(CAN1_MB29_DATA3)
1227#define bfin_write_CAN1_MB29_DATA3(val) bfin_write16(CAN1_MB29_DATA3, val)
1228#define bfin_read_CAN1_MB29_LENGTH() bfin_read16(CAN1_MB29_LENGTH)
1229#define bfin_write_CAN1_MB29_LENGTH(val) bfin_write16(CAN1_MB29_LENGTH, val)
1230#define bfin_read_CAN1_MB29_TIMESTAMP() bfin_read16(CAN1_MB29_TIMESTAMP)
1231#define bfin_write_CAN1_MB29_TIMESTAMP(val) bfin_write16(CAN1_MB29_TIMESTAMP, val)
1232#define bfin_read_CAN1_MB29_ID0() bfin_read16(CAN1_MB29_ID0)
1233#define bfin_write_CAN1_MB29_ID0(val) bfin_write16(CAN1_MB29_ID0, val)
1234#define bfin_read_CAN1_MB29_ID1() bfin_read16(CAN1_MB29_ID1)
1235#define bfin_write_CAN1_MB29_ID1(val) bfin_write16(CAN1_MB29_ID1, val)
1236#define bfin_read_CAN1_MB30_DATA0() bfin_read16(CAN1_MB30_DATA0)
1237#define bfin_write_CAN1_MB30_DATA0(val) bfin_write16(CAN1_MB30_DATA0, val)
1238#define bfin_read_CAN1_MB30_DATA1() bfin_read16(CAN1_MB30_DATA1)
1239#define bfin_write_CAN1_MB30_DATA1(val) bfin_write16(CAN1_MB30_DATA1, val)
1240#define bfin_read_CAN1_MB30_DATA2() bfin_read16(CAN1_MB30_DATA2)
1241#define bfin_write_CAN1_MB30_DATA2(val) bfin_write16(CAN1_MB30_DATA2, val)
1242#define bfin_read_CAN1_MB30_DATA3() bfin_read16(CAN1_MB30_DATA3)
1243#define bfin_write_CAN1_MB30_DATA3(val) bfin_write16(CAN1_MB30_DATA3, val)
1244#define bfin_read_CAN1_MB30_LENGTH() bfin_read16(CAN1_MB30_LENGTH)
1245#define bfin_write_CAN1_MB30_LENGTH(val) bfin_write16(CAN1_MB30_LENGTH, val)
1246#define bfin_read_CAN1_MB30_TIMESTAMP() bfin_read16(CAN1_MB30_TIMESTAMP)
1247#define bfin_write_CAN1_MB30_TIMESTAMP(val) bfin_write16(CAN1_MB30_TIMESTAMP, val)
1248#define bfin_read_CAN1_MB30_ID0() bfin_read16(CAN1_MB30_ID0)
1249#define bfin_write_CAN1_MB30_ID0(val) bfin_write16(CAN1_MB30_ID0, val)
1250#define bfin_read_CAN1_MB30_ID1() bfin_read16(CAN1_MB30_ID1)
1251#define bfin_write_CAN1_MB30_ID1(val) bfin_write16(CAN1_MB30_ID1, val)
1252#define bfin_read_CAN1_MB31_DATA0() bfin_read16(CAN1_MB31_DATA0)
1253#define bfin_write_CAN1_MB31_DATA0(val) bfin_write16(CAN1_MB31_DATA0, val)
1254#define bfin_read_CAN1_MB31_DATA1() bfin_read16(CAN1_MB31_DATA1)
1255#define bfin_write_CAN1_MB31_DATA1(val) bfin_write16(CAN1_MB31_DATA1, val)
1256#define bfin_read_CAN1_MB31_DATA2() bfin_read16(CAN1_MB31_DATA2)
1257#define bfin_write_CAN1_MB31_DATA2(val) bfin_write16(CAN1_MB31_DATA2, val)
1258#define bfin_read_CAN1_MB31_DATA3() bfin_read16(CAN1_MB31_DATA3)
1259#define bfin_write_CAN1_MB31_DATA3(val) bfin_write16(CAN1_MB31_DATA3, val)
1260#define bfin_read_CAN1_MB31_LENGTH() bfin_read16(CAN1_MB31_LENGTH)
1261#define bfin_write_CAN1_MB31_LENGTH(val) bfin_write16(CAN1_MB31_LENGTH, val)
1262#define bfin_read_CAN1_MB31_TIMESTAMP() bfin_read16(CAN1_MB31_TIMESTAMP)
1263#define bfin_write_CAN1_MB31_TIMESTAMP(val) bfin_write16(CAN1_MB31_TIMESTAMP, val)
1264#define bfin_read_CAN1_MB31_ID0() bfin_read16(CAN1_MB31_ID0)
1265#define bfin_write_CAN1_MB31_ID0(val) bfin_write16(CAN1_MB31_ID0, val)
1266#define bfin_read_CAN1_MB31_ID1() bfin_read16(CAN1_MB31_ID1)
1267#define bfin_write_CAN1_MB31_ID1(val) bfin_write16(CAN1_MB31_ID1, val)
1268
1269/* ATAPI Registers */
1270
1271#define bfin_read_ATAPI_CONTROL() bfin_read16(ATAPI_CONTROL)
1272#define bfin_write_ATAPI_CONTROL(val) bfin_write16(ATAPI_CONTROL, val)
1273#define bfin_read_ATAPI_STATUS() bfin_read16(ATAPI_STATUS)
1274#define bfin_write_ATAPI_STATUS(val) bfin_write16(ATAPI_STATUS, val)
1275#define bfin_read_ATAPI_DEV_ADDR() bfin_read16(ATAPI_DEV_ADDR)
1276#define bfin_write_ATAPI_DEV_ADDR(val) bfin_write16(ATAPI_DEV_ADDR, val)
1277#define bfin_read_ATAPI_DEV_TXBUF() bfin_read16(ATAPI_DEV_TXBUF)
1278#define bfin_write_ATAPI_DEV_TXBUF(val) bfin_write16(ATAPI_DEV_TXBUF, val)
1279#define bfin_read_ATAPI_DEV_RXBUF() bfin_read16(ATAPI_DEV_RXBUF)
1280#define bfin_write_ATAPI_DEV_RXBUF(val) bfin_write16(ATAPI_DEV_RXBUF, val)
1281#define bfin_read_ATAPI_INT_MASK() bfin_read16(ATAPI_INT_MASK)
1282#define bfin_write_ATAPI_INT_MASK(val) bfin_write16(ATAPI_INT_MASK, val)
1283#define bfin_read_ATAPI_INT_STATUS() bfin_read16(ATAPI_INT_STATUS)
1284#define bfin_write_ATAPI_INT_STATUS(val) bfin_write16(ATAPI_INT_STATUS, val)
1285#define bfin_read_ATAPI_XFER_LEN() bfin_read16(ATAPI_XFER_LEN)
1286#define bfin_write_ATAPI_XFER_LEN(val) bfin_write16(ATAPI_XFER_LEN, val)
1287#define bfin_read_ATAPI_LINE_STATUS() bfin_read16(ATAPI_LINE_STATUS)
1288#define bfin_write_ATAPI_LINE_STATUS(val) bfin_write16(ATAPI_LINE_STATUS, val)
1289#define bfin_read_ATAPI_SM_STATE() bfin_read16(ATAPI_SM_STATE)
1290#define bfin_write_ATAPI_SM_STATE(val) bfin_write16(ATAPI_SM_STATE, val)
1291#define bfin_read_ATAPI_TERMINATE() bfin_read16(ATAPI_TERMINATE)
1292#define bfin_write_ATAPI_TERMINATE(val) bfin_write16(ATAPI_TERMINATE, val)
1293#define bfin_read_ATAPI_PIO_TFRCNT() bfin_read16(ATAPI_PIO_TFRCNT)
1294#define bfin_write_ATAPI_PIO_TFRCNT(val) bfin_write16(ATAPI_PIO_TFRCNT, val)
1295#define bfin_read_ATAPI_DMA_TFRCNT() bfin_read16(ATAPI_DMA_TFRCNT)
1296#define bfin_write_ATAPI_DMA_TFRCNT(val) bfin_write16(ATAPI_DMA_TFRCNT, val)
1297#define bfin_read_ATAPI_UMAIN_TFRCNT() bfin_read16(ATAPI_UMAIN_TFRCNT)
1298#define bfin_write_ATAPI_UMAIN_TFRCNT(val) bfin_write16(ATAPI_UMAIN_TFRCNT, val)
1299#define bfin_read_ATAPI_UDMAOUT_TFRCNT() bfin_read16(ATAPI_UDMAOUT_TFRCNT)
1300#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val) bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
1301#define bfin_read_ATAPI_REG_TIM_0() bfin_read16(ATAPI_REG_TIM_0)
1302#define bfin_write_ATAPI_REG_TIM_0(val) bfin_write16(ATAPI_REG_TIM_0, val)
1303#define bfin_read_ATAPI_PIO_TIM_0() bfin_read16(ATAPI_PIO_TIM_0)
1304#define bfin_write_ATAPI_PIO_TIM_0(val) bfin_write16(ATAPI_PIO_TIM_0, val)
1305#define bfin_read_ATAPI_PIO_TIM_1() bfin_read16(ATAPI_PIO_TIM_1)
1306#define bfin_write_ATAPI_PIO_TIM_1(val) bfin_write16(ATAPI_PIO_TIM_1, val)
1307#define bfin_read_ATAPI_MULTI_TIM_0() bfin_read16(ATAPI_MULTI_TIM_0)
1308#define bfin_write_ATAPI_MULTI_TIM_0(val) bfin_write16(ATAPI_MULTI_TIM_0, val)
1309#define bfin_read_ATAPI_MULTI_TIM_1() bfin_read16(ATAPI_MULTI_TIM_1)
1310#define bfin_write_ATAPI_MULTI_TIM_1(val) bfin_write16(ATAPI_MULTI_TIM_1, val)
1311#define bfin_read_ATAPI_MULTI_TIM_2() bfin_read16(ATAPI_MULTI_TIM_2)
1312#define bfin_write_ATAPI_MULTI_TIM_2(val) bfin_write16(ATAPI_MULTI_TIM_2, val)
1313#define bfin_read_ATAPI_ULTRA_TIM_0() bfin_read16(ATAPI_ULTRA_TIM_0)
1314#define bfin_write_ATAPI_ULTRA_TIM_0(val) bfin_write16(ATAPI_ULTRA_TIM_0, val)
1315#define bfin_read_ATAPI_ULTRA_TIM_1() bfin_read16(ATAPI_ULTRA_TIM_1)
1316#define bfin_write_ATAPI_ULTRA_TIM_1(val) bfin_write16(ATAPI_ULTRA_TIM_1, val)
1317#define bfin_read_ATAPI_ULTRA_TIM_2() bfin_read16(ATAPI_ULTRA_TIM_2)
1318#define bfin_write_ATAPI_ULTRA_TIM_2(val) bfin_write16(ATAPI_ULTRA_TIM_2, val)
1319#define bfin_read_ATAPI_ULTRA_TIM_3() bfin_read16(ATAPI_ULTRA_TIM_3)
1320#define bfin_write_ATAPI_ULTRA_TIM_3(val) bfin_write16(ATAPI_ULTRA_TIM_3, val)
1321
1322/* SDH Registers */
1323
1324#define bfin_read_SDH_PWR_CTL() bfin_read16(SDH_PWR_CTL)
1325#define bfin_write_SDH_PWR_CTL(val) bfin_write16(SDH_PWR_CTL, val)
1326#define bfin_read_SDH_CLK_CTL() bfin_read16(SDH_CLK_CTL)
1327#define bfin_write_SDH_CLK_CTL(val) bfin_write16(SDH_CLK_CTL, val)
1328#define bfin_read_SDH_ARGUMENT() bfin_read32(SDH_ARGUMENT)
1329#define bfin_write_SDH_ARGUMENT(val) bfin_write32(SDH_ARGUMENT, val)
1330#define bfin_read_SDH_COMMAND() bfin_read16(SDH_COMMAND)
1331#define bfin_write_SDH_COMMAND(val) bfin_write16(SDH_COMMAND, val)
1332#define bfin_read_SDH_RESP_CMD() bfin_read16(SDH_RESP_CMD)
1333#define bfin_write_SDH_RESP_CMD(val) bfin_write16(SDH_RESP_CMD, val)
1334#define bfin_read_SDH_RESPONSE0() bfin_read32(SDH_RESPONSE0)
1335#define bfin_write_SDH_RESPONSE0(val) bfin_write32(SDH_RESPONSE0, val)
1336#define bfin_read_SDH_RESPONSE1() bfin_read32(SDH_RESPONSE1)
1337#define bfin_write_SDH_RESPONSE1(val) bfin_write32(SDH_RESPONSE1, val)
1338#define bfin_read_SDH_RESPONSE2() bfin_read32(SDH_RESPONSE2)
1339#define bfin_write_SDH_RESPONSE2(val) bfin_write32(SDH_RESPONSE2, val)
1340#define bfin_read_SDH_RESPONSE3() bfin_read32(SDH_RESPONSE3)
1341#define bfin_write_SDH_RESPONSE3(val) bfin_write32(SDH_RESPONSE3, val)
1342#define bfin_read_SDH_DATA_TIMER() bfin_read32(SDH_DATA_TIMER)
1343#define bfin_write_SDH_DATA_TIMER(val) bfin_write32(SDH_DATA_TIMER, val)
1344#define bfin_read_SDH_DATA_LGTH() bfin_read16(SDH_DATA_LGTH)
1345#define bfin_write_SDH_DATA_LGTH(val) bfin_write16(SDH_DATA_LGTH, val)
1346#define bfin_read_SDH_DATA_CTL() bfin_read16(SDH_DATA_CTL)
1347#define bfin_write_SDH_DATA_CTL(val) bfin_write16(SDH_DATA_CTL, val)
1348#define bfin_read_SDH_DATA_CNT() bfin_read16(SDH_DATA_CNT)
1349#define bfin_write_SDH_DATA_CNT(val) bfin_write16(SDH_DATA_CNT, val)
1350#define bfin_read_SDH_STATUS() bfin_read32(SDH_STATUS)
1351#define bfin_write_SDH_STATUS(val) bfin_write32(SDH_STATUS, val)
1352#define bfin_read_SDH_STATUS_CLR() bfin_read16(SDH_STATUS_CLR)
1353#define bfin_write_SDH_STATUS_CLR(val) bfin_write16(SDH_STATUS_CLR, val)
1354#define bfin_read_SDH_MASK0() bfin_read32(SDH_MASK0)
1355#define bfin_write_SDH_MASK0(val) bfin_write32(SDH_MASK0, val)
1356#define bfin_read_SDH_MASK1() bfin_read32(SDH_MASK1)
1357#define bfin_write_SDH_MASK1(val) bfin_write32(SDH_MASK1, val)
1358#define bfin_read_SDH_FIFO_CNT() bfin_read16(SDH_FIFO_CNT)
1359#define bfin_write_SDH_FIFO_CNT(val) bfin_write16(SDH_FIFO_CNT, val)
1360#define bfin_read_SDH_FIFO() bfin_read32(SDH_FIFO)
1361#define bfin_write_SDH_FIFO(val) bfin_write32(SDH_FIFO, val)
1362#define bfin_read_SDH_E_STATUS() bfin_read16(SDH_E_STATUS)
1363#define bfin_write_SDH_E_STATUS(val) bfin_write16(SDH_E_STATUS, val)
1364#define bfin_read_SDH_E_MASK() bfin_read16(SDH_E_MASK)
1365#define bfin_write_SDH_E_MASK(val) bfin_write16(SDH_E_MASK, val)
1366#define bfin_read_SDH_CFG() bfin_read16(SDH_CFG)
1367#define bfin_write_SDH_CFG(val) bfin_write16(SDH_CFG, val)
1368#define bfin_read_SDH_RD_WAIT_EN() bfin_read16(SDH_RD_WAIT_EN)
1369#define bfin_write_SDH_RD_WAIT_EN(val) bfin_write16(SDH_RD_WAIT_EN, val)
1370#define bfin_read_SDH_PID0() bfin_read16(SDH_PID0)
1371#define bfin_write_SDH_PID0(val) bfin_write16(SDH_PID0, val)
1372#define bfin_read_SDH_PID1() bfin_read16(SDH_PID1)
1373#define bfin_write_SDH_PID1(val) bfin_write16(SDH_PID1, val)
1374#define bfin_read_SDH_PID2() bfin_read16(SDH_PID2)
1375#define bfin_write_SDH_PID2(val) bfin_write16(SDH_PID2, val)
1376#define bfin_read_SDH_PID3() bfin_read16(SDH_PID3)
1377#define bfin_write_SDH_PID3(val) bfin_write16(SDH_PID3, val)
1378#define bfin_read_SDH_PID4() bfin_read16(SDH_PID4)
1379#define bfin_write_SDH_PID4(val) bfin_write16(SDH_PID4, val)
1380#define bfin_read_SDH_PID5() bfin_read16(SDH_PID5)
1381#define bfin_write_SDH_PID5(val) bfin_write16(SDH_PID5, val)
1382#define bfin_read_SDH_PID6() bfin_read16(SDH_PID6)
1383#define bfin_write_SDH_PID6(val) bfin_write16(SDH_PID6, val)
1384#define bfin_read_SDH_PID7() bfin_read16(SDH_PID7)
1385#define bfin_write_SDH_PID7(val) bfin_write16(SDH_PID7, val)
1386
1387/* HOST Port Registers */
1388
1389#define bfin_read_HOST_CONTROL() bfin_read16(HOST_CONTROL)
1390#define bfin_write_HOST_CONTROL(val) bfin_write16(HOST_CONTROL, val)
1391#define bfin_read_HOST_STATUS() bfin_read16(HOST_STATUS)
1392#define bfin_write_HOST_STATUS(val) bfin_write16(HOST_STATUS, val)
1393#define bfin_read_HOST_TIMEOUT() bfin_read16(HOST_TIMEOUT)
1394#define bfin_write_HOST_TIMEOUT(val) bfin_write16(HOST_TIMEOUT, val)
1395
1396/* USB Control Registers */
1397
1398#define bfin_read_USB_FADDR() bfin_read16(USB_FADDR)
1399#define bfin_write_USB_FADDR(val) bfin_write16(USB_FADDR, val)
1400#define bfin_read_USB_POWER() bfin_read16(USB_POWER)
1401#define bfin_write_USB_POWER(val) bfin_write16(USB_POWER, val)
1402#define bfin_read_USB_INTRTX() bfin_read16(USB_INTRTX)
1403#define bfin_write_USB_INTRTX(val) bfin_write16(USB_INTRTX, val)
1404#define bfin_read_USB_INTRRX() bfin_read16(USB_INTRRX)
1405#define bfin_write_USB_INTRRX(val) bfin_write16(USB_INTRRX, val)
1406#define bfin_read_USB_INTRTXE() bfin_read16(USB_INTRTXE)
1407#define bfin_write_USB_INTRTXE(val) bfin_write16(USB_INTRTXE, val)
1408#define bfin_read_USB_INTRRXE() bfin_read16(USB_INTRRXE)
1409#define bfin_write_USB_INTRRXE(val) bfin_write16(USB_INTRRXE, val)
1410#define bfin_read_USB_INTRUSB() bfin_read16(USB_INTRUSB)
1411#define bfin_write_USB_INTRUSB(val) bfin_write16(USB_INTRUSB, val)
1412#define bfin_read_USB_INTRUSBE() bfin_read16(USB_INTRUSBE)
1413#define bfin_write_USB_INTRUSBE(val) bfin_write16(USB_INTRUSBE, val)
1414#define bfin_read_USB_FRAME() bfin_read16(USB_FRAME)
1415#define bfin_write_USB_FRAME(val) bfin_write16(USB_FRAME, val)
1416#define bfin_read_USB_INDEX() bfin_read16(USB_INDEX)
1417#define bfin_write_USB_INDEX(val) bfin_write16(USB_INDEX, val)
1418#define bfin_read_USB_TESTMODE() bfin_read16(USB_TESTMODE)
1419#define bfin_write_USB_TESTMODE(val) bfin_write16(USB_TESTMODE, val)
1420#define bfin_read_USB_GLOBINTR() bfin_read16(USB_GLOBINTR)
1421#define bfin_write_USB_GLOBINTR(val) bfin_write16(USB_GLOBINTR, val)
1422#define bfin_read_USB_GLOBAL_CTL() bfin_read16(USB_GLOBAL_CTL)
1423#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
1424
1425/* USB Packet Control Registers */
1426
1427#define bfin_read_USB_TX_MAX_PACKET() bfin_read16(USB_TX_MAX_PACKET)
1428#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
1429#define bfin_read_USB_CSR0() bfin_read16(USB_CSR0)
1430#define bfin_write_USB_CSR0(val) bfin_write16(USB_CSR0, val)
1431#define bfin_read_USB_TXCSR() bfin_read16(USB_TXCSR)
1432#define bfin_write_USB_TXCSR(val) bfin_write16(USB_TXCSR, val)
1433#define bfin_read_USB_RX_MAX_PACKET() bfin_read16(USB_RX_MAX_PACKET)
1434#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
1435#define bfin_read_USB_RXCSR() bfin_read16(USB_RXCSR)
1436#define bfin_write_USB_RXCSR(val) bfin_write16(USB_RXCSR, val)
1437#define bfin_read_USB_COUNT0() bfin_read16(USB_COUNT0)
1438#define bfin_write_USB_COUNT0(val) bfin_write16(USB_COUNT0, val)
1439#define bfin_read_USB_RXCOUNT() bfin_read16(USB_RXCOUNT)
1440#define bfin_write_USB_RXCOUNT(val) bfin_write16(USB_RXCOUNT, val)
1441#define bfin_read_USB_TXTYPE() bfin_read16(USB_TXTYPE)
1442#define bfin_write_USB_TXTYPE(val) bfin_write16(USB_TXTYPE, val)
1443#define bfin_read_USB_NAKLIMIT0() bfin_read16(USB_NAKLIMIT0)
1444#define bfin_write_USB_NAKLIMIT0(val) bfin_write16(USB_NAKLIMIT0, val)
1445#define bfin_read_USB_TXINTERVAL() bfin_read16(USB_TXINTERVAL)
1446#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
1447#define bfin_read_USB_RXTYPE() bfin_read16(USB_RXTYPE)
1448#define bfin_write_USB_RXTYPE(val) bfin_write16(USB_RXTYPE, val)
1449#define bfin_read_USB_RXINTERVAL() bfin_read16(USB_RXINTERVAL)
1450#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
1451#define bfin_read_USB_TXCOUNT() bfin_read16(USB_TXCOUNT)
1452#define bfin_write_USB_TXCOUNT(val) bfin_write16(USB_TXCOUNT, val)
1453
1454/* USB Endbfin_read_()oint FIFO Registers */
1455
1456#define bfin_read_USB_EP0_FIFO() bfin_read16(USB_EP0_FIFO)
1457#define bfin_write_USB_EP0_FIFO(val) bfin_write16(USB_EP0_FIFO, val)
1458#define bfin_read_USB_EP1_FIFO() bfin_read16(USB_EP1_FIFO)
1459#define bfin_write_USB_EP1_FIFO(val) bfin_write16(USB_EP1_FIFO, val)
1460#define bfin_read_USB_EP2_FIFO() bfin_read16(USB_EP2_FIFO)
1461#define bfin_write_USB_EP2_FIFO(val) bfin_write16(USB_EP2_FIFO, val)
1462#define bfin_read_USB_EP3_FIFO() bfin_read16(USB_EP3_FIFO)
1463#define bfin_write_USB_EP3_FIFO(val) bfin_write16(USB_EP3_FIFO, val)
1464#define bfin_read_USB_EP4_FIFO() bfin_read16(USB_EP4_FIFO)
1465#define bfin_write_USB_EP4_FIFO(val) bfin_write16(USB_EP4_FIFO, val)
1466#define bfin_read_USB_EP5_FIFO() bfin_read16(USB_EP5_FIFO)
1467#define bfin_write_USB_EP5_FIFO(val) bfin_write16(USB_EP5_FIFO, val)
1468#define bfin_read_USB_EP6_FIFO() bfin_read16(USB_EP6_FIFO)
1469#define bfin_write_USB_EP6_FIFO(val) bfin_write16(USB_EP6_FIFO, val)
1470#define bfin_read_USB_EP7_FIFO() bfin_read16(USB_EP7_FIFO)
1471#define bfin_write_USB_EP7_FIFO(val) bfin_write16(USB_EP7_FIFO, val)
1472
1473/* USB OTG Control Registers */
1474
1475#define bfin_read_USB_OTG_DEV_CTL() bfin_read16(USB_OTG_DEV_CTL)
1476#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
1477#define bfin_read_USB_OTG_VBUS_IRQ() bfin_read16(USB_OTG_VBUS_IRQ)
1478#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
1479#define bfin_read_USB_OTG_VBUS_MASK() bfin_read16(USB_OTG_VBUS_MASK)
1480#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
1481
1482/* USB Phy Control Registers */
1483
1484#define bfin_read_USB_LINKINFO() bfin_read16(USB_LINKINFO)
1485#define bfin_write_USB_LINKINFO(val) bfin_write16(USB_LINKINFO, val)
1486#define bfin_read_USB_VPLEN() bfin_read16(USB_VPLEN)
1487#define bfin_write_USB_VPLEN(val) bfin_write16(USB_VPLEN, val)
1488#define bfin_read_USB_HS_EOF1() bfin_read16(USB_HS_EOF1)
1489#define bfin_write_USB_HS_EOF1(val) bfin_write16(USB_HS_EOF1, val)
1490#define bfin_read_USB_FS_EOF1() bfin_read16(USB_FS_EOF1)
1491#define bfin_write_USB_FS_EOF1(val) bfin_write16(USB_FS_EOF1, val)
1492#define bfin_read_USB_LS_EOF1() bfin_read16(USB_LS_EOF1)
1493#define bfin_write_USB_LS_EOF1(val) bfin_write16(USB_LS_EOF1, val)
1494
1495/* (APHY_CNTRL is for ADI usage only) */
1496
1497#define bfin_read_USB_APHY_CNTRL() bfin_read16(USB_APHY_CNTRL)
1498#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
1499
1500/* (APHY_CALIB is for ADI usage only) */
1501
1502#define bfin_read_USB_APHY_CALIB() bfin_read16(USB_APHY_CALIB)
1503#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
1504#define bfin_read_USB_APHY_CNTRL2() bfin_read16(USB_APHY_CNTRL2)
1505#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
1506
1507/* (PHY_TEST is for ADI usage only) */
1508
1509#define bfin_read_USB_PHY_TEST() bfin_read16(USB_PHY_TEST)
1510#define bfin_write_USB_PHY_TEST(val) bfin_write16(USB_PHY_TEST, val)
1511#define bfin_read_USB_PLLOSC_CTRL() bfin_read16(USB_PLLOSC_CTRL)
1512#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
1513#define bfin_read_USB_SRP_CLKDIV() bfin_read16(USB_SRP_CLKDIV)
1514#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
1515
1516/* USB Endbfin_read_()oint 0 Control Registers */
1517
1518#define bfin_read_USB_EP_NI0_TXMAXP() bfin_read16(USB_EP_NI0_TXMAXP)
1519#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
1520#define bfin_read_USB_EP_NI0_TXCSR() bfin_read16(USB_EP_NI0_TXCSR)
1521#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
1522#define bfin_read_USB_EP_NI0_RXMAXP() bfin_read16(USB_EP_NI0_RXMAXP)
1523#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
1524#define bfin_read_USB_EP_NI0_RXCSR() bfin_read16(USB_EP_NI0_RXCSR)
1525#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
1526#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
1527#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
1528#define bfin_read_USB_EP_NI0_TXTYPE() bfin_read16(USB_EP_NI0_TXTYPE)
1529#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
1530#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
1531#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
1532#define bfin_read_USB_EP_NI0_RXTYPE() bfin_read16(USB_EP_NI0_RXTYPE)
1533#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
1534#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
1535#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
1536
1537/* USB Endbfin_read_()oint 1 Control Registers */
1538
1539#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
1540#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
1541#define bfin_read_USB_EP_NI1_TXMAXP() bfin_read16(USB_EP_NI1_TXMAXP)
1542#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
1543#define bfin_read_USB_EP_NI1_TXCSR() bfin_read16(USB_EP_NI1_TXCSR)
1544#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
1545#define bfin_read_USB_EP_NI1_RXMAXP() bfin_read16(USB_EP_NI1_RXMAXP)
1546#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
1547#define bfin_read_USB_EP_NI1_RXCSR() bfin_read16(USB_EP_NI1_RXCSR)
1548#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
1549#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
1550#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
1551#define bfin_read_USB_EP_NI1_TXTYPE() bfin_read16(USB_EP_NI1_TXTYPE)
1552#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
1553#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
1554#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
1555#define bfin_read_USB_EP_NI1_RXTYPE() bfin_read16(USB_EP_NI1_RXTYPE)
1556#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
1557#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
1558#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
1559
1560/* USB Endbfin_read_()oint 2 Control Registers */
1561
1562#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
1563#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
1564#define bfin_read_USB_EP_NI2_TXMAXP() bfin_read16(USB_EP_NI2_TXMAXP)
1565#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
1566#define bfin_read_USB_EP_NI2_TXCSR() bfin_read16(USB_EP_NI2_TXCSR)
1567#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
1568#define bfin_read_USB_EP_NI2_RXMAXP() bfin_read16(USB_EP_NI2_RXMAXP)
1569#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
1570#define bfin_read_USB_EP_NI2_RXCSR() bfin_read16(USB_EP_NI2_RXCSR)
1571#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
1572#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
1573#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
1574#define bfin_read_USB_EP_NI2_TXTYPE() bfin_read16(USB_EP_NI2_TXTYPE)
1575#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
1576#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
1577#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
1578#define bfin_read_USB_EP_NI2_RXTYPE() bfin_read16(USB_EP_NI2_RXTYPE)
1579#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
1580#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
1581#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
1582
1583/* USB Endbfin_read_()oint 3 Control Registers */
1584
1585#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
1586#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
1587#define bfin_read_USB_EP_NI3_TXMAXP() bfin_read16(USB_EP_NI3_TXMAXP)
1588#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
1589#define bfin_read_USB_EP_NI3_TXCSR() bfin_read16(USB_EP_NI3_TXCSR)
1590#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
1591#define bfin_read_USB_EP_NI3_RXMAXP() bfin_read16(USB_EP_NI3_RXMAXP)
1592#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
1593#define bfin_read_USB_EP_NI3_RXCSR() bfin_read16(USB_EP_NI3_RXCSR)
1594#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
1595#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
1596#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
1597#define bfin_read_USB_EP_NI3_TXTYPE() bfin_read16(USB_EP_NI3_TXTYPE)
1598#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
1599#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
1600#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
1601#define bfin_read_USB_EP_NI3_RXTYPE() bfin_read16(USB_EP_NI3_RXTYPE)
1602#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
1603#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
1604#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
1605
1606/* USB Endbfin_read_()oint 4 Control Registers */
1607
1608#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
1609#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
1610#define bfin_read_USB_EP_NI4_TXMAXP() bfin_read16(USB_EP_NI4_TXMAXP)
1611#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
1612#define bfin_read_USB_EP_NI4_TXCSR() bfin_read16(USB_EP_NI4_TXCSR)
1613#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
1614#define bfin_read_USB_EP_NI4_RXMAXP() bfin_read16(USB_EP_NI4_RXMAXP)
1615#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
1616#define bfin_read_USB_EP_NI4_RXCSR() bfin_read16(USB_EP_NI4_RXCSR)
1617#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
1618#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
1619#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
1620#define bfin_read_USB_EP_NI4_TXTYPE() bfin_read16(USB_EP_NI4_TXTYPE)
1621#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
1622#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
1623#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
1624#define bfin_read_USB_EP_NI4_RXTYPE() bfin_read16(USB_EP_NI4_RXTYPE)
1625#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
1626#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
1627#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
1628
1629/* USB Endbfin_read_()oint 5 Control Registers */
1630
1631#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
1632#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
1633#define bfin_read_USB_EP_NI5_TXMAXP() bfin_read16(USB_EP_NI5_TXMAXP)
1634#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
1635#define bfin_read_USB_EP_NI5_TXCSR() bfin_read16(USB_EP_NI5_TXCSR)
1636#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
1637#define bfin_read_USB_EP_NI5_RXMAXP() bfin_read16(USB_EP_NI5_RXMAXP)
1638#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
1639#define bfin_read_USB_EP_NI5_RXCSR() bfin_read16(USB_EP_NI5_RXCSR)
1640#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
1641#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
1642#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
1643#define bfin_read_USB_EP_NI5_TXTYPE() bfin_read16(USB_EP_NI5_TXTYPE)
1644#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
1645#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
1646#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
1647#define bfin_read_USB_EP_NI5_RXTYPE() bfin_read16(USB_EP_NI5_RXTYPE)
1648#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
1649#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
1650#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
1651
1652/* USB Endbfin_read_()oint 6 Control Registers */
1653
1654#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
1655#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
1656#define bfin_read_USB_EP_NI6_TXMAXP() bfin_read16(USB_EP_NI6_TXMAXP)
1657#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
1658#define bfin_read_USB_EP_NI6_TXCSR() bfin_read16(USB_EP_NI6_TXCSR)
1659#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
1660#define bfin_read_USB_EP_NI6_RXMAXP() bfin_read16(USB_EP_NI6_RXMAXP)
1661#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
1662#define bfin_read_USB_EP_NI6_RXCSR() bfin_read16(USB_EP_NI6_RXCSR)
1663#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
1664#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
1665#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
1666#define bfin_read_USB_EP_NI6_TXTYPE() bfin_read16(USB_EP_NI6_TXTYPE)
1667#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
1668#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
1669#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
1670#define bfin_read_USB_EP_NI6_RXTYPE() bfin_read16(USB_EP_NI6_RXTYPE)
1671#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
1672#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
1673#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
1674
1675/* USB Endbfin_read_()oint 7 Control Registers */
1676
1677#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
1678#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
1679#define bfin_read_USB_EP_NI7_TXMAXP() bfin_read16(USB_EP_NI7_TXMAXP)
1680#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
1681#define bfin_read_USB_EP_NI7_TXCSR() bfin_read16(USB_EP_NI7_TXCSR)
1682#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
1683#define bfin_read_USB_EP_NI7_RXMAXP() bfin_read16(USB_EP_NI7_RXMAXP)
1684#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
1685#define bfin_read_USB_EP_NI7_RXCSR() bfin_read16(USB_EP_NI7_RXCSR)
1686#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
1687#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
1688#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
1689#define bfin_read_USB_EP_NI7_TXTYPE() bfin_read16(USB_EP_NI7_TXTYPE)
1690#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
1691#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
1692#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
1693#define bfin_read_USB_EP_NI7_RXTYPE() bfin_read16(USB_EP_NI7_RXTYPE)
1694#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
1695#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
1696#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
1697#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
1698#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
1699#define bfin_read_USB_DMA_INTERRUPT() bfin_read16(USB_DMA_INTERRUPT)
1700#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
1701
1702/* USB Channel 0 Config Registers */
1703
1704#define bfin_read_USB_DMA0CONTROL() bfin_read16(USB_DMA0CONTROL)
1705#define bfin_write_USB_DMA0CONTROL(val) bfin_write16(USB_DMA0CONTROL, val)
1706#define bfin_read_USB_DMA0ADDRLOW() bfin_read16(USB_DMA0ADDRLOW)
1707#define bfin_write_USB_DMA0ADDRLOW(val) bfin_write16(USB_DMA0ADDRLOW, val)
1708#define bfin_read_USB_DMA0ADDRHIGH() bfin_read16(USB_DMA0ADDRHIGH)
1709#define bfin_write_USB_DMA0ADDRHIGH(val) bfin_write16(USB_DMA0ADDRHIGH, val)
1710#define bfin_read_USB_DMA0COUNTLOW() bfin_read16(USB_DMA0COUNTLOW)
1711#define bfin_write_USB_DMA0COUNTLOW(val) bfin_write16(USB_DMA0COUNTLOW, val)
1712#define bfin_read_USB_DMA0COUNTHIGH() bfin_read16(USB_DMA0COUNTHIGH)
1713#define bfin_write_USB_DMA0COUNTHIGH(val) bfin_write16(USB_DMA0COUNTHIGH, val)
1714
1715/* USB Channel 1 Config Registers */
1716
1717#define bfin_read_USB_DMA1CONTROL() bfin_read16(USB_DMA1CONTROL)
1718#define bfin_write_USB_DMA1CONTROL(val) bfin_write16(USB_DMA1CONTROL, val)
1719#define bfin_read_USB_DMA1ADDRLOW() bfin_read16(USB_DMA1ADDRLOW)
1720#define bfin_write_USB_DMA1ADDRLOW(val) bfin_write16(USB_DMA1ADDRLOW, val)
1721#define bfin_read_USB_DMA1ADDRHIGH() bfin_read16(USB_DMA1ADDRHIGH)
1722#define bfin_write_USB_DMA1ADDRHIGH(val) bfin_write16(USB_DMA1ADDRHIGH, val)
1723#define bfin_read_USB_DMA1COUNTLOW() bfin_read16(USB_DMA1COUNTLOW)
1724#define bfin_write_USB_DMA1COUNTLOW(val) bfin_write16(USB_DMA1COUNTLOW, val)
1725#define bfin_read_USB_DMA1COUNTHIGH() bfin_read16(USB_DMA1COUNTHIGH)
1726#define bfin_write_USB_DMA1COUNTHIGH(val) bfin_write16(USB_DMA1COUNTHIGH, val)
1727
1728/* USB Channel 2 Config Registers */
1729
1730#define bfin_read_USB_DMA2CONTROL() bfin_read16(USB_DMA2CONTROL)
1731#define bfin_write_USB_DMA2CONTROL(val) bfin_write16(USB_DMA2CONTROL, val)
1732#define bfin_read_USB_DMA2ADDRLOW() bfin_read16(USB_DMA2ADDRLOW)
1733#define bfin_write_USB_DMA2ADDRLOW(val) bfin_write16(USB_DMA2ADDRLOW, val)
1734#define bfin_read_USB_DMA2ADDRHIGH() bfin_read16(USB_DMA2ADDRHIGH)
1735#define bfin_write_USB_DMA2ADDRHIGH(val) bfin_write16(USB_DMA2ADDRHIGH, val)
1736#define bfin_read_USB_DMA2COUNTLOW() bfin_read16(USB_DMA2COUNTLOW)
1737#define bfin_write_USB_DMA2COUNTLOW(val) bfin_write16(USB_DMA2COUNTLOW, val)
1738#define bfin_read_USB_DMA2COUNTHIGH() bfin_read16(USB_DMA2COUNTHIGH)
1739#define bfin_write_USB_DMA2COUNTHIGH(val) bfin_write16(USB_DMA2COUNTHIGH, val)
1740
1741/* USB Channel 3 Config Registers */
1742
1743#define bfin_read_USB_DMA3CONTROL() bfin_read16(USB_DMA3CONTROL)
1744#define bfin_write_USB_DMA3CONTROL(val) bfin_write16(USB_DMA3CONTROL, val)
1745#define bfin_read_USB_DMA3ADDRLOW() bfin_read16(USB_DMA3ADDRLOW)
1746#define bfin_write_USB_DMA3ADDRLOW(val) bfin_write16(USB_DMA3ADDRLOW, val)
1747#define bfin_read_USB_DMA3ADDRHIGH() bfin_read16(USB_DMA3ADDRHIGH)
1748#define bfin_write_USB_DMA3ADDRHIGH(val) bfin_write16(USB_DMA3ADDRHIGH, val)
1749#define bfin_read_USB_DMA3COUNTLOW() bfin_read16(USB_DMA3COUNTLOW)
1750#define bfin_write_USB_DMA3COUNTLOW(val) bfin_write16(USB_DMA3COUNTLOW, val)
1751#define bfin_read_USB_DMA3COUNTHIGH() bfin_read16(USB_DMA3COUNTHIGH)
1752#define bfin_write_USB_DMA3COUNTHIGH(val) bfin_write16(USB_DMA3COUNTHIGH, val)
1753
1754/* USB Channel 4 Config Registers */
1755
1756#define bfin_read_USB_DMA4CONTROL() bfin_read16(USB_DMA4CONTROL)
1757#define bfin_write_USB_DMA4CONTROL(val) bfin_write16(USB_DMA4CONTROL, val)
1758#define bfin_read_USB_DMA4ADDRLOW() bfin_read16(USB_DMA4ADDRLOW)
1759#define bfin_write_USB_DMA4ADDRLOW(val) bfin_write16(USB_DMA4ADDRLOW, val)
1760#define bfin_read_USB_DMA4ADDRHIGH() bfin_read16(USB_DMA4ADDRHIGH)
1761#define bfin_write_USB_DMA4ADDRHIGH(val) bfin_write16(USB_DMA4ADDRHIGH, val)
1762#define bfin_read_USB_DMA4COUNTLOW() bfin_read16(USB_DMA4COUNTLOW)
1763#define bfin_write_USB_DMA4COUNTLOW(val) bfin_write16(USB_DMA4COUNTLOW, val)
1764#define bfin_read_USB_DMA4COUNTHIGH() bfin_read16(USB_DMA4COUNTHIGH)
1765#define bfin_write_USB_DMA4COUNTHIGH(val) bfin_write16(USB_DMA4COUNTHIGH, val)
1766
1767/* USB Channel 5 Config Registers */
1768
1769#define bfin_read_USB_DMA5CONTROL() bfin_read16(USB_DMA5CONTROL)
1770#define bfin_write_USB_DMA5CONTROL(val) bfin_write16(USB_DMA5CONTROL, val)
1771#define bfin_read_USB_DMA5ADDRLOW() bfin_read16(USB_DMA5ADDRLOW)
1772#define bfin_write_USB_DMA5ADDRLOW(val) bfin_write16(USB_DMA5ADDRLOW, val)
1773#define bfin_read_USB_DMA5ADDRHIGH() bfin_read16(USB_DMA5ADDRHIGH)
1774#define bfin_write_USB_DMA5ADDRHIGH(val) bfin_write16(USB_DMA5ADDRHIGH, val)
1775#define bfin_read_USB_DMA5COUNTLOW() bfin_read16(USB_DMA5COUNTLOW)
1776#define bfin_write_USB_DMA5COUNTLOW(val) fin_write16(USB_DMA5COUNTLOW, val)
1777#define bfin_read_USB_DMA5COUNTHIGH() bfin_read16(USB_DMA5COUNTHIGH)
1778#define bfin_write_USB_DMA5COUNTHIGH(val) bfin_write16(USB_DMA5COUNTHIGH, val)
1779
1780/* USB Channel 6 Config Registers */
1781
1782#define bfin_read_USB_DMA6CONTROL() bfin_read16(USB_DMA6CONTROL)
1783#define bfin_write_USB_DMA6CONTROL(val) bfin_write16(USB_DMA6CONTROL, val)
1784#define bfin_read_USB_DMA6ADDRLOW() bfin_read16(USB_DMA6ADDRLOW)
1785#define bfin_write_USB_DMA6ADDRLOW(val) bfin_write16(USB_DMA6ADDRLOW, val)
1786#define bfin_read_USB_DMA6ADDRHIGH() bfin_read16(USB_DMA6ADDRHIGH)
1787#define bfin_write_USB_DMA6ADDRHIGH(val) bfin_write16(USB_DMA6ADDRHIGH, val)
1788#define bfin_read_USB_DMA6COUNTLOW() bfin_read16(USB_DMA6COUNTLOW)
1789#define bfin_write_USB_DMA6COUNTLOW(val) bfin_write16(USB_DMA6COUNTLOW, val)
1790#define bfin_read_USB_DMA6COUNTHIGH() bfin_read16(USB_DMA6COUNTHIGH)
1791#define bfin_write_USB_DMA6COUNTHIGH(val) bfin_write16(USB_DMA6COUNTHIGH, val)
1792
1793/* USB Channel 7 Config Registers */
1794
1795#define bfin_read_USB_DMA7CONTROL() bfin_read16(USB_DMA7CONTROL)
1796#define bfin_write_USB_DMA7CONTROL(val) bfin_write16(USB_DMA7CONTROL, val)
1797#define bfin_read_USB_DMA7ADDRLOW() bfin_read16(USB_DMA7ADDRLOW)
1798#define bfin_write_USB_DMA7ADDRLOW(val) bfin_write16(USB_DMA7ADDRLOW, val)
1799#define bfin_read_USB_DMA7ADDRHIGH() bfin_read16(USB_DMA7ADDRHIGH)
1800#define bfin_write_USB_DMA7ADDRHIGH(val) bfin_write16(USB_DMA7ADDRHIGH, val)
1801#define bfin_read_USB_DMA7COUNTLOW() bfin_read16(USB_DMA7COUNTLOW)
1802#define bfin_write_USB_DMA7COUNTLOW(val) bfin_write16(USB_DMA7COUNTLOW, val)
1803#define bfin_read_USB_DMA7COUNTHIGH() bfin_read16(USB_DMA7COUNTHIGH)
1804#define bfin_write_USB_DMA7COUNTHIGH(val) bfin_write16(USB_DMA7COUNTHIGH, val)
1805
1806/* Keybfin_read_()ad Registers */
1807
1808#define bfin_read_KPAD_CTL() bfin_read16(KPAD_CTL)
1809#define bfin_write_KPAD_CTL(val) bfin_write16(KPAD_CTL, val)
1810#define bfin_read_KPAD_PRESCALE() bfin_read16(KPAD_PRESCALE)
1811#define bfin_write_KPAD_PRESCALE(val) bfin_write16(KPAD_PRESCALE, val)
1812#define bfin_read_KPAD_MSEL() bfin_read16(KPAD_MSEL)
1813#define bfin_write_KPAD_MSEL(val) bfin_write16(KPAD_MSEL, val)
1814#define bfin_read_KPAD_ROWCOL() bfin_read16(KPAD_ROWCOL)
1815#define bfin_write_KPAD_ROWCOL(val) bfin_write16(KPAD_ROWCOL, val)
1816#define bfin_read_KPAD_STAT() bfin_read16(KPAD_STAT)
1817#define bfin_write_KPAD_STAT(val) bfin_write16(KPAD_STAT, val)
1818#define bfin_read_KPAD_SOFTEVAL() bfin_read16(KPAD_SOFTEVAL)
1819#define bfin_write_KPAD_SOFTEVAL(val) bfin_write16(KPAD_SOFTEVAL, val)
1820
1821/* Pixel Combfin_read_()ositor (PIXC) Registers */
1822
1823#define bfin_read_PIXC_CTL() bfin_read16(PIXC_CTL)
1824#define bfin_write_PIXC_CTL(val) bfin_write16(PIXC_CTL, val)
1825#define bfin_read_PIXC_PPL() bfin_read16(PIXC_PPL)
1826#define bfin_write_PIXC_PPL(val) bfin_write16(PIXC_PPL, val)
1827#define bfin_read_PIXC_LPF() bfin_read16(PIXC_LPF)
1828#define bfin_write_PIXC_LPF(val) bfin_write16(PIXC_LPF, val)
1829#define bfin_read_PIXC_AHSTART() bfin_read16(PIXC_AHSTART)
1830#define bfin_write_PIXC_AHSTART(val) bfin_write16(PIXC_AHSTART, val)
1831#define bfin_read_PIXC_AHEND() bfin_read16(PIXC_AHEND)
1832#define bfin_write_PIXC_AHEND(val) bfin_write16(PIXC_AHEND, val)
1833#define bfin_read_PIXC_AVSTART() bfin_read16(PIXC_AVSTART)
1834#define bfin_write_PIXC_AVSTART(val) bfin_write16(PIXC_AVSTART, val)
1835#define bfin_read_PIXC_AVEND() bfin_read16(PIXC_AVEND)
1836#define bfin_write_PIXC_AVEND(val) bfin_write16(PIXC_AVEND, val)
1837#define bfin_read_PIXC_ATRANSP() bfin_read16(PIXC_ATRANSP)
1838#define bfin_write_PIXC_ATRANSP(val) bfin_write16(PIXC_ATRANSP, val)
1839#define bfin_read_PIXC_BHSTART() bfin_read16(PIXC_BHSTART)
1840#define bfin_write_PIXC_BHSTART(val) bfin_write16(PIXC_BHSTART, val)
1841#define bfin_read_PIXC_BHEND() bfin_read16(PIXC_BHEND)
1842#define bfin_write_PIXC_BHEND(val) bfin_write16(PIXC_BHEND, val)
1843#define bfin_read_PIXC_BVSTART() bfin_read16(PIXC_BVSTART)
1844#define bfin_write_PIXC_BVSTART(val) bfin_write16(PIXC_BVSTART, val)
1845#define bfin_read_PIXC_BVEND() bfin_read16(PIXC_BVEND)
1846#define bfin_write_PIXC_BVEND(val) bfin_write16(PIXC_BVEND, val)
1847#define bfin_read_PIXC_BTRANSP() bfin_read16(PIXC_BTRANSP)
1848#define bfin_write_PIXC_BTRANSP(val) bfin_write16(PIXC_BTRANSP, val)
1849#define bfin_read_PIXC_INTRSTAT() bfin_read16(PIXC_INTRSTAT)
1850#define bfin_write_PIXC_INTRSTAT(val) bfin_write16(PIXC_INTRSTAT, val)
1851#define bfin_read_PIXC_RYCON() bfin_read32(PIXC_RYCON)
1852#define bfin_write_PIXC_RYCON(val) bfin_write32(PIXC_RYCON, val)
1853#define bfin_read_PIXC_GUCON() bfin_read32(PIXC_GUCON)
1854#define bfin_write_PIXC_GUCON(val) bfin_write32(PIXC_GUCON, val)
1855#define bfin_read_PIXC_BVCON() bfin_read32(PIXC_BVCON)
1856#define bfin_write_PIXC_BVCON(val) bfin_write32(PIXC_BVCON, val)
1857#define bfin_read_PIXC_CCBIAS() bfin_read32(PIXC_CCBIAS)
1858#define bfin_write_PIXC_CCBIAS(val) bfin_write32(PIXC_CCBIAS, val)
1859#define bfin_read_PIXC_TC() bfin_read32(PIXC_TC)
1860#define bfin_write_PIXC_TC(val) bfin_write32(PIXC_TC, val)
1861
1862/* Handshake MDMA 0 Registers */
1863
1864#define bfin_read_HMDMA0_CONTROL() bfin_read16(HMDMA0_CONTROL)
1865#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
1866#define bfin_read_HMDMA0_ECINIT() bfin_read16(HMDMA0_ECINIT)
1867#define bfin_write_HMDMA0_ECINIT(val) bfin_write16(HMDMA0_ECINIT, val)
1868#define bfin_read_HMDMA0_BCINIT() bfin_read16(HMDMA0_BCINIT)
1869#define bfin_write_HMDMA0_BCINIT(val) bfin_write16(HMDMA0_BCINIT, val)
1870#define bfin_read_HMDMA0_ECURGENT() bfin_read16(HMDMA0_ECURGENT)
1871#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
1872#define bfin_read_HMDMA0_ECOVERFLOW() bfin_read16(HMDMA0_ECOVERFLOW)
1873#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
1874#define bfin_read_HMDMA0_ECOUNT() bfin_read16(HMDMA0_ECOUNT)
1875#define bfin_write_HMDMA0_ECOUNT(val) bfin_write16(HMDMA0_ECOUNT, val)
1876#define bfin_read_HMDMA0_BCOUNT() bfin_read16(HMDMA0_BCOUNT)
1877#define bfin_write_HMDMA0_BCOUNT(val) bfin_write16(HMDMA0_BCOUNT, val)
1878
1879/* Handshake MDMA 1 Registers */
1880
1881#define bfin_read_HMDMA1_CONTROL() bfin_read16(HMDMA1_CONTROL)
1882#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
1883#define bfin_read_HMDMA1_ECINIT() bfin_read16(HMDMA1_ECINIT)
1884#define bfin_write_HMDMA1_ECINIT(val) bfin_write16(HMDMA1_ECINIT, val)
1885#define bfin_read_HMDMA1_BCINIT() bfin_read16(HMDMA1_BCINIT)
1886#define bfin_write_HMDMA1_BCINIT(val) bfin_write16(HMDMA1_BCINIT, val)
1887#define bfin_read_HMDMA1_ECURGENT() bfin_read16(HMDMA1_ECURGENT)
1888#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
1889#define bfin_read_HMDMA1_ECOVERFLOW() bfin_read16(HMDMA1_ECOVERFLOW)
1890#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
1891#define bfin_read_HMDMA1_ECOUNT() bfin_read16(HMDMA1_ECOUNT)
1892#define bfin_write_HMDMA1_ECOUNT(val) bfin_write16(HMDMA1_ECOUNT, val)
1893#define bfin_read_HMDMA1_BCOUNT() bfin_read16(HMDMA1_BCOUNT)
1894#define bfin_write_HMDMA1_BCOUNT(val) bfin_write16(HMDMA1_BCOUNT, val)
1895
1896#endif /* _CDEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
new file mode 100644
index 000000000000..6bbcefeb3627
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
@@ -0,0 +1,2722 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/cdefBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _CDEF_BF54X_H
32#define _CDEF_BF54X_H
33
34#include <defBF54x_base.h>
35
36/* ************************************************************** */
37/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
38/* ************************************************************** */
39
40/* PLL Registers */
41
42#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
43#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
44#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
45#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
46#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
47#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
48#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
49#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
50#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
51#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
52
53/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
54
55#define bfin_read_CHIPID() bfin_read32(CHIPID)
56#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
57
58/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
59
60#define bfin_read_SWRST() bfin_read16(SWRST)
61#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
62#define bfin_read_SYSCR() bfin_read16(SYSCR)
63#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
64
65/* SIC Registers */
66
67#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
68#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
69#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
70#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
71#define bfin_read_SIC_IMASK2() bfin_read32(SIC_IMASK2)
72#define bfin_write_SIC_IMASK2(val) bfin_write32(SIC_IMASK2, val)
73#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
74#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
75#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
76#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
77#define bfin_read_SIC_ISR2() bfin_read32(SIC_ISR2)
78#define bfin_write_SIC_ISR2(val) bfin_write32(SIC_ISR2, val)
79#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
80#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
81#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
82#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
83#define bfin_read_SIC_IWR2() bfin_read32(SIC_IWR2)
84#define bfin_write_SIC_IWR2(val) bfin_write32(SIC_IWR2, val)
85#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
86#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
87#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
88#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
89#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
90#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
91#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
92#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
93#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
94#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
95#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
96#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
97#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
98#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
99#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
100#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
101#define bfin_read_SIC_IAR8() bfin_read32(SIC_IAR8)
102#define bfin_write_SIC_IAR8(val) bfin_write32(SIC_IAR8, val)
103#define bfin_read_SIC_IAR9() bfin_read32(SIC_IAR9)
104#define bfin_write_SIC_IAR9(val) bfin_write32(SIC_IAR9, val)
105#define bfin_read_SIC_IAR10() bfin_read32(SIC_IAR10)
106#define bfin_write_SIC_IAR10(val) bfin_write32(SIC_IAR10, val)
107#define bfin_read_SIC_IAR11() bfin_read32(SIC_IAR11)
108#define bfin_write_SIC_IAR11(val) bfin_write32(SIC_IAR11, val)
109
110/* Watchdog Timer Registers */
111
112#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
113#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
114#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
115#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
116#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
117#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
118
119/* RTC Registers */
120
121#define bfin_read_RTC_STAT() bfin_read32(RTC_STAT)
122#define bfin_write_RTC_STAT(val) bfin_write32(RTC_STAT, val)
123#define bfin_read_RTC_ICTL() bfin_read16(RTC_ICTL)
124#define bfin_write_RTC_ICTL(val) bfin_write16(RTC_ICTL, val)
125#define bfin_read_RTC_ISTAT() bfin_read16(RTC_ISTAT)
126#define bfin_write_RTC_ISTAT(val) bfin_write16(RTC_ISTAT, val)
127#define bfin_read_RTC_SWCNT() bfin_read16(RTC_SWCNT)
128#define bfin_write_RTC_SWCNT(val) bfin_write16(RTC_SWCNT, val)
129#define bfin_read_RTC_ALARM() bfin_read32(RTC_ALARM)
130#define bfin_write_RTC_ALARM(val) bfin_write32(RTC_ALARM, val)
131#define bfin_read_RTC_PREN() bfin_read16(RTC_PREN)
132#define bfin_write_RTC_PREN(val) bfin_write16(RTC_PREN, val)
133
134/* UART0 Registers */
135
136#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
137#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
138#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
139#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
140#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
141#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
142#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
143#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
144#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
145#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
146#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
147#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
148#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
149#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
150#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
151#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
152#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
153#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
154#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
155#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
156#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
157#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
158#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
159#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
160
161/* SPI0 Registers */
162
163#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
164#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
165#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
166#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
167#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
168#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
169#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
170#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
171#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
172#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
173#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
174#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
175#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
176#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
177
178/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
179
180/* Two Wire Interface Registers (TWI0) */
181
182#define bfin_read_TWI0_CLKDIV() bfin_read16(TWI0_CLKDIV)
183#define bfin_write_TWI0_CLKDIV(val) bfin_write16(TWI0_CLKDIV, val)
184#define bfin_read_TWI0_CONTROL() bfin_read16(TWI0_CONTROL)
185#define bfin_write_TWI0_CONTROL(val) bfin_write16(TWI0_CONTROL, val)
186#define bfin_read_TWI0_SLAVE_CTRL() bfin_read16(TWI0_SLAVE_CTRL)
187#define bfin_write_TWI0_SLAVE_CTRL(val) bfin_write16(TWI0_SLAVE_CTRL, val)
188#define bfin_read_TWI0_SLAVE_STAT() bfin_read16(TWI0_SLAVE_STAT)
189#define bfin_write_TWI0_SLAVE_STAT(val) bfin_write16(TWI0_SLAVE_STAT, val)
190#define bfin_read_TWI0_SLAVE_ADDR() bfin_read16(TWI0_SLAVE_ADDR)
191#define bfin_write_TWI0_SLAVE_ADDR(val) bfin_write16(TWI0_SLAVE_ADDR, val)
192#define bfin_read_TWI0_MASTER_CTRL() bfin_read16(TWI0_MASTER_CTRL)
193#define bfin_write_TWI0_MASTER_CTRL(val) bfin_write16(TWI0_MASTER_CTRL, val)
194#define bfin_read_TWI0_MASTER_STAT() bfin_read16(TWI0_MASTER_STAT)
195#define bfin_write_TWI0_MASTER_STAT(val) bfin_write16(TWI0_MASTER_STAT, val)
196#define bfin_read_TWI0_MASTER_ADDR() bfin_read16(TWI0_MASTER_ADDR)
197#define bfin_write_TWI0_MASTER_ADDR(val) bfin_write16(TWI0_MASTER_ADDR, val)
198#define bfin_read_TWI0_INT_STAT() bfin_read16(TWI0_INT_STAT)
199#define bfin_write_TWI0_INT_STAT(val) bfin_write16(TWI0_INT_STAT, val)
200#define bfin_read_TWI0_INT_MASK() bfin_read16(TWI0_INT_MASK)
201#define bfin_write_TWI0_INT_MASK(val) bfin_write16(TWI0_INT_MASK, val)
202#define bfin_read_TWI0_FIFO_CTRL() bfin_read16(TWI0_FIFO_CTRL)
203#define bfin_write_TWI0_FIFO_CTRL(val) bfin_write16(TWI0_FIFO_CTRL, val)
204#define bfin_read_TWI0_FIFO_STAT() bfin_read16(TWI0_FIFO_STAT)
205#define bfin_write_TWI0_FIFO_STAT(val) bfin_write16(TWI0_FIFO_STAT, val)
206#define bfin_read_TWI0_XMT_DATA8() bfin_read16(TWI0_XMT_DATA8)
207#define bfin_write_TWI0_XMT_DATA8(val) bfin_write16(TWI0_XMT_DATA8, val)
208#define bfin_read_TWI0_XMT_DATA16() bfin_read16(TWI0_XMT_DATA16)
209#define bfin_write_TWI0_XMT_DATA16(val) bfin_write16(TWI0_XMT_DATA16, val)
210#define bfin_read_TWI0_RCV_DATA8() bfin_read16(TWI0_RCV_DATA8)
211#define bfin_write_TWI0_RCV_DATA8(val) bfin_write16(TWI0_RCV_DATA8, val)
212#define bfin_read_TWI0_RCV_DATA16() bfin_read16(TWI0_RCV_DATA16)
213#define bfin_write_TWI0_RCV_DATA16(val) bfin_write16(TWI0_RCV_DATA16, val)
214
215/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
216
217/* SPORT1 Registers */
218
219#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
220#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
221#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
222#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
223#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
224#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
225#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
226#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
227#define bfin_read_SPORT1_TX() bfin_read32(SPORT1_TX)
228#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
229#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
230#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
231#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
232#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
233#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
234#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
235#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
236#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
237#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
238#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
239#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
240#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
241#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
242#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
243#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
244#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
245#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
246#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
247#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
248#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
249#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
250#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
251#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
252#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
253#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
254#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
255#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
256#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
257#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
258#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
259#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
260#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
261#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
262#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
263
264/* Asynchronous Memory Control Registers */
265
266#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
267#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
268#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
269#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
270#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
271#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
272#define bfin_read_EBIU_MBSCTL() bfin_read16(EBIU_MBSCTL)
273#define bfin_write_EBIU_MBSCTL(val) bfin_write16(EBIU_MBSCTL, val)
274#define bfin_read_EBIU_ARBSTAT() bfin_read32(EBIU_ARBSTAT)
275#define bfin_write_EBIU_ARBSTAT(val) bfin_write32(EBIU_ARBSTAT, val)
276#define bfin_read_EBIU_MODE() bfin_read32(EBIU_MODE)
277#define bfin_write_EBIU_MODE(val) bfin_write32(EBIU_MODE, val)
278#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
279#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
280
281/* DDR Memory Control Registers */
282
283#define bfin_read_EBIU_DDRCTL0() bfin_read32(EBIU_DDRCTL0)
284#define bfin_write_EBIU_DDRCTL0(val) bfin_write32(EBIU_DDRCTL0, val)
285#define bfin_read_EBIU_DDRCTL1() bfin_read32(EBIU_DDRCTL1)
286#define bfin_write_EBIU_DDRCTL1(val) bfin_write32(EBIU_DDRCTL1, val)
287#define bfin_read_EBIU_DDRCTL2() bfin_read32(EBIU_DDRCTL2)
288#define bfin_write_EBIU_DDRCTL2(val) bfin_write32(EBIU_DDRCTL2, val)
289#define bfin_read_EBIU_DDRCTL3() bfin_read32(EBIU_DDRCTL3)
290#define bfin_write_EBIU_DDRCTL3(val) bfin_write32(EBIU_DDRCTL3, val)
291#define bfin_read_EBIU_DDRQUE() bfin_read32(EBIU_DDRQUE)
292#define bfin_write_EBIU_DDRQUE(val) bfin_write32(EBIU_DDRQUE, val)
293#define bfin_read_EBIU_ERRADD() bfin_read32(EBIU_ERRADD)
294#define bfin_write_EBIU_ERRADD(val) bfin_write32(EBIU_ERRADD)
295#define bfin_read_EBIU_ERRMST() bfin_read16(EBIU_ERRMST)
296#define bfin_write_EBIU_ERRMST(val) bfin_write16(EBIU_ERRMST, val)
297#define bfin_read_EBIU_RSTCTL() bfin_read16(EBIU_RSTCTL)
298#define bfin_write_EBIU_RSTCTL(val) bfin_write16(EBIU_RSTCTL, val)
299
300/* DDR BankRead and Write Count Registers */
301
302#define bfin_read_EBIU_DDRBRC0() bfin_read32(EBIU_DDRBRC0)
303#define bfin_write_EBIU_DDRBRC0(val) bfin_write32(EBIU_DDRBRC0, val)
304#define bfin_read_EBIU_DDRBRC1() bfin_read32(EBIU_DDRBRC1)
305#define bfin_write_EBIU_DDRBRC1(val) bfin_write32(EBIU_DDRBRC1, val)
306#define bfin_read_EBIU_DDRBRC2() bfin_read32(EBIU_DDRBRC2)
307#define bfin_write_EBIU_DDRBRC2(val) bfin_write32(EBIU_DDRBRC2, val)
308#define bfin_read_EBIU_DDRBRC3() bfin_read32(EBIU_DDRBRC3)
309#define bfin_write_EBIU_DDRBRC3(val) bfin_write32(EBIU_DDRBRC3, val)
310#define bfin_read_EBIU_DDRBRC4() bfin_read32(EBIU_DDRBRC4)
311#define bfin_write_EBIU_DDRBRC4(val) bfin_write32(EBIU_DDRBRC4, val)
312#define bfin_read_EBIU_DDRBRC5() bfin_read32(EBIU_DDRBRC5)
313#define bfin_write_EBIU_DDRBRC5(val) bfin_write32(EBIU_DDRBRC5, val)
314#define bfin_read_EBIU_DDRBRC6() bfin_read32(EBIU_DDRBRC6)
315#define bfin_write_EBIU_DDRBRC6(val) bfin_write32(EBIU_DDRBRC6, val)
316#define bfin_read_EBIU_DDRBRC7() bfin_read32(EBIU_DDRBRC7)
317#define bfin_write_EBIU_DDRBRC7(val) bfin_write32(EBIU_DDRBRC7, val)
318#define bfin_read_EBIU_DDRBWC0() bfin_read32(EBIU_DDRBWC0)
319#define bfin_write_EBIU_DDRBWC0(val) bfin_write32(EBIU_DDRBWC0, val)
320#define bfin_read_EBIU_DDRBWC1() bfin_read32(EBIU_DDRBWC1)
321#define bfin_write_EBIU_DDRBWC1(val) bfin_write32(EBIU_DDRBWC1, val)
322#define bfin_read_EBIU_DDRBWC2() bfin_read32(EBIU_DDRBWC2)
323#define bfin_write_EBIU_DDRBWC2(val) bfin_write32(EBIU_DDRBWC2, val)
324#define bfin_read_EBIU_DDRBWC3() bfin_read32(EBIU_DDRBWC3)
325#define bfin_write_EBIU_DDRBWC3(val) bfin_write32(EBIU_DDRBWC3, val)
326#define bfin_read_EBIU_DDRBWC4() bfin_read32(EBIU_DDRBWC4)
327#define bfin_write_EBIU_DDRBWC4(val) bfin_write32(EBIU_DDRBWC4, val)
328#define bfin_read_EBIU_DDRBWC5() bfin_read32(EBIU_DDRBWC5)
329#define bfin_write_EBIU_DDRBWC5(val) bfin_write32(EBIU_DDRBWC5, val)
330#define bfin_read_EBIU_DDRBWC6() bfin_read32(EBIU_DDRBWC6)
331#define bfin_write_EBIU_DDRBWC6(val) bfin_write32(EBIU_DDRBWC6, val)
332#define bfin_read_EBIU_DDRBWC7() bfin_read32(EBIU_DDRBWC7)
333#define bfin_write_EBIU_DDRBWC7(val) bfin_write32(EBIU_DDRBWC7, val)
334#define bfin_read_EBIU_DDRACCT() bfin_read32(EBIU_DDRACCT)
335#define bfin_write_EBIU_DDRACCT(val) bfin_write32(EBIU_DDRACCT, val)
336#define bfin_read_EBIU_DDRTACT() bfin_read32(EBIU_DDRTACT)
337#define bfin_write_EBIU_DDRTACT(val) bfin_write32(EBIU_DDRTACT, val)
338#define bfin_read_EBIU_DDRARCT() bfin_read32(EBIU_DDRARCT)
339#define bfin_write_EBIU_DDRARCT(val) bfin_write32(EBIU_DDRARCT, val)
340#define bfin_read_EBIU_DDRGC0() bfin_read32(EBIU_DDRGC0)
341#define bfin_write_EBIU_DDRGC0(val) bfin_write32(EBIU_DDRGC0, val)
342#define bfin_read_EBIU_DDRGC1() bfin_read32(EBIU_DDRGC1)
343#define bfin_write_EBIU_DDRGC1(val) bfin_write32(EBIU_DDRGC1, val)
344#define bfin_read_EBIU_DDRGC2() bfin_read32(EBIU_DDRGC2)
345#define bfin_write_EBIU_DDRGC2(val) bfin_write32(EBIU_DDRGC2, val)
346#define bfin_read_EBIU_DDRGC3() bfin_read32(EBIU_DDRGC3)
347#define bfin_write_EBIU_DDRGC3(val) bfin_write32(EBIU_DDRGC3, val)
348#define bfin_read_EBIU_DDRMCEN() bfin_read32(EBIU_DDRMCEN)
349#define bfin_write_EBIU_DDRMCEN(val) bfin_write32(EBIU_DDRMCEN, val)
350#define bfin_read_EBIU_DDRMCCL() bfin_read32(EBIU_DDRMCCL)
351#define bfin_write_EBIU_DDRMCCL(val) bfin_write32(EBIU_DDRMCCL, val)
352
353/* DMAC0 Registers */
354
355#define bfin_read_DMAC0_TCPER() bfin_read16(DMAC0_TCPER)
356#define bfin_write_DMAC0_TCPER(val) bfin_write16(DMAC0_TCPER, val)
357#define bfin_read_DMAC0_TCCNT() bfin_read16(DMAC0_TCCNT)
358#define bfin_write_DMAC0_TCCNT(val) bfin_write16(DMAC0_TCCNT, val)
359
360/* DMA Channel 0 Registers */
361
362#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
363#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR)
364#define bfin_read_DMA0_START_ADDR() bfin_read32(DMA0_START_ADDR)
365#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR)
366#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
367#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
368#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
369#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
370#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
371#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY)
372#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
373#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
374#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
375#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY)
376#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
377#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR)
378#define bfin_read_DMA0_CURR_ADDR() bfin_read32(DMA0_CURR_ADDR)
379#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR)
380#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
381#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
382#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
383#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
384#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
385#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
386#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
387#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
388
389/* DMA Channel 1 Registers */
390
391#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
392#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR)
393#define bfin_read_DMA1_START_ADDR() bfin_read32(DMA1_START_ADDR)
394#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR)
395#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
396#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
397#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
398#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
399#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
400#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY)
401#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
402#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
403#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
404#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY)
405#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
406#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR)
407#define bfin_read_DMA1_CURR_ADDR() bfin_read32(DMA1_CURR_ADDR)
408#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR)
409#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
410#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
411#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
412#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
413#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
414#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
415#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
416#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
417
418/* DMA Channel 2 Registers */
419
420#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
421#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR)
422#define bfin_read_DMA2_START_ADDR() bfin_read32(DMA2_START_ADDR)
423#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR)
424#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
425#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
426#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
427#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
428#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
429#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY)
430#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
431#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
432#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
433#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY)
434#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
435#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR)
436#define bfin_read_DMA2_CURR_ADDR() bfin_read32(DMA2_CURR_ADDR)
437#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR)
438#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
439#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
440#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
441#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
442#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
443#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
444#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
445#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
446
447/* DMA Channel 3 Registers */
448
449#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
450#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR)
451#define bfin_read_DMA3_START_ADDR() bfin_read32(DMA3_START_ADDR)
452#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR)
453#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
454#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
455#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
456#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
457#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
458#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY)
459#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
460#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
461#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
462#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY)
463#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
464#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR)
465#define bfin_read_DMA3_CURR_ADDR() bfin_read32(DMA3_CURR_ADDR)
466#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR)
467#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
468#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
469#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
470#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
471#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
472#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
473#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
474#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
475
476/* DMA Channel 4 Registers */
477
478#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
479#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR)
480#define bfin_read_DMA4_START_ADDR() bfin_read32(DMA4_START_ADDR)
481#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR)
482#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
483#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
484#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
485#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
486#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
487#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY)
488#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
489#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
490#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
491#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY)
492#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
493#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR)
494#define bfin_read_DMA4_CURR_ADDR() bfin_read32(DMA4_CURR_ADDR)
495#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR)
496#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
497#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
498#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
499#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
500#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
501#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
502#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
503#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
504
505/* DMA Channel 5 Registers */
506
507#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
508#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR)
509#define bfin_read_DMA5_START_ADDR() bfin_read32(DMA5_START_ADDR)
510#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR)
511#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
512#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
513#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
514#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
515#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
516#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY)
517#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
518#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
519#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
520#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY)
521#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
522#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR)
523#define bfin_read_DMA5_CURR_ADDR() bfin_read32(DMA5_CURR_ADDR)
524#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR)
525#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
526#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
527#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
528#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
529#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
530#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
531#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
532#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
533
534/* DMA Channel 6 Registers */
535
536#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
537#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR)
538#define bfin_read_DMA6_START_ADDR() bfin_read32(DMA6_START_ADDR)
539#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR)
540#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
541#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
542#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
543#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
544#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
545#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY)
546#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
547#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
548#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
549#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY)
550#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
551#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR)
552#define bfin_read_DMA6_CURR_ADDR() bfin_read32(DMA6_CURR_ADDR)
553#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR)
554#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
555#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
556#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
557#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
558#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
559#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
560#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
561#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
562
563/* DMA Channel 7 Registers */
564
565#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
566#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR)
567#define bfin_read_DMA7_START_ADDR() bfin_read32(DMA7_START_ADDR)
568#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR)
569#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
570#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
571#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
572#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
573#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
574#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY)
575#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
576#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
577#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
578#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY)
579#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
580#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR)
581#define bfin_read_DMA7_CURR_ADDR() bfin_read32(DMA7_CURR_ADDR)
582#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR)
583#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
584#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
585#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
586#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
587#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
588#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
589#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
590#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
591
592/* DMA Channel 8 Registers */
593
594#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_read32(DMA8_NEXT_DESC_PTR)
595#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_write32(DMA8_NEXT_DESC_PTR)
596#define bfin_read_DMA8_START_ADDR() bfin_read32(DMA8_START_ADDR)
597#define bfin_write_DMA8_START_ADDR(val) bfin_write32(DMA8_START_ADDR)
598#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
599#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
600#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
601#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
602#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
603#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY)
604#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
605#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
606#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
607#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY)
608#define bfin_read_DMA8_CURR_DESC_PTR() bfin_read32(DMA8_CURR_DESC_PTR)
609#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_write32(DMA8_CURR_DESC_PTR)
610#define bfin_read_DMA8_CURR_ADDR() bfin_read32(DMA8_CURR_ADDR)
611#define bfin_write_DMA8_CURR_ADDR(val) bfin_write32(DMA8_CURR_ADDR)
612#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
613#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
614#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
615#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
616#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
617#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
618#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
619#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
620
621/* DMA Channel 9 Registers */
622
623#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_read32(DMA9_NEXT_DESC_PTR)
624#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_write32(DMA9_NEXT_DESC_PTR)
625#define bfin_read_DMA9_START_ADDR() bfin_read32(DMA9_START_ADDR)
626#define bfin_write_DMA9_START_ADDR(val) bfin_write32(DMA9_START_ADDR)
627#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
628#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
629#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
630#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
631#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
632#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY)
633#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
634#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
635#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
636#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY)
637#define bfin_read_DMA9_CURR_DESC_PTR() bfin_read32(DMA9_CURR_DESC_PTR)
638#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_write32(DMA9_CURR_DESC_PTR)
639#define bfin_read_DMA9_CURR_ADDR() bfin_read32(DMA9_CURR_ADDR)
640#define bfin_write_DMA9_CURR_ADDR(val) bfin_write32(DMA9_CURR_ADDR)
641#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
642#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
643#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
644#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
645#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
646#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
647#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
648#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
649
650/* DMA Channel 10 Registers */
651
652#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_read32(DMA10_NEXT_DESC_PTR)
653#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_write32(DMA10_NEXT_DESC_PTR)
654#define bfin_read_DMA10_START_ADDR() bfin_read32(DMA10_START_ADDR)
655#define bfin_write_DMA10_START_ADDR(val) bfin_write32(DMA10_START_ADDR)
656#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
657#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
658#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
659#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
660#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
661#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY)
662#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
663#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
664#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
665#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY)
666#define bfin_read_DMA10_CURR_DESC_PTR() bfin_read32(DMA10_CURR_DESC_PTR)
667#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_write32(DMA10_CURR_DESC_PTR)
668#define bfin_read_DMA10_CURR_ADDR() bfin_read32(DMA10_CURR_ADDR)
669#define bfin_write_DMA10_CURR_ADDR(val) bfin_write32(DMA10_CURR_ADDR)
670#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
671#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
672#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
673#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
674#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
675#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
676#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
677#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
678
679/* DMA Channel 11 Registers */
680
681#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_read32(DMA11_NEXT_DESC_PTR)
682#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_write32(DMA11_NEXT_DESC_PTR)
683#define bfin_read_DMA11_START_ADDR() bfin_read32(DMA11_START_ADDR)
684#define bfin_write_DMA11_START_ADDR(val) bfin_write32(DMA11_START_ADDR)
685#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
686#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
687#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
688#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
689#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
690#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY)
691#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
692#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
693#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
694#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY)
695#define bfin_read_DMA11_CURR_DESC_PTR() bfin_read32(DMA11_CURR_DESC_PTR)
696#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_write32(DMA11_CURR_DESC_PTR)
697#define bfin_read_DMA11_CURR_ADDR() bfin_read32(DMA11_CURR_ADDR)
698#define bfin_write_DMA11_CURR_ADDR(val) bfin_write32(DMA11_CURR_ADDR)
699#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
700#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
701#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
702#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
703#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
704#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
705#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
706#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
707
708/* MDMA Stream 0 Registers */
709
710#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
711#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR)
712#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
713#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR)
714#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
715#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
716#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
717#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
718#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
719#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY)
720#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
721#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
722#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
723#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY)
724#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
725#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR)
726#define bfin_read_MDMA_D0_CURR_ADDR() bfin_read32(MDMA_D0_CURR_ADDR)
727#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR)
728#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
729#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
730#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
731#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
732#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
733#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
734#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
735#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
736#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
737#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR)
738#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
739#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR)
740#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
741#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
742#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
743#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
744#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
745#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY)
746#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
747#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
748#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
749#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY)
750#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
751#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR)
752#define bfin_read_MDMA_S0_CURR_ADDR() bfin_read32(MDMA_S0_CURR_ADDR)
753#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR)
754#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
755#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
756#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
757#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
758#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
759#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
760#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
761#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
762
763/* MDMA Stream 1 Registers */
764
765#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
766#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR)
767#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
768#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR)
769#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
770#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
771#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
772#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
773#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
774#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY)
775#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
776#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
777#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
778#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY)
779#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
780#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR)
781#define bfin_read_MDMA_D1_CURR_ADDR() bfin_read32(MDMA_D1_CURR_ADDR)
782#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR)
783#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
784#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
785#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
786#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
787#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
788#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
789#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
790#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
791#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
792#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR)
793#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
794#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR)
795#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
796#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
797#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
798#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
799#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
800#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY)
801#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
802#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
803#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
804#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY)
805#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
806#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR)
807#define bfin_read_MDMA_S1_CURR_ADDR() bfin_read32(MDMA_S1_CURR_ADDR)
808#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR)
809#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
810#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
811#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
812#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
813#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
814#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
815#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
816#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
817
818/* EPPI1 Registers */
819
820#define bfin_read_EPPI1_STATUS() bfin_read16(EPPI1_STATUS)
821#define bfin_write_EPPI1_STATUS(val) bfin_write16(EPPI1_STATUS, val)
822#define bfin_read_EPPI1_HCOUNT() bfin_read16(EPPI1_HCOUNT)
823#define bfin_write_EPPI1_HCOUNT(val) bfin_write16(EPPI1_HCOUNT, val)
824#define bfin_read_EPPI1_HDELAY() bfin_read16(EPPI1_HDELAY)
825#define bfin_write_EPPI1_HDELAY(val) bfin_write16(EPPI1_HDELAY, val)
826#define bfin_read_EPPI1_VCOUNT() bfin_read16(EPPI1_VCOUNT)
827#define bfin_write_EPPI1_VCOUNT(val) bfin_write16(EPPI1_VCOUNT, val)
828#define bfin_read_EPPI1_VDELAY() bfin_read16(EPPI1_VDELAY)
829#define bfin_write_EPPI1_VDELAY(val) bfin_write16(EPPI1_VDELAY, val)
830#define bfin_read_EPPI1_FRAME() bfin_read16(EPPI1_FRAME)
831#define bfin_write_EPPI1_FRAME(val) bfin_write16(EPPI1_FRAME, val)
832#define bfin_read_EPPI1_LINE() bfin_read16(EPPI1_LINE)
833#define bfin_write_EPPI1_LINE(val) bfin_write16(EPPI1_LINE, val)
834#define bfin_read_EPPI1_CLKDIV() bfin_read16(EPPI1_CLKDIV)
835#define bfin_write_EPPI1_CLKDIV(val) bfin_write16(EPPI1_CLKDIV, val)
836#define bfin_read_EPPI1_CONTROL() bfin_read32(EPPI1_CONTROL)
837#define bfin_write_EPPI1_CONTROL(val) bfin_write32(EPPI1_CONTROL, val)
838#define bfin_read_EPPI1_FS1W_HBL() bfin_read32(EPPI1_FS1W_HBL)
839#define bfin_write_EPPI1_FS1W_HBL(val) bfin_write32(EPPI1_FS1W_HBL, val)
840#define bfin_read_EPPI1_FS1P_AVPL() bfin_read32(EPPI1_FS1P_AVPL)
841#define bfin_write_EPPI1_FS1P_AVPL(val) bfin_write32(EPPI1_FS1P_AVPL, val)
842#define bfin_read_EPPI1_FS2W_LVB() bfin_read32(EPPI1_FS2W_LVB)
843#define bfin_write_EPPI1_FS2W_LVB(val) bfin_write32(EPPI1_FS2W_LVB, val)
844#define bfin_read_EPPI1_FS2P_LAVF() bfin_read32(EPPI1_FS2P_LAVF)
845#define bfin_write_EPPI1_FS2P_LAVF(val) bfin_write32(EPPI1_FS2P_LAVF, val)
846#define bfin_read_EPPI1_CLIP() bfin_read32(EPPI1_CLIP)
847#define bfin_write_EPPI1_CLIP(val) bfin_write32(EPPI1_CLIP, val)
848
849/* Port Interrubfin_read_()t 0 Registers (32-bit) */
850
851#define bfin_read_PINT0_MASK_SET() bfin_read32(PINT0_MASK_SET)
852#define bfin_write_PINT0_MASK_SET(val) bfin_write32(PINT0_MASK_SET, val)
853#define bfin_read_PINT0_MASK_CLEAR() bfin_read32(PINT0_MASK_CLEAR)
854#define bfin_write_PINT0_MASK_CLEAR(val) bfin_write32(PINT0_MASK_CLEAR, val)
855#define bfin_read_PINT0_REQUEST() bfin_read32(PINT0_REQUEST)
856#define bfin_write_PINT0_REQUEST(val) bfin_write32(PINT0_REQUEST, val)
857#define bfin_read_PINT0_ASSIGN() bfin_read32(PINT0_ASSIGN)
858#define bfin_write_PINT0_ASSIGN(val) bfin_write32(PINT0_ASSIGN, val)
859#define bfin_read_PINT0_EDGE_SET() bfin_read32(PINT0_EDGE_SET)
860#define bfin_write_PINT0_EDGE_SET(val) bfin_write32(PINT0_EDGE_SET, val)
861#define bfin_read_PINT0_EDGE_CLEAR() bfin_read32(PINT0_EDGE_CLEAR)
862#define bfin_write_PINT0_EDGE_CLEAR(val) bfin_write32(PINT0_EDGE_CLEAR, val)
863#define bfin_read_PINT0_INVERT_SET() bfin_read32(PINT0_INVERT_SET)
864#define bfin_write_PINT0_INVERT_SET(val) bfin_write32(PINT0_INVERT_SET, val)
865#define bfin_read_PINT0_INVERT_CLEAR() bfin_read32(PINT0_INVERT_CLEAR)
866#define bfin_write_PINT0_INVERT_CLEAR(val) bfin_write32(PINT0_INVERT_CLEAR, val)
867#define bfin_read_PINT0_PINSTATE() bfin_read32(PINT0_PINSTATE)
868#define bfin_write_PINT0_PINSTATE(val) bfin_write32(PINT0_PINSTATE, val)
869#define bfin_read_PINT0_LATCH() bfin_read32(PINT0_LATCH)
870#define bfin_write_PINT0_LATCH(val) bfin_write32(PINT0_LATCH, val)
871
872/* Port Interrubfin_read_()t 1 Registers (32-bit) */
873
874#define bfin_read_PINT1_MASK_SET() bfin_read32(PINT1_MASK_SET)
875#define bfin_write_PINT1_MASK_SET(val) bfin_write32(PINT1_MASK_SET, val)
876#define bfin_read_PINT1_MASK_CLEAR() bfin_read32(PINT1_MASK_CLEAR)
877#define bfin_write_PINT1_MASK_CLEAR(val) bfin_write32(PINT1_MASK_CLEAR, val)
878#define bfin_read_PINT1_REQUEST() bfin_read32(PINT1_REQUEST)
879#define bfin_write_PINT1_REQUEST(val) bfin_write32(PINT1_REQUEST, val)
880#define bfin_read_PINT1_ASSIGN() bfin_read32(PINT1_ASSIGN)
881#define bfin_write_PINT1_ASSIGN(val) bfin_write32(PINT1_ASSIGN, val)
882#define bfin_read_PINT1_EDGE_SET() bfin_read32(PINT1_EDGE_SET)
883#define bfin_write_PINT1_EDGE_SET(val) bfin_write32(PINT1_EDGE_SET, val)
884#define bfin_read_PINT1_EDGE_CLEAR() bfin_read32(PINT1_EDGE_CLEAR)
885#define bfin_write_PINT1_EDGE_CLEAR(val) bfin_write32(PINT1_EDGE_CLEAR, val)
886#define bfin_read_PINT1_INVERT_SET() bfin_read32(PINT1_INVERT_SET)
887#define bfin_write_PINT1_INVERT_SET(val) bfin_write32(PINT1_INVERT_SET, val)
888#define bfin_read_PINT1_INVERT_CLEAR() bfin_read32(PINT1_INVERT_CLEAR)
889#define bfin_write_PINT1_INVERT_CLEAR(val) bfin_write32(PINT1_INVERT_CLEAR, val)
890#define bfin_read_PINT1_PINSTATE() bfin_read32(PINT1_PINSTATE)
891#define bfin_write_PINT1_PINSTATE(val) bfin_write32(PINT1_PINSTATE, val)
892#define bfin_read_PINT1_LATCH() bfin_read32(PINT1_LATCH)
893#define bfin_write_PINT1_LATCH(val) bfin_write32(PINT1_LATCH, val)
894
895/* Port Interrubfin_read_()t 2 Registers (32-bit) */
896
897#define bfin_read_PINT2_MASK_SET() bfin_read32(PINT2_MASK_SET)
898#define bfin_write_PINT2_MASK_SET(val) bfin_write32(PINT2_MASK_SET, val)
899#define bfin_read_PINT2_MASK_CLEAR() bfin_read32(PINT2_MASK_CLEAR)
900#define bfin_write_PINT2_MASK_CLEAR(val) bfin_write32(PINT2_MASK_CLEAR, val)
901#define bfin_read_PINT2_REQUEST() bfin_read32(PINT2_REQUEST)
902#define bfin_write_PINT2_REQUEST(val) bfin_write32(PINT2_REQUEST, val)
903#define bfin_read_PINT2_ASSIGN() bfin_read32(PINT2_ASSIGN)
904#define bfin_write_PINT2_ASSIGN(val) bfin_write32(PINT2_ASSIGN, val)
905#define bfin_read_PINT2_EDGE_SET() bfin_read32(PINT2_EDGE_SET)
906#define bfin_write_PINT2_EDGE_SET(val) bfin_write32(PINT2_EDGE_SET, val)
907#define bfin_read_PINT2_EDGE_CLEAR() bfin_read32(PINT2_EDGE_CLEAR)
908#define bfin_write_PINT2_EDGE_CLEAR(val) bfin_write32(PINT2_EDGE_CLEAR, val)
909#define bfin_read_PINT2_INVERT_SET() bfin_read32(PINT2_INVERT_SET)
910#define bfin_write_PINT2_INVERT_SET(val) bfin_write32(PINT2_INVERT_SET, val)
911#define bfin_read_PINT2_INVERT_CLEAR() bfin_read32(PINT2_INVERT_CLEAR)
912#define bfin_write_PINT2_INVERT_CLEAR(val) bfin_write32(PINT2_INVERT_CLEAR, val)
913#define bfin_read_PINT2_PINSTATE() bfin_read32(PINT2_PINSTATE)
914#define bfin_write_PINT2_PINSTATE(val) bfin_write32(PINT2_PINSTATE, val)
915#define bfin_read_PINT2_LATCH() bfin_read32(PINT2_LATCH)
916#define bfin_write_PINT2_LATCH(val) bfin_write32(PINT2_LATCH, val)
917
918/* Port Interrubfin_read_()t 3 Registers (32-bit) */
919
920#define bfin_read_PINT3_MASK_SET() bfin_read32(PINT3_MASK_SET)
921#define bfin_write_PINT3_MASK_SET(val) bfin_write32(PINT3_MASK_SET, val)
922#define bfin_read_PINT3_MASK_CLEAR() bfin_read32(PINT3_MASK_CLEAR)
923#define bfin_write_PINT3_MASK_CLEAR(val) bfin_write32(PINT3_MASK_CLEAR, val)
924#define bfin_read_PINT3_REQUEST() bfin_read32(PINT3_REQUEST)
925#define bfin_write_PINT3_REQUEST(val) bfin_write32(PINT3_REQUEST, val)
926#define bfin_read_PINT3_ASSIGN() bfin_read32(PINT3_ASSIGN)
927#define bfin_write_PINT3_ASSIGN(val) bfin_write32(PINT3_ASSIGN, val)
928#define bfin_read_PINT3_EDGE_SET() bfin_read32(PINT3_EDGE_SET)
929#define bfin_write_PINT3_EDGE_SET(val) bfin_write32(PINT3_EDGE_SET, val)
930#define bfin_read_PINT3_EDGE_CLEAR() bfin_read32(PINT3_EDGE_CLEAR)
931#define bfin_write_PINT3_EDGE_CLEAR(val) bfin_write32(PINT3_EDGE_CLEAR, val)
932#define bfin_read_PINT3_INVERT_SET() bfin_read32(PINT3_INVERT_SET)
933#define bfin_write_PINT3_INVERT_SET(val) bfin_write32(PINT3_INVERT_SET, val)
934#define bfin_read_PINT3_INVERT_CLEAR() bfin_read32(PINT3_INVERT_CLEAR)
935#define bfin_write_PINT3_INVERT_CLEAR(val) bfin_write32(PINT3_INVERT_CLEAR, val)
936#define bfin_read_PINT3_PINSTATE() bfin_read32(PINT3_PINSTATE)
937#define bfin_write_PINT3_PINSTATE(val) bfin_write32(PINT3_PINSTATE, val)
938#define bfin_read_PINT3_LATCH() bfin_read32(PINT3_LATCH)
939#define bfin_write_PINT3_LATCH(val) bfin_write32(PINT3_LATCH, val)
940
941/* Port A Registers */
942
943#define bfin_read_PORTA_FER() bfin_read16(PORTA_FER)
944#define bfin_write_PORTA_FER(val) bfin_write16(PORTA_FER, val)
945#define bfin_read_PORTA() bfin_read16(PORTA)
946#define bfin_write_PORTA(val) bfin_write16(PORTA, val)
947#define bfin_read_PORTA_SET() bfin_read16(PORTA_SET)
948#define bfin_write_PORTA_SET(val) bfin_write16(PORTA_SET, val)
949#define bfin_read_PORTA_CLEAR() bfin_read16(PORTA_CLEAR)
950#define bfin_write_PORTA_CLEAR(val) bfin_write16(PORTA_CLEAR, val)
951#define bfin_read_PORTA_DIR_SET() bfin_read16(PORTA_DIR_SET)
952#define bfin_write_PORTA_DIR_SET(val) bfin_write16(PORTA_DIR_SET, val)
953#define bfin_read_PORTA_DIR_CLEAR() bfin_read16(PORTA_DIR_CLEAR)
954#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
955#define bfin_read_PORTA_INEN() bfin_read16(PORTA_INEN)
956#define bfin_write_PORTA_INEN(val) bfin_write16(PORTA_INEN, val)
957#define bfin_read_PORTA_MUX() bfin_read32(PORTA_MUX)
958#define bfin_write_PORTA_MUX(val) bfin_write32(PORTA_MUX, val)
959
960/* Port B Registers */
961
962#define bfin_read_PORTB_FER() bfin_read16(PORTB_FER)
963#define bfin_write_PORTB_FER(val) bfin_write16(PORTB_FER, val)
964#define bfin_read_PORTB() bfin_read16(PORTB)
965#define bfin_write_PORTB(val) bfin_write16(PORTB, val)
966#define bfin_read_PORTB_SET() bfin_read16(PORTB_SET)
967#define bfin_write_PORTB_SET(val) bfin_write16(PORTB_SET, val)
968#define bfin_read_PORTB_CLEAR() bfin_read16(PORTB_CLEAR)
969#define bfin_write_PORTB_CLEAR(val) bfin_write16(PORTB_CLEAR, val)
970#define bfin_read_PORTB_DIR_SET() bfin_read16(PORTB_DIR_SET)
971#define bfin_write_PORTB_DIR_SET(val) bfin_write16(PORTB_DIR_SET, val)
972#define bfin_read_PORTB_DIR_CLEAR() bfin_read16(PORTB_DIR_CLEAR)
973#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
974#define bfin_read_PORTB_INEN() bfin_read16(PORTB_INEN)
975#define bfin_write_PORTB_INEN(val) bfin_write16(PORTB_INEN, val)
976#define bfin_read_PORTB_MUX() bfin_read32(PORTB_MUX)
977#define bfin_write_PORTB_MUX(val) bfin_write32(PORTB_MUX, val)
978
979/* Port C Registers */
980
981#define bfin_read_PORTC_FER() bfin_read16(PORTC_FER)
982#define bfin_write_PORTC_FER(val) bfin_write16(PORTC_FER, val)
983#define bfin_read_PORTC() bfin_read16(PORTC)
984#define bfin_write_PORTC(val) bfin_write16(PORTC, val)
985#define bfin_read_PORTC_SET() bfin_read16(PORTC_SET)
986#define bfin_write_PORTC_SET(val) bfin_write16(PORTC_SET, val)
987#define bfin_read_PORTC_CLEAR() bfin_read16(PORTC_CLEAR)
988#define bfin_write_PORTC_CLEAR(val) bfin_write16(PORTC_CLEAR, val)
989#define bfin_read_PORTC_DIR_SET() bfin_read16(PORTC_DIR_SET)
990#define bfin_write_PORTC_DIR_SET(val) bfin_write16(PORTC_DIR_SET, val)
991#define bfin_read_PORTC_DIR_CLEAR() bfin_read16(PORTC_DIR_CLEAR)
992#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
993#define bfin_read_PORTC_INEN() bfin_read16(PORTC_INEN)
994#define bfin_write_PORTC_INEN(val) bfin_write16(PORTC_INEN, val)
995#define bfin_read_PORTC_MUX() bfin_read32(PORTC_MUX)
996#define bfin_write_PORTC_MUX(val) bfin_write32(PORTC_MUX, val)
997
998/* Port D Registers */
999
1000#define bfin_read_PORTD_FER() bfin_read16(PORTD_FER)
1001#define bfin_write_PORTD_FER(val) bfin_write16(PORTD_FER, val)
1002#define bfin_read_PORTD() bfin_read16(PORTD)
1003#define bfin_write_PORTD(val) bfin_write16(PORTD, val)
1004#define bfin_read_PORTD_SET() bfin_read16(PORTD_SET)
1005#define bfin_write_PORTD_SET(val) bfin_write16(PORTD_SET, val)
1006#define bfin_read_PORTD_CLEAR() bfin_read16(PORTD_CLEAR)
1007#define bfin_write_PORTD_CLEAR(val) bfin_write16(PORTD_CLEAR, val)
1008#define bfin_read_PORTD_DIR_SET() bfin_read16(PORTD_DIR_SET)
1009#define bfin_write_PORTD_DIR_SET(val) bfin_write16(PORTD_DIR_SET, val)
1010#define bfin_read_PORTD_DIR_CLEAR() bfin_read16(PORTD_DIR_CLEAR)
1011#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
1012#define bfin_read_PORTD_INEN() bfin_read16(PORTD_INEN)
1013#define bfin_write_PORTD_INEN(val) bfin_write16(PORTD_INEN, val)
1014#define bfin_read_PORTD_MUX() bfin_read32(PORTD_MUX)
1015#define bfin_write_PORTD_MUX(val) bfin_write32(PORTD_MUX, val)
1016
1017/* Port E Registers */
1018
1019#define bfin_read_PORTE_FER() bfin_read16(PORTE_FER)
1020#define bfin_write_PORTE_FER(val) bfin_write16(PORTE_FER, val)
1021#define bfin_read_PORTE() bfin_read16(PORTE)
1022#define bfin_write_PORTE(val) bfin_write16(PORTE, val)
1023#define bfin_read_PORTE_SET() bfin_read16(PORTE_SET)
1024#define bfin_write_PORTE_SET(val) bfin_write16(PORTE_SET, val)
1025#define bfin_read_PORTE_CLEAR() bfin_read16(PORTE_CLEAR)
1026#define bfin_write_PORTE_CLEAR(val) bfin_write16(PORTE_CLEAR, val)
1027#define bfin_read_PORTE_DIR_SET() bfin_read16(PORTE_DIR_SET)
1028#define bfin_write_PORTE_DIR_SET(val) bfin_write16(PORTE_DIR_SET, val)
1029#define bfin_read_PORTE_DIR_CLEAR() bfin_read16(PORTE_DIR_CLEAR)
1030#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
1031#define bfin_read_PORTE_INEN() bfin_read16(PORTE_INEN)
1032#define bfin_write_PORTE_INEN(val) bfin_write16(PORTE_INEN, val)
1033#define bfin_read_PORTE_MUX() bfin_read32(PORTE_MUX)
1034#define bfin_write_PORTE_MUX(val) bfin_write32(PORTE_MUX, val)
1035
1036/* Port F Registers */
1037
1038#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
1039#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
1040#define bfin_read_PORTF() bfin_read16(PORTF)
1041#define bfin_write_PORTF(val) bfin_write16(PORTF, val)
1042#define bfin_read_PORTF_SET() bfin_read16(PORTF_SET)
1043#define bfin_write_PORTF_SET(val) bfin_write16(PORTF_SET, val)
1044#define bfin_read_PORTF_CLEAR() bfin_read16(PORTF_CLEAR)
1045#define bfin_write_PORTF_CLEAR(val) bfin_write16(PORTF_CLEAR, val)
1046#define bfin_read_PORTF_DIR_SET() bfin_read16(PORTF_DIR_SET)
1047#define bfin_write_PORTF_DIR_SET(val) bfin_write16(PORTF_DIR_SET, val)
1048#define bfin_read_PORTF_DIR_CLEAR() bfin_read16(PORTF_DIR_CLEAR)
1049#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
1050#define bfin_read_PORTF_INEN() bfin_read16(PORTF_INEN)
1051#define bfin_write_PORTF_INEN(val) bfin_write16(PORTF_INEN, val)
1052#define bfin_read_PORTF_MUX() bfin_read32(PORTF_MUX)
1053#define bfin_write_PORTF_MUX(val) bfin_write32(PORTF_MUX, val)
1054
1055/* Port G Registers */
1056
1057#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
1058#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
1059#define bfin_read_PORTG() bfin_read16(PORTG)
1060#define bfin_write_PORTG(val) bfin_write16(PORTG, val)
1061#define bfin_read_PORTG_SET() bfin_read16(PORTG_SET)
1062#define bfin_write_PORTG_SET(val) bfin_write16(PORTG_SET, val)
1063#define bfin_read_PORTG_CLEAR() bfin_read16(PORTG_CLEAR)
1064#define bfin_write_PORTG_CLEAR(val) bfin_write16(PORTG_CLEAR, val)
1065#define bfin_read_PORTG_DIR_SET() bfin_read16(PORTG_DIR_SET)
1066#define bfin_write_PORTG_DIR_SET(val) bfin_write16(PORTG_DIR_SET, val)
1067#define bfin_read_PORTG_DIR_CLEAR() bfin_read16(PORTG_DIR_CLEAR)
1068#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
1069#define bfin_read_PORTG_INEN() bfin_read16(PORTG_INEN)
1070#define bfin_write_PORTG_INEN(val) bfin_write16(PORTG_INEN, val)
1071#define bfin_read_PORTG_MUX() bfin_read32(PORTG_MUX)
1072#define bfin_write_PORTG_MUX(val) bfin_write32(PORTG_MUX, val)
1073
1074/* Port H Registers */
1075
1076#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
1077#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
1078#define bfin_read_PORTH() bfin_read16(PORTH)
1079#define bfin_write_PORTH(val) bfin_write16(PORTH, val)
1080#define bfin_read_PORTH_SET() bfin_read16(PORTH_SET)
1081#define bfin_write_PORTH_SET(val) bfin_write16(PORTH_SET, val)
1082#define bfin_read_PORTH_CLEAR() bfin_read16(PORTH_CLEAR)
1083#define bfin_write_PORTH_CLEAR(val) bfin_write16(PORTH_CLEAR, val)
1084#define bfin_read_PORTH_DIR_SET() bfin_read16(PORTH_DIR_SET)
1085#define bfin_write_PORTH_DIR_SET(val) bfin_write16(PORTH_DIR_SET, val)
1086#define bfin_read_PORTH_DIR_CLEAR() bfin_read16(PORTH_DIR_CLEAR)
1087#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
1088#define bfin_read_PORTH_INEN() bfin_read16(PORTH_INEN)
1089#define bfin_write_PORTH_INEN(val) bfin_write16(PORTH_INEN, val)
1090#define bfin_read_PORTH_MUX() bfin_read32(PORTH_MUX)
1091#define bfin_write_PORTH_MUX(val) bfin_write32(PORTH_MUX, val)
1092
1093/* Port I Registers */
1094
1095#define bfin_read_PORTI_FER() bfin_read16(PORTI_FER)
1096#define bfin_write_PORTI_FER(val) bfin_write16(PORTI_FER, val)
1097#define bfin_read_PORTI() bfin_read16(PORTI)
1098#define bfin_write_PORTI(val) bfin_write16(PORTI, val)
1099#define bfin_read_PORTI_SET() bfin_read16(PORTI_SET)
1100#define bfin_write_PORTI_SET(val) bfin_write16(PORTI_SET, val)
1101#define bfin_read_PORTI_CLEAR() bfin_read16(PORTI_CLEAR)
1102#define bfin_write_PORTI_CLEAR(val) bfin_write16(PORTI_CLEAR, val)
1103#define bfin_read_PORTI_DIR_SET() bfin_read16(PORTI_DIR_SET)
1104#define bfin_write_PORTI_DIR_SET(val) bfin_write16(PORTI_DIR_SET, val)
1105#define bfin_read_PORTI_DIR_CLEAR() bfin_read16(PORTI_DIR_CLEAR)
1106#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
1107#define bfin_read_PORTI_INEN() bfin_read16(PORTI_INEN)
1108#define bfin_write_PORTI_INEN(val) bfin_write16(PORTI_INEN, val)
1109#define bfin_read_PORTI_MUX() bfin_read32(PORTI_MUX)
1110#define bfin_write_PORTI_MUX(val) bfin_write32(PORTI_MUX, val)
1111
1112/* Port J Registers */
1113
1114#define bfin_read_PORTJ_FER() bfin_read16(PORTJ_FER)
1115#define bfin_write_PORTJ_FER(val) bfin_write16(PORTJ_FER, val)
1116#define bfin_read_PORTJ() bfin_read16(PORTJ)
1117#define bfin_write_PORTJ(val) bfin_write16(PORTJ, val)
1118#define bfin_read_PORTJ_SET() bfin_read16(PORTJ_SET)
1119#define bfin_write_PORTJ_SET(val) bfin_write16(PORTJ_SET, val)
1120#define bfin_read_PORTJ_CLEAR() bfin_read16(PORTJ_CLEAR)
1121#define bfin_write_PORTJ_CLEAR(val) bfin_write16(PORTJ_CLEAR, val)
1122#define bfin_read_PORTJ_DIR_SET() bfin_read16(PORTJ_DIR_SET)
1123#define bfin_write_PORTJ_DIR_SET(val) bfin_write16(PORTJ_DIR_SET, val)
1124#define bfin_read_PORTJ_DIR_CLEAR() bfin_read16(PORTJ_DIR_CLEAR)
1125#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
1126#define bfin_read_PORTJ_INEN() bfin_read16(PORTJ_INEN)
1127#define bfin_write_PORTJ_INEN(val) bfin_write16(PORTJ_INEN, val)
1128#define bfin_read_PORTJ_MUX() bfin_read32(PORTJ_MUX)
1129#define bfin_write_PORTJ_MUX(val) bfin_write32(PORTJ_MUX, val)
1130
1131/* PWM Timer Registers */
1132
1133#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
1134#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
1135#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
1136#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
1137#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
1138#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
1139#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
1140#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
1141#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
1142#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
1143#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
1144#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
1145#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
1146#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
1147#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
1148#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
1149#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
1150#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
1151#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
1152#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
1153#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
1154#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
1155#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
1156#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
1157#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
1158#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
1159#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
1160#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
1161#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
1162#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
1163#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
1164#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
1165#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
1166#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
1167#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
1168#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
1169#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
1170#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
1171#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
1172#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
1173#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
1174#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
1175#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
1176#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
1177#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
1178#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
1179#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
1180#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
1181#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
1182#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
1183#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
1184#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
1185#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
1186#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
1187#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
1188#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
1189#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
1190#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
1191#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
1192#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
1193#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
1194#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
1195#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
1196#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
1197
1198/* Timer Groubfin_read_() of 8 */
1199
1200#define bfin_read_TIMER_ENABLE0() bfin_read16(TIMER_ENABLE0)
1201#define bfin_write_TIMER_ENABLE0(val) bfin_write16(TIMER_ENABLE0, val)
1202#define bfin_read_TIMER_DISABLE0() bfin_read16(TIMER_DISABLE0)
1203#define bfin_write_TIMER_DISABLE0(val) bfin_write16(TIMER_DISABLE0, val)
1204#define bfin_read_TIMER_STATUS0() bfin_read32(TIMER_STATUS0)
1205#define bfin_write_TIMER_STATUS0(val) bfin_write32(TIMER_STATUS0, val)
1206
1207/* DMAC1 Registers */
1208
1209#define bfin_read_DMAC1_TCPER() bfin_read16(DMAC1_TCPER)
1210#define bfin_write_DMAC1_TCPER(val) bfin_write16(DMAC1_TCPER, val)
1211#define bfin_read_DMAC1_TCCNT() bfin_read16(DMAC1_TCCNT)
1212#define bfin_write_DMAC1_TCCNT(val) bfin_write16(DMAC1_TCCNT, val)
1213
1214/* DMA Channel 12 Registers */
1215
1216#define bfin_read_DMA12_NEXT_DESC_PTR() bfin_read32(DMA12_NEXT_DESC_PTR)
1217#define bfin_write_DMA12_NEXT_DESC_PTR(val) bfin_write32(DMA12_NEXT_DESC_PTR)
1218#define bfin_read_DMA12_START_ADDR() bfin_read32(DMA12_START_ADDR)
1219#define bfin_write_DMA12_START_ADDR(val) bfin_write32(DMA12_START_ADDR)
1220#define bfin_read_DMA12_CONFIG() bfin_read16(DMA12_CONFIG)
1221#define bfin_write_DMA12_CONFIG(val) bfin_write16(DMA12_CONFIG, val)
1222#define bfin_read_DMA12_X_COUNT() bfin_read16(DMA12_X_COUNT)
1223#define bfin_write_DMA12_X_COUNT(val) bfin_write16(DMA12_X_COUNT, val)
1224#define bfin_read_DMA12_X_MODIFY() bfin_read16(DMA12_X_MODIFY)
1225#define bfin_write_DMA12_X_MODIFY(val) bfin_write16(DMA12_X_MODIFY)
1226#define bfin_read_DMA12_Y_COUNT() bfin_read16(DMA12_Y_COUNT)
1227#define bfin_write_DMA12_Y_COUNT(val) bfin_write16(DMA12_Y_COUNT, val)
1228#define bfin_read_DMA12_Y_MODIFY() bfin_read16(DMA12_Y_MODIFY)
1229#define bfin_write_DMA12_Y_MODIFY(val) bfin_write16(DMA12_Y_MODIFY)
1230#define bfin_read_DMA12_CURR_DESC_PTR() bfin_read32(DMA12_CURR_DESC_PTR)
1231#define bfin_write_DMA12_CURR_DESC_PTR(val) bfin_write32(DMA12_CURR_DESC_PTR)
1232#define bfin_read_DMA12_CURR_ADDR() bfin_read32(DMA12_CURR_ADDR)
1233#define bfin_write_DMA12_CURR_ADDR(val) bfin_write32(DMA12_CURR_ADDR)
1234#define bfin_read_DMA12_IRQ_STATUS() bfin_read16(DMA12_IRQ_STATUS)
1235#define bfin_write_DMA12_IRQ_STATUS(val) bfin_write16(DMA12_IRQ_STATUS, val)
1236#define bfin_read_DMA12_PERIPHERAL_MAP() bfin_read16(DMA12_PERIPHERAL_MAP)
1237#define bfin_write_DMA12_PERIPHERAL_MAP(val) bfin_write16(DMA12_PERIPHERAL_MAP, val)
1238#define bfin_read_DMA12_CURR_X_COUNT() bfin_read16(DMA12_CURR_X_COUNT)
1239#define bfin_write_DMA12_CURR_X_COUNT(val) bfin_write16(DMA12_CURR_X_COUNT, val)
1240#define bfin_read_DMA12_CURR_Y_COUNT() bfin_read16(DMA12_CURR_Y_COUNT)
1241#define bfin_write_DMA12_CURR_Y_COUNT(val) bfin_write16(DMA12_CURR_Y_COUNT, val)
1242
1243/* DMA Channel 13 Registers */
1244
1245#define bfin_read_DMA13_NEXT_DESC_PTR() bfin_read32(DMA13_NEXT_DESC_PTR)
1246#define bfin_write_DMA13_NEXT_DESC_PTR(val) bfin_write32(DMA13_NEXT_DESC_PTR)
1247#define bfin_read_DMA13_START_ADDR() bfin_read32(DMA13_START_ADDR)
1248#define bfin_write_DMA13_START_ADDR(val) bfin_write32(DMA13_START_ADDR)
1249#define bfin_read_DMA13_CONFIG() bfin_read16(DMA13_CONFIG)
1250#define bfin_write_DMA13_CONFIG(val) bfin_write16(DMA13_CONFIG, val)
1251#define bfin_read_DMA13_X_COUNT() bfin_read16(DMA13_X_COUNT)
1252#define bfin_write_DMA13_X_COUNT(val) bfin_write16(DMA13_X_COUNT, val)
1253#define bfin_read_DMA13_X_MODIFY() bfin_read16(DMA13_X_MODIFY)
1254#define bfin_write_DMA13_X_MODIFY(val) bfin_write16(DMA13_X_MODIFY)
1255#define bfin_read_DMA13_Y_COUNT() bfin_read16(DMA13_Y_COUNT)
1256#define bfin_write_DMA13_Y_COUNT(val) bfin_write16(DMA13_Y_COUNT, val)
1257#define bfin_read_DMA13_Y_MODIFY() bfin_read16(DMA13_Y_MODIFY)
1258#define bfin_write_DMA13_Y_MODIFY(val) bfin_write16(DMA13_Y_MODIFY)
1259#define bfin_read_DMA13_CURR_DESC_PTR() bfin_read32(DMA13_CURR_DESC_PTR)
1260#define bfin_write_DMA13_CURR_DESC_PTR(val) bfin_write32(DMA13_CURR_DESC_PTR)
1261#define bfin_read_DMA13_CURR_ADDR() bfin_read32(DMA13_CURR_ADDR)
1262#define bfin_write_DMA13_CURR_ADDR(val) bfin_write32(DMA13_CURR_ADDR)
1263#define bfin_read_DMA13_IRQ_STATUS() bfin_read16(DMA13_IRQ_STATUS)
1264#define bfin_write_DMA13_IRQ_STATUS(val) bfin_write16(DMA13_IRQ_STATUS, val)
1265#define bfin_read_DMA13_PERIPHERAL_MAP() bfin_read16(DMA13_PERIPHERAL_MAP)
1266#define bfin_write_DMA13_PERIPHERAL_MAP(val) bfin_write16(DMA13_PERIPHERAL_MAP, val)
1267#define bfin_read_DMA13_CURR_X_COUNT() bfin_read16(DMA13_CURR_X_COUNT)
1268#define bfin_write_DMA13_CURR_X_COUNT(val) bfin_write16(DMA13_CURR_X_COUNT, val)
1269#define bfin_read_DMA13_CURR_Y_COUNT() bfin_read16(DMA13_CURR_Y_COUNT)
1270#define bfin_write_DMA13_CURR_Y_COUNT(val) bfin_write16(DMA13_CURR_Y_COUNT, val)
1271
1272/* DMA Channel 14 Registers */
1273
1274#define bfin_read_DMA14_NEXT_DESC_PTR() bfin_read32(DMA14_NEXT_DESC_PTR)
1275#define bfin_write_DMA14_NEXT_DESC_PTR(val) bfin_write32(DMA14_NEXT_DESC_PTR)
1276#define bfin_read_DMA14_START_ADDR() bfin_read32(DMA14_START_ADDR)
1277#define bfin_write_DMA14_START_ADDR(val) bfin_write32(DMA14_START_ADDR)
1278#define bfin_read_DMA14_CONFIG() bfin_read16(DMA14_CONFIG)
1279#define bfin_write_DMA14_CONFIG(val) bfin_write16(DMA14_CONFIG, val)
1280#define bfin_read_DMA14_X_COUNT() bfin_read16(DMA14_X_COUNT)
1281#define bfin_write_DMA14_X_COUNT(val) bfin_write16(DMA14_X_COUNT, val)
1282#define bfin_read_DMA14_X_MODIFY() bfin_read16(DMA14_X_MODIFY)
1283#define bfin_write_DMA14_X_MODIFY(val) bfin_write16(DMA14_X_MODIFY)
1284#define bfin_read_DMA14_Y_COUNT() bfin_read16(DMA14_Y_COUNT)
1285#define bfin_write_DMA14_Y_COUNT(val) bfin_write16(DMA14_Y_COUNT, val)
1286#define bfin_read_DMA14_Y_MODIFY() bfin_read16(DMA14_Y_MODIFY)
1287#define bfin_write_DMA14_Y_MODIFY(val) bfin_write16(DMA14_Y_MODIFY)
1288#define bfin_read_DMA14_CURR_DESC_PTR() bfin_read32(DMA14_CURR_DESC_PTR)
1289#define bfin_write_DMA14_CURR_DESC_PTR(val) bfin_write32(DMA14_CURR_DESC_PTR)
1290#define bfin_read_DMA14_CURR_ADDR() bfin_read32(DMA14_CURR_ADDR)
1291#define bfin_write_DMA14_CURR_ADDR(val) bfin_write32(DMA14_CURR_ADDR)
1292#define bfin_read_DMA14_IRQ_STATUS() bfin_read16(DMA14_IRQ_STATUS)
1293#define bfin_write_DMA14_IRQ_STATUS(val) bfin_write16(DMA14_IRQ_STATUS, val)
1294#define bfin_read_DMA14_PERIPHERAL_MAP() bfin_read16(DMA14_PERIPHERAL_MAP)
1295#define bfin_write_DMA14_PERIPHERAL_MAP(val) bfin_write16(DMA14_PERIPHERAL_MAP, val)
1296#define bfin_read_DMA14_CURR_X_COUNT() bfin_read16(DMA14_CURR_X_COUNT)
1297#define bfin_write_DMA14_CURR_X_COUNT(val) bfin_write16(DMA14_CURR_X_COUNT, val)
1298#define bfin_read_DMA14_CURR_Y_COUNT() bfin_read16(DMA14_CURR_Y_COUNT)
1299#define bfin_write_DMA14_CURR_Y_COUNT(val) bfin_write16(DMA14_CURR_Y_COUNT, val)
1300
1301/* DMA Channel 15 Registers */
1302
1303#define bfin_read_DMA15_NEXT_DESC_PTR() bfin_read32(DMA15_NEXT_DESC_PTR)
1304#define bfin_write_DMA15_NEXT_DESC_PTR(val) bfin_write32(DMA15_NEXT_DESC_PTR)
1305#define bfin_read_DMA15_START_ADDR() bfin_read32(DMA15_START_ADDR)
1306#define bfin_write_DMA15_START_ADDR(val) bfin_write32(DMA15_START_ADDR)
1307#define bfin_read_DMA15_CONFIG() bfin_read16(DMA15_CONFIG)
1308#define bfin_write_DMA15_CONFIG(val) bfin_write16(DMA15_CONFIG, val)
1309#define bfin_read_DMA15_X_COUNT() bfin_read16(DMA15_X_COUNT)
1310#define bfin_write_DMA15_X_COUNT(val) bfin_write16(DMA15_X_COUNT, val)
1311#define bfin_read_DMA15_X_MODIFY() bfin_read16(DMA15_X_MODIFY)
1312#define bfin_write_DMA15_X_MODIFY(val) bfin_write16(DMA15_X_MODIFY)
1313#define bfin_read_DMA15_Y_COUNT() bfin_read16(DMA15_Y_COUNT)
1314#define bfin_write_DMA15_Y_COUNT(val) bfin_write16(DMA15_Y_COUNT, val)
1315#define bfin_read_DMA15_Y_MODIFY() bfin_read16(DMA15_Y_MODIFY)
1316#define bfin_write_DMA15_Y_MODIFY(val) bfin_write16(DMA15_Y_MODIFY)
1317#define bfin_read_DMA15_CURR_DESC_PTR() bfin_read32(DMA15_CURR_DESC_PTR)
1318#define bfin_write_DMA15_CURR_DESC_PTR(val) bfin_write32(DMA15_CURR_DESC_PTR)
1319#define bfin_read_DMA15_CURR_ADDR() bfin_read32(DMA15_CURR_ADDR)
1320#define bfin_write_DMA15_CURR_ADDR(val) bfin_write32(DMA15_CURR_ADDR)
1321#define bfin_read_DMA15_IRQ_STATUS() bfin_read16(DMA15_IRQ_STATUS)
1322#define bfin_write_DMA15_IRQ_STATUS(val) bfin_write16(DMA15_IRQ_STATUS, val)
1323#define bfin_read_DMA15_PERIPHERAL_MAP() bfin_read16(DMA15_PERIPHERAL_MAP)
1324#define bfin_write_DMA15_PERIPHERAL_MAP(val) bfin_write16(DMA15_PERIPHERAL_MAP, val)
1325#define bfin_read_DMA15_CURR_X_COUNT() bfin_read16(DMA15_CURR_X_COUNT)
1326#define bfin_write_DMA15_CURR_X_COUNT(val) bfin_write16(DMA15_CURR_X_COUNT, val)
1327#define bfin_read_DMA15_CURR_Y_COUNT() bfin_read16(DMA15_CURR_Y_COUNT)
1328#define bfin_write_DMA15_CURR_Y_COUNT(val) bfin_write16(DMA15_CURR_Y_COUNT, val)
1329
1330/* DMA Channel 16 Registers */
1331
1332#define bfin_read_DMA16_NEXT_DESC_PTR() bfin_read32(DMA16_NEXT_DESC_PTR)
1333#define bfin_write_DMA16_NEXT_DESC_PTR(val) bfin_write32(DMA16_NEXT_DESC_PTR)
1334#define bfin_read_DMA16_START_ADDR() bfin_read32(DMA16_START_ADDR)
1335#define bfin_write_DMA16_START_ADDR(val) bfin_write32(DMA16_START_ADDR)
1336#define bfin_read_DMA16_CONFIG() bfin_read16(DMA16_CONFIG)
1337#define bfin_write_DMA16_CONFIG(val) bfin_write16(DMA16_CONFIG, val)
1338#define bfin_read_DMA16_X_COUNT() bfin_read16(DMA16_X_COUNT)
1339#define bfin_write_DMA16_X_COUNT(val) bfin_write16(DMA16_X_COUNT, val)
1340#define bfin_read_DMA16_X_MODIFY() bfin_read16(DMA16_X_MODIFY)
1341#define bfin_write_DMA16_X_MODIFY(val) bfin_write16(DMA16_X_MODIFY)
1342#define bfin_read_DMA16_Y_COUNT() bfin_read16(DMA16_Y_COUNT)
1343#define bfin_write_DMA16_Y_COUNT(val) bfin_write16(DMA16_Y_COUNT, val)
1344#define bfin_read_DMA16_Y_MODIFY() bfin_read16(DMA16_Y_MODIFY)
1345#define bfin_write_DMA16_Y_MODIFY(val) bfin_write16(DMA16_Y_MODIFY)
1346#define bfin_read_DMA16_CURR_DESC_PTR() bfin_read32(DMA16_CURR_DESC_PTR)
1347#define bfin_write_DMA16_CURR_DESC_PTR(val) bfin_write32(DMA16_CURR_DESC_PTR)
1348#define bfin_read_DMA16_CURR_ADDR() bfin_read32(DMA16_CURR_ADDR)
1349#define bfin_write_DMA16_CURR_ADDR(val) bfin_write32(DMA16_CURR_ADDR)
1350#define bfin_read_DMA16_IRQ_STATUS() bfin_read16(DMA16_IRQ_STATUS)
1351#define bfin_write_DMA16_IRQ_STATUS(val) bfin_write16(DMA16_IRQ_STATUS, val)
1352#define bfin_read_DMA16_PERIPHERAL_MAP() bfin_read16(DMA16_PERIPHERAL_MAP)
1353#define bfin_write_DMA16_PERIPHERAL_MAP(val) bfin_write16(DMA16_PERIPHERAL_MAP, val)
1354#define bfin_read_DMA16_CURR_X_COUNT() bfin_read16(DMA16_CURR_X_COUNT)
1355#define bfin_write_DMA16_CURR_X_COUNT(val) bfin_write16(DMA16_CURR_X_COUNT, val)
1356#define bfin_read_DMA16_CURR_Y_COUNT() bfin_read16(DMA16_CURR_Y_COUNT)
1357#define bfin_write_DMA16_CURR_Y_COUNT(val) bfin_write16(DMA16_CURR_Y_COUNT, val)
1358
1359/* DMA Channel 17 Registers */
1360
1361#define bfin_read_DMA17_NEXT_DESC_PTR() bfin_read32(DMA17_NEXT_DESC_PTR)
1362#define bfin_write_DMA17_NEXT_DESC_PTR(val) bfin_write32(DMA17_NEXT_DESC_PTR)
1363#define bfin_read_DMA17_START_ADDR() bfin_read32(DMA17_START_ADDR)
1364#define bfin_write_DMA17_START_ADDR(val) bfin_write32(DMA17_START_ADDR)
1365#define bfin_read_DMA17_CONFIG() bfin_read16(DMA17_CONFIG)
1366#define bfin_write_DMA17_CONFIG(val) bfin_write16(DMA17_CONFIG, val)
1367#define bfin_read_DMA17_X_COUNT() bfin_read16(DMA17_X_COUNT)
1368#define bfin_write_DMA17_X_COUNT(val) bfin_write16(DMA17_X_COUNT, val)
1369#define bfin_read_DMA17_X_MODIFY() bfin_read16(DMA17_X_MODIFY)
1370#define bfin_write_DMA17_X_MODIFY(val) bfin_write16(DMA17_X_MODIFY)
1371#define bfin_read_DMA17_Y_COUNT() bfin_read16(DMA17_Y_COUNT)
1372#define bfin_write_DMA17_Y_COUNT(val) bfin_write16(DMA17_Y_COUNT, val)
1373#define bfin_read_DMA17_Y_MODIFY() bfin_read16(DMA17_Y_MODIFY)
1374#define bfin_write_DMA17_Y_MODIFY(val) bfin_write16(DMA17_Y_MODIFY)
1375#define bfin_read_DMA17_CURR_DESC_PTR() bfin_read32(DMA17_CURR_DESC_PTR)
1376#define bfin_write_DMA17_CURR_DESC_PTR(val) bfin_write32(DMA17_CURR_DESC_PTR)
1377#define bfin_read_DMA17_CURR_ADDR() bfin_read32(DMA17_CURR_ADDR)
1378#define bfin_write_DMA17_CURR_ADDR(val) bfin_write32(DMA17_CURR_ADDR)
1379#define bfin_read_DMA17_IRQ_STATUS() bfin_read16(DMA17_IRQ_STATUS)
1380#define bfin_write_DMA17_IRQ_STATUS(val) bfin_write16(DMA17_IRQ_STATUS, val)
1381#define bfin_read_DMA17_PERIPHERAL_MAP() bfin_read16(DMA17_PERIPHERAL_MAP)
1382#define bfin_write_DMA17_PERIPHERAL_MAP(val) bfin_write16(DMA17_PERIPHERAL_MAP, val)
1383#define bfin_read_DMA17_CURR_X_COUNT() bfin_read16(DMA17_CURR_X_COUNT)
1384#define bfin_write_DMA17_CURR_X_COUNT(val) bfin_write16(DMA17_CURR_X_COUNT, val)
1385#define bfin_read_DMA17_CURR_Y_COUNT() bfin_read16(DMA17_CURR_Y_COUNT)
1386#define bfin_write_DMA17_CURR_Y_COUNT(val) bfin_write16(DMA17_CURR_Y_COUNT, val)
1387
1388/* DMA Channel 18 Registers */
1389
1390#define bfin_read_DMA18_NEXT_DESC_PTR() bfin_read32(DMA18_NEXT_DESC_PTR)
1391#define bfin_write_DMA18_NEXT_DESC_PTR(val) bfin_write32(DMA18_NEXT_DESC_PTR)
1392#define bfin_read_DMA18_START_ADDR() bfin_read32(DMA18_START_ADDR)
1393#define bfin_write_DMA18_START_ADDR(val) bfin_write32(DMA18_START_ADDR)
1394#define bfin_read_DMA18_CONFIG() bfin_read16(DMA18_CONFIG)
1395#define bfin_write_DMA18_CONFIG(val) bfin_write16(DMA18_CONFIG, val)
1396#define bfin_read_DMA18_X_COUNT() bfin_read16(DMA18_X_COUNT)
1397#define bfin_write_DMA18_X_COUNT(val) bfin_write16(DMA18_X_COUNT, val)
1398#define bfin_read_DMA18_X_MODIFY() bfin_read16(DMA18_X_MODIFY)
1399#define bfin_write_DMA18_X_MODIFY(val) bfin_write16(DMA18_X_MODIFY)
1400#define bfin_read_DMA18_Y_COUNT() bfin_read16(DMA18_Y_COUNT)
1401#define bfin_write_DMA18_Y_COUNT(val) bfin_write16(DMA18_Y_COUNT, val)
1402#define bfin_read_DMA18_Y_MODIFY() bfin_read16(DMA18_Y_MODIFY)
1403#define bfin_write_DMA18_Y_MODIFY(val) bfin_write16(DMA18_Y_MODIFY)
1404#define bfin_read_DMA18_CURR_DESC_PTR() bfin_read32(DMA18_CURR_DESC_PTR)
1405#define bfin_write_DMA18_CURR_DESC_PTR(val) bfin_write32(DMA18_CURR_DESC_PTR)
1406#define bfin_read_DMA18_CURR_ADDR() bfin_read32(DMA18_CURR_ADDR)
1407#define bfin_write_DMA18_CURR_ADDR(val) bfin_write32(DMA18_CURR_ADDR)
1408#define bfin_read_DMA18_IRQ_STATUS() bfin_read16(DMA18_IRQ_STATUS)
1409#define bfin_write_DMA18_IRQ_STATUS(val) bfin_write16(DMA18_IRQ_STATUS, val)
1410#define bfin_read_DMA18_PERIPHERAL_MAP() bfin_read16(DMA18_PERIPHERAL_MAP)
1411#define bfin_write_DMA18_PERIPHERAL_MAP(val) bfin_write16(DMA18_PERIPHERAL_MAP, val)
1412#define bfin_read_DMA18_CURR_X_COUNT() bfin_read16(DMA18_CURR_X_COUNT)
1413#define bfin_write_DMA18_CURR_X_COUNT(val) bfin_write16(DMA18_CURR_X_COUNT, val)
1414#define bfin_read_DMA18_CURR_Y_COUNT() bfin_read16(DMA18_CURR_Y_COUNT)
1415#define bfin_write_DMA18_CURR_Y_COUNT(val) bfin_write16(DMA18_CURR_Y_COUNT, val)
1416
1417/* DMA Channel 19 Registers */
1418
1419#define bfin_read_DMA19_NEXT_DESC_PTR() bfin_read32(DMA19_NEXT_DESC_PTR)
1420#define bfin_write_DMA19_NEXT_DESC_PTR(val) bfin_write32(DMA19_NEXT_DESC_PTR)
1421#define bfin_read_DMA19_START_ADDR() bfin_read32(DMA19_START_ADDR)
1422#define bfin_write_DMA19_START_ADDR(val) bfin_write32(DMA19_START_ADDR)
1423#define bfin_read_DMA19_CONFIG() bfin_read16(DMA19_CONFIG)
1424#define bfin_write_DMA19_CONFIG(val) bfin_write16(DMA19_CONFIG, val)
1425#define bfin_read_DMA19_X_COUNT() bfin_read16(DMA19_X_COUNT)
1426#define bfin_write_DMA19_X_COUNT(val) bfin_write16(DMA19_X_COUNT, val)
1427#define bfin_read_DMA19_X_MODIFY() bfin_read16(DMA19_X_MODIFY)
1428#define bfin_write_DMA19_X_MODIFY(val) bfin_write16(DMA19_X_MODIFY)
1429#define bfin_read_DMA19_Y_COUNT() bfin_read16(DMA19_Y_COUNT)
1430#define bfin_write_DMA19_Y_COUNT(val) bfin_write16(DMA19_Y_COUNT, val)
1431#define bfin_read_DMA19_Y_MODIFY() bfin_read16(DMA19_Y_MODIFY)
1432#define bfin_write_DMA19_Y_MODIFY(val) bfin_write16(DMA19_Y_MODIFY)
1433#define bfin_read_DMA19_CURR_DESC_PTR() bfin_read32(DMA19_CURR_DESC_PTR)
1434#define bfin_write_DMA19_CURR_DESC_PTR(val) bfin_write32(DMA19_CURR_DESC_PTR)
1435#define bfin_read_DMA19_CURR_ADDR() bfin_read32(DMA19_CURR_ADDR)
1436#define bfin_write_DMA19_CURR_ADDR(val) bfin_write32(DMA19_CURR_ADDR)
1437#define bfin_read_DMA19_IRQ_STATUS() bfin_read16(DMA19_IRQ_STATUS)
1438#define bfin_write_DMA19_IRQ_STATUS(val) bfin_write16(DMA19_IRQ_STATUS, val)
1439#define bfin_read_DMA19_PERIPHERAL_MAP() bfin_read16(DMA19_PERIPHERAL_MAP)
1440#define bfin_write_DMA19_PERIPHERAL_MAP(val) bfin_write16(DMA19_PERIPHERAL_MAP, val)
1441#define bfin_read_DMA19_CURR_X_COUNT() bfin_read16(DMA19_CURR_X_COUNT)
1442#define bfin_write_DMA19_CURR_X_COUNT(val) bfin_write16(DMA19_CURR_X_COUNT, val)
1443#define bfin_read_DMA19_CURR_Y_COUNT() bfin_read16(DMA19_CURR_Y_COUNT)
1444#define bfin_write_DMA19_CURR_Y_COUNT(val) bfin_write16(DMA19_CURR_Y_COUNT, val)
1445
1446/* DMA Channel 20 Registers */
1447
1448#define bfin_read_DMA20_NEXT_DESC_PTR() bfin_read32(DMA20_NEXT_DESC_PTR)
1449#define bfin_write_DMA20_NEXT_DESC_PTR(val) bfin_write32(DMA20_NEXT_DESC_PTR)
1450#define bfin_read_DMA20_START_ADDR() bfin_read32(DMA20_START_ADDR)
1451#define bfin_write_DMA20_START_ADDR(val) bfin_write32(DMA20_START_ADDR)
1452#define bfin_read_DMA20_CONFIG() bfin_read16(DMA20_CONFIG)
1453#define bfin_write_DMA20_CONFIG(val) bfin_write16(DMA20_CONFIG, val)
1454#define bfin_read_DMA20_X_COUNT() bfin_read16(DMA20_X_COUNT)
1455#define bfin_write_DMA20_X_COUNT(val) bfin_write16(DMA20_X_COUNT, val)
1456#define bfin_read_DMA20_X_MODIFY() bfin_read16(DMA20_X_MODIFY)
1457#define bfin_write_DMA20_X_MODIFY(val) bfin_write16(DMA20_X_MODIFY)
1458#define bfin_read_DMA20_Y_COUNT() bfin_read16(DMA20_Y_COUNT)
1459#define bfin_write_DMA20_Y_COUNT(val) bfin_write16(DMA20_Y_COUNT, val)
1460#define bfin_read_DMA20_Y_MODIFY() bfin_read16(DMA20_Y_MODIFY)
1461#define bfin_write_DMA20_Y_MODIFY(val) bfin_write16(DMA20_Y_MODIFY)
1462#define bfin_read_DMA20_CURR_DESC_PTR() bfin_read32(DMA20_CURR_DESC_PTR)
1463#define bfin_write_DMA20_CURR_DESC_PTR(val) bfin_write32(DMA20_CURR_DESC_PTR)
1464#define bfin_read_DMA20_CURR_ADDR() bfin_read32(DMA20_CURR_ADDR)
1465#define bfin_write_DMA20_CURR_ADDR(val) bfin_write32(DMA20_CURR_ADDR)
1466#define bfin_read_DMA20_IRQ_STATUS() bfin_read16(DMA20_IRQ_STATUS)
1467#define bfin_write_DMA20_IRQ_STATUS(val) bfin_write16(DMA20_IRQ_STATUS, val)
1468#define bfin_read_DMA20_PERIPHERAL_MAP() bfin_read16(DMA20_PERIPHERAL_MAP)
1469#define bfin_write_DMA20_PERIPHERAL_MAP(val) bfin_write16(DMA20_PERIPHERAL_MAP, val)
1470#define bfin_read_DMA20_CURR_X_COUNT() bfin_read16(DMA20_CURR_X_COUNT)
1471#define bfin_write_DMA20_CURR_X_COUNT(val) bfin_write16(DMA20_CURR_X_COUNT, val)
1472#define bfin_read_DMA20_CURR_Y_COUNT() bfin_read16(DMA20_CURR_Y_COUNT)
1473#define bfin_write_DMA20_CURR_Y_COUNT(val) bfin_write16(DMA20_CURR_Y_COUNT, val)
1474
1475/* DMA Channel 21 Registers */
1476
1477#define bfin_read_DMA21_NEXT_DESC_PTR() bfin_read32(DMA21_NEXT_DESC_PTR)
1478#define bfin_write_DMA21_NEXT_DESC_PTR(val) bfin_write32(DMA21_NEXT_DESC_PTR)
1479#define bfin_read_DMA21_START_ADDR() bfin_read32(DMA21_START_ADDR)
1480#define bfin_write_DMA21_START_ADDR(val) bfin_write32(DMA21_START_ADDR)
1481#define bfin_read_DMA21_CONFIG() bfin_read16(DMA21_CONFIG)
1482#define bfin_write_DMA21_CONFIG(val) bfin_write16(DMA21_CONFIG, val)
1483#define bfin_read_DMA21_X_COUNT() bfin_read16(DMA21_X_COUNT)
1484#define bfin_write_DMA21_X_COUNT(val) bfin_write16(DMA21_X_COUNT, val)
1485#define bfin_read_DMA21_X_MODIFY() bfin_read16(DMA21_X_MODIFY)
1486#define bfin_write_DMA21_X_MODIFY(val) bfin_write16(DMA21_X_MODIFY)
1487#define bfin_read_DMA21_Y_COUNT() bfin_read16(DMA21_Y_COUNT)
1488#define bfin_write_DMA21_Y_COUNT(val) bfin_write16(DMA21_Y_COUNT, val)
1489#define bfin_read_DMA21_Y_MODIFY() bfin_read16(DMA21_Y_MODIFY)
1490#define bfin_write_DMA21_Y_MODIFY(val) bfin_write16(DMA21_Y_MODIFY)
1491#define bfin_read_DMA21_CURR_DESC_PTR() bfin_read32(DMA21_CURR_DESC_PTR)
1492#define bfin_write_DMA21_CURR_DESC_PTR(val) bfin_write32(DMA21_CURR_DESC_PTR)
1493#define bfin_read_DMA21_CURR_ADDR() bfin_read32(DMA21_CURR_ADDR)
1494#define bfin_write_DMA21_CURR_ADDR(val) bfin_write32(DMA21_CURR_ADDR)
1495#define bfin_read_DMA21_IRQ_STATUS() bfin_read16(DMA21_IRQ_STATUS)
1496#define bfin_write_DMA21_IRQ_STATUS(val) bfin_write16(DMA21_IRQ_STATUS, val)
1497#define bfin_read_DMA21_PERIPHERAL_MAP() bfin_read16(DMA21_PERIPHERAL_MAP)
1498#define bfin_write_DMA21_PERIPHERAL_MAP(val) bfin_write16(DMA21_PERIPHERAL_MAP, val)
1499#define bfin_read_DMA21_CURR_X_COUNT() bfin_read16(DMA21_CURR_X_COUNT)
1500#define bfin_write_DMA21_CURR_X_COUNT(val) bfin_write16(DMA21_CURR_X_COUNT, val)
1501#define bfin_read_DMA21_CURR_Y_COUNT() bfin_read16(DMA21_CURR_Y_COUNT)
1502#define bfin_write_DMA21_CURR_Y_COUNT(val) bfin_write16(DMA21_CURR_Y_COUNT, val)
1503
1504/* DMA Channel 22 Registers */
1505
1506#define bfin_read_DMA22_NEXT_DESC_PTR() bfin_read32(DMA22_NEXT_DESC_PTR)
1507#define bfin_write_DMA22_NEXT_DESC_PTR(val) bfin_write32(DMA22_NEXT_DESC_PTR)
1508#define bfin_read_DMA22_START_ADDR() bfin_read32(DMA22_START_ADDR)
1509#define bfin_write_DMA22_START_ADDR(val) bfin_write32(DMA22_START_ADDR)
1510#define bfin_read_DMA22_CONFIG() bfin_read16(DMA22_CONFIG)
1511#define bfin_write_DMA22_CONFIG(val) bfin_write16(DMA22_CONFIG, val)
1512#define bfin_read_DMA22_X_COUNT() bfin_read16(DMA22_X_COUNT)
1513#define bfin_write_DMA22_X_COUNT(val) bfin_write16(DMA22_X_COUNT, val)
1514#define bfin_read_DMA22_X_MODIFY() bfin_read16(DMA22_X_MODIFY)
1515#define bfin_write_DMA22_X_MODIFY(val) bfin_write16(DMA22_X_MODIFY)
1516#define bfin_read_DMA22_Y_COUNT() bfin_read16(DMA22_Y_COUNT)
1517#define bfin_write_DMA22_Y_COUNT(val) bfin_write16(DMA22_Y_COUNT, val)
1518#define bfin_read_DMA22_Y_MODIFY() bfin_read16(DMA22_Y_MODIFY)
1519#define bfin_write_DMA22_Y_MODIFY(val) bfin_write16(DMA22_Y_MODIFY)
1520#define bfin_read_DMA22_CURR_DESC_PTR() bfin_read32(DMA22_CURR_DESC_PTR)
1521#define bfin_write_DMA22_CURR_DESC_PTR(val) bfin_write32(DMA22_CURR_DESC_PTR)
1522#define bfin_read_DMA22_CURR_ADDR() bfin_read32(DMA22_CURR_ADDR)
1523#define bfin_write_DMA22_CURR_ADDR(val) bfin_write32(DMA22_CURR_ADDR)
1524#define bfin_read_DMA22_IRQ_STATUS() bfin_read16(DMA22_IRQ_STATUS)
1525#define bfin_write_DMA22_IRQ_STATUS(val) bfin_write16(DMA22_IRQ_STATUS, val)
1526#define bfin_read_DMA22_PERIPHERAL_MAP() bfin_read16(DMA22_PERIPHERAL_MAP)
1527#define bfin_write_DMA22_PERIPHERAL_MAP(val) bfin_write16(DMA22_PERIPHERAL_MAP, val)
1528#define bfin_read_DMA22_CURR_X_COUNT() bfin_read16(DMA22_CURR_X_COUNT)
1529#define bfin_write_DMA22_CURR_X_COUNT(val) bfin_write16(DMA22_CURR_X_COUNT, val)
1530#define bfin_read_DMA22_CURR_Y_COUNT() bfin_read16(DMA22_CURR_Y_COUNT)
1531#define bfin_write_DMA22_CURR_Y_COUNT(val) bfin_write16(DMA22_CURR_Y_COUNT, val)
1532
1533/* DMA Channel 23 Registers */
1534
1535#define bfin_read_DMA23_NEXT_DESC_PTR() bfin_read32(DMA23_NEXT_DESC_PTR)
1536#define bfin_write_DMA23_NEXT_DESC_PTR(val) bfin_write32(DMA23_NEXT_DESC_PTR)
1537#define bfin_read_DMA23_START_ADDR() bfin_read32(DMA23_START_ADDR)
1538#define bfin_write_DMA23_START_ADDR(val) bfin_write32(DMA23_START_ADDR)
1539#define bfin_read_DMA23_CONFIG() bfin_read16(DMA23_CONFIG)
1540#define bfin_write_DMA23_CONFIG(val) bfin_write16(DMA23_CONFIG, val)
1541#define bfin_read_DMA23_X_COUNT() bfin_read16(DMA23_X_COUNT)
1542#define bfin_write_DMA23_X_COUNT(val) bfin_write16(DMA23_X_COUNT, val)
1543#define bfin_read_DMA23_X_MODIFY() bfin_read16(DMA23_X_MODIFY)
1544#define bfin_write_DMA23_X_MODIFY(val) bfin_write16(DMA23_X_MODIFY)
1545#define bfin_read_DMA23_Y_COUNT() bfin_read16(DMA23_Y_COUNT)
1546#define bfin_write_DMA23_Y_COUNT(val) bfin_write16(DMA23_Y_COUNT, val)
1547#define bfin_read_DMA23_Y_MODIFY() bfin_read16(DMA23_Y_MODIFY)
1548#define bfin_write_DMA23_Y_MODIFY(val) bfin_write16(DMA23_Y_MODIFY)
1549#define bfin_read_DMA23_CURR_DESC_PTR() bfin_read32(DMA23_CURR_DESC_PTR)
1550#define bfin_write_DMA23_CURR_DESC_PTR(val) bfin_write32(DMA23_CURR_DESC_PTR)
1551#define bfin_read_DMA23_CURR_ADDR() bfin_read32(DMA23_CURR_ADDR)
1552#define bfin_write_DMA23_CURR_ADDR(val) bfin_write32(DMA23_CURR_ADDR)
1553#define bfin_read_DMA23_IRQ_STATUS() bfin_read16(DMA23_IRQ_STATUS)
1554#define bfin_write_DMA23_IRQ_STATUS(val) bfin_write16(DMA23_IRQ_STATUS, val)
1555#define bfin_read_DMA23_PERIPHERAL_MAP() bfin_read16(DMA23_PERIPHERAL_MAP)
1556#define bfin_write_DMA23_PERIPHERAL_MAP(val) bfin_write16(DMA23_PERIPHERAL_MAP, val)
1557#define bfin_read_DMA23_CURR_X_COUNT() bfin_read16(DMA23_CURR_X_COUNT)
1558#define bfin_write_DMA23_CURR_X_COUNT(val) bfin_write16(DMA23_CURR_X_COUNT, val)
1559#define bfin_read_DMA23_CURR_Y_COUNT() bfin_read16(DMA23_CURR_Y_COUNT)
1560#define bfin_write_DMA23_CURR_Y_COUNT(val) bfin_write16(DMA23_CURR_Y_COUNT, val)
1561
1562/* MDMA Stream 2 Registers */
1563
1564#define bfin_read_MDMA_D2_NEXT_DESC_PTR() bfin_read32(MDMA_D2_NEXT_DESC_PTR)
1565#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val) bfin_write32(MDMA_D2_NEXT_DESC_PTR)
1566#define bfin_read_MDMA_D2_START_ADDR() bfin_read32(MDMA_D2_START_ADDR)
1567#define bfin_write_MDMA_D2_START_ADDR(val) bfin_write32(MDMA_D2_START_ADDR)
1568#define bfin_read_MDMA_D2_CONFIG() bfin_read16(MDMA_D2_CONFIG)
1569#define bfin_write_MDMA_D2_CONFIG(val) bfin_write16(MDMA_D2_CONFIG, val)
1570#define bfin_read_MDMA_D2_X_COUNT() bfin_read16(MDMA_D2_X_COUNT)
1571#define bfin_write_MDMA_D2_X_COUNT(val) bfin_write16(MDMA_D2_X_COUNT, val)
1572#define bfin_read_MDMA_D2_X_MODIFY() bfin_read16(MDMA_D2_X_MODIFY)
1573#define bfin_write_MDMA_D2_X_MODIFY(val) bfin_write16(MDMA_D2_X_MODIFY)
1574#define bfin_read_MDMA_D2_Y_COUNT() bfin_read16(MDMA_D2_Y_COUNT)
1575#define bfin_write_MDMA_D2_Y_COUNT(val) bfin_write16(MDMA_D2_Y_COUNT, val)
1576#define bfin_read_MDMA_D2_Y_MODIFY() bfin_read16(MDMA_D2_Y_MODIFY)
1577#define bfin_write_MDMA_D2_Y_MODIFY(val) bfin_write16(MDMA_D2_Y_MODIFY)
1578#define bfin_read_MDMA_D2_CURR_DESC_PTR() bfin_read32(MDMA_D2_CURR_DESC_PTR)
1579#define bfin_write_MDMA_D2_CURR_DESC_PTR(val) bfin_write32(MDMA_D2_CURR_DESC_PTR)
1580#define bfin_read_MDMA_D2_CURR_ADDR() bfin_read32(MDMA_D2_CURR_ADDR)
1581#define bfin_write_MDMA_D2_CURR_ADDR(val) bfin_write32(MDMA_D2_CURR_ADDR)
1582#define bfin_read_MDMA_D2_IRQ_STATUS() bfin_read16(MDMA_D2_IRQ_STATUS)
1583#define bfin_write_MDMA_D2_IRQ_STATUS(val) bfin_write16(MDMA_D2_IRQ_STATUS, val)
1584#define bfin_read_MDMA_D2_PERIPHERAL_MAP() bfin_read16(MDMA_D2_PERIPHERAL_MAP)
1585#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val) bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
1586#define bfin_read_MDMA_D2_CURR_X_COUNT() bfin_read16(MDMA_D2_CURR_X_COUNT)
1587#define bfin_write_MDMA_D2_CURR_X_COUNT(val) bfin_write16(MDMA_D2_CURR_X_COUNT, val)
1588#define bfin_read_MDMA_D2_CURR_Y_COUNT() bfin_read16(MDMA_D2_CURR_Y_COUNT)
1589#define bfin_write_MDMA_D2_CURR_Y_COUNT(val) bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
1590#define bfin_read_MDMA_S2_NEXT_DESC_PTR() bfin_read32(MDMA_S2_NEXT_DESC_PTR)
1591#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val) bfin_write32(MDMA_S2_NEXT_DESC_PTR)
1592#define bfin_read_MDMA_S2_START_ADDR() bfin_read32(MDMA_S2_START_ADDR)
1593#define bfin_write_MDMA_S2_START_ADDR(val) bfin_write32(MDMA_S2_START_ADDR)
1594#define bfin_read_MDMA_S2_CONFIG() bfin_read16(MDMA_S2_CONFIG)
1595#define bfin_write_MDMA_S2_CONFIG(val) bfin_write16(MDMA_S2_CONFIG, val)
1596#define bfin_read_MDMA_S2_X_COUNT() bfin_read16(MDMA_S2_X_COUNT)
1597#define bfin_write_MDMA_S2_X_COUNT(val) bfin_write16(MDMA_S2_X_COUNT, val)
1598#define bfin_read_MDMA_S2_X_MODIFY() bfin_read16(MDMA_S2_X_MODIFY)
1599#define bfin_write_MDMA_S2_X_MODIFY(val) bfin_write16(MDMA_S2_X_MODIFY)
1600#define bfin_read_MDMA_S2_Y_COUNT() bfin_read16(MDMA_S2_Y_COUNT)
1601#define bfin_write_MDMA_S2_Y_COUNT(val) bfin_write16(MDMA_S2_Y_COUNT, val)
1602#define bfin_read_MDMA_S2_Y_MODIFY() bfin_read16(MDMA_S2_Y_MODIFY)
1603#define bfin_write_MDMA_S2_Y_MODIFY(val) bfin_write16(MDMA_S2_Y_MODIFY)
1604#define bfin_read_MDMA_S2_CURR_DESC_PTR() bfin_read32(MDMA_S2_CURR_DESC_PTR)
1605#define bfin_write_MDMA_S2_CURR_DESC_PTR(val) bfin_write32(MDMA_S2_CURR_DESC_PTR)
1606#define bfin_read_MDMA_S2_CURR_ADDR() bfin_read32(MDMA_S2_CURR_ADDR)
1607#define bfin_write_MDMA_S2_CURR_ADDR(val) bfin_write32(MDMA_S2_CURR_ADDR)
1608#define bfin_read_MDMA_S2_IRQ_STATUS() bfin_read16(MDMA_S2_IRQ_STATUS)
1609#define bfin_write_MDMA_S2_IRQ_STATUS(val) bfin_write16(MDMA_S2_IRQ_STATUS, val)
1610#define bfin_read_MDMA_S2_PERIPHERAL_MAP() bfin_read16(MDMA_S2_PERIPHERAL_MAP)
1611#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val) bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
1612#define bfin_read_MDMA_S2_CURR_X_COUNT() bfin_read16(MDMA_S2_CURR_X_COUNT)
1613#define bfin_write_MDMA_S2_CURR_X_COUNT(val) bfin_write16(MDMA_S2_CURR_X_COUNT, val)
1614#define bfin_read_MDMA_S2_CURR_Y_COUNT() bfin_read16(MDMA_S2_CURR_Y_COUNT)
1615#define bfin_write_MDMA_S2_CURR_Y_COUNT(val) bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
1616
1617/* MDMA Stream 3 Registers */
1618
1619#define bfin_read_MDMA_D3_NEXT_DESC_PTR() bfin_read32(MDMA_D3_NEXT_DESC_PTR)
1620#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val) bfin_write32(MDMA_D3_NEXT_DESC_PTR)
1621#define bfin_read_MDMA_D3_START_ADDR() bfin_read32(MDMA_D3_START_ADDR)
1622#define bfin_write_MDMA_D3_START_ADDR(val) bfin_write32(MDMA_D3_START_ADDR)
1623#define bfin_read_MDMA_D3_CONFIG() bfin_read16(MDMA_D3_CONFIG)
1624#define bfin_write_MDMA_D3_CONFIG(val) bfin_write16(MDMA_D3_CONFIG, val)
1625#define bfin_read_MDMA_D3_X_COUNT() bfin_read16(MDMA_D3_X_COUNT)
1626#define bfin_write_MDMA_D3_X_COUNT(val) bfin_write16(MDMA_D3_X_COUNT, val)
1627#define bfin_read_MDMA_D3_X_MODIFY() bfin_read16(MDMA_D3_X_MODIFY)
1628#define bfin_write_MDMA_D3_X_MODIFY(val) bfin_write16(MDMA_D3_X_MODIFY)
1629#define bfin_read_MDMA_D3_Y_COUNT() bfin_read16(MDMA_D3_Y_COUNT)
1630#define bfin_write_MDMA_D3_Y_COUNT(val) bfin_write16(MDMA_D3_Y_COUNT, val)
1631#define bfin_read_MDMA_D3_Y_MODIFY() bfin_read16(MDMA_D3_Y_MODIFY)
1632#define bfin_write_MDMA_D3_Y_MODIFY(val) bfin_write16(MDMA_D3_Y_MODIFY)
1633#define bfin_read_MDMA_D3_CURR_DESC_PTR() bfin_read32(MDMA_D3_CURR_DESC_PTR)
1634#define bfin_write_MDMA_D3_CURR_DESC_PTR(val) bfin_write32(MDMA_D3_CURR_DESC_PTR)
1635#define bfin_read_MDMA_D3_CURR_ADDR() bfin_read32(MDMA_D3_CURR_ADDR)
1636#define bfin_write_MDMA_D3_CURR_ADDR(val) bfin_write32(MDMA_D3_CURR_ADDR)
1637#define bfin_read_MDMA_D3_IRQ_STATUS() bfin_read16(MDMA_D3_IRQ_STATUS)
1638#define bfin_write_MDMA_D3_IRQ_STATUS(val) bfin_write16(MDMA_D3_IRQ_STATUS, val)
1639#define bfin_read_MDMA_D3_PERIPHERAL_MAP() bfin_read16(MDMA_D3_PERIPHERAL_MAP)
1640#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val) bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
1641#define bfin_read_MDMA_D3_CURR_X_COUNT() bfin_read16(MDMA_D3_CURR_X_COUNT)
1642#define bfin_write_MDMA_D3_CURR_X_COUNT(val) bfin_write16(MDMA_D3_CURR_X_COUNT, val)
1643#define bfin_read_MDMA_D3_CURR_Y_COUNT() bfin_read16(MDMA_D3_CURR_Y_COUNT)
1644#define bfin_write_MDMA_D3_CURR_Y_COUNT(val) bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
1645#define bfin_read_MDMA_S3_NEXT_DESC_PTR() bfin_read32(MDMA_S3_NEXT_DESC_PTR)
1646#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val) bfin_write32(MDMA_S3_NEXT_DESC_PTR)
1647#define bfin_read_MDMA_S3_START_ADDR() bfin_read32(MDMA_S3_START_ADDR)
1648#define bfin_write_MDMA_S3_START_ADDR(val) bfin_write32(MDMA_S3_START_ADDR)
1649#define bfin_read_MDMA_S3_CONFIG() bfin_read16(MDMA_S3_CONFIG)
1650#define bfin_write_MDMA_S3_CONFIG(val) bfin_write16(MDMA_S3_CONFIG, val)
1651#define bfin_read_MDMA_S3_X_COUNT() bfin_read16(MDMA_S3_X_COUNT)
1652#define bfin_write_MDMA_S3_X_COUNT(val) bfin_write16(MDMA_S3_X_COUNT, val)
1653#define bfin_read_MDMA_S3_X_MODIFY() bfin_read16(MDMA_S3_X_MODIFY)
1654#define bfin_write_MDMA_S3_X_MODIFY(val) bfin_write16(MDMA_S3_X_MODIFY)
1655#define bfin_read_MDMA_S3_Y_COUNT() bfin_read16(MDMA_S3_Y_COUNT)
1656#define bfin_write_MDMA_S3_Y_COUNT(val) bfin_write16(MDMA_S3_Y_COUNT, val)
1657#define bfin_read_MDMA_S3_Y_MODIFY() bfin_read16(MDMA_S3_Y_MODIFY)
1658#define bfin_write_MDMA_S3_Y_MODIFY(val) bfin_write16(MDMA_S3_Y_MODIFY)
1659#define bfin_read_MDMA_S3_CURR_DESC_PTR() bfin_read32(MDMA_S3_CURR_DESC_PTR)
1660#define bfin_write_MDMA_S3_CURR_DESC_PTR(val) bfin_write32(MDMA_S3_CURR_DESC_PTR)
1661#define bfin_read_MDMA_S3_CURR_ADDR() bfin_read32(MDMA_S3_CURR_ADDR)
1662#define bfin_write_MDMA_S3_CURR_ADDR(val) bfin_write32(MDMA_S3_CURR_ADDR)
1663#define bfin_read_MDMA_S3_IRQ_STATUS() bfin_read16(MDMA_S3_IRQ_STATUS)
1664#define bfin_write_MDMA_S3_IRQ_STATUS(val) bfin_write16(MDMA_S3_IRQ_STATUS, val)
1665#define bfin_read_MDMA_S3_PERIPHERAL_MAP() bfin_read16(MDMA_S3_PERIPHERAL_MAP)
1666#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val) bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
1667#define bfin_read_MDMA_S3_CURR_X_COUNT() bfin_read16(MDMA_S3_CURR_X_COUNT)
1668#define bfin_write_MDMA_S3_CURR_X_COUNT(val) bfin_write16(MDMA_S3_CURR_X_COUNT, val)
1669#define bfin_read_MDMA_S3_CURR_Y_COUNT() bfin_read16(MDMA_S3_CURR_Y_COUNT)
1670#define bfin_write_MDMA_S3_CURR_Y_COUNT(val) bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
1671
1672/* UART1 Registers */
1673
1674#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
1675#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
1676#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
1677#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
1678#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
1679#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
1680#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
1681#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
1682#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
1683#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
1684#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
1685#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
1686#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
1687#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
1688#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
1689#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
1690#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
1691#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
1692#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
1693#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
1694#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
1695#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
1696#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
1697#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
1698
1699/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
1700
1701/* SPI1 Registers */
1702
1703#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
1704#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
1705#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
1706#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
1707#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
1708#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
1709#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
1710#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
1711#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
1712#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
1713#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
1714#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
1715#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
1716#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
1717
1718/* SPORT2 Registers */
1719
1720#define bfin_read_SPORT2_TCR1() bfin_read16(SPORT2_TCR1)
1721#define bfin_write_SPORT2_TCR1(val) bfin_write16(SPORT2_TCR1, val)
1722#define bfin_read_SPORT2_TCR2() bfin_read16(SPORT2_TCR2)
1723#define bfin_write_SPORT2_TCR2(val) bfin_write16(SPORT2_TCR2, val)
1724#define bfin_read_SPORT2_TCLKDIV() bfin_read16(SPORT2_TCLKDIV)
1725#define bfin_write_SPORT2_TCLKDIV(val) bfin_write16(SPORT2_TCLKDIV, val)
1726#define bfin_read_SPORT2_TFSDIV() bfin_read16(SPORT2_TFSDIV)
1727#define bfin_write_SPORT2_TFSDIV(val) bfin_write16(SPORT2_TFSDIV, val)
1728#define bfin_read_SPORT2_TX() bfin_read32(SPORT2_TX)
1729#define bfin_write_SPORT2_TX(val) bfin_write32(SPORT2_TX, val)
1730#define bfin_read_SPORT2_RX() bfin_read32(SPORT2_RX)
1731#define bfin_write_SPORT2_RX(val) bfin_write32(SPORT2_RX, val)
1732#define bfin_read_SPORT2_RCR1() bfin_read16(SPORT2_RCR1)
1733#define bfin_write_SPORT2_RCR1(val) bfin_write16(SPORT2_RCR1, val)
1734#define bfin_read_SPORT2_RCR2() bfin_read16(SPORT2_RCR2)
1735#define bfin_write_SPORT2_RCR2(val) bfin_write16(SPORT2_RCR2, val)
1736#define bfin_read_SPORT2_RCLKDIV() bfin_read16(SPORT2_RCLKDIV)
1737#define bfin_write_SPORT2_RCLKDIV(val) bfin_write16(SPORT2_RCLKDIV, val)
1738#define bfin_read_SPORT2_RFSDIV() bfin_read16(SPORT2_RFSDIV)
1739#define bfin_write_SPORT2_RFSDIV(val) bfin_write16(SPORT2_RFSDIV, val)
1740#define bfin_read_SPORT2_STAT() bfin_read16(SPORT2_STAT)
1741#define bfin_write_SPORT2_STAT(val) bfin_write16(SPORT2_STAT, val)
1742#define bfin_read_SPORT2_CHNL() bfin_read16(SPORT2_CHNL)
1743#define bfin_write_SPORT2_CHNL(val) bfin_write16(SPORT2_CHNL, val)
1744#define bfin_read_SPORT2_MCMC1() bfin_read16(SPORT2_MCMC1)
1745#define bfin_write_SPORT2_MCMC1(val) bfin_write16(SPORT2_MCMC1, val)
1746#define bfin_read_SPORT2_MCMC2() bfin_read16(SPORT2_MCMC2)
1747#define bfin_write_SPORT2_MCMC2(val) bfin_write16(SPORT2_MCMC2, val)
1748#define bfin_read_SPORT2_MTCS0() bfin_read32(SPORT2_MTCS0)
1749#define bfin_write_SPORT2_MTCS0(val) bfin_write32(SPORT2_MTCS0, val)
1750#define bfin_read_SPORT2_MTCS1() bfin_read32(SPORT2_MTCS1)
1751#define bfin_write_SPORT2_MTCS1(val) bfin_write32(SPORT2_MTCS1, val)
1752#define bfin_read_SPORT2_MTCS2() bfin_read32(SPORT2_MTCS2)
1753#define bfin_write_SPORT2_MTCS2(val) bfin_write32(SPORT2_MTCS2, val)
1754#define bfin_read_SPORT2_MTCS3() bfin_read32(SPORT2_MTCS3)
1755#define bfin_write_SPORT2_MTCS3(val) bfin_write32(SPORT2_MTCS3, val)
1756#define bfin_read_SPORT2_MRCS0() bfin_read32(SPORT2_MRCS0)
1757#define bfin_write_SPORT2_MRCS0(val) bfin_write32(SPORT2_MRCS0, val)
1758#define bfin_read_SPORT2_MRCS1() bfin_read32(SPORT2_MRCS1)
1759#define bfin_write_SPORT2_MRCS1(val) bfin_write32(SPORT2_MRCS1, val)
1760#define bfin_read_SPORT2_MRCS2() bfin_read32(SPORT2_MRCS2)
1761#define bfin_write_SPORT2_MRCS2(val) bfin_write32(SPORT2_MRCS2, val)
1762#define bfin_read_SPORT2_MRCS3() bfin_read32(SPORT2_MRCS3)
1763#define bfin_write_SPORT2_MRCS3(val) bfin_write32(SPORT2_MRCS3, val)
1764
1765/* SPORT3 Registers */
1766
1767#define bfin_read_SPORT3_TCR1() bfin_read16(SPORT3_TCR1)
1768#define bfin_write_SPORT3_TCR1(val) bfin_write16(SPORT3_TCR1, val)
1769#define bfin_read_SPORT3_TCR2() bfin_read16(SPORT3_TCR2)
1770#define bfin_write_SPORT3_TCR2(val) bfin_write16(SPORT3_TCR2, val)
1771#define bfin_read_SPORT3_TCLKDIV() bfin_read16(SPORT3_TCLKDIV)
1772#define bfin_write_SPORT3_TCLKDIV(val) bfin_write16(SPORT3_TCLKDIV, val)
1773#define bfin_read_SPORT3_TFSDIV() bfin_read16(SPORT3_TFSDIV)
1774#define bfin_write_SPORT3_TFSDIV(val) bfin_write16(SPORT3_TFSDIV, val)
1775#define bfin_read_SPORT3_TX() bfin_read32(SPORT3_TX)
1776#define bfin_write_SPORT3_TX(val) bfin_write32(SPORT3_TX, val)
1777#define bfin_read_SPORT3_RX() bfin_read32(SPORT3_RX)
1778#define bfin_write_SPORT3_RX(val) bfin_write32(SPORT3_RX, val)
1779#define bfin_read_SPORT3_RCR1() bfin_read16(SPORT3_RCR1)
1780#define bfin_write_SPORT3_RCR1(val) bfin_write16(SPORT3_RCR1, val)
1781#define bfin_read_SPORT3_RCR2() bfin_read16(SPORT3_RCR2)
1782#define bfin_write_SPORT3_RCR2(val) bfin_write16(SPORT3_RCR2, val)
1783#define bfin_read_SPORT3_RCLKDIV() bfin_read16(SPORT3_RCLKDIV)
1784#define bfin_write_SPORT3_RCLKDIV(val) bfin_write16(SPORT3_RCLKDIV, val)
1785#define bfin_read_SPORT3_RFSDIV() bfin_read16(SPORT3_RFSDIV)
1786#define bfin_write_SPORT3_RFSDIV(val) bfin_write16(SPORT3_RFSDIV, val)
1787#define bfin_read_SPORT3_STAT() bfin_read16(SPORT3_STAT)
1788#define bfin_write_SPORT3_STAT(val) bfin_write16(SPORT3_STAT, val)
1789#define bfin_read_SPORT3_CHNL() bfin_read16(SPORT3_CHNL)
1790#define bfin_write_SPORT3_CHNL(val) bfin_write16(SPORT3_CHNL, val)
1791#define bfin_read_SPORT3_MCMC1() bfin_read16(SPORT3_MCMC1)
1792#define bfin_write_SPORT3_MCMC1(val) bfin_write16(SPORT3_MCMC1, val)
1793#define bfin_read_SPORT3_MCMC2() bfin_read16(SPORT3_MCMC2)
1794#define bfin_write_SPORT3_MCMC2(val) bfin_write16(SPORT3_MCMC2, val)
1795#define bfin_read_SPORT3_MTCS0() bfin_read32(SPORT3_MTCS0)
1796#define bfin_write_SPORT3_MTCS0(val) bfin_write32(SPORT3_MTCS0, val)
1797#define bfin_read_SPORT3_MTCS1() bfin_read32(SPORT3_MTCS1)
1798#define bfin_write_SPORT3_MTCS1(val) bfin_write32(SPORT3_MTCS1, val)
1799#define bfin_read_SPORT3_MTCS2() bfin_read32(SPORT3_MTCS2)
1800#define bfin_write_SPORT3_MTCS2(val) bfin_write32(SPORT3_MTCS2, val)
1801#define bfin_read_SPORT3_MTCS3() bfin_read32(SPORT3_MTCS3)
1802#define bfin_write_SPORT3_MTCS3(val) bfin_write32(SPORT3_MTCS3, val)
1803#define bfin_read_SPORT3_MRCS0() bfin_read32(SPORT3_MRCS0)
1804#define bfin_write_SPORT3_MRCS0(val) bfin_write32(SPORT3_MRCS0, val)
1805#define bfin_read_SPORT3_MRCS1() bfin_read32(SPORT3_MRCS1)
1806#define bfin_write_SPORT3_MRCS1(val) bfin_write32(SPORT3_MRCS1, val)
1807#define bfin_read_SPORT3_MRCS2() bfin_read32(SPORT3_MRCS2)
1808#define bfin_write_SPORT3_MRCS2(val) bfin_write32(SPORT3_MRCS2, val)
1809#define bfin_read_SPORT3_MRCS3() bfin_read32(SPORT3_MRCS3)
1810#define bfin_write_SPORT3_MRCS3(val) bfin_write32(SPORT3_MRCS3, val)
1811
1812/* EPPI2 Registers */
1813
1814#define bfin_read_EPPI2_STATUS() bfin_read16(EPPI2_STATUS)
1815#define bfin_write_EPPI2_STATUS(val) bfin_write16(EPPI2_STATUS, val)
1816#define bfin_read_EPPI2_HCOUNT() bfin_read16(EPPI2_HCOUNT)
1817#define bfin_write_EPPI2_HCOUNT(val) bfin_write16(EPPI2_HCOUNT, val)
1818#define bfin_read_EPPI2_HDELAY() bfin_read16(EPPI2_HDELAY)
1819#define bfin_write_EPPI2_HDELAY(val) bfin_write16(EPPI2_HDELAY, val)
1820#define bfin_read_EPPI2_VCOUNT() bfin_read16(EPPI2_VCOUNT)
1821#define bfin_write_EPPI2_VCOUNT(val) bfin_write16(EPPI2_VCOUNT, val)
1822#define bfin_read_EPPI2_VDELAY() bfin_read16(EPPI2_VDELAY)
1823#define bfin_write_EPPI2_VDELAY(val) bfin_write16(EPPI2_VDELAY, val)
1824#define bfin_read_EPPI2_FRAME() bfin_read16(EPPI2_FRAME)
1825#define bfin_write_EPPI2_FRAME(val) bfin_write16(EPPI2_FRAME, val)
1826#define bfin_read_EPPI2_LINE() bfin_read16(EPPI2_LINE)
1827#define bfin_write_EPPI2_LINE(val) bfin_write16(EPPI2_LINE, val)
1828#define bfin_read_EPPI2_CLKDIV() bfin_read16(EPPI2_CLKDIV)
1829#define bfin_write_EPPI2_CLKDIV(val) bfin_write16(EPPI2_CLKDIV, val)
1830#define bfin_read_EPPI2_CONTROL() bfin_read32(EPPI2_CONTROL)
1831#define bfin_write_EPPI2_CONTROL(val) bfin_write32(EPPI2_CONTROL, val)
1832#define bfin_read_EPPI2_FS1W_HBL() bfin_read32(EPPI2_FS1W_HBL)
1833#define bfin_write_EPPI2_FS1W_HBL(val) bfin_write32(EPPI2_FS1W_HBL, val)
1834#define bfin_read_EPPI2_FS1P_AVPL() bfin_read32(EPPI2_FS1P_AVPL)
1835#define bfin_write_EPPI2_FS1P_AVPL(val) bfin_write32(EPPI2_FS1P_AVPL, val)
1836#define bfin_read_EPPI2_FS2W_LVB() bfin_read32(EPPI2_FS2W_LVB)
1837#define bfin_write_EPPI2_FS2W_LVB(val) bfin_write32(EPPI2_FS2W_LVB, val)
1838#define bfin_read_EPPI2_FS2P_LAVF() bfin_read32(EPPI2_FS2P_LAVF)
1839#define bfin_write_EPPI2_FS2P_LAVF(val) bfin_write32(EPPI2_FS2P_LAVF, val)
1840#define bfin_read_EPPI2_CLIP() bfin_read32(EPPI2_CLIP)
1841#define bfin_write_EPPI2_CLIP(val) bfin_write32(EPPI2_CLIP, val)
1842
1843/* CAN Controller 0 Config 1 Registers */
1844
1845#define bfin_read_CAN0_MC1() bfin_read16(CAN0_MC1)
1846#define bfin_write_CAN0_MC1(val) bfin_write16(CAN0_MC1, val)
1847#define bfin_read_CAN0_MD1() bfin_read16(CAN0_MD1)
1848#define bfin_write_CAN0_MD1(val) bfin_write16(CAN0_MD1, val)
1849#define bfin_read_CAN0_TRS1() bfin_read16(CAN0_TRS1)
1850#define bfin_write_CAN0_TRS1(val) bfin_write16(CAN0_TRS1, val)
1851#define bfin_read_CAN0_TRR1() bfin_read16(CAN0_TRR1)
1852#define bfin_write_CAN0_TRR1(val) bfin_write16(CAN0_TRR1, val)
1853#define bfin_read_CAN0_TA1() bfin_read16(CAN0_TA1)
1854#define bfin_write_CAN0_TA1(val) bfin_write16(CAN0_TA1, val)
1855#define bfin_read_CAN0_AA1() bfin_read16(CAN0_AA1)
1856#define bfin_write_CAN0_AA1(val) bfin_write16(CAN0_AA1, val)
1857#define bfin_read_CAN0_RMP1() bfin_read16(CAN0_RMP1)
1858#define bfin_write_CAN0_RMP1(val) bfin_write16(CAN0_RMP1, val)
1859#define bfin_read_CAN0_RML1() bfin_read16(CAN0_RML1)
1860#define bfin_write_CAN0_RML1(val) bfin_write16(CAN0_RML1, val)
1861#define bfin_read_CAN0_MBTIF1() bfin_read16(CAN0_MBTIF1)
1862#define bfin_write_CAN0_MBTIF1(val) bfin_write16(CAN0_MBTIF1, val)
1863#define bfin_read_CAN0_MBRIF1() bfin_read16(CAN0_MBRIF1)
1864#define bfin_write_CAN0_MBRIF1(val) bfin_write16(CAN0_MBRIF1, val)
1865#define bfin_read_CAN0_MBIM1() bfin_read16(CAN0_MBIM1)
1866#define bfin_write_CAN0_MBIM1(val) bfin_write16(CAN0_MBIM1, val)
1867#define bfin_read_CAN0_RFH1() bfin_read16(CAN0_RFH1)
1868#define bfin_write_CAN0_RFH1(val) bfin_write16(CAN0_RFH1, val)
1869#define bfin_read_CAN0_OPSS1() bfin_read16(CAN0_OPSS1)
1870#define bfin_write_CAN0_OPSS1(val) bfin_write16(CAN0_OPSS1, val)
1871
1872/* CAN Controller 0 Config 2 Registers */
1873
1874#define bfin_read_CAN0_MC2() bfin_read16(CAN0_MC2)
1875#define bfin_write_CAN0_MC2(val) bfin_write16(CAN0_MC2, val)
1876#define bfin_read_CAN0_MD2() bfin_read16(CAN0_MD2)
1877#define bfin_write_CAN0_MD2(val) bfin_write16(CAN0_MD2, val)
1878#define bfin_read_CAN0_TRS2() bfin_read16(CAN0_TRS2)
1879#define bfin_write_CAN0_TRS2(val) bfin_write16(CAN0_TRS2, val)
1880#define bfin_read_CAN0_TRR2() bfin_read16(CAN0_TRR2)
1881#define bfin_write_CAN0_TRR2(val) bfin_write16(CAN0_TRR2, val)
1882#define bfin_read_CAN0_TA2() bfin_read16(CAN0_TA2)
1883#define bfin_write_CAN0_TA2(val) bfin_write16(CAN0_TA2, val)
1884#define bfin_read_CAN0_AA2() bfin_read16(CAN0_AA2)
1885#define bfin_write_CAN0_AA2(val) bfin_write16(CAN0_AA2, val)
1886#define bfin_read_CAN0_RMP2() bfin_read16(CAN0_RMP2)
1887#define bfin_write_CAN0_RMP2(val) bfin_write16(CAN0_RMP2, val)
1888#define bfin_read_CAN0_RML2() bfin_read16(CAN0_RML2)
1889#define bfin_write_CAN0_RML2(val) bfin_write16(CAN0_RML2, val)
1890#define bfin_read_CAN0_MBTIF2() bfin_read16(CAN0_MBTIF2)
1891#define bfin_write_CAN0_MBTIF2(val) bfin_write16(CAN0_MBTIF2, val)
1892#define bfin_read_CAN0_MBRIF2() bfin_read16(CAN0_MBRIF2)
1893#define bfin_write_CAN0_MBRIF2(val) bfin_write16(CAN0_MBRIF2, val)
1894#define bfin_read_CAN0_MBIM2() bfin_read16(CAN0_MBIM2)
1895#define bfin_write_CAN0_MBIM2(val) bfin_write16(CAN0_MBIM2, val)
1896#define bfin_read_CAN0_RFH2() bfin_read16(CAN0_RFH2)
1897#define bfin_write_CAN0_RFH2(val) bfin_write16(CAN0_RFH2, val)
1898#define bfin_read_CAN0_OPSS2() bfin_read16(CAN0_OPSS2)
1899#define bfin_write_CAN0_OPSS2(val) bfin_write16(CAN0_OPSS2, val)
1900
1901/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
1902
1903#define bfin_read_CAN0_CLOCK() bfin_read16(CAN0_CLOCK)
1904#define bfin_write_CAN0_CLOCK(val) bfin_write16(CAN0_CLOCK, val)
1905#define bfin_read_CAN0_TIMING() bfin_read16(CAN0_TIMING)
1906#define bfin_write_CAN0_TIMING(val) bfin_write16(CAN0_TIMING, val)
1907#define bfin_read_CAN0_DEBUG() bfin_read16(CAN0_DEBUG)
1908#define bfin_write_CAN0_DEBUG(val) bfin_write16(CAN0_DEBUG, val)
1909#define bfin_read_CAN0_STATUS() bfin_read16(CAN0_STATUS)
1910#define bfin_write_CAN0_STATUS(val) bfin_write16(CAN0_STATUS, val)
1911#define bfin_read_CAN0_CEC() bfin_read16(CAN0_CEC)
1912#define bfin_write_CAN0_CEC(val) bfin_write16(CAN0_CEC, val)
1913#define bfin_read_CAN0_GIS() bfin_read16(CAN0_GIS)
1914#define bfin_write_CAN0_GIS(val) bfin_write16(CAN0_GIS, val)
1915#define bfin_read_CAN0_GIM() bfin_read16(CAN0_GIM)
1916#define bfin_write_CAN0_GIM(val) bfin_write16(CAN0_GIM, val)
1917#define bfin_read_CAN0_GIF() bfin_read16(CAN0_GIF)
1918#define bfin_write_CAN0_GIF(val) bfin_write16(CAN0_GIF, val)
1919#define bfin_read_CAN0_CONTROL() bfin_read16(CAN0_CONTROL)
1920#define bfin_write_CAN0_CONTROL(val) bfin_write16(CAN0_CONTROL, val)
1921#define bfin_read_CAN0_INTR() bfin_read16(CAN0_INTR)
1922#define bfin_write_CAN0_INTR(val) bfin_write16(CAN0_INTR, val)
1923#define bfin_read_CAN0_MBTD() bfin_read16(CAN0_MBTD)
1924#define bfin_write_CAN0_MBTD(val) bfin_write16(CAN0_MBTD, val)
1925#define bfin_read_CAN0_EWR() bfin_read16(CAN0_EWR)
1926#define bfin_write_CAN0_EWR(val) bfin_write16(CAN0_EWR, val)
1927#define bfin_read_CAN0_ESR() bfin_read16(CAN0_ESR)
1928#define bfin_write_CAN0_ESR(val) bfin_write16(CAN0_ESR, val)
1929#define bfin_read_CAN0_UCCNT() bfin_read16(CAN0_UCCNT)
1930#define bfin_write_CAN0_UCCNT(val) bfin_write16(CAN0_UCCNT, val)
1931#define bfin_read_CAN0_UCRC() bfin_read16(CAN0_UCRC)
1932#define bfin_write_CAN0_UCRC(val) bfin_write16(CAN0_UCRC, val)
1933#define bfin_read_CAN0_UCCNF() bfin_read16(CAN0_UCCNF)
1934#define bfin_write_CAN0_UCCNF(val) bfin_write16(CAN0_UCCNF, val)
1935
1936/* CAN Controller 0 Accebfin_read_()tance Registers */
1937
1938#define bfin_read_CAN0_AM00L() bfin_read16(CAN0_AM00L)
1939#define bfin_write_CAN0_AM00L(val) bfin_write16(CAN0_AM00L, val)
1940#define bfin_read_CAN0_AM00H() bfin_read16(CAN0_AM00H)
1941#define bfin_write_CAN0_AM00H(val) bfin_write16(CAN0_AM00H, val)
1942#define bfin_read_CAN0_AM01L() bfin_read16(CAN0_AM01L)
1943#define bfin_write_CAN0_AM01L(val) bfin_write16(CAN0_AM01L, val)
1944#define bfin_read_CAN0_AM01H() bfin_read16(CAN0_AM01H)
1945#define bfin_write_CAN0_AM01H(val) bfin_write16(CAN0_AM01H, val)
1946#define bfin_read_CAN0_AM02L() bfin_read16(CAN0_AM02L)
1947#define bfin_write_CAN0_AM02L(val) bfin_write16(CAN0_AM02L, val)
1948#define bfin_read_CAN0_AM02H() bfin_read16(CAN0_AM02H)
1949#define bfin_write_CAN0_AM02H(val) bfin_write16(CAN0_AM02H, val)
1950#define bfin_read_CAN0_AM03L() bfin_read16(CAN0_AM03L)
1951#define bfin_write_CAN0_AM03L(val) bfin_write16(CAN0_AM03L, val)
1952#define bfin_read_CAN0_AM03H() bfin_read16(CAN0_AM03H)
1953#define bfin_write_CAN0_AM03H(val) bfin_write16(CAN0_AM03H, val)
1954#define bfin_read_CAN0_AM04L() bfin_read16(CAN0_AM04L)
1955#define bfin_write_CAN0_AM04L(val) bfin_write16(CAN0_AM04L, val)
1956#define bfin_read_CAN0_AM04H() bfin_read16(CAN0_AM04H)
1957#define bfin_write_CAN0_AM04H(val) bfin_write16(CAN0_AM04H, val)
1958#define bfin_read_CAN0_AM05L() bfin_read16(CAN0_AM05L)
1959#define bfin_write_CAN0_AM05L(val) bfin_write16(CAN0_AM05L, val)
1960#define bfin_read_CAN0_AM05H() bfin_read16(CAN0_AM05H)
1961#define bfin_write_CAN0_AM05H(val) bfin_write16(CAN0_AM05H, val)
1962#define bfin_read_CAN0_AM06L() bfin_read16(CAN0_AM06L)
1963#define bfin_write_CAN0_AM06L(val) bfin_write16(CAN0_AM06L, val)
1964#define bfin_read_CAN0_AM06H() bfin_read16(CAN0_AM06H)
1965#define bfin_write_CAN0_AM06H(val) bfin_write16(CAN0_AM06H, val)
1966#define bfin_read_CAN0_AM07L() bfin_read16(CAN0_AM07L)
1967#define bfin_write_CAN0_AM07L(val) bfin_write16(CAN0_AM07L, val)
1968#define bfin_read_CAN0_AM07H() bfin_read16(CAN0_AM07H)
1969#define bfin_write_CAN0_AM07H(val) bfin_write16(CAN0_AM07H, val)
1970#define bfin_read_CAN0_AM08L() bfin_read16(CAN0_AM08L)
1971#define bfin_write_CAN0_AM08L(val) bfin_write16(CAN0_AM08L, val)
1972#define bfin_read_CAN0_AM08H() bfin_read16(CAN0_AM08H)
1973#define bfin_write_CAN0_AM08H(val) bfin_write16(CAN0_AM08H, val)
1974#define bfin_read_CAN0_AM09L() bfin_read16(CAN0_AM09L)
1975#define bfin_write_CAN0_AM09L(val) bfin_write16(CAN0_AM09L, val)
1976#define bfin_read_CAN0_AM09H() bfin_read16(CAN0_AM09H)
1977#define bfin_write_CAN0_AM09H(val) bfin_write16(CAN0_AM09H, val)
1978#define bfin_read_CAN0_AM10L() bfin_read16(CAN0_AM10L)
1979#define bfin_write_CAN0_AM10L(val) bfin_write16(CAN0_AM10L, val)
1980#define bfin_read_CAN0_AM10H() bfin_read16(CAN0_AM10H)
1981#define bfin_write_CAN0_AM10H(val) bfin_write16(CAN0_AM10H, val)
1982#define bfin_read_CAN0_AM11L() bfin_read16(CAN0_AM11L)
1983#define bfin_write_CAN0_AM11L(val) bfin_write16(CAN0_AM11L, val)
1984#define bfin_read_CAN0_AM11H() bfin_read16(CAN0_AM11H)
1985#define bfin_write_CAN0_AM11H(val) bfin_write16(CAN0_AM11H, val)
1986#define bfin_read_CAN0_AM12L() bfin_read16(CAN0_AM12L)
1987#define bfin_write_CAN0_AM12L(val) bfin_write16(CAN0_AM12L, val)
1988#define bfin_read_CAN0_AM12H() bfin_read16(CAN0_AM12H)
1989#define bfin_write_CAN0_AM12H(val) bfin_write16(CAN0_AM12H, val)
1990#define bfin_read_CAN0_AM13L() bfin_read16(CAN0_AM13L)
1991#define bfin_write_CAN0_AM13L(val) bfin_write16(CAN0_AM13L, val)
1992#define bfin_read_CAN0_AM13H() bfin_read16(CAN0_AM13H)
1993#define bfin_write_CAN0_AM13H(val) bfin_write16(CAN0_AM13H, val)
1994#define bfin_read_CAN0_AM14L() bfin_read16(CAN0_AM14L)
1995#define bfin_write_CAN0_AM14L(val) bfin_write16(CAN0_AM14L, val)
1996#define bfin_read_CAN0_AM14H() bfin_read16(CAN0_AM14H)
1997#define bfin_write_CAN0_AM14H(val) bfin_write16(CAN0_AM14H, val)
1998#define bfin_read_CAN0_AM15L() bfin_read16(CAN0_AM15L)
1999#define bfin_write_CAN0_AM15L(val) bfin_write16(CAN0_AM15L, val)
2000#define bfin_read_CAN0_AM15H() bfin_read16(CAN0_AM15H)
2001#define bfin_write_CAN0_AM15H(val) bfin_write16(CAN0_AM15H, val)
2002
2003/* CAN Controller 0 Accebfin_read_()tance Registers */
2004
2005#define bfin_read_CAN0_AM16L() bfin_read16(CAN0_AM16L)
2006#define bfin_write_CAN0_AM16L(val) bfin_write16(CAN0_AM16L, val)
2007#define bfin_read_CAN0_AM16H() bfin_read16(CAN0_AM16H)
2008#define bfin_write_CAN0_AM16H(val) bfin_write16(CAN0_AM16H, val)
2009#define bfin_read_CAN0_AM17L() bfin_read16(CAN0_AM17L)
2010#define bfin_write_CAN0_AM17L(val) bfin_write16(CAN0_AM17L, val)
2011#define bfin_read_CAN0_AM17H() bfin_read16(CAN0_AM17H)
2012#define bfin_write_CAN0_AM17H(val) bfin_write16(CAN0_AM17H, val)
2013#define bfin_read_CAN0_AM18L() bfin_read16(CAN0_AM18L)
2014#define bfin_write_CAN0_AM18L(val) bfin_write16(CAN0_AM18L, val)
2015#define bfin_read_CAN0_AM18H() bfin_read16(CAN0_AM18H)
2016#define bfin_write_CAN0_AM18H(val) bfin_write16(CAN0_AM18H, val)
2017#define bfin_read_CAN0_AM19L() bfin_read16(CAN0_AM19L)
2018#define bfin_write_CAN0_AM19L(val) bfin_write16(CAN0_AM19L, val)
2019#define bfin_read_CAN0_AM19H() bfin_read16(CAN0_AM19H)
2020#define bfin_write_CAN0_AM19H(val) bfin_write16(CAN0_AM19H, val)
2021#define bfin_read_CAN0_AM20L() bfin_read16(CAN0_AM20L)
2022#define bfin_write_CAN0_AM20L(val) bfin_write16(CAN0_AM20L, val)
2023#define bfin_read_CAN0_AM20H() bfin_read16(CAN0_AM20H)
2024#define bfin_write_CAN0_AM20H(val) bfin_write16(CAN0_AM20H, val)
2025#define bfin_read_CAN0_AM21L() bfin_read16(CAN0_AM21L)
2026#define bfin_write_CAN0_AM21L(val) bfin_write16(CAN0_AM21L, val)
2027#define bfin_read_CAN0_AM21H() bfin_read16(CAN0_AM21H)
2028#define bfin_write_CAN0_AM21H(val) bfin_write16(CAN0_AM21H, val)
2029#define bfin_read_CAN0_AM22L() bfin_read16(CAN0_AM22L)
2030#define bfin_write_CAN0_AM22L(val) bfin_write16(CAN0_AM22L, val)
2031#define bfin_read_CAN0_AM22H() bfin_read16(CAN0_AM22H)
2032#define bfin_write_CAN0_AM22H(val) bfin_write16(CAN0_AM22H, val)
2033#define bfin_read_CAN0_AM23L() bfin_read16(CAN0_AM23L)
2034#define bfin_write_CAN0_AM23L(val) bfin_write16(CAN0_AM23L, val)
2035#define bfin_read_CAN0_AM23H() bfin_read16(CAN0_AM23H)
2036#define bfin_write_CAN0_AM23H(val) bfin_write16(CAN0_AM23H, val)
2037#define bfin_read_CAN0_AM24L() bfin_read16(CAN0_AM24L)
2038#define bfin_write_CAN0_AM24L(val) bfin_write16(CAN0_AM24L, val)
2039#define bfin_read_CAN0_AM24H() bfin_read16(CAN0_AM24H)
2040#define bfin_write_CAN0_AM24H(val) bfin_write16(CAN0_AM24H, val)
2041#define bfin_read_CAN0_AM25L() bfin_read16(CAN0_AM25L)
2042#define bfin_write_CAN0_AM25L(val) bfin_write16(CAN0_AM25L, val)
2043#define bfin_read_CAN0_AM25H() bfin_read16(CAN0_AM25H)
2044#define bfin_write_CAN0_AM25H(val) bfin_write16(CAN0_AM25H, val)
2045#define bfin_read_CAN0_AM26L() bfin_read16(CAN0_AM26L)
2046#define bfin_write_CAN0_AM26L(val) bfin_write16(CAN0_AM26L, val)
2047#define bfin_read_CAN0_AM26H() bfin_read16(CAN0_AM26H)
2048#define bfin_write_CAN0_AM26H(val) bfin_write16(CAN0_AM26H, val)
2049#define bfin_read_CAN0_AM27L() bfin_read16(CAN0_AM27L)
2050#define bfin_write_CAN0_AM27L(val) bfin_write16(CAN0_AM27L, val)
2051#define bfin_read_CAN0_AM27H() bfin_read16(CAN0_AM27H)
2052#define bfin_write_CAN0_AM27H(val) bfin_write16(CAN0_AM27H, val)
2053#define bfin_read_CAN0_AM28L() bfin_read16(CAN0_AM28L)
2054#define bfin_write_CAN0_AM28L(val) bfin_write16(CAN0_AM28L, val)
2055#define bfin_read_CAN0_AM28H() bfin_read16(CAN0_AM28H)
2056#define bfin_write_CAN0_AM28H(val) bfin_write16(CAN0_AM28H, val)
2057#define bfin_read_CAN0_AM29L() bfin_read16(CAN0_AM29L)
2058#define bfin_write_CAN0_AM29L(val) bfin_write16(CAN0_AM29L, val)
2059#define bfin_read_CAN0_AM29H() bfin_read16(CAN0_AM29H)
2060#define bfin_write_CAN0_AM29H(val) bfin_write16(CAN0_AM29H, val)
2061#define bfin_read_CAN0_AM30L() bfin_read16(CAN0_AM30L)
2062#define bfin_write_CAN0_AM30L(val) bfin_write16(CAN0_AM30L, val)
2063#define bfin_read_CAN0_AM30H() bfin_read16(CAN0_AM30H)
2064#define bfin_write_CAN0_AM30H(val) bfin_write16(CAN0_AM30H, val)
2065#define bfin_read_CAN0_AM31L() bfin_read16(CAN0_AM31L)
2066#define bfin_write_CAN0_AM31L(val) bfin_write16(CAN0_AM31L, val)
2067#define bfin_read_CAN0_AM31H() bfin_read16(CAN0_AM31H)
2068#define bfin_write_CAN0_AM31H(val) bfin_write16(CAN0_AM31H, val)
2069
2070/* CAN Controller 0 Mailbox Data Registers */
2071
2072#define bfin_read_CAN0_MB00_DATA0() bfin_read16(CAN0_MB00_DATA0)
2073#define bfin_write_CAN0_MB00_DATA0(val) bfin_write16(CAN0_MB00_DATA0, val)
2074#define bfin_read_CAN0_MB00_DATA1() bfin_read16(CAN0_MB00_DATA1)
2075#define bfin_write_CAN0_MB00_DATA1(val) bfin_write16(CAN0_MB00_DATA1, val)
2076#define bfin_read_CAN0_MB00_DATA2() bfin_read16(CAN0_MB00_DATA2)
2077#define bfin_write_CAN0_MB00_DATA2(val) bfin_write16(CAN0_MB00_DATA2, val)
2078#define bfin_read_CAN0_MB00_DATA3() bfin_read16(CAN0_MB00_DATA3)
2079#define bfin_write_CAN0_MB00_DATA3(val) bfin_write16(CAN0_MB00_DATA3, val)
2080#define bfin_read_CAN0_MB00_LENGTH() bfin_read16(CAN0_MB00_LENGTH)
2081#define bfin_write_CAN0_MB00_LENGTH(val) bfin_write16(CAN0_MB00_LENGTH, val)
2082#define bfin_read_CAN0_MB00_TIMESTAMP() bfin_read16(CAN0_MB00_TIMESTAMP)
2083#define bfin_write_CAN0_MB00_TIMESTAMP(val) bfin_write16(CAN0_MB00_TIMESTAMP, val)
2084#define bfin_read_CAN0_MB00_ID0() bfin_read16(CAN0_MB00_ID0)
2085#define bfin_write_CAN0_MB00_ID0(val) bfin_write16(CAN0_MB00_ID0, val)
2086#define bfin_read_CAN0_MB00_ID1() bfin_read16(CAN0_MB00_ID1)
2087#define bfin_write_CAN0_MB00_ID1(val) bfin_write16(CAN0_MB00_ID1, val)
2088#define bfin_read_CAN0_MB01_DATA0() bfin_read16(CAN0_MB01_DATA0)
2089#define bfin_write_CAN0_MB01_DATA0(val) bfin_write16(CAN0_MB01_DATA0, val)
2090#define bfin_read_CAN0_MB01_DATA1() bfin_read16(CAN0_MB01_DATA1)
2091#define bfin_write_CAN0_MB01_DATA1(val) bfin_write16(CAN0_MB01_DATA1, val)
2092#define bfin_read_CAN0_MB01_DATA2() bfin_read16(CAN0_MB01_DATA2)
2093#define bfin_write_CAN0_MB01_DATA2(val) bfin_write16(CAN0_MB01_DATA2, val)
2094#define bfin_read_CAN0_MB01_DATA3() bfin_read16(CAN0_MB01_DATA3)
2095#define bfin_write_CAN0_MB01_DATA3(val) bfin_write16(CAN0_MB01_DATA3, val)
2096#define bfin_read_CAN0_MB01_LENGTH() bfin_read16(CAN0_MB01_LENGTH)
2097#define bfin_write_CAN0_MB01_LENGTH(val) bfin_write16(CAN0_MB01_LENGTH, val)
2098#define bfin_read_CAN0_MB01_TIMESTAMP() bfin_read16(CAN0_MB01_TIMESTAMP)
2099#define bfin_write_CAN0_MB01_TIMESTAMP(val) bfin_write16(CAN0_MB01_TIMESTAMP, val)
2100#define bfin_read_CAN0_MB01_ID0() bfin_read16(CAN0_MB01_ID0)
2101#define bfin_write_CAN0_MB01_ID0(val) bfin_write16(CAN0_MB01_ID0, val)
2102#define bfin_read_CAN0_MB01_ID1() bfin_read16(CAN0_MB01_ID1)
2103#define bfin_write_CAN0_MB01_ID1(val) bfin_write16(CAN0_MB01_ID1, val)
2104#define bfin_read_CAN0_MB02_DATA0() bfin_read16(CAN0_MB02_DATA0)
2105#define bfin_write_CAN0_MB02_DATA0(val) bfin_write16(CAN0_MB02_DATA0, val)
2106#define bfin_read_CAN0_MB02_DATA1() bfin_read16(CAN0_MB02_DATA1)
2107#define bfin_write_CAN0_MB02_DATA1(val) bfin_write16(CAN0_MB02_DATA1, val)
2108#define bfin_read_CAN0_MB02_DATA2() bfin_read16(CAN0_MB02_DATA2)
2109#define bfin_write_CAN0_MB02_DATA2(val) bfin_write16(CAN0_MB02_DATA2, val)
2110#define bfin_read_CAN0_MB02_DATA3() bfin_read16(CAN0_MB02_DATA3)
2111#define bfin_write_CAN0_MB02_DATA3(val) bfin_write16(CAN0_MB02_DATA3, val)
2112#define bfin_read_CAN0_MB02_LENGTH() bfin_read16(CAN0_MB02_LENGTH)
2113#define bfin_write_CAN0_MB02_LENGTH(val) bfin_write16(CAN0_MB02_LENGTH, val)
2114#define bfin_read_CAN0_MB02_TIMESTAMP() bfin_read16(CAN0_MB02_TIMESTAMP)
2115#define bfin_write_CAN0_MB02_TIMESTAMP(val) bfin_write16(CAN0_MB02_TIMESTAMP, val)
2116#define bfin_read_CAN0_MB02_ID0() bfin_read16(CAN0_MB02_ID0)
2117#define bfin_write_CAN0_MB02_ID0(val) bfin_write16(CAN0_MB02_ID0, val)
2118#define bfin_read_CAN0_MB02_ID1() bfin_read16(CAN0_MB02_ID1)
2119#define bfin_write_CAN0_MB02_ID1(val) bfin_write16(CAN0_MB02_ID1, val)
2120#define bfin_read_CAN0_MB03_DATA0() bfin_read16(CAN0_MB03_DATA0)
2121#define bfin_write_CAN0_MB03_DATA0(val) bfin_write16(CAN0_MB03_DATA0, val)
2122#define bfin_read_CAN0_MB03_DATA1() bfin_read16(CAN0_MB03_DATA1)
2123#define bfin_write_CAN0_MB03_DATA1(val) bfin_write16(CAN0_MB03_DATA1, val)
2124#define bfin_read_CAN0_MB03_DATA2() bfin_read16(CAN0_MB03_DATA2)
2125#define bfin_write_CAN0_MB03_DATA2(val) bfin_write16(CAN0_MB03_DATA2, val)
2126#define bfin_read_CAN0_MB03_DATA3() bfin_read16(CAN0_MB03_DATA3)
2127#define bfin_write_CAN0_MB03_DATA3(val) bfin_write16(CAN0_MB03_DATA3, val)
2128#define bfin_read_CAN0_MB03_LENGTH() bfin_read16(CAN0_MB03_LENGTH)
2129#define bfin_write_CAN0_MB03_LENGTH(val) bfin_write16(CAN0_MB03_LENGTH, val)
2130#define bfin_read_CAN0_MB03_TIMESTAMP() bfin_read16(CAN0_MB03_TIMESTAMP)
2131#define bfin_write_CAN0_MB03_TIMESTAMP(val) bfin_write16(CAN0_MB03_TIMESTAMP, val)
2132#define bfin_read_CAN0_MB03_ID0() bfin_read16(CAN0_MB03_ID0)
2133#define bfin_write_CAN0_MB03_ID0(val) bfin_write16(CAN0_MB03_ID0, val)
2134#define bfin_read_CAN0_MB03_ID1() bfin_read16(CAN0_MB03_ID1)
2135#define bfin_write_CAN0_MB03_ID1(val) bfin_write16(CAN0_MB03_ID1, val)
2136#define bfin_read_CAN0_MB04_DATA0() bfin_read16(CAN0_MB04_DATA0)
2137#define bfin_write_CAN0_MB04_DATA0(val) bfin_write16(CAN0_MB04_DATA0, val)
2138#define bfin_read_CAN0_MB04_DATA1() bfin_read16(CAN0_MB04_DATA1)
2139#define bfin_write_CAN0_MB04_DATA1(val) bfin_write16(CAN0_MB04_DATA1, val)
2140#define bfin_read_CAN0_MB04_DATA2() bfin_read16(CAN0_MB04_DATA2)
2141#define bfin_write_CAN0_MB04_DATA2(val) bfin_write16(CAN0_MB04_DATA2, val)
2142#define bfin_read_CAN0_MB04_DATA3() bfin_read16(CAN0_MB04_DATA3)
2143#define bfin_write_CAN0_MB04_DATA3(val) bfin_write16(CAN0_MB04_DATA3, val)
2144#define bfin_read_CAN0_MB04_LENGTH() bfin_read16(CAN0_MB04_LENGTH)
2145#define bfin_write_CAN0_MB04_LENGTH(val) bfin_write16(CAN0_MB04_LENGTH, val)
2146#define bfin_read_CAN0_MB04_TIMESTAMP() bfin_read16(CAN0_MB04_TIMESTAMP)
2147#define bfin_write_CAN0_MB04_TIMESTAMP(val) bfin_write16(CAN0_MB04_TIMESTAMP, val)
2148#define bfin_read_CAN0_MB04_ID0() bfin_read16(CAN0_MB04_ID0)
2149#define bfin_write_CAN0_MB04_ID0(val) bfin_write16(CAN0_MB04_ID0, val)
2150#define bfin_read_CAN0_MB04_ID1() bfin_read16(CAN0_MB04_ID1)
2151#define bfin_write_CAN0_MB04_ID1(val) bfin_write16(CAN0_MB04_ID1, val)
2152#define bfin_read_CAN0_MB05_DATA0() bfin_read16(CAN0_MB05_DATA0)
2153#define bfin_write_CAN0_MB05_DATA0(val) bfin_write16(CAN0_MB05_DATA0, val)
2154#define bfin_read_CAN0_MB05_DATA1() bfin_read16(CAN0_MB05_DATA1)
2155#define bfin_write_CAN0_MB05_DATA1(val) bfin_write16(CAN0_MB05_DATA1, val)
2156#define bfin_read_CAN0_MB05_DATA2() bfin_read16(CAN0_MB05_DATA2)
2157#define bfin_write_CAN0_MB05_DATA2(val) bfin_write16(CAN0_MB05_DATA2, val)
2158#define bfin_read_CAN0_MB05_DATA3() bfin_read16(CAN0_MB05_DATA3)
2159#define bfin_write_CAN0_MB05_DATA3(val) bfin_write16(CAN0_MB05_DATA3, val)
2160#define bfin_read_CAN0_MB05_LENGTH() bfin_read16(CAN0_MB05_LENGTH)
2161#define bfin_write_CAN0_MB05_LENGTH(val) bfin_write16(CAN0_MB05_LENGTH, val)
2162#define bfin_read_CAN0_MB05_TIMESTAMP() bfin_read16(CAN0_MB05_TIMESTAMP)
2163#define bfin_write_CAN0_MB05_TIMESTAMP(val) bfin_write16(CAN0_MB05_TIMESTAMP, val)
2164#define bfin_read_CAN0_MB05_ID0() bfin_read16(CAN0_MB05_ID0)
2165#define bfin_write_CAN0_MB05_ID0(val) bfin_write16(CAN0_MB05_ID0, val)
2166#define bfin_read_CAN0_MB05_ID1() bfin_read16(CAN0_MB05_ID1)
2167#define bfin_write_CAN0_MB05_ID1(val) bfin_write16(CAN0_MB05_ID1, val)
2168#define bfin_read_CAN0_MB06_DATA0() bfin_read16(CAN0_MB06_DATA0)
2169#define bfin_write_CAN0_MB06_DATA0(val) bfin_write16(CAN0_MB06_DATA0, val)
2170#define bfin_read_CAN0_MB06_DATA1() bfin_read16(CAN0_MB06_DATA1)
2171#define bfin_write_CAN0_MB06_DATA1(val) bfin_write16(CAN0_MB06_DATA1, val)
2172#define bfin_read_CAN0_MB06_DATA2() bfin_read16(CAN0_MB06_DATA2)
2173#define bfin_write_CAN0_MB06_DATA2(val) bfin_write16(CAN0_MB06_DATA2, val)
2174#define bfin_read_CAN0_MB06_DATA3() bfin_read16(CAN0_MB06_DATA3)
2175#define bfin_write_CAN0_MB06_DATA3(val) bfin_write16(CAN0_MB06_DATA3, val)
2176#define bfin_read_CAN0_MB06_LENGTH() bfin_read16(CAN0_MB06_LENGTH)
2177#define bfin_write_CAN0_MB06_LENGTH(val) bfin_write16(CAN0_MB06_LENGTH, val)
2178#define bfin_read_CAN0_MB06_TIMESTAMP() bfin_read16(CAN0_MB06_TIMESTAMP)
2179#define bfin_write_CAN0_MB06_TIMESTAMP(val) bfin_write16(CAN0_MB06_TIMESTAMP, val)
2180#define bfin_read_CAN0_MB06_ID0() bfin_read16(CAN0_MB06_ID0)
2181#define bfin_write_CAN0_MB06_ID0(val) bfin_write16(CAN0_MB06_ID0, val)
2182#define bfin_read_CAN0_MB06_ID1() bfin_read16(CAN0_MB06_ID1)
2183#define bfin_write_CAN0_MB06_ID1(val) bfin_write16(CAN0_MB06_ID1, val)
2184#define bfin_read_CAN0_MB07_DATA0() bfin_read16(CAN0_MB07_DATA0)
2185#define bfin_write_CAN0_MB07_DATA0(val) bfin_write16(CAN0_MB07_DATA0, val)
2186#define bfin_read_CAN0_MB07_DATA1() bfin_read16(CAN0_MB07_DATA1)
2187#define bfin_write_CAN0_MB07_DATA1(val) bfin_write16(CAN0_MB07_DATA1, val)
2188#define bfin_read_CAN0_MB07_DATA2() bfin_read16(CAN0_MB07_DATA2)
2189#define bfin_write_CAN0_MB07_DATA2(val) bfin_write16(CAN0_MB07_DATA2, val)
2190#define bfin_read_CAN0_MB07_DATA3() bfin_read16(CAN0_MB07_DATA3)
2191#define bfin_write_CAN0_MB07_DATA3(val) bfin_write16(CAN0_MB07_DATA3, val)
2192#define bfin_read_CAN0_MB07_LENGTH() bfin_read16(CAN0_MB07_LENGTH)
2193#define bfin_write_CAN0_MB07_LENGTH(val) bfin_write16(CAN0_MB07_LENGTH, val)
2194#define bfin_read_CAN0_MB07_TIMESTAMP() bfin_read16(CAN0_MB07_TIMESTAMP)
2195#define bfin_write_CAN0_MB07_TIMESTAMP(val) bfin_write16(CAN0_MB07_TIMESTAMP, val)
2196#define bfin_read_CAN0_MB07_ID0() bfin_read16(CAN0_MB07_ID0)
2197#define bfin_write_CAN0_MB07_ID0(val) bfin_write16(CAN0_MB07_ID0, val)
2198#define bfin_read_CAN0_MB07_ID1() bfin_read16(CAN0_MB07_ID1)
2199#define bfin_write_CAN0_MB07_ID1(val) bfin_write16(CAN0_MB07_ID1, val)
2200#define bfin_read_CAN0_MB08_DATA0() bfin_read16(CAN0_MB08_DATA0)
2201#define bfin_write_CAN0_MB08_DATA0(val) bfin_write16(CAN0_MB08_DATA0, val)
2202#define bfin_read_CAN0_MB08_DATA1() bfin_read16(CAN0_MB08_DATA1)
2203#define bfin_write_CAN0_MB08_DATA1(val) bfin_write16(CAN0_MB08_DATA1, val)
2204#define bfin_read_CAN0_MB08_DATA2() bfin_read16(CAN0_MB08_DATA2)
2205#define bfin_write_CAN0_MB08_DATA2(val) bfin_write16(CAN0_MB08_DATA2, val)
2206#define bfin_read_CAN0_MB08_DATA3() bfin_read16(CAN0_MB08_DATA3)
2207#define bfin_write_CAN0_MB08_DATA3(val) bfin_write16(CAN0_MB08_DATA3, val)
2208#define bfin_read_CAN0_MB08_LENGTH() bfin_read16(CAN0_MB08_LENGTH)
2209#define bfin_write_CAN0_MB08_LENGTH(val) bfin_write16(CAN0_MB08_LENGTH, val)
2210#define bfin_read_CAN0_MB08_TIMESTAMP() bfin_read16(CAN0_MB08_TIMESTAMP)
2211#define bfin_write_CAN0_MB08_TIMESTAMP(val) bfin_write16(CAN0_MB08_TIMESTAMP, val)
2212#define bfin_read_CAN0_MB08_ID0() bfin_read16(CAN0_MB08_ID0)
2213#define bfin_write_CAN0_MB08_ID0(val) bfin_write16(CAN0_MB08_ID0, val)
2214#define bfin_read_CAN0_MB08_ID1() bfin_read16(CAN0_MB08_ID1)
2215#define bfin_write_CAN0_MB08_ID1(val) bfin_write16(CAN0_MB08_ID1, val)
2216#define bfin_read_CAN0_MB09_DATA0() bfin_read16(CAN0_MB09_DATA0)
2217#define bfin_write_CAN0_MB09_DATA0(val) bfin_write16(CAN0_MB09_DATA0, val)
2218#define bfin_read_CAN0_MB09_DATA1() bfin_read16(CAN0_MB09_DATA1)
2219#define bfin_write_CAN0_MB09_DATA1(val) bfin_write16(CAN0_MB09_DATA1, val)
2220#define bfin_read_CAN0_MB09_DATA2() bfin_read16(CAN0_MB09_DATA2)
2221#define bfin_write_CAN0_MB09_DATA2(val) bfin_write16(CAN0_MB09_DATA2, val)
2222#define bfin_read_CAN0_MB09_DATA3() bfin_read16(CAN0_MB09_DATA3)
2223#define bfin_write_CAN0_MB09_DATA3(val) bfin_write16(CAN0_MB09_DATA3, val)
2224#define bfin_read_CAN0_MB09_LENGTH() bfin_read16(CAN0_MB09_LENGTH)
2225#define bfin_write_CAN0_MB09_LENGTH(val) bfin_write16(CAN0_MB09_LENGTH, val)
2226#define bfin_read_CAN0_MB09_TIMESTAMP() bfin_read16(CAN0_MB09_TIMESTAMP)
2227#define bfin_write_CAN0_MB09_TIMESTAMP(val) bfin_write16(CAN0_MB09_TIMESTAMP, val)
2228#define bfin_read_CAN0_MB09_ID0() bfin_read16(CAN0_MB09_ID0)
2229#define bfin_write_CAN0_MB09_ID0(val) bfin_write16(CAN0_MB09_ID0, val)
2230#define bfin_read_CAN0_MB09_ID1() bfin_read16(CAN0_MB09_ID1)
2231#define bfin_write_CAN0_MB09_ID1(val) bfin_write16(CAN0_MB09_ID1, val)
2232#define bfin_read_CAN0_MB10_DATA0() bfin_read16(CAN0_MB10_DATA0)
2233#define bfin_write_CAN0_MB10_DATA0(val) bfin_write16(CAN0_MB10_DATA0, val)
2234#define bfin_read_CAN0_MB10_DATA1() bfin_read16(CAN0_MB10_DATA1)
2235#define bfin_write_CAN0_MB10_DATA1(val) bfin_write16(CAN0_MB10_DATA1, val)
2236#define bfin_read_CAN0_MB10_DATA2() bfin_read16(CAN0_MB10_DATA2)
2237#define bfin_write_CAN0_MB10_DATA2(val) bfin_write16(CAN0_MB10_DATA2, val)
2238#define bfin_read_CAN0_MB10_DATA3() bfin_read16(CAN0_MB10_DATA3)
2239#define bfin_write_CAN0_MB10_DATA3(val) bfin_write16(CAN0_MB10_DATA3, val)
2240#define bfin_read_CAN0_MB10_LENGTH() bfin_read16(CAN0_MB10_LENGTH)
2241#define bfin_write_CAN0_MB10_LENGTH(val) bfin_write16(CAN0_MB10_LENGTH, val)
2242#define bfin_read_CAN0_MB10_TIMESTAMP() bfin_read16(CAN0_MB10_TIMESTAMP)
2243#define bfin_write_CAN0_MB10_TIMESTAMP(val) bfin_write16(CAN0_MB10_TIMESTAMP, val)
2244#define bfin_read_CAN0_MB10_ID0() bfin_read16(CAN0_MB10_ID0)
2245#define bfin_write_CAN0_MB10_ID0(val) bfin_write16(CAN0_MB10_ID0, val)
2246#define bfin_read_CAN0_MB10_ID1() bfin_read16(CAN0_MB10_ID1)
2247#define bfin_write_CAN0_MB10_ID1(val) bfin_write16(CAN0_MB10_ID1, val)
2248#define bfin_read_CAN0_MB11_DATA0() bfin_read16(CAN0_MB11_DATA0)
2249#define bfin_write_CAN0_MB11_DATA0(val) bfin_write16(CAN0_MB11_DATA0, val)
2250#define bfin_read_CAN0_MB11_DATA1() bfin_read16(CAN0_MB11_DATA1)
2251#define bfin_write_CAN0_MB11_DATA1(val) bfin_write16(CAN0_MB11_DATA1, val)
2252#define bfin_read_CAN0_MB11_DATA2() bfin_read16(CAN0_MB11_DATA2)
2253#define bfin_write_CAN0_MB11_DATA2(val) bfin_write16(CAN0_MB11_DATA2, val)
2254#define bfin_read_CAN0_MB11_DATA3() bfin_read16(CAN0_MB11_DATA3)
2255#define bfin_write_CAN0_MB11_DATA3(val) bfin_write16(CAN0_MB11_DATA3, val)
2256#define bfin_read_CAN0_MB11_LENGTH() bfin_read16(CAN0_MB11_LENGTH)
2257#define bfin_write_CAN0_MB11_LENGTH(val) bfin_write16(CAN0_MB11_LENGTH, val)
2258#define bfin_read_CAN0_MB11_TIMESTAMP() bfin_read16(CAN0_MB11_TIMESTAMP)
2259#define bfin_write_CAN0_MB11_TIMESTAMP(val) bfin_write16(CAN0_MB11_TIMESTAMP, val)
2260#define bfin_read_CAN0_MB11_ID0() bfin_read16(CAN0_MB11_ID0)
2261#define bfin_write_CAN0_MB11_ID0(val) bfin_write16(CAN0_MB11_ID0, val)
2262#define bfin_read_CAN0_MB11_ID1() bfin_read16(CAN0_MB11_ID1)
2263#define bfin_write_CAN0_MB11_ID1(val) bfin_write16(CAN0_MB11_ID1, val)
2264#define bfin_read_CAN0_MB12_DATA0() bfin_read16(CAN0_MB12_DATA0)
2265#define bfin_write_CAN0_MB12_DATA0(val) bfin_write16(CAN0_MB12_DATA0, val)
2266#define bfin_read_CAN0_MB12_DATA1() bfin_read16(CAN0_MB12_DATA1)
2267#define bfin_write_CAN0_MB12_DATA1(val) bfin_write16(CAN0_MB12_DATA1, val)
2268#define bfin_read_CAN0_MB12_DATA2() bfin_read16(CAN0_MB12_DATA2)
2269#define bfin_write_CAN0_MB12_DATA2(val) bfin_write16(CAN0_MB12_DATA2, val)
2270#define bfin_read_CAN0_MB12_DATA3() bfin_read16(CAN0_MB12_DATA3)
2271#define bfin_write_CAN0_MB12_DATA3(val) bfin_write16(CAN0_MB12_DATA3, val)
2272#define bfin_read_CAN0_MB12_LENGTH() bfin_read16(CAN0_MB12_LENGTH)
2273#define bfin_write_CAN0_MB12_LENGTH(val) bfin_write16(CAN0_MB12_LENGTH, val)
2274#define bfin_read_CAN0_MB12_TIMESTAMP() bfin_read16(CAN0_MB12_TIMESTAMP)
2275#define bfin_write_CAN0_MB12_TIMESTAMP(val) bfin_write16(CAN0_MB12_TIMESTAMP, val)
2276#define bfin_read_CAN0_MB12_ID0() bfin_read16(CAN0_MB12_ID0)
2277#define bfin_write_CAN0_MB12_ID0(val) bfin_write16(CAN0_MB12_ID0, val)
2278#define bfin_read_CAN0_MB12_ID1() bfin_read16(CAN0_MB12_ID1)
2279#define bfin_write_CAN0_MB12_ID1(val) bfin_write16(CAN0_MB12_ID1, val)
2280#define bfin_read_CAN0_MB13_DATA0() bfin_read16(CAN0_MB13_DATA0)
2281#define bfin_write_CAN0_MB13_DATA0(val) bfin_write16(CAN0_MB13_DATA0, val)
2282#define bfin_read_CAN0_MB13_DATA1() bfin_read16(CAN0_MB13_DATA1)
2283#define bfin_write_CAN0_MB13_DATA1(val) bfin_write16(CAN0_MB13_DATA1, val)
2284#define bfin_read_CAN0_MB13_DATA2() bfin_read16(CAN0_MB13_DATA2)
2285#define bfin_write_CAN0_MB13_DATA2(val) bfin_write16(CAN0_MB13_DATA2, val)
2286#define bfin_read_CAN0_MB13_DATA3() bfin_read16(CAN0_MB13_DATA3)
2287#define bfin_write_CAN0_MB13_DATA3(val) bfin_write16(CAN0_MB13_DATA3, val)
2288#define bfin_read_CAN0_MB13_LENGTH() bfin_read16(CAN0_MB13_LENGTH)
2289#define bfin_write_CAN0_MB13_LENGTH(val) bfin_write16(CAN0_MB13_LENGTH, val)
2290#define bfin_read_CAN0_MB13_TIMESTAMP() bfin_read16(CAN0_MB13_TIMESTAMP)
2291#define bfin_write_CAN0_MB13_TIMESTAMP(val) bfin_write16(CAN0_MB13_TIMESTAMP, val)
2292#define bfin_read_CAN0_MB13_ID0() bfin_read16(CAN0_MB13_ID0)
2293#define bfin_write_CAN0_MB13_ID0(val) bfin_write16(CAN0_MB13_ID0, val)
2294#define bfin_read_CAN0_MB13_ID1() bfin_read16(CAN0_MB13_ID1)
2295#define bfin_write_CAN0_MB13_ID1(val) bfin_write16(CAN0_MB13_ID1, val)
2296#define bfin_read_CAN0_MB14_DATA0() bfin_read16(CAN0_MB14_DATA0)
2297#define bfin_write_CAN0_MB14_DATA0(val) bfin_write16(CAN0_MB14_DATA0, val)
2298#define bfin_read_CAN0_MB14_DATA1() bfin_read16(CAN0_MB14_DATA1)
2299#define bfin_write_CAN0_MB14_DATA1(val) bfin_write16(CAN0_MB14_DATA1, val)
2300#define bfin_read_CAN0_MB14_DATA2() bfin_read16(CAN0_MB14_DATA2)
2301#define bfin_write_CAN0_MB14_DATA2(val) bfin_write16(CAN0_MB14_DATA2, val)
2302#define bfin_read_CAN0_MB14_DATA3() bfin_read16(CAN0_MB14_DATA3)
2303#define bfin_write_CAN0_MB14_DATA3(val) bfin_write16(CAN0_MB14_DATA3, val)
2304#define bfin_read_CAN0_MB14_LENGTH() bfin_read16(CAN0_MB14_LENGTH)
2305#define bfin_write_CAN0_MB14_LENGTH(val) bfin_write16(CAN0_MB14_LENGTH, val)
2306#define bfin_read_CAN0_MB14_TIMESTAMP() bfin_read16(CAN0_MB14_TIMESTAMP)
2307#define bfin_write_CAN0_MB14_TIMESTAMP(val) bfin_write16(CAN0_MB14_TIMESTAMP, val)
2308#define bfin_read_CAN0_MB14_ID0() bfin_read16(CAN0_MB14_ID0)
2309#define bfin_write_CAN0_MB14_ID0(val) bfin_write16(CAN0_MB14_ID0, val)
2310#define bfin_read_CAN0_MB14_ID1() bfin_read16(CAN0_MB14_ID1)
2311#define bfin_write_CAN0_MB14_ID1(val) bfin_write16(CAN0_MB14_ID1, val)
2312#define bfin_read_CAN0_MB15_DATA0() bfin_read16(CAN0_MB15_DATA0)
2313#define bfin_write_CAN0_MB15_DATA0(val) bfin_write16(CAN0_MB15_DATA0, val)
2314#define bfin_read_CAN0_MB15_DATA1() bfin_read16(CAN0_MB15_DATA1)
2315#define bfin_write_CAN0_MB15_DATA1(val) bfin_write16(CAN0_MB15_DATA1, val)
2316#define bfin_read_CAN0_MB15_DATA2() bfin_read16(CAN0_MB15_DATA2)
2317#define bfin_write_CAN0_MB15_DATA2(val) bfin_write16(CAN0_MB15_DATA2, val)
2318#define bfin_read_CAN0_MB15_DATA3() bfin_read16(CAN0_MB15_DATA3)
2319#define bfin_write_CAN0_MB15_DATA3(val) bfin_write16(CAN0_MB15_DATA3, val)
2320#define bfin_read_CAN0_MB15_LENGTH() bfin_read16(CAN0_MB15_LENGTH)
2321#define bfin_write_CAN0_MB15_LENGTH(val) bfin_write16(CAN0_MB15_LENGTH, val)
2322#define bfin_read_CAN0_MB15_TIMESTAMP() bfin_read16(CAN0_MB15_TIMESTAMP)
2323#define bfin_write_CAN0_MB15_TIMESTAMP(val) bfin_write16(CAN0_MB15_TIMESTAMP, val)
2324#define bfin_read_CAN0_MB15_ID0() bfin_read16(CAN0_MB15_ID0)
2325#define bfin_write_CAN0_MB15_ID0(val) bfin_write16(CAN0_MB15_ID0, val)
2326#define bfin_read_CAN0_MB15_ID1() bfin_read16(CAN0_MB15_ID1)
2327#define bfin_write_CAN0_MB15_ID1(val) bfin_write16(CAN0_MB15_ID1, val)
2328
2329/* CAN Controller 0 Mailbox Data Registers */
2330
2331#define bfin_read_CAN0_MB16_DATA0() bfin_read16(CAN0_MB16_DATA0)
2332#define bfin_write_CAN0_MB16_DATA0(val) bfin_write16(CAN0_MB16_DATA0, val)
2333#define bfin_read_CAN0_MB16_DATA1() bfin_read16(CAN0_MB16_DATA1)
2334#define bfin_write_CAN0_MB16_DATA1(val) bfin_write16(CAN0_MB16_DATA1, val)
2335#define bfin_read_CAN0_MB16_DATA2() bfin_read16(CAN0_MB16_DATA2)
2336#define bfin_write_CAN0_MB16_DATA2(val) bfin_write16(CAN0_MB16_DATA2, val)
2337#define bfin_read_CAN0_MB16_DATA3() bfin_read16(CAN0_MB16_DATA3)
2338#define bfin_write_CAN0_MB16_DATA3(val) bfin_write16(CAN0_MB16_DATA3, val)
2339#define bfin_read_CAN0_MB16_LENGTH() bfin_read16(CAN0_MB16_LENGTH)
2340#define bfin_write_CAN0_MB16_LENGTH(val) bfin_write16(CAN0_MB16_LENGTH, val)
2341#define bfin_read_CAN0_MB16_TIMESTAMP() bfin_read16(CAN0_MB16_TIMESTAMP)
2342#define bfin_write_CAN0_MB16_TIMESTAMP(val) bfin_write16(CAN0_MB16_TIMESTAMP, val)
2343#define bfin_read_CAN0_MB16_ID0() bfin_read16(CAN0_MB16_ID0)
2344#define bfin_write_CAN0_MB16_ID0(val) bfin_write16(CAN0_MB16_ID0, val)
2345#define bfin_read_CAN0_MB16_ID1() bfin_read16(CAN0_MB16_ID1)
2346#define bfin_write_CAN0_MB16_ID1(val) bfin_write16(CAN0_MB16_ID1, val)
2347#define bfin_read_CAN0_MB17_DATA0() bfin_read16(CAN0_MB17_DATA0)
2348#define bfin_write_CAN0_MB17_DATA0(val) bfin_write16(CAN0_MB17_DATA0, val)
2349#define bfin_read_CAN0_MB17_DATA1() bfin_read16(CAN0_MB17_DATA1)
2350#define bfin_write_CAN0_MB17_DATA1(val) bfin_write16(CAN0_MB17_DATA1, val)
2351#define bfin_read_CAN0_MB17_DATA2() bfin_read16(CAN0_MB17_DATA2)
2352#define bfin_write_CAN0_MB17_DATA2(val) bfin_write16(CAN0_MB17_DATA2, val)
2353#define bfin_read_CAN0_MB17_DATA3() bfin_read16(CAN0_MB17_DATA3)
2354#define bfin_write_CAN0_MB17_DATA3(val) bfin_write16(CAN0_MB17_DATA3, val)
2355#define bfin_read_CAN0_MB17_LENGTH() bfin_read16(CAN0_MB17_LENGTH)
2356#define bfin_write_CAN0_MB17_LENGTH(val) bfin_write16(CAN0_MB17_LENGTH, val)
2357#define bfin_read_CAN0_MB17_TIMESTAMP() bfin_read16(CAN0_MB17_TIMESTAMP)
2358#define bfin_write_CAN0_MB17_TIMESTAMP(val) bfin_write16(CAN0_MB17_TIMESTAMP, val)
2359#define bfin_read_CAN0_MB17_ID0() bfin_read16(CAN0_MB17_ID0)
2360#define bfin_write_CAN0_MB17_ID0(val) bfin_write16(CAN0_MB17_ID0, val)
2361#define bfin_read_CAN0_MB17_ID1() bfin_read16(CAN0_MB17_ID1)
2362#define bfin_write_CAN0_MB17_ID1(val) bfin_write16(CAN0_MB17_ID1, val)
2363#define bfin_read_CAN0_MB18_DATA0() bfin_read16(CAN0_MB18_DATA0)
2364#define bfin_write_CAN0_MB18_DATA0(val) bfin_write16(CAN0_MB18_DATA0, val)
2365#define bfin_read_CAN0_MB18_DATA1() bfin_read16(CAN0_MB18_DATA1)
2366#define bfin_write_CAN0_MB18_DATA1(val) bfin_write16(CAN0_MB18_DATA1, val)
2367#define bfin_read_CAN0_MB18_DATA2() bfin_read16(CAN0_MB18_DATA2)
2368#define bfin_write_CAN0_MB18_DATA2(val) bfin_write16(CAN0_MB18_DATA2, val)
2369#define bfin_read_CAN0_MB18_DATA3() bfin_read16(CAN0_MB18_DATA3)
2370#define bfin_write_CAN0_MB18_DATA3(val) bfin_write16(CAN0_MB18_DATA3, val)
2371#define bfin_read_CAN0_MB18_LENGTH() bfin_read16(CAN0_MB18_LENGTH)
2372#define bfin_write_CAN0_MB18_LENGTH(val) bfin_write16(CAN0_MB18_LENGTH, val)
2373#define bfin_read_CAN0_MB18_TIMESTAMP() bfin_read16(CAN0_MB18_TIMESTAMP)
2374#define bfin_write_CAN0_MB18_TIMESTAMP(val) bfin_write16(CAN0_MB18_TIMESTAMP, val)
2375#define bfin_read_CAN0_MB18_ID0() bfin_read16(CAN0_MB18_ID0)
2376#define bfin_write_CAN0_MB18_ID0(val) bfin_write16(CAN0_MB18_ID0, val)
2377#define bfin_read_CAN0_MB18_ID1() bfin_read16(CAN0_MB18_ID1)
2378#define bfin_write_CAN0_MB18_ID1(val) bfin_write16(CAN0_MB18_ID1, val)
2379#define bfin_read_CAN0_MB19_DATA0() bfin_read16(CAN0_MB19_DATA0)
2380#define bfin_write_CAN0_MB19_DATA0(val) bfin_write16(CAN0_MB19_DATA0, val)
2381#define bfin_read_CAN0_MB19_DATA1() bfin_read16(CAN0_MB19_DATA1)
2382#define bfin_write_CAN0_MB19_DATA1(val) bfin_write16(CAN0_MB19_DATA1, val)
2383#define bfin_read_CAN0_MB19_DATA2() bfin_read16(CAN0_MB19_DATA2)
2384#define bfin_write_CAN0_MB19_DATA2(val) bfin_write16(CAN0_MB19_DATA2, val)
2385#define bfin_read_CAN0_MB19_DATA3() bfin_read16(CAN0_MB19_DATA3)
2386#define bfin_write_CAN0_MB19_DATA3(val) bfin_write16(CAN0_MB19_DATA3, val)
2387#define bfin_read_CAN0_MB19_LENGTH() bfin_read16(CAN0_MB19_LENGTH)
2388#define bfin_write_CAN0_MB19_LENGTH(val) bfin_write16(CAN0_MB19_LENGTH, val)
2389#define bfin_read_CAN0_MB19_TIMESTAMP() bfin_read16(CAN0_MB19_TIMESTAMP)
2390#define bfin_write_CAN0_MB19_TIMESTAMP(val) bfin_write16(CAN0_MB19_TIMESTAMP, val)
2391#define bfin_read_CAN0_MB19_ID0() bfin_read16(CAN0_MB19_ID0)
2392#define bfin_write_CAN0_MB19_ID0(val) bfin_write16(CAN0_MB19_ID0, val)
2393#define bfin_read_CAN0_MB19_ID1() bfin_read16(CAN0_MB19_ID1)
2394#define bfin_write_CAN0_MB19_ID1(val) bfin_write16(CAN0_MB19_ID1, val)
2395#define bfin_read_CAN0_MB20_DATA0() bfin_read16(CAN0_MB20_DATA0)
2396#define bfin_write_CAN0_MB20_DATA0(val) bfin_write16(CAN0_MB20_DATA0, val)
2397#define bfin_read_CAN0_MB20_DATA1() bfin_read16(CAN0_MB20_DATA1)
2398#define bfin_write_CAN0_MB20_DATA1(val) bfin_write16(CAN0_MB20_DATA1, val)
2399#define bfin_read_CAN0_MB20_DATA2() bfin_read16(CAN0_MB20_DATA2)
2400#define bfin_write_CAN0_MB20_DATA2(val) bfin_write16(CAN0_MB20_DATA2, val)
2401#define bfin_read_CAN0_MB20_DATA3() bfin_read16(CAN0_MB20_DATA3)
2402#define bfin_write_CAN0_MB20_DATA3(val) bfin_write16(CAN0_MB20_DATA3, val)
2403#define bfin_read_CAN0_MB20_LENGTH() bfin_read16(CAN0_MB20_LENGTH)
2404#define bfin_write_CAN0_MB20_LENGTH(val) bfin_write16(CAN0_MB20_LENGTH, val)
2405#define bfin_read_CAN0_MB20_TIMESTAMP() bfin_read16(CAN0_MB20_TIMESTAMP)
2406#define bfin_write_CAN0_MB20_TIMESTAMP(val) bfin_write16(CAN0_MB20_TIMESTAMP, val)
2407#define bfin_read_CAN0_MB20_ID0() bfin_read16(CAN0_MB20_ID0)
2408#define bfin_write_CAN0_MB20_ID0(val) bfin_write16(CAN0_MB20_ID0, val)
2409#define bfin_read_CAN0_MB20_ID1() bfin_read16(CAN0_MB20_ID1)
2410#define bfin_write_CAN0_MB20_ID1(val) bfin_write16(CAN0_MB20_ID1, val)
2411#define bfin_read_CAN0_MB21_DATA0() bfin_read16(CAN0_MB21_DATA0)
2412#define bfin_write_CAN0_MB21_DATA0(val) bfin_write16(CAN0_MB21_DATA0, val)
2413#define bfin_read_CAN0_MB21_DATA1() bfin_read16(CAN0_MB21_DATA1)
2414#define bfin_write_CAN0_MB21_DATA1(val) bfin_write16(CAN0_MB21_DATA1, val)
2415#define bfin_read_CAN0_MB21_DATA2() bfin_read16(CAN0_MB21_DATA2)
2416#define bfin_write_CAN0_MB21_DATA2(val) bfin_write16(CAN0_MB21_DATA2, val)
2417#define bfin_read_CAN0_MB21_DATA3() bfin_read16(CAN0_MB21_DATA3)
2418#define bfin_write_CAN0_MB21_DATA3(val) bfin_write16(CAN0_MB21_DATA3, val)
2419#define bfin_read_CAN0_MB21_LENGTH() bfin_read16(CAN0_MB21_LENGTH)
2420#define bfin_write_CAN0_MB21_LENGTH(val) bfin_write16(CAN0_MB21_LENGTH, val)
2421#define bfin_read_CAN0_MB21_TIMESTAMP() bfin_read16(CAN0_MB21_TIMESTAMP)
2422#define bfin_write_CAN0_MB21_TIMESTAMP(val) bfin_write16(CAN0_MB21_TIMESTAMP, val)
2423#define bfin_read_CAN0_MB21_ID0() bfin_read16(CAN0_MB21_ID0)
2424#define bfin_write_CAN0_MB21_ID0(val) bfin_write16(CAN0_MB21_ID0, val)
2425#define bfin_read_CAN0_MB21_ID1() bfin_read16(CAN0_MB21_ID1)
2426#define bfin_write_CAN0_MB21_ID1(val) bfin_write16(CAN0_MB21_ID1, val)
2427#define bfin_read_CAN0_MB22_DATA0() bfin_read16(CAN0_MB22_DATA0)
2428#define bfin_write_CAN0_MB22_DATA0(val) bfin_write16(CAN0_MB22_DATA0, val)
2429#define bfin_read_CAN0_MB22_DATA1() bfin_read16(CAN0_MB22_DATA1)
2430#define bfin_write_CAN0_MB22_DATA1(val) bfin_write16(CAN0_MB22_DATA1, val)
2431#define bfin_read_CAN0_MB22_DATA2() bfin_read16(CAN0_MB22_DATA2)
2432#define bfin_write_CAN0_MB22_DATA2(val) bfin_write16(CAN0_MB22_DATA2, val)
2433#define bfin_read_CAN0_MB22_DATA3() bfin_read16(CAN0_MB22_DATA3)
2434#define bfin_write_CAN0_MB22_DATA3(val) bfin_write16(CAN0_MB22_DATA3, val)
2435#define bfin_read_CAN0_MB22_LENGTH() bfin_read16(CAN0_MB22_LENGTH)
2436#define bfin_write_CAN0_MB22_LENGTH(val) bfin_write16(CAN0_MB22_LENGTH, val)
2437#define bfin_read_CAN0_MB22_TIMESTAMP() bfin_read16(CAN0_MB22_TIMESTAMP)
2438#define bfin_write_CAN0_MB22_TIMESTAMP(val) bfin_write16(CAN0_MB22_TIMESTAMP, val)
2439#define bfin_read_CAN0_MB22_ID0() bfin_read16(CAN0_MB22_ID0)
2440#define bfin_write_CAN0_MB22_ID0(val) bfin_write16(CAN0_MB22_ID0, val)
2441#define bfin_read_CAN0_MB22_ID1() bfin_read16(CAN0_MB22_ID1)
2442#define bfin_write_CAN0_MB22_ID1(val) bfin_write16(CAN0_MB22_ID1, val)
2443#define bfin_read_CAN0_MB23_DATA0() bfin_read16(CAN0_MB23_DATA0)
2444#define bfin_write_CAN0_MB23_DATA0(val) bfin_write16(CAN0_MB23_DATA0, val)
2445#define bfin_read_CAN0_MB23_DATA1() bfin_read16(CAN0_MB23_DATA1)
2446#define bfin_write_CAN0_MB23_DATA1(val) bfin_write16(CAN0_MB23_DATA1, val)
2447#define bfin_read_CAN0_MB23_DATA2() bfin_read16(CAN0_MB23_DATA2)
2448#define bfin_write_CAN0_MB23_DATA2(val) bfin_write16(CAN0_MB23_DATA2, val)
2449#define bfin_read_CAN0_MB23_DATA3() bfin_read16(CAN0_MB23_DATA3)
2450#define bfin_write_CAN0_MB23_DATA3(val) bfin_write16(CAN0_MB23_DATA3, val)
2451#define bfin_read_CAN0_MB23_LENGTH() bfin_read16(CAN0_MB23_LENGTH)
2452#define bfin_write_CAN0_MB23_LENGTH(val) bfin_write16(CAN0_MB23_LENGTH, val)
2453#define bfin_read_CAN0_MB23_TIMESTAMP() bfin_read16(CAN0_MB23_TIMESTAMP)
2454#define bfin_write_CAN0_MB23_TIMESTAMP(val) bfin_write16(CAN0_MB23_TIMESTAMP, val)
2455#define bfin_read_CAN0_MB23_ID0() bfin_read16(CAN0_MB23_ID0)
2456#define bfin_write_CAN0_MB23_ID0(val) bfin_write16(CAN0_MB23_ID0, val)
2457#define bfin_read_CAN0_MB23_ID1() bfin_read16(CAN0_MB23_ID1)
2458#define bfin_write_CAN0_MB23_ID1(val) bfin_write16(CAN0_MB23_ID1, val)
2459#define bfin_read_CAN0_MB24_DATA0() bfin_read16(CAN0_MB24_DATA0)
2460#define bfin_write_CAN0_MB24_DATA0(val) bfin_write16(CAN0_MB24_DATA0, val)
2461#define bfin_read_CAN0_MB24_DATA1() bfin_read16(CAN0_MB24_DATA1)
2462#define bfin_write_CAN0_MB24_DATA1(val) bfin_write16(CAN0_MB24_DATA1, val)
2463#define bfin_read_CAN0_MB24_DATA2() bfin_read16(CAN0_MB24_DATA2)
2464#define bfin_write_CAN0_MB24_DATA2(val) bfin_write16(CAN0_MB24_DATA2, val)
2465#define bfin_read_CAN0_MB24_DATA3() bfin_read16(CAN0_MB24_DATA3)
2466#define bfin_write_CAN0_MB24_DATA3(val) bfin_write16(CAN0_MB24_DATA3, val)
2467#define bfin_read_CAN0_MB24_LENGTH() bfin_read16(CAN0_MB24_LENGTH)
2468#define bfin_write_CAN0_MB24_LENGTH(val) bfin_write16(CAN0_MB24_LENGTH, val)
2469#define bfin_read_CAN0_MB24_TIMESTAMP() bfin_read16(CAN0_MB24_TIMESTAMP)
2470#define bfin_write_CAN0_MB24_TIMESTAMP(val) bfin_write16(CAN0_MB24_TIMESTAMP, val)
2471#define bfin_read_CAN0_MB24_ID0() bfin_read16(CAN0_MB24_ID0)
2472#define bfin_write_CAN0_MB24_ID0(val) bfin_write16(CAN0_MB24_ID0, val)
2473#define bfin_read_CAN0_MB24_ID1() bfin_read16(CAN0_MB24_ID1)
2474#define bfin_write_CAN0_MB24_ID1(val) bfin_write16(CAN0_MB24_ID1, val)
2475#define bfin_read_CAN0_MB25_DATA0() bfin_read16(CAN0_MB25_DATA0)
2476#define bfin_write_CAN0_MB25_DATA0(val) bfin_write16(CAN0_MB25_DATA0, val)
2477#define bfin_read_CAN0_MB25_DATA1() bfin_read16(CAN0_MB25_DATA1)
2478#define bfin_write_CAN0_MB25_DATA1(val) bfin_write16(CAN0_MB25_DATA1, val)
2479#define bfin_read_CAN0_MB25_DATA2() bfin_read16(CAN0_MB25_DATA2)
2480#define bfin_write_CAN0_MB25_DATA2(val) bfin_write16(CAN0_MB25_DATA2, val)
2481#define bfin_read_CAN0_MB25_DATA3() bfin_read16(CAN0_MB25_DATA3)
2482#define bfin_write_CAN0_MB25_DATA3(val) bfin_write16(CAN0_MB25_DATA3, val)
2483#define bfin_read_CAN0_MB25_LENGTH() bfin_read16(CAN0_MB25_LENGTH)
2484#define bfin_write_CAN0_MB25_LENGTH(val) bfin_write16(CAN0_MB25_LENGTH, val)
2485#define bfin_read_CAN0_MB25_TIMESTAMP() bfin_read16(CAN0_MB25_TIMESTAMP)
2486#define bfin_write_CAN0_MB25_TIMESTAMP(val) bfin_write16(CAN0_MB25_TIMESTAMP, val)
2487#define bfin_read_CAN0_MB25_ID0() bfin_read16(CAN0_MB25_ID0)
2488#define bfin_write_CAN0_MB25_ID0(val) bfin_write16(CAN0_MB25_ID0, val)
2489#define bfin_read_CAN0_MB25_ID1() bfin_read16(CAN0_MB25_ID1)
2490#define bfin_write_CAN0_MB25_ID1(val) bfin_write16(CAN0_MB25_ID1, val)
2491#define bfin_read_CAN0_MB26_DATA0() bfin_read16(CAN0_MB26_DATA0)
2492#define bfin_write_CAN0_MB26_DATA0(val) bfin_write16(CAN0_MB26_DATA0, val)
2493#define bfin_read_CAN0_MB26_DATA1() bfin_read16(CAN0_MB26_DATA1)
2494#define bfin_write_CAN0_MB26_DATA1(val) bfin_write16(CAN0_MB26_DATA1, val)
2495#define bfin_read_CAN0_MB26_DATA2() bfin_read16(CAN0_MB26_DATA2)
2496#define bfin_write_CAN0_MB26_DATA2(val) bfin_write16(CAN0_MB26_DATA2, val)
2497#define bfin_read_CAN0_MB26_DATA3() bfin_read16(CAN0_MB26_DATA3)
2498#define bfin_write_CAN0_MB26_DATA3(val) bfin_write16(CAN0_MB26_DATA3, val)
2499#define bfin_read_CAN0_MB26_LENGTH() bfin_read16(CAN0_MB26_LENGTH)
2500#define bfin_write_CAN0_MB26_LENGTH(val) bfin_write16(CAN0_MB26_LENGTH, val)
2501#define bfin_read_CAN0_MB26_TIMESTAMP() bfin_read16(CAN0_MB26_TIMESTAMP)
2502#define bfin_write_CAN0_MB26_TIMESTAMP(val) bfin_write16(CAN0_MB26_TIMESTAMP, val)
2503#define bfin_read_CAN0_MB26_ID0() bfin_read16(CAN0_MB26_ID0)
2504#define bfin_write_CAN0_MB26_ID0(val) bfin_write16(CAN0_MB26_ID0, val)
2505#define bfin_read_CAN0_MB26_ID1() bfin_read16(CAN0_MB26_ID1)
2506#define bfin_write_CAN0_MB26_ID1(val) bfin_write16(CAN0_MB26_ID1, val)
2507#define bfin_read_CAN0_MB27_DATA0() bfin_read16(CAN0_MB27_DATA0)
2508#define bfin_write_CAN0_MB27_DATA0(val) bfin_write16(CAN0_MB27_DATA0, val)
2509#define bfin_read_CAN0_MB27_DATA1() bfin_read16(CAN0_MB27_DATA1)
2510#define bfin_write_CAN0_MB27_DATA1(val) bfin_write16(CAN0_MB27_DATA1, val)
2511#define bfin_read_CAN0_MB27_DATA2() bfin_read16(CAN0_MB27_DATA2)
2512#define bfin_write_CAN0_MB27_DATA2(val) bfin_write16(CAN0_MB27_DATA2, val)
2513#define bfin_read_CAN0_MB27_DATA3() bfin_read16(CAN0_MB27_DATA3)
2514#define bfin_write_CAN0_MB27_DATA3(val) bfin_write16(CAN0_MB27_DATA3, val)
2515#define bfin_read_CAN0_MB27_LENGTH() bfin_read16(CAN0_MB27_LENGTH)
2516#define bfin_write_CAN0_MB27_LENGTH(val) bfin_write16(CAN0_MB27_LENGTH, val)
2517#define bfin_read_CAN0_MB27_TIMESTAMP() bfin_read16(CAN0_MB27_TIMESTAMP)
2518#define bfin_write_CAN0_MB27_TIMESTAMP(val) bfin_write16(CAN0_MB27_TIMESTAMP, val)
2519#define bfin_read_CAN0_MB27_ID0() bfin_read16(CAN0_MB27_ID0)
2520#define bfin_write_CAN0_MB27_ID0(val) bfin_write16(CAN0_MB27_ID0, val)
2521#define bfin_read_CAN0_MB27_ID1() bfin_read16(CAN0_MB27_ID1)
2522#define bfin_write_CAN0_MB27_ID1(val) bfin_write16(CAN0_MB27_ID1, val)
2523#define bfin_read_CAN0_MB28_DATA0() bfin_read16(CAN0_MB28_DATA0)
2524#define bfin_write_CAN0_MB28_DATA0(val) bfin_write16(CAN0_MB28_DATA0, val)
2525#define bfin_read_CAN0_MB28_DATA1() bfin_read16(CAN0_MB28_DATA1)
2526#define bfin_write_CAN0_MB28_DATA1(val) bfin_write16(CAN0_MB28_DATA1, val)
2527#define bfin_read_CAN0_MB28_DATA2() bfin_read16(CAN0_MB28_DATA2)
2528#define bfin_write_CAN0_MB28_DATA2(val) bfin_write16(CAN0_MB28_DATA2, val)
2529#define bfin_read_CAN0_MB28_DATA3() bfin_read16(CAN0_MB28_DATA3)
2530#define bfin_write_CAN0_MB28_DATA3(val) bfin_write16(CAN0_MB28_DATA3, val)
2531#define bfin_read_CAN0_MB28_LENGTH() bfin_read16(CAN0_MB28_LENGTH)
2532#define bfin_write_CAN0_MB28_LENGTH(val) bfin_write16(CAN0_MB28_LENGTH, val)
2533#define bfin_read_CAN0_MB28_TIMESTAMP() bfin_read16(CAN0_MB28_TIMESTAMP)
2534#define bfin_write_CAN0_MB28_TIMESTAMP(val) bfin_write16(CAN0_MB28_TIMESTAMP, val)
2535#define bfin_read_CAN0_MB28_ID0() bfin_read16(CAN0_MB28_ID0)
2536#define bfin_write_CAN0_MB28_ID0(val) bfin_write16(CAN0_MB28_ID0, val)
2537#define bfin_read_CAN0_MB28_ID1() bfin_read16(CAN0_MB28_ID1)
2538#define bfin_write_CAN0_MB28_ID1(val) bfin_write16(CAN0_MB28_ID1, val)
2539#define bfin_read_CAN0_MB29_DATA0() bfin_read16(CAN0_MB29_DATA0)
2540#define bfin_write_CAN0_MB29_DATA0(val) bfin_write16(CAN0_MB29_DATA0, val)
2541#define bfin_read_CAN0_MB29_DATA1() bfin_read16(CAN0_MB29_DATA1)
2542#define bfin_write_CAN0_MB29_DATA1(val) bfin_write16(CAN0_MB29_DATA1, val)
2543#define bfin_read_CAN0_MB29_DATA2() bfin_read16(CAN0_MB29_DATA2)
2544#define bfin_write_CAN0_MB29_DATA2(val) bfin_write16(CAN0_MB29_DATA2, val)
2545#define bfin_read_CAN0_MB29_DATA3() bfin_read16(CAN0_MB29_DATA3)
2546#define bfin_write_CAN0_MB29_DATA3(val) bfin_write16(CAN0_MB29_DATA3, val)
2547#define bfin_read_CAN0_MB29_LENGTH() bfin_read16(CAN0_MB29_LENGTH)
2548#define bfin_write_CAN0_MB29_LENGTH(val) bfin_write16(CAN0_MB29_LENGTH, val)
2549#define bfin_read_CAN0_MB29_TIMESTAMP() bfin_read16(CAN0_MB29_TIMESTAMP)
2550#define bfin_write_CAN0_MB29_TIMESTAMP(val) bfin_write16(CAN0_MB29_TIMESTAMP, val)
2551#define bfin_read_CAN0_MB29_ID0() bfin_read16(CAN0_MB29_ID0)
2552#define bfin_write_CAN0_MB29_ID0(val) bfin_write16(CAN0_MB29_ID0, val)
2553#define bfin_read_CAN0_MB29_ID1() bfin_read16(CAN0_MB29_ID1)
2554#define bfin_write_CAN0_MB29_ID1(val) bfin_write16(CAN0_MB29_ID1, val)
2555#define bfin_read_CAN0_MB30_DATA0() bfin_read16(CAN0_MB30_DATA0)
2556#define bfin_write_CAN0_MB30_DATA0(val) bfin_write16(CAN0_MB30_DATA0, val)
2557#define bfin_read_CAN0_MB30_DATA1() bfin_read16(CAN0_MB30_DATA1)
2558#define bfin_write_CAN0_MB30_DATA1(val) bfin_write16(CAN0_MB30_DATA1, val)
2559#define bfin_read_CAN0_MB30_DATA2() bfin_read16(CAN0_MB30_DATA2)
2560#define bfin_write_CAN0_MB30_DATA2(val) bfin_write16(CAN0_MB30_DATA2, val)
2561#define bfin_read_CAN0_MB30_DATA3() bfin_read16(CAN0_MB30_DATA3)
2562#define bfin_write_CAN0_MB30_DATA3(val) bfin_write16(CAN0_MB30_DATA3, val)
2563#define bfin_read_CAN0_MB30_LENGTH() bfin_read16(CAN0_MB30_LENGTH)
2564#define bfin_write_CAN0_MB30_LENGTH(val) bfin_write16(CAN0_MB30_LENGTH, val)
2565#define bfin_read_CAN0_MB30_TIMESTAMP() bfin_read16(CAN0_MB30_TIMESTAMP)
2566#define bfin_write_CAN0_MB30_TIMESTAMP(val) bfin_write16(CAN0_MB30_TIMESTAMP, val)
2567#define bfin_read_CAN0_MB30_ID0() bfin_read16(CAN0_MB30_ID0)
2568#define bfin_write_CAN0_MB30_ID0(val) bfin_write16(CAN0_MB30_ID0, val)
2569#define bfin_read_CAN0_MB30_ID1() bfin_read16(CAN0_MB30_ID1)
2570#define bfin_write_CAN0_MB30_ID1(val) bfin_write16(CAN0_MB30_ID1, val)
2571#define bfin_read_CAN0_MB31_DATA0() bfin_read16(CAN0_MB31_DATA0)
2572#define bfin_write_CAN0_MB31_DATA0(val) bfin_write16(CAN0_MB31_DATA0, val)
2573#define bfin_read_CAN0_MB31_DATA1() bfin_read16(CAN0_MB31_DATA1)
2574#define bfin_write_CAN0_MB31_DATA1(val) bfin_write16(CAN0_MB31_DATA1, val)
2575#define bfin_read_CAN0_MB31_DATA2() bfin_read16(CAN0_MB31_DATA2)
2576#define bfin_write_CAN0_MB31_DATA2(val) bfin_write16(CAN0_MB31_DATA2, val)
2577#define bfin_read_CAN0_MB31_DATA3() bfin_read16(CAN0_MB31_DATA3)
2578#define bfin_write_CAN0_MB31_DATA3(val) bfin_write16(CAN0_MB31_DATA3, val)
2579#define bfin_read_CAN0_MB31_LENGTH() bfin_read16(CAN0_MB31_LENGTH)
2580#define bfin_write_CAN0_MB31_LENGTH(val) bfin_write16(CAN0_MB31_LENGTH, val)
2581#define bfin_read_CAN0_MB31_TIMESTAMP() bfin_read16(CAN0_MB31_TIMESTAMP)
2582#define bfin_write_CAN0_MB31_TIMESTAMP(val) bfin_write16(CAN0_MB31_TIMESTAMP, val)
2583#define bfin_read_CAN0_MB31_ID0() bfin_read16(CAN0_MB31_ID0)
2584#define bfin_write_CAN0_MB31_ID0(val) bfin_write16(CAN0_MB31_ID0, val)
2585#define bfin_read_CAN0_MB31_ID1() bfin_read16(CAN0_MB31_ID1)
2586#define bfin_write_CAN0_MB31_ID1(val) bfin_write16(CAN0_MB31_ID1, val)
2587
2588/* UART3 Registers */
2589
2590#define bfin_read_UART3_DLL() bfin_read16(UART3_DLL)
2591#define bfin_write_UART3_DLL(val) bfin_write16(UART3_DLL, val)
2592#define bfin_read_UART3_DLH() bfin_read16(UART3_DLH)
2593#define bfin_write_UART3_DLH(val) bfin_write16(UART3_DLH, val)
2594#define bfin_read_UART3_GCTL() bfin_read16(UART3_GCTL)
2595#define bfin_write_UART3_GCTL(val) bfin_write16(UART3_GCTL, val)
2596#define bfin_read_UART3_LCR() bfin_read16(UART3_LCR)
2597#define bfin_write_UART3_LCR(val) bfin_write16(UART3_LCR, val)
2598#define bfin_read_UART3_MCR() bfin_read16(UART3_MCR)
2599#define bfin_write_UART3_MCR(val) bfin_write16(UART3_MCR, val)
2600#define bfin_read_UART3_LSR() bfin_read16(UART3_LSR)
2601#define bfin_write_UART3_LSR(val) bfin_write16(UART3_LSR, val)
2602#define bfin_read_UART3_MSR() bfin_read16(UART3_MSR)
2603#define bfin_write_UART3_MSR(val) bfin_write16(UART3_MSR, val)
2604#define bfin_read_UART3_SCR() bfin_read16(UART3_SCR)
2605#define bfin_write_UART3_SCR(val) bfin_write16(UART3_SCR, val)
2606#define bfin_read_UART3_IER_SET() bfin_read16(UART3_IER_SET)
2607#define bfin_write_UART3_IER_SET(val) bfin_write16(UART3_IER_SET, val)
2608#define bfin_read_UART3_IER_CLEAR() bfin_read16(UART3_IER_CLEAR)
2609#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
2610#define bfin_read_UART3_THR() bfin_read16(UART3_THR)
2611#define bfin_write_UART3_THR(val) bfin_write16(UART3_THR, val)
2612#define bfin_read_UART3_RBR() bfin_read16(UART3_RBR)
2613#define bfin_write_UART3_RBR(val) bfin_write16(UART3_RBR, val)
2614
2615/* NFC Registers */
2616
2617#define bfin_read_NFC_CTL() bfin_read16(NFC_CTL)
2618#define bfin_write_NFC_CTL(val) bfin_write16(NFC_CTL, val)
2619#define bfin_read_NFC_STAT() bfin_read16(NFC_STAT)
2620#define bfin_write_NFC_STAT(val) bfin_write16(NFC_STAT, val)
2621#define bfin_read_NFC_IRQSTAT() bfin_read16(NFC_IRQSTAT)
2622#define bfin_write_NFC_IRQSTAT(val) bfin_write16(NFC_IRQSTAT, val)
2623#define bfin_read_NFC_IRQMASK() bfin_read16(NFC_IRQMASK)
2624#define bfin_write_NFC_IRQMASK(val) bfin_write16(NFC_IRQMASK, val)
2625#define bfin_read_NFC_ECC0() bfin_read16(NFC_ECC0)
2626#define bfin_write_NFC_ECC0(val) bfin_write16(NFC_ECC0, val)
2627#define bfin_read_NFC_ECC1() bfin_read16(NFC_ECC1)
2628#define bfin_write_NFC_ECC1(val) bfin_write16(NFC_ECC1, val)
2629#define bfin_read_NFC_ECC2() bfin_read16(NFC_ECC2)
2630#define bfin_write_NFC_ECC2(val) bfin_write16(NFC_ECC2, val)
2631#define bfin_read_NFC_ECC3() bfin_read16(NFC_ECC3)
2632#define bfin_write_NFC_ECC3(val) bfin_write16(NFC_ECC3, val)
2633#define bfin_read_NFC_COUNT() bfin_read16(NFC_COUNT)
2634#define bfin_write_NFC_COUNT(val) bfin_write16(NFC_COUNT, val)
2635#define bfin_read_NFC_RST() bfin_read16(NFC_RST)
2636#define bfin_write_NFC_RST(val) bfin_write16(NFC_RST, val)
2637#define bfin_read_NFC_PGCTL() bfin_read16(NFC_PGCTL)
2638#define bfin_write_NFC_PGCTL(val) bfin_write16(NFC_PGCTL, val)
2639#define bfin_read_NFC_READ() bfin_read16(NFC_READ)
2640#define bfin_write_NFC_READ(val) bfin_write16(NFC_READ, val)
2641#define bfin_read_NFC_ADDR() bfin_read16(NFC_ADDR)
2642#define bfin_write_NFC_ADDR(val) bfin_write16(NFC_ADDR, val)
2643#define bfin_read_NFC_CMD() bfin_read16(NFC_CMD)
2644#define bfin_write_NFC_CMD(val) bfin_write16(NFC_CMD, val)
2645#define bfin_read_NFC_DATA_WR() bfin_read16(NFC_DATA_WR)
2646#define bfin_write_NFC_DATA_WR(val) bfin_write16(NFC_DATA_WR, val)
2647#define bfin_read_NFC_DATA_RD() bfin_read16(NFC_DATA_RD)
2648#define bfin_write_NFC_DATA_RD(val) bfin_write16(NFC_DATA_RD, val)
2649
2650/* Counter Registers */
2651
2652#define bfin_read_CNT_CONFIG() bfin_read16(CNT_CONFIG)
2653#define bfin_write_CNT_CONFIG(val) bfin_write16(CNT_CONFIG, val)
2654#define bfin_read_CNT_IMASK() bfin_read16(CNT_IMASK)
2655#define bfin_write_CNT_IMASK(val) bfin_write16(CNT_IMASK, val)
2656#define bfin_read_CNT_STATUS() bfin_read16(CNT_STATUS)
2657#define bfin_write_CNT_STATUS(val) bfin_write16(CNT_STATUS, val)
2658#define bfin_read_CNT_COMMAND() bfin_read16(CNT_COMMAND)
2659#define bfin_write_CNT_COMMAND(val) bfin_write16(CNT_COMMAND, val)
2660#define bfin_read_CNT_DEBOUNCE() bfin_read16(CNT_DEBOUNCE)
2661#define bfin_write_CNT_DEBOUNCE(val) bfin_write16(CNT_DEBOUNCE, val)
2662#define bfin_read_CNT_COUNTER() bfin_read32(CNT_COUNTER)
2663#define bfin_write_CNT_COUNTER(val) bfin_write32(CNT_COUNTER, val)
2664#define bfin_read_CNT_MAX() bfin_read32(CNT_MAX)
2665#define bfin_write_CNT_MAX(val) bfin_write32(CNT_MAX, val)
2666#define bfin_read_CNT_MIN() bfin_read32(CNT_MIN)
2667#define bfin_write_CNT_MIN(val) bfin_write32(CNT_MIN, val)
2668
2669/* OTP/FUSE Registers */
2670
2671#define bfin_read_OTP_CONTROL() bfin_read16(OTP_CONTROL)
2672#define bfin_write_OTP_CONTROL(val) bfin_write16(OTP_CONTROL, val)
2673#define bfin_read_OTP_BEN() bfin_read16(OTP_BEN)
2674#define bfin_write_OTP_BEN(val) bfin_write16(OTP_BEN, val)
2675#define bfin_read_OTP_STATUS() bfin_read16(OTP_STATUS)
2676#define bfin_write_OTP_STATUS(val) bfin_write16(OTP_STATUS, val)
2677#define bfin_read_OTP_TIMING() bfin_read32(OTP_TIMING)
2678#define bfin_write_OTP_TIMING(val) bfin_write32(OTP_TIMING, val)
2679
2680/* Security Registers */
2681
2682#define bfin_read_SECURE_SYSSWT() bfin_read32(SECURE_SYSSWT)
2683#define bfin_write_SECURE_SYSSWT(val) bfin_write32(SECURE_SYSSWT, val)
2684#define bfin_read_SECURE_CONTROL() bfin_read16(SECURE_CONTROL)
2685#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
2686#define bfin_read_SECURE_STATUS() bfin_read16(SECURE_STATUS)
2687#define bfin_write_SECURE_STATUS(val) bfin_write16(SECURE_STATUS, val)
2688
2689/* DMA Peribfin_read_()heral Mux Register */
2690
2691#define bfin_read_DMAC1_PERIMUX() bfin_read16(DMAC1_PERIMUX)
2692#define bfin_write_DMAC1_PERIMUX(val) bfin_write16(DMAC1_PERIMUX, val)
2693
2694/* OTP Read/Write Data Buffer Registers */
2695
2696#define bfin_read_OTP_DATA0() bfin_read32(OTP_DATA0)
2697#define bfin_write_OTP_DATA0(val) bfin_write32(OTP_DATA0, val)
2698#define bfin_read_OTP_DATA1() bfin_read32(OTP_DATA1)
2699#define bfin_write_OTP_DATA1(val) bfin_write32(OTP_DATA1, val)
2700#define bfin_read_OTP_DATA2() bfin_read32(OTP_DATA2)
2701#define bfin_write_OTP_DATA2(val) bfin_write32(OTP_DATA2, val)
2702#define bfin_read_OTP_DATA3() bfin_read32(OTP_DATA3)
2703#define bfin_write_OTP_DATA3(val) bfin_write32(OTP_DATA3, val)
2704
2705/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
2706
2707/* legacy definitions */
2708#define bfin_read_EBIU_AMCBCTL0 bfin_read_EBIU_AMBCTL0
2709#define bfin_write_EBIU_AMCBCTL0 bfin_write_EBIU_AMBCTL0
2710#define bfin_read_EBIU_AMCBCTL1 bfin_read_EBIU_AMBCTL1
2711#define bfin_write_EBIU_AMCBCTL1 bfin_write_EBIU_AMBCTL1
2712#define bfin_read_PINT0_IRQ bfin_read_PINT0_REQUEST
2713#define bfin_write_PINT0_IRQ bfin_write_PINT0_REQUEST
2714#define bfin_read_PINT1_IRQ bfin_read_PINT1_REQUEST
2715#define bfin_write_PINT1_IRQ bfin_write_PINT1_REQUEST
2716#define bfin_read_PINT2_IRQ bfin_read_PINT2_REQUEST
2717#define bfin_write_PINT2_IRQ bfin_write_PINT2_REQUEST
2718#define bfin_read_PINT3_IRQ bfin_read_PINT3_REQUEST
2719#define bfin_write_PINT3_IRQ bfin_write_PINT3_REQUEST
2720
2721#endif /* _CDEF_BF54X_H */
2722
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
new file mode 100644
index 000000000000..ac968fca5cc5
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF542.h
@@ -0,0 +1,1206 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF542.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF542_H
32#define _DEF_BF542_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
43
44/* ATAPI Registers */
45
46#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
47#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
48#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
49#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
50#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
51#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
52#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
53#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
54#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
55#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
56#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
57#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
58#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
59#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
60#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
61#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
62#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
63#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
64#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
65#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
66#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
67#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
68#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
69#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
70#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
71
72/* SDH Registers */
73
74#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
75#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
76#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
77#define SDH_COMMAND 0xffc0390c /* SDH Command */
78#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
79#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
80#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
81#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
82#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
83#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
84#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
85#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
86#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
87#define SDH_STATUS 0xffc03934 /* SDH Status */
88#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
89#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
90#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
91#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
92#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
93#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
94#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
95#define SDH_CFG 0xffc039c8 /* SDH Configuration */
96#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
97#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
98#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
99#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
100#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
101#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
102#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
103#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
104#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
105
106/* USB Control Registers */
107
108#define USB_FADDR 0xffc03c00 /* Function address register */
109#define USB_POWER 0xffc03c04 /* Power management register */
110#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
111#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
112#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
113#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
114#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
115#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
116#define USB_FRAME 0xffc03c20 /* USB frame number */
117#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
118#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
119#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
120#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
121
122/* USB Packet Control Registers */
123
124#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
125#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
126#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
127#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
128#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
129#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
130#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
131#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
132#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
133#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
134#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
135#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
136#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
137
138/* USB Endpoint FIFO Registers */
139
140#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
141#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
142#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
143#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
144#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
145#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
146#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
147#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
148
149/* USB OTG Control Registers */
150
151#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
152#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
153#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
154
155/* USB Phy Control Registers */
156
157#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
158#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
159#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
160#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
161#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
162
163/* (APHY_CNTRL is for ADI usage only) */
164
165#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
166
167/* (APHY_CALIB is for ADI usage only) */
168
169#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
170#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
171
172/* (PHY_TEST is for ADI usage only) */
173
174#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
175#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
176#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
177
178/* USB Endpoint 0 Control Registers */
179
180#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
181#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
182#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
183#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
184#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
185#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
186#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
187#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
188#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
189
190/* USB Endpoint 1 Control Registers */
191
192#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
193#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
194#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
195#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
196#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
197#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
198#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
199#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
200#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
201#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
202
203/* USB Endpoint 2 Control Registers */
204
205#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
206#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
207#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
208#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
209#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
210#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
211#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
212#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
213#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
214#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
215
216/* USB Endpoint 3 Control Registers */
217
218#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
219#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
220#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
221#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
222#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
223#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
224#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
225#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
226#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
227#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
228
229/* USB Endpoint 4 Control Registers */
230
231#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
232#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
233#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
234#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
235#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
236#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
237#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
238#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
239#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
240#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
241
242/* USB Endpoint 5 Control Registers */
243
244#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
245#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
246#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
247#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
248#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
249#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
250#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
251#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
252#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
253#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
254
255/* USB Endpoint 6 Control Registers */
256
257#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
258#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
259#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
260#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
261#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
262#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
263#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
264#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
265#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
266#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
267
268/* USB Endpoint 7 Control Registers */
269
270#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
271#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
272#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
273#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
274#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
275#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
276#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
277#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
278#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
279#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
280#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
281#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
282
283/* USB Channel 0 Config Registers */
284
285#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
286#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
287#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
288#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
289#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
290
291/* USB Channel 1 Config Registers */
292
293#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
294#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
295#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
296#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
297#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
298
299/* USB Channel 2 Config Registers */
300
301#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
302#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
303#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
304#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
305#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
306
307/* USB Channel 3 Config Registers */
308
309#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
310#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
311#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
312#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
313#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
314
315/* USB Channel 4 Config Registers */
316
317#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
318#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
319#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
320#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
321#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
322
323/* USB Channel 5 Config Registers */
324
325#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
326#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
327#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
328#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
329#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
330
331/* USB Channel 6 Config Registers */
332
333#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
334#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
335#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
336#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
337#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
338
339/* USB Channel 7 Config Registers */
340
341#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
342#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
343#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
344#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
345#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
346
347/* Keypad Registers */
348
349#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
350#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
351#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
352#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
353#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
354#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
355
356
357/* ********************************************************** */
358/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
359/* and MULTI BIT READ MACROS */
360/* ********************************************************** */
361
362/* Bit masks for KPAD_CTL */
363
364#define KPAD_EN 0x1 /* Keypad Enable */
365#define nKPAD_EN 0x0
366#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
367#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
368#define KPAD_COLEN 0xe000 /* Column Enable Width */
369
370/* Bit masks for KPAD_PRESCALE */
371
372#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
373
374/* Bit masks for KPAD_MSEL */
375
376#define DBON_SCALE 0xff /* Debounce Scale Value */
377#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
378
379/* Bit masks for KPAD_ROWCOL */
380
381#define KPAD_ROW 0xff /* Rows Pressed */
382#define KPAD_COL 0xff00 /* Columns Pressed */
383
384/* Bit masks for KPAD_STAT */
385
386#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
387#define nKPAD_IRQ 0x0
388#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
389#define KPAD_PRESSED 0x8 /* Key press current status */
390#define nKPAD_PRESSED 0x0
391
392/* Bit masks for KPAD_SOFTEVAL */
393
394#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
395#define nKPAD_SOFTEVAL_E 0x0
396
397/* Bit masks for SDH_COMMAND */
398
399#define CMD_IDX 0x3f /* Command Index */
400#define CMD_RSP 0x40 /* Response */
401#define nCMD_RSP 0x0
402#define CMD_L_RSP 0x80 /* Long Response */
403#define nCMD_L_RSP 0x0
404#define CMD_INT_E 0x100 /* Command Interrupt */
405#define nCMD_INT_E 0x0
406#define CMD_PEND_E 0x200 /* Command Pending */
407#define nCMD_PEND_E 0x0
408#define CMD_E 0x400 /* Command Enable */
409#define nCMD_E 0x0
410
411/* Bit masks for SDH_PWR_CTL */
412
413#define PWR_ON 0x3 /* Power On */
414#if 0
415#define TBD 0x3c /* TBD */
416#endif
417#define SD_CMD_OD 0x40 /* Open Drain Output */
418#define nSD_CMD_OD 0x0
419#define ROD_CTL 0x80 /* Rod Control */
420#define nROD_CTL 0x0
421
422/* Bit masks for SDH_CLK_CTL */
423
424#define CLKDIV 0xff /* MC_CLK Divisor */
425#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
426#define nCLK_E 0x0
427#define PWR_SV_E 0x200 /* Power Save Enable */
428#define nPWR_SV_E 0x0
429#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
430#define nCLKDIV_BYPASS 0x0
431#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
432#define nWIDE_BUS 0x0
433
434/* Bit masks for SDH_RESP_CMD */
435
436#define RESP_CMD 0x3f /* Response Command */
437
438/* Bit masks for SDH_DATA_CTL */
439
440#define DTX_E 0x1 /* Data Transfer Enable */
441#define nDTX_E 0x0
442#define DTX_DIR 0x2 /* Data Transfer Direction */
443#define nDTX_DIR 0x0
444#define DTX_MODE 0x4 /* Data Transfer Mode */
445#define nDTX_MODE 0x0
446#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
447#define nDTX_DMA_E 0x0
448#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
449
450/* Bit masks for SDH_STATUS */
451
452#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
453#define nCMD_CRC_FAIL 0x0
454#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
455#define nDAT_CRC_FAIL 0x0
456#define CMD_TIMEOUT 0x4 /* CMD Time Out */
457#define nCMD_TIMEOUT 0x0
458#define DAT_TIMEOUT 0x8 /* Data Time Out */
459#define nDAT_TIMEOUT 0x0
460#define TX_UNDERRUN 0x10 /* Transmit Underrun */
461#define nTX_UNDERRUN 0x0
462#define RX_OVERRUN 0x20 /* Receive Overrun */
463#define nRX_OVERRUN 0x0
464#define CMD_RESP_END 0x40 /* CMD Response End */
465#define nCMD_RESP_END 0x0
466#define CMD_SENT 0x80 /* CMD Sent */
467#define nCMD_SENT 0x0
468#define DAT_END 0x100 /* Data End */
469#define nDAT_END 0x0
470#define START_BIT_ERR 0x200 /* Start Bit Error */
471#define nSTART_BIT_ERR 0x0
472#define DAT_BLK_END 0x400 /* Data Block End */
473#define nDAT_BLK_END 0x0
474#define CMD_ACT 0x800 /* CMD Active */
475#define nCMD_ACT 0x0
476#define TX_ACT 0x1000 /* Transmit Active */
477#define nTX_ACT 0x0
478#define RX_ACT 0x2000 /* Receive Active */
479#define nRX_ACT 0x0
480#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
481#define nTX_FIFO_STAT 0x0
482#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
483#define nRX_FIFO_STAT 0x0
484#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
485#define nTX_FIFO_FULL 0x0
486#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
487#define nRX_FIFO_FULL 0x0
488#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
489#define nTX_FIFO_ZERO 0x0
490#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
491#define nRX_DAT_ZERO 0x0
492#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
493#define nTX_DAT_RDY 0x0
494#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
495#define nRX_FIFO_RDY 0x0
496
497/* Bit masks for SDH_STATUS_CLR */
498
499#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
500#define nCMD_CRC_FAIL_STAT 0x0
501#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
502#define nDAT_CRC_FAIL_STAT 0x0
503#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
504#define nCMD_TIMEOUT_STAT 0x0
505#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
506#define nDAT_TIMEOUT_STAT 0x0
507#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
508#define nTX_UNDERRUN_STAT 0x0
509#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
510#define nRX_OVERRUN_STAT 0x0
511#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
512#define nCMD_RESP_END_STAT 0x0
513#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
514#define nCMD_SENT_STAT 0x0
515#define DAT_END_STAT 0x100 /* Data End Status */
516#define nDAT_END_STAT 0x0
517#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
518#define nSTART_BIT_ERR_STAT 0x0
519#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
520#define nDAT_BLK_END_STAT 0x0
521
522/* Bit masks for SDH_MASK0 */
523
524#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
525#define nCMD_CRC_FAIL_MASK 0x0
526#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
527#define nDAT_CRC_FAIL_MASK 0x0
528#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
529#define nCMD_TIMEOUT_MASK 0x0
530#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
531#define nDAT_TIMEOUT_MASK 0x0
532#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
533#define nTX_UNDERRUN_MASK 0x0
534#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
535#define nRX_OVERRUN_MASK 0x0
536#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
537#define nCMD_RESP_END_MASK 0x0
538#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
539#define nCMD_SENT_MASK 0x0
540#define DAT_END_MASK 0x100 /* Data End Mask */
541#define nDAT_END_MASK 0x0
542#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
543#define nSTART_BIT_ERR_MASK 0x0
544#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
545#define nDAT_BLK_END_MASK 0x0
546#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
547#define nCMD_ACT_MASK 0x0
548#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
549#define nTX_ACT_MASK 0x0
550#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
551#define nRX_ACT_MASK 0x0
552#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
553#define nTX_FIFO_STAT_MASK 0x0
554#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
555#define nRX_FIFO_STAT_MASK 0x0
556#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
557#define nTX_FIFO_FULL_MASK 0x0
558#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
559#define nRX_FIFO_FULL_MASK 0x0
560#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
561#define nTX_FIFO_ZERO_MASK 0x0
562#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
563#define nRX_DAT_ZERO_MASK 0x0
564#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
565#define nTX_DAT_RDY_MASK 0x0
566#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
567#define nRX_FIFO_RDY_MASK 0x0
568
569/* Bit masks for SDH_FIFO_CNT */
570
571#define FIFO_COUNT 0x7fff /* FIFO Count */
572
573/* Bit masks for SDH_E_STATUS */
574
575#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
576#define nSDIO_INT_DET 0x0
577#define SD_CARD_DET 0x10 /* SD Card Detect */
578#define nSD_CARD_DET 0x0
579
580/* Bit masks for SDH_E_MASK */
581
582#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
583#define nSDIO_MSK 0x0
584#define SCD_MSK 0x40 /* Mask Card Detect */
585#define nSCD_MSK 0x0
586
587/* Bit masks for SDH_CFG */
588
589#define CLKS_EN 0x1 /* Clocks Enable */
590#define nCLKS_EN 0x0
591#define SD4E 0x4 /* SDIO 4-Bit Enable */
592#define nSD4E 0x0
593#define MWE 0x8 /* Moving Window Enable */
594#define nMWE 0x0
595#define SD_RST 0x10 /* SDMMC Reset */
596#define nSD_RST 0x0
597#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
598#define nPUP_SDDAT 0x0
599#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
600#define nPUP_SDDAT3 0x0
601#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
602#define nPD_SDDAT3 0x0
603
604/* Bit masks for SDH_RD_WAIT_EN */
605
606#define RWR 0x1 /* Read Wait Request */
607#define nRWR 0x0
608
609/* Bit masks for ATAPI_CONTROL */
610
611#define PIO_START 0x1 /* Start PIO/Reg Op */
612#define nPIO_START 0x0
613#define MULTI_START 0x2 /* Start Multi-DMA Op */
614#define nMULTI_START 0x0
615#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
616#define nULTRA_START 0x0
617#define XFER_DIR 0x8 /* Transfer Direction */
618#define nXFER_DIR 0x0
619#define IORDY_EN 0x10 /* IORDY Enable */
620#define nIORDY_EN 0x0
621#define FIFO_FLUSH 0x20 /* Flush FIFOs */
622#define nFIFO_FLUSH 0x0
623#define SOFT_RST 0x40 /* Soft Reset */
624#define nSOFT_RST 0x0
625#define DEV_RST 0x80 /* Device Reset */
626#define nDEV_RST 0x0
627#define TFRCNT_RST 0x100 /* Trans Count Reset */
628#define nTFRCNT_RST 0x0
629#define END_ON_TERM 0x200 /* End/Terminate Select */
630#define nEND_ON_TERM 0x0
631#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
632#define nPIO_USE_DMA 0x0
633#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
634
635/* Bit masks for ATAPI_STATUS */
636
637#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
638#define nPIO_XFER_ON 0x0
639#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
640#define nMULTI_XFER_ON 0x0
641#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
642#define nULTRA_XFER_ON 0x0
643#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
644
645/* Bit masks for ATAPI_DEV_ADDR */
646
647#define DEV_ADDR 0x1f /* Device Address */
648
649/* Bit masks for ATAPI_INT_MASK */
650
651#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
652#define nATAPI_DEV_INT_MASK 0x0
653#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
654#define nPIO_DONE_MASK 0x0
655#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
656#define nMULTI_DONE_MASK 0x0
657#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
658#define nUDMAIN_DONE_MASK 0x0
659#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
660#define nUDMAOUT_DONE_MASK 0x0
661#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
662#define nHOST_TERM_XFER_MASK 0x0
663#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
664#define nMULTI_TERM_MASK 0x0
665#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
666#define nUDMAIN_TERM_MASK 0x0
667#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
668#define nUDMAOUT_TERM_MASK 0x0
669
670/* Bit masks for ATAPI_INT_STATUS */
671
672#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
673#define nATAPI_DEV_INT 0x0
674#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
675#define nPIO_DONE_INT 0x0
676#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
677#define nMULTI_DONE_INT 0x0
678#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
679#define nUDMAIN_DONE_INT 0x0
680#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
681#define nUDMAOUT_DONE_INT 0x0
682#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
683#define nHOST_TERM_XFER_INT 0x0
684#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
685#define nMULTI_TERM_INT 0x0
686#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
687#define nUDMAIN_TERM_INT 0x0
688#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
689#define nUDMAOUT_TERM_INT 0x0
690
691/* Bit masks for ATAPI_LINE_STATUS */
692
693#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
694#define nATAPI_INTR 0x0
695#define ATAPI_DASP 0x2 /* Device dasp to host line status */
696#define nATAPI_DASP 0x0
697#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
698#define nATAPI_CS0N 0x0
699#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
700#define nATAPI_CS1N 0x0
701#define ATAPI_ADDR 0x70 /* ATAPI address line status */
702#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
703#define nATAPI_DMAREQ 0x0
704#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
705#define nATAPI_DMAACKN 0x0
706#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
707#define nATAPI_DIOWN 0x0
708#define ATAPI_DIORN 0x400 /* ATAPI read line status */
709#define nATAPI_DIORN 0x0
710#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
711#define nATAPI_IORDY 0x0
712
713/* Bit masks for ATAPI_SM_STATE */
714
715#define PIO_CSTATE 0xf /* PIO mode state machine current state */
716#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
717#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
718#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
719
720/* Bit masks for ATAPI_TERMINATE */
721
722#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
723#define nATAPI_HOST_TERM 0x0
724
725/* Bit masks for ATAPI_REG_TIM_0 */
726
727#define T2_REG 0xff /* End of cycle time for register access transfers */
728#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
729
730/* Bit masks for ATAPI_PIO_TIM_0 */
731
732#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
733#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
734#define T4_REG 0xf000 /* DIOW data hold */
735
736/* Bit masks for ATAPI_PIO_TIM_1 */
737
738#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
739
740/* Bit masks for ATAPI_MULTI_TIM_0 */
741
742#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
743#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
744
745/* Bit masks for ATAPI_MULTI_TIM_1 */
746
747#define TKW 0xff /* Selects DIOW negated pulsewidth */
748#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
749
750/* Bit masks for ATAPI_MULTI_TIM_2 */
751
752#define TH 0xff /* Selects DIOW data hold */
753#define TEOC 0xff00 /* Selects end of cycle for DMA */
754
755/* Bit masks for ATAPI_ULTRA_TIM_0 */
756
757#define TACK 0xff /* Selects setup and hold times for TACK */
758#define TENV 0xff00 /* Selects envelope time */
759
760/* Bit masks for ATAPI_ULTRA_TIM_1 */
761
762#define TDVS 0xff /* Selects data valid setup time */
763#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
764
765/* Bit masks for ATAPI_ULTRA_TIM_2 */
766
767#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
768#define TMLI 0xff00 /* Selects interlock time */
769
770/* Bit masks for ATAPI_ULTRA_TIM_3 */
771
772#define TZAH 0xff /* Selects minimum delay required for output */
773#define READY_PAUSE 0xff00 /* Selects ready to pause */
774
775/* Bit masks for USB_FADDR */
776
777#define FUNCTION_ADDRESS 0x7f /* Function address */
778
779/* Bit masks for USB_POWER */
780
781#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
782#define nENABLE_SUSPENDM 0x0
783#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
784#define nSUSPEND_MODE 0x0
785#define RESUME_MODE 0x4 /* DMA Mode */
786#define nRESUME_MODE 0x0
787#define RESET 0x8 /* Reset indicator */
788#define nRESET 0x0
789#define HS_MODE 0x10 /* High Speed mode indicator */
790#define nHS_MODE 0x0
791#define HS_ENABLE 0x20 /* high Speed Enable */
792#define nHS_ENABLE 0x0
793#define SOFT_CONN 0x40 /* Soft connect */
794#define nSOFT_CONN 0x0
795#define ISO_UPDATE 0x80 /* Isochronous update */
796#define nISO_UPDATE 0x0
797
798/* Bit masks for USB_INTRTX */
799
800#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
801#define nEP0_TX 0x0
802#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
803#define nEP1_TX 0x0
804#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
805#define nEP2_TX 0x0
806#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
807#define nEP3_TX 0x0
808#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
809#define nEP4_TX 0x0
810#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
811#define nEP5_TX 0x0
812#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
813#define nEP6_TX 0x0
814#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
815#define nEP7_TX 0x0
816
817/* Bit masks for USB_INTRRX */
818
819#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
820#define nEP1_RX 0x0
821#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
822#define nEP2_RX 0x0
823#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
824#define nEP3_RX 0x0
825#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
826#define nEP4_RX 0x0
827#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
828#define nEP5_RX 0x0
829#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
830#define nEP6_RX 0x0
831#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
832#define nEP7_RX 0x0
833
834/* Bit masks for USB_INTRTXE */
835
836#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
837#define nEP0_TX_E 0x0
838#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
839#define nEP1_TX_E 0x0
840#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
841#define nEP2_TX_E 0x0
842#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
843#define nEP3_TX_E 0x0
844#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
845#define nEP4_TX_E 0x0
846#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
847#define nEP5_TX_E 0x0
848#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
849#define nEP6_TX_E 0x0
850#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
851#define nEP7_TX_E 0x0
852
853/* Bit masks for USB_INTRRXE */
854
855#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
856#define nEP1_RX_E 0x0
857#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
858#define nEP2_RX_E 0x0
859#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
860#define nEP3_RX_E 0x0
861#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
862#define nEP4_RX_E 0x0
863#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
864#define nEP5_RX_E 0x0
865#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
866#define nEP6_RX_E 0x0
867#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
868#define nEP7_RX_E 0x0
869
870/* Bit masks for USB_INTRUSB */
871
872#define SUSPEND_B 0x1 /* Suspend indicator */
873#define nSUSPEND_B 0x0
874#define RESUME_B 0x2 /* Resume indicator */
875#define nRESUME_B 0x0
876#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
877#define nRESET_OR_BABLE_B 0x0
878#define SOF_B 0x8 /* Start of frame */
879#define nSOF_B 0x0
880#define CONN_B 0x10 /* Connection indicator */
881#define nCONN_B 0x0
882#define DISCON_B 0x20 /* Disconnect indicator */
883#define nDISCON_B 0x0
884#define SESSION_REQ_B 0x40 /* Session Request */
885#define nSESSION_REQ_B 0x0
886#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
887#define nVBUS_ERROR_B 0x0
888
889/* Bit masks for USB_INTRUSBE */
890
891#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
892#define nSUSPEND_BE 0x0
893#define RESUME_BE 0x2 /* Resume indicator int enable */
894#define nRESUME_BE 0x0
895#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
896#define nRESET_OR_BABLE_BE 0x0
897#define SOF_BE 0x8 /* Start of frame int enable */
898#define nSOF_BE 0x0
899#define CONN_BE 0x10 /* Connection indicator int enable */
900#define nCONN_BE 0x0
901#define DISCON_BE 0x20 /* Disconnect indicator int enable */
902#define nDISCON_BE 0x0
903#define SESSION_REQ_BE 0x40 /* Session Request int enable */
904#define nSESSION_REQ_BE 0x0
905#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
906#define nVBUS_ERROR_BE 0x0
907
908/* Bit masks for USB_FRAME */
909
910#define FRAME_NUMBER 0x7ff /* Frame number */
911
912/* Bit masks for USB_INDEX */
913
914#define SELECTED_ENDPOINT 0xf /* selected endpoint */
915
916/* Bit masks for USB_GLOBAL_CTL */
917
918#define GLOBAL_ENA 0x1 /* enables USB module */
919#define nGLOBAL_ENA 0x0
920#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
921#define nEP1_TX_ENA 0x0
922#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
923#define nEP2_TX_ENA 0x0
924#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
925#define nEP3_TX_ENA 0x0
926#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
927#define nEP4_TX_ENA 0x0
928#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
929#define nEP5_TX_ENA 0x0
930#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
931#define nEP6_TX_ENA 0x0
932#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
933#define nEP7_TX_ENA 0x0
934#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
935#define nEP1_RX_ENA 0x0
936#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
937#define nEP2_RX_ENA 0x0
938#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
939#define nEP3_RX_ENA 0x0
940#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
941#define nEP4_RX_ENA 0x0
942#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
943#define nEP5_RX_ENA 0x0
944#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
945#define nEP6_RX_ENA 0x0
946#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
947#define nEP7_RX_ENA 0x0
948
949/* Bit masks for USB_OTG_DEV_CTL */
950
951#define SESSION 0x1 /* session indicator */
952#define nSESSION 0x0
953#define HOST_REQ 0x2 /* Host negotiation request */
954#define nHOST_REQ 0x0
955#define HOST_MODE 0x4 /* indicates USBDRC is a host */
956#define nHOST_MODE 0x0
957#define VBUS0 0x8 /* Vbus level indicator[0] */
958#define nVBUS0 0x0
959#define VBUS1 0x10 /* Vbus level indicator[1] */
960#define nVBUS1 0x0
961#define LSDEV 0x20 /* Low-speed indicator */
962#define nLSDEV 0x0
963#define FSDEV 0x40 /* Full or High-speed indicator */
964#define nFSDEV 0x0
965#define B_DEVICE 0x80 /* A' or 'B' device indicator */
966#define nB_DEVICE 0x0
967
968/* Bit masks for USB_OTG_VBUS_IRQ */
969
970#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
971#define nDRIVE_VBUS_ON 0x0
972#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
973#define nDRIVE_VBUS_OFF 0x0
974#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
975#define nCHRG_VBUS_START 0x0
976#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
977#define nCHRG_VBUS_END 0x0
978#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
979#define nDISCHRG_VBUS_START 0x0
980#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
981#define nDISCHRG_VBUS_END 0x0
982
983/* Bit masks for USB_OTG_VBUS_MASK */
984
985#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
986#define nDRIVE_VBUS_ON_ENA 0x0
987#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
988#define nDRIVE_VBUS_OFF_ENA 0x0
989#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
990#define nCHRG_VBUS_START_ENA 0x0
991#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
992#define nCHRG_VBUS_END_ENA 0x0
993#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
994#define nDISCHRG_VBUS_START_ENA 0x0
995#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
996#define nDISCHRG_VBUS_END_ENA 0x0
997
998/* Bit masks for USB_CSR0 */
999
1000#define RXPKTRDY 0x1 /* data packet receive indicator */
1001#define nRXPKTRDY 0x0
1002#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1003#define nTXPKTRDY 0x0
1004#define STALL_SENT 0x4 /* STALL handshake sent */
1005#define nSTALL_SENT 0x0
1006#define DATAEND 0x8 /* Data end indicator */
1007#define nDATAEND 0x0
1008#define SETUPEND 0x10 /* Setup end */
1009#define nSETUPEND 0x0
1010#define SENDSTALL 0x20 /* Send STALL handshake */
1011#define nSENDSTALL 0x0
1012#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1013#define nSERVICED_RXPKTRDY 0x0
1014#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1015#define nSERVICED_SETUPEND 0x0
1016#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1017#define nFLUSHFIFO 0x0
1018#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1019#define nSTALL_RECEIVED_H 0x0
1020#define SETUPPKT_H 0x8 /* send Setup token host mode */
1021#define nSETUPPKT_H 0x0
1022#define ERROR_H 0x10 /* timeout error indicator host mode */
1023#define nERROR_H 0x0
1024#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1025#define nREQPKT_H 0x0
1026#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1027#define nSTATUSPKT_H 0x0
1028#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1029#define nNAK_TIMEOUT_H 0x0
1030
1031/* Bit masks for USB_COUNT0 */
1032
1033#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1034
1035/* Bit masks for USB_NAKLIMIT0 */
1036
1037#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1038
1039/* Bit masks for USB_TX_MAX_PACKET */
1040
1041#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1042
1043/* Bit masks for USB_RX_MAX_PACKET */
1044
1045#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1046
1047/* Bit masks for USB_TXCSR */
1048
1049#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1050#define nTXPKTRDY_T 0x0
1051#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1052#define nFIFO_NOT_EMPTY_T 0x0
1053#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1054#define nUNDERRUN_T 0x0
1055#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1056#define nFLUSHFIFO_T 0x0
1057#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1058#define nSTALL_SEND_T 0x0
1059#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1060#define nSTALL_SENT_T 0x0
1061#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1062#define nCLEAR_DATATOGGLE_T 0x0
1063#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1064#define nINCOMPTX_T 0x0
1065#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1066#define nDMAREQMODE_T 0x0
1067#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1068#define nFORCE_DATATOGGLE_T 0x0
1069#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1070#define nDMAREQ_ENA_T 0x0
1071#define ISO_T 0x4000 /* enable Isochronous transfers */
1072#define nISO_T 0x0
1073#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1074#define nAUTOSET_T 0x0
1075#define ERROR_TH 0x4 /* error condition host mode */
1076#define nERROR_TH 0x0
1077#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1078#define nSTALL_RECEIVED_TH 0x0
1079#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1080#define nNAK_TIMEOUT_TH 0x0
1081
1082/* Bit masks for USB_TXCOUNT */
1083
1084#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1085
1086/* Bit masks for USB_RXCSR */
1087
1088#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1089#define nRXPKTRDY_R 0x0
1090#define FIFO_FULL_R 0x2 /* FIFO not empty */
1091#define nFIFO_FULL_R 0x0
1092#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1093#define nOVERRUN_R 0x0
1094#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1095#define nDATAERROR_R 0x0
1096#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1097#define nFLUSHFIFO_R 0x0
1098#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1099#define nSTALL_SEND_R 0x0
1100#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1101#define nSTALL_SENT_R 0x0
1102#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1103#define nCLEAR_DATATOGGLE_R 0x0
1104#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1105#define nINCOMPRX_R 0x0
1106#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1107#define nDMAREQMODE_R 0x0
1108#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1109#define nDISNYET_R 0x0
1110#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1111#define nDMAREQ_ENA_R 0x0
1112#define ISO_R 0x4000 /* enable Isochronous transfers */
1113#define nISO_R 0x0
1114#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1115#define nAUTOCLEAR_R 0x0
1116#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1117#define nERROR_RH 0x0
1118#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1119#define nREQPKT_RH 0x0
1120#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1121#define nSTALL_RECEIVED_RH 0x0
1122#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1123#define nINCOMPRX_RH 0x0
1124#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1125#define nDMAREQMODE_RH 0x0
1126#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1127#define nAUTOREQ_RH 0x0
1128
1129/* Bit masks for USB_RXCOUNT */
1130
1131#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1132
1133/* Bit masks for USB_TXTYPE */
1134
1135#define TARGET_EP_NO_T 0xf /* EP number */
1136#define PROTOCOL_T 0xc /* transfer type */
1137
1138/* Bit masks for USB_TXINTERVAL */
1139
1140#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1141
1142/* Bit masks for USB_RXTYPE */
1143
1144#define TARGET_EP_NO_R 0xf /* EP number */
1145#define PROTOCOL_R 0xc /* transfer type */
1146
1147/* Bit masks for USB_RXINTERVAL */
1148
1149#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1150
1151/* Bit masks for USB_DMA_INTERRUPT */
1152
1153#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1154#define nDMA0_INT 0x0
1155#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1156#define nDMA1_INT 0x0
1157#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1158#define nDMA2_INT 0x0
1159#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1160#define nDMA3_INT 0x0
1161#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1162#define nDMA4_INT 0x0
1163#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1164#define nDMA5_INT 0x0
1165#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1166#define nDMA6_INT 0x0
1167#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1168#define nDMA7_INT 0x0
1169
1170/* Bit masks for USB_DMAxCONTROL */
1171
1172#define DMA_ENA 0x1 /* DMA enable */
1173#define nDMA_ENA 0x0
1174#define DIRECTION 0x2 /* direction of DMA transfer */
1175#define nDIRECTION 0x0
1176#define MODE 0x4 /* DMA Bus error */
1177#define nMODE 0x0
1178#define INT_ENA 0x8 /* Interrupt enable */
1179#define nINT_ENA 0x0
1180#define EPNUM 0xf0 /* EP number */
1181#define BUSERROR 0x100 /* DMA Bus error */
1182#define nBUSERROR 0x0
1183
1184/* Bit masks for USB_DMAxADDRHIGH */
1185
1186#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1187
1188/* Bit masks for USB_DMAxADDRLOW */
1189
1190#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1191
1192/* Bit masks for USB_DMAxCOUNTHIGH */
1193
1194#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1195
1196/* Bit masks for USB_DMAxCOUNTLOW */
1197
1198#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1199
1200
1201/* ******************************************* */
1202/* MULTI BIT MACRO ENUMERATIONS */
1203/* ******************************************* */
1204
1205
1206#endif /* _DEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
new file mode 100644
index 000000000000..8fc77ea12aa9
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -0,0 +1,766 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF544.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF544_H
32#define _DEF_BF544_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* EPPI0 Registers */
66
67#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
68#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
69#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
70#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
71#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
72#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
73#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
74#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
75#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
76#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
77#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
78#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
79#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
80#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
81
82/* Two Wire Interface Registers (TWI1) */
83
84#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
85#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
86#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
87#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
88#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
89#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
90#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
91#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
92#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
93#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
94#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
95#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
96#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
97#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
98#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
99#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
100
101/* CAN Controller 1 Config 1 Registers */
102
103#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
104#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
105#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
106#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
107#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
108#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
109#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
110#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
111#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
112#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
113#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
114#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
115#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
116
117/* CAN Controller 1 Config 2 Registers */
118
119#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
120#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
121#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
122#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
123#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
124#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
125#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
126#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
127#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
128#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
129#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
130#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
131#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
132
133/* CAN Controller 1 Clock/Interrupt/Counter Registers */
134
135#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
136#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
137#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
138#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
139#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
140#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
141#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
142#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
143#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
144#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
145#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
146#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
147#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
148#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
149#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
150#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
151
152/* CAN Controller 1 Mailbox Acceptance Registers */
153
154#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
155#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
156#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
157#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
158#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
159#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
160#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
161#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
162#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
163#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
164#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
165#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
166#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
167#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
168#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
169#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
170#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
171#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
172#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
173#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
174#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
175#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
176#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
177#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
178#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
179#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
180#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
181#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
182#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
183#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
184#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
185#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
186
187/* CAN Controller 1 Mailbox Acceptance Registers */
188
189#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
190#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
191#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
192#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
193#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
194#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
195#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
196#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
197#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
198#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
199#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
200#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
201#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
202#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
203#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
204#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
205#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
206#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
207#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
208#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
209#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
210#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
211#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
212#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
213#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
214#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
215#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
216#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
217#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
218#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
219#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
220#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
221
222/* CAN Controller 1 Mailbox Data Registers */
223
224#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
225#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
226#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
227#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
228#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
229#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
230#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
231#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
232#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
233#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
234#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
235#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
236#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
237#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
238#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
239#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
240#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
241#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
242#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
243#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
244#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
245#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
246#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
247#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
248#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
249#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
250#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
251#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
252#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
253#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
254#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
255#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
256#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
257#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
258#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
259#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
260#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
261#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
262#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
263#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
264#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
265#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
266#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
267#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
268#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
269#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
270#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
271#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
272#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
273#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
274#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
275#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
276#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
277#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
278#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
279#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
280#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
281#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
282#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
283#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
284#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
285#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
286#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
287#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
288#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
289#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
290#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
291#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
292#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
293#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
294#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
295#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
296#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
297#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
298#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
299#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
300#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
301#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
302#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
303#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
304#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
305#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
306#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
307#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
308#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
309#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
310#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
311#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
312#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
313#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
314#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
315#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
316#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
317#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
318#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
319#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
320#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
321#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
322#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
323#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
324#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
325#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
326#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
327#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
328#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
329#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
330#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
331#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
332#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
333#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
334#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
335#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
336#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
337#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
338#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
339#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
340#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
341#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
342#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
343#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
344#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
345#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
346#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
347#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
348#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
349#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
350#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
351#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
352
353/* CAN Controller 1 Mailbox Data Registers */
354
355#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
356#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
357#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
358#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
359#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
360#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
361#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
362#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
363#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
364#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
365#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
366#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
367#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
368#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
369#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
370#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
371#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
372#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
373#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
374#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
375#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
376#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
377#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
378#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
379#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
380#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
381#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
382#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
383#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
384#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
385#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
386#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
387#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
388#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
389#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
390#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
391#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
392#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
393#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
394#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
395#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
396#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
397#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
398#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
399#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
400#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
401#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
402#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
403#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
404#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
405#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
406#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
407#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
408#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
409#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
410#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
411#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
412#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
413#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
414#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
415#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
416#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
417#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
418#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
419#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
420#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
421#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
422#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
423#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
424#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
425#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
426#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
427#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
428#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
429#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
430#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
431#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
432#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
433#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
434#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
435#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
436#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
437#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
438#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
439#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
440#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
441#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
442#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
443#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
444#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
445#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
446#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
447#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
448#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
449#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
450#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
451#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
452#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
453#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
454#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
455#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
456#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
457#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
458#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
459#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
460#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
461#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
462#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
463#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
464#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
465#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
466#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
467#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
468#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
469#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
470#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
471#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
472#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
473#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
474#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
475#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
476#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
477#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
478#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
479#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
480#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
481#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
482#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
483
484/* HOST Port Registers */
485
486#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
487#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
488#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
489
490/* Pixel Compositor (PIXC) Registers */
491
492#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
493#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
494#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
495#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
496#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
497#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
498#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
499#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
500#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
501#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
502#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
503#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
504#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
505#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
506#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
507#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
508#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
509#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
510#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
511
512/* Handshake MDMA 0 Registers */
513
514#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
515#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
516#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
517#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
518#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
519#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
520#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
521
522/* Handshake MDMA 1 Registers */
523
524#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
525#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
526#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
527#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
528#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
529#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
530#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
531
532
533/* ********************************************************** */
534/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
535/* and MULTI BIT READ MACROS */
536/* ********************************************************** */
537
538/* Bit masks for PIXC_CTL */
539
540#define PIXC_EN 0x1 /* Pixel Compositor Enable */
541#define nPIXC_EN 0x0
542#define OVR_A_EN 0x2 /* Overlay A Enable */
543#define nOVR_A_EN 0x0
544#define OVR_B_EN 0x4 /* Overlay B Enable */
545#define nOVR_B_EN 0x0
546#define IMG_FORM 0x8 /* Image Data Format */
547#define nIMG_FORM 0x0
548#define OVR_FORM 0x10 /* Overlay Data Format */
549#define nOVR_FORM 0x0
550#define OUT_FORM 0x20 /* Output Data Format */
551#define nOUT_FORM 0x0
552#define UDS_MOD 0x40 /* Resampling Mode */
553#define nUDS_MOD 0x0
554#define TC_EN 0x80 /* Transparent Color Enable */
555#define nTC_EN 0x0
556#define IMG_STAT 0x300 /* Image FIFO Status */
557#define OVR_STAT 0xc00 /* Overlay FIFO Status */
558#define WM_LVL 0x3000 /* FIFO Watermark Level */
559
560/* Bit masks for PIXC_AHSTART */
561
562#define A_HSTART 0xfff /* Horizontal Start Coordinates */
563
564/* Bit masks for PIXC_AHEND */
565
566#define A_HEND 0xfff /* Horizontal End Coordinates */
567
568/* Bit masks for PIXC_AVSTART */
569
570#define A_VSTART 0x3ff /* Vertical Start Coordinates */
571
572/* Bit masks for PIXC_AVEND */
573
574#define A_VEND 0x3ff /* Vertical End Coordinates */
575
576/* Bit masks for PIXC_ATRANSP */
577
578#define A_TRANSP 0xf /* Transparency Value */
579
580/* Bit masks for PIXC_BHSTART */
581
582#define B_HSTART 0xfff /* Horizontal Start Coordinates */
583
584/* Bit masks for PIXC_BHEND */
585
586#define B_HEND 0xfff /* Horizontal End Coordinates */
587
588/* Bit masks for PIXC_BVSTART */
589
590#define B_VSTART 0x3ff /* Vertical Start Coordinates */
591
592/* Bit masks for PIXC_BVEND */
593
594#define B_VEND 0x3ff /* Vertical End Coordinates */
595
596/* Bit masks for PIXC_BTRANSP */
597
598#define B_TRANSP 0xf /* Transparency Value */
599
600/* Bit masks for PIXC_INTRSTAT */
601
602#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
603#define nOVR_INT_EN 0x0
604#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
605#define nFRM_INT_EN 0x0
606#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
607#define nOVR_INT_STAT 0x0
608#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
609#define nFRM_INT_STAT 0x0
610
611/* Bit masks for PIXC_RYCON */
612
613#define A11 0x3ff /* A11 in the Coefficient Matrix */
614#define A12 0xffc00 /* A12 in the Coefficient Matrix */
615#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
616#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
617#define nRY_MULT4 0x0
618
619/* Bit masks for PIXC_GUCON */
620
621#define A21 0x3ff /* A21 in the Coefficient Matrix */
622#define A22 0xffc00 /* A22 in the Coefficient Matrix */
623#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
624#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
625#define nGU_MULT4 0x0
626
627/* Bit masks for PIXC_BVCON */
628
629#define A31 0x3ff /* A31 in the Coefficient Matrix */
630#define A32 0xffc00 /* A32 in the Coefficient Matrix */
631#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
632#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
633#define nBV_MULT4 0x0
634
635/* Bit masks for PIXC_CCBIAS */
636
637#define A14 0x3ff /* A14 in the Bias Vector */
638#define A24 0xffc00 /* A24 in the Bias Vector */
639#define A34 0x3ff00000 /* A34 in the Bias Vector */
640
641/* Bit masks for PIXC_TC */
642
643#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
644#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
645#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
646
647/* Bit masks for HOST_CONTROL */
648
649#define HOST_EN 0x1 /* Host Enable */
650#define nHOST_EN 0x0
651#define HOST_END 0x2 /* Host Endianess */
652#define nHOST_END 0x0
653#define DATA_SIZE 0x4 /* Data Size */
654#define nDATA_SIZE 0x0
655#define HOST_RST 0x8 /* Host Reset */
656#define nHOST_RST 0x0
657#define HRDY_OVR 0x20 /* Host Ready Override */
658#define nHRDY_OVR 0x0
659#define INT_MODE 0x40 /* Interrupt Mode */
660#define nINT_MODE 0x0
661#define BT_EN 0x80 /* Bus Timeout Enable */
662#define nBT_EN 0x0
663#define EHW 0x100 /* Enable Host Write */
664#define nEHW 0x0
665#define EHR 0x200 /* Enable Host Read */
666#define nEHR 0x0
667#define BDR 0x400 /* Burst DMA Requests */
668#define nBDR 0x0
669
670/* Bit masks for HOST_STATUS */
671
672#define READY 0x1 /* DMA Ready */
673#define nREADY 0x0
674#define FIFOFULL 0x2 /* FIFO Full */
675#define nFIFOFULL 0x0
676#define FIFOEMPTY 0x4 /* FIFO Empty */
677#define nFIFOEMPTY 0x0
678#define COMPLETE 0x8 /* DMA Complete */
679#define nCOMPLETE 0x0
680#define HSHK 0x10 /* Host Handshake */
681#define nHSHK 0x0
682#define TIMEOUT 0x20 /* Host Timeout */
683#define nTIMEOUT 0x0
684#define HIRQ 0x40 /* Host Interrupt Request */
685#define nHIRQ 0x0
686#define ALLOW_CNFG 0x80 /* Allow New Configuration */
687#define nALLOW_CNFG 0x0
688#define DMA_DIR 0x100 /* DMA Direction */
689#define nDMA_DIR 0x0
690#define BTE 0x200 /* Bus Timeout Enabled */
691#define nBTE 0x0
692
693/* Bit masks for HOST_TIMEOUT */
694
695#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
696
697/* Bit masks for TIMER_ENABLE1 */
698
699#define TIMEN8 0x1 /* Timer 8 Enable */
700#define nTIMEN8 0x0
701#define TIMEN9 0x2 /* Timer 9 Enable */
702#define nTIMEN9 0x0
703#define TIMEN10 0x4 /* Timer 10 Enable */
704#define nTIMEN10 0x0
705
706/* Bit masks for TIMER_DISABLE1 */
707
708#define TIMDIS8 0x1 /* Timer 8 Disable */
709#define nTIMDIS8 0x0
710#define TIMDIS9 0x2 /* Timer 9 Disable */
711#define nTIMDIS9 0x0
712#define TIMDIS10 0x4 /* Timer 10 Disable */
713#define nTIMDIS10 0x0
714
715/* Bit masks for TIMER_STATUS1 */
716
717#define TIMIL8 0x1 /* Timer 8 Interrupt */
718#define nTIMIL8 0x0
719#define TIMIL9 0x2 /* Timer 9 Interrupt */
720#define nTIMIL9 0x0
721#define TIMIL10 0x4 /* Timer 10 Interrupt */
722#define nTIMIL10 0x0
723#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
724#define nTOVF_ERR8 0x0
725#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
726#define nTOVF_ERR9 0x0
727#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
728#define nTOVF_ERR10 0x0
729#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
730#define nTRUN8 0x0
731#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
732#define nTRUN9 0x0
733#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
734#define nTRUN10 0x0
735
736/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
737
738/* Bit masks for HMDMAx_CONTROL */
739
740#define HMDMAEN 0x1 /* Handshake MDMA Enable */
741#define nHMDMAEN 0x0
742#define REP 0x2 /* Handshake MDMA Request Polarity */
743#define nREP 0x0
744#define UTE 0x8 /* Urgency Threshold Enable */
745#define nUTE 0x0
746#define OIE 0x10 /* Overflow Interrupt Enable */
747#define nOIE 0x0
748#define BDIE 0x20 /* Block Done Interrupt Enable */
749#define nBDIE 0x0
750#define MBDI 0x40 /* Mask Block Done Interrupt */
751#define nMBDI 0x0
752#define DRQ 0x300 /* Handshake MDMA Request Type */
753#define RBC 0x1000 /* Force Reload of BCOUNT */
754#define nRBC 0x0
755#define PS 0x2000 /* Pin Status */
756#define nPS 0x0
757#define OI 0x4000 /* Overflow Interrupt Generated */
758#define nOI 0x0
759#define BDI 0x8000 /* Block Done Interrupt Generated */
760#define nBDI 0x0
761
762/* ******************************************* */
763/* MULTI BIT MACRO ENUMERATIONS */
764/* ******************************************* */
765
766#endif /* _DEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
new file mode 100644
index 000000000000..d9e3062a9117
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -0,0 +1,1966 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF548.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF548_H
32#define _DEF_BF548_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
38
39/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
40#include "defBF54x_base.h"
41
42/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
43
44/* Timer Registers */
45
46#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
47#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
48#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
49#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
50#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
51#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
52#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
53#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
54#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
55#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
56#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
57#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
58
59/* Timer Group of 3 Registers */
60
61#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
62#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
63#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
64
65/* SPORT0 Registers */
66
67#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
68#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
69#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
70#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
71#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
72#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
73#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
74#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
75#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
76#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
77#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
78#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
79#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
80#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
81#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
82#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
83#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
84#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
85#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
86#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
87#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
88#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
89
90/* EPPI0 Registers */
91
92#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
93#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
94#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
95#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
96#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
97#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
98#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
99#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
100#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
101#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
102#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
103#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
104#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
105#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
106
107/* UART2 Registers */
108
109#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
110#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
111#define UART2_GCTL 0xffc02108 /* Global Control Register */
112#define UART2_LCR 0xffc0210c /* Line Control Register */
113#define UART2_MCR 0xffc02110 /* Modem Control Register */
114#define UART2_LSR 0xffc02114 /* Line Status Register */
115#define UART2_MSR 0xffc02118 /* Modem Status Register */
116#define UART2_SCR 0xffc0211c /* Scratch Register */
117#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
118#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
119#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
120
121/* Two Wire Interface Registers (TWI1) */
122
123#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
124#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
125#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
126#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
127#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
128#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
129#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
130#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
131#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
132#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
133#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
134#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
135#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
136#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
137#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
138#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
139
140/* SPI2 Registers */
141
142#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
143#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
144#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
145#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
146#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
147#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
148#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
149
150/* CAN Controller 1 Config 1 Registers */
151
152#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
153#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
154#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
155#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
156#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
157#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
158#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
159#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
160#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
161#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
162#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
163#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
164#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
165
166/* CAN Controller 1 Config 2 Registers */
167
168#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
169#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
170#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
171#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
172#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
173#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
174#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
175#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
176#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
177#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
178#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
179#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
180#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
181
182/* CAN Controller 1 Clock/Interrupt/Counter Registers */
183
184#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
185#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
186#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
187#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
188#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
189#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
190#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
191#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
192#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
193#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
194#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
195#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
196#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
197#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
198#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
199#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
200
201/* CAN Controller 1 Mailbox Acceptance Registers */
202
203#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
204#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
205#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
206#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
207#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
208#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
209#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
210#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
211#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
212#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
213#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
214#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
215#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
216#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
217#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
218#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
219#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
220#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
221#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
222#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
223#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
224#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
225#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
226#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
227#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
228#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
229#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
230#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
231#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
232#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
233#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
234#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
235
236/* CAN Controller 1 Mailbox Acceptance Registers */
237
238#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
239#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
240#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
241#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
242#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
243#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
244#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
245#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
246#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
247#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
248#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
249#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
250#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
251#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
252#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
253#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
254#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
255#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
256#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
257#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
258#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
259#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
260#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
261#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
262#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
263#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
264#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
265#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
266#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
267#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
268#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
269#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
270
271/* CAN Controller 1 Mailbox Data Registers */
272
273#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
274#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
275#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
276#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
277#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
278#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
279#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
280#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
281#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
282#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
283#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
284#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
285#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
286#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
287#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
288#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
289#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
290#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
291#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
292#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
293#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
294#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
295#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
296#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
297#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
298#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
299#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
300#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
301#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
302#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
303#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
304#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
305#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
306#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
307#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
308#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
309#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
310#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
311#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
312#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
313#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
314#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
315#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
316#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
317#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
318#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
319#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
320#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
321#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
322#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
323#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
324#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
325#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
326#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
327#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
328#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
329#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
330#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
331#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
332#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
333#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
334#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
335#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
336#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
337#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
338#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
339#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
340#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
341#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
342#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
343#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
344#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
345#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
346#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
347#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
348#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
349#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
350#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
351#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
352#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
353#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
354#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
355#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
356#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
357#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
358#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
359#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
360#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
361#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
362#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
363#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
364#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
365#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
366#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
367#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
368#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
369#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
370#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
371#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
372#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
373#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
374#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
375#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
376#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
377#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
378#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
379#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
380#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
381#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
382#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
383#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
384#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
385#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
386#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
387#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
388#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
389#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
390#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
391#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
392#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
393#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
394#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
395#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
396#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
397#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
398#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
399#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
400#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
401
402/* CAN Controller 1 Mailbox Data Registers */
403
404#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
405#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
406#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
407#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
408#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
409#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
410#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
411#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
412#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
413#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
414#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
415#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
416#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
417#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
418#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
419#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
420#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
421#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
422#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
423#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
424#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
425#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
426#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
427#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
428#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
429#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
430#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
431#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
432#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
433#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
434#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
435#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
436#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
437#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
438#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
439#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
440#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
441#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
442#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
443#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
444#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
445#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
446#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
447#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
448#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
449#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
450#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
451#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
452#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
453#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
454#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
455#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
456#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
457#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
458#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
459#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
460#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
461#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
462#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
463#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
464#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
465#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
466#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
467#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
468#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
469#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
470#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
471#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
472#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
473#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
474#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
475#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
476#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
477#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
478#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
479#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
480#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
481#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
482#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
483#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
484#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
485#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
486#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
487#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
488#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
489#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
490#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
491#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
492#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
493#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
494#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
495#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
496#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
497#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
498#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
499#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
500#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
501#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
502#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
503#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
504#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
505#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
506#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
507#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
508#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
509#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
510#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
511#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
512#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
513#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
514#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
515#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
516#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
517#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
518#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
519#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
520#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
521#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
522#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
523#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
524#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
525#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
526#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
527#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
528#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
529#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
530#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
531#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
532
533/* ATAPI Registers */
534
535#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
536#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
537#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
538#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
539#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
540#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
541#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
542#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
543#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
544#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
545#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
546#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
547#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
548#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
549#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
550#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
551#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
552#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
553#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
554#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
555#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
556#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
557#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
558#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
559#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
560
561/* SDH Registers */
562
563#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
564#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
565#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
566#define SDH_COMMAND 0xffc0390c /* SDH Command */
567#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
568#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
569#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
570#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
571#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
572#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
573#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
574#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
575#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
576#define SDH_STATUS 0xffc03934 /* SDH Status */
577#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
578#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
579#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
580#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
581#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
582#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
583#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
584#define SDH_CFG 0xffc039c8 /* SDH Configuration */
585#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
586#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
587#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
588#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
589#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
590#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
591#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
592#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
593#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
594
595/* HOST Port Registers */
596
597#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
598#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
599#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
600
601/* USB Control Registers */
602
603#define USB_FADDR 0xffc03c00 /* Function address register */
604#define USB_POWER 0xffc03c04 /* Power management register */
605#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
606#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
607#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
608#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
609#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
610#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
611#define USB_FRAME 0xffc03c20 /* USB frame number */
612#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
613#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
614#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
615#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
616
617/* USB Packet Control Registers */
618
619#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
620#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
621#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
622#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
623#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
624#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
625#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
626#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
627#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
628#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
629#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
630#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
631#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
632
633/* USB Endpoint FIFO Registers */
634
635#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
636#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
637#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
638#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
639#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
640#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
641#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
642#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
643
644/* USB OTG Control Registers */
645
646#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
647#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
648#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
649
650/* USB Phy Control Registers */
651
652#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
653#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
654#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
655#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
656#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
657
658/* (APHY_CNTRL is for ADI usage only) */
659
660#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
661
662/* (APHY_CALIB is for ADI usage only) */
663
664#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
665#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
666
667/* (PHY_TEST is for ADI usage only) */
668
669#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
670#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
671#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
672
673/* USB Endpoint 0 Control Registers */
674
675#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
676#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
677#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
678#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
679#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
680#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
681#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
682#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
683#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
684
685/* USB Endpoint 1 Control Registers */
686
687#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
688#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
689#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
690#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
691#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
692#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
693#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
694#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
695#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
696#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
697
698/* USB Endpoint 2 Control Registers */
699
700#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
701#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
702#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
703#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
704#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
705#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
706#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
707#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
708#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
709#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
710
711/* USB Endpoint 3 Control Registers */
712
713#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
714#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
715#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
716#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
717#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
718#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
719#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
720#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
721#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
722#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
723
724/* USB Endpoint 4 Control Registers */
725
726#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
727#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
728#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
729#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
730#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
731#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
732#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
733#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
734#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
735#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
736
737/* USB Endpoint 5 Control Registers */
738
739#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
740#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
741#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
742#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
743#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
744#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
745#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
746#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
747#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
748#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
749
750/* USB Endpoint 6 Control Registers */
751
752#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
753#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
754#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
755#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
756#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
757#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
758#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
759#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
760#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
761#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
762
763/* USB Endpoint 7 Control Registers */
764
765#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
766#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
767#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
768#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
769#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
770#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
771#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
772#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
773#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
774#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
775#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
776#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
777
778/* USB Channel 0 Config Registers */
779
780#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
781#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
782#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
783#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
784#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
785
786/* USB Channel 1 Config Registers */
787
788#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
789#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
790#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
791#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
792#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
793
794/* USB Channel 2 Config Registers */
795
796#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
797#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
798#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
799#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
800#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
801
802/* USB Channel 3 Config Registers */
803
804#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
805#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
806#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
807#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
808#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
809
810/* USB Channel 4 Config Registers */
811
812#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
813#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
814#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
815#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
816#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
817
818/* USB Channel 5 Config Registers */
819
820#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
821#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
822#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
823#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
824#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
825
826/* USB Channel 6 Config Registers */
827
828#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
829#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
830#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
831#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
832#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
833
834/* USB Channel 7 Config Registers */
835
836#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
837#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
838#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
839#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
840#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
841
842/* Keypad Registers */
843
844#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
845#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
846#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
847#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
848#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
849#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
850
851/* Pixel Compositor (PIXC) Registers */
852
853#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
854#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
855#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
856#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
857#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
858#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
859#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
860#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
861#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
862#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
863#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
864#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
865#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
866#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
867#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
868#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
869#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
870#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
871#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
872
873/* Handshake MDMA 0 Registers */
874
875#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
876#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
877#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
878#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
879#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
880#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
881#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
882
883/* Handshake MDMA 1 Registers */
884
885#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
886#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
887#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
888#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
889#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
890#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
891#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
892
893
894/* ********************************************************** */
895/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
896/* and MULTI BIT READ MACROS */
897/* ********************************************************** */
898
899/* Bit masks for PIXC_CTL */
900
901#define PIXC_EN 0x1 /* Pixel Compositor Enable */
902#define nPIXC_EN 0x0
903#define OVR_A_EN 0x2 /* Overlay A Enable */
904#define nOVR_A_EN 0x0
905#define OVR_B_EN 0x4 /* Overlay B Enable */
906#define nOVR_B_EN 0x0
907#define IMG_FORM 0x8 /* Image Data Format */
908#define nIMG_FORM 0x0
909#define OVR_FORM 0x10 /* Overlay Data Format */
910#define nOVR_FORM 0x0
911#define OUT_FORM 0x20 /* Output Data Format */
912#define nOUT_FORM 0x0
913#define UDS_MOD 0x40 /* Resampling Mode */
914#define nUDS_MOD 0x0
915#define TC_EN 0x80 /* Transparent Color Enable */
916#define nTC_EN 0x0
917#define IMG_STAT 0x300 /* Image FIFO Status */
918#define OVR_STAT 0xc00 /* Overlay FIFO Status */
919#define WM_LVL 0x3000 /* FIFO Watermark Level */
920
921/* Bit masks for PIXC_AHSTART */
922
923#define A_HSTART 0xfff /* Horizontal Start Coordinates */
924
925/* Bit masks for PIXC_AHEND */
926
927#define A_HEND 0xfff /* Horizontal End Coordinates */
928
929/* Bit masks for PIXC_AVSTART */
930
931#define A_VSTART 0x3ff /* Vertical Start Coordinates */
932
933/* Bit masks for PIXC_AVEND */
934
935#define A_VEND 0x3ff /* Vertical End Coordinates */
936
937/* Bit masks for PIXC_ATRANSP */
938
939#define A_TRANSP 0xf /* Transparency Value */
940
941/* Bit masks for PIXC_BHSTART */
942
943#define B_HSTART 0xfff /* Horizontal Start Coordinates */
944
945/* Bit masks for PIXC_BHEND */
946
947#define B_HEND 0xfff /* Horizontal End Coordinates */
948
949/* Bit masks for PIXC_BVSTART */
950
951#define B_VSTART 0x3ff /* Vertical Start Coordinates */
952
953/* Bit masks for PIXC_BVEND */
954
955#define B_VEND 0x3ff /* Vertical End Coordinates */
956
957/* Bit masks for PIXC_BTRANSP */
958
959#define B_TRANSP 0xf /* Transparency Value */
960
961/* Bit masks for PIXC_INTRSTAT */
962
963#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
964#define nOVR_INT_EN 0x0
965#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
966#define nFRM_INT_EN 0x0
967#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
968#define nOVR_INT_STAT 0x0
969#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
970#define nFRM_INT_STAT 0x0
971
972/* Bit masks for PIXC_RYCON */
973
974#define A11 0x3ff /* A11 in the Coefficient Matrix */
975#define A12 0xffc00 /* A12 in the Coefficient Matrix */
976#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
977#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
978#define nRY_MULT4 0x0
979
980/* Bit masks for PIXC_GUCON */
981
982#define A21 0x3ff /* A21 in the Coefficient Matrix */
983#define A22 0xffc00 /* A22 in the Coefficient Matrix */
984#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
985#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
986#define nGU_MULT4 0x0
987
988/* Bit masks for PIXC_BVCON */
989
990#define A31 0x3ff /* A31 in the Coefficient Matrix */
991#define A32 0xffc00 /* A32 in the Coefficient Matrix */
992#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
993#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
994#define nBV_MULT4 0x0
995
996/* Bit masks for PIXC_CCBIAS */
997
998#define A14 0x3ff /* A14 in the Bias Vector */
999#define A24 0xffc00 /* A24 in the Bias Vector */
1000#define A34 0x3ff00000 /* A34 in the Bias Vector */
1001
1002/* Bit masks for PIXC_TC */
1003
1004#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
1005#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
1006#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
1007
1008/* Bit masks for HOST_CONTROL */
1009
1010#define HOST_EN 0x1 /* Host Enable */
1011#define nHOST_EN 0x0
1012#define HOST_END 0x2 /* Host Endianess */
1013#define nHOST_END 0x0
1014#define DATA_SIZE 0x4 /* Data Size */
1015#define nDATA_SIZE 0x0
1016#define HOST_RST 0x8 /* Host Reset */
1017#define nHOST_RST 0x0
1018#define HRDY_OVR 0x20 /* Host Ready Override */
1019#define nHRDY_OVR 0x0
1020#define INT_MODE 0x40 /* Interrupt Mode */
1021#define nINT_MODE 0x0
1022#define BT_EN 0x80 /* Bus Timeout Enable */
1023#define nBT_EN 0x0
1024#define EHW 0x100 /* Enable Host Write */
1025#define nEHW 0x0
1026#define EHR 0x200 /* Enable Host Read */
1027#define nEHR 0x0
1028#define BDR 0x400 /* Burst DMA Requests */
1029#define nBDR 0x0
1030
1031/* Bit masks for HOST_STATUS */
1032
1033#define READY 0x1 /* DMA Ready */
1034#define nREADY 0x0
1035#define FIFOFULL 0x2 /* FIFO Full */
1036#define nFIFOFULL 0x0
1037#define FIFOEMPTY 0x4 /* FIFO Empty */
1038#define nFIFOEMPTY 0x0
1039#define COMPLETE 0x8 /* DMA Complete */
1040#define nCOMPLETE 0x0
1041#define HSHK 0x10 /* Host Handshake */
1042#define nHSHK 0x0
1043#define TIMEOUT 0x20 /* Host Timeout */
1044#define nTIMEOUT 0x0
1045#define HIRQ 0x40 /* Host Interrupt Request */
1046#define nHIRQ 0x0
1047#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1048#define nALLOW_CNFG 0x0
1049#define DMA_DIR 0x100 /* DMA Direction */
1050#define nDMA_DIR 0x0
1051#define BTE 0x200 /* Bus Timeout Enabled */
1052#define nBTE 0x0
1053
1054/* Bit masks for HOST_TIMEOUT */
1055
1056#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1057
1058/* Bit masks for KPAD_CTL */
1059
1060#define KPAD_EN 0x1 /* Keypad Enable */
1061#define nKPAD_EN 0x0
1062#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
1063#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
1064#define KPAD_COLEN 0xe000 /* Column Enable Width */
1065
1066/* Bit masks for KPAD_PRESCALE */
1067
1068#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
1069
1070/* Bit masks for KPAD_MSEL */
1071
1072#define DBON_SCALE 0xff /* Debounce Scale Value */
1073#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
1074
1075/* Bit masks for KPAD_ROWCOL */
1076
1077#define KPAD_ROW 0xff /* Rows Pressed */
1078#define KPAD_COL 0xff00 /* Columns Pressed */
1079
1080/* Bit masks for KPAD_STAT */
1081
1082#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
1083#define nKPAD_IRQ 0x0
1084#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
1085#define KPAD_PRESSED 0x8 /* Key press current status */
1086#define nKPAD_PRESSED 0x0
1087
1088/* Bit masks for KPAD_SOFTEVAL */
1089
1090#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
1091#define nKPAD_SOFTEVAL_E 0x0
1092
1093/* Bit masks for SDH_COMMAND */
1094
1095#define CMD_IDX 0x3f /* Command Index */
1096#define CMD_RSP 0x40 /* Response */
1097#define nCMD_RSP 0x0
1098#define CMD_L_RSP 0x80 /* Long Response */
1099#define nCMD_L_RSP 0x0
1100#define CMD_INT_E 0x100 /* Command Interrupt */
1101#define nCMD_INT_E 0x0
1102#define CMD_PEND_E 0x200 /* Command Pending */
1103#define nCMD_PEND_E 0x0
1104#define CMD_E 0x400 /* Command Enable */
1105#define nCMD_E 0x0
1106
1107/* Bit masks for SDH_PWR_CTL */
1108
1109#define PWR_ON 0x3 /* Power On */
1110#if 0
1111#define TBD 0x3c /* TBD */
1112#endif
1113#define SD_CMD_OD 0x40 /* Open Drain Output */
1114#define nSD_CMD_OD 0x0
1115#define ROD_CTL 0x80 /* Rod Control */
1116#define nROD_CTL 0x0
1117
1118/* Bit masks for SDH_CLK_CTL */
1119
1120#define CLKDIV 0xff /* MC_CLK Divisor */
1121#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
1122#define nCLK_E 0x0
1123#define PWR_SV_E 0x200 /* Power Save Enable */
1124#define nPWR_SV_E 0x0
1125#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
1126#define nCLKDIV_BYPASS 0x0
1127#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
1128#define nWIDE_BUS 0x0
1129
1130/* Bit masks for SDH_RESP_CMD */
1131
1132#define RESP_CMD 0x3f /* Response Command */
1133
1134/* Bit masks for SDH_DATA_CTL */
1135
1136#define DTX_E 0x1 /* Data Transfer Enable */
1137#define nDTX_E 0x0
1138#define DTX_DIR 0x2 /* Data Transfer Direction */
1139#define nDTX_DIR 0x0
1140#define DTX_MODE 0x4 /* Data Transfer Mode */
1141#define nDTX_MODE 0x0
1142#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
1143#define nDTX_DMA_E 0x0
1144#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
1145
1146/* Bit masks for SDH_STATUS */
1147
1148#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
1149#define nCMD_CRC_FAIL 0x0
1150#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
1151#define nDAT_CRC_FAIL 0x0
1152#define CMD_TIMEOUT 0x4 /* CMD Time Out */
1153#define nCMD_TIMEOUT 0x0
1154#define DAT_TIMEOUT 0x8 /* Data Time Out */
1155#define nDAT_TIMEOUT 0x0
1156#define TX_UNDERRUN 0x10 /* Transmit Underrun */
1157#define nTX_UNDERRUN 0x0
1158#define RX_OVERRUN 0x20 /* Receive Overrun */
1159#define nRX_OVERRUN 0x0
1160#define CMD_RESP_END 0x40 /* CMD Response End */
1161#define nCMD_RESP_END 0x0
1162#define CMD_SENT 0x80 /* CMD Sent */
1163#define nCMD_SENT 0x0
1164#define DAT_END 0x100 /* Data End */
1165#define nDAT_END 0x0
1166#define START_BIT_ERR 0x200 /* Start Bit Error */
1167#define nSTART_BIT_ERR 0x0
1168#define DAT_BLK_END 0x400 /* Data Block End */
1169#define nDAT_BLK_END 0x0
1170#define CMD_ACT 0x800 /* CMD Active */
1171#define nCMD_ACT 0x0
1172#define TX_ACT 0x1000 /* Transmit Active */
1173#define nTX_ACT 0x0
1174#define RX_ACT 0x2000 /* Receive Active */
1175#define nRX_ACT 0x0
1176#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
1177#define nTX_FIFO_STAT 0x0
1178#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
1179#define nRX_FIFO_STAT 0x0
1180#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
1181#define nTX_FIFO_FULL 0x0
1182#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
1183#define nRX_FIFO_FULL 0x0
1184#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
1185#define nTX_FIFO_ZERO 0x0
1186#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
1187#define nRX_DAT_ZERO 0x0
1188#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
1189#define nTX_DAT_RDY 0x0
1190#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
1191#define nRX_FIFO_RDY 0x0
1192
1193/* Bit masks for SDH_STATUS_CLR */
1194
1195#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
1196#define nCMD_CRC_FAIL_STAT 0x0
1197#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
1198#define nDAT_CRC_FAIL_STAT 0x0
1199#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
1200#define nCMD_TIMEOUT_STAT 0x0
1201#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
1202#define nDAT_TIMEOUT_STAT 0x0
1203#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
1204#define nTX_UNDERRUN_STAT 0x0
1205#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
1206#define nRX_OVERRUN_STAT 0x0
1207#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
1208#define nCMD_RESP_END_STAT 0x0
1209#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
1210#define nCMD_SENT_STAT 0x0
1211#define DAT_END_STAT 0x100 /* Data End Status */
1212#define nDAT_END_STAT 0x0
1213#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
1214#define nSTART_BIT_ERR_STAT 0x0
1215#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
1216#define nDAT_BLK_END_STAT 0x0
1217
1218/* Bit masks for SDH_MASK0 */
1219
1220#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
1221#define nCMD_CRC_FAIL_MASK 0x0
1222#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
1223#define nDAT_CRC_FAIL_MASK 0x0
1224#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
1225#define nCMD_TIMEOUT_MASK 0x0
1226#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
1227#define nDAT_TIMEOUT_MASK 0x0
1228#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
1229#define nTX_UNDERRUN_MASK 0x0
1230#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
1231#define nRX_OVERRUN_MASK 0x0
1232#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
1233#define nCMD_RESP_END_MASK 0x0
1234#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
1235#define nCMD_SENT_MASK 0x0
1236#define DAT_END_MASK 0x100 /* Data End Mask */
1237#define nDAT_END_MASK 0x0
1238#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
1239#define nSTART_BIT_ERR_MASK 0x0
1240#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
1241#define nDAT_BLK_END_MASK 0x0
1242#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
1243#define nCMD_ACT_MASK 0x0
1244#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
1245#define nTX_ACT_MASK 0x0
1246#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
1247#define nRX_ACT_MASK 0x0
1248#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
1249#define nTX_FIFO_STAT_MASK 0x0
1250#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
1251#define nRX_FIFO_STAT_MASK 0x0
1252#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
1253#define nTX_FIFO_FULL_MASK 0x0
1254#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
1255#define nRX_FIFO_FULL_MASK 0x0
1256#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
1257#define nTX_FIFO_ZERO_MASK 0x0
1258#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
1259#define nRX_DAT_ZERO_MASK 0x0
1260#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
1261#define nTX_DAT_RDY_MASK 0x0
1262#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
1263#define nRX_FIFO_RDY_MASK 0x0
1264
1265/* Bit masks for SDH_FIFO_CNT */
1266
1267#define FIFO_COUNT 0x7fff /* FIFO Count */
1268
1269/* Bit masks for SDH_E_STATUS */
1270
1271#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
1272#define nSDIO_INT_DET 0x0
1273#define SD_CARD_DET 0x10 /* SD Card Detect */
1274#define nSD_CARD_DET 0x0
1275
1276/* Bit masks for SDH_E_MASK */
1277
1278#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
1279#define nSDIO_MSK 0x0
1280#define SCD_MSK 0x40 /* Mask Card Detect */
1281#define nSCD_MSK 0x0
1282
1283/* Bit masks for SDH_CFG */
1284
1285#define CLKS_EN 0x1 /* Clocks Enable */
1286#define nCLKS_EN 0x0
1287#define SD4E 0x4 /* SDIO 4-Bit Enable */
1288#define nSD4E 0x0
1289#define MWE 0x8 /* Moving Window Enable */
1290#define nMWE 0x0
1291#define SD_RST 0x10 /* SDMMC Reset */
1292#define nSD_RST 0x0
1293#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
1294#define nPUP_SDDAT 0x0
1295#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
1296#define nPUP_SDDAT3 0x0
1297#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
1298#define nPD_SDDAT3 0x0
1299
1300/* Bit masks for SDH_RD_WAIT_EN */
1301
1302#define RWR 0x1 /* Read Wait Request */
1303#define nRWR 0x0
1304
1305/* Bit masks for ATAPI_CONTROL */
1306
1307#define PIO_START 0x1 /* Start PIO/Reg Op */
1308#define nPIO_START 0x0
1309#define MULTI_START 0x2 /* Start Multi-DMA Op */
1310#define nMULTI_START 0x0
1311#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
1312#define nULTRA_START 0x0
1313#define XFER_DIR 0x8 /* Transfer Direction */
1314#define nXFER_DIR 0x0
1315#define IORDY_EN 0x10 /* IORDY Enable */
1316#define nIORDY_EN 0x0
1317#define FIFO_FLUSH 0x20 /* Flush FIFOs */
1318#define nFIFO_FLUSH 0x0
1319#define SOFT_RST 0x40 /* Soft Reset */
1320#define nSOFT_RST 0x0
1321#define DEV_RST 0x80 /* Device Reset */
1322#define nDEV_RST 0x0
1323#define TFRCNT_RST 0x100 /* Trans Count Reset */
1324#define nTFRCNT_RST 0x0
1325#define END_ON_TERM 0x200 /* End/Terminate Select */
1326#define nEND_ON_TERM 0x0
1327#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
1328#define nPIO_USE_DMA 0x0
1329#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
1330
1331/* Bit masks for ATAPI_STATUS */
1332
1333#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
1334#define nPIO_XFER_ON 0x0
1335#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
1336#define nMULTI_XFER_ON 0x0
1337#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
1338#define nULTRA_XFER_ON 0x0
1339#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
1340
1341/* Bit masks for ATAPI_DEV_ADDR */
1342
1343#define DEV_ADDR 0x1f /* Device Address */
1344
1345/* Bit masks for ATAPI_INT_MASK */
1346
1347#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
1348#define nATAPI_DEV_INT_MASK 0x0
1349#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
1350#define nPIO_DONE_MASK 0x0
1351#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
1352#define nMULTI_DONE_MASK 0x0
1353#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
1354#define nUDMAIN_DONE_MASK 0x0
1355#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
1356#define nUDMAOUT_DONE_MASK 0x0
1357#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
1358#define nHOST_TERM_XFER_MASK 0x0
1359#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
1360#define nMULTI_TERM_MASK 0x0
1361#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
1362#define nUDMAIN_TERM_MASK 0x0
1363#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
1364#define nUDMAOUT_TERM_MASK 0x0
1365
1366/* Bit masks for ATAPI_INT_STATUS */
1367
1368#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
1369#define nATAPI_DEV_INT 0x0
1370#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
1371#define nPIO_DONE_INT 0x0
1372#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
1373#define nMULTI_DONE_INT 0x0
1374#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
1375#define nUDMAIN_DONE_INT 0x0
1376#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
1377#define nUDMAOUT_DONE_INT 0x0
1378#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
1379#define nHOST_TERM_XFER_INT 0x0
1380#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
1381#define nMULTI_TERM_INT 0x0
1382#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
1383#define nUDMAIN_TERM_INT 0x0
1384#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
1385#define nUDMAOUT_TERM_INT 0x0
1386
1387/* Bit masks for ATAPI_LINE_STATUS */
1388
1389#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
1390#define nATAPI_INTR 0x0
1391#define ATAPI_DASP 0x2 /* Device dasp to host line status */
1392#define nATAPI_DASP 0x0
1393#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
1394#define nATAPI_CS0N 0x0
1395#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
1396#define nATAPI_CS1N 0x0
1397#define ATAPI_ADDR 0x70 /* ATAPI address line status */
1398#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
1399#define nATAPI_DMAREQ 0x0
1400#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
1401#define nATAPI_DMAACKN 0x0
1402#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
1403#define nATAPI_DIOWN 0x0
1404#define ATAPI_DIORN 0x400 /* ATAPI read line status */
1405#define nATAPI_DIORN 0x0
1406#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
1407#define nATAPI_IORDY 0x0
1408
1409/* Bit masks for ATAPI_SM_STATE */
1410
1411#define PIO_CSTATE 0xf /* PIO mode state machine current state */
1412#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
1413#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
1414#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
1415
1416/* Bit masks for ATAPI_TERMINATE */
1417
1418#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
1419#define nATAPI_HOST_TERM 0x0
1420
1421/* Bit masks for ATAPI_REG_TIM_0 */
1422
1423#define T2_REG 0xff /* End of cycle time for register access transfers */
1424#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
1425
1426/* Bit masks for ATAPI_PIO_TIM_0 */
1427
1428#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
1429#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
1430#define T4_REG 0xf000 /* DIOW data hold */
1431
1432/* Bit masks for ATAPI_PIO_TIM_1 */
1433
1434#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
1435
1436/* Bit masks for ATAPI_MULTI_TIM_0 */
1437
1438#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
1439#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
1440
1441/* Bit masks for ATAPI_MULTI_TIM_1 */
1442
1443#define TKW 0xff /* Selects DIOW negated pulsewidth */
1444#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
1445
1446/* Bit masks for ATAPI_MULTI_TIM_2 */
1447
1448#define TH 0xff /* Selects DIOW data hold */
1449#define TEOC 0xff00 /* Selects end of cycle for DMA */
1450
1451/* Bit masks for ATAPI_ULTRA_TIM_0 */
1452
1453#define TACK 0xff /* Selects setup and hold times for TACK */
1454#define TENV 0xff00 /* Selects envelope time */
1455
1456/* Bit masks for ATAPI_ULTRA_TIM_1 */
1457
1458#define TDVS 0xff /* Selects data valid setup time */
1459#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
1460
1461/* Bit masks for ATAPI_ULTRA_TIM_2 */
1462
1463#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
1464#define TMLI 0xff00 /* Selects interlock time */
1465
1466/* Bit masks for ATAPI_ULTRA_TIM_3 */
1467
1468#define TZAH 0xff /* Selects minimum delay required for output */
1469#define READY_PAUSE 0xff00 /* Selects ready to pause */
1470
1471/* Bit masks for TIMER_ENABLE1 */
1472
1473#define TIMEN8 0x1 /* Timer 8 Enable */
1474#define nTIMEN8 0x0
1475#define TIMEN9 0x2 /* Timer 9 Enable */
1476#define nTIMEN9 0x0
1477#define TIMEN10 0x4 /* Timer 10 Enable */
1478#define nTIMEN10 0x0
1479
1480/* Bit masks for TIMER_DISABLE1 */
1481
1482#define TIMDIS8 0x1 /* Timer 8 Disable */
1483#define nTIMDIS8 0x0
1484#define TIMDIS9 0x2 /* Timer 9 Disable */
1485#define nTIMDIS9 0x0
1486#define TIMDIS10 0x4 /* Timer 10 Disable */
1487#define nTIMDIS10 0x0
1488
1489/* Bit masks for TIMER_STATUS1 */
1490
1491#define TIMIL8 0x1 /* Timer 8 Interrupt */
1492#define nTIMIL8 0x0
1493#define TIMIL9 0x2 /* Timer 9 Interrupt */
1494#define nTIMIL9 0x0
1495#define TIMIL10 0x4 /* Timer 10 Interrupt */
1496#define nTIMIL10 0x0
1497#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
1498#define nTOVF_ERR8 0x0
1499#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
1500#define nTOVF_ERR9 0x0
1501#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
1502#define nTOVF_ERR10 0x0
1503#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
1504#define nTRUN8 0x0
1505#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
1506#define nTRUN9 0x0
1507#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
1508#define nTRUN10 0x0
1509
1510/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
1511
1512/* Bit masks for USB_FADDR */
1513
1514#define FUNCTION_ADDRESS 0x7f /* Function address */
1515
1516/* Bit masks for USB_POWER */
1517
1518#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
1519#define nENABLE_SUSPENDM 0x0
1520#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
1521#define nSUSPEND_MODE 0x0
1522#define RESUME_MODE 0x4 /* DMA Mode */
1523#define nRESUME_MODE 0x0
1524#define RESET 0x8 /* Reset indicator */
1525#define nRESET 0x0
1526#define HS_MODE 0x10 /* High Speed mode indicator */
1527#define nHS_MODE 0x0
1528#define HS_ENABLE 0x20 /* high Speed Enable */
1529#define nHS_ENABLE 0x0
1530#define SOFT_CONN 0x40 /* Soft connect */
1531#define nSOFT_CONN 0x0
1532#define ISO_UPDATE 0x80 /* Isochronous update */
1533#define nISO_UPDATE 0x0
1534
1535/* Bit masks for USB_INTRTX */
1536
1537#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
1538#define nEP0_TX 0x0
1539#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
1540#define nEP1_TX 0x0
1541#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
1542#define nEP2_TX 0x0
1543#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
1544#define nEP3_TX 0x0
1545#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
1546#define nEP4_TX 0x0
1547#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
1548#define nEP5_TX 0x0
1549#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
1550#define nEP6_TX 0x0
1551#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
1552#define nEP7_TX 0x0
1553
1554/* Bit masks for USB_INTRRX */
1555
1556#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
1557#define nEP1_RX 0x0
1558#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
1559#define nEP2_RX 0x0
1560#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
1561#define nEP3_RX 0x0
1562#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
1563#define nEP4_RX 0x0
1564#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
1565#define nEP5_RX 0x0
1566#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
1567#define nEP6_RX 0x0
1568#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
1569#define nEP7_RX 0x0
1570
1571/* Bit masks for USB_INTRTXE */
1572
1573#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
1574#define nEP0_TX_E 0x0
1575#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
1576#define nEP1_TX_E 0x0
1577#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
1578#define nEP2_TX_E 0x0
1579#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
1580#define nEP3_TX_E 0x0
1581#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
1582#define nEP4_TX_E 0x0
1583#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
1584#define nEP5_TX_E 0x0
1585#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
1586#define nEP6_TX_E 0x0
1587#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
1588#define nEP7_TX_E 0x0
1589
1590/* Bit masks for USB_INTRRXE */
1591
1592#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
1593#define nEP1_RX_E 0x0
1594#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
1595#define nEP2_RX_E 0x0
1596#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
1597#define nEP3_RX_E 0x0
1598#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
1599#define nEP4_RX_E 0x0
1600#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
1601#define nEP5_RX_E 0x0
1602#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
1603#define nEP6_RX_E 0x0
1604#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
1605#define nEP7_RX_E 0x0
1606
1607/* Bit masks for USB_INTRUSB */
1608
1609#define SUSPEND_B 0x1 /* Suspend indicator */
1610#define nSUSPEND_B 0x0
1611#define RESUME_B 0x2 /* Resume indicator */
1612#define nRESUME_B 0x0
1613#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
1614#define nRESET_OR_BABLE_B 0x0
1615#define SOF_B 0x8 /* Start of frame */
1616#define nSOF_B 0x0
1617#define CONN_B 0x10 /* Connection indicator */
1618#define nCONN_B 0x0
1619#define DISCON_B 0x20 /* Disconnect indicator */
1620#define nDISCON_B 0x0
1621#define SESSION_REQ_B 0x40 /* Session Request */
1622#define nSESSION_REQ_B 0x0
1623#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
1624#define nVBUS_ERROR_B 0x0
1625
1626/* Bit masks for USB_INTRUSBE */
1627
1628#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
1629#define nSUSPEND_BE 0x0
1630#define RESUME_BE 0x2 /* Resume indicator int enable */
1631#define nRESUME_BE 0x0
1632#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
1633#define nRESET_OR_BABLE_BE 0x0
1634#define SOF_BE 0x8 /* Start of frame int enable */
1635#define nSOF_BE 0x0
1636#define CONN_BE 0x10 /* Connection indicator int enable */
1637#define nCONN_BE 0x0
1638#define DISCON_BE 0x20 /* Disconnect indicator int enable */
1639#define nDISCON_BE 0x0
1640#define SESSION_REQ_BE 0x40 /* Session Request int enable */
1641#define nSESSION_REQ_BE 0x0
1642#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
1643#define nVBUS_ERROR_BE 0x0
1644
1645/* Bit masks for USB_FRAME */
1646
1647#define FRAME_NUMBER 0x7ff /* Frame number */
1648
1649/* Bit masks for USB_INDEX */
1650
1651#define SELECTED_ENDPOINT 0xf /* selected endpoint */
1652
1653/* Bit masks for USB_GLOBAL_CTL */
1654
1655#define GLOBAL_ENA 0x1 /* enables USB module */
1656#define nGLOBAL_ENA 0x0
1657#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
1658#define nEP1_TX_ENA 0x0
1659#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
1660#define nEP2_TX_ENA 0x0
1661#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
1662#define nEP3_TX_ENA 0x0
1663#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
1664#define nEP4_TX_ENA 0x0
1665#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
1666#define nEP5_TX_ENA 0x0
1667#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
1668#define nEP6_TX_ENA 0x0
1669#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
1670#define nEP7_TX_ENA 0x0
1671#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
1672#define nEP1_RX_ENA 0x0
1673#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
1674#define nEP2_RX_ENA 0x0
1675#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
1676#define nEP3_RX_ENA 0x0
1677#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
1678#define nEP4_RX_ENA 0x0
1679#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
1680#define nEP5_RX_ENA 0x0
1681#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
1682#define nEP6_RX_ENA 0x0
1683#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
1684#define nEP7_RX_ENA 0x0
1685
1686/* Bit masks for USB_OTG_DEV_CTL */
1687
1688#define SESSION 0x1 /* session indicator */
1689#define nSESSION 0x0
1690#define HOST_REQ 0x2 /* Host negotiation request */
1691#define nHOST_REQ 0x0
1692#define HOST_MODE 0x4 /* indicates USBDRC is a host */
1693#define nHOST_MODE 0x0
1694#define VBUS0 0x8 /* Vbus level indicator[0] */
1695#define nVBUS0 0x0
1696#define VBUS1 0x10 /* Vbus level indicator[1] */
1697#define nVBUS1 0x0
1698#define LSDEV 0x20 /* Low-speed indicator */
1699#define nLSDEV 0x0
1700#define FSDEV 0x40 /* Full or High-speed indicator */
1701#define nFSDEV 0x0
1702#define B_DEVICE 0x80 /* A' or 'B' device indicator */
1703#define nB_DEVICE 0x0
1704
1705/* Bit masks for USB_OTG_VBUS_IRQ */
1706
1707#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
1708#define nDRIVE_VBUS_ON 0x0
1709#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
1710#define nDRIVE_VBUS_OFF 0x0
1711#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
1712#define nCHRG_VBUS_START 0x0
1713#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
1714#define nCHRG_VBUS_END 0x0
1715#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
1716#define nDISCHRG_VBUS_START 0x0
1717#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
1718#define nDISCHRG_VBUS_END 0x0
1719
1720/* Bit masks for USB_OTG_VBUS_MASK */
1721
1722#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
1723#define nDRIVE_VBUS_ON_ENA 0x0
1724#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
1725#define nDRIVE_VBUS_OFF_ENA 0x0
1726#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
1727#define nCHRG_VBUS_START_ENA 0x0
1728#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
1729#define nCHRG_VBUS_END_ENA 0x0
1730#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
1731#define nDISCHRG_VBUS_START_ENA 0x0
1732#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
1733#define nDISCHRG_VBUS_END_ENA 0x0
1734
1735/* Bit masks for USB_CSR0 */
1736
1737#define RXPKTRDY 0x1 /* data packet receive indicator */
1738#define nRXPKTRDY 0x0
1739#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
1740#define nTXPKTRDY 0x0
1741#define STALL_SENT 0x4 /* STALL handshake sent */
1742#define nSTALL_SENT 0x0
1743#define DATAEND 0x8 /* Data end indicator */
1744#define nDATAEND 0x0
1745#define SETUPEND 0x10 /* Setup end */
1746#define nSETUPEND 0x0
1747#define SENDSTALL 0x20 /* Send STALL handshake */
1748#define nSENDSTALL 0x0
1749#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
1750#define nSERVICED_RXPKTRDY 0x0
1751#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
1752#define nSERVICED_SETUPEND 0x0
1753#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
1754#define nFLUSHFIFO 0x0
1755#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
1756#define nSTALL_RECEIVED_H 0x0
1757#define SETUPPKT_H 0x8 /* send Setup token host mode */
1758#define nSETUPPKT_H 0x0
1759#define ERROR_H 0x10 /* timeout error indicator host mode */
1760#define nERROR_H 0x0
1761#define REQPKT_H 0x20 /* Request an IN transaction host mode */
1762#define nREQPKT_H 0x0
1763#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
1764#define nSTATUSPKT_H 0x0
1765#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
1766#define nNAK_TIMEOUT_H 0x0
1767
1768/* Bit masks for USB_COUNT0 */
1769
1770#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
1771
1772/* Bit masks for USB_NAKLIMIT0 */
1773
1774#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
1775
1776/* Bit masks for USB_TX_MAX_PACKET */
1777
1778#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
1779
1780/* Bit masks for USB_RX_MAX_PACKET */
1781
1782#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
1783
1784/* Bit masks for USB_TXCSR */
1785
1786#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
1787#define nTXPKTRDY_T 0x0
1788#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
1789#define nFIFO_NOT_EMPTY_T 0x0
1790#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
1791#define nUNDERRUN_T 0x0
1792#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
1793#define nFLUSHFIFO_T 0x0
1794#define STALL_SEND_T 0x10 /* issue a Stall handshake */
1795#define nSTALL_SEND_T 0x0
1796#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
1797#define nSTALL_SENT_T 0x0
1798#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
1799#define nCLEAR_DATATOGGLE_T 0x0
1800#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
1801#define nINCOMPTX_T 0x0
1802#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
1803#define nDMAREQMODE_T 0x0
1804#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
1805#define nFORCE_DATATOGGLE_T 0x0
1806#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
1807#define nDMAREQ_ENA_T 0x0
1808#define ISO_T 0x4000 /* enable Isochronous transfers */
1809#define nISO_T 0x0
1810#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
1811#define nAUTOSET_T 0x0
1812#define ERROR_TH 0x4 /* error condition host mode */
1813#define nERROR_TH 0x0
1814#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
1815#define nSTALL_RECEIVED_TH 0x0
1816#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
1817#define nNAK_TIMEOUT_TH 0x0
1818
1819/* Bit masks for USB_TXCOUNT */
1820
1821#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
1822
1823/* Bit masks for USB_RXCSR */
1824
1825#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
1826#define nRXPKTRDY_R 0x0
1827#define FIFO_FULL_R 0x2 /* FIFO not empty */
1828#define nFIFO_FULL_R 0x0
1829#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
1830#define nOVERRUN_R 0x0
1831#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
1832#define nDATAERROR_R 0x0
1833#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
1834#define nFLUSHFIFO_R 0x0
1835#define STALL_SEND_R 0x20 /* issue a Stall handshake */
1836#define nSTALL_SEND_R 0x0
1837#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
1838#define nSTALL_SENT_R 0x0
1839#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
1840#define nCLEAR_DATATOGGLE_R 0x0
1841#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
1842#define nINCOMPRX_R 0x0
1843#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
1844#define nDMAREQMODE_R 0x0
1845#define DISNYET_R 0x1000 /* disable Nyet handshakes */
1846#define nDISNYET_R 0x0
1847#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
1848#define nDMAREQ_ENA_R 0x0
1849#define ISO_R 0x4000 /* enable Isochronous transfers */
1850#define nISO_R 0x0
1851#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
1852#define nAUTOCLEAR_R 0x0
1853#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
1854#define nERROR_RH 0x0
1855#define REQPKT_RH 0x20 /* request an IN transaction host mode */
1856#define nREQPKT_RH 0x0
1857#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
1858#define nSTALL_RECEIVED_RH 0x0
1859#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
1860#define nINCOMPRX_RH 0x0
1861#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
1862#define nDMAREQMODE_RH 0x0
1863#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
1864#define nAUTOREQ_RH 0x0
1865
1866/* Bit masks for USB_RXCOUNT */
1867
1868#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
1869
1870/* Bit masks for USB_TXTYPE */
1871
1872#define TARGET_EP_NO_T 0xf /* EP number */
1873#define PROTOCOL_T 0xc /* transfer type */
1874
1875/* Bit masks for USB_TXINTERVAL */
1876
1877#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
1878
1879/* Bit masks for USB_RXTYPE */
1880
1881#define TARGET_EP_NO_R 0xf /* EP number */
1882#define PROTOCOL_R 0xc /* transfer type */
1883
1884/* Bit masks for USB_RXINTERVAL */
1885
1886#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
1887
1888/* Bit masks for USB_DMA_INTERRUPT */
1889
1890#define DMA0_INT 0x1 /* DMA0 pending interrupt */
1891#define nDMA0_INT 0x0
1892#define DMA1_INT 0x2 /* DMA1 pending interrupt */
1893#define nDMA1_INT 0x0
1894#define DMA2_INT 0x4 /* DMA2 pending interrupt */
1895#define nDMA2_INT 0x0
1896#define DMA3_INT 0x8 /* DMA3 pending interrupt */
1897#define nDMA3_INT 0x0
1898#define DMA4_INT 0x10 /* DMA4 pending interrupt */
1899#define nDMA4_INT 0x0
1900#define DMA5_INT 0x20 /* DMA5 pending interrupt */
1901#define nDMA5_INT 0x0
1902#define DMA6_INT 0x40 /* DMA6 pending interrupt */
1903#define nDMA6_INT 0x0
1904#define DMA7_INT 0x80 /* DMA7 pending interrupt */
1905#define nDMA7_INT 0x0
1906
1907/* Bit masks for USB_DMAxCONTROL */
1908
1909#define DMA_ENA 0x1 /* DMA enable */
1910#define nDMA_ENA 0x0
1911#define DIRECTION 0x2 /* direction of DMA transfer */
1912#define nDIRECTION 0x0
1913#define MODE 0x4 /* DMA Bus error */
1914#define nMODE 0x0
1915#define INT_ENA 0x8 /* Interrupt enable */
1916#define nINT_ENA 0x0
1917#define EPNUM 0xf0 /* EP number */
1918#define BUSERROR 0x100 /* DMA Bus error */
1919#define nBUSERROR 0x0
1920
1921/* Bit masks for USB_DMAxADDRHIGH */
1922
1923#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
1924
1925/* Bit masks for USB_DMAxADDRLOW */
1926
1927#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
1928
1929/* Bit masks for USB_DMAxCOUNTHIGH */
1930
1931#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
1932
1933/* Bit masks for USB_DMAxCOUNTLOW */
1934
1935#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
1936
1937/* Bit masks for HMDMAx_CONTROL */
1938
1939#define HMDMAEN 0x1 /* Handshake MDMA Enable */
1940#define nHMDMAEN 0x0
1941#define REP 0x2 /* Handshake MDMA Request Polarity */
1942#define nREP 0x0
1943#define UTE 0x8 /* Urgency Threshold Enable */
1944#define nUTE 0x0
1945#define OIE 0x10 /* Overflow Interrupt Enable */
1946#define nOIE 0x0
1947#define BDIE 0x20 /* Block Done Interrupt Enable */
1948#define nBDIE 0x0
1949#define MBDI 0x40 /* Mask Block Done Interrupt */
1950#define nMBDI 0x0
1951#define DRQ 0x300 /* Handshake MDMA Request Type */
1952#define RBC 0x1000 /* Force Reload of BCOUNT */
1953#define nRBC 0x0
1954#define PS 0x2000 /* Pin Status */
1955#define nPS 0x0
1956#define OI 0x4000 /* Overflow Interrupt Generated */
1957#define nOI 0x0
1958#define BDI 0x8000 /* Block Done Interrupt Generated */
1959#define nBDI 0x0
1960
1961/* ******************************************* */
1962/* MULTI BIT MACRO ENUMERATIONS */
1963/* ******************************************* */
1964
1965
1966#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
new file mode 100644
index 000000000000..b1cc1c073b41
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF549.h
@@ -0,0 +1,3472 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF549.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF549_H
32#define _DEF_BF549_H
33
34/* Include all Core registers and bit definitions */
35#include <asm/mach-common/def_LPBlackfin.h>
36
37
38/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
39
40/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
41#include "defBF54x_base.h"
42
43/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
44
45/* Timer Registers */
46
47#define TIMER8_CONFIG 0xffc00600 /* Timer 8 Configuration Register */
48#define TIMER8_COUNTER 0xffc00604 /* Timer 8 Counter Register */
49#define TIMER8_PERIOD 0xffc00608 /* Timer 8 Period Register */
50#define TIMER8_WIDTH 0xffc0060c /* Timer 8 Width Register */
51#define TIMER9_CONFIG 0xffc00610 /* Timer 9 Configuration Register */
52#define TIMER9_COUNTER 0xffc00614 /* Timer 9 Counter Register */
53#define TIMER9_PERIOD 0xffc00618 /* Timer 9 Period Register */
54#define TIMER9_WIDTH 0xffc0061c /* Timer 9 Width Register */
55#define TIMER10_CONFIG 0xffc00620 /* Timer 10 Configuration Register */
56#define TIMER10_COUNTER 0xffc00624 /* Timer 10 Counter Register */
57#define TIMER10_PERIOD 0xffc00628 /* Timer 10 Period Register */
58#define TIMER10_WIDTH 0xffc0062c /* Timer 10 Width Register */
59
60/* Timer Group of 3 Registers */
61
62#define TIMER_ENABLE1 0xffc00640 /* Timer Group of 3 Enable Register */
63#define TIMER_DISABLE1 0xffc00644 /* Timer Group of 3 Disable Register */
64#define TIMER_STATUS1 0xffc00648 /* Timer Group of 3 Status Register */
65
66/* SPORT0 Registers */
67
68#define SPORT0_TCR1 0xffc00800 /* SPORT0 Transmit Configuration 1 Register */
69#define SPORT0_TCR2 0xffc00804 /* SPORT0 Transmit Configuration 2 Register */
70#define SPORT0_TCLKDIV 0xffc00808 /* SPORT0 Transmit Serial Clock Divider Register */
71#define SPORT0_TFSDIV 0xffc0080c /* SPORT0 Transmit Frame Sync Divider Register */
72#define SPORT0_TX 0xffc00810 /* SPORT0 Transmit Data Register */
73#define SPORT0_RX 0xffc00818 /* SPORT0 Receive Data Register */
74#define SPORT0_RCR1 0xffc00820 /* SPORT0 Receive Configuration 1 Register */
75#define SPORT0_RCR2 0xffc00824 /* SPORT0 Receive Configuration 2 Register */
76#define SPORT0_RCLKDIV 0xffc00828 /* SPORT0 Receive Serial Clock Divider Register */
77#define SPORT0_RFSDIV 0xffc0082c /* SPORT0 Receive Frame Sync Divider Register */
78#define SPORT0_STAT 0xffc00830 /* SPORT0 Status Register */
79#define SPORT0_CHNL 0xffc00834 /* SPORT0 Current Channel Register */
80#define SPORT0_MCMC1 0xffc00838 /* SPORT0 Multi channel Configuration Register 1 */
81#define SPORT0_MCMC2 0xffc0083c /* SPORT0 Multi channel Configuration Register 2 */
82#define SPORT0_MTCS0 0xffc00840 /* SPORT0 Multi channel Transmit Select Register 0 */
83#define SPORT0_MTCS1 0xffc00844 /* SPORT0 Multi channel Transmit Select Register 1 */
84#define SPORT0_MTCS2 0xffc00848 /* SPORT0 Multi channel Transmit Select Register 2 */
85#define SPORT0_MTCS3 0xffc0084c /* SPORT0 Multi channel Transmit Select Register 3 */
86#define SPORT0_MRCS0 0xffc00850 /* SPORT0 Multi channel Receive Select Register 0 */
87#define SPORT0_MRCS1 0xffc00854 /* SPORT0 Multi channel Receive Select Register 1 */
88#define SPORT0_MRCS2 0xffc00858 /* SPORT0 Multi channel Receive Select Register 2 */
89#define SPORT0_MRCS3 0xffc0085c /* SPORT0 Multi channel Receive Select Register 3 */
90
91/* EPPI0 Registers */
92
93#define EPPI0_STATUS 0xffc01000 /* EPPI0 Status Register */
94#define EPPI0_HCOUNT 0xffc01004 /* EPPI0 Horizontal Transfer Count Register */
95#define EPPI0_HDELAY 0xffc01008 /* EPPI0 Horizontal Delay Count Register */
96#define EPPI0_VCOUNT 0xffc0100c /* EPPI0 Vertical Transfer Count Register */
97#define EPPI0_VDELAY 0xffc01010 /* EPPI0 Vertical Delay Count Register */
98#define EPPI0_FRAME 0xffc01014 /* EPPI0 Lines per Frame Register */
99#define EPPI0_LINE 0xffc01018 /* EPPI0 Samples per Line Register */
100#define EPPI0_CLKDIV 0xffc0101c /* EPPI0 Clock Divide Register */
101#define EPPI0_CONTROL 0xffc01020 /* EPPI0 Control Register */
102#define EPPI0_FS1W_HBL 0xffc01024 /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
103#define EPPI0_FS1P_AVPL 0xffc01028 /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
104#define EPPI0_FS2W_LVB 0xffc0102c /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
105#define EPPI0_FS2P_LAVF 0xffc01030 /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
106#define EPPI0_CLIP 0xffc01034 /* EPPI0 Clipping Register */
107
108/* UART2 Registers */
109
110#define UART2_DLL 0xffc02100 /* Divisor Latch Low Byte */
111#define UART2_DLH 0xffc02104 /* Divisor Latch High Byte */
112#define UART2_GCTL 0xffc02108 /* Global Control Register */
113#define UART2_LCR 0xffc0210c /* Line Control Register */
114#define UART2_MCR 0xffc02110 /* Modem Control Register */
115#define UART2_LSR 0xffc02114 /* Line Status Register */
116#define UART2_MSR 0xffc02118 /* Modem Status Register */
117#define UART2_SCR 0xffc0211c /* Scratch Register */
118#define UART2_IER_SET 0xffc02120 /* Interrupt Enable Register Set */
119#define UART2_IER_CLEAR 0xffc02124 /* Interrupt Enable Register Clear */
120#define UART2_RBR 0xffc0212c /* Receive Buffer Register */
121
122/* Two Wire Interface Registers (TWI1) */
123
124#define TWI1_CLKDIV 0xffc02200 /* Clock Divider Register */
125#define TWI1_CONTROL 0xffc02204 /* TWI Control Register */
126#define TWI1_SLAVE_CTRL 0xffc02208 /* TWI Slave Mode Control Register */
127#define TWI1_SLAVE_STAT 0xffc0220c /* TWI Slave Mode Status Register */
128#define TWI1_SLAVE_ADDR 0xffc02210 /* TWI Slave Mode Address Register */
129#define TWI1_MASTER_CTRL 0xffc02214 /* TWI Master Mode Control Register */
130#define TWI1_MASTER_STAT 0xffc02218 /* TWI Master Mode Status Register */
131#define TWI1_MASTER_ADDR 0xffc0221c /* TWI Master Mode Address Register */
132#define TWI1_INT_STAT 0xffc02220 /* TWI Interrupt Status Register */
133#define TWI1_INT_MASK 0xffc02224 /* TWI Interrupt Mask Register */
134#define TWI1_FIFO_CTRL 0xffc02228 /* TWI FIFO Control Register */
135#define TWI1_FIFO_STAT 0xffc0222c /* TWI FIFO Status Register */
136#define TWI1_XMT_DATA8 0xffc02280 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI1_XMT_DATA16 0xffc02284 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI1_RCV_DATA8 0xffc02288 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI1_RCV_DATA16 0xffc0228c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPI2 Registers */
142
143#define SPI2_CTL 0xffc02400 /* SPI2 Control Register */
144#define SPI2_FLG 0xffc02404 /* SPI2 Flag Register */
145#define SPI2_STAT 0xffc02408 /* SPI2 Status Register */
146#define SPI2_TDBR 0xffc0240c /* SPI2 Transmit Data Buffer Register */
147#define SPI2_RDBR 0xffc02410 /* SPI2 Receive Data Buffer Register */
148#define SPI2_BAUD 0xffc02414 /* SPI2 Baud Rate Register */
149#define SPI2_SHADOW 0xffc02418 /* SPI2 Receive Data Buffer Shadow Register */
150
151/* MXVR Registers */
152
153#define MXVR_CONFIG 0xffc02700 /* MXVR Configuration Register */
154#define MXVR_STATE_0 0xffc02708 /* MXVR State Register 0 */
155#define MXVR_STATE_1 0xffc0270c /* MXVR State Register 1 */
156#define MXVR_INT_STAT_0 0xffc02710 /* MXVR Interrupt Status Register 0 */
157#define MXVR_INT_STAT_1 0xffc02714 /* MXVR Interrupt Status Register 1 */
158#define MXVR_INT_EN_0 0xffc02718 /* MXVR Interrupt Enable Register 0 */
159#define MXVR_INT_EN_1 0xffc0271c /* MXVR Interrupt Enable Register 1 */
160#define MXVR_POSITION 0xffc02720 /* MXVR Node Position Register */
161#define MXVR_MAX_POSITION 0xffc02724 /* MXVR Maximum Node Position Register */
162#define MXVR_DELAY 0xffc02728 /* MXVR Node Frame Delay Register */
163#define MXVR_MAX_DELAY 0xffc0272c /* MXVR Maximum Node Frame Delay Register */
164#define MXVR_LADDR 0xffc02730 /* MXVR Logical Address Register */
165#define MXVR_GADDR 0xffc02734 /* MXVR Group Address Register */
166#define MXVR_AADDR 0xffc02738 /* MXVR Alternate Address Register */
167
168/* MXVR Allocation Table Registers */
169
170#define MXVR_ALLOC_0 0xffc0273c /* MXVR Allocation Table Register 0 */
171#define MXVR_ALLOC_1 0xffc02740 /* MXVR Allocation Table Register 1 */
172#define MXVR_ALLOC_2 0xffc02744 /* MXVR Allocation Table Register 2 */
173#define MXVR_ALLOC_3 0xffc02748 /* MXVR Allocation Table Register 3 */
174#define MXVR_ALLOC_4 0xffc0274c /* MXVR Allocation Table Register 4 */
175#define MXVR_ALLOC_5 0xffc02750 /* MXVR Allocation Table Register 5 */
176#define MXVR_ALLOC_6 0xffc02754 /* MXVR Allocation Table Register 6 */
177#define MXVR_ALLOC_7 0xffc02758 /* MXVR Allocation Table Register 7 */
178#define MXVR_ALLOC_8 0xffc0275c /* MXVR Allocation Table Register 8 */
179#define MXVR_ALLOC_9 0xffc02760 /* MXVR Allocation Table Register 9 */
180#define MXVR_ALLOC_10 0xffc02764 /* MXVR Allocation Table Register 10 */
181#define MXVR_ALLOC_11 0xffc02768 /* MXVR Allocation Table Register 11 */
182#define MXVR_ALLOC_12 0xffc0276c /* MXVR Allocation Table Register 12 */
183#define MXVR_ALLOC_13 0xffc02770 /* MXVR Allocation Table Register 13 */
184#define MXVR_ALLOC_14 0xffc02774 /* MXVR Allocation Table Register 14 */
185
186/* MXVR Channel Assign Registers */
187
188#define MXVR_SYNC_LCHAN_0 0xffc02778 /* MXVR Sync Data Logical Channel Assign Register 0 */
189#define MXVR_SYNC_LCHAN_1 0xffc0277c /* MXVR Sync Data Logical Channel Assign Register 1 */
190#define MXVR_SYNC_LCHAN_2 0xffc02780 /* MXVR Sync Data Logical Channel Assign Register 2 */
191#define MXVR_SYNC_LCHAN_3 0xffc02784 /* MXVR Sync Data Logical Channel Assign Register 3 */
192#define MXVR_SYNC_LCHAN_4 0xffc02788 /* MXVR Sync Data Logical Channel Assign Register 4 */
193#define MXVR_SYNC_LCHAN_5 0xffc0278c /* MXVR Sync Data Logical Channel Assign Register 5 */
194#define MXVR_SYNC_LCHAN_6 0xffc02790 /* MXVR Sync Data Logical Channel Assign Register 6 */
195#define MXVR_SYNC_LCHAN_7 0xffc02794 /* MXVR Sync Data Logical Channel Assign Register 7 */
196
197/* MXVR DMA0 Registers */
198
199#define MXVR_DMA0_CONFIG 0xffc02798 /* MXVR Sync Data DMA0 Config Register */
200#define MXVR_DMA0_START_ADDR 0xffc0279c /* MXVR Sync Data DMA0 Start Address */
201#define MXVR_DMA0_COUNT 0xffc027a0 /* MXVR Sync Data DMA0 Loop Count Register */
202#define MXVR_DMA0_CURR_ADDR 0xffc027a4 /* MXVR Sync Data DMA0 Current Address */
203#define MXVR_DMA0_CURR_COUNT 0xffc027a8 /* MXVR Sync Data DMA0 Current Loop Count */
204
205/* MXVR DMA1 Registers */
206
207#define MXVR_DMA1_CONFIG 0xffc027ac /* MXVR Sync Data DMA1 Config Register */
208#define MXVR_DMA1_START_ADDR 0xffc027b0 /* MXVR Sync Data DMA1 Start Address */
209#define MXVR_DMA1_COUNT 0xffc027b4 /* MXVR Sync Data DMA1 Loop Count Register */
210#define MXVR_DMA1_CURR_ADDR 0xffc027b8 /* MXVR Sync Data DMA1 Current Address */
211#define MXVR_DMA1_CURR_COUNT 0xffc027bc /* MXVR Sync Data DMA1 Current Loop Count */
212
213/* MXVR DMA2 Registers */
214
215#define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */
216#define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */
217#define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */
218#define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */
219#define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
220
221/* MXVR DMA3 Registers */
222
223#define MXVR_DMA3_CONFIG 0xffc027d4 /* MXVR Sync Data DMA3 Config Register */
224#define MXVR_DMA3_START_ADDR 0xffc027d8 /* MXVR Sync Data DMA3 Start Address */
225#define MXVR_DMA3_COUNT 0xffc027dc /* MXVR Sync Data DMA3 Loop Count Register */
226#define MXVR_DMA3_CURR_ADDR 0xffc027e0 /* MXVR Sync Data DMA3 Current Address */
227#define MXVR_DMA3_CURR_COUNT 0xffc027e4 /* MXVR Sync Data DMA3 Current Loop Count */
228
229/* MXVR DMA4 Registers */
230
231#define MXVR_DMA4_CONFIG 0xffc027e8 /* MXVR Sync Data DMA4 Config Register */
232#define MXVR_DMA4_START_ADDR 0xffc027ec /* MXVR Sync Data DMA4 Start Address */
233#define MXVR_DMA4_COUNT 0xffc027f0 /* MXVR Sync Data DMA4 Loop Count Register */
234#define MXVR_DMA4_CURR_ADDR 0xffc027f4 /* MXVR Sync Data DMA4 Current Address */
235#define MXVR_DMA4_CURR_COUNT 0xffc027f8 /* MXVR Sync Data DMA4 Current Loop Count */
236
237/* MXVR DMA5 Registers */
238
239#define MXVR_DMA5_CONFIG 0xffc027fc /* MXVR Sync Data DMA5 Config Register */
240#define MXVR_DMA5_START_ADDR 0xffc02800 /* MXVR Sync Data DMA5 Start Address */
241#define MXVR_DMA5_COUNT 0xffc02804 /* MXVR Sync Data DMA5 Loop Count Register */
242#define MXVR_DMA5_CURR_ADDR 0xffc02808 /* MXVR Sync Data DMA5 Current Address */
243#define MXVR_DMA5_CURR_COUNT 0xffc0280c /* MXVR Sync Data DMA5 Current Loop Count */
244
245/* MXVR DMA6 Registers */
246
247#define MXVR_DMA6_CONFIG 0xffc02810 /* MXVR Sync Data DMA6 Config Register */
248#define MXVR_DMA6_START_ADDR 0xffc02814 /* MXVR Sync Data DMA6 Start Address */
249#define MXVR_DMA6_COUNT 0xffc02818 /* MXVR Sync Data DMA6 Loop Count Register */
250#define MXVR_DMA6_CURR_ADDR 0xffc0281c /* MXVR Sync Data DMA6 Current Address */
251#define MXVR_DMA6_CURR_COUNT 0xffc02820 /* MXVR Sync Data DMA6 Current Loop Count */
252
253/* MXVR DMA7 Registers */
254
255#define MXVR_DMA7_CONFIG 0xffc02824 /* MXVR Sync Data DMA7 Config Register */
256#define MXVR_DMA7_START_ADDR 0xffc02828 /* MXVR Sync Data DMA7 Start Address */
257#define MXVR_DMA7_COUNT 0xffc0282c /* MXVR Sync Data DMA7 Loop Count Register */
258#define MXVR_DMA7_CURR_ADDR 0xffc02830 /* MXVR Sync Data DMA7 Current Address */
259#define MXVR_DMA7_CURR_COUNT 0xffc02834 /* MXVR Sync Data DMA7 Current Loop Count */
260
261/* MXVR Asynch Packet Registers */
262
263#define MXVR_AP_CTL 0xffc02838 /* MXVR Async Packet Control Register */
264#define MXVR_APRB_START_ADDR 0xffc0283c /* MXVR Async Packet RX Buffer Start Addr Register */
265#define MXVR_APRB_CURR_ADDR 0xffc02840 /* MXVR Async Packet RX Buffer Current Addr Register */
266#define MXVR_APTB_START_ADDR 0xffc02844 /* MXVR Async Packet TX Buffer Start Addr Register */
267#define MXVR_APTB_CURR_ADDR 0xffc02848 /* MXVR Async Packet TX Buffer Current Addr Register */
268
269/* MXVR Control Message Registers */
270
271#define MXVR_CM_CTL 0xffc0284c /* MXVR Control Message Control Register */
272#define MXVR_CMRB_START_ADDR 0xffc02850 /* MXVR Control Message RX Buffer Start Addr Register */
273#define MXVR_CMRB_CURR_ADDR 0xffc02854 /* MXVR Control Message RX Buffer Current Address */
274#define MXVR_CMTB_START_ADDR 0xffc02858 /* MXVR Control Message TX Buffer Start Addr Register */
275#define MXVR_CMTB_CURR_ADDR 0xffc0285c /* MXVR Control Message TX Buffer Current Address */
276
277/* MXVR Remote Read Registers */
278
279#define MXVR_RRDB_START_ADDR 0xffc02860 /* MXVR Remote Read Buffer Start Addr Register */
280#define MXVR_RRDB_CURR_ADDR 0xffc02864 /* MXVR Remote Read Buffer Current Addr Register */
281
282/* MXVR Pattern Data Registers */
283
284#define MXVR_PAT_DATA_0 0xffc02868 /* MXVR Pattern Data Register 0 */
285#define MXVR_PAT_EN_0 0xffc0286c /* MXVR Pattern Enable Register 0 */
286#define MXVR_PAT_DATA_1 0xffc02870 /* MXVR Pattern Data Register 1 */
287#define MXVR_PAT_EN_1 0xffc02874 /* MXVR Pattern Enable Register 1 */
288
289/* MXVR Frame Counter Registers */
290
291#define MXVR_FRAME_CNT_0 0xffc02878 /* MXVR Frame Counter 0 */
292#define MXVR_FRAME_CNT_1 0xffc0287c /* MXVR Frame Counter 1 */
293
294/* MXVR Routing Table Registers */
295
296#define MXVR_ROUTING_0 0xffc02880 /* MXVR Routing Table Register 0 */
297#define MXVR_ROUTING_1 0xffc02884 /* MXVR Routing Table Register 1 */
298#define MXVR_ROUTING_2 0xffc02888 /* MXVR Routing Table Register 2 */
299#define MXVR_ROUTING_3 0xffc0288c /* MXVR Routing Table Register 3 */
300#define MXVR_ROUTING_4 0xffc02890 /* MXVR Routing Table Register 4 */
301#define MXVR_ROUTING_5 0xffc02894 /* MXVR Routing Table Register 5 */
302#define MXVR_ROUTING_6 0xffc02898 /* MXVR Routing Table Register 6 */
303#define MXVR_ROUTING_7 0xffc0289c /* MXVR Routing Table Register 7 */
304#define MXVR_ROUTING_8 0xffc028a0 /* MXVR Routing Table Register 8 */
305#define MXVR_ROUTING_9 0xffc028a4 /* MXVR Routing Table Register 9 */
306#define MXVR_ROUTING_10 0xffc028a8 /* MXVR Routing Table Register 10 */
307#define MXVR_ROUTING_11 0xffc028ac /* MXVR Routing Table Register 11 */
308#define MXVR_ROUTING_12 0xffc028b0 /* MXVR Routing Table Register 12 */
309#define MXVR_ROUTING_13 0xffc028b4 /* MXVR Routing Table Register 13 */
310#define MXVR_ROUTING_14 0xffc028b8 /* MXVR Routing Table Register 14 */
311
312/* MXVR Counter-Clock-Control Registers */
313
314#define MXVR_BLOCK_CNT 0xffc028c0 /* MXVR Block Counter */
315#define MXVR_CLK_CTL 0xffc028d0 /* MXVR Clock Control Register */
316#define MXVR_CDRPLL_CTL 0xffc028d4 /* MXVR Clock/Data Recovery PLL Control Register */
317#define MXVR_FMPLL_CTL 0xffc028d8 /* MXVR Frequency Multiply PLL Control Register */
318#define MXVR_PIN_CTL 0xffc028dc /* MXVR Pin Control Register */
319#define MXVR_SCLK_CNT 0xffc028e0 /* MXVR System Clock Counter Register */
320
321/* CAN Controller 1 Config 1 Registers */
322
323#define CAN1_MC1 0xffc03200 /* CAN Controller 1 Mailbox Configuration Register 1 */
324#define CAN1_MD1 0xffc03204 /* CAN Controller 1 Mailbox Direction Register 1 */
325#define CAN1_TRS1 0xffc03208 /* CAN Controller 1 Transmit Request Set Register 1 */
326#define CAN1_TRR1 0xffc0320c /* CAN Controller 1 Transmit Request Reset Register 1 */
327#define CAN1_TA1 0xffc03210 /* CAN Controller 1 Transmit Acknowledge Register 1 */
328#define CAN1_AA1 0xffc03214 /* CAN Controller 1 Abort Acknowledge Register 1 */
329#define CAN1_RMP1 0xffc03218 /* CAN Controller 1 Receive Message Pending Register 1 */
330#define CAN1_RML1 0xffc0321c /* CAN Controller 1 Receive Message Lost Register 1 */
331#define CAN1_MBTIF1 0xffc03220 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
332#define CAN1_MBRIF1 0xffc03224 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
333#define CAN1_MBIM1 0xffc03228 /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
334#define CAN1_RFH1 0xffc0322c /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
335#define CAN1_OPSS1 0xffc03230 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
336
337/* CAN Controller 1 Config 2 Registers */
338
339#define CAN1_MC2 0xffc03240 /* CAN Controller 1 Mailbox Configuration Register 2 */
340#define CAN1_MD2 0xffc03244 /* CAN Controller 1 Mailbox Direction Register 2 */
341#define CAN1_TRS2 0xffc03248 /* CAN Controller 1 Transmit Request Set Register 2 */
342#define CAN1_TRR2 0xffc0324c /* CAN Controller 1 Transmit Request Reset Register 2 */
343#define CAN1_TA2 0xffc03250 /* CAN Controller 1 Transmit Acknowledge Register 2 */
344#define CAN1_AA2 0xffc03254 /* CAN Controller 1 Abort Acknowledge Register 2 */
345#define CAN1_RMP2 0xffc03258 /* CAN Controller 1 Receive Message Pending Register 2 */
346#define CAN1_RML2 0xffc0325c /* CAN Controller 1 Receive Message Lost Register 2 */
347#define CAN1_MBTIF2 0xffc03260 /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
348#define CAN1_MBRIF2 0xffc03264 /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
349#define CAN1_MBIM2 0xffc03268 /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
350#define CAN1_RFH2 0xffc0326c /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
351#define CAN1_OPSS2 0xffc03270 /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
352
353/* CAN Controller 1 Clock/Interrupt/Counter Registers */
354
355#define CAN1_CLOCK 0xffc03280 /* CAN Controller 1 Clock Register */
356#define CAN1_TIMING 0xffc03284 /* CAN Controller 1 Timing Register */
357#define CAN1_DEBUG 0xffc03288 /* CAN Controller 1 Debug Register */
358#define CAN1_STATUS 0xffc0328c /* CAN Controller 1 Global Status Register */
359#define CAN1_CEC 0xffc03290 /* CAN Controller 1 Error Counter Register */
360#define CAN1_GIS 0xffc03294 /* CAN Controller 1 Global Interrupt Status Register */
361#define CAN1_GIM 0xffc03298 /* CAN Controller 1 Global Interrupt Mask Register */
362#define CAN1_GIF 0xffc0329c /* CAN Controller 1 Global Interrupt Flag Register */
363#define CAN1_CONTROL 0xffc032a0 /* CAN Controller 1 Master Control Register */
364#define CAN1_INTR 0xffc032a4 /* CAN Controller 1 Interrupt Pending Register */
365#define CAN1_MBTD 0xffc032ac /* CAN Controller 1 Mailbox Temporary Disable Register */
366#define CAN1_EWR 0xffc032b0 /* CAN Controller 1 Programmable Warning Level Register */
367#define CAN1_ESR 0xffc032b4 /* CAN Controller 1 Error Status Register */
368#define CAN1_UCCNT 0xffc032c4 /* CAN Controller 1 Universal Counter Register */
369#define CAN1_UCRC 0xffc032c8 /* CAN Controller 1 Universal Counter Force Reload Register */
370#define CAN1_UCCNF 0xffc032cc /* CAN Controller 1 Universal Counter Configuration Register */
371
372/* CAN Controller 1 Mailbox Acceptance Registers */
373
374#define CAN1_AM00L 0xffc03300 /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
375#define CAN1_AM00H 0xffc03304 /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
376#define CAN1_AM01L 0xffc03308 /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
377#define CAN1_AM01H 0xffc0330c /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
378#define CAN1_AM02L 0xffc03310 /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
379#define CAN1_AM02H 0xffc03314 /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
380#define CAN1_AM03L 0xffc03318 /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
381#define CAN1_AM03H 0xffc0331c /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
382#define CAN1_AM04L 0xffc03320 /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
383#define CAN1_AM04H 0xffc03324 /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
384#define CAN1_AM05L 0xffc03328 /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
385#define CAN1_AM05H 0xffc0332c /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
386#define CAN1_AM06L 0xffc03330 /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
387#define CAN1_AM06H 0xffc03334 /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
388#define CAN1_AM07L 0xffc03338 /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
389#define CAN1_AM07H 0xffc0333c /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
390#define CAN1_AM08L 0xffc03340 /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
391#define CAN1_AM08H 0xffc03344 /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
392#define CAN1_AM09L 0xffc03348 /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
393#define CAN1_AM09H 0xffc0334c /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
394#define CAN1_AM10L 0xffc03350 /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
395#define CAN1_AM10H 0xffc03354 /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
396#define CAN1_AM11L 0xffc03358 /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
397#define CAN1_AM11H 0xffc0335c /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
398#define CAN1_AM12L 0xffc03360 /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
399#define CAN1_AM12H 0xffc03364 /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
400#define CAN1_AM13L 0xffc03368 /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
401#define CAN1_AM13H 0xffc0336c /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
402#define CAN1_AM14L 0xffc03370 /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
403#define CAN1_AM14H 0xffc03374 /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
404#define CAN1_AM15L 0xffc03378 /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
405#define CAN1_AM15H 0xffc0337c /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
406
407/* CAN Controller 1 Mailbox Acceptance Registers */
408
409#define CAN1_AM16L 0xffc03380 /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
410#define CAN1_AM16H 0xffc03384 /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
411#define CAN1_AM17L 0xffc03388 /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
412#define CAN1_AM17H 0xffc0338c /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
413#define CAN1_AM18L 0xffc03390 /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
414#define CAN1_AM18H 0xffc03394 /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
415#define CAN1_AM19L 0xffc03398 /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
416#define CAN1_AM19H 0xffc0339c /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
417#define CAN1_AM20L 0xffc033a0 /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
418#define CAN1_AM20H 0xffc033a4 /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
419#define CAN1_AM21L 0xffc033a8 /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
420#define CAN1_AM21H 0xffc033ac /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
421#define CAN1_AM22L 0xffc033b0 /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
422#define CAN1_AM22H 0xffc033b4 /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
423#define CAN1_AM23L 0xffc033b8 /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
424#define CAN1_AM23H 0xffc033bc /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
425#define CAN1_AM24L 0xffc033c0 /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
426#define CAN1_AM24H 0xffc033c4 /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
427#define CAN1_AM25L 0xffc033c8 /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
428#define CAN1_AM25H 0xffc033cc /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
429#define CAN1_AM26L 0xffc033d0 /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
430#define CAN1_AM26H 0xffc033d4 /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
431#define CAN1_AM27L 0xffc033d8 /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
432#define CAN1_AM27H 0xffc033dc /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
433#define CAN1_AM28L 0xffc033e0 /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
434#define CAN1_AM28H 0xffc033e4 /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
435#define CAN1_AM29L 0xffc033e8 /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
436#define CAN1_AM29H 0xffc033ec /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
437#define CAN1_AM30L 0xffc033f0 /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
438#define CAN1_AM30H 0xffc033f4 /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
439#define CAN1_AM31L 0xffc033f8 /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
440#define CAN1_AM31H 0xffc033fc /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
441
442/* CAN Controller 1 Mailbox Data Registers */
443
444#define CAN1_MB00_DATA0 0xffc03400 /* CAN Controller 1 Mailbox 0 Data 0 Register */
445#define CAN1_MB00_DATA1 0xffc03404 /* CAN Controller 1 Mailbox 0 Data 1 Register */
446#define CAN1_MB00_DATA2 0xffc03408 /* CAN Controller 1 Mailbox 0 Data 2 Register */
447#define CAN1_MB00_DATA3 0xffc0340c /* CAN Controller 1 Mailbox 0 Data 3 Register */
448#define CAN1_MB00_LENGTH 0xffc03410 /* CAN Controller 1 Mailbox 0 Length Register */
449#define CAN1_MB00_TIMESTAMP 0xffc03414 /* CAN Controller 1 Mailbox 0 Timestamp Register */
450#define CAN1_MB00_ID0 0xffc03418 /* CAN Controller 1 Mailbox 0 ID0 Register */
451#define CAN1_MB00_ID1 0xffc0341c /* CAN Controller 1 Mailbox 0 ID1 Register */
452#define CAN1_MB01_DATA0 0xffc03420 /* CAN Controller 1 Mailbox 1 Data 0 Register */
453#define CAN1_MB01_DATA1 0xffc03424 /* CAN Controller 1 Mailbox 1 Data 1 Register */
454#define CAN1_MB01_DATA2 0xffc03428 /* CAN Controller 1 Mailbox 1 Data 2 Register */
455#define CAN1_MB01_DATA3 0xffc0342c /* CAN Controller 1 Mailbox 1 Data 3 Register */
456#define CAN1_MB01_LENGTH 0xffc03430 /* CAN Controller 1 Mailbox 1 Length Register */
457#define CAN1_MB01_TIMESTAMP 0xffc03434 /* CAN Controller 1 Mailbox 1 Timestamp Register */
458#define CAN1_MB01_ID0 0xffc03438 /* CAN Controller 1 Mailbox 1 ID0 Register */
459#define CAN1_MB01_ID1 0xffc0343c /* CAN Controller 1 Mailbox 1 ID1 Register */
460#define CAN1_MB02_DATA0 0xffc03440 /* CAN Controller 1 Mailbox 2 Data 0 Register */
461#define CAN1_MB02_DATA1 0xffc03444 /* CAN Controller 1 Mailbox 2 Data 1 Register */
462#define CAN1_MB02_DATA2 0xffc03448 /* CAN Controller 1 Mailbox 2 Data 2 Register */
463#define CAN1_MB02_DATA3 0xffc0344c /* CAN Controller 1 Mailbox 2 Data 3 Register */
464#define CAN1_MB02_LENGTH 0xffc03450 /* CAN Controller 1 Mailbox 2 Length Register */
465#define CAN1_MB02_TIMESTAMP 0xffc03454 /* CAN Controller 1 Mailbox 2 Timestamp Register */
466#define CAN1_MB02_ID0 0xffc03458 /* CAN Controller 1 Mailbox 2 ID0 Register */
467#define CAN1_MB02_ID1 0xffc0345c /* CAN Controller 1 Mailbox 2 ID1 Register */
468#define CAN1_MB03_DATA0 0xffc03460 /* CAN Controller 1 Mailbox 3 Data 0 Register */
469#define CAN1_MB03_DATA1 0xffc03464 /* CAN Controller 1 Mailbox 3 Data 1 Register */
470#define CAN1_MB03_DATA2 0xffc03468 /* CAN Controller 1 Mailbox 3 Data 2 Register */
471#define CAN1_MB03_DATA3 0xffc0346c /* CAN Controller 1 Mailbox 3 Data 3 Register */
472#define CAN1_MB03_LENGTH 0xffc03470 /* CAN Controller 1 Mailbox 3 Length Register */
473#define CAN1_MB03_TIMESTAMP 0xffc03474 /* CAN Controller 1 Mailbox 3 Timestamp Register */
474#define CAN1_MB03_ID0 0xffc03478 /* CAN Controller 1 Mailbox 3 ID0 Register */
475#define CAN1_MB03_ID1 0xffc0347c /* CAN Controller 1 Mailbox 3 ID1 Register */
476#define CAN1_MB04_DATA0 0xffc03480 /* CAN Controller 1 Mailbox 4 Data 0 Register */
477#define CAN1_MB04_DATA1 0xffc03484 /* CAN Controller 1 Mailbox 4 Data 1 Register */
478#define CAN1_MB04_DATA2 0xffc03488 /* CAN Controller 1 Mailbox 4 Data 2 Register */
479#define CAN1_MB04_DATA3 0xffc0348c /* CAN Controller 1 Mailbox 4 Data 3 Register */
480#define CAN1_MB04_LENGTH 0xffc03490 /* CAN Controller 1 Mailbox 4 Length Register */
481#define CAN1_MB04_TIMESTAMP 0xffc03494 /* CAN Controller 1 Mailbox 4 Timestamp Register */
482#define CAN1_MB04_ID0 0xffc03498 /* CAN Controller 1 Mailbox 4 ID0 Register */
483#define CAN1_MB04_ID1 0xffc0349c /* CAN Controller 1 Mailbox 4 ID1 Register */
484#define CAN1_MB05_DATA0 0xffc034a0 /* CAN Controller 1 Mailbox 5 Data 0 Register */
485#define CAN1_MB05_DATA1 0xffc034a4 /* CAN Controller 1 Mailbox 5 Data 1 Register */
486#define CAN1_MB05_DATA2 0xffc034a8 /* CAN Controller 1 Mailbox 5 Data 2 Register */
487#define CAN1_MB05_DATA3 0xffc034ac /* CAN Controller 1 Mailbox 5 Data 3 Register */
488#define CAN1_MB05_LENGTH 0xffc034b0 /* CAN Controller 1 Mailbox 5 Length Register */
489#define CAN1_MB05_TIMESTAMP 0xffc034b4 /* CAN Controller 1 Mailbox 5 Timestamp Register */
490#define CAN1_MB05_ID0 0xffc034b8 /* CAN Controller 1 Mailbox 5 ID0 Register */
491#define CAN1_MB05_ID1 0xffc034bc /* CAN Controller 1 Mailbox 5 ID1 Register */
492#define CAN1_MB06_DATA0 0xffc034c0 /* CAN Controller 1 Mailbox 6 Data 0 Register */
493#define CAN1_MB06_DATA1 0xffc034c4 /* CAN Controller 1 Mailbox 6 Data 1 Register */
494#define CAN1_MB06_DATA2 0xffc034c8 /* CAN Controller 1 Mailbox 6 Data 2 Register */
495#define CAN1_MB06_DATA3 0xffc034cc /* CAN Controller 1 Mailbox 6 Data 3 Register */
496#define CAN1_MB06_LENGTH 0xffc034d0 /* CAN Controller 1 Mailbox 6 Length Register */
497#define CAN1_MB06_TIMESTAMP 0xffc034d4 /* CAN Controller 1 Mailbox 6 Timestamp Register */
498#define CAN1_MB06_ID0 0xffc034d8 /* CAN Controller 1 Mailbox 6 ID0 Register */
499#define CAN1_MB06_ID1 0xffc034dc /* CAN Controller 1 Mailbox 6 ID1 Register */
500#define CAN1_MB07_DATA0 0xffc034e0 /* CAN Controller 1 Mailbox 7 Data 0 Register */
501#define CAN1_MB07_DATA1 0xffc034e4 /* CAN Controller 1 Mailbox 7 Data 1 Register */
502#define CAN1_MB07_DATA2 0xffc034e8 /* CAN Controller 1 Mailbox 7 Data 2 Register */
503#define CAN1_MB07_DATA3 0xffc034ec /* CAN Controller 1 Mailbox 7 Data 3 Register */
504#define CAN1_MB07_LENGTH 0xffc034f0 /* CAN Controller 1 Mailbox 7 Length Register */
505#define CAN1_MB07_TIMESTAMP 0xffc034f4 /* CAN Controller 1 Mailbox 7 Timestamp Register */
506#define CAN1_MB07_ID0 0xffc034f8 /* CAN Controller 1 Mailbox 7 ID0 Register */
507#define CAN1_MB07_ID1 0xffc034fc /* CAN Controller 1 Mailbox 7 ID1 Register */
508#define CAN1_MB08_DATA0 0xffc03500 /* CAN Controller 1 Mailbox 8 Data 0 Register */
509#define CAN1_MB08_DATA1 0xffc03504 /* CAN Controller 1 Mailbox 8 Data 1 Register */
510#define CAN1_MB08_DATA2 0xffc03508 /* CAN Controller 1 Mailbox 8 Data 2 Register */
511#define CAN1_MB08_DATA3 0xffc0350c /* CAN Controller 1 Mailbox 8 Data 3 Register */
512#define CAN1_MB08_LENGTH 0xffc03510 /* CAN Controller 1 Mailbox 8 Length Register */
513#define CAN1_MB08_TIMESTAMP 0xffc03514 /* CAN Controller 1 Mailbox 8 Timestamp Register */
514#define CAN1_MB08_ID0 0xffc03518 /* CAN Controller 1 Mailbox 8 ID0 Register */
515#define CAN1_MB08_ID1 0xffc0351c /* CAN Controller 1 Mailbox 8 ID1 Register */
516#define CAN1_MB09_DATA0 0xffc03520 /* CAN Controller 1 Mailbox 9 Data 0 Register */
517#define CAN1_MB09_DATA1 0xffc03524 /* CAN Controller 1 Mailbox 9 Data 1 Register */
518#define CAN1_MB09_DATA2 0xffc03528 /* CAN Controller 1 Mailbox 9 Data 2 Register */
519#define CAN1_MB09_DATA3 0xffc0352c /* CAN Controller 1 Mailbox 9 Data 3 Register */
520#define CAN1_MB09_LENGTH 0xffc03530 /* CAN Controller 1 Mailbox 9 Length Register */
521#define CAN1_MB09_TIMESTAMP 0xffc03534 /* CAN Controller 1 Mailbox 9 Timestamp Register */
522#define CAN1_MB09_ID0 0xffc03538 /* CAN Controller 1 Mailbox 9 ID0 Register */
523#define CAN1_MB09_ID1 0xffc0353c /* CAN Controller 1 Mailbox 9 ID1 Register */
524#define CAN1_MB10_DATA0 0xffc03540 /* CAN Controller 1 Mailbox 10 Data 0 Register */
525#define CAN1_MB10_DATA1 0xffc03544 /* CAN Controller 1 Mailbox 10 Data 1 Register */
526#define CAN1_MB10_DATA2 0xffc03548 /* CAN Controller 1 Mailbox 10 Data 2 Register */
527#define CAN1_MB10_DATA3 0xffc0354c /* CAN Controller 1 Mailbox 10 Data 3 Register */
528#define CAN1_MB10_LENGTH 0xffc03550 /* CAN Controller 1 Mailbox 10 Length Register */
529#define CAN1_MB10_TIMESTAMP 0xffc03554 /* CAN Controller 1 Mailbox 10 Timestamp Register */
530#define CAN1_MB10_ID0 0xffc03558 /* CAN Controller 1 Mailbox 10 ID0 Register */
531#define CAN1_MB10_ID1 0xffc0355c /* CAN Controller 1 Mailbox 10 ID1 Register */
532#define CAN1_MB11_DATA0 0xffc03560 /* CAN Controller 1 Mailbox 11 Data 0 Register */
533#define CAN1_MB11_DATA1 0xffc03564 /* CAN Controller 1 Mailbox 11 Data 1 Register */
534#define CAN1_MB11_DATA2 0xffc03568 /* CAN Controller 1 Mailbox 11 Data 2 Register */
535#define CAN1_MB11_DATA3 0xffc0356c /* CAN Controller 1 Mailbox 11 Data 3 Register */
536#define CAN1_MB11_LENGTH 0xffc03570 /* CAN Controller 1 Mailbox 11 Length Register */
537#define CAN1_MB11_TIMESTAMP 0xffc03574 /* CAN Controller 1 Mailbox 11 Timestamp Register */
538#define CAN1_MB11_ID0 0xffc03578 /* CAN Controller 1 Mailbox 11 ID0 Register */
539#define CAN1_MB11_ID1 0xffc0357c /* CAN Controller 1 Mailbox 11 ID1 Register */
540#define CAN1_MB12_DATA0 0xffc03580 /* CAN Controller 1 Mailbox 12 Data 0 Register */
541#define CAN1_MB12_DATA1 0xffc03584 /* CAN Controller 1 Mailbox 12 Data 1 Register */
542#define CAN1_MB12_DATA2 0xffc03588 /* CAN Controller 1 Mailbox 12 Data 2 Register */
543#define CAN1_MB12_DATA3 0xffc0358c /* CAN Controller 1 Mailbox 12 Data 3 Register */
544#define CAN1_MB12_LENGTH 0xffc03590 /* CAN Controller 1 Mailbox 12 Length Register */
545#define CAN1_MB12_TIMESTAMP 0xffc03594 /* CAN Controller 1 Mailbox 12 Timestamp Register */
546#define CAN1_MB12_ID0 0xffc03598 /* CAN Controller 1 Mailbox 12 ID0 Register */
547#define CAN1_MB12_ID1 0xffc0359c /* CAN Controller 1 Mailbox 12 ID1 Register */
548#define CAN1_MB13_DATA0 0xffc035a0 /* CAN Controller 1 Mailbox 13 Data 0 Register */
549#define CAN1_MB13_DATA1 0xffc035a4 /* CAN Controller 1 Mailbox 13 Data 1 Register */
550#define CAN1_MB13_DATA2 0xffc035a8 /* CAN Controller 1 Mailbox 13 Data 2 Register */
551#define CAN1_MB13_DATA3 0xffc035ac /* CAN Controller 1 Mailbox 13 Data 3 Register */
552#define CAN1_MB13_LENGTH 0xffc035b0 /* CAN Controller 1 Mailbox 13 Length Register */
553#define CAN1_MB13_TIMESTAMP 0xffc035b4 /* CAN Controller 1 Mailbox 13 Timestamp Register */
554#define CAN1_MB13_ID0 0xffc035b8 /* CAN Controller 1 Mailbox 13 ID0 Register */
555#define CAN1_MB13_ID1 0xffc035bc /* CAN Controller 1 Mailbox 13 ID1 Register */
556#define CAN1_MB14_DATA0 0xffc035c0 /* CAN Controller 1 Mailbox 14 Data 0 Register */
557#define CAN1_MB14_DATA1 0xffc035c4 /* CAN Controller 1 Mailbox 14 Data 1 Register */
558#define CAN1_MB14_DATA2 0xffc035c8 /* CAN Controller 1 Mailbox 14 Data 2 Register */
559#define CAN1_MB14_DATA3 0xffc035cc /* CAN Controller 1 Mailbox 14 Data 3 Register */
560#define CAN1_MB14_LENGTH 0xffc035d0 /* CAN Controller 1 Mailbox 14 Length Register */
561#define CAN1_MB14_TIMESTAMP 0xffc035d4 /* CAN Controller 1 Mailbox 14 Timestamp Register */
562#define CAN1_MB14_ID0 0xffc035d8 /* CAN Controller 1 Mailbox 14 ID0 Register */
563#define CAN1_MB14_ID1 0xffc035dc /* CAN Controller 1 Mailbox 14 ID1 Register */
564#define CAN1_MB15_DATA0 0xffc035e0 /* CAN Controller 1 Mailbox 15 Data 0 Register */
565#define CAN1_MB15_DATA1 0xffc035e4 /* CAN Controller 1 Mailbox 15 Data 1 Register */
566#define CAN1_MB15_DATA2 0xffc035e8 /* CAN Controller 1 Mailbox 15 Data 2 Register */
567#define CAN1_MB15_DATA3 0xffc035ec /* CAN Controller 1 Mailbox 15 Data 3 Register */
568#define CAN1_MB15_LENGTH 0xffc035f0 /* CAN Controller 1 Mailbox 15 Length Register */
569#define CAN1_MB15_TIMESTAMP 0xffc035f4 /* CAN Controller 1 Mailbox 15 Timestamp Register */
570#define CAN1_MB15_ID0 0xffc035f8 /* CAN Controller 1 Mailbox 15 ID0 Register */
571#define CAN1_MB15_ID1 0xffc035fc /* CAN Controller 1 Mailbox 15 ID1 Register */
572
573/* CAN Controller 1 Mailbox Data Registers */
574
575#define CAN1_MB16_DATA0 0xffc03600 /* CAN Controller 1 Mailbox 16 Data 0 Register */
576#define CAN1_MB16_DATA1 0xffc03604 /* CAN Controller 1 Mailbox 16 Data 1 Register */
577#define CAN1_MB16_DATA2 0xffc03608 /* CAN Controller 1 Mailbox 16 Data 2 Register */
578#define CAN1_MB16_DATA3 0xffc0360c /* CAN Controller 1 Mailbox 16 Data 3 Register */
579#define CAN1_MB16_LENGTH 0xffc03610 /* CAN Controller 1 Mailbox 16 Length Register */
580#define CAN1_MB16_TIMESTAMP 0xffc03614 /* CAN Controller 1 Mailbox 16 Timestamp Register */
581#define CAN1_MB16_ID0 0xffc03618 /* CAN Controller 1 Mailbox 16 ID0 Register */
582#define CAN1_MB16_ID1 0xffc0361c /* CAN Controller 1 Mailbox 16 ID1 Register */
583#define CAN1_MB17_DATA0 0xffc03620 /* CAN Controller 1 Mailbox 17 Data 0 Register */
584#define CAN1_MB17_DATA1 0xffc03624 /* CAN Controller 1 Mailbox 17 Data 1 Register */
585#define CAN1_MB17_DATA2 0xffc03628 /* CAN Controller 1 Mailbox 17 Data 2 Register */
586#define CAN1_MB17_DATA3 0xffc0362c /* CAN Controller 1 Mailbox 17 Data 3 Register */
587#define CAN1_MB17_LENGTH 0xffc03630 /* CAN Controller 1 Mailbox 17 Length Register */
588#define CAN1_MB17_TIMESTAMP 0xffc03634 /* CAN Controller 1 Mailbox 17 Timestamp Register */
589#define CAN1_MB17_ID0 0xffc03638 /* CAN Controller 1 Mailbox 17 ID0 Register */
590#define CAN1_MB17_ID1 0xffc0363c /* CAN Controller 1 Mailbox 17 ID1 Register */
591#define CAN1_MB18_DATA0 0xffc03640 /* CAN Controller 1 Mailbox 18 Data 0 Register */
592#define CAN1_MB18_DATA1 0xffc03644 /* CAN Controller 1 Mailbox 18 Data 1 Register */
593#define CAN1_MB18_DATA2 0xffc03648 /* CAN Controller 1 Mailbox 18 Data 2 Register */
594#define CAN1_MB18_DATA3 0xffc0364c /* CAN Controller 1 Mailbox 18 Data 3 Register */
595#define CAN1_MB18_LENGTH 0xffc03650 /* CAN Controller 1 Mailbox 18 Length Register */
596#define CAN1_MB18_TIMESTAMP 0xffc03654 /* CAN Controller 1 Mailbox 18 Timestamp Register */
597#define CAN1_MB18_ID0 0xffc03658 /* CAN Controller 1 Mailbox 18 ID0 Register */
598#define CAN1_MB18_ID1 0xffc0365c /* CAN Controller 1 Mailbox 18 ID1 Register */
599#define CAN1_MB19_DATA0 0xffc03660 /* CAN Controller 1 Mailbox 19 Data 0 Register */
600#define CAN1_MB19_DATA1 0xffc03664 /* CAN Controller 1 Mailbox 19 Data 1 Register */
601#define CAN1_MB19_DATA2 0xffc03668 /* CAN Controller 1 Mailbox 19 Data 2 Register */
602#define CAN1_MB19_DATA3 0xffc0366c /* CAN Controller 1 Mailbox 19 Data 3 Register */
603#define CAN1_MB19_LENGTH 0xffc03670 /* CAN Controller 1 Mailbox 19 Length Register */
604#define CAN1_MB19_TIMESTAMP 0xffc03674 /* CAN Controller 1 Mailbox 19 Timestamp Register */
605#define CAN1_MB19_ID0 0xffc03678 /* CAN Controller 1 Mailbox 19 ID0 Register */
606#define CAN1_MB19_ID1 0xffc0367c /* CAN Controller 1 Mailbox 19 ID1 Register */
607#define CAN1_MB20_DATA0 0xffc03680 /* CAN Controller 1 Mailbox 20 Data 0 Register */
608#define CAN1_MB20_DATA1 0xffc03684 /* CAN Controller 1 Mailbox 20 Data 1 Register */
609#define CAN1_MB20_DATA2 0xffc03688 /* CAN Controller 1 Mailbox 20 Data 2 Register */
610#define CAN1_MB20_DATA3 0xffc0368c /* CAN Controller 1 Mailbox 20 Data 3 Register */
611#define CAN1_MB20_LENGTH 0xffc03690 /* CAN Controller 1 Mailbox 20 Length Register */
612#define CAN1_MB20_TIMESTAMP 0xffc03694 /* CAN Controller 1 Mailbox 20 Timestamp Register */
613#define CAN1_MB20_ID0 0xffc03698 /* CAN Controller 1 Mailbox 20 ID0 Register */
614#define CAN1_MB20_ID1 0xffc0369c /* CAN Controller 1 Mailbox 20 ID1 Register */
615#define CAN1_MB21_DATA0 0xffc036a0 /* CAN Controller 1 Mailbox 21 Data 0 Register */
616#define CAN1_MB21_DATA1 0xffc036a4 /* CAN Controller 1 Mailbox 21 Data 1 Register */
617#define CAN1_MB21_DATA2 0xffc036a8 /* CAN Controller 1 Mailbox 21 Data 2 Register */
618#define CAN1_MB21_DATA3 0xffc036ac /* CAN Controller 1 Mailbox 21 Data 3 Register */
619#define CAN1_MB21_LENGTH 0xffc036b0 /* CAN Controller 1 Mailbox 21 Length Register */
620#define CAN1_MB21_TIMESTAMP 0xffc036b4 /* CAN Controller 1 Mailbox 21 Timestamp Register */
621#define CAN1_MB21_ID0 0xffc036b8 /* CAN Controller 1 Mailbox 21 ID0 Register */
622#define CAN1_MB21_ID1 0xffc036bc /* CAN Controller 1 Mailbox 21 ID1 Register */
623#define CAN1_MB22_DATA0 0xffc036c0 /* CAN Controller 1 Mailbox 22 Data 0 Register */
624#define CAN1_MB22_DATA1 0xffc036c4 /* CAN Controller 1 Mailbox 22 Data 1 Register */
625#define CAN1_MB22_DATA2 0xffc036c8 /* CAN Controller 1 Mailbox 22 Data 2 Register */
626#define CAN1_MB22_DATA3 0xffc036cc /* CAN Controller 1 Mailbox 22 Data 3 Register */
627#define CAN1_MB22_LENGTH 0xffc036d0 /* CAN Controller 1 Mailbox 22 Length Register */
628#define CAN1_MB22_TIMESTAMP 0xffc036d4 /* CAN Controller 1 Mailbox 22 Timestamp Register */
629#define CAN1_MB22_ID0 0xffc036d8 /* CAN Controller 1 Mailbox 22 ID0 Register */
630#define CAN1_MB22_ID1 0xffc036dc /* CAN Controller 1 Mailbox 22 ID1 Register */
631#define CAN1_MB23_DATA0 0xffc036e0 /* CAN Controller 1 Mailbox 23 Data 0 Register */
632#define CAN1_MB23_DATA1 0xffc036e4 /* CAN Controller 1 Mailbox 23 Data 1 Register */
633#define CAN1_MB23_DATA2 0xffc036e8 /* CAN Controller 1 Mailbox 23 Data 2 Register */
634#define CAN1_MB23_DATA3 0xffc036ec /* CAN Controller 1 Mailbox 23 Data 3 Register */
635#define CAN1_MB23_LENGTH 0xffc036f0 /* CAN Controller 1 Mailbox 23 Length Register */
636#define CAN1_MB23_TIMESTAMP 0xffc036f4 /* CAN Controller 1 Mailbox 23 Timestamp Register */
637#define CAN1_MB23_ID0 0xffc036f8 /* CAN Controller 1 Mailbox 23 ID0 Register */
638#define CAN1_MB23_ID1 0xffc036fc /* CAN Controller 1 Mailbox 23 ID1 Register */
639#define CAN1_MB24_DATA0 0xffc03700 /* CAN Controller 1 Mailbox 24 Data 0 Register */
640#define CAN1_MB24_DATA1 0xffc03704 /* CAN Controller 1 Mailbox 24 Data 1 Register */
641#define CAN1_MB24_DATA2 0xffc03708 /* CAN Controller 1 Mailbox 24 Data 2 Register */
642#define CAN1_MB24_DATA3 0xffc0370c /* CAN Controller 1 Mailbox 24 Data 3 Register */
643#define CAN1_MB24_LENGTH 0xffc03710 /* CAN Controller 1 Mailbox 24 Length Register */
644#define CAN1_MB24_TIMESTAMP 0xffc03714 /* CAN Controller 1 Mailbox 24 Timestamp Register */
645#define CAN1_MB24_ID0 0xffc03718 /* CAN Controller 1 Mailbox 24 ID0 Register */
646#define CAN1_MB24_ID1 0xffc0371c /* CAN Controller 1 Mailbox 24 ID1 Register */
647#define CAN1_MB25_DATA0 0xffc03720 /* CAN Controller 1 Mailbox 25 Data 0 Register */
648#define CAN1_MB25_DATA1 0xffc03724 /* CAN Controller 1 Mailbox 25 Data 1 Register */
649#define CAN1_MB25_DATA2 0xffc03728 /* CAN Controller 1 Mailbox 25 Data 2 Register */
650#define CAN1_MB25_DATA3 0xffc0372c /* CAN Controller 1 Mailbox 25 Data 3 Register */
651#define CAN1_MB25_LENGTH 0xffc03730 /* CAN Controller 1 Mailbox 25 Length Register */
652#define CAN1_MB25_TIMESTAMP 0xffc03734 /* CAN Controller 1 Mailbox 25 Timestamp Register */
653#define CAN1_MB25_ID0 0xffc03738 /* CAN Controller 1 Mailbox 25 ID0 Register */
654#define CAN1_MB25_ID1 0xffc0373c /* CAN Controller 1 Mailbox 25 ID1 Register */
655#define CAN1_MB26_DATA0 0xffc03740 /* CAN Controller 1 Mailbox 26 Data 0 Register */
656#define CAN1_MB26_DATA1 0xffc03744 /* CAN Controller 1 Mailbox 26 Data 1 Register */
657#define CAN1_MB26_DATA2 0xffc03748 /* CAN Controller 1 Mailbox 26 Data 2 Register */
658#define CAN1_MB26_DATA3 0xffc0374c /* CAN Controller 1 Mailbox 26 Data 3 Register */
659#define CAN1_MB26_LENGTH 0xffc03750 /* CAN Controller 1 Mailbox 26 Length Register */
660#define CAN1_MB26_TIMESTAMP 0xffc03754 /* CAN Controller 1 Mailbox 26 Timestamp Register */
661#define CAN1_MB26_ID0 0xffc03758 /* CAN Controller 1 Mailbox 26 ID0 Register */
662#define CAN1_MB26_ID1 0xffc0375c /* CAN Controller 1 Mailbox 26 ID1 Register */
663#define CAN1_MB27_DATA0 0xffc03760 /* CAN Controller 1 Mailbox 27 Data 0 Register */
664#define CAN1_MB27_DATA1 0xffc03764 /* CAN Controller 1 Mailbox 27 Data 1 Register */
665#define CAN1_MB27_DATA2 0xffc03768 /* CAN Controller 1 Mailbox 27 Data 2 Register */
666#define CAN1_MB27_DATA3 0xffc0376c /* CAN Controller 1 Mailbox 27 Data 3 Register */
667#define CAN1_MB27_LENGTH 0xffc03770 /* CAN Controller 1 Mailbox 27 Length Register */
668#define CAN1_MB27_TIMESTAMP 0xffc03774 /* CAN Controller 1 Mailbox 27 Timestamp Register */
669#define CAN1_MB27_ID0 0xffc03778 /* CAN Controller 1 Mailbox 27 ID0 Register */
670#define CAN1_MB27_ID1 0xffc0377c /* CAN Controller 1 Mailbox 27 ID1 Register */
671#define CAN1_MB28_DATA0 0xffc03780 /* CAN Controller 1 Mailbox 28 Data 0 Register */
672#define CAN1_MB28_DATA1 0xffc03784 /* CAN Controller 1 Mailbox 28 Data 1 Register */
673#define CAN1_MB28_DATA2 0xffc03788 /* CAN Controller 1 Mailbox 28 Data 2 Register */
674#define CAN1_MB28_DATA3 0xffc0378c /* CAN Controller 1 Mailbox 28 Data 3 Register */
675#define CAN1_MB28_LENGTH 0xffc03790 /* CAN Controller 1 Mailbox 28 Length Register */
676#define CAN1_MB28_TIMESTAMP 0xffc03794 /* CAN Controller 1 Mailbox 28 Timestamp Register */
677#define CAN1_MB28_ID0 0xffc03798 /* CAN Controller 1 Mailbox 28 ID0 Register */
678#define CAN1_MB28_ID1 0xffc0379c /* CAN Controller 1 Mailbox 28 ID1 Register */
679#define CAN1_MB29_DATA0 0xffc037a0 /* CAN Controller 1 Mailbox 29 Data 0 Register */
680#define CAN1_MB29_DATA1 0xffc037a4 /* CAN Controller 1 Mailbox 29 Data 1 Register */
681#define CAN1_MB29_DATA2 0xffc037a8 /* CAN Controller 1 Mailbox 29 Data 2 Register */
682#define CAN1_MB29_DATA3 0xffc037ac /* CAN Controller 1 Mailbox 29 Data 3 Register */
683#define CAN1_MB29_LENGTH 0xffc037b0 /* CAN Controller 1 Mailbox 29 Length Register */
684#define CAN1_MB29_TIMESTAMP 0xffc037b4 /* CAN Controller 1 Mailbox 29 Timestamp Register */
685#define CAN1_MB29_ID0 0xffc037b8 /* CAN Controller 1 Mailbox 29 ID0 Register */
686#define CAN1_MB29_ID1 0xffc037bc /* CAN Controller 1 Mailbox 29 ID1 Register */
687#define CAN1_MB30_DATA0 0xffc037c0 /* CAN Controller 1 Mailbox 30 Data 0 Register */
688#define CAN1_MB30_DATA1 0xffc037c4 /* CAN Controller 1 Mailbox 30 Data 1 Register */
689#define CAN1_MB30_DATA2 0xffc037c8 /* CAN Controller 1 Mailbox 30 Data 2 Register */
690#define CAN1_MB30_DATA3 0xffc037cc /* CAN Controller 1 Mailbox 30 Data 3 Register */
691#define CAN1_MB30_LENGTH 0xffc037d0 /* CAN Controller 1 Mailbox 30 Length Register */
692#define CAN1_MB30_TIMESTAMP 0xffc037d4 /* CAN Controller 1 Mailbox 30 Timestamp Register */
693#define CAN1_MB30_ID0 0xffc037d8 /* CAN Controller 1 Mailbox 30 ID0 Register */
694#define CAN1_MB30_ID1 0xffc037dc /* CAN Controller 1 Mailbox 30 ID1 Register */
695#define CAN1_MB31_DATA0 0xffc037e0 /* CAN Controller 1 Mailbox 31 Data 0 Register */
696#define CAN1_MB31_DATA1 0xffc037e4 /* CAN Controller 1 Mailbox 31 Data 1 Register */
697#define CAN1_MB31_DATA2 0xffc037e8 /* CAN Controller 1 Mailbox 31 Data 2 Register */
698#define CAN1_MB31_DATA3 0xffc037ec /* CAN Controller 1 Mailbox 31 Data 3 Register */
699#define CAN1_MB31_LENGTH 0xffc037f0 /* CAN Controller 1 Mailbox 31 Length Register */
700#define CAN1_MB31_TIMESTAMP 0xffc037f4 /* CAN Controller 1 Mailbox 31 Timestamp Register */
701#define CAN1_MB31_ID0 0xffc037f8 /* CAN Controller 1 Mailbox 31 ID0 Register */
702#define CAN1_MB31_ID1 0xffc037fc /* CAN Controller 1 Mailbox 31 ID1 Register */
703
704/* ATAPI Registers */
705
706#define ATAPI_CONTROL 0xffc03800 /* ATAPI Control Register */
707#define ATAPI_STATUS 0xffc03804 /* ATAPI Status Register */
708#define ATAPI_DEV_ADDR 0xffc03808 /* ATAPI Device Register Address */
709#define ATAPI_DEV_TXBUF 0xffc0380c /* ATAPI Device Register Write Data */
710#define ATAPI_DEV_RXBUF 0xffc03810 /* ATAPI Device Register Read Data */
711#define ATAPI_INT_MASK 0xffc03814 /* ATAPI Interrupt Mask Register */
712#define ATAPI_INT_STATUS 0xffc03818 /* ATAPI Interrupt Status Register */
713#define ATAPI_XFER_LEN 0xffc0381c /* ATAPI Length of Transfer */
714#define ATAPI_LINE_STATUS 0xffc03820 /* ATAPI Line Status */
715#define ATAPI_SM_STATE 0xffc03824 /* ATAPI State Machine Status */
716#define ATAPI_TERMINATE 0xffc03828 /* ATAPI Host Terminate */
717#define ATAPI_PIO_TFRCNT 0xffc0382c /* ATAPI PIO mode transfer count */
718#define ATAPI_DMA_TFRCNT 0xffc03830 /* ATAPI DMA mode transfer count */
719#define ATAPI_UMAIN_TFRCNT 0xffc03834 /* ATAPI UDMAIN transfer count */
720#define ATAPI_UDMAOUT_TFRCNT 0xffc03838 /* ATAPI UDMAOUT transfer count */
721#define ATAPI_REG_TIM_0 0xffc03840 /* ATAPI Register Transfer Timing 0 */
722#define ATAPI_PIO_TIM_0 0xffc03844 /* ATAPI PIO Timing 0 Register */
723#define ATAPI_PIO_TIM_1 0xffc03848 /* ATAPI PIO Timing 1 Register */
724#define ATAPI_MULTI_TIM_0 0xffc03850 /* ATAPI Multi-DMA Timing 0 Register */
725#define ATAPI_MULTI_TIM_1 0xffc03854 /* ATAPI Multi-DMA Timing 1 Register */
726#define ATAPI_MULTI_TIM_2 0xffc03858 /* ATAPI Multi-DMA Timing 2 Register */
727#define ATAPI_ULTRA_TIM_0 0xffc03860 /* ATAPI Ultra-DMA Timing 0 Register */
728#define ATAPI_ULTRA_TIM_1 0xffc03864 /* ATAPI Ultra-DMA Timing 1 Register */
729#define ATAPI_ULTRA_TIM_2 0xffc03868 /* ATAPI Ultra-DMA Timing 2 Register */
730#define ATAPI_ULTRA_TIM_3 0xffc0386c /* ATAPI Ultra-DMA Timing 3 Register */
731
732/* SDH Registers */
733
734#define SDH_PWR_CTL 0xffc03900 /* SDH Power Control */
735#define SDH_CLK_CTL 0xffc03904 /* SDH Clock Control */
736#define SDH_ARGUMENT 0xffc03908 /* SDH Argument */
737#define SDH_COMMAND 0xffc0390c /* SDH Command */
738#define SDH_RESP_CMD 0xffc03910 /* SDH Response Command */
739#define SDH_RESPONSE0 0xffc03914 /* SDH Response0 */
740#define SDH_RESPONSE1 0xffc03918 /* SDH Response1 */
741#define SDH_RESPONSE2 0xffc0391c /* SDH Response2 */
742#define SDH_RESPONSE3 0xffc03920 /* SDH Response3 */
743#define SDH_DATA_TIMER 0xffc03924 /* SDH Data Timer */
744#define SDH_DATA_LGTH 0xffc03928 /* SDH Data Length */
745#define SDH_DATA_CTL 0xffc0392c /* SDH Data Control */
746#define SDH_DATA_CNT 0xffc03930 /* SDH Data Counter */
747#define SDH_STATUS 0xffc03934 /* SDH Status */
748#define SDH_STATUS_CLR 0xffc03938 /* SDH Status Clear */
749#define SDH_MASK0 0xffc0393c /* SDH Interrupt0 Mask */
750#define SDH_MASK1 0xffc03940 /* SDH Interrupt1 Mask */
751#define SDH_FIFO_CNT 0xffc03948 /* SDH FIFO Counter */
752#define SDH_FIFO 0xffc03980 /* SDH Data FIFO */
753#define SDH_E_STATUS 0xffc039c0 /* SDH Exception Status */
754#define SDH_E_MASK 0xffc039c4 /* SDH Exception Mask */
755#define SDH_CFG 0xffc039c8 /* SDH Configuration */
756#define SDH_RD_WAIT_EN 0xffc039cc /* SDH Read Wait Enable */
757#define SDH_PID0 0xffc039d0 /* SDH Peripheral Identification0 */
758#define SDH_PID1 0xffc039d4 /* SDH Peripheral Identification1 */
759#define SDH_PID2 0xffc039d8 /* SDH Peripheral Identification2 */
760#define SDH_PID3 0xffc039dc /* SDH Peripheral Identification3 */
761#define SDH_PID4 0xffc039e0 /* SDH Peripheral Identification4 */
762#define SDH_PID5 0xffc039e4 /* SDH Peripheral Identification5 */
763#define SDH_PID6 0xffc039e8 /* SDH Peripheral Identification6 */
764#define SDH_PID7 0xffc039ec /* SDH Peripheral Identification7 */
765
766/* HOST Port Registers */
767
768#define HOST_CONTROL 0xffc03a00 /* HOST Control Register */
769#define HOST_STATUS 0xffc03a04 /* HOST Status Register */
770#define HOST_TIMEOUT 0xffc03a08 /* HOST Acknowledge Mode Timeout Register */
771
772/* USB Control Registers */
773
774#define USB_FADDR 0xffc03c00 /* Function address register */
775#define USB_POWER 0xffc03c04 /* Power management register */
776#define USB_INTRTX 0xffc03c08 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
777#define USB_INTRRX 0xffc03c0c /* Interrupt register for Rx endpoints 1 to 7 */
778#define USB_INTRTXE 0xffc03c10 /* Interrupt enable register for IntrTx */
779#define USB_INTRRXE 0xffc03c14 /* Interrupt enable register for IntrRx */
780#define USB_INTRUSB 0xffc03c18 /* Interrupt register for common USB interrupts */
781#define USB_INTRUSBE 0xffc03c1c /* Interrupt enable register for IntrUSB */
782#define USB_FRAME 0xffc03c20 /* USB frame number */
783#define USB_INDEX 0xffc03c24 /* Index register for selecting the indexed endpoint registers */
784#define USB_TESTMODE 0xffc03c28 /* Enabled USB 20 test modes */
785#define USB_GLOBINTR 0xffc03c2c /* Global Interrupt Mask register and Wakeup Exception Interrupt */
786#define USB_GLOBAL_CTL 0xffc03c30 /* Global Clock Control for the core */
787
788/* USB Packet Control Registers */
789
790#define USB_TX_MAX_PACKET 0xffc03c40 /* Maximum packet size for Host Tx endpoint */
791#define USB_CSR0 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
792#define USB_TXCSR 0xffc03c44 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
793#define USB_RX_MAX_PACKET 0xffc03c48 /* Maximum packet size for Host Rx endpoint */
794#define USB_RXCSR 0xffc03c4c /* Control Status register for Host Rx endpoint */
795#define USB_COUNT0 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
796#define USB_RXCOUNT 0xffc03c50 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
797#define USB_TXTYPE 0xffc03c54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
798#define USB_NAKLIMIT0 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
799#define USB_TXINTERVAL 0xffc03c58 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
800#define USB_RXTYPE 0xffc03c5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
801#define USB_RXINTERVAL 0xffc03c60 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
802#define USB_TXCOUNT 0xffc03c68 /* Number of bytes to be written to the selected endpoint Tx FIFO */
803
804/* USB Endpoint FIFO Registers */
805
806#define USB_EP0_FIFO 0xffc03c80 /* Endpoint 0 FIFO */
807#define USB_EP1_FIFO 0xffc03c88 /* Endpoint 1 FIFO */
808#define USB_EP2_FIFO 0xffc03c90 /* Endpoint 2 FIFO */
809#define USB_EP3_FIFO 0xffc03c98 /* Endpoint 3 FIFO */
810#define USB_EP4_FIFO 0xffc03ca0 /* Endpoint 4 FIFO */
811#define USB_EP5_FIFO 0xffc03ca8 /* Endpoint 5 FIFO */
812#define USB_EP6_FIFO 0xffc03cb0 /* Endpoint 6 FIFO */
813#define USB_EP7_FIFO 0xffc03cb8 /* Endpoint 7 FIFO */
814
815/* USB OTG Control Registers */
816
817#define USB_OTG_DEV_CTL 0xffc03d00 /* OTG Device Control Register */
818#define USB_OTG_VBUS_IRQ 0xffc03d04 /* OTG VBUS Control Interrupts */
819#define USB_OTG_VBUS_MASK 0xffc03d08 /* VBUS Control Interrupt Enable */
820
821/* USB Phy Control Registers */
822
823#define USB_LINKINFO 0xffc03d48 /* Enables programming of some PHY-side delays */
824#define USB_VPLEN 0xffc03d4c /* Determines duration of VBUS pulse for VBUS charging */
825#define USB_HS_EOF1 0xffc03d50 /* Time buffer for High-Speed transactions */
826#define USB_FS_EOF1 0xffc03d54 /* Time buffer for Full-Speed transactions */
827#define USB_LS_EOF1 0xffc03d58 /* Time buffer for Low-Speed transactions */
828
829/* (APHY_CNTRL is for ADI usage only) */
830
831#define USB_APHY_CNTRL 0xffc03de0 /* Register that increases visibility of Analog PHY */
832
833/* (APHY_CALIB is for ADI usage only) */
834
835#define USB_APHY_CALIB 0xffc03de4 /* Register used to set some calibration values */
836#define USB_APHY_CNTRL2 0xffc03de8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
837
838/* (PHY_TEST is for ADI usage only) */
839
840#define USB_PHY_TEST 0xffc03dec /* Used for reducing simulation time and simplifies FIFO testability */
841#define USB_PLLOSC_CTRL 0xffc03df0 /* Used to program different parameters for USB PLL and Oscillator */
842#define USB_SRP_CLKDIV 0xffc03df4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
843
844/* USB Endpoint 0 Control Registers */
845
846#define USB_EP_NI0_TXMAXP 0xffc03e00 /* Maximum packet size for Host Tx endpoint0 */
847#define USB_EP_NI0_TXCSR 0xffc03e04 /* Control Status register for endpoint 0 */
848#define USB_EP_NI0_RXMAXP 0xffc03e08 /* Maximum packet size for Host Rx endpoint0 */
849#define USB_EP_NI0_RXCSR 0xffc03e0c /* Control Status register for Host Rx endpoint0 */
850#define USB_EP_NI0_RXCOUNT 0xffc03e10 /* Number of bytes received in endpoint 0 FIFO */
851#define USB_EP_NI0_TXTYPE 0xffc03e14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
852#define USB_EP_NI0_TXINTERVAL 0xffc03e18 /* Sets the NAK response timeout on Endpoint 0 */
853#define USB_EP_NI0_RXTYPE 0xffc03e1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
854#define USB_EP_NI0_RXINTERVAL 0xffc03e20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
855
856/* USB Endpoint 1 Control Registers */
857
858#define USB_EP_NI0_TXCOUNT 0xffc03e28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
859#define USB_EP_NI1_TXMAXP 0xffc03e40 /* Maximum packet size for Host Tx endpoint1 */
860#define USB_EP_NI1_TXCSR 0xffc03e44 /* Control Status register for endpoint1 */
861#define USB_EP_NI1_RXMAXP 0xffc03e48 /* Maximum packet size for Host Rx endpoint1 */
862#define USB_EP_NI1_RXCSR 0xffc03e4c /* Control Status register for Host Rx endpoint1 */
863#define USB_EP_NI1_RXCOUNT 0xffc03e50 /* Number of bytes received in endpoint1 FIFO */
864#define USB_EP_NI1_TXTYPE 0xffc03e54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
865#define USB_EP_NI1_TXINTERVAL 0xffc03e58 /* Sets the NAK response timeout on Endpoint1 */
866#define USB_EP_NI1_RXTYPE 0xffc03e5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
867#define USB_EP_NI1_RXINTERVAL 0xffc03e60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
868
869/* USB Endpoint 2 Control Registers */
870
871#define USB_EP_NI1_TXCOUNT 0xffc03e68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
872#define USB_EP_NI2_TXMAXP 0xffc03e80 /* Maximum packet size for Host Tx endpoint2 */
873#define USB_EP_NI2_TXCSR 0xffc03e84 /* Control Status register for endpoint2 */
874#define USB_EP_NI2_RXMAXP 0xffc03e88 /* Maximum packet size for Host Rx endpoint2 */
875#define USB_EP_NI2_RXCSR 0xffc03e8c /* Control Status register for Host Rx endpoint2 */
876#define USB_EP_NI2_RXCOUNT 0xffc03e90 /* Number of bytes received in endpoint2 FIFO */
877#define USB_EP_NI2_TXTYPE 0xffc03e94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
878#define USB_EP_NI2_TXINTERVAL 0xffc03e98 /* Sets the NAK response timeout on Endpoint2 */
879#define USB_EP_NI2_RXTYPE 0xffc03e9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
880#define USB_EP_NI2_RXINTERVAL 0xffc03ea0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
881
882/* USB Endpoint 3 Control Registers */
883
884#define USB_EP_NI2_TXCOUNT 0xffc03ea8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
885#define USB_EP_NI3_TXMAXP 0xffc03ec0 /* Maximum packet size for Host Tx endpoint3 */
886#define USB_EP_NI3_TXCSR 0xffc03ec4 /* Control Status register for endpoint3 */
887#define USB_EP_NI3_RXMAXP 0xffc03ec8 /* Maximum packet size for Host Rx endpoint3 */
888#define USB_EP_NI3_RXCSR 0xffc03ecc /* Control Status register for Host Rx endpoint3 */
889#define USB_EP_NI3_RXCOUNT 0xffc03ed0 /* Number of bytes received in endpoint3 FIFO */
890#define USB_EP_NI3_TXTYPE 0xffc03ed4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
891#define USB_EP_NI3_TXINTERVAL 0xffc03ed8 /* Sets the NAK response timeout on Endpoint3 */
892#define USB_EP_NI3_RXTYPE 0xffc03edc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
893#define USB_EP_NI3_RXINTERVAL 0xffc03ee0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
894
895/* USB Endpoint 4 Control Registers */
896
897#define USB_EP_NI3_TXCOUNT 0xffc03ee8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
898#define USB_EP_NI4_TXMAXP 0xffc03f00 /* Maximum packet size for Host Tx endpoint4 */
899#define USB_EP_NI4_TXCSR 0xffc03f04 /* Control Status register for endpoint4 */
900#define USB_EP_NI4_RXMAXP 0xffc03f08 /* Maximum packet size for Host Rx endpoint4 */
901#define USB_EP_NI4_RXCSR 0xffc03f0c /* Control Status register for Host Rx endpoint4 */
902#define USB_EP_NI4_RXCOUNT 0xffc03f10 /* Number of bytes received in endpoint4 FIFO */
903#define USB_EP_NI4_TXTYPE 0xffc03f14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
904#define USB_EP_NI4_TXINTERVAL 0xffc03f18 /* Sets the NAK response timeout on Endpoint4 */
905#define USB_EP_NI4_RXTYPE 0xffc03f1c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
906#define USB_EP_NI4_RXINTERVAL 0xffc03f20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
907
908/* USB Endpoint 5 Control Registers */
909
910#define USB_EP_NI4_TXCOUNT 0xffc03f28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
911#define USB_EP_NI5_TXMAXP 0xffc03f40 /* Maximum packet size for Host Tx endpoint5 */
912#define USB_EP_NI5_TXCSR 0xffc03f44 /* Control Status register for endpoint5 */
913#define USB_EP_NI5_RXMAXP 0xffc03f48 /* Maximum packet size for Host Rx endpoint5 */
914#define USB_EP_NI5_RXCSR 0xffc03f4c /* Control Status register for Host Rx endpoint5 */
915#define USB_EP_NI5_RXCOUNT 0xffc03f50 /* Number of bytes received in endpoint5 FIFO */
916#define USB_EP_NI5_TXTYPE 0xffc03f54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
917#define USB_EP_NI5_TXINTERVAL 0xffc03f58 /* Sets the NAK response timeout on Endpoint5 */
918#define USB_EP_NI5_RXTYPE 0xffc03f5c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
919#define USB_EP_NI5_RXINTERVAL 0xffc03f60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
920
921/* USB Endpoint 6 Control Registers */
922
923#define USB_EP_NI5_TXCOUNT 0xffc03f68 /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
924#define USB_EP_NI6_TXMAXP 0xffc03f80 /* Maximum packet size for Host Tx endpoint6 */
925#define USB_EP_NI6_TXCSR 0xffc03f84 /* Control Status register for endpoint6 */
926#define USB_EP_NI6_RXMAXP 0xffc03f88 /* Maximum packet size for Host Rx endpoint6 */
927#define USB_EP_NI6_RXCSR 0xffc03f8c /* Control Status register for Host Rx endpoint6 */
928#define USB_EP_NI6_RXCOUNT 0xffc03f90 /* Number of bytes received in endpoint6 FIFO */
929#define USB_EP_NI6_TXTYPE 0xffc03f94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
930#define USB_EP_NI6_TXINTERVAL 0xffc03f98 /* Sets the NAK response timeout on Endpoint6 */
931#define USB_EP_NI6_RXTYPE 0xffc03f9c /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
932#define USB_EP_NI6_RXINTERVAL 0xffc03fa0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
933
934/* USB Endpoint 7 Control Registers */
935
936#define USB_EP_NI6_TXCOUNT 0xffc03fa8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
937#define USB_EP_NI7_TXMAXP 0xffc03fc0 /* Maximum packet size for Host Tx endpoint7 */
938#define USB_EP_NI7_TXCSR 0xffc03fc4 /* Control Status register for endpoint7 */
939#define USB_EP_NI7_RXMAXP 0xffc03fc8 /* Maximum packet size for Host Rx endpoint7 */
940#define USB_EP_NI7_RXCSR 0xffc03fcc /* Control Status register for Host Rx endpoint7 */
941#define USB_EP_NI7_RXCOUNT 0xffc03fd0 /* Number of bytes received in endpoint7 FIFO */
942#define USB_EP_NI7_TXTYPE 0xffc03fd4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
943#define USB_EP_NI7_TXINTERVAL 0xffc03fd8 /* Sets the NAK response timeout on Endpoint7 */
944#define USB_EP_NI7_RXTYPE 0xffc03fdc /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
945#define USB_EP_NI7_RXINTERVAL 0xffc03ff0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
946#define USB_EP_NI7_TXCOUNT 0xffc03ff8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
947#define USB_DMA_INTERRUPT 0xffc04000 /* Indicates pending interrupts for the DMA channels */
948
949/* USB Channel 0 Config Registers */
950
951#define USB_DMA0CONTROL 0xffc04004 /* DMA master channel 0 configuration */
952#define USB_DMA0ADDRLOW 0xffc04008 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
953#define USB_DMA0ADDRHIGH 0xffc0400c /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
954#define USB_DMA0COUNTLOW 0xffc04010 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
955#define USB_DMA0COUNTHIGH 0xffc04014 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
956
957/* USB Channel 1 Config Registers */
958
959#define USB_DMA1CONTROL 0xffc04024 /* DMA master channel 1 configuration */
960#define USB_DMA1ADDRLOW 0xffc04028 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
961#define USB_DMA1ADDRHIGH 0xffc0402c /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
962#define USB_DMA1COUNTLOW 0xffc04030 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
963#define USB_DMA1COUNTHIGH 0xffc04034 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
964
965/* USB Channel 2 Config Registers */
966
967#define USB_DMA2CONTROL 0xffc04044 /* DMA master channel 2 configuration */
968#define USB_DMA2ADDRLOW 0xffc04048 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
969#define USB_DMA2ADDRHIGH 0xffc0404c /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
970#define USB_DMA2COUNTLOW 0xffc04050 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
971#define USB_DMA2COUNTHIGH 0xffc04054 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
972
973/* USB Channel 3 Config Registers */
974
975#define USB_DMA3CONTROL 0xffc04064 /* DMA master channel 3 configuration */
976#define USB_DMA3ADDRLOW 0xffc04068 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
977#define USB_DMA3ADDRHIGH 0xffc0406c /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
978#define USB_DMA3COUNTLOW 0xffc04070 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
979#define USB_DMA3COUNTHIGH 0xffc04074 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
980
981/* USB Channel 4 Config Registers */
982
983#define USB_DMA4CONTROL 0xffc04084 /* DMA master channel 4 configuration */
984#define USB_DMA4ADDRLOW 0xffc04088 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
985#define USB_DMA4ADDRHIGH 0xffc0408c /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
986#define USB_DMA4COUNTLOW 0xffc04090 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
987#define USB_DMA4COUNTHIGH 0xffc04094 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
988
989/* USB Channel 5 Config Registers */
990
991#define USB_DMA5CONTROL 0xffc040a4 /* DMA master channel 5 configuration */
992#define USB_DMA5ADDRLOW 0xffc040a8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
993#define USB_DMA5ADDRHIGH 0xffc040ac /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
994#define USB_DMA5COUNTLOW 0xffc040b0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
995#define USB_DMA5COUNTHIGH 0xffc040b4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
996
997/* USB Channel 6 Config Registers */
998
999#define USB_DMA6CONTROL 0xffc040c4 /* DMA master channel 6 configuration */
1000#define USB_DMA6ADDRLOW 0xffc040c8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
1001#define USB_DMA6ADDRHIGH 0xffc040cc /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
1002#define USB_DMA6COUNTLOW 0xffc040d0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
1003#define USB_DMA6COUNTHIGH 0xffc040d4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
1004
1005/* USB Channel 7 Config Registers */
1006
1007#define USB_DMA7CONTROL 0xffc040e4 /* DMA master channel 7 configuration */
1008#define USB_DMA7ADDRLOW 0xffc040e8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
1009#define USB_DMA7ADDRHIGH 0xffc040ec /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
1010#define USB_DMA7COUNTLOW 0xffc040f0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
1011#define USB_DMA7COUNTHIGH 0xffc040f4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
1012
1013/* Keypad Registers */
1014
1015#define KPAD_CTL 0xffc04100 /* Controls keypad module enable and disable */
1016#define KPAD_PRESCALE 0xffc04104 /* Establish a time base for programing the KPAD_MSEL register */
1017#define KPAD_MSEL 0xffc04108 /* Selects delay parameters for keypad interface sensitivity */
1018#define KPAD_ROWCOL 0xffc0410c /* Captures the row and column output values of the keys pressed */
1019#define KPAD_STAT 0xffc04110 /* Holds and clears the status of the keypad interface interrupt */
1020#define KPAD_SOFTEVAL 0xffc04114 /* Lets software force keypad interface to check for keys being pressed */
1021
1022/* Pixel Compositor (PIXC) Registers */
1023
1024#define PIXC_CTL 0xffc04400 /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
1025#define PIXC_PPL 0xffc04404 /* Holds the number of pixels per line of the display */
1026#define PIXC_LPF 0xffc04408 /* Holds the number of lines per frame of the display */
1027#define PIXC_AHSTART 0xffc0440c /* Contains horizontal start pixel information of the overlay data (set A) */
1028#define PIXC_AHEND 0xffc04410 /* Contains horizontal end pixel information of the overlay data (set A) */
1029#define PIXC_AVSTART 0xffc04414 /* Contains vertical start pixel information of the overlay data (set A) */
1030#define PIXC_AVEND 0xffc04418 /* Contains vertical end pixel information of the overlay data (set A) */
1031#define PIXC_ATRANSP 0xffc0441c /* Contains the transparency ratio (set A) */
1032#define PIXC_BHSTART 0xffc04420 /* Contains horizontal start pixel information of the overlay data (set B) */
1033#define PIXC_BHEND 0xffc04424 /* Contains horizontal end pixel information of the overlay data (set B) */
1034#define PIXC_BVSTART 0xffc04428 /* Contains vertical start pixel information of the overlay data (set B) */
1035#define PIXC_BVEND 0xffc0442c /* Contains vertical end pixel information of the overlay data (set B) */
1036#define PIXC_BTRANSP 0xffc04430 /* Contains the transparency ratio (set B) */
1037#define PIXC_INTRSTAT 0xffc0443c /* Overlay interrupt configuration/status */
1038#define PIXC_RYCON 0xffc04440 /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
1039#define PIXC_GUCON 0xffc04444 /* Color space conversion matrix register. Contains the G/U conversion coefficients */
1040#define PIXC_BVCON 0xffc04448 /* Color space conversion matrix register. Contains the B/V conversion coefficients */
1041#define PIXC_CCBIAS 0xffc0444c /* Bias values for the color space conversion matrix */
1042#define PIXC_TC 0xffc04450 /* Holds the transparent color value */
1043
1044/* Handshake MDMA 0 Registers */
1045
1046#define HMDMA0_CONTROL 0xffc04500 /* Handshake MDMA0 Control Register */
1047#define HMDMA0_ECINIT 0xffc04504 /* Handshake MDMA0 Initial Edge Count Register */
1048#define HMDMA0_BCINIT 0xffc04508 /* Handshake MDMA0 Initial Block Count Register */
1049#define HMDMA0_ECURGENT 0xffc0450c /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
1050#define HMDMA0_ECOVERFLOW 0xffc04510 /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
1051#define HMDMA0_ECOUNT 0xffc04514 /* Handshake MDMA0 Current Edge Count Register */
1052#define HMDMA0_BCOUNT 0xffc04518 /* Handshake MDMA0 Current Block Count Register */
1053
1054/* Handshake MDMA 1 Registers */
1055
1056#define HMDMA1_CONTROL 0xffc04540 /* Handshake MDMA1 Control Register */
1057#define HMDMA1_ECINIT 0xffc04544 /* Handshake MDMA1 Initial Edge Count Register */
1058#define HMDMA1_BCINIT 0xffc04548 /* Handshake MDMA1 Initial Block Count Register */
1059#define HMDMA1_ECURGENT 0xffc0454c /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
1060#define HMDMA1_ECOVERFLOW 0xffc04550 /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
1061#define HMDMA1_ECOUNT 0xffc04554 /* Handshake MDMA1 Current Edge Count Register */
1062#define HMDMA1_BCOUNT 0xffc04558 /* Handshake MDMA1 Current Block Count Register */
1063
1064
1065/* ********************************************************** */
1066/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1067/* and MULTI BIT READ MACROS */
1068/* ********************************************************** */
1069
1070/* Bit masks for PIXC_CTL */
1071
1072#define PIXC_EN 0x1 /* Pixel Compositor Enable */
1073#define nPIXC_EN 0x0
1074#define OVR_A_EN 0x2 /* Overlay A Enable */
1075#define nOVR_A_EN 0x0
1076#define OVR_B_EN 0x4 /* Overlay B Enable */
1077#define nOVR_B_EN 0x0
1078#define IMG_FORM 0x8 /* Image Data Format */
1079#define nIMG_FORM 0x0
1080#define OVR_FORM 0x10 /* Overlay Data Format */
1081#define nOVR_FORM 0x0
1082#define OUT_FORM 0x20 /* Output Data Format */
1083#define nOUT_FORM 0x0
1084#define UDS_MOD 0x40 /* Resampling Mode */
1085#define nUDS_MOD 0x0
1086#define TC_EN 0x80 /* Transparent Color Enable */
1087#define nTC_EN 0x0
1088#define IMG_STAT 0x300 /* Image FIFO Status */
1089#define OVR_STAT 0xc00 /* Overlay FIFO Status */
1090#define WM_LVL 0x3000 /* FIFO Watermark Level */
1091
1092/* Bit masks for PIXC_AHSTART */
1093
1094#define A_HSTART 0xfff /* Horizontal Start Coordinates */
1095
1096/* Bit masks for PIXC_AHEND */
1097
1098#define A_HEND 0xfff /* Horizontal End Coordinates */
1099
1100/* Bit masks for PIXC_AVSTART */
1101
1102#define A_VSTART 0x3ff /* Vertical Start Coordinates */
1103
1104/* Bit masks for PIXC_AVEND */
1105
1106#define A_VEND 0x3ff /* Vertical End Coordinates */
1107
1108/* Bit masks for PIXC_ATRANSP */
1109
1110#define A_TRANSP 0xf /* Transparency Value */
1111
1112/* Bit masks for PIXC_BHSTART */
1113
1114#define B_HSTART 0xfff /* Horizontal Start Coordinates */
1115
1116/* Bit masks for PIXC_BHEND */
1117
1118#define B_HEND 0xfff /* Horizontal End Coordinates */
1119
1120/* Bit masks for PIXC_BVSTART */
1121
1122#define B_VSTART 0x3ff /* Vertical Start Coordinates */
1123
1124/* Bit masks for PIXC_BVEND */
1125
1126#define B_VEND 0x3ff /* Vertical End Coordinates */
1127
1128/* Bit masks for PIXC_BTRANSP */
1129
1130#define B_TRANSP 0xf /* Transparency Value */
1131
1132/* Bit masks for PIXC_INTRSTAT */
1133
1134#define OVR_INT_EN 0x1 /* Interrupt at End of Last Valid Overlay */
1135#define nOVR_INT_EN 0x0
1136#define FRM_INT_EN 0x2 /* Interrupt at End of Frame */
1137#define nFRM_INT_EN 0x0
1138#define OVR_INT_STAT 0x4 /* Overlay Interrupt Status */
1139#define nOVR_INT_STAT 0x0
1140#define FRM_INT_STAT 0x8 /* Frame Interrupt Status */
1141#define nFRM_INT_STAT 0x0
1142
1143/* Bit masks for PIXC_RYCON */
1144
1145#define A11 0x3ff /* A11 in the Coefficient Matrix */
1146#define A12 0xffc00 /* A12 in the Coefficient Matrix */
1147#define A13 0x3ff00000 /* A13 in the Coefficient Matrix */
1148#define RY_MULT4 0x40000000 /* Multiply Row by 4 */
1149#define nRY_MULT4 0x0
1150
1151/* Bit masks for PIXC_GUCON */
1152
1153#define A21 0x3ff /* A21 in the Coefficient Matrix */
1154#define A22 0xffc00 /* A22 in the Coefficient Matrix */
1155#define A23 0x3ff00000 /* A23 in the Coefficient Matrix */
1156#define GU_MULT4 0x40000000 /* Multiply Row by 4 */
1157#define nGU_MULT4 0x0
1158
1159/* Bit masks for PIXC_BVCON */
1160
1161#define A31 0x3ff /* A31 in the Coefficient Matrix */
1162#define A32 0xffc00 /* A32 in the Coefficient Matrix */
1163#define A33 0x3ff00000 /* A33 in the Coefficient Matrix */
1164#define BV_MULT4 0x40000000 /* Multiply Row by 4 */
1165#define nBV_MULT4 0x0
1166
1167/* Bit masks for PIXC_CCBIAS */
1168
1169#define A14 0x3ff /* A14 in the Bias Vector */
1170#define A24 0xffc00 /* A24 in the Bias Vector */
1171#define A34 0x3ff00000 /* A34 in the Bias Vector */
1172
1173/* Bit masks for PIXC_TC */
1174
1175#define RY_TRANS 0xff /* Transparent Color - R/Y Component */
1176#define GU_TRANS 0xff00 /* Transparent Color - G/U Component */
1177#define BV_TRANS 0xff0000 /* Transparent Color - B/V Component */
1178
1179/* Bit masks for HOST_CONTROL */
1180
1181#define HOST_EN 0x1 /* Host Enable */
1182#define nHOST_EN 0x0
1183#define HOST_END 0x2 /* Host Endianess */
1184#define nHOST_END 0x0
1185#define DATA_SIZE 0x4 /* Data Size */
1186#define nDATA_SIZE 0x0
1187#define HOST_RST 0x8 /* Host Reset */
1188#define nHOST_RST 0x0
1189#define HRDY_OVR 0x20 /* Host Ready Override */
1190#define nHRDY_OVR 0x0
1191#define INT_MODE 0x40 /* Interrupt Mode */
1192#define nINT_MODE 0x0
1193#define BT_EN 0x80 /* Bus Timeout Enable */
1194#define nBT_EN 0x0
1195#define EHW 0x100 /* Enable Host Write */
1196#define nEHW 0x0
1197#define EHR 0x200 /* Enable Host Read */
1198#define nEHR 0x0
1199#define BDR 0x400 /* Burst DMA Requests */
1200#define nBDR 0x0
1201
1202/* Bit masks for HOST_STATUS */
1203
1204#define READY 0x1 /* DMA Ready */
1205#define nREADY 0x0
1206#define FIFOFULL 0x2 /* FIFO Full */
1207#define nFIFOFULL 0x0
1208#define FIFOEMPTY 0x4 /* FIFO Empty */
1209#define nFIFOEMPTY 0x0
1210#define COMPLETE 0x8 /* DMA Complete */
1211#define nCOMPLETE 0x0
1212#define HSHK 0x10 /* Host Handshake */
1213#define nHSHK 0x0
1214#define TIMEOUT 0x20 /* Host Timeout */
1215#define nTIMEOUT 0x0
1216#define HIRQ 0x40 /* Host Interrupt Request */
1217#define nHIRQ 0x0
1218#define ALLOW_CNFG 0x80 /* Allow New Configuration */
1219#define nALLOW_CNFG 0x0
1220#define DMA_DIR 0x100 /* DMA Direction */
1221#define nDMA_DIR 0x0
1222#define BTE 0x200 /* Bus Timeout Enabled */
1223#define nBTE 0x0
1224
1225/* Bit masks for HOST_TIMEOUT */
1226
1227#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */
1228
1229/* Bit masks for MXVR_CONFIG */
1230
1231#define MXVREN 0x1 /* MXVR Enable */
1232#define nMXVREN 0x0
1233#define MMSM 0x2 /* MXVR Master/Slave Mode Select */
1234#define nMMSM 0x0
1235#define ACTIVE 0x4 /* Active Mode */
1236#define nACTIVE 0x0
1237#define SDELAY 0x8 /* Synchronous Data Delay */
1238#define nSDELAY 0x0
1239#define NCMRXEN 0x10 /* Normal Control Message Receive Enable */
1240#define nNCMRXEN 0x0
1241#define RWRRXEN 0x20 /* Remote Write Receive Enable */
1242#define nRWRRXEN 0x0
1243#define MTXEN 0x40 /* MXVR Transmit Data Enable */
1244#define nMTXEN 0x0
1245#define MTXONB 0x80 /* MXVR Phy Transmitter On */
1246#define nMTXONB 0x0
1247#define EPARITY 0x100 /* Even Parity Select */
1248#define nEPARITY 0x0
1249#define MSB 0x1e00 /* Master Synchronous Boundary */
1250#define APRXEN 0x2000 /* Asynchronous Packet Receive Enable */
1251#define nAPRXEN 0x0
1252#define WAKEUP 0x4000 /* Wake-Up */
1253#define nWAKEUP 0x0
1254#define LMECH 0x8000 /* Lock Mechanism Select */
1255#define nLMECH 0x0
1256
1257/* Bit masks for MXVR_STATE_0 */
1258
1259#define NACT 0x1 /* Network Activity */
1260#define nNACT 0x0
1261#define SBLOCK 0x2 /* Super Block Lock */
1262#define nSBLOCK 0x0
1263#define FMPLLST 0xc /* Frequency Multiply PLL SM State */
1264#define CDRPLLST 0xe0 /* Clock/Data Recovery PLL SM State */
1265#define APBSY 0x100 /* Asynchronous Packet Transmit Buffer Busy */
1266#define nAPBSY 0x0
1267#define APARB 0x200 /* Asynchronous Packet Arbitrating */
1268#define nAPARB 0x0
1269#define APTX 0x400 /* Asynchronous Packet Transmitting */
1270#define nAPTX 0x0
1271#define APRX 0x800 /* Receiving Asynchronous Packet */
1272#define nAPRX 0x0
1273#define CMBSY 0x1000 /* Control Message Transmit Buffer Busy */
1274#define nCMBSY 0x0
1275#define CMARB 0x2000 /* Control Message Arbitrating */
1276#define nCMARB 0x0
1277#define CMTX 0x4000 /* Control Message Transmitting */
1278#define nCMTX 0x0
1279#define CMRX 0x8000 /* Receiving Control Message */
1280#define nCMRX 0x0
1281#define MRXONB 0x10000 /* MRXONB Pin State */
1282#define nMRXONB 0x0
1283#define RGSIP 0x20000 /* Remote Get Source In Progress */
1284#define nRGSIP 0x0
1285#define DALIP 0x40000 /* Resource Deallocate In Progress */
1286#define nDALIP 0x0
1287#define ALIP 0x80000 /* Resource Allocate In Progress */
1288#define nALIP 0x0
1289#define RRDIP 0x100000 /* Remote Read In Progress */
1290#define nRRDIP 0x0
1291#define RWRIP 0x200000 /* Remote Write In Progress */
1292#define nRWRIP 0x0
1293#define FLOCK 0x400000 /* Frame Lock */
1294#define nFLOCK 0x0
1295#define BLOCK 0x800000 /* Block Lock */
1296#define nBLOCK 0x0
1297#define RSB 0xf000000 /* Received Synchronous Boundary */
1298#define DERRNUM 0xf0000000 /* DMA Error Channel Number */
1299
1300/* Bit masks for MXVR_STATE_1 */
1301
1302#define SRXNUMB 0xf /* Synchronous Receive FIFO Number of Bytes */
1303#define STXNUMB 0xf0 /* Synchronous Transmit FIFO Number of Bytes */
1304#define APCONT 0x100 /* Asynchronous Packet Continuation */
1305#define nAPCONT 0x0
1306#define OBERRNUM 0xe00 /* DMA Out of Bounds Error Channel Number */
1307#define DMAACTIVE0 0x10000 /* DMA0 Active */
1308#define nDMAACTIVE0 0x0
1309#define DMAACTIVE1 0x20000 /* DMA1 Active */
1310#define nDMAACTIVE1 0x0
1311#define DMAACTIVE2 0x40000 /* DMA2 Active */
1312#define nDMAACTIVE2 0x0
1313#define DMAACTIVE3 0x80000 /* DMA3 Active */
1314#define nDMAACTIVE3 0x0
1315#define DMAACTIVE4 0x100000 /* DMA4 Active */
1316#define nDMAACTIVE4 0x0
1317#define DMAACTIVE5 0x200000 /* DMA5 Active */
1318#define nDMAACTIVE5 0x0
1319#define DMAACTIVE6 0x400000 /* DMA6 Active */
1320#define nDMAACTIVE6 0x0
1321#define DMAACTIVE7 0x800000 /* DMA7 Active */
1322#define nDMAACTIVE7 0x0
1323#define DMAPMEN0 0x1000000 /* DMA0 Pattern Matching Enabled */
1324#define nDMAPMEN0 0x0
1325#define DMAPMEN1 0x2000000 /* DMA1 Pattern Matching Enabled */
1326#define nDMAPMEN1 0x0
1327#define DMAPMEN2 0x4000000 /* DMA2 Pattern Matching Enabled */
1328#define nDMAPMEN2 0x0
1329#define DMAPMEN3 0x8000000 /* DMA3 Pattern Matching Enabled */
1330#define nDMAPMEN3 0x0
1331#define DMAPMEN4 0x10000000 /* DMA4 Pattern Matching Enabled */
1332#define nDMAPMEN4 0x0
1333#define DMAPMEN5 0x20000000 /* DMA5 Pattern Matching Enabled */
1334#define nDMAPMEN5 0x0
1335#define DMAPMEN6 0x40000000 /* DMA6 Pattern Matching Enabled */
1336#define nDMAPMEN6 0x0
1337#define DMAPMEN7 0x80000000 /* DMA7 Pattern Matching Enabled */
1338#define nDMAPMEN7 0x0
1339
1340/* Bit masks for MXVR_INT_STAT_0 */
1341
1342#define NI2A 0x1 /* Network Inactive to Active */
1343#define nNI2A 0x0
1344#define NA2I 0x2 /* Network Active to Inactive */
1345#define nNA2I 0x0
1346#define SBU2L 0x4 /* Super Block Unlock to Lock */
1347#define nSBU2L 0x0
1348#define SBL2U 0x8 /* Super Block Lock to Unlock */
1349#define nSBL2U 0x0
1350#define PRU 0x10 /* Position Register Updated */
1351#define nPRU 0x0
1352#define MPRU 0x20 /* Maximum Position Register Updated */
1353#define nMPRU 0x0
1354#define DRU 0x40 /* Delay Register Updated */
1355#define nDRU 0x0
1356#define MDRU 0x80 /* Maximum Delay Register Updated */
1357#define nMDRU 0x0
1358#define SBU 0x100 /* Synchronous Boundary Updated */
1359#define nSBU 0x0
1360#define ATU 0x200 /* Allocation Table Updated */
1361#define nATU 0x0
1362#define FCZ0 0x400 /* Frame Counter 0 Zero */
1363#define nFCZ0 0x0
1364#define FCZ1 0x800 /* Frame Counter 1 Zero */
1365#define nFCZ1 0x0
1366#define PERR 0x1000 /* Parity Error */
1367#define nPERR 0x0
1368#define MH2L 0x2000 /* MRXONB High to Low */
1369#define nMH2L 0x0
1370#define ML2H 0x4000 /* MRXONB Low to High */
1371#define nML2H 0x0
1372#define WUP 0x8000 /* Wake-Up Preamble Received */
1373#define nWUP 0x0
1374#define FU2L 0x10000 /* Frame Unlock to Lock */
1375#define nFU2L 0x0
1376#define FL2U 0x20000 /* Frame Lock to Unlock */
1377#define nFL2U 0x0
1378#define BU2L 0x40000 /* Block Unlock to Lock */
1379#define nBU2L 0x0
1380#define BL2U 0x80000 /* Block Lock to Unlock */
1381#define nBL2U 0x0
1382#define OBERR 0x100000 /* DMA Out of Bounds Error */
1383#define nOBERR 0x0
1384#define PFL 0x200000 /* PLL Frequency Locked */
1385#define nPFL 0x0
1386#define SCZ 0x400000 /* System Clock Counter Zero */
1387#define nSCZ 0x0
1388#define FERR 0x800000 /* FIFO Error */
1389#define nFERR 0x0
1390#define CMR 0x1000000 /* Control Message Received */
1391#define nCMR 0x0
1392#define CMROF 0x2000000 /* Control Message Receive Buffer Overflow */
1393#define nCMROF 0x0
1394#define CMTS 0x4000000 /* Control Message Transmit Buffer Successfully Sent */
1395#define nCMTS 0x0
1396#define CMTC 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled */
1397#define nCMTC 0x0
1398#define RWRC 0x10000000 /* Remote Write Control Message Completed */
1399#define nRWRC 0x0
1400#define BCZ 0x20000000 /* Block Counter Zero */
1401#define nBCZ 0x0
1402#define BMERR 0x40000000 /* Biphase Mark Coding Error */
1403#define nBMERR 0x0
1404#define DERR 0x80000000 /* DMA Error */
1405#define nDERR 0x0
1406
1407/* Bit masks for MXVR_INT_STAT_1 */
1408
1409#define HDONE0 0x1 /* DMA0 Half Done */
1410#define nHDONE0 0x0
1411#define DONE0 0x2 /* DMA0 Done */
1412#define nDONE0 0x0
1413#define APR 0x4 /* Asynchronous Packet Received */
1414#define nAPR 0x0
1415#define APROF 0x8 /* Asynchronous Packet Receive Buffer Overflow */
1416#define nAPROF 0x0
1417#define HDONE1 0x10 /* DMA1 Half Done */
1418#define nHDONE1 0x0
1419#define DONE1 0x20 /* DMA1 Done */
1420#define nDONE1 0x0
1421#define APTS 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent */
1422#define nAPTS 0x0
1423#define APTC 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
1424#define nAPTC 0x0
1425#define HDONE2 0x100 /* DMA2 Half Done */
1426#define nHDONE2 0x0
1427#define DONE2 0x200 /* DMA2 Done */
1428#define nDONE2 0x0
1429#define APRCE 0x400 /* Asynchronous Packet Receive CRC Error */
1430#define nAPRCE 0x0
1431#define APRPE 0x800 /* Asynchronous Packet Receive Packet Error */
1432#define nAPRPE 0x0
1433#define HDONE3 0x1000 /* DMA3 Half Done */
1434#define nHDONE3 0x0
1435#define DONE3 0x2000 /* DMA3 Done */
1436#define nDONE3 0x0
1437#define HDONE4 0x10000 /* DMA4 Half Done */
1438#define nHDONE4 0x0
1439#define DONE4 0x20000 /* DMA4 Done */
1440#define nDONE4 0x0
1441#define HDONE5 0x100000 /* DMA5 Half Done */
1442#define nHDONE5 0x0
1443#define DONE5 0x200000 /* DMA5 Done */
1444#define nDONE5 0x0
1445#define HDONE6 0x1000000 /* DMA6 Half Done */
1446#define nHDONE6 0x0
1447#define DONE6 0x2000000 /* DMA6 Done */
1448#define nDONE6 0x0
1449#define HDONE7 0x10000000 /* DMA7 Half Done */
1450#define nHDONE7 0x0
1451#define DONE7 0x20000000 /* DMA7 Done */
1452#define nDONE7 0x0
1453
1454/* Bit masks for MXVR_INT_EN_0 */
1455
1456#define NI2AEN 0x1 /* Network Inactive to Active Interrupt Enable */
1457#define nNI2AEN 0x0
1458#define NA2IEN 0x2 /* Network Active to Inactive Interrupt Enable */
1459#define nNA2IEN 0x0
1460#define SBU2LEN 0x4 /* Super Block Unlock to Lock Interrupt Enable */
1461#define nSBU2LEN 0x0
1462#define SBL2UEN 0x8 /* Super Block Lock to Unlock Interrupt Enable */
1463#define nSBL2UEN 0x0
1464#define PRUEN 0x10 /* Position Register Updated Interrupt Enable */
1465#define nPRUEN 0x0
1466#define MPRUEN 0x20 /* Maximum Position Register Updated Interrupt Enable */
1467#define nMPRUEN 0x0
1468#define DRUEN 0x40 /* Delay Register Updated Interrupt Enable */
1469#define nDRUEN 0x0
1470#define MDRUEN 0x80 /* Maximum Delay Register Updated Interrupt Enable */
1471#define nMDRUEN 0x0
1472#define SBUEN 0x100 /* Synchronous Boundary Updated Interrupt Enable */
1473#define nSBUEN 0x0
1474#define ATUEN 0x200 /* Allocation Table Updated Interrupt Enable */
1475#define nATUEN 0x0
1476#define FCZ0EN 0x400 /* Frame Counter 0 Zero Interrupt Enable */
1477#define nFCZ0EN 0x0
1478#define FCZ1EN 0x800 /* Frame Counter 1 Zero Interrupt Enable */
1479#define nFCZ1EN 0x0
1480#define PERREN 0x1000 /* Parity Error Interrupt Enable */
1481#define nPERREN 0x0
1482#define MH2LEN 0x2000 /* MRXONB High to Low Interrupt Enable */
1483#define nMH2LEN 0x0
1484#define ML2HEN 0x4000 /* MRXONB Low to High Interrupt Enable */
1485#define nML2HEN 0x0
1486#define WUPEN 0x8000 /* Wake-Up Preamble Received Interrupt Enable */
1487#define nWUPEN 0x0
1488#define FU2LEN 0x10000 /* Frame Unlock to Lock Interrupt Enable */
1489#define nFU2LEN 0x0
1490#define FL2UEN 0x20000 /* Frame Lock to Unlock Interrupt Enable */
1491#define nFL2UEN 0x0
1492#define BU2LEN 0x40000 /* Block Unlock to Lock Interrupt Enable */
1493#define nBU2LEN 0x0
1494#define BL2UEN 0x80000 /* Block Lock to Unlock Interrupt Enable */
1495#define nBL2UEN 0x0
1496#define OBERREN 0x100000 /* DMA Out of Bounds Error Interrupt Enable */
1497#define nOBERREN 0x0
1498#define PFLEN 0x200000 /* PLL Frequency Locked Interrupt Enable */
1499#define nPFLEN 0x0
1500#define SCZEN 0x400000 /* System Clock Counter Zero Interrupt Enable */
1501#define nSCZEN 0x0
1502#define FERREN 0x800000 /* FIFO Error Interrupt Enable */
1503#define nFERREN 0x0
1504#define CMREN 0x1000000 /* Control Message Received Interrupt Enable */
1505#define nCMREN 0x0
1506#define CMROFEN 0x2000000 /* Control Message Receive Buffer Overflow Interrupt Enable */
1507#define nCMROFEN 0x0
1508#define CMTSEN 0x4000000 /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
1509#define nCMTSEN 0x0
1510#define CMTCEN 0x8000000 /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
1511#define nCMTCEN 0x0
1512#define RWRCEN 0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
1513#define nRWRCEN 0x0
1514#define BCZEN 0x20000000 /* Block Counter Zero Interrupt Enable */
1515#define nBCZEN 0x0
1516#define BMERREN 0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
1517#define nBMERREN 0x0
1518#define DERREN 0x80000000 /* DMA Error Interrupt Enable */
1519#define nDERREN 0x0
1520
1521/* Bit masks for MXVR_INT_EN_1 */
1522
1523#define HDONEEN0 0x1 /* DMA0 Half Done Interrupt Enable */
1524#define nHDONEEN0 0x0
1525#define DONEEN0 0x2 /* DMA0 Done Interrupt Enable */
1526#define nDONEEN0 0x0
1527#define APREN 0x4 /* Asynchronous Packet Received Interrupt Enable */
1528#define nAPREN 0x0
1529#define APROFEN 0x8 /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
1530#define nAPROFEN 0x0
1531#define HDONEEN1 0x10 /* DMA1 Half Done Interrupt Enable */
1532#define nHDONEEN1 0x0
1533#define DONEEN1 0x20 /* DMA1 Done Interrupt Enable */
1534#define nDONEEN1 0x0
1535#define APTSEN 0x40 /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
1536#define nAPTSEN 0x0
1537#define APTCEN 0x80 /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
1538#define nAPTCEN 0x0
1539#define HDONEEN2 0x100 /* DMA2 Half Done Interrupt Enable */
1540#define nHDONEEN2 0x0
1541#define DONEEN2 0x200 /* DMA2 Done Interrupt Enable */
1542#define nDONEEN2 0x0
1543#define APRCEEN 0x400 /* Asynchronous Packet Receive CRC Error Interrupt Enable */
1544#define nAPRCEEN 0x0
1545#define APRPEEN 0x800 /* Asynchronous Packet Receive Packet Error Interrupt Enable */
1546#define nAPRPEEN 0x0
1547#define HDONEEN3 0x1000 /* DMA3 Half Done Interrupt Enable */
1548#define nHDONEEN3 0x0
1549#define DONEEN3 0x2000 /* DMA3 Done Interrupt Enable */
1550#define nDONEEN3 0x0
1551#define HDONEEN4 0x10000 /* DMA4 Half Done Interrupt Enable */
1552#define nHDONEEN4 0x0
1553#define DONEEN4 0x20000 /* DMA4 Done Interrupt Enable */
1554#define nDONEEN4 0x0
1555#define HDONEEN5 0x100000 /* DMA5 Half Done Interrupt Enable */
1556#define nHDONEEN5 0x0
1557#define DONEEN5 0x200000 /* DMA5 Done Interrupt Enable */
1558#define nDONEEN5 0x0
1559#define HDONEEN6 0x1000000 /* DMA6 Half Done Interrupt Enable */
1560#define nHDONEEN6 0x0
1561#define DONEEN6 0x2000000 /* DMA6 Done Interrupt Enable */
1562#define nDONEEN6 0x0
1563#define HDONEEN7 0x10000000 /* DMA7 Half Done Interrupt Enable */
1564#define nHDONEEN7 0x0
1565#define DONEEN7 0x20000000 /* DMA7 Done Interrupt Enable */
1566#define nDONEEN7 0x0
1567
1568/* Bit masks for MXVR_POSITION */
1569
1570#define POSITION 0x3f /* Node Position */
1571#define PVALID 0x8000 /* Node Position Valid */
1572#define nPVALID 0x0
1573
1574/* Bit masks for MXVR_MAX_POSITION */
1575
1576#define MPOSITION 0x3f /* Maximum Node Position */
1577#define MPVALID 0x8000 /* Maximum Node Position Valid */
1578#define nMPVALID 0x0
1579
1580/* Bit masks for MXVR_DELAY */
1581
1582#define DELAY 0x3f /* Node Frame Delay */
1583#define DVALID 0x8000 /* Node Frame Delay Valid */
1584#define nDVALID 0x0
1585
1586/* Bit masks for MXVR_MAX_DELAY */
1587
1588#define MDELAY 0x3f /* Maximum Node Frame Delay */
1589#define MDVALID 0x8000 /* Maximum Node Frame Delay Valid */
1590#define nMDVALID 0x0
1591
1592/* Bit masks for MXVR_LADDR */
1593
1594#define LADDR 0xffff /* Logical Address */
1595#define LVALID 0x80000000 /* Logical Address Valid */
1596#define nLVALID 0x0
1597
1598/* Bit masks for MXVR_GADDR */
1599
1600#define GADDRL 0xff /* Group Address Lower Byte */
1601#define GVALID 0x8000 /* Group Address Valid */
1602#define nGVALID 0x0
1603
1604/* Bit masks for MXVR_AADDR */
1605
1606#define AADDR 0xffff /* Alternate Address */
1607#define AVALID 0x80000000 /* Alternate Address Valid */
1608#define nAVALID 0x0
1609
1610/* Bit masks for MXVR_ALLOC_0 */
1611
1612#define CL0 0x7f /* Channel 0 Connection Label */
1613#define CIU0 0x80 /* Channel 0 In Use */
1614#define nCIU0 0x0
1615#define CL1 0x7f00 /* Channel 0 Connection Label */
1616#define CIU1 0x8000 /* Channel 0 In Use */
1617#define nCIU1 0x0
1618#define CL2 0x7f0000 /* Channel 0 Connection Label */
1619#define CIU2 0x800000 /* Channel 0 In Use */
1620#define nCIU2 0x0
1621#define CL3 0x7f000000 /* Channel 0 Connection Label */
1622#define CIU3 0x80000000 /* Channel 0 In Use */
1623#define nCIU3 0x0
1624
1625/* Bit masks for MXVR_ALLOC_1 */
1626
1627#define CL4 0x7f /* Channel 4 Connection Label */
1628#define CIU4 0x80 /* Channel 4 In Use */
1629#define nCIU4 0x0
1630#define CL5 0x7f00 /* Channel 5 Connection Label */
1631#define CIU5 0x8000 /* Channel 5 In Use */
1632#define nCIU5 0x0
1633#define CL6 0x7f0000 /* Channel 6 Connection Label */
1634#define CIU6 0x800000 /* Channel 6 In Use */
1635#define nCIU6 0x0
1636#define CL7 0x7f000000 /* Channel 7 Connection Label */
1637#define CIU7 0x80000000 /* Channel 7 In Use */
1638#define nCIU7 0x0
1639
1640/* Bit masks for MXVR_ALLOC_2 */
1641
1642#define CL8 0x7f /* Channel 8 Connection Label */
1643#define CIU8 0x80 /* Channel 8 In Use */
1644#define nCIU8 0x0
1645#define CL9 0x7f00 /* Channel 9 Connection Label */
1646#define CIU9 0x8000 /* Channel 9 In Use */
1647#define nCIU9 0x0
1648#define CL10 0x7f0000 /* Channel 10 Connection Label */
1649#define CIU10 0x800000 /* Channel 10 In Use */
1650#define nCIU10 0x0
1651#define CL11 0x7f000000 /* Channel 11 Connection Label */
1652#define CIU11 0x80000000 /* Channel 11 In Use */
1653#define nCIU11 0x0
1654
1655/* Bit masks for MXVR_ALLOC_3 */
1656
1657#define CL12 0x7f /* Channel 12 Connection Label */
1658#define CIU12 0x80 /* Channel 12 In Use */
1659#define nCIU12 0x0
1660#define CL13 0x7f00 /* Channel 13 Connection Label */
1661#define CIU13 0x8000 /* Channel 13 In Use */
1662#define nCIU13 0x0
1663#define CL14 0x7f0000 /* Channel 14 Connection Label */
1664#define CIU14 0x800000 /* Channel 14 In Use */
1665#define nCIU14 0x0
1666#define CL15 0x7f000000 /* Channel 15 Connection Label */
1667#define CIU15 0x80000000 /* Channel 15 In Use */
1668#define nCIU15 0x0
1669
1670/* Bit masks for MXVR_ALLOC_4 */
1671
1672#define CL16 0x7f /* Channel 16 Connection Label */
1673#define CIU16 0x80 /* Channel 16 In Use */
1674#define nCIU16 0x0
1675#define CL17 0x7f00 /* Channel 17 Connection Label */
1676#define CIU17 0x8000 /* Channel 17 In Use */
1677#define nCIU17 0x0
1678#define CL18 0x7f0000 /* Channel 18 Connection Label */
1679#define CIU18 0x800000 /* Channel 18 In Use */
1680#define nCIU18 0x0
1681#define CL19 0x7f000000 /* Channel 19 Connection Label */
1682#define CIU19 0x80000000 /* Channel 19 In Use */
1683#define nCIU19 0x0
1684
1685/* Bit masks for MXVR_ALLOC_5 */
1686
1687#define CL20 0x7f /* Channel 20 Connection Label */
1688#define CIU20 0x80 /* Channel 20 In Use */
1689#define nCIU20 0x0
1690#define CL21 0x7f00 /* Channel 21 Connection Label */
1691#define CIU21 0x8000 /* Channel 21 In Use */
1692#define nCIU21 0x0
1693#define CL22 0x7f0000 /* Channel 22 Connection Label */
1694#define CIU22 0x800000 /* Channel 22 In Use */
1695#define nCIU22 0x0
1696#define CL23 0x7f000000 /* Channel 23 Connection Label */
1697#define CIU23 0x80000000 /* Channel 23 In Use */
1698#define nCIU23 0x0
1699
1700/* Bit masks for MXVR_ALLOC_6 */
1701
1702#define CL24 0x7f /* Channel 24 Connection Label */
1703#define CIU24 0x80 /* Channel 24 In Use */
1704#define nCIU24 0x0
1705#define CL25 0x7f00 /* Channel 25 Connection Label */
1706#define CIU25 0x8000 /* Channel 25 In Use */
1707#define nCIU25 0x0
1708#define CL26 0x7f0000 /* Channel 26 Connection Label */
1709#define CIU26 0x800000 /* Channel 26 In Use */
1710#define nCIU26 0x0
1711#define CL27 0x7f000000 /* Channel 27 Connection Label */
1712#define CIU27 0x80000000 /* Channel 27 In Use */
1713#define nCIU27 0x0
1714
1715/* Bit masks for MXVR_ALLOC_7 */
1716
1717#define CL28 0x7f /* Channel 28 Connection Label */
1718#define CIU28 0x80 /* Channel 28 In Use */
1719#define nCIU28 0x0
1720#define CL29 0x7f00 /* Channel 29 Connection Label */
1721#define CIU29 0x8000 /* Channel 29 In Use */
1722#define nCIU29 0x0
1723#define CL30 0x7f0000 /* Channel 30 Connection Label */
1724#define CIU30 0x800000 /* Channel 30 In Use */
1725#define nCIU30 0x0
1726#define CL31 0x7f000000 /* Channel 31 Connection Label */
1727#define CIU31 0x80000000 /* Channel 31 In Use */
1728#define nCIU31 0x0
1729
1730/* Bit masks for MXVR_ALLOC_8 */
1731
1732#define CL32 0x7f /* Channel 32 Connection Label */
1733#define CIU32 0x80 /* Channel 32 In Use */
1734#define nCIU32 0x0
1735#define CL33 0x7f00 /* Channel 33 Connection Label */
1736#define CIU33 0x8000 /* Channel 33 In Use */
1737#define nCIU33 0x0
1738#define CL34 0x7f0000 /* Channel 34 Connection Label */
1739#define CIU34 0x800000 /* Channel 34 In Use */
1740#define nCIU34 0x0
1741#define CL35 0x7f000000 /* Channel 35 Connection Label */
1742#define CIU35 0x80000000 /* Channel 35 In Use */
1743#define nCIU35 0x0
1744
1745/* Bit masks for MXVR_ALLOC_9 */
1746
1747#define CL36 0x7f /* Channel 36 Connection Label */
1748#define CIU36 0x80 /* Channel 36 In Use */
1749#define nCIU36 0x0
1750#define CL37 0x7f00 /* Channel 37 Connection Label */
1751#define CIU37 0x8000 /* Channel 37 In Use */
1752#define nCIU37 0x0
1753#define CL38 0x7f0000 /* Channel 38 Connection Label */
1754#define CIU38 0x800000 /* Channel 38 In Use */
1755#define nCIU38 0x0
1756#define CL39 0x7f000000 /* Channel 39 Connection Label */
1757#define CIU39 0x80000000 /* Channel 39 In Use */
1758#define nCIU39 0x0
1759
1760/* Bit masks for MXVR_ALLOC_10 */
1761
1762#define CL40 0x7f /* Channel 40 Connection Label */
1763#define CIU40 0x80 /* Channel 40 In Use */
1764#define nCIU40 0x0
1765#define CL41 0x7f00 /* Channel 41 Connection Label */
1766#define CIU41 0x8000 /* Channel 41 In Use */
1767#define nCIU41 0x0
1768#define CL42 0x7f0000 /* Channel 42 Connection Label */
1769#define CIU42 0x800000 /* Channel 42 In Use */
1770#define nCIU42 0x0
1771#define CL43 0x7f000000 /* Channel 43 Connection Label */
1772#define CIU43 0x80000000 /* Channel 43 In Use */
1773#define nCIU43 0x0
1774
1775/* Bit masks for MXVR_ALLOC_11 */
1776
1777#define CL44 0x7f /* Channel 44 Connection Label */
1778#define CIU44 0x80 /* Channel 44 In Use */
1779#define nCIU44 0x0
1780#define CL45 0x7f00 /* Channel 45 Connection Label */
1781#define CIU45 0x8000 /* Channel 45 In Use */
1782#define nCIU45 0x0
1783#define CL46 0x7f0000 /* Channel 46 Connection Label */
1784#define CIU46 0x800000 /* Channel 46 In Use */
1785#define nCIU46 0x0
1786#define CL47 0x7f000000 /* Channel 47 Connection Label */
1787#define CIU47 0x80000000 /* Channel 47 In Use */
1788#define nCIU47 0x0
1789
1790/* Bit masks for MXVR_ALLOC_12 */
1791
1792#define CL48 0x7f /* Channel 48 Connection Label */
1793#define CIU48 0x80 /* Channel 48 In Use */
1794#define nCIU48 0x0
1795#define CL49 0x7f00 /* Channel 49 Connection Label */
1796#define CIU49 0x8000 /* Channel 49 In Use */
1797#define nCIU49 0x0
1798#define CL50 0x7f0000 /* Channel 50 Connection Label */
1799#define CIU50 0x800000 /* Channel 50 In Use */
1800#define nCIU50 0x0
1801#define CL51 0x7f000000 /* Channel 51 Connection Label */
1802#define CIU51 0x80000000 /* Channel 51 In Use */
1803#define nCIU51 0x0
1804
1805/* Bit masks for MXVR_ALLOC_13 */
1806
1807#define CL52 0x7f /* Channel 52 Connection Label */
1808#define CIU52 0x80 /* Channel 52 In Use */
1809#define nCIU52 0x0
1810#define CL53 0x7f00 /* Channel 53 Connection Label */
1811#define CIU53 0x8000 /* Channel 53 In Use */
1812#define nCIU53 0x0
1813#define CL54 0x7f0000 /* Channel 54 Connection Label */
1814#define CIU54 0x800000 /* Channel 54 In Use */
1815#define nCIU54 0x0
1816#define CL55 0x7f000000 /* Channel 55 Connection Label */
1817#define CIU55 0x80000000 /* Channel 55 In Use */
1818#define nCIU55 0x0
1819
1820/* Bit masks for MXVR_ALLOC_14 */
1821
1822#define CL56 0x7f /* Channel 56 Connection Label */
1823#define CIU56 0x80 /* Channel 56 In Use */
1824#define nCIU56 0x0
1825#define CL57 0x7f00 /* Channel 57 Connection Label */
1826#define CIU57 0x8000 /* Channel 57 In Use */
1827#define nCIU57 0x0
1828#define CL58 0x7f0000 /* Channel 58 Connection Label */
1829#define CIU58 0x800000 /* Channel 58 In Use */
1830#define nCIU58 0x0
1831#define CL59 0x7f000000 /* Channel 59 Connection Label */
1832#define CIU59 0x80000000 /* Channel 59 In Use */
1833#define nCIU59 0x0
1834
1835/* MXVR_SYNC_LCHAN_0 Masks */
1836
1837#define LCHANPC0 0x0000000Flu
1838#define LCHANPC1 0x000000F0lu
1839#define LCHANPC2 0x00000F00lu
1840#define LCHANPC3 0x0000F000lu
1841#define LCHANPC4 0x000F0000lu
1842#define LCHANPC5 0x00F00000lu
1843#define LCHANPC6 0x0F000000lu
1844#define LCHANPC7 0xF0000000lu
1845
1846
1847/* MXVR_SYNC_LCHAN_1 Masks */
1848
1849#define LCHANPC8 0x0000000Flu
1850#define LCHANPC9 0x000000F0lu
1851#define LCHANPC10 0x00000F00lu
1852#define LCHANPC11 0x0000F000lu
1853#define LCHANPC12 0x000F0000lu
1854#define LCHANPC13 0x00F00000lu
1855#define LCHANPC14 0x0F000000lu
1856#define LCHANPC15 0xF0000000lu
1857
1858
1859/* MXVR_SYNC_LCHAN_2 Masks */
1860
1861#define LCHANPC16 0x0000000Flu
1862#define LCHANPC17 0x000000F0lu
1863#define LCHANPC18 0x00000F00lu
1864#define LCHANPC19 0x0000F000lu
1865#define LCHANPC20 0x000F0000lu
1866#define LCHANPC21 0x00F00000lu
1867#define LCHANPC22 0x0F000000lu
1868#define LCHANPC23 0xF0000000lu
1869
1870
1871/* MXVR_SYNC_LCHAN_3 Masks */
1872
1873#define LCHANPC24 0x0000000Flu
1874#define LCHANPC25 0x000000F0lu
1875#define LCHANPC26 0x00000F00lu
1876#define LCHANPC27 0x0000F000lu
1877#define LCHANPC28 0x000F0000lu
1878#define LCHANPC29 0x00F00000lu
1879#define LCHANPC30 0x0F000000lu
1880#define LCHANPC31 0xF0000000lu
1881
1882
1883/* MXVR_SYNC_LCHAN_4 Masks */
1884
1885#define LCHANPC32 0x0000000Flu
1886#define LCHANPC33 0x000000F0lu
1887#define LCHANPC34 0x00000F00lu
1888#define LCHANPC35 0x0000F000lu
1889#define LCHANPC36 0x000F0000lu
1890#define LCHANPC37 0x00F00000lu
1891#define LCHANPC38 0x0F000000lu
1892#define LCHANPC39 0xF0000000lu
1893
1894
1895/* MXVR_SYNC_LCHAN_5 Masks */
1896
1897#define LCHANPC40 0x0000000Flu
1898#define LCHANPC41 0x000000F0lu
1899#define LCHANPC42 0x00000F00lu
1900#define LCHANPC43 0x0000F000lu
1901#define LCHANPC44 0x000F0000lu
1902#define LCHANPC45 0x00F00000lu
1903#define LCHANPC46 0x0F000000lu
1904#define LCHANPC47 0xF0000000lu
1905
1906
1907/* MXVR_SYNC_LCHAN_6 Masks */
1908
1909#define LCHANPC48 0x0000000Flu
1910#define LCHANPC49 0x000000F0lu
1911#define LCHANPC50 0x00000F00lu
1912#define LCHANPC51 0x0000F000lu
1913#define LCHANPC52 0x000F0000lu
1914#define LCHANPC53 0x00F00000lu
1915#define LCHANPC54 0x0F000000lu
1916#define LCHANPC55 0xF0000000lu
1917
1918
1919/* MXVR_SYNC_LCHAN_7 Masks */
1920
1921#define LCHANPC56 0x0000000Flu
1922#define LCHANPC57 0x000000F0lu
1923#define LCHANPC58 0x00000F00lu
1924#define LCHANPC59 0x0000F000lu
1925
1926/* Bit masks for MXVR_DMAx_CONFIG */
1927
1928#define MDMAEN 0x1 /* DMA Channel Enable */
1929#define nMDMAEN 0x0
1930#define DD 0x2 /* DMA Channel Direction */
1931#define nDD 0x0
1932#define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */
1933#define nBY4SWAPEN 0x0
1934#define LCHAN 0x3c0 /* DMA Channel Logical Channel */
1935#define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */
1936#define nBITSWAPEN 0x0
1937#define BY2SWAPEN 0x800 /* DMA Channel Two Byte Swap Enable */
1938#define nBY2SWAPEN 0x0
1939#define MFLOW 0x7000 /* DMA Channel Operation Flow */
1940#define FIXEDPM 0x80000 /* DMA Channel Fixed Pattern Matching Select */
1941#define nFIXEDPM 0x0
1942#define STARTPAT 0x300000 /* DMA Channel Start Pattern Select */
1943#define STOPPAT 0xc00000 /* DMA Channel Stop Pattern Select */
1944#define COUNTPOS 0x1c000000 /* DMA Channel Count Position */
1945
1946/* Bit masks for MXVR_AP_CTL */
1947
1948#define STARTAP 0x1 /* Start Asynchronous Packet Transmission */
1949#define nSTARTAP 0x0
1950#define CANCELAP 0x2 /* Cancel Asynchronous Packet Transmission */
1951#define nCANCELAP 0x0
1952#define RESETAP 0x4 /* Reset Asynchronous Packet Arbitration */
1953#define nRESETAP 0x0
1954#define APRBE0 0x4000 /* Asynchronous Packet Receive Buffer Entry 0 */
1955#define nAPRBE0 0x0
1956#define APRBE1 0x8000 /* Asynchronous Packet Receive Buffer Entry 1 */
1957#define nAPRBE1 0x0
1958
1959/* Bit masks for MXVR_APRB_START_ADDR */
1960
1961#define MXVR_APRB_START_ADDR 0x1fffffe /* Asynchronous Packet Receive Buffer Start Address */
1962
1963/* Bit masks for MXVR_APRB_CURR_ADDR */
1964
1965#define MXVR_APRB_CURR_ADDR 0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
1966
1967/* Bit masks for MXVR_APTB_START_ADDR */
1968
1969#define MXVR_APTB_START_ADDR 0x1fffffe /* Asynchronous Packet Transmit Buffer Start Address */
1970
1971/* Bit masks for MXVR_APTB_CURR_ADDR */
1972
1973#define MXVR_APTB_CURR_ADDR 0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
1974
1975/* Bit masks for MXVR_CM_CTL */
1976
1977#define STARTCM 0x1 /* Start Control Message Transmission */
1978#define nSTARTCM 0x0
1979#define CANCELCM 0x2 /* Cancel Control Message Transmission */
1980#define nCANCELCM 0x0
1981#define CMRBE0 0x10000 /* Control Message Receive Buffer Entry 0 */
1982#define nCMRBE0 0x0
1983#define CMRBE1 0x20000 /* Control Message Receive Buffer Entry 1 */
1984#define nCMRBE1 0x0
1985#define CMRBE2 0x40000 /* Control Message Receive Buffer Entry 2 */
1986#define nCMRBE2 0x0
1987#define CMRBE3 0x80000 /* Control Message Receive Buffer Entry 3 */
1988#define nCMRBE3 0x0
1989#define CMRBE4 0x100000 /* Control Message Receive Buffer Entry 4 */
1990#define nCMRBE4 0x0
1991#define CMRBE5 0x200000 /* Control Message Receive Buffer Entry 5 */
1992#define nCMRBE5 0x0
1993#define CMRBE6 0x400000 /* Control Message Receive Buffer Entry 6 */
1994#define nCMRBE6 0x0
1995#define CMRBE7 0x800000 /* Control Message Receive Buffer Entry 7 */
1996#define nCMRBE7 0x0
1997#define CMRBE8 0x1000000 /* Control Message Receive Buffer Entry 8 */
1998#define nCMRBE8 0x0
1999#define CMRBE9 0x2000000 /* Control Message Receive Buffer Entry 9 */
2000#define nCMRBE9 0x0
2001#define CMRBE10 0x4000000 /* Control Message Receive Buffer Entry 10 */
2002#define nCMRBE10 0x0
2003#define CMRBE11 0x8000000 /* Control Message Receive Buffer Entry 11 */
2004#define nCMRBE11 0x0
2005#define CMRBE12 0x10000000 /* Control Message Receive Buffer Entry 12 */
2006#define nCMRBE12 0x0
2007#define CMRBE13 0x20000000 /* Control Message Receive Buffer Entry 13 */
2008#define nCMRBE13 0x0
2009#define CMRBE14 0x40000000 /* Control Message Receive Buffer Entry 14 */
2010#define nCMRBE14 0x0
2011#define CMRBE15 0x80000000 /* Control Message Receive Buffer Entry 15 */
2012#define nCMRBE15 0x0
2013
2014/* Bit masks for MXVR_CMRB_START_ADDR */
2015
2016#define MXVR_CMRB_START_ADDR 0x1fffffe /* Control Message Receive Buffer Start Address */
2017
2018/* Bit masks for MXVR_CMRB_CURR_ADDR */
2019
2020#define MXVR_CMRB_CURR_ADDR 0xffffffff /* Control Message Receive Buffer Current Address */
2021
2022/* Bit masks for MXVR_CMTB_START_ADDR */
2023
2024#define MXVR_CMTB_START_ADDR 0x1fffffe /* Control Message Transmit Buffer Start Address */
2025
2026/* Bit masks for MXVR_CMTB_CURR_ADDR */
2027
2028#define MXVR_CMTB_CURR_ADDR 0xffffffff /* Control Message Transmit Buffer Current Address */
2029
2030/* Bit masks for MXVR_RRDB_START_ADDR */
2031
2032#define MXVR_RRDB_START_ADDR 0x1fffffe /* Remote Read Buffer Start Address */
2033
2034/* Bit masks for MXVR_RRDB_CURR_ADDR */
2035
2036#define MXVR_RRDB_CURR_ADDR 0xffffffff /* Remote Read Buffer Current Address */
2037
2038/* Bit masks for MXVR_PAT_DATAx */
2039
2040#define MATCH_DATA_0 0xff /* Pattern Match Data Byte 0 */
2041#define MATCH_DATA_1 0xff00 /* Pattern Match Data Byte 1 */
2042#define MATCH_DATA_2 0xff0000 /* Pattern Match Data Byte 2 */
2043#define MATCH_DATA_3 0xff000000 /* Pattern Match Data Byte 3 */
2044
2045/* Bit masks for MXVR_PAT_EN_0 */
2046
2047#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
2048#define nMATCH_EN_0_0 0x0
2049#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
2050#define nMATCH_EN_0_1 0x0
2051#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
2052#define nMATCH_EN_0_2 0x0
2053#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
2054#define nMATCH_EN_0_3 0x0
2055#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
2056#define nMATCH_EN_0_4 0x0
2057#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
2058#define nMATCH_EN_0_5 0x0
2059#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
2060#define nMATCH_EN_0_6 0x0
2061#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
2062#define nMATCH_EN_0_7 0x0
2063#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
2064#define nMATCH_EN_1_0 0x0
2065#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
2066#define nMATCH_EN_1_1 0x0
2067#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
2068#define nMATCH_EN_1_2 0x0
2069#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
2070#define nMATCH_EN_1_3 0x0
2071#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
2072#define nMATCH_EN_1_4 0x0
2073#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
2074#define nMATCH_EN_1_5 0x0
2075#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
2076#define nMATCH_EN_1_6 0x0
2077#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
2078#define nMATCH_EN_1_7 0x0
2079#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
2080#define nMATCH_EN_2_0 0x0
2081#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
2082#define nMATCH_EN_2_1 0x0
2083#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
2084#define nMATCH_EN_2_2 0x0
2085#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
2086#define nMATCH_EN_2_3 0x0
2087#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
2088#define nMATCH_EN_2_4 0x0
2089#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
2090#define nMATCH_EN_2_5 0x0
2091#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
2092#define nMATCH_EN_2_6 0x0
2093#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
2094#define nMATCH_EN_2_7 0x0
2095#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
2096#define nMATCH_EN_3_0 0x0
2097#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
2098#define nMATCH_EN_3_1 0x0
2099#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
2100#define nMATCH_EN_3_2 0x0
2101#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
2102#define nMATCH_EN_3_3 0x0
2103#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
2104#define nMATCH_EN_3_4 0x0
2105#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
2106#define nMATCH_EN_3_5 0x0
2107#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
2108#define nMATCH_EN_3_6 0x0
2109#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
2110#define nMATCH_EN_3_7 0x0
2111
2112/* Bit masks for MXVR_PAT_EN_1 */
2113
2114#define MATCH_EN_0_0 0x1 /* Pattern Match Enable Byte 0 Bit 0 */
2115#define nMATCH_EN_0_0 0x0
2116#define MATCH_EN_0_1 0x2 /* Pattern Match Enable Byte 0 Bit 1 */
2117#define nMATCH_EN_0_1 0x0
2118#define MATCH_EN_0_2 0x4 /* Pattern Match Enable Byte 0 Bit 2 */
2119#define nMATCH_EN_0_2 0x0
2120#define MATCH_EN_0_3 0x8 /* Pattern Match Enable Byte 0 Bit 3 */
2121#define nMATCH_EN_0_3 0x0
2122#define MATCH_EN_0_4 0x10 /* Pattern Match Enable Byte 0 Bit 4 */
2123#define nMATCH_EN_0_4 0x0
2124#define MATCH_EN_0_5 0x20 /* Pattern Match Enable Byte 0 Bit 5 */
2125#define nMATCH_EN_0_5 0x0
2126#define MATCH_EN_0_6 0x40 /* Pattern Match Enable Byte 0 Bit 6 */
2127#define nMATCH_EN_0_6 0x0
2128#define MATCH_EN_0_7 0x80 /* Pattern Match Enable Byte 0 Bit 7 */
2129#define nMATCH_EN_0_7 0x0
2130#define MATCH_EN_1_0 0x100 /* Pattern Match Enable Byte 1 Bit 0 */
2131#define nMATCH_EN_1_0 0x0
2132#define MATCH_EN_1_1 0x200 /* Pattern Match Enable Byte 1 Bit 1 */
2133#define nMATCH_EN_1_1 0x0
2134#define MATCH_EN_1_2 0x400 /* Pattern Match Enable Byte 1 Bit 2 */
2135#define nMATCH_EN_1_2 0x0
2136#define MATCH_EN_1_3 0x800 /* Pattern Match Enable Byte 1 Bit 3 */
2137#define nMATCH_EN_1_3 0x0
2138#define MATCH_EN_1_4 0x1000 /* Pattern Match Enable Byte 1 Bit 4 */
2139#define nMATCH_EN_1_4 0x0
2140#define MATCH_EN_1_5 0x2000 /* Pattern Match Enable Byte 1 Bit 5 */
2141#define nMATCH_EN_1_5 0x0
2142#define MATCH_EN_1_6 0x4000 /* Pattern Match Enable Byte 1 Bit 6 */
2143#define nMATCH_EN_1_6 0x0
2144#define MATCH_EN_1_7 0x8000 /* Pattern Match Enable Byte 1 Bit 7 */
2145#define nMATCH_EN_1_7 0x0
2146#define MATCH_EN_2_0 0x10000 /* Pattern Match Enable Byte 2 Bit 0 */
2147#define nMATCH_EN_2_0 0x0
2148#define MATCH_EN_2_1 0x20000 /* Pattern Match Enable Byte 2 Bit 1 */
2149#define nMATCH_EN_2_1 0x0
2150#define MATCH_EN_2_2 0x40000 /* Pattern Match Enable Byte 2 Bit 2 */
2151#define nMATCH_EN_2_2 0x0
2152#define MATCH_EN_2_3 0x80000 /* Pattern Match Enable Byte 2 Bit 3 */
2153#define nMATCH_EN_2_3 0x0
2154#define MATCH_EN_2_4 0x100000 /* Pattern Match Enable Byte 2 Bit 4 */
2155#define nMATCH_EN_2_4 0x0
2156#define MATCH_EN_2_5 0x200000 /* Pattern Match Enable Byte 2 Bit 5 */
2157#define nMATCH_EN_2_5 0x0
2158#define MATCH_EN_2_6 0x400000 /* Pattern Match Enable Byte 2 Bit 6 */
2159#define nMATCH_EN_2_6 0x0
2160#define MATCH_EN_2_7 0x800000 /* Pattern Match Enable Byte 2 Bit 7 */
2161#define nMATCH_EN_2_7 0x0
2162#define MATCH_EN_3_0 0x1000000 /* Pattern Match Enable Byte 3 Bit 0 */
2163#define nMATCH_EN_3_0 0x0
2164#define MATCH_EN_3_1 0x2000000 /* Pattern Match Enable Byte 3 Bit 1 */
2165#define nMATCH_EN_3_1 0x0
2166#define MATCH_EN_3_2 0x4000000 /* Pattern Match Enable Byte 3 Bit 2 */
2167#define nMATCH_EN_3_2 0x0
2168#define MATCH_EN_3_3 0x8000000 /* Pattern Match Enable Byte 3 Bit 3 */
2169#define nMATCH_EN_3_3 0x0
2170#define MATCH_EN_3_4 0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
2171#define nMATCH_EN_3_4 0x0
2172#define MATCH_EN_3_5 0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
2173#define nMATCH_EN_3_5 0x0
2174#define MATCH_EN_3_6 0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
2175#define nMATCH_EN_3_6 0x0
2176#define MATCH_EN_3_7 0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
2177#define nMATCH_EN_3_7 0x0
2178
2179/* Bit masks for MXVR_FRAME_CNT_0 */
2180
2181#define FCNT 0xffff /* Frame Count */
2182
2183/* Bit masks for MXVR_FRAME_CNT_1 */
2184
2185#define FCNT 0xffff /* Frame Count */
2186
2187/* Bit masks for MXVR_ROUTING_0 */
2188
2189#define TX_CH0 0x3f /* Transmit Channel 0 */
2190#define MUTE_CH0 0x80 /* Mute Channel 0 */
2191#define nMUTE_CH0 0x0
2192#define TX_CH1 0x3f00 /* Transmit Channel 0 */
2193#define MUTE_CH1 0x8000 /* Mute Channel 0 */
2194#define nMUTE_CH1 0x0
2195#define TX_CH2 0x3f0000 /* Transmit Channel 0 */
2196#define MUTE_CH2 0x800000 /* Mute Channel 0 */
2197#define nMUTE_CH2 0x0
2198#define TX_CH3 0x3f000000 /* Transmit Channel 0 */
2199#define MUTE_CH3 0x80000000 /* Mute Channel 0 */
2200#define nMUTE_CH3 0x0
2201
2202/* Bit masks for MXVR_ROUTING_1 */
2203
2204#define TX_CH4 0x3f /* Transmit Channel 4 */
2205#define MUTE_CH4 0x80 /* Mute Channel 4 */
2206#define nMUTE_CH4 0x0
2207#define TX_CH5 0x3f00 /* Transmit Channel 5 */
2208#define MUTE_CH5 0x8000 /* Mute Channel 5 */
2209#define nMUTE_CH5 0x0
2210#define TX_CH6 0x3f0000 /* Transmit Channel 6 */
2211#define MUTE_CH6 0x800000 /* Mute Channel 6 */
2212#define nMUTE_CH6 0x0
2213#define TX_CH7 0x3f000000 /* Transmit Channel 7 */
2214#define MUTE_CH7 0x80000000 /* Mute Channel 7 */
2215#define nMUTE_CH7 0x0
2216
2217/* Bit masks for MXVR_ROUTING_2 */
2218
2219#define TX_CH8 0x3f /* Transmit Channel 8 */
2220#define MUTE_CH8 0x80 /* Mute Channel 8 */
2221#define nMUTE_CH8 0x0
2222#define TX_CH9 0x3f00 /* Transmit Channel 9 */
2223#define MUTE_CH9 0x8000 /* Mute Channel 9 */
2224#define nMUTE_CH9 0x0
2225#define TX_CH10 0x3f0000 /* Transmit Channel 10 */
2226#define MUTE_CH10 0x800000 /* Mute Channel 10 */
2227#define nMUTE_CH10 0x0
2228#define TX_CH11 0x3f000000 /* Transmit Channel 11 */
2229#define MUTE_CH11 0x80000000 /* Mute Channel 11 */
2230#define nMUTE_CH11 0x0
2231
2232/* Bit masks for MXVR_ROUTING_3 */
2233
2234#define TX_CH12 0x3f /* Transmit Channel 12 */
2235#define MUTE_CH12 0x80 /* Mute Channel 12 */
2236#define nMUTE_CH12 0x0
2237#define TX_CH13 0x3f00 /* Transmit Channel 13 */
2238#define MUTE_CH13 0x8000 /* Mute Channel 13 */
2239#define nMUTE_CH13 0x0
2240#define TX_CH14 0x3f0000 /* Transmit Channel 14 */
2241#define MUTE_CH14 0x800000 /* Mute Channel 14 */
2242#define nMUTE_CH14 0x0
2243#define TX_CH15 0x3f000000 /* Transmit Channel 15 */
2244#define MUTE_CH15 0x80000000 /* Mute Channel 15 */
2245#define nMUTE_CH15 0x0
2246
2247/* Bit masks for MXVR_ROUTING_4 */
2248
2249#define TX_CH16 0x3f /* Transmit Channel 16 */
2250#define MUTE_CH16 0x80 /* Mute Channel 16 */
2251#define nMUTE_CH16 0x0
2252#define TX_CH17 0x3f00 /* Transmit Channel 17 */
2253#define MUTE_CH17 0x8000 /* Mute Channel 17 */
2254#define nMUTE_CH17 0x0
2255#define TX_CH18 0x3f0000 /* Transmit Channel 18 */
2256#define MUTE_CH18 0x800000 /* Mute Channel 18 */
2257#define nMUTE_CH18 0x0
2258#define TX_CH19 0x3f000000 /* Transmit Channel 19 */
2259#define MUTE_CH19 0x80000000 /* Mute Channel 19 */
2260#define nMUTE_CH19 0x0
2261
2262/* Bit masks for MXVR_ROUTING_5 */
2263
2264#define TX_CH20 0x3f /* Transmit Channel 20 */
2265#define MUTE_CH20 0x80 /* Mute Channel 20 */
2266#define nMUTE_CH20 0x0
2267#define TX_CH21 0x3f00 /* Transmit Channel 21 */
2268#define MUTE_CH21 0x8000 /* Mute Channel 21 */
2269#define nMUTE_CH21 0x0
2270#define TX_CH22 0x3f0000 /* Transmit Channel 22 */
2271#define MUTE_CH22 0x800000 /* Mute Channel 22 */
2272#define nMUTE_CH22 0x0
2273#define TX_CH23 0x3f000000 /* Transmit Channel 23 */
2274#define MUTE_CH23 0x80000000 /* Mute Channel 23 */
2275#define nMUTE_CH23 0x0
2276
2277/* Bit masks for MXVR_ROUTING_6 */
2278
2279#define TX_CH24 0x3f /* Transmit Channel 24 */
2280#define MUTE_CH24 0x80 /* Mute Channel 24 */
2281#define nMUTE_CH24 0x0
2282#define TX_CH25 0x3f00 /* Transmit Channel 25 */
2283#define MUTE_CH25 0x8000 /* Mute Channel 25 */
2284#define nMUTE_CH25 0x0
2285#define TX_CH26 0x3f0000 /* Transmit Channel 26 */
2286#define MUTE_CH26 0x800000 /* Mute Channel 26 */
2287#define nMUTE_CH26 0x0
2288#define TX_CH27 0x3f000000 /* Transmit Channel 27 */
2289#define MUTE_CH27 0x80000000 /* Mute Channel 27 */
2290#define nMUTE_CH27 0x0
2291
2292/* Bit masks for MXVR_ROUTING_7 */
2293
2294#define TX_CH28 0x3f /* Transmit Channel 28 */
2295#define MUTE_CH28 0x80 /* Mute Channel 28 */
2296#define nMUTE_CH28 0x0
2297#define TX_CH29 0x3f00 /* Transmit Channel 29 */
2298#define MUTE_CH29 0x8000 /* Mute Channel 29 */
2299#define nMUTE_CH29 0x0
2300#define TX_CH30 0x3f0000 /* Transmit Channel 30 */
2301#define MUTE_CH30 0x800000 /* Mute Channel 30 */
2302#define nMUTE_CH30 0x0
2303#define TX_CH31 0x3f000000 /* Transmit Channel 31 */
2304#define MUTE_CH31 0x80000000 /* Mute Channel 31 */
2305#define nMUTE_CH31 0x0
2306
2307/* Bit masks for MXVR_ROUTING_8 */
2308
2309#define TX_CH32 0x3f /* Transmit Channel 32 */
2310#define MUTE_CH32 0x80 /* Mute Channel 32 */
2311#define nMUTE_CH32 0x0
2312#define TX_CH33 0x3f00 /* Transmit Channel 33 */
2313#define MUTE_CH33 0x8000 /* Mute Channel 33 */
2314#define nMUTE_CH33 0x0
2315#define TX_CH34 0x3f0000 /* Transmit Channel 34 */
2316#define MUTE_CH34 0x800000 /* Mute Channel 34 */
2317#define nMUTE_CH34 0x0
2318#define TX_CH35 0x3f000000 /* Transmit Channel 35 */
2319#define MUTE_CH35 0x80000000 /* Mute Channel 35 */
2320#define nMUTE_CH35 0x0
2321
2322/* Bit masks for MXVR_ROUTING_9 */
2323
2324#define TX_CH36 0x3f /* Transmit Channel 36 */
2325#define MUTE_CH36 0x80 /* Mute Channel 36 */
2326#define nMUTE_CH36 0x0
2327#define TX_CH37 0x3f00 /* Transmit Channel 37 */
2328#define MUTE_CH37 0x8000 /* Mute Channel 37 */
2329#define nMUTE_CH37 0x0
2330#define TX_CH38 0x3f0000 /* Transmit Channel 38 */
2331#define MUTE_CH38 0x800000 /* Mute Channel 38 */
2332#define nMUTE_CH38 0x0
2333#define TX_CH39 0x3f000000 /* Transmit Channel 39 */
2334#define MUTE_CH39 0x80000000 /* Mute Channel 39 */
2335#define nMUTE_CH39 0x0
2336
2337/* Bit masks for MXVR_ROUTING_10 */
2338
2339#define TX_CH40 0x3f /* Transmit Channel 40 */
2340#define MUTE_CH40 0x80 /* Mute Channel 40 */
2341#define nMUTE_CH40 0x0
2342#define TX_CH41 0x3f00 /* Transmit Channel 41 */
2343#define MUTE_CH41 0x8000 /* Mute Channel 41 */
2344#define nMUTE_CH41 0x0
2345#define TX_CH42 0x3f0000 /* Transmit Channel 42 */
2346#define MUTE_CH42 0x800000 /* Mute Channel 42 */
2347#define nMUTE_CH42 0x0
2348#define TX_CH43 0x3f000000 /* Transmit Channel 43 */
2349#define MUTE_CH43 0x80000000 /* Mute Channel 43 */
2350#define nMUTE_CH43 0x0
2351
2352/* Bit masks for MXVR_ROUTING_11 */
2353
2354#define TX_CH44 0x3f /* Transmit Channel 44 */
2355#define MUTE_CH44 0x80 /* Mute Channel 44 */
2356#define nMUTE_CH44 0x0
2357#define TX_CH45 0x3f00 /* Transmit Channel 45 */
2358#define MUTE_CH45 0x8000 /* Mute Channel 45 */
2359#define nMUTE_CH45 0x0
2360#define TX_CH46 0x3f0000 /* Transmit Channel 46 */
2361#define MUTE_CH46 0x800000 /* Mute Channel 46 */
2362#define nMUTE_CH46 0x0
2363#define TX_CH47 0x3f000000 /* Transmit Channel 47 */
2364#define MUTE_CH47 0x80000000 /* Mute Channel 47 */
2365#define nMUTE_CH47 0x0
2366
2367/* Bit masks for MXVR_ROUTING_12 */
2368
2369#define TX_CH48 0x3f /* Transmit Channel 48 */
2370#define MUTE_CH48 0x80 /* Mute Channel 48 */
2371#define nMUTE_CH48 0x0
2372#define TX_CH49 0x3f00 /* Transmit Channel 49 */
2373#define MUTE_CH49 0x8000 /* Mute Channel 49 */
2374#define nMUTE_CH49 0x0
2375#define TX_CH50 0x3f0000 /* Transmit Channel 50 */
2376#define MUTE_CH50 0x800000 /* Mute Channel 50 */
2377#define nMUTE_CH50 0x0
2378#define TX_CH51 0x3f000000 /* Transmit Channel 51 */
2379#define MUTE_CH51 0x80000000 /* Mute Channel 51 */
2380#define nMUTE_CH51 0x0
2381
2382/* Bit masks for MXVR_ROUTING_13 */
2383
2384#define TX_CH52 0x3f /* Transmit Channel 52 */
2385#define MUTE_CH52 0x80 /* Mute Channel 52 */
2386#define nMUTE_CH52 0x0
2387#define TX_CH53 0x3f00 /* Transmit Channel 53 */
2388#define MUTE_CH53 0x8000 /* Mute Channel 53 */
2389#define nMUTE_CH53 0x0
2390#define TX_CH54 0x3f0000 /* Transmit Channel 54 */
2391#define MUTE_CH54 0x800000 /* Mute Channel 54 */
2392#define nMUTE_CH54 0x0
2393#define TX_CH55 0x3f000000 /* Transmit Channel 55 */
2394#define MUTE_CH55 0x80000000 /* Mute Channel 55 */
2395#define nMUTE_CH55 0x0
2396
2397/* Bit masks for MXVR_ROUTING_14 */
2398
2399#define TX_CH56 0x3f /* Transmit Channel 56 */
2400#define MUTE_CH56 0x80 /* Mute Channel 56 */
2401#define nMUTE_CH56 0x0
2402#define TX_CH57 0x3f00 /* Transmit Channel 57 */
2403#define MUTE_CH57 0x8000 /* Mute Channel 57 */
2404#define nMUTE_CH57 0x0
2405#define TX_CH58 0x3f0000 /* Transmit Channel 58 */
2406#define MUTE_CH58 0x800000 /* Mute Channel 58 */
2407#define nMUTE_CH58 0x0
2408#define TX_CH59 0x3f000000 /* Transmit Channel 59 */
2409#define MUTE_CH59 0x80000000 /* Mute Channel 59 */
2410#define nMUTE_CH59 0x0
2411
2412/* Bit masks for MXVR_BLOCK_CNT */
2413
2414#define BCNT 0xffff /* Block Count */
2415
2416/* Bit masks for MXVR_CLK_CTL */
2417
2418#define MXTALCEN 0x1 /* MXVR Crystal Oscillator Clock Enable */
2419#define nMXTALCEN 0x0
2420#define MXTALFEN 0x2 /* MXVR Crystal Oscillator Feedback Enable */
2421#define nMXTALFEN 0x0
2422#define MXTALMUL 0x30 /* MXVR Crystal Multiplier */
2423#define CLKX3SEL 0x80 /* Clock Generation Source Select */
2424#define nCLKX3SEL 0x0
2425#define MMCLKEN 0x100 /* Master Clock Enable */
2426#define nMMCLKEN 0x0
2427#define MMCLKMUL 0x1e00 /* Master Clock Multiplication Factor */
2428#define PLLSMPS 0xe000 /* MXVR PLL State Machine Prescaler */
2429#define MBCLKEN 0x10000 /* Bit Clock Enable */
2430#define nMBCLKEN 0x0
2431#define MBCLKDIV 0x1e0000 /* Bit Clock Divide Factor */
2432#define INVRX 0x800000 /* Invert Receive Data */
2433#define nINVRX 0x0
2434#define MFSEN 0x1000000 /* Frame Sync Enable */
2435#define nMFSEN 0x0
2436#define MFSDIV 0x1e000000 /* Frame Sync Divide Factor */
2437#define MFSSEL 0x60000000 /* Frame Sync Select */
2438#define MFSSYNC 0x80000000 /* Frame Sync Synchronization Select */
2439#define nMFSSYNC 0x0
2440
2441/* Bit masks for MXVR_CDRPLL_CTL */
2442
2443#define CDRSMEN 0x1 /* MXVR CDRPLL State Machine Enable */
2444#define nCDRSMEN 0x0
2445#define CDRRSTB 0x2 /* MXVR CDRPLL Reset */
2446#define nCDRRSTB 0x0
2447#define CDRSVCO 0x4 /* MXVR CDRPLL Start VCO */
2448#define nCDRSVCO 0x0
2449#define CDRMODE 0x8 /* MXVR CDRPLL CDR Mode Select */
2450#define nCDRMODE 0x0
2451#define CDRSCNT 0x3f0 /* MXVR CDRPLL Start Counter */
2452#define CDRLCNT 0xfc00 /* MXVR CDRPLL Lock Counter */
2453#define CDRSHPSEL 0x3f0000 /* MXVR CDRPLL Shaper Select */
2454#define CDRSHPEN 0x800000 /* MXVR CDRPLL Shaper Enable */
2455#define nCDRSHPEN 0x0
2456#define CDRCPSEL 0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
2457
2458/* Bit masks for MXVR_FMPLL_CTL */
2459
2460#define FMSMEN 0x1 /* MXVR FMPLL State Machine Enable */
2461#define nFMSMEN 0x0
2462#define FMRSTB 0x2 /* MXVR FMPLL Reset */
2463#define nFMRSTB 0x0
2464#define FMSVCO 0x4 /* MXVR FMPLL Start VCO */
2465#define nFMSVCO 0x0
2466#define FMSCNT 0x3f0 /* MXVR FMPLL Start Counter */
2467#define FMLCNT 0xfc00 /* MXVR FMPLL Lock Counter */
2468#define FMCPSEL 0xff000000 /* MXVR FMPLL Charge Pump Current Select */
2469
2470/* Bit masks for MXVR_PIN_CTL */
2471
2472#define MTXONBOD 0x1 /* MTXONB Open Drain Select */
2473#define nMTXONBOD 0x0
2474#define MTXONBG 0x2 /* MTXONB Gates MTX Select */
2475#define nMTXONBG 0x0
2476#define MFSOE 0x10 /* MFS Output Enable */
2477#define nMFSOE 0x0
2478#define MFSGPSEL 0x20 /* MFS General Purpose Output Select */
2479#define nMFSGPSEL 0x0
2480#define MFSGPDAT 0x40 /* MFS General Purpose Output Data */
2481#define nMFSGPDAT 0x0
2482
2483/* Bit masks for MXVR_SCLK_CNT */
2484
2485#define SCNT 0xffff /* System Clock Count */
2486
2487/* Bit masks for KPAD_CTL */
2488
2489#define KPAD_EN 0x1 /* Keypad Enable */
2490#define nKPAD_EN 0x0
2491#define KPAD_IRQMODE 0x6 /* Key Press Interrupt Enable */
2492#define KPAD_ROWEN 0x1c00 /* Row Enable Width */
2493#define KPAD_COLEN 0xe000 /* Column Enable Width */
2494
2495/* Bit masks for KPAD_PRESCALE */
2496
2497#define KPAD_PRESCALE_VAL 0x3f /* Key Prescale Value */
2498
2499/* Bit masks for KPAD_MSEL */
2500
2501#define DBON_SCALE 0xff /* Debounce Scale Value */
2502#define COLDRV_SCALE 0xff00 /* Column Driver Scale Value */
2503
2504/* Bit masks for KPAD_ROWCOL */
2505
2506#define KPAD_ROW 0xff /* Rows Pressed */
2507#define KPAD_COL 0xff00 /* Columns Pressed */
2508
2509/* Bit masks for KPAD_STAT */
2510
2511#define KPAD_IRQ 0x1 /* Keypad Interrupt Status */
2512#define nKPAD_IRQ 0x0
2513#define KPAD_MROWCOL 0x6 /* Multiple Row/Column Keypress Status */
2514#define KPAD_PRESSED 0x8 /* Key press current status */
2515#define nKPAD_PRESSED 0x0
2516
2517/* Bit masks for KPAD_SOFTEVAL */
2518
2519#define KPAD_SOFTEVAL_E 0x2 /* Software Programmable Force Evaluate */
2520#define nKPAD_SOFTEVAL_E 0x0
2521
2522/* Bit masks for SDH_COMMAND */
2523
2524#define CMD_IDX 0x3f /* Command Index */
2525#define CMD_RSP 0x40 /* Response */
2526#define nCMD_RSP 0x0
2527#define CMD_L_RSP 0x80 /* Long Response */
2528#define nCMD_L_RSP 0x0
2529#define CMD_INT_E 0x100 /* Command Interrupt */
2530#define nCMD_INT_E 0x0
2531#define CMD_PEND_E 0x200 /* Command Pending */
2532#define nCMD_PEND_E 0x0
2533#define CMD_E 0x400 /* Command Enable */
2534#define nCMD_E 0x0
2535
2536/* Bit masks for SDH_PWR_CTL */
2537
2538#define PWR_ON 0x3 /* Power On */
2539#if 0
2540#define TBD 0x3c /* TBD */
2541#endif
2542#define SD_CMD_OD 0x40 /* Open Drain Output */
2543#define nSD_CMD_OD 0x0
2544#define ROD_CTL 0x80 /* Rod Control */
2545#define nROD_CTL 0x0
2546
2547/* Bit masks for SDH_CLK_CTL */
2548
2549#define CLKDIV 0xff /* MC_CLK Divisor */
2550#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
2551#define nCLK_E 0x0
2552#define PWR_SV_E 0x200 /* Power Save Enable */
2553#define nPWR_SV_E 0x0
2554#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
2555#define nCLKDIV_BYPASS 0x0
2556#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
2557#define nWIDE_BUS 0x0
2558
2559/* Bit masks for SDH_RESP_CMD */
2560
2561#define RESP_CMD 0x3f /* Response Command */
2562
2563/* Bit masks for SDH_DATA_CTL */
2564
2565#define DTX_E 0x1 /* Data Transfer Enable */
2566#define nDTX_E 0x0
2567#define DTX_DIR 0x2 /* Data Transfer Direction */
2568#define nDTX_DIR 0x0
2569#define DTX_MODE 0x4 /* Data Transfer Mode */
2570#define nDTX_MODE 0x0
2571#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
2572#define nDTX_DMA_E 0x0
2573#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
2574
2575/* Bit masks for SDH_STATUS */
2576
2577#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
2578#define nCMD_CRC_FAIL 0x0
2579#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
2580#define nDAT_CRC_FAIL 0x0
2581#define CMD_TIMEOUT 0x4 /* CMD Time Out */
2582#define nCMD_TIMEOUT 0x0
2583#define DAT_TIMEOUT 0x8 /* Data Time Out */
2584#define nDAT_TIMEOUT 0x0
2585#define TX_UNDERRUN 0x10 /* Transmit Underrun */
2586#define nTX_UNDERRUN 0x0
2587#define RX_OVERRUN 0x20 /* Receive Overrun */
2588#define nRX_OVERRUN 0x0
2589#define CMD_RESP_END 0x40 /* CMD Response End */
2590#define nCMD_RESP_END 0x0
2591#define CMD_SENT 0x80 /* CMD Sent */
2592#define nCMD_SENT 0x0
2593#define DAT_END 0x100 /* Data End */
2594#define nDAT_END 0x0
2595#define START_BIT_ERR 0x200 /* Start Bit Error */
2596#define nSTART_BIT_ERR 0x0
2597#define DAT_BLK_END 0x400 /* Data Block End */
2598#define nDAT_BLK_END 0x0
2599#define CMD_ACT 0x800 /* CMD Active */
2600#define nCMD_ACT 0x0
2601#define TX_ACT 0x1000 /* Transmit Active */
2602#define nTX_ACT 0x0
2603#define RX_ACT 0x2000 /* Receive Active */
2604#define nRX_ACT 0x0
2605#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
2606#define nTX_FIFO_STAT 0x0
2607#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
2608#define nRX_FIFO_STAT 0x0
2609#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
2610#define nTX_FIFO_FULL 0x0
2611#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
2612#define nRX_FIFO_FULL 0x0
2613#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
2614#define nTX_FIFO_ZERO 0x0
2615#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
2616#define nRX_DAT_ZERO 0x0
2617#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
2618#define nTX_DAT_RDY 0x0
2619#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
2620#define nRX_FIFO_RDY 0x0
2621
2622/* Bit masks for SDH_STATUS_CLR */
2623
2624#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
2625#define nCMD_CRC_FAIL_STAT 0x0
2626#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
2627#define nDAT_CRC_FAIL_STAT 0x0
2628#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
2629#define nCMD_TIMEOUT_STAT 0x0
2630#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
2631#define nDAT_TIMEOUT_STAT 0x0
2632#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
2633#define nTX_UNDERRUN_STAT 0x0
2634#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
2635#define nRX_OVERRUN_STAT 0x0
2636#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
2637#define nCMD_RESP_END_STAT 0x0
2638#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
2639#define nCMD_SENT_STAT 0x0
2640#define DAT_END_STAT 0x100 /* Data End Status */
2641#define nDAT_END_STAT 0x0
2642#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
2643#define nSTART_BIT_ERR_STAT 0x0
2644#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
2645#define nDAT_BLK_END_STAT 0x0
2646
2647/* Bit masks for SDH_MASK0 */
2648
2649#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
2650#define nCMD_CRC_FAIL_MASK 0x0
2651#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
2652#define nDAT_CRC_FAIL_MASK 0x0
2653#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
2654#define nCMD_TIMEOUT_MASK 0x0
2655#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
2656#define nDAT_TIMEOUT_MASK 0x0
2657#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
2658#define nTX_UNDERRUN_MASK 0x0
2659#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
2660#define nRX_OVERRUN_MASK 0x0
2661#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
2662#define nCMD_RESP_END_MASK 0x0
2663#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
2664#define nCMD_SENT_MASK 0x0
2665#define DAT_END_MASK 0x100 /* Data End Mask */
2666#define nDAT_END_MASK 0x0
2667#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
2668#define nSTART_BIT_ERR_MASK 0x0
2669#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
2670#define nDAT_BLK_END_MASK 0x0
2671#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
2672#define nCMD_ACT_MASK 0x0
2673#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
2674#define nTX_ACT_MASK 0x0
2675#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
2676#define nRX_ACT_MASK 0x0
2677#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
2678#define nTX_FIFO_STAT_MASK 0x0
2679#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
2680#define nRX_FIFO_STAT_MASK 0x0
2681#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
2682#define nTX_FIFO_FULL_MASK 0x0
2683#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
2684#define nRX_FIFO_FULL_MASK 0x0
2685#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
2686#define nTX_FIFO_ZERO_MASK 0x0
2687#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
2688#define nRX_DAT_ZERO_MASK 0x0
2689#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
2690#define nTX_DAT_RDY_MASK 0x0
2691#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
2692#define nRX_FIFO_RDY_MASK 0x0
2693
2694/* Bit masks for SDH_FIFO_CNT */
2695
2696#define FIFO_COUNT 0x7fff /* FIFO Count */
2697
2698/* Bit masks for SDH_E_STATUS */
2699
2700#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
2701#define nSDIO_INT_DET 0x0
2702#define SD_CARD_DET 0x10 /* SD Card Detect */
2703#define nSD_CARD_DET 0x0
2704
2705/* Bit masks for SDH_E_MASK */
2706
2707#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
2708#define nSDIO_MSK 0x0
2709#define SCD_MSK 0x40 /* Mask Card Detect */
2710#define nSCD_MSK 0x0
2711
2712/* Bit masks for SDH_CFG */
2713
2714#define CLKS_EN 0x1 /* Clocks Enable */
2715#define nCLKS_EN 0x0
2716#define SD4E 0x4 /* SDIO 4-Bit Enable */
2717#define nSD4E 0x0
2718#define MWE 0x8 /* Moving Window Enable */
2719#define nMWE 0x0
2720#define SD_RST 0x10 /* SDMMC Reset */
2721#define nSD_RST 0x0
2722#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
2723#define nPUP_SDDAT 0x0
2724#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
2725#define nPUP_SDDAT3 0x0
2726#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
2727#define nPD_SDDAT3 0x0
2728
2729/* Bit masks for SDH_RD_WAIT_EN */
2730
2731#define RWR 0x1 /* Read Wait Request */
2732#define nRWR 0x0
2733
2734/* Bit masks for ATAPI_CONTROL */
2735
2736#define PIO_START 0x1 /* Start PIO/Reg Op */
2737#define nPIO_START 0x0
2738#define MULTI_START 0x2 /* Start Multi-DMA Op */
2739#define nMULTI_START 0x0
2740#define ULTRA_START 0x4 /* Start Ultra-DMA Op */
2741#define nULTRA_START 0x0
2742#define XFER_DIR 0x8 /* Transfer Direction */
2743#define nXFER_DIR 0x0
2744#define IORDY_EN 0x10 /* IORDY Enable */
2745#define nIORDY_EN 0x0
2746#define FIFO_FLUSH 0x20 /* Flush FIFOs */
2747#define nFIFO_FLUSH 0x0
2748#define SOFT_RST 0x40 /* Soft Reset */
2749#define nSOFT_RST 0x0
2750#define DEV_RST 0x80 /* Device Reset */
2751#define nDEV_RST 0x0
2752#define TFRCNT_RST 0x100 /* Trans Count Reset */
2753#define nTFRCNT_RST 0x0
2754#define END_ON_TERM 0x200 /* End/Terminate Select */
2755#define nEND_ON_TERM 0x0
2756#define PIO_USE_DMA 0x400 /* PIO-DMA Enable */
2757#define nPIO_USE_DMA 0x0
2758#define UDMAIN_FIFO_THRS 0xf000 /* Ultra DMA-IN FIFO Threshold */
2759
2760/* Bit masks for ATAPI_STATUS */
2761
2762#define PIO_XFER_ON 0x1 /* PIO transfer in progress */
2763#define nPIO_XFER_ON 0x0
2764#define MULTI_XFER_ON 0x2 /* Multi-word DMA transfer in progress */
2765#define nMULTI_XFER_ON 0x0
2766#define ULTRA_XFER_ON 0x4 /* Ultra DMA transfer in progress */
2767#define nULTRA_XFER_ON 0x0
2768#define ULTRA_IN_FL 0xf0 /* Ultra DMA Input FIFO Level */
2769
2770/* Bit masks for ATAPI_DEV_ADDR */
2771
2772#define DEV_ADDR 0x1f /* Device Address */
2773
2774/* Bit masks for ATAPI_INT_MASK */
2775
2776#define ATAPI_DEV_INT_MASK 0x1 /* Device interrupt mask */
2777#define nATAPI_DEV_INT_MASK 0x0
2778#define PIO_DONE_MASK 0x2 /* PIO transfer done interrupt mask */
2779#define nPIO_DONE_MASK 0x0
2780#define MULTI_DONE_MASK 0x4 /* Multi-DMA transfer done interrupt mask */
2781#define nMULTI_DONE_MASK 0x0
2782#define UDMAIN_DONE_MASK 0x8 /* Ultra-DMA in transfer done interrupt mask */
2783#define nUDMAIN_DONE_MASK 0x0
2784#define UDMAOUT_DONE_MASK 0x10 /* Ultra-DMA out transfer done interrupt mask */
2785#define nUDMAOUT_DONE_MASK 0x0
2786#define HOST_TERM_XFER_MASK 0x20 /* Host terminate current transfer interrupt mask */
2787#define nHOST_TERM_XFER_MASK 0x0
2788#define MULTI_TERM_MASK 0x40 /* Device terminate Multi-DMA transfer interrupt mask */
2789#define nMULTI_TERM_MASK 0x0
2790#define UDMAIN_TERM_MASK 0x80 /* Device terminate Ultra-DMA-in transfer interrupt mask */
2791#define nUDMAIN_TERM_MASK 0x0
2792#define UDMAOUT_TERM_MASK 0x100 /* Device terminate Ultra-DMA-out transfer interrupt mask */
2793#define nUDMAOUT_TERM_MASK 0x0
2794
2795/* Bit masks for ATAPI_INT_STATUS */
2796
2797#define ATAPI_DEV_INT 0x1 /* Device interrupt status */
2798#define nATAPI_DEV_INT 0x0
2799#define PIO_DONE_INT 0x2 /* PIO transfer done interrupt status */
2800#define nPIO_DONE_INT 0x0
2801#define MULTI_DONE_INT 0x4 /* Multi-DMA transfer done interrupt status */
2802#define nMULTI_DONE_INT 0x0
2803#define UDMAIN_DONE_INT 0x8 /* Ultra-DMA in transfer done interrupt status */
2804#define nUDMAIN_DONE_INT 0x0
2805#define UDMAOUT_DONE_INT 0x10 /* Ultra-DMA out transfer done interrupt status */
2806#define nUDMAOUT_DONE_INT 0x0
2807#define HOST_TERM_XFER_INT 0x20 /* Host terminate current transfer interrupt status */
2808#define nHOST_TERM_XFER_INT 0x0
2809#define MULTI_TERM_INT 0x40 /* Device terminate Multi-DMA transfer interrupt status */
2810#define nMULTI_TERM_INT 0x0
2811#define UDMAIN_TERM_INT 0x80 /* Device terminate Ultra-DMA-in transfer interrupt status */
2812#define nUDMAIN_TERM_INT 0x0
2813#define UDMAOUT_TERM_INT 0x100 /* Device terminate Ultra-DMA-out transfer interrupt status */
2814#define nUDMAOUT_TERM_INT 0x0
2815
2816/* Bit masks for ATAPI_LINE_STATUS */
2817
2818#define ATAPI_INTR 0x1 /* Device interrupt to host line status */
2819#define nATAPI_INTR 0x0
2820#define ATAPI_DASP 0x2 /* Device dasp to host line status */
2821#define nATAPI_DASP 0x0
2822#define ATAPI_CS0N 0x4 /* ATAPI chip select 0 line status */
2823#define nATAPI_CS0N 0x0
2824#define ATAPI_CS1N 0x8 /* ATAPI chip select 1 line status */
2825#define nATAPI_CS1N 0x0
2826#define ATAPI_ADDR 0x70 /* ATAPI address line status */
2827#define ATAPI_DMAREQ 0x80 /* ATAPI DMA request line status */
2828#define nATAPI_DMAREQ 0x0
2829#define ATAPI_DMAACKN 0x100 /* ATAPI DMA acknowledge line status */
2830#define nATAPI_DMAACKN 0x0
2831#define ATAPI_DIOWN 0x200 /* ATAPI write line status */
2832#define nATAPI_DIOWN 0x0
2833#define ATAPI_DIORN 0x400 /* ATAPI read line status */
2834#define nATAPI_DIORN 0x0
2835#define ATAPI_IORDY 0x800 /* ATAPI IORDY line status */
2836#define nATAPI_IORDY 0x0
2837
2838/* Bit masks for ATAPI_SM_STATE */
2839
2840#define PIO_CSTATE 0xf /* PIO mode state machine current state */
2841#define DMA_CSTATE 0xf0 /* DMA mode state machine current state */
2842#define UDMAIN_CSTATE 0xf00 /* Ultra DMA-In mode state machine current state */
2843#define UDMAOUT_CSTATE 0xf000 /* ATAPI IORDY line status */
2844
2845/* Bit masks for ATAPI_TERMINATE */
2846
2847#define ATAPI_HOST_TERM 0x1 /* Host terminationation */
2848#define nATAPI_HOST_TERM 0x0
2849
2850/* Bit masks for ATAPI_REG_TIM_0 */
2851
2852#define T2_REG 0xff /* End of cycle time for register access transfers */
2853#define TEOC_REG 0xff00 /* Selects DIOR/DIOW pulsewidth */
2854
2855/* Bit masks for ATAPI_PIO_TIM_0 */
2856
2857#define T1_REG 0xf /* Time from address valid to DIOR/DIOW */
2858#define T2_REG_PIO 0xff0 /* DIOR/DIOW pulsewidth */
2859#define T4_REG 0xf000 /* DIOW data hold */
2860
2861/* Bit masks for ATAPI_PIO_TIM_1 */
2862
2863#define TEOC_REG_PIO 0xff /* End of cycle time for PIO access transfers. */
2864
2865/* Bit masks for ATAPI_MULTI_TIM_0 */
2866
2867#define TD 0xff /* DIOR/DIOW asserted pulsewidth */
2868#define TM 0xff00 /* Time from address valid to DIOR/DIOW */
2869
2870/* Bit masks for ATAPI_MULTI_TIM_1 */
2871
2872#define TKW 0xff /* Selects DIOW negated pulsewidth */
2873#define TKR 0xff00 /* Selects DIOR negated pulsewidth */
2874
2875/* Bit masks for ATAPI_MULTI_TIM_2 */
2876
2877#define TH 0xff /* Selects DIOW data hold */
2878#define TEOC 0xff00 /* Selects end of cycle for DMA */
2879
2880/* Bit masks for ATAPI_ULTRA_TIM_0 */
2881
2882#define TACK 0xff /* Selects setup and hold times for TACK */
2883#define TENV 0xff00 /* Selects envelope time */
2884
2885/* Bit masks for ATAPI_ULTRA_TIM_1 */
2886
2887#define TDVS 0xff /* Selects data valid setup time */
2888#define TCYC_TDVS 0xff00 /* Selects cycle time - TDVS time */
2889
2890/* Bit masks for ATAPI_ULTRA_TIM_2 */
2891
2892#define TSS 0xff /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
2893#define TMLI 0xff00 /* Selects interlock time */
2894
2895/* Bit masks for ATAPI_ULTRA_TIM_3 */
2896
2897#define TZAH 0xff /* Selects minimum delay required for output */
2898#define READY_PAUSE 0xff00 /* Selects ready to pause */
2899
2900/* Bit masks for TIMER_ENABLE1 */
2901
2902#define TIMEN8 0x1 /* Timer 8 Enable */
2903#define nTIMEN8 0x0
2904#define TIMEN9 0x2 /* Timer 9 Enable */
2905#define nTIMEN9 0x0
2906#define TIMEN10 0x4 /* Timer 10 Enable */
2907#define nTIMEN10 0x0
2908
2909/* Bit masks for TIMER_DISABLE1 */
2910
2911#define TIMDIS8 0x1 /* Timer 8 Disable */
2912#define nTIMDIS8 0x0
2913#define TIMDIS9 0x2 /* Timer 9 Disable */
2914#define nTIMDIS9 0x0
2915#define TIMDIS10 0x4 /* Timer 10 Disable */
2916#define nTIMDIS10 0x0
2917
2918/* Bit masks for TIMER_STATUS1 */
2919
2920#define TIMIL8 0x1 /* Timer 8 Interrupt */
2921#define nTIMIL8 0x0
2922#define TIMIL9 0x2 /* Timer 9 Interrupt */
2923#define nTIMIL9 0x0
2924#define TIMIL10 0x4 /* Timer 10 Interrupt */
2925#define nTIMIL10 0x0
2926#define TOVF_ERR8 0x10 /* Timer 8 Counter Overflow */
2927#define nTOVF_ERR8 0x0
2928#define TOVF_ERR9 0x20 /* Timer 9 Counter Overflow */
2929#define nTOVF_ERR9 0x0
2930#define TOVF_ERR10 0x40 /* Timer 10 Counter Overflow */
2931#define nTOVF_ERR10 0x0
2932#define TRUN8 0x1000 /* Timer 8 Slave Enable Status */
2933#define nTRUN8 0x0
2934#define TRUN9 0x2000 /* Timer 9 Slave Enable Status */
2935#define nTRUN9 0x0
2936#define TRUN10 0x4000 /* Timer 10 Slave Enable Status */
2937#define nTRUN10 0x0
2938
2939/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
2940
2941/* Bit masks for USB_FADDR */
2942
2943#define FUNCTION_ADDRESS 0x7f /* Function address */
2944
2945/* Bit masks for USB_POWER */
2946
2947#define ENABLE_SUSPENDM 0x1 /* enable SuspendM output */
2948#define nENABLE_SUSPENDM 0x0
2949#define SUSPEND_MODE 0x2 /* Suspend Mode indicator */
2950#define nSUSPEND_MODE 0x0
2951#define RESUME_MODE 0x4 /* DMA Mode */
2952#define nRESUME_MODE 0x0
2953#define RESET 0x8 /* Reset indicator */
2954#define nRESET 0x0
2955#define HS_MODE 0x10 /* High Speed mode indicator */
2956#define nHS_MODE 0x0
2957#define HS_ENABLE 0x20 /* high Speed Enable */
2958#define nHS_ENABLE 0x0
2959#define SOFT_CONN 0x40 /* Soft connect */
2960#define nSOFT_CONN 0x0
2961#define ISO_UPDATE 0x80 /* Isochronous update */
2962#define nISO_UPDATE 0x0
2963
2964/* Bit masks for USB_INTRTX */
2965
2966#define EP0_TX 0x1 /* Tx Endpoint 0 interrupt */
2967#define nEP0_TX 0x0
2968#define EP1_TX 0x2 /* Tx Endpoint 1 interrupt */
2969#define nEP1_TX 0x0
2970#define EP2_TX 0x4 /* Tx Endpoint 2 interrupt */
2971#define nEP2_TX 0x0
2972#define EP3_TX 0x8 /* Tx Endpoint 3 interrupt */
2973#define nEP3_TX 0x0
2974#define EP4_TX 0x10 /* Tx Endpoint 4 interrupt */
2975#define nEP4_TX 0x0
2976#define EP5_TX 0x20 /* Tx Endpoint 5 interrupt */
2977#define nEP5_TX 0x0
2978#define EP6_TX 0x40 /* Tx Endpoint 6 interrupt */
2979#define nEP6_TX 0x0
2980#define EP7_TX 0x80 /* Tx Endpoint 7 interrupt */
2981#define nEP7_TX 0x0
2982
2983/* Bit masks for USB_INTRRX */
2984
2985#define EP1_RX 0x2 /* Rx Endpoint 1 interrupt */
2986#define nEP1_RX 0x0
2987#define EP2_RX 0x4 /* Rx Endpoint 2 interrupt */
2988#define nEP2_RX 0x0
2989#define EP3_RX 0x8 /* Rx Endpoint 3 interrupt */
2990#define nEP3_RX 0x0
2991#define EP4_RX 0x10 /* Rx Endpoint 4 interrupt */
2992#define nEP4_RX 0x0
2993#define EP5_RX 0x20 /* Rx Endpoint 5 interrupt */
2994#define nEP5_RX 0x0
2995#define EP6_RX 0x40 /* Rx Endpoint 6 interrupt */
2996#define nEP6_RX 0x0
2997#define EP7_RX 0x80 /* Rx Endpoint 7 interrupt */
2998#define nEP7_RX 0x0
2999
3000/* Bit masks for USB_INTRTXE */
3001
3002#define EP0_TX_E 0x1 /* Endpoint 0 interrupt Enable */
3003#define nEP0_TX_E 0x0
3004#define EP1_TX_E 0x2 /* Tx Endpoint 1 interrupt Enable */
3005#define nEP1_TX_E 0x0
3006#define EP2_TX_E 0x4 /* Tx Endpoint 2 interrupt Enable */
3007#define nEP2_TX_E 0x0
3008#define EP3_TX_E 0x8 /* Tx Endpoint 3 interrupt Enable */
3009#define nEP3_TX_E 0x0
3010#define EP4_TX_E 0x10 /* Tx Endpoint 4 interrupt Enable */
3011#define nEP4_TX_E 0x0
3012#define EP5_TX_E 0x20 /* Tx Endpoint 5 interrupt Enable */
3013#define nEP5_TX_E 0x0
3014#define EP6_TX_E 0x40 /* Tx Endpoint 6 interrupt Enable */
3015#define nEP6_TX_E 0x0
3016#define EP7_TX_E 0x80 /* Tx Endpoint 7 interrupt Enable */
3017#define nEP7_TX_E 0x0
3018
3019/* Bit masks for USB_INTRRXE */
3020
3021#define EP1_RX_E 0x2 /* Rx Endpoint 1 interrupt Enable */
3022#define nEP1_RX_E 0x0
3023#define EP2_RX_E 0x4 /* Rx Endpoint 2 interrupt Enable */
3024#define nEP2_RX_E 0x0
3025#define EP3_RX_E 0x8 /* Rx Endpoint 3 interrupt Enable */
3026#define nEP3_RX_E 0x0
3027#define EP4_RX_E 0x10 /* Rx Endpoint 4 interrupt Enable */
3028#define nEP4_RX_E 0x0
3029#define EP5_RX_E 0x20 /* Rx Endpoint 5 interrupt Enable */
3030#define nEP5_RX_E 0x0
3031#define EP6_RX_E 0x40 /* Rx Endpoint 6 interrupt Enable */
3032#define nEP6_RX_E 0x0
3033#define EP7_RX_E 0x80 /* Rx Endpoint 7 interrupt Enable */
3034#define nEP7_RX_E 0x0
3035
3036/* Bit masks for USB_INTRUSB */
3037
3038#define SUSPEND_B 0x1 /* Suspend indicator */
3039#define nSUSPEND_B 0x0
3040#define RESUME_B 0x2 /* Resume indicator */
3041#define nRESUME_B 0x0
3042#define RESET_OR_BABLE_B 0x4 /* Reset/babble indicator */
3043#define nRESET_OR_BABLE_B 0x0
3044#define SOF_B 0x8 /* Start of frame */
3045#define nSOF_B 0x0
3046#define CONN_B 0x10 /* Connection indicator */
3047#define nCONN_B 0x0
3048#define DISCON_B 0x20 /* Disconnect indicator */
3049#define nDISCON_B 0x0
3050#define SESSION_REQ_B 0x40 /* Session Request */
3051#define nSESSION_REQ_B 0x0
3052#define VBUS_ERROR_B 0x80 /* Vbus threshold indicator */
3053#define nVBUS_ERROR_B 0x0
3054
3055/* Bit masks for USB_INTRUSBE */
3056
3057#define SUSPEND_BE 0x1 /* Suspend indicator int enable */
3058#define nSUSPEND_BE 0x0
3059#define RESUME_BE 0x2 /* Resume indicator int enable */
3060#define nRESUME_BE 0x0
3061#define RESET_OR_BABLE_BE 0x4 /* Reset/babble indicator int enable */
3062#define nRESET_OR_BABLE_BE 0x0
3063#define SOF_BE 0x8 /* Start of frame int enable */
3064#define nSOF_BE 0x0
3065#define CONN_BE 0x10 /* Connection indicator int enable */
3066#define nCONN_BE 0x0
3067#define DISCON_BE 0x20 /* Disconnect indicator int enable */
3068#define nDISCON_BE 0x0
3069#define SESSION_REQ_BE 0x40 /* Session Request int enable */
3070#define nSESSION_REQ_BE 0x0
3071#define VBUS_ERROR_BE 0x80 /* Vbus threshold indicator int enable */
3072#define nVBUS_ERROR_BE 0x0
3073
3074/* Bit masks for USB_FRAME */
3075
3076#define FRAME_NUMBER 0x7ff /* Frame number */
3077
3078/* Bit masks for USB_INDEX */
3079
3080#define SELECTED_ENDPOINT 0xf /* selected endpoint */
3081
3082/* Bit masks for USB_GLOBAL_CTL */
3083
3084#define GLOBAL_ENA 0x1 /* enables USB module */
3085#define nGLOBAL_ENA 0x0
3086#define EP1_TX_ENA 0x2 /* Transmit endpoint 1 enable */
3087#define nEP1_TX_ENA 0x0
3088#define EP2_TX_ENA 0x4 /* Transmit endpoint 2 enable */
3089#define nEP2_TX_ENA 0x0
3090#define EP3_TX_ENA 0x8 /* Transmit endpoint 3 enable */
3091#define nEP3_TX_ENA 0x0
3092#define EP4_TX_ENA 0x10 /* Transmit endpoint 4 enable */
3093#define nEP4_TX_ENA 0x0
3094#define EP5_TX_ENA 0x20 /* Transmit endpoint 5 enable */
3095#define nEP5_TX_ENA 0x0
3096#define EP6_TX_ENA 0x40 /* Transmit endpoint 6 enable */
3097#define nEP6_TX_ENA 0x0
3098#define EP7_TX_ENA 0x80 /* Transmit endpoint 7 enable */
3099#define nEP7_TX_ENA 0x0
3100#define EP1_RX_ENA 0x100 /* Receive endpoint 1 enable */
3101#define nEP1_RX_ENA 0x0
3102#define EP2_RX_ENA 0x200 /* Receive endpoint 2 enable */
3103#define nEP2_RX_ENA 0x0
3104#define EP3_RX_ENA 0x400 /* Receive endpoint 3 enable */
3105#define nEP3_RX_ENA 0x0
3106#define EP4_RX_ENA 0x800 /* Receive endpoint 4 enable */
3107#define nEP4_RX_ENA 0x0
3108#define EP5_RX_ENA 0x1000 /* Receive endpoint 5 enable */
3109#define nEP5_RX_ENA 0x0
3110#define EP6_RX_ENA 0x2000 /* Receive endpoint 6 enable */
3111#define nEP6_RX_ENA 0x0
3112#define EP7_RX_ENA 0x4000 /* Receive endpoint 7 enable */
3113#define nEP7_RX_ENA 0x0
3114
3115/* Bit masks for USB_OTG_DEV_CTL */
3116
3117#define SESSION 0x1 /* session indicator */
3118#define nSESSION 0x0
3119#define HOST_REQ 0x2 /* Host negotiation request */
3120#define nHOST_REQ 0x0
3121#define HOST_MODE 0x4 /* indicates USBDRC is a host */
3122#define nHOST_MODE 0x0
3123#define VBUS0 0x8 /* Vbus level indicator[0] */
3124#define nVBUS0 0x0
3125#define VBUS1 0x10 /* Vbus level indicator[1] */
3126#define nVBUS1 0x0
3127#define LSDEV 0x20 /* Low-speed indicator */
3128#define nLSDEV 0x0
3129#define FSDEV 0x40 /* Full or High-speed indicator */
3130#define nFSDEV 0x0
3131#define B_DEVICE 0x80 /* A' or 'B' device indicator */
3132#define nB_DEVICE 0x0
3133
3134/* Bit masks for USB_OTG_VBUS_IRQ */
3135
3136#define DRIVE_VBUS_ON 0x1 /* indicator to drive VBUS control circuit */
3137#define nDRIVE_VBUS_ON 0x0
3138#define DRIVE_VBUS_OFF 0x2 /* indicator to shut off charge pump */
3139#define nDRIVE_VBUS_OFF 0x0
3140#define CHRG_VBUS_START 0x4 /* indicator for external circuit to start charging VBUS */
3141#define nCHRG_VBUS_START 0x0
3142#define CHRG_VBUS_END 0x8 /* indicator for external circuit to end charging VBUS */
3143#define nCHRG_VBUS_END 0x0
3144#define DISCHRG_VBUS_START 0x10 /* indicator to start discharging VBUS */
3145#define nDISCHRG_VBUS_START 0x0
3146#define DISCHRG_VBUS_END 0x20 /* indicator to stop discharging VBUS */
3147#define nDISCHRG_VBUS_END 0x0
3148
3149/* Bit masks for USB_OTG_VBUS_MASK */
3150
3151#define DRIVE_VBUS_ON_ENA 0x1 /* enable DRIVE_VBUS_ON interrupt */
3152#define nDRIVE_VBUS_ON_ENA 0x0
3153#define DRIVE_VBUS_OFF_ENA 0x2 /* enable DRIVE_VBUS_OFF interrupt */
3154#define nDRIVE_VBUS_OFF_ENA 0x0
3155#define CHRG_VBUS_START_ENA 0x4 /* enable CHRG_VBUS_START interrupt */
3156#define nCHRG_VBUS_START_ENA 0x0
3157#define CHRG_VBUS_END_ENA 0x8 /* enable CHRG_VBUS_END interrupt */
3158#define nCHRG_VBUS_END_ENA 0x0
3159#define DISCHRG_VBUS_START_ENA 0x10 /* enable DISCHRG_VBUS_START interrupt */
3160#define nDISCHRG_VBUS_START_ENA 0x0
3161#define DISCHRG_VBUS_END_ENA 0x20 /* enable DISCHRG_VBUS_END interrupt */
3162#define nDISCHRG_VBUS_END_ENA 0x0
3163
3164/* Bit masks for USB_CSR0 */
3165
3166#define RXPKTRDY 0x1 /* data packet receive indicator */
3167#define nRXPKTRDY 0x0
3168#define TXPKTRDY 0x2 /* data packet in FIFO indicator */
3169#define nTXPKTRDY 0x0
3170#define STALL_SENT 0x4 /* STALL handshake sent */
3171#define nSTALL_SENT 0x0
3172#define DATAEND 0x8 /* Data end indicator */
3173#define nDATAEND 0x0
3174#define SETUPEND 0x10 /* Setup end */
3175#define nSETUPEND 0x0
3176#define SENDSTALL 0x20 /* Send STALL handshake */
3177#define nSENDSTALL 0x0
3178#define SERVICED_RXPKTRDY 0x40 /* used to clear the RxPktRdy bit */
3179#define nSERVICED_RXPKTRDY 0x0
3180#define SERVICED_SETUPEND 0x80 /* used to clear the SetupEnd bit */
3181#define nSERVICED_SETUPEND 0x0
3182#define FLUSHFIFO 0x100 /* flush endpoint FIFO */
3183#define nFLUSHFIFO 0x0
3184#define STALL_RECEIVED_H 0x4 /* STALL handshake received host mode */
3185#define nSTALL_RECEIVED_H 0x0
3186#define SETUPPKT_H 0x8 /* send Setup token host mode */
3187#define nSETUPPKT_H 0x0
3188#define ERROR_H 0x10 /* timeout error indicator host mode */
3189#define nERROR_H 0x0
3190#define REQPKT_H 0x20 /* Request an IN transaction host mode */
3191#define nREQPKT_H 0x0
3192#define STATUSPKT_H 0x40 /* Status stage transaction host mode */
3193#define nSTATUSPKT_H 0x0
3194#define NAK_TIMEOUT_H 0x80 /* EP0 halted after a NAK host mode */
3195#define nNAK_TIMEOUT_H 0x0
3196
3197/* Bit masks for USB_COUNT0 */
3198
3199#define EP0_RX_COUNT 0x7f /* number of received bytes in EP0 FIFO */
3200
3201/* Bit masks for USB_NAKLIMIT0 */
3202
3203#define EP0_NAK_LIMIT 0x1f /* number of frames/micro frames after which EP0 timeouts */
3204
3205/* Bit masks for USB_TX_MAX_PACKET */
3206
3207#define MAX_PACKET_SIZE_T 0x7ff /* maximum data pay load in a frame */
3208
3209/* Bit masks for USB_RX_MAX_PACKET */
3210
3211#define MAX_PACKET_SIZE_R 0x7ff /* maximum data pay load in a frame */
3212
3213/* Bit masks for USB_TXCSR */
3214
3215#define TXPKTRDY_T 0x1 /* data packet in FIFO indicator */
3216#define nTXPKTRDY_T 0x0
3217#define FIFO_NOT_EMPTY_T 0x2 /* FIFO not empty */
3218#define nFIFO_NOT_EMPTY_T 0x0
3219#define UNDERRUN_T 0x4 /* TxPktRdy not set for an IN token */
3220#define nUNDERRUN_T 0x0
3221#define FLUSHFIFO_T 0x8 /* flush endpoint FIFO */
3222#define nFLUSHFIFO_T 0x0
3223#define STALL_SEND_T 0x10 /* issue a Stall handshake */
3224#define nSTALL_SEND_T 0x0
3225#define STALL_SENT_T 0x20 /* Stall handshake transmitted */
3226#define nSTALL_SENT_T 0x0
3227#define CLEAR_DATATOGGLE_T 0x40 /* clear endpoint data toggle */
3228#define nCLEAR_DATATOGGLE_T 0x0
3229#define INCOMPTX_T 0x80 /* indicates that a large packet is split */
3230#define nINCOMPTX_T 0x0
3231#define DMAREQMODE_T 0x400 /* DMA mode (0 or 1) selection */
3232#define nDMAREQMODE_T 0x0
3233#define FORCE_DATATOGGLE_T 0x800 /* Force data toggle */
3234#define nFORCE_DATATOGGLE_T 0x0
3235#define DMAREQ_ENA_T 0x1000 /* Enable DMA request for Tx EP */
3236#define nDMAREQ_ENA_T 0x0
3237#define ISO_T 0x4000 /* enable Isochronous transfers */
3238#define nISO_T 0x0
3239#define AUTOSET_T 0x8000 /* allows TxPktRdy to be set automatically */
3240#define nAUTOSET_T 0x0
3241#define ERROR_TH 0x4 /* error condition host mode */
3242#define nERROR_TH 0x0
3243#define STALL_RECEIVED_TH 0x20 /* Stall handshake received host mode */
3244#define nSTALL_RECEIVED_TH 0x0
3245#define NAK_TIMEOUT_TH 0x80 /* NAK timeout host mode */
3246#define nNAK_TIMEOUT_TH 0x0
3247
3248/* Bit masks for USB_TXCOUNT */
3249
3250#define TX_COUNT 0x1fff /* Number of bytes to be written to the selected endpoint Tx FIFO */
3251
3252/* Bit masks for USB_RXCSR */
3253
3254#define RXPKTRDY_R 0x1 /* data packet in FIFO indicator */
3255#define nRXPKTRDY_R 0x0
3256#define FIFO_FULL_R 0x2 /* FIFO not empty */
3257#define nFIFO_FULL_R 0x0
3258#define OVERRUN_R 0x4 /* TxPktRdy not set for an IN token */
3259#define nOVERRUN_R 0x0
3260#define DATAERROR_R 0x8 /* Out packet cannot be loaded into Rx FIFO */
3261#define nDATAERROR_R 0x0
3262#define FLUSHFIFO_R 0x10 /* flush endpoint FIFO */
3263#define nFLUSHFIFO_R 0x0
3264#define STALL_SEND_R 0x20 /* issue a Stall handshake */
3265#define nSTALL_SEND_R 0x0
3266#define STALL_SENT_R 0x40 /* Stall handshake transmitted */
3267#define nSTALL_SENT_R 0x0
3268#define CLEAR_DATATOGGLE_R 0x80 /* clear endpoint data toggle */
3269#define nCLEAR_DATATOGGLE_R 0x0
3270#define INCOMPRX_R 0x100 /* indicates that a large packet is split */
3271#define nINCOMPRX_R 0x0
3272#define DMAREQMODE_R 0x800 /* DMA mode (0 or 1) selection */
3273#define nDMAREQMODE_R 0x0
3274#define DISNYET_R 0x1000 /* disable Nyet handshakes */
3275#define nDISNYET_R 0x0
3276#define DMAREQ_ENA_R 0x2000 /* Enable DMA request for Tx EP */
3277#define nDMAREQ_ENA_R 0x0
3278#define ISO_R 0x4000 /* enable Isochronous transfers */
3279#define nISO_R 0x0
3280#define AUTOCLEAR_R 0x8000 /* allows TxPktRdy to be set automatically */
3281#define nAUTOCLEAR_R 0x0
3282#define ERROR_RH 0x4 /* TxPktRdy not set for an IN token host mode */
3283#define nERROR_RH 0x0
3284#define REQPKT_RH 0x20 /* request an IN transaction host mode */
3285#define nREQPKT_RH 0x0
3286#define STALL_RECEIVED_RH 0x40 /* Stall handshake received host mode */
3287#define nSTALL_RECEIVED_RH 0x0
3288#define INCOMPRX_RH 0x100 /* indicates that a large packet is split host mode */
3289#define nINCOMPRX_RH 0x0
3290#define DMAREQMODE_RH 0x800 /* DMA mode (0 or 1) selection host mode */
3291#define nDMAREQMODE_RH 0x0
3292#define AUTOREQ_RH 0x4000 /* sets ReqPkt automatically host mode */
3293#define nAUTOREQ_RH 0x0
3294
3295/* Bit masks for USB_RXCOUNT */
3296
3297#define RX_COUNT 0x1fff /* Number of received bytes in the packet in the Rx FIFO */
3298
3299/* Bit masks for USB_TXTYPE */
3300
3301#define TARGET_EP_NO_T 0xf /* EP number */
3302#define PROTOCOL_T 0xc /* transfer type */
3303
3304/* Bit masks for USB_TXINTERVAL */
3305
3306#define TX_POLL_INTERVAL 0xff /* polling interval for selected Tx EP */
3307
3308/* Bit masks for USB_RXTYPE */
3309
3310#define TARGET_EP_NO_R 0xf /* EP number */
3311#define PROTOCOL_R 0xc /* transfer type */
3312
3313/* Bit masks for USB_RXINTERVAL */
3314
3315#define RX_POLL_INTERVAL 0xff /* polling interval for selected Rx EP */
3316
3317/* Bit masks for USB_DMA_INTERRUPT */
3318
3319#define DMA0_INT 0x1 /* DMA0 pending interrupt */
3320#define nDMA0_INT 0x0
3321#define DMA1_INT 0x2 /* DMA1 pending interrupt */
3322#define nDMA1_INT 0x0
3323#define DMA2_INT 0x4 /* DMA2 pending interrupt */
3324#define nDMA2_INT 0x0
3325#define DMA3_INT 0x8 /* DMA3 pending interrupt */
3326#define nDMA3_INT 0x0
3327#define DMA4_INT 0x10 /* DMA4 pending interrupt */
3328#define nDMA4_INT 0x0
3329#define DMA5_INT 0x20 /* DMA5 pending interrupt */
3330#define nDMA5_INT 0x0
3331#define DMA6_INT 0x40 /* DMA6 pending interrupt */
3332#define nDMA6_INT 0x0
3333#define DMA7_INT 0x80 /* DMA7 pending interrupt */
3334#define nDMA7_INT 0x0
3335
3336/* Bit masks for USB_DMAxCONTROL */
3337
3338#define DMA_ENA 0x1 /* DMA enable */
3339#define nDMA_ENA 0x0
3340#define DIRECTION 0x2 /* direction of DMA transfer */
3341#define nDIRECTION 0x0
3342#define MODE 0x4 /* DMA Bus error */
3343#define nMODE 0x0
3344#define INT_ENA 0x8 /* Interrupt enable */
3345#define nINT_ENA 0x0
3346#define EPNUM 0xf0 /* EP number */
3347#define BUSERROR 0x100 /* DMA Bus error */
3348#define nBUSERROR 0x0
3349
3350/* Bit masks for USB_DMAxADDRHIGH */
3351
3352#define DMA_ADDR_HIGH 0xffff /* Upper 16-bits of memory source/destination address for the DMA master channel */
3353
3354/* Bit masks for USB_DMAxADDRLOW */
3355
3356#define DMA_ADDR_LOW 0xffff /* Lower 16-bits of memory source/destination address for the DMA master channel */
3357
3358/* Bit masks for USB_DMAxCOUNTHIGH */
3359
3360#define DMA_COUNT_HIGH 0xffff /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
3361
3362/* Bit masks for USB_DMAxCOUNTLOW */
3363
3364#define DMA_COUNT_LOW 0xffff /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
3365
3366/* Bit masks for HMDMAx_CONTROL */
3367
3368#define HMDMAEN 0x1 /* Handshake MDMA Enable */
3369#define nHMDMAEN 0x0
3370#define REP 0x2 /* Handshake MDMA Request Polarity */
3371#define nREP 0x0
3372#define UTE 0x8 /* Urgency Threshold Enable */
3373#define nUTE 0x0
3374#define OIE 0x10 /* Overflow Interrupt Enable */
3375#define nOIE 0x0
3376#define BDIE 0x20 /* Block Done Interrupt Enable */
3377#define nBDIE 0x0
3378#define MBDI 0x40 /* Mask Block Done Interrupt */
3379#define nMBDI 0x0
3380#define DRQ 0x300 /* Handshake MDMA Request Type */
3381#define RBC 0x1000 /* Force Reload of BCOUNT */
3382#define nRBC 0x0
3383#define PS 0x2000 /* Pin Status */
3384#define nPS 0x0
3385#define OI 0x4000 /* Overflow Interrupt Generated */
3386#define nOI 0x0
3387#define BDI 0x8000 /* Block Done Interrupt Generated */
3388#define nBDI 0x0
3389
3390/* ******************************************* */
3391/* MULTI BIT MACRO ENUMERATIONS */
3392/* ******************************************* */
3393
3394/* ************************ */
3395/* MXVR Address Offsets */
3396/* ************************ */
3397
3398/* Control Message Receive Buffer (CMRB) Address Offsets */
3399
3400#define CMRB_STRIDE 0x00000016lu
3401
3402#define CMRB_DST_OFFSET 0x00000000lu
3403#define CMRB_SRC_OFFSET 0x00000002lu
3404#define CMRB_DATA_OFFSET 0x00000005lu
3405
3406/* Control Message Transmit Buffer (CMTB) Address Offsets */
3407
3408#define CMTB_PRIO_OFFSET 0x00000000lu
3409#define CMTB_DST_OFFSET 0x00000002lu
3410#define CMTB_SRC_OFFSET 0x00000004lu
3411#define CMTB_TYPE_OFFSET 0x00000006lu
3412#define CMTB_DATA_OFFSET 0x00000007lu
3413
3414#define CMTB_ANSWER_OFFSET 0x0000000Alu
3415
3416#define CMTB_STAT_N_OFFSET 0x00000018lu
3417#define CMTB_STAT_A_OFFSET 0x00000016lu
3418#define CMTB_STAT_D_OFFSET 0x0000000Elu
3419#define CMTB_STAT_R_OFFSET 0x00000014lu
3420#define CMTB_STAT_W_OFFSET 0x00000014lu
3421#define CMTB_STAT_G_OFFSET 0x00000014lu
3422
3423/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
3424
3425#define APRB_STRIDE 0x00000400lu
3426
3427#define APRB_DST_OFFSET 0x00000000lu
3428#define APRB_LEN_OFFSET 0x00000002lu
3429#define APRB_SRC_OFFSET 0x00000004lu
3430#define APRB_DATA_OFFSET 0x00000006lu
3431
3432/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
3433
3434#define APTB_PRIO_OFFSET 0x00000000lu
3435#define APTB_DST_OFFSET 0x00000002lu
3436#define APTB_LEN_OFFSET 0x00000004lu
3437#define APTB_SRC_OFFSET 0x00000006lu
3438#define APTB_DATA_OFFSET 0x00000008lu
3439
3440/* Remote Read Buffer (RRDB) Address Offsets */
3441
3442#define RRDB_WADDR_OFFSET 0x00000100lu
3443#define RRDB_WLEN_OFFSET 0x00000101lu
3444
3445/* **************** */
3446/* MXVR Macros */
3447/* **************** */
3448
3449/* MXVR_CONFIG Macros */
3450
3451#define SET_MSB(x) ( ( (x) & 0xF ) << 9)
3452
3453/* MXVR_INT_STAT_1 Macros */
3454
3455#define DONEX(x) (0x00000002 << (4 * (x)))
3456#define HDONEX(x) (0x00000001 << (4 * (x)))
3457
3458/* MXVR_INT_EN_1 Macros */
3459
3460#define DONEENX(x) (0x00000002 << (4 * (x)))
3461#define HDONEENX(x) (0x00000001 << (4 * (x)))
3462
3463/* MXVR_CDRPLL_CTL Macros */
3464
3465#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
3466
3467/* MXVR_FMPLL_CTL Macros */
3468
3469#define SET_CDRCPSEL(x) ( ( (x) & 0xFF ) << 24)
3470#define SET_FMCPSEL(x) ( ( (x) & 0xFF ) << 24)
3471
3472#endif /* _DEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
new file mode 100644
index 000000000000..a1b200fe6a1f
--- /dev/null
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -0,0 +1,4902 @@
1/*
2 * File: include/asm-blackfin/mach-bf548/defBF54x_base.h
3 * Based on:
4 * Author:
5 *
6 * Created:
7 * Description:
8 *
9 * Rev:
10 *
11 * Modified:
12 *
13 * Bugs: Enter bugs at http://blackfin.uclinux.org/
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2, or (at your option)
18 * any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; see the file COPYING.
27 * If not, write to the Free Software Foundation,
28 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29 */
30
31#ifndef _DEF_BF54X_H
32#define _DEF_BF54X_H
33
34
35/* ************************************************************** */
36/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x */
37/* ************************************************************** */
38
39/* PLL Registers */
40
41#define PLL_CTL 0xffc00000 /* PLL Control Register */
42#define PLL_DIV 0xffc00004 /* PLL Divisor Register */
43#define VR_CTL 0xffc00008 /* Voltage Regulator Control Register */
44#define PLL_STAT 0xffc0000c /* PLL Status Register */
45#define PLL_LOCKCNT 0xffc00010 /* PLL Lock Count Register */
46
47/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
48
49#define CHIPID 0xffc00014
50
51/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
52
53#define SWRST 0xffc00100 /* Software Reset Register */
54#define SYSCR 0xffc00104 /* System Configuration register */
55
56/* SIC Registers */
57
58#define SIC_IMASK0 0xffc0010c /* System Interrupt Mask Register 0 */
59#define SIC_IMASK1 0xffc00110 /* System Interrupt Mask Register 1 */
60#define SIC_IMASK2 0xffc00114 /* System Interrupt Mask Register 2 */
61#define SIC_ISR0 0xffc00118 /* System Interrupt Status Register 0 */
62#define SIC_ISR1 0xffc0011c /* System Interrupt Status Register 1 */
63#define SIC_ISR2 0xffc00120 /* System Interrupt Status Register 2 */
64#define SIC_IWR0 0xffc00124 /* System Interrupt Wakeup Register 0 */
65#define SIC_IWR1 0xffc00128 /* System Interrupt Wakeup Register 1 */
66#define SIC_IWR2 0xffc0012c /* System Interrupt Wakeup Register 2 */
67#define SIC_IAR0 0xffc00130 /* System Interrupt Assignment Register 0 */
68#define SIC_IAR1 0xffc00134 /* System Interrupt Assignment Register 1 */
69#define SIC_IAR2 0xffc00138 /* System Interrupt Assignment Register 2 */
70#define SIC_IAR3 0xffc0013c /* System Interrupt Assignment Register 3 */
71#define SIC_IAR4 0xffc00140 /* System Interrupt Assignment Register 4 */
72#define SIC_IAR5 0xffc00144 /* System Interrupt Assignment Register 5 */
73#define SIC_IAR6 0xffc00148 /* System Interrupt Assignment Register 6 */
74#define SIC_IAR7 0xffc0014c /* System Interrupt Assignment Register 7 */
75#define SIC_IAR8 0xffc00150 /* System Interrupt Assignment Register 8 */
76#define SIC_IAR9 0xffc00154 /* System Interrupt Assignment Register 9 */
77#define SIC_IAR10 0xffc00158 /* System Interrupt Assignment Register 10 */
78#define SIC_IAR11 0xffc0015c /* System Interrupt Assignment Register 11 */
79
80/* Watchdog Timer Registers */
81
82#define WDOG_CTL 0xffc00200 /* Watchdog Control Register */
83#define WDOG_CNT 0xffc00204 /* Watchdog Count Register */
84#define WDOG_STAT 0xffc00208 /* Watchdog Status Register */
85
86/* RTC Registers */
87
88#define RTC_STAT 0xffc00300 /* RTC Status Register */
89#define RTC_ICTL 0xffc00304 /* RTC Interrupt Control Register */
90#define RTC_ISTAT 0xffc00308 /* RTC Interrupt Status Register */
91#define RTC_SWCNT 0xffc0030c /* RTC Stopwatch Count Register */
92#define RTC_ALARM 0xffc00310 /* RTC Alarm Register */
93#define RTC_PREN 0xffc00314 /* RTC Prescaler Enable Register */
94
95/* UART0 Registers */
96
97#define UART0_DLL 0xffc00400 /* Divisor Latch Low Byte */
98#define UART0_DLH 0xffc00404 /* Divisor Latch High Byte */
99#define UART0_GCTL 0xffc00408 /* Global Control Register */
100#define UART0_LCR 0xffc0040c /* Line Control Register */
101#define UART0_MCR 0xffc00410 /* Modem Control Register */
102#define UART0_LSR 0xffc00414 /* Line Status Register */
103#define UART0_MSR 0xffc00418 /* Modem Status Register */
104#define UART0_SCR 0xffc0041c /* Scratch Register */
105#define UART0_IER_SET 0xffc00420 /* Interrupt Enable Register Set */
106#define UART0_IER_CLEAR 0xffc00424 /* Interrupt Enable Register Clear */
107#define UART0_THR 0xffc00428 /* Transmit Hold Register */
108#define UART0_RBR 0xffc0042c /* Receive Buffer Register */
109
110/* SPI0 Registers */
111
112#define SPI0_CTL 0xffc00500 /* SPI0 Control Register */
113#define SPI0_FLG 0xffc00504 /* SPI0 Flag Register */
114#define SPI0_STAT 0xffc00508 /* SPI0 Status Register */
115#define SPI0_TDBR 0xffc0050c /* SPI0 Transmit Data Buffer Register */
116#define SPI0_RDBR 0xffc00510 /* SPI0 Receive Data Buffer Register */
117#define SPI0_BAUD 0xffc00514 /* SPI0 Baud Rate Register */
118#define SPI0_SHADOW 0xffc00518 /* SPI0 Receive Data Buffer Shadow Register */
119
120/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
121
122/* Two Wire Interface Registers (TWI0) */
123
124#define TWI0_CLKDIV 0xffc00700 /* Clock Divider Register */
125#define TWI0_CONTROL 0xffc00704 /* TWI Control Register */
126#define TWI0_SLAVE_CTRL 0xffc00708 /* TWI Slave Mode Control Register */
127#define TWI0_SLAVE_STAT 0xffc0070c /* TWI Slave Mode Status Register */
128#define TWI0_SLAVE_ADDR 0xffc00710 /* TWI Slave Mode Address Register */
129#define TWI0_MASTER_CTRL 0xffc00714 /* TWI Master Mode Control Register */
130#define TWI0_MASTER_STAT 0xffc00718 /* TWI Master Mode Status Register */
131#define TWI0_MASTER_ADDR 0xffc0071c /* TWI Master Mode Address Register */
132#define TWI0_INT_STAT 0xffc00720 /* TWI Interrupt Status Register */
133#define TWI0_INT_MASK 0xffc00724 /* TWI Interrupt Mask Register */
134#define TWI0_FIFO_CTRL 0xffc00728 /* TWI FIFO Control Register */
135#define TWI0_FIFO_STAT 0xffc0072c /* TWI FIFO Status Register */
136#define TWI0_XMT_DATA8 0xffc00780 /* TWI FIFO Transmit Data Single Byte Register */
137#define TWI0_XMT_DATA16 0xffc00784 /* TWI FIFO Transmit Data Double Byte Register */
138#define TWI0_RCV_DATA8 0xffc00788 /* TWI FIFO Receive Data Single Byte Register */
139#define TWI0_RCV_DATA16 0xffc0078c /* TWI FIFO Receive Data Double Byte Register */
140
141/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
142
143/* SPORT1 Registers */
144
145#define SPORT1_TCR1 0xffc00900 /* SPORT1 Transmit Configuration 1 Register */
146#define SPORT1_TCR2 0xffc00904 /* SPORT1 Transmit Configuration 2 Register */
147#define SPORT1_TCLKDIV 0xffc00908 /* SPORT1 Transmit Serial Clock Divider Register */
148#define SPORT1_TFSDIV 0xffc0090c /* SPORT1 Transmit Frame Sync Divider Register */
149#define SPORT1_TX 0xffc00910 /* SPORT1 Transmit Data Register */
150#define SPORT1_RX 0xffc00918 /* SPORT1 Receive Data Register */
151#define SPORT1_RCR1 0xffc00920 /* SPORT1 Receive Configuration 1 Register */
152#define SPORT1_RCR2 0xffc00924 /* SPORT1 Receive Configuration 2 Register */
153#define SPORT1_RCLKDIV 0xffc00928 /* SPORT1 Receive Serial Clock Divider Register */
154#define SPORT1_RFSDIV 0xffc0092c /* SPORT1 Receive Frame Sync Divider Register */
155#define SPORT1_STAT 0xffc00930 /* SPORT1 Status Register */
156#define SPORT1_CHNL 0xffc00934 /* SPORT1 Current Channel Register */
157#define SPORT1_MCMC1 0xffc00938 /* SPORT1 Multi channel Configuration Register 1 */
158#define SPORT1_MCMC2 0xffc0093c /* SPORT1 Multi channel Configuration Register 2 */
159#define SPORT1_MTCS0 0xffc00940 /* SPORT1 Multi channel Transmit Select Register 0 */
160#define SPORT1_MTCS1 0xffc00944 /* SPORT1 Multi channel Transmit Select Register 1 */
161#define SPORT1_MTCS2 0xffc00948 /* SPORT1 Multi channel Transmit Select Register 2 */
162#define SPORT1_MTCS3 0xffc0094c /* SPORT1 Multi channel Transmit Select Register 3 */
163#define SPORT1_MRCS0 0xffc00950 /* SPORT1 Multi channel Receive Select Register 0 */
164#define SPORT1_MRCS1 0xffc00954 /* SPORT1 Multi channel Receive Select Register 1 */
165#define SPORT1_MRCS2 0xffc00958 /* SPORT1 Multi channel Receive Select Register 2 */
166#define SPORT1_MRCS3 0xffc0095c /* SPORT1 Multi channel Receive Select Register 3 */
167
168/* Asynchronous Memory Control Registers */
169
170#define EBIU_AMGCTL 0xffc00a00 /* Asynchronous Memory Global Control Register */
171#define EBIU_AMBCTL0 0xffc00a04 /* Asynchronous Memory Bank Control Register */
172#define EBIU_AMBCTL1 0xffc00a08 /* Asynchronous Memory Bank Control Register */
173#define EBIU_MBSCTL 0xffc00a0c /* Asynchronous Memory Bank Select Control Register */
174#define EBIU_ARBSTAT 0xffc00a10 /* Asynchronous Memory Arbiter Status Register */
175#define EBIU_MODE 0xffc00a14 /* Asynchronous Mode Control Register */
176#define EBIU_FCTL 0xffc00a18 /* Asynchronous Memory Flash Control Register */
177
178/* DDR Memory Control Registers */
179
180#define EBIU_DDRCTL0 0xffc00a20 /* DDR Memory Control 0 Register */
181#define EBIU_DDRCTL1 0xffc00a24 /* DDR Memory Control 1 Register */
182#define EBIU_DDRCTL2 0xffc00a28 /* DDR Memory Control 2 Register */
183#define EBIU_DDRCTL3 0xffc00a2c /* DDR Memory Control 3 Register */
184#define EBIU_DDRQUE 0xffc00a30 /* DDR Queue Configuration Register */
185#define EBIU_ERRADD 0xffc00a34 /* DDR Error Address Register */
186#define EBIU_ERRMST 0xffc00a38 /* DDR Error Master Register */
187#define EBIU_RSTCTL 0xffc00a3c /* DDR Reset Control Register */
188
189/* DDR BankRead and Write Count Registers */
190
191#define EBIU_DDRBRC0 0xffc00a60 /* DDR Bank0 Read Count Register */
192#define EBIU_DDRBRC1 0xffc00a64 /* DDR Bank1 Read Count Register */
193#define EBIU_DDRBRC2 0xffc00a68 /* DDR Bank2 Read Count Register */
194#define EBIU_DDRBRC3 0xffc00a6c /* DDR Bank3 Read Count Register */
195#define EBIU_DDRBRC4 0xffc00a70 /* DDR Bank4 Read Count Register */
196#define EBIU_DDRBRC5 0xffc00a74 /* DDR Bank5 Read Count Register */
197#define EBIU_DDRBRC6 0xffc00a78 /* DDR Bank6 Read Count Register */
198#define EBIU_DDRBRC7 0xffc00a7c /* DDR Bank7 Read Count Register */
199#define EBIU_DDRBWC0 0xffc00a80 /* DDR Bank0 Write Count Register */
200#define EBIU_DDRBWC1 0xffc00a84 /* DDR Bank1 Write Count Register */
201#define EBIU_DDRBWC2 0xffc00a88 /* DDR Bank2 Write Count Register */
202#define EBIU_DDRBWC3 0xffc00a8c /* DDR Bank3 Write Count Register */
203#define EBIU_DDRBWC4 0xffc00a90 /* DDR Bank4 Write Count Register */
204#define EBIU_DDRBWC5 0xffc00a94 /* DDR Bank5 Write Count Register */
205#define EBIU_DDRBWC6 0xffc00a98 /* DDR Bank6 Write Count Register */
206#define EBIU_DDRBWC7 0xffc00a9c /* DDR Bank7 Write Count Register */
207#define EBIU_DDRACCT 0xffc00aa0 /* DDR Activation Count Register */
208#define EBIU_DDRTACT 0xffc00aa8 /* DDR Turn Around Count Register */
209#define EBIU_DDRARCT 0xffc00aac /* DDR Auto-refresh Count Register */
210#define EBIU_DDRGC0 0xffc00ab0 /* DDR Grant Count 0 Register */
211#define EBIU_DDRGC1 0xffc00ab4 /* DDR Grant Count 1 Register */
212#define EBIU_DDRGC2 0xffc00ab8 /* DDR Grant Count 2 Register */
213#define EBIU_DDRGC3 0xffc00abc /* DDR Grant Count 3 Register */
214#define EBIU_DDRMCEN 0xffc00ac0 /* DDR Metrics Counter Enable Register */
215#define EBIU_DDRMCCL 0xffc00ac4 /* DDR Metrics Counter Clear Register */
216
217/* DMAC0 Registers */
218
219#define DMAC0_TCPER 0xffc00b0c /* DMA Controller 0 Traffic Control Periods Register */
220#define DMAC0_TCCNT 0xffc00b10 /* DMA Controller 0 Current Counts Register */
221
222/* DMA Channel 0 Registers */
223
224#define DMA0_NEXT_DESC_PTR 0xffc00c00 /* DMA Channel 0 Next Descriptor Pointer Register */
225#define DMA0_START_ADDR 0xffc00c04 /* DMA Channel 0 Start Address Register */
226#define DMA0_CONFIG 0xffc00c08 /* DMA Channel 0 Configuration Register */
227#define DMA0_X_COUNT 0xffc00c10 /* DMA Channel 0 X Count Register */
228#define DMA0_X_MODIFY 0xffc00c14 /* DMA Channel 0 X Modify Register */
229#define DMA0_Y_COUNT 0xffc00c18 /* DMA Channel 0 Y Count Register */
230#define DMA0_Y_MODIFY 0xffc00c1c /* DMA Channel 0 Y Modify Register */
231#define DMA0_CURR_DESC_PTR 0xffc00c20 /* DMA Channel 0 Current Descriptor Pointer Register */
232#define DMA0_CURR_ADDR 0xffc00c24 /* DMA Channel 0 Current Address Register */
233#define DMA0_IRQ_STATUS 0xffc00c28 /* DMA Channel 0 Interrupt/Status Register */
234#define DMA0_PERIPHERAL_MAP 0xffc00c2c /* DMA Channel 0 Peripheral Map Register */
235#define DMA0_CURR_X_COUNT 0xffc00c30 /* DMA Channel 0 Current X Count Register */
236#define DMA0_CURR_Y_COUNT 0xffc00c38 /* DMA Channel 0 Current Y Count Register */
237
238/* DMA Channel 1 Registers */
239
240#define DMA1_NEXT_DESC_PTR 0xffc00c40 /* DMA Channel 1 Next Descriptor Pointer Register */
241#define DMA1_START_ADDR 0xffc00c44 /* DMA Channel 1 Start Address Register */
242#define DMA1_CONFIG 0xffc00c48 /* DMA Channel 1 Configuration Register */
243#define DMA1_X_COUNT 0xffc00c50 /* DMA Channel 1 X Count Register */
244#define DMA1_X_MODIFY 0xffc00c54 /* DMA Channel 1 X Modify Register */
245#define DMA1_Y_COUNT 0xffc00c58 /* DMA Channel 1 Y Count Register */
246#define DMA1_Y_MODIFY 0xffc00c5c /* DMA Channel 1 Y Modify Register */
247#define DMA1_CURR_DESC_PTR 0xffc00c60 /* DMA Channel 1 Current Descriptor Pointer Register */
248#define DMA1_CURR_ADDR 0xffc00c64 /* DMA Channel 1 Current Address Register */
249#define DMA1_IRQ_STATUS 0xffc00c68 /* DMA Channel 1 Interrupt/Status Register */
250#define DMA1_PERIPHERAL_MAP 0xffc00c6c /* DMA Channel 1 Peripheral Map Register */
251#define DMA1_CURR_X_COUNT 0xffc00c70 /* DMA Channel 1 Current X Count Register */
252#define DMA1_CURR_Y_COUNT 0xffc00c78 /* DMA Channel 1 Current Y Count Register */
253
254/* DMA Channel 2 Registers */
255
256#define DMA2_NEXT_DESC_PTR 0xffc00c80 /* DMA Channel 2 Next Descriptor Pointer Register */
257#define DMA2_START_ADDR 0xffc00c84 /* DMA Channel 2 Start Address Register */
258#define DMA2_CONFIG 0xffc00c88 /* DMA Channel 2 Configuration Register */
259#define DMA2_X_COUNT 0xffc00c90 /* DMA Channel 2 X Count Register */
260#define DMA2_X_MODIFY 0xffc00c94 /* DMA Channel 2 X Modify Register */
261#define DMA2_Y_COUNT 0xffc00c98 /* DMA Channel 2 Y Count Register */
262#define DMA2_Y_MODIFY 0xffc00c9c /* DMA Channel 2 Y Modify Register */
263#define DMA2_CURR_DESC_PTR 0xffc00ca0 /* DMA Channel 2 Current Descriptor Pointer Register */
264#define DMA2_CURR_ADDR 0xffc00ca4 /* DMA Channel 2 Current Address Register */
265#define DMA2_IRQ_STATUS 0xffc00ca8 /* DMA Channel 2 Interrupt/Status Register */
266#define DMA2_PERIPHERAL_MAP 0xffc00cac /* DMA Channel 2 Peripheral Map Register */
267#define DMA2_CURR_X_COUNT 0xffc00cb0 /* DMA Channel 2 Current X Count Register */
268#define DMA2_CURR_Y_COUNT 0xffc00cb8 /* DMA Channel 2 Current Y Count Register */
269
270/* DMA Channel 3 Registers */
271
272#define DMA3_NEXT_DESC_PTR 0xffc00cc0 /* DMA Channel 3 Next Descriptor Pointer Register */
273#define DMA3_START_ADDR 0xffc00cc4 /* DMA Channel 3 Start Address Register */
274#define DMA3_CONFIG 0xffc00cc8 /* DMA Channel 3 Configuration Register */
275#define DMA3_X_COUNT 0xffc00cd0 /* DMA Channel 3 X Count Register */
276#define DMA3_X_MODIFY 0xffc00cd4 /* DMA Channel 3 X Modify Register */
277#define DMA3_Y_COUNT 0xffc00cd8 /* DMA Channel 3 Y Count Register */
278#define DMA3_Y_MODIFY 0xffc00cdc /* DMA Channel 3 Y Modify Register */
279#define DMA3_CURR_DESC_PTR 0xffc00ce0 /* DMA Channel 3 Current Descriptor Pointer Register */
280#define DMA3_CURR_ADDR 0xffc00ce4 /* DMA Channel 3 Current Address Register */
281#define DMA3_IRQ_STATUS 0xffc00ce8 /* DMA Channel 3 Interrupt/Status Register */
282#define DMA3_PERIPHERAL_MAP 0xffc00cec /* DMA Channel 3 Peripheral Map Register */
283#define DMA3_CURR_X_COUNT 0xffc00cf0 /* DMA Channel 3 Current X Count Register */
284#define DMA3_CURR_Y_COUNT 0xffc00cf8 /* DMA Channel 3 Current Y Count Register */
285
286/* DMA Channel 4 Registers */
287
288#define DMA4_NEXT_DESC_PTR 0xffc00d00 /* DMA Channel 4 Next Descriptor Pointer Register */
289#define DMA4_START_ADDR 0xffc00d04 /* DMA Channel 4 Start Address Register */
290#define DMA4_CONFIG 0xffc00d08 /* DMA Channel 4 Configuration Register */
291#define DMA4_X_COUNT 0xffc00d10 /* DMA Channel 4 X Count Register */
292#define DMA4_X_MODIFY 0xffc00d14 /* DMA Channel 4 X Modify Register */
293#define DMA4_Y_COUNT 0xffc00d18 /* DMA Channel 4 Y Count Register */
294#define DMA4_Y_MODIFY 0xffc00d1c /* DMA Channel 4 Y Modify Register */
295#define DMA4_CURR_DESC_PTR 0xffc00d20 /* DMA Channel 4 Current Descriptor Pointer Register */
296#define DMA4_CURR_ADDR 0xffc00d24 /* DMA Channel 4 Current Address Register */
297#define DMA4_IRQ_STATUS 0xffc00d28 /* DMA Channel 4 Interrupt/Status Register */
298#define DMA4_PERIPHERAL_MAP 0xffc00d2c /* DMA Channel 4 Peripheral Map Register */
299#define DMA4_CURR_X_COUNT 0xffc00d30 /* DMA Channel 4 Current X Count Register */
300#define DMA4_CURR_Y_COUNT 0xffc00d38 /* DMA Channel 4 Current Y Count Register */
301
302/* DMA Channel 5 Registers */
303
304#define DMA5_NEXT_DESC_PTR 0xffc00d40 /* DMA Channel 5 Next Descriptor Pointer Register */
305#define DMA5_START_ADDR 0xffc00d44 /* DMA Channel 5 Start Address Register */
306#define DMA5_CONFIG 0xffc00d48 /* DMA Channel 5 Configuration Register */
307#define DMA5_X_COUNT 0xffc00d50 /* DMA Channel 5 X Count Register */
308#define DMA5_X_MODIFY 0xffc00d54 /* DMA Channel 5 X Modify Register */
309#define DMA5_Y_COUNT 0xffc00d58 /* DMA Channel 5 Y Count Register */
310#define DMA5_Y_MODIFY 0xffc00d5c /* DMA Channel 5 Y Modify Register */
311#define DMA5_CURR_DESC_PTR 0xffc00d60 /* DMA Channel 5 Current Descriptor Pointer Register */
312#define DMA5_CURR_ADDR 0xffc00d64 /* DMA Channel 5 Current Address Register */
313#define DMA5_IRQ_STATUS 0xffc00d68 /* DMA Channel 5 Interrupt/Status Register */
314#define DMA5_PERIPHERAL_MAP 0xffc00d6c /* DMA Channel 5 Peripheral Map Register */
315#define DMA5_CURR_X_COUNT 0xffc00d70 /* DMA Channel 5 Current X Count Register */
316#define DMA5_CURR_Y_COUNT 0xffc00d78 /* DMA Channel 5 Current Y Count Register */
317
318/* DMA Channel 6 Registers */
319
320#define DMA6_NEXT_DESC_PTR 0xffc00d80 /* DMA Channel 6 Next Descriptor Pointer Register */
321#define DMA6_START_ADDR 0xffc00d84 /* DMA Channel 6 Start Address Register */
322#define DMA6_CONFIG 0xffc00d88 /* DMA Channel 6 Configuration Register */
323#define DMA6_X_COUNT 0xffc00d90 /* DMA Channel 6 X Count Register */
324#define DMA6_X_MODIFY 0xffc00d94 /* DMA Channel 6 X Modify Register */
325#define DMA6_Y_COUNT 0xffc00d98 /* DMA Channel 6 Y Count Register */
326#define DMA6_Y_MODIFY 0xffc00d9c /* DMA Channel 6 Y Modify Register */
327#define DMA6_CURR_DESC_PTR 0xffc00da0 /* DMA Channel 6 Current Descriptor Pointer Register */
328#define DMA6_CURR_ADDR 0xffc00da4 /* DMA Channel 6 Current Address Register */
329#define DMA6_IRQ_STATUS 0xffc00da8 /* DMA Channel 6 Interrupt/Status Register */
330#define DMA6_PERIPHERAL_MAP 0xffc00dac /* DMA Channel 6 Peripheral Map Register */
331#define DMA6_CURR_X_COUNT 0xffc00db0 /* DMA Channel 6 Current X Count Register */
332#define DMA6_CURR_Y_COUNT 0xffc00db8 /* DMA Channel 6 Current Y Count Register */
333
334/* DMA Channel 7 Registers */
335
336#define DMA7_NEXT_DESC_PTR 0xffc00dc0 /* DMA Channel 7 Next Descriptor Pointer Register */
337#define DMA7_START_ADDR 0xffc00dc4 /* DMA Channel 7 Start Address Register */
338#define DMA7_CONFIG 0xffc00dc8 /* DMA Channel 7 Configuration Register */
339#define DMA7_X_COUNT 0xffc00dd0 /* DMA Channel 7 X Count Register */
340#define DMA7_X_MODIFY 0xffc00dd4 /* DMA Channel 7 X Modify Register */
341#define DMA7_Y_COUNT 0xffc00dd8 /* DMA Channel 7 Y Count Register */
342#define DMA7_Y_MODIFY 0xffc00ddc /* DMA Channel 7 Y Modify Register */
343#define DMA7_CURR_DESC_PTR 0xffc00de0 /* DMA Channel 7 Current Descriptor Pointer Register */
344#define DMA7_CURR_ADDR 0xffc00de4 /* DMA Channel 7 Current Address Register */
345#define DMA7_IRQ_STATUS 0xffc00de8 /* DMA Channel 7 Interrupt/Status Register */
346#define DMA7_PERIPHERAL_MAP 0xffc00dec /* DMA Channel 7 Peripheral Map Register */
347#define DMA7_CURR_X_COUNT 0xffc00df0 /* DMA Channel 7 Current X Count Register */
348#define DMA7_CURR_Y_COUNT 0xffc00df8 /* DMA Channel 7 Current Y Count Register */
349
350/* DMA Channel 8 Registers */
351
352#define DMA8_NEXT_DESC_PTR 0xffc00e00 /* DMA Channel 8 Next Descriptor Pointer Register */
353#define DMA8_START_ADDR 0xffc00e04 /* DMA Channel 8 Start Address Register */
354#define DMA8_CONFIG 0xffc00e08 /* DMA Channel 8 Configuration Register */
355#define DMA8_X_COUNT 0xffc00e10 /* DMA Channel 8 X Count Register */
356#define DMA8_X_MODIFY 0xffc00e14 /* DMA Channel 8 X Modify Register */
357#define DMA8_Y_COUNT 0xffc00e18 /* DMA Channel 8 Y Count Register */
358#define DMA8_Y_MODIFY 0xffc00e1c /* DMA Channel 8 Y Modify Register */
359#define DMA8_CURR_DESC_PTR 0xffc00e20 /* DMA Channel 8 Current Descriptor Pointer Register */
360#define DMA8_CURR_ADDR 0xffc00e24 /* DMA Channel 8 Current Address Register */
361#define DMA8_IRQ_STATUS 0xffc00e28 /* DMA Channel 8 Interrupt/Status Register */
362#define DMA8_PERIPHERAL_MAP 0xffc00e2c /* DMA Channel 8 Peripheral Map Register */
363#define DMA8_CURR_X_COUNT 0xffc00e30 /* DMA Channel 8 Current X Count Register */
364#define DMA8_CURR_Y_COUNT 0xffc00e38 /* DMA Channel 8 Current Y Count Register */
365
366/* DMA Channel 9 Registers */
367
368#define DMA9_NEXT_DESC_PTR 0xffc00e40 /* DMA Channel 9 Next Descriptor Pointer Register */
369#define DMA9_START_ADDR 0xffc00e44 /* DMA Channel 9 Start Address Register */
370#define DMA9_CONFIG 0xffc00e48 /* DMA Channel 9 Configuration Register */
371#define DMA9_X_COUNT 0xffc00e50 /* DMA Channel 9 X Count Register */
372#define DMA9_X_MODIFY 0xffc00e54 /* DMA Channel 9 X Modify Register */
373#define DMA9_Y_COUNT 0xffc00e58 /* DMA Channel 9 Y Count Register */
374#define DMA9_Y_MODIFY 0xffc00e5c /* DMA Channel 9 Y Modify Register */
375#define DMA9_CURR_DESC_PTR 0xffc00e60 /* DMA Channel 9 Current Descriptor Pointer Register */
376#define DMA9_CURR_ADDR 0xffc00e64 /* DMA Channel 9 Current Address Register */
377#define DMA9_IRQ_STATUS 0xffc00e68 /* DMA Channel 9 Interrupt/Status Register */
378#define DMA9_PERIPHERAL_MAP 0xffc00e6c /* DMA Channel 9 Peripheral Map Register */
379#define DMA9_CURR_X_COUNT 0xffc00e70 /* DMA Channel 9 Current X Count Register */
380#define DMA9_CURR_Y_COUNT 0xffc00e78 /* DMA Channel 9 Current Y Count Register */
381
382/* DMA Channel 10 Registers */
383
384#define DMA10_NEXT_DESC_PTR 0xffc00e80 /* DMA Channel 10 Next Descriptor Pointer Register */
385#define DMA10_START_ADDR 0xffc00e84 /* DMA Channel 10 Start Address Register */
386#define DMA10_CONFIG 0xffc00e88 /* DMA Channel 10 Configuration Register */
387#define DMA10_X_COUNT 0xffc00e90 /* DMA Channel 10 X Count Register */
388#define DMA10_X_MODIFY 0xffc00e94 /* DMA Channel 10 X Modify Register */
389#define DMA10_Y_COUNT 0xffc00e98 /* DMA Channel 10 Y Count Register */
390#define DMA10_Y_MODIFY 0xffc00e9c /* DMA Channel 10 Y Modify Register */
391#define DMA10_CURR_DESC_PTR 0xffc00ea0 /* DMA Channel 10 Current Descriptor Pointer Register */
392#define DMA10_CURR_ADDR 0xffc00ea4 /* DMA Channel 10 Current Address Register */
393#define DMA10_IRQ_STATUS 0xffc00ea8 /* DMA Channel 10 Interrupt/Status Register */
394#define DMA10_PERIPHERAL_MAP 0xffc00eac /* DMA Channel 10 Peripheral Map Register */
395#define DMA10_CURR_X_COUNT 0xffc00eb0 /* DMA Channel 10 Current X Count Register */
396#define DMA10_CURR_Y_COUNT 0xffc00eb8 /* DMA Channel 10 Current Y Count Register */
397
398/* DMA Channel 11 Registers */
399
400#define DMA11_NEXT_DESC_PTR 0xffc00ec0 /* DMA Channel 11 Next Descriptor Pointer Register */
401#define DMA11_START_ADDR 0xffc00ec4 /* DMA Channel 11 Start Address Register */
402#define DMA11_CONFIG 0xffc00ec8 /* DMA Channel 11 Configuration Register */
403#define DMA11_X_COUNT 0xffc00ed0 /* DMA Channel 11 X Count Register */
404#define DMA11_X_MODIFY 0xffc00ed4 /* DMA Channel 11 X Modify Register */
405#define DMA11_Y_COUNT 0xffc00ed8 /* DMA Channel 11 Y Count Register */
406#define DMA11_Y_MODIFY 0xffc00edc /* DMA Channel 11 Y Modify Register */
407#define DMA11_CURR_DESC_PTR 0xffc00ee0 /* DMA Channel 11 Current Descriptor Pointer Register */
408#define DMA11_CURR_ADDR 0xffc00ee4 /* DMA Channel 11 Current Address Register */
409#define DMA11_IRQ_STATUS 0xffc00ee8 /* DMA Channel 11 Interrupt/Status Register */
410#define DMA11_PERIPHERAL_MAP 0xffc00eec /* DMA Channel 11 Peripheral Map Register */
411#define DMA11_CURR_X_COUNT 0xffc00ef0 /* DMA Channel 11 Current X Count Register */
412#define DMA11_CURR_Y_COUNT 0xffc00ef8 /* DMA Channel 11 Current Y Count Register */
413
414/* MDMA Stream 0 Registers */
415
416#define MDMA_D0_NEXT_DESC_PTR 0xffc00f00 /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
417#define MDMA_D0_START_ADDR 0xffc00f04 /* Memory DMA Stream 0 Destination Start Address Register */
418#define MDMA_D0_CONFIG 0xffc00f08 /* Memory DMA Stream 0 Destination Configuration Register */
419#define MDMA_D0_X_COUNT 0xffc00f10 /* Memory DMA Stream 0 Destination X Count Register */
420#define MDMA_D0_X_MODIFY 0xffc00f14 /* Memory DMA Stream 0 Destination X Modify Register */
421#define MDMA_D0_Y_COUNT 0xffc00f18 /* Memory DMA Stream 0 Destination Y Count Register */
422#define MDMA_D0_Y_MODIFY 0xffc00f1c /* Memory DMA Stream 0 Destination Y Modify Register */
423#define MDMA_D0_CURR_DESC_PTR 0xffc00f20 /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
424#define MDMA_D0_CURR_ADDR 0xffc00f24 /* Memory DMA Stream 0 Destination Current Address Register */
425#define MDMA_D0_IRQ_STATUS 0xffc00f28 /* Memory DMA Stream 0 Destination Interrupt/Status Register */
426#define MDMA_D0_PERIPHERAL_MAP 0xffc00f2c /* Memory DMA Stream 0 Destination Peripheral Map Register */
427#define MDMA_D0_CURR_X_COUNT 0xffc00f30 /* Memory DMA Stream 0 Destination Current X Count Register */
428#define MDMA_D0_CURR_Y_COUNT 0xffc00f38 /* Memory DMA Stream 0 Destination Current Y Count Register */
429#define MDMA_S0_NEXT_DESC_PTR 0xffc00f40 /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
430#define MDMA_S0_START_ADDR 0xffc00f44 /* Memory DMA Stream 0 Source Start Address Register */
431#define MDMA_S0_CONFIG 0xffc00f48 /* Memory DMA Stream 0 Source Configuration Register */
432#define MDMA_S0_X_COUNT 0xffc00f50 /* Memory DMA Stream 0 Source X Count Register */
433#define MDMA_S0_X_MODIFY 0xffc00f54 /* Memory DMA Stream 0 Source X Modify Register */
434#define MDMA_S0_Y_COUNT 0xffc00f58 /* Memory DMA Stream 0 Source Y Count Register */
435#define MDMA_S0_Y_MODIFY 0xffc00f5c /* Memory DMA Stream 0 Source Y Modify Register */
436#define MDMA_S0_CURR_DESC_PTR 0xffc00f60 /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
437#define MDMA_S0_CURR_ADDR 0xffc00f64 /* Memory DMA Stream 0 Source Current Address Register */
438#define MDMA_S0_IRQ_STATUS 0xffc00f68 /* Memory DMA Stream 0 Source Interrupt/Status Register */
439#define MDMA_S0_PERIPHERAL_MAP 0xffc00f6c /* Memory DMA Stream 0 Source Peripheral Map Register */
440#define MDMA_S0_CURR_X_COUNT 0xffc00f70 /* Memory DMA Stream 0 Source Current X Count Register */
441#define MDMA_S0_CURR_Y_COUNT 0xffc00f78 /* Memory DMA Stream 0 Source Current Y Count Register */
442
443/* MDMA Stream 1 Registers */
444
445#define MDMA_D1_NEXT_DESC_PTR 0xffc00f80 /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
446#define MDMA_D1_START_ADDR 0xffc00f84 /* Memory DMA Stream 1 Destination Start Address Register */
447#define MDMA_D1_CONFIG 0xffc00f88 /* Memory DMA Stream 1 Destination Configuration Register */
448#define MDMA_D1_X_COUNT 0xffc00f90 /* Memory DMA Stream 1 Destination X Count Register */
449#define MDMA_D1_X_MODIFY 0xffc00f94 /* Memory DMA Stream 1 Destination X Modify Register */
450#define MDMA_D1_Y_COUNT 0xffc00f98 /* Memory DMA Stream 1 Destination Y Count Register */
451#define MDMA_D1_Y_MODIFY 0xffc00f9c /* Memory DMA Stream 1 Destination Y Modify Register */
452#define MDMA_D1_CURR_DESC_PTR 0xffc00fa0 /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
453#define MDMA_D1_CURR_ADDR 0xffc00fa4 /* Memory DMA Stream 1 Destination Current Address Register */
454#define MDMA_D1_IRQ_STATUS 0xffc00fa8 /* Memory DMA Stream 1 Destination Interrupt/Status Register */
455#define MDMA_D1_PERIPHERAL_MAP 0xffc00fac /* Memory DMA Stream 1 Destination Peripheral Map Register */
456#define MDMA_D1_CURR_X_COUNT 0xffc00fb0 /* Memory DMA Stream 1 Destination Current X Count Register */
457#define MDMA_D1_CURR_Y_COUNT 0xffc00fb8 /* Memory DMA Stream 1 Destination Current Y Count Register */
458#define MDMA_S1_NEXT_DESC_PTR 0xffc00fc0 /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
459#define MDMA_S1_START_ADDR 0xffc00fc4 /* Memory DMA Stream 1 Source Start Address Register */
460#define MDMA_S1_CONFIG 0xffc00fc8 /* Memory DMA Stream 1 Source Configuration Register */
461#define MDMA_S1_X_COUNT 0xffc00fd0 /* Memory DMA Stream 1 Source X Count Register */
462#define MDMA_S1_X_MODIFY 0xffc00fd4 /* Memory DMA Stream 1 Source X Modify Register */
463#define MDMA_S1_Y_COUNT 0xffc00fd8 /* Memory DMA Stream 1 Source Y Count Register */
464#define MDMA_S1_Y_MODIFY 0xffc00fdc /* Memory DMA Stream 1 Source Y Modify Register */
465#define MDMA_S1_CURR_DESC_PTR 0xffc00fe0 /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
466#define MDMA_S1_CURR_ADDR 0xffc00fe4 /* Memory DMA Stream 1 Source Current Address Register */
467#define MDMA_S1_IRQ_STATUS 0xffc00fe8 /* Memory DMA Stream 1 Source Interrupt/Status Register */
468#define MDMA_S1_PERIPHERAL_MAP 0xffc00fec /* Memory DMA Stream 1 Source Peripheral Map Register */
469#define MDMA_S1_CURR_X_COUNT 0xffc00ff0 /* Memory DMA Stream 1 Source Current X Count Register */
470#define MDMA_S1_CURR_Y_COUNT 0xffc00ff8 /* Memory DMA Stream 1 Source Current Y Count Register */
471
472/* UART3 Registers */
473
474#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
475#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
476#define UART3_GCTL 0xffc03108 /* Global Control Register */
477#define UART3_LCR 0xffc0310c /* Line Control Register */
478#define UART3_MCR 0xffc03110 /* Modem Control Register */
479#define UART3_LSR 0xffc03114 /* Line Status Register */
480#define UART3_MSR 0xffc03118 /* Modem Status Register */
481#define UART3_SCR 0xffc0311c /* Scratch Register */
482#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
483#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
484#define UART3_THR 0xffc03128 /* Transmit Hold Register */
485#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
486
487/* EPPI1 Registers */
488
489#define EPPI1_STATUS 0xffc01300 /* EPPI1 Status Register */
490#define EPPI1_HCOUNT 0xffc01304 /* EPPI1 Horizontal Transfer Count Register */
491#define EPPI1_HDELAY 0xffc01308 /* EPPI1 Horizontal Delay Count Register */
492#define EPPI1_VCOUNT 0xffc0130c /* EPPI1 Vertical Transfer Count Register */
493#define EPPI1_VDELAY 0xffc01310 /* EPPI1 Vertical Delay Count Register */
494#define EPPI1_FRAME 0xffc01314 /* EPPI1 Lines per Frame Register */
495#define EPPI1_LINE 0xffc01318 /* EPPI1 Samples per Line Register */
496#define EPPI1_CLKDIV 0xffc0131c /* EPPI1 Clock Divide Register */
497#define EPPI1_CONTROL 0xffc01320 /* EPPI1 Control Register */
498#define EPPI1_FS1W_HBL 0xffc01324 /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
499#define EPPI1_FS1P_AVPL 0xffc01328 /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
500#define EPPI1_FS2W_LVB 0xffc0132c /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
501#define EPPI1_FS2P_LAVF 0xffc01330 /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
502#define EPPI1_CLIP 0xffc01334 /* EPPI1 Clipping Register */
503
504/* Port Interrupt 0 Registers (32-bit) */
505
506#define PINT0_MASK_SET 0xffc01400 /* Pin Interrupt 0 Mask Set Register */
507#define PINT0_MASK_CLEAR 0xffc01404 /* Pin Interrupt 0 Mask Clear Register */
508#define PINT0_REQUEST 0xffc01408 /* Pin Interrupt 0 Interrupt Request Register */
509#define PINT0_ASSIGN 0xffc0140c /* Pin Interrupt 0 Port Assign Register */
510#define PINT0_EDGE_SET 0xffc01410 /* Pin Interrupt 0 Edge-sensitivity Set Register */
511#define PINT0_EDGE_CLEAR 0xffc01414 /* Pin Interrupt 0 Edge-sensitivity Clear Register */
512#define PINT0_INVERT_SET 0xffc01418 /* Pin Interrupt 0 Inversion Set Register */
513#define PINT0_INVERT_CLEAR 0xffc0141c /* Pin Interrupt 0 Inversion Clear Register */
514#define PINT0_PINSTATE 0xffc01420 /* Pin Interrupt 0 Pin Status Register */
515#define PINT0_LATCH 0xffc01424 /* Pin Interrupt 0 Latch Register */
516
517/* Port Interrupt 1 Registers (32-bit) */
518
519#define PINT1_MASK_SET 0xffc01430 /* Pin Interrupt 1 Mask Set Register */
520#define PINT1_MASK_CLEAR 0xffc01434 /* Pin Interrupt 1 Mask Clear Register */
521#define PINT1_REQUEST 0xffc01438 /* Pin Interrupt 1 Interrupt Request Register */
522#define PINT1_ASSIGN 0xffc0143c /* Pin Interrupt 1 Port Assign Register */
523#define PINT1_EDGE_SET 0xffc01440 /* Pin Interrupt 1 Edge-sensitivity Set Register */
524#define PINT1_EDGE_CLEAR 0xffc01444 /* Pin Interrupt 1 Edge-sensitivity Clear Register */
525#define PINT1_INVERT_SET 0xffc01448 /* Pin Interrupt 1 Inversion Set Register */
526#define PINT1_INVERT_CLEAR 0xffc0144c /* Pin Interrupt 1 Inversion Clear Register */
527#define PINT1_PINSTATE 0xffc01450 /* Pin Interrupt 1 Pin Status Register */
528#define PINT1_LATCH 0xffc01454 /* Pin Interrupt 1 Latch Register */
529
530/* Port Interrupt 2 Registers (32-bit) */
531
532#define PINT2_MASK_SET 0xffc01460 /* Pin Interrupt 2 Mask Set Register */
533#define PINT2_MASK_CLEAR 0xffc01464 /* Pin Interrupt 2 Mask Clear Register */
534#define PINT2_REQUEST 0xffc01468 /* Pin Interrupt 2 Interrupt Request Register */
535#define PINT2_ASSIGN 0xffc0146c /* Pin Interrupt 2 Port Assign Register */
536#define PINT2_EDGE_SET 0xffc01470 /* Pin Interrupt 2 Edge-sensitivity Set Register */
537#define PINT2_EDGE_CLEAR 0xffc01474 /* Pin Interrupt 2 Edge-sensitivity Clear Register */
538#define PINT2_INVERT_SET 0xffc01478 /* Pin Interrupt 2 Inversion Set Register */
539#define PINT2_INVERT_CLEAR 0xffc0147c /* Pin Interrupt 2 Inversion Clear Register */
540#define PINT2_PINSTATE 0xffc01480 /* Pin Interrupt 2 Pin Status Register */
541#define PINT2_LATCH 0xffc01484 /* Pin Interrupt 2 Latch Register */
542
543/* Port Interrupt 3 Registers (32-bit) */
544
545#define PINT3_MASK_SET 0xffc01490 /* Pin Interrupt 3 Mask Set Register */
546#define PINT3_MASK_CLEAR 0xffc01494 /* Pin Interrupt 3 Mask Clear Register */
547#define PINT3_REQUEST 0xffc01498 /* Pin Interrupt 3 Interrupt Request Register */
548#define PINT3_ASSIGN 0xffc0149c /* Pin Interrupt 3 Port Assign Register */
549#define PINT3_EDGE_SET 0xffc014a0 /* Pin Interrupt 3 Edge-sensitivity Set Register */
550#define PINT3_EDGE_CLEAR 0xffc014a4 /* Pin Interrupt 3 Edge-sensitivity Clear Register */
551#define PINT3_INVERT_SET 0xffc014a8 /* Pin Interrupt 3 Inversion Set Register */
552#define PINT3_INVERT_CLEAR 0xffc014ac /* Pin Interrupt 3 Inversion Clear Register */
553#define PINT3_PINSTATE 0xffc014b0 /* Pin Interrupt 3 Pin Status Register */
554#define PINT3_LATCH 0xffc014b4 /* Pin Interrupt 3 Latch Register */
555
556/* Port A Registers */
557
558#define PORTA_FER 0xffc014c0 /* Function Enable Register */
559#define PORTA 0xffc014c4 /* GPIO Data Register */
560#define PORTA_SET 0xffc014c8 /* GPIO Data Set Register */
561#define PORTA_CLEAR 0xffc014cc /* GPIO Data Clear Register */
562#define PORTA_DIR_SET 0xffc014d0 /* GPIO Direction Set Register */
563#define PORTA_DIR_CLEAR 0xffc014d4 /* GPIO Direction Clear Register */
564#define PORTA_INEN 0xffc014d8 /* GPIO Input Enable Register */
565#define PORTA_MUX 0xffc014dc /* Multiplexer Control Register */
566
567/* Port B Registers */
568
569#define PORTB_FER 0xffc014e0 /* Function Enable Register */
570#define PORTB 0xffc014e4 /* GPIO Data Register */
571#define PORTB_SET 0xffc014e8 /* GPIO Data Set Register */
572#define PORTB_CLEAR 0xffc014ec /* GPIO Data Clear Register */
573#define PORTB_DIR_SET 0xffc014f0 /* GPIO Direction Set Register */
574#define PORTB_DIR_CLEAR 0xffc014f4 /* GPIO Direction Clear Register */
575#define PORTB_INEN 0xffc014f8 /* GPIO Input Enable Register */
576#define PORTB_MUX 0xffc014fc /* Multiplexer Control Register */
577
578/* Port C Registers */
579
580#define PORTC_FER 0xffc01500 /* Function Enable Register */
581#define PORTC 0xffc01504 /* GPIO Data Register */
582#define PORTC_SET 0xffc01508 /* GPIO Data Set Register */
583#define PORTC_CLEAR 0xffc0150c /* GPIO Data Clear Register */
584#define PORTC_DIR_SET 0xffc01510 /* GPIO Direction Set Register */
585#define PORTC_DIR_CLEAR 0xffc01514 /* GPIO Direction Clear Register */
586#define PORTC_INEN 0xffc01518 /* GPIO Input Enable Register */
587#define PORTC_MUX 0xffc0151c /* Multiplexer Control Register */
588
589/* Port D Registers */
590
591#define PORTD_FER 0xffc01520 /* Function Enable Register */
592#define PORTD 0xffc01524 /* GPIO Data Register */
593#define PORTD_SET 0xffc01528 /* GPIO Data Set Register */
594#define PORTD_CLEAR 0xffc0152c /* GPIO Data Clear Register */
595#define PORTD_DIR_SET 0xffc01530 /* GPIO Direction Set Register */
596#define PORTD_DIR_CLEAR 0xffc01534 /* GPIO Direction Clear Register */
597#define PORTD_INEN 0xffc01538 /* GPIO Input Enable Register */
598#define PORTD_MUX 0xffc0153c /* Multiplexer Control Register */
599
600/* Port E Registers */
601
602#define PORTE_FER 0xffc01540 /* Function Enable Register */
603#define PORTE 0xffc01544 /* GPIO Data Register */
604#define PORTE_SET 0xffc01548 /* GPIO Data Set Register */
605#define PORTE_CLEAR 0xffc0154c /* GPIO Data Clear Register */
606#define PORTE_DIR_SET 0xffc01550 /* GPIO Direction Set Register */
607#define PORTE_DIR_CLEAR 0xffc01554 /* GPIO Direction Clear Register */
608#define PORTE_INEN 0xffc01558 /* GPIO Input Enable Register */
609#define PORTE_MUX 0xffc0155c /* Multiplexer Control Register */
610
611/* Port F Registers */
612
613#define PORTF_FER 0xffc01560 /* Function Enable Register */
614#define PORTF 0xffc01564 /* GPIO Data Register */
615#define PORTF_SET 0xffc01568 /* GPIO Data Set Register */
616#define PORTF_CLEAR 0xffc0156c /* GPIO Data Clear Register */
617#define PORTF_DIR_SET 0xffc01570 /* GPIO Direction Set Register */
618#define PORTF_DIR_CLEAR 0xffc01574 /* GPIO Direction Clear Register */
619#define PORTF_INEN 0xffc01578 /* GPIO Input Enable Register */
620#define PORTF_MUX 0xffc0157c /* Multiplexer Control Register */
621
622/* Port G Registers */
623
624#define PORTG_FER 0xffc01580 /* Function Enable Register */
625#define PORTG 0xffc01584 /* GPIO Data Register */
626#define PORTG_SET 0xffc01588 /* GPIO Data Set Register */
627#define PORTG_CLEAR 0xffc0158c /* GPIO Data Clear Register */
628#define PORTG_DIR_SET 0xffc01590 /* GPIO Direction Set Register */
629#define PORTG_DIR_CLEAR 0xffc01594 /* GPIO Direction Clear Register */
630#define PORTG_INEN 0xffc01598 /* GPIO Input Enable Register */
631#define PORTG_MUX 0xffc0159c /* Multiplexer Control Register */
632
633/* Port H Registers */
634
635#define PORTH_FER 0xffc015a0 /* Function Enable Register */
636#define PORTH 0xffc015a4 /* GPIO Data Register */
637#define PORTH_SET 0xffc015a8 /* GPIO Data Set Register */
638#define PORTH_CLEAR 0xffc015ac /* GPIO Data Clear Register */
639#define PORTH_DIR_SET 0xffc015b0 /* GPIO Direction Set Register */
640#define PORTH_DIR_CLEAR 0xffc015b4 /* GPIO Direction Clear Register */
641#define PORTH_INEN 0xffc015b8 /* GPIO Input Enable Register */
642#define PORTH_MUX 0xffc015bc /* Multiplexer Control Register */
643
644/* Port I Registers */
645
646#define PORTI_FER 0xffc015c0 /* Function Enable Register */
647#define PORTI 0xffc015c4 /* GPIO Data Register */
648#define PORTI_SET 0xffc015c8 /* GPIO Data Set Register */
649#define PORTI_CLEAR 0xffc015cc /* GPIO Data Clear Register */
650#define PORTI_DIR_SET 0xffc015d0 /* GPIO Direction Set Register */
651#define PORTI_DIR_CLEAR 0xffc015d4 /* GPIO Direction Clear Register */
652#define PORTI_INEN 0xffc015d8 /* GPIO Input Enable Register */
653#define PORTI_MUX 0xffc015dc /* Multiplexer Control Register */
654
655/* Port J Registers */
656
657#define PORTJ_FER 0xffc015e0 /* Function Enable Register */
658#define PORTJ 0xffc015e4 /* GPIO Data Register */
659#define PORTJ_SET 0xffc015e8 /* GPIO Data Set Register */
660#define PORTJ_CLEAR 0xffc015ec /* GPIO Data Clear Register */
661#define PORTJ_DIR_SET 0xffc015f0 /* GPIO Direction Set Register */
662#define PORTJ_DIR_CLEAR 0xffc015f4 /* GPIO Direction Clear Register */
663#define PORTJ_INEN 0xffc015f8 /* GPIO Input Enable Register */
664#define PORTJ_MUX 0xffc015fc /* Multiplexer Control Register */
665
666/* PWM Timer Registers */
667
668#define TIMER0_CONFIG 0xffc01600 /* Timer 0 Configuration Register */
669#define TIMER0_COUNTER 0xffc01604 /* Timer 0 Counter Register */
670#define TIMER0_PERIOD 0xffc01608 /* Timer 0 Period Register */
671#define TIMER0_WIDTH 0xffc0160c /* Timer 0 Width Register */
672#define TIMER1_CONFIG 0xffc01610 /* Timer 1 Configuration Register */
673#define TIMER1_COUNTER 0xffc01614 /* Timer 1 Counter Register */
674#define TIMER1_PERIOD 0xffc01618 /* Timer 1 Period Register */
675#define TIMER1_WIDTH 0xffc0161c /* Timer 1 Width Register */
676#define TIMER2_CONFIG 0xffc01620 /* Timer 2 Configuration Register */
677#define TIMER2_COUNTER 0xffc01624 /* Timer 2 Counter Register */
678#define TIMER2_PERIOD 0xffc01628 /* Timer 2 Period Register */
679#define TIMER2_WIDTH 0xffc0162c /* Timer 2 Width Register */
680#define TIMER3_CONFIG 0xffc01630 /* Timer 3 Configuration Register */
681#define TIMER3_COUNTER 0xffc01634 /* Timer 3 Counter Register */
682#define TIMER3_PERIOD 0xffc01638 /* Timer 3 Period Register */
683#define TIMER3_WIDTH 0xffc0163c /* Timer 3 Width Register */
684#define TIMER4_CONFIG 0xffc01640 /* Timer 4 Configuration Register */
685#define TIMER4_COUNTER 0xffc01644 /* Timer 4 Counter Register */
686#define TIMER4_PERIOD 0xffc01648 /* Timer 4 Period Register */
687#define TIMER4_WIDTH 0xffc0164c /* Timer 4 Width Register */
688#define TIMER5_CONFIG 0xffc01650 /* Timer 5 Configuration Register */
689#define TIMER5_COUNTER 0xffc01654 /* Timer 5 Counter Register */
690#define TIMER5_PERIOD 0xffc01658 /* Timer 5 Period Register */
691#define TIMER5_WIDTH 0xffc0165c /* Timer 5 Width Register */
692#define TIMER6_CONFIG 0xffc01660 /* Timer 6 Configuration Register */
693#define TIMER6_COUNTER 0xffc01664 /* Timer 6 Counter Register */
694#define TIMER6_PERIOD 0xffc01668 /* Timer 6 Period Register */
695#define TIMER6_WIDTH 0xffc0166c /* Timer 6 Width Register */
696#define TIMER7_CONFIG 0xffc01670 /* Timer 7 Configuration Register */
697#define TIMER7_COUNTER 0xffc01674 /* Timer 7 Counter Register */
698#define TIMER7_PERIOD 0xffc01678 /* Timer 7 Period Register */
699#define TIMER7_WIDTH 0xffc0167c /* Timer 7 Width Register */
700
701/* Timer Group of 8 */
702
703#define TIMER_ENABLE0 0xffc01680 /* Timer Group of 8 Enable Register */
704#define TIMER_DISABLE0 0xffc01684 /* Timer Group of 8 Disable Register */
705#define TIMER_STATUS0 0xffc01688 /* Timer Group of 8 Status Register */
706
707/* DMAC1 Registers */
708
709#define DMAC1_TCPER 0xffc01b0c /* DMA Controller 1 Traffic Control Periods Register */
710#define DMAC1_TCCNT 0xffc01b10 /* DMA Controller 1 Current Counts Register */
711
712/* DMA Channel 12 Registers */
713
714#define DMA12_NEXT_DESC_PTR 0xffc01c00 /* DMA Channel 12 Next Descriptor Pointer Register */
715#define DMA12_START_ADDR 0xffc01c04 /* DMA Channel 12 Start Address Register */
716#define DMA12_CONFIG 0xffc01c08 /* DMA Channel 12 Configuration Register */
717#define DMA12_X_COUNT 0xffc01c10 /* DMA Channel 12 X Count Register */
718#define DMA12_X_MODIFY 0xffc01c14 /* DMA Channel 12 X Modify Register */
719#define DMA12_Y_COUNT 0xffc01c18 /* DMA Channel 12 Y Count Register */
720#define DMA12_Y_MODIFY 0xffc01c1c /* DMA Channel 12 Y Modify Register */
721#define DMA12_CURR_DESC_PTR 0xffc01c20 /* DMA Channel 12 Current Descriptor Pointer Register */
722#define DMA12_CURR_ADDR 0xffc01c24 /* DMA Channel 12 Current Address Register */
723#define DMA12_IRQ_STATUS 0xffc01c28 /* DMA Channel 12 Interrupt/Status Register */
724#define DMA12_PERIPHERAL_MAP 0xffc01c2c /* DMA Channel 12 Peripheral Map Register */
725#define DMA12_CURR_X_COUNT 0xffc01c30 /* DMA Channel 12 Current X Count Register */
726#define DMA12_CURR_Y_COUNT 0xffc01c38 /* DMA Channel 12 Current Y Count Register */
727
728/* DMA Channel 13 Registers */
729
730#define DMA13_NEXT_DESC_PTR 0xffc01c40 /* DMA Channel 13 Next Descriptor Pointer Register */
731#define DMA13_START_ADDR 0xffc01c44 /* DMA Channel 13 Start Address Register */
732#define DMA13_CONFIG 0xffc01c48 /* DMA Channel 13 Configuration Register */
733#define DMA13_X_COUNT 0xffc01c50 /* DMA Channel 13 X Count Register */
734#define DMA13_X_MODIFY 0xffc01c54 /* DMA Channel 13 X Modify Register */
735#define DMA13_Y_COUNT 0xffc01c58 /* DMA Channel 13 Y Count Register */
736#define DMA13_Y_MODIFY 0xffc01c5c /* DMA Channel 13 Y Modify Register */
737#define DMA13_CURR_DESC_PTR 0xffc01c60 /* DMA Channel 13 Current Descriptor Pointer Register */
738#define DMA13_CURR_ADDR 0xffc01c64 /* DMA Channel 13 Current Address Register */
739#define DMA13_IRQ_STATUS 0xffc01c68 /* DMA Channel 13 Interrupt/Status Register */
740#define DMA13_PERIPHERAL_MAP 0xffc01c6c /* DMA Channel 13 Peripheral Map Register */
741#define DMA13_CURR_X_COUNT 0xffc01c70 /* DMA Channel 13 Current X Count Register */
742#define DMA13_CURR_Y_COUNT 0xffc01c78 /* DMA Channel 13 Current Y Count Register */
743
744/* DMA Channel 14 Registers */
745
746#define DMA14_NEXT_DESC_PTR 0xffc01c80 /* DMA Channel 14 Next Descriptor Pointer Register */
747#define DMA14_START_ADDR 0xffc01c84 /* DMA Channel 14 Start Address Register */
748#define DMA14_CONFIG 0xffc01c88 /* DMA Channel 14 Configuration Register */
749#define DMA14_X_COUNT 0xffc01c90 /* DMA Channel 14 X Count Register */
750#define DMA14_X_MODIFY 0xffc01c94 /* DMA Channel 14 X Modify Register */
751#define DMA14_Y_COUNT 0xffc01c98 /* DMA Channel 14 Y Count Register */
752#define DMA14_Y_MODIFY 0xffc01c9c /* DMA Channel 14 Y Modify Register */
753#define DMA14_CURR_DESC_PTR 0xffc01ca0 /* DMA Channel 14 Current Descriptor Pointer Register */
754#define DMA14_CURR_ADDR 0xffc01ca4 /* DMA Channel 14 Current Address Register */
755#define DMA14_IRQ_STATUS 0xffc01ca8 /* DMA Channel 14 Interrupt/Status Register */
756#define DMA14_PERIPHERAL_MAP 0xffc01cac /* DMA Channel 14 Peripheral Map Register */
757#define DMA14_CURR_X_COUNT 0xffc01cb0 /* DMA Channel 14 Current X Count Register */
758#define DMA14_CURR_Y_COUNT 0xffc01cb8 /* DMA Channel 14 Current Y Count Register */
759
760/* DMA Channel 15 Registers */
761
762#define DMA15_NEXT_DESC_PTR 0xffc01cc0 /* DMA Channel 15 Next Descriptor Pointer Register */
763#define DMA15_START_ADDR 0xffc01cc4 /* DMA Channel 15 Start Address Register */
764#define DMA15_CONFIG 0xffc01cc8 /* DMA Channel 15 Configuration Register */
765#define DMA15_X_COUNT 0xffc01cd0 /* DMA Channel 15 X Count Register */
766#define DMA15_X_MODIFY 0xffc01cd4 /* DMA Channel 15 X Modify Register */
767#define DMA15_Y_COUNT 0xffc01cd8 /* DMA Channel 15 Y Count Register */
768#define DMA15_Y_MODIFY 0xffc01cdc /* DMA Channel 15 Y Modify Register */
769#define DMA15_CURR_DESC_PTR 0xffc01ce0 /* DMA Channel 15 Current Descriptor Pointer Register */
770#define DMA15_CURR_ADDR 0xffc01ce4 /* DMA Channel 15 Current Address Register */
771#define DMA15_IRQ_STATUS 0xffc01ce8 /* DMA Channel 15 Interrupt/Status Register */
772#define DMA15_PERIPHERAL_MAP 0xffc01cec /* DMA Channel 15 Peripheral Map Register */
773#define DMA15_CURR_X_COUNT 0xffc01cf0 /* DMA Channel 15 Current X Count Register */
774#define DMA15_CURR_Y_COUNT 0xffc01cf8 /* DMA Channel 15 Current Y Count Register */
775
776/* DMA Channel 16 Registers */
777
778#define DMA16_NEXT_DESC_PTR 0xffc01d00 /* DMA Channel 16 Next Descriptor Pointer Register */
779#define DMA16_START_ADDR 0xffc01d04 /* DMA Channel 16 Start Address Register */
780#define DMA16_CONFIG 0xffc01d08 /* DMA Channel 16 Configuration Register */
781#define DMA16_X_COUNT 0xffc01d10 /* DMA Channel 16 X Count Register */
782#define DMA16_X_MODIFY 0xffc01d14 /* DMA Channel 16 X Modify Register */
783#define DMA16_Y_COUNT 0xffc01d18 /* DMA Channel 16 Y Count Register */
784#define DMA16_Y_MODIFY 0xffc01d1c /* DMA Channel 16 Y Modify Register */
785#define DMA16_CURR_DESC_PTR 0xffc01d20 /* DMA Channel 16 Current Descriptor Pointer Register */
786#define DMA16_CURR_ADDR 0xffc01d24 /* DMA Channel 16 Current Address Register */
787#define DMA16_IRQ_STATUS 0xffc01d28 /* DMA Channel 16 Interrupt/Status Register */
788#define DMA16_PERIPHERAL_MAP 0xffc01d2c /* DMA Channel 16 Peripheral Map Register */
789#define DMA16_CURR_X_COUNT 0xffc01d30 /* DMA Channel 16 Current X Count Register */
790#define DMA16_CURR_Y_COUNT 0xffc01d38 /* DMA Channel 16 Current Y Count Register */
791
792/* DMA Channel 17 Registers */
793
794#define DMA17_NEXT_DESC_PTR 0xffc01d40 /* DMA Channel 17 Next Descriptor Pointer Register */
795#define DMA17_START_ADDR 0xffc01d44 /* DMA Channel 17 Start Address Register */
796#define DMA17_CONFIG 0xffc01d48 /* DMA Channel 17 Configuration Register */
797#define DMA17_X_COUNT 0xffc01d50 /* DMA Channel 17 X Count Register */
798#define DMA17_X_MODIFY 0xffc01d54 /* DMA Channel 17 X Modify Register */
799#define DMA17_Y_COUNT 0xffc01d58 /* DMA Channel 17 Y Count Register */
800#define DMA17_Y_MODIFY 0xffc01d5c /* DMA Channel 17 Y Modify Register */
801#define DMA17_CURR_DESC_PTR 0xffc01d60 /* DMA Channel 17 Current Descriptor Pointer Register */
802#define DMA17_CURR_ADDR 0xffc01d64 /* DMA Channel 17 Current Address Register */
803#define DMA17_IRQ_STATUS 0xffc01d68 /* DMA Channel 17 Interrupt/Status Register */
804#define DMA17_PERIPHERAL_MAP 0xffc01d6c /* DMA Channel 17 Peripheral Map Register */
805#define DMA17_CURR_X_COUNT 0xffc01d70 /* DMA Channel 17 Current X Count Register */
806#define DMA17_CURR_Y_COUNT 0xffc01d78 /* DMA Channel 17 Current Y Count Register */
807
808/* DMA Channel 18 Registers */
809
810#define DMA18_NEXT_DESC_PTR 0xffc01d80 /* DMA Channel 18 Next Descriptor Pointer Register */
811#define DMA18_START_ADDR 0xffc01d84 /* DMA Channel 18 Start Address Register */
812#define DMA18_CONFIG 0xffc01d88 /* DMA Channel 18 Configuration Register */
813#define DMA18_X_COUNT 0xffc01d90 /* DMA Channel 18 X Count Register */
814#define DMA18_X_MODIFY 0xffc01d94 /* DMA Channel 18 X Modify Register */
815#define DMA18_Y_COUNT 0xffc01d98 /* DMA Channel 18 Y Count Register */
816#define DMA18_Y_MODIFY 0xffc01d9c /* DMA Channel 18 Y Modify Register */
817#define DMA18_CURR_DESC_PTR 0xffc01da0 /* DMA Channel 18 Current Descriptor Pointer Register */
818#define DMA18_CURR_ADDR 0xffc01da4 /* DMA Channel 18 Current Address Register */
819#define DMA18_IRQ_STATUS 0xffc01da8 /* DMA Channel 18 Interrupt/Status Register */
820#define DMA18_PERIPHERAL_MAP 0xffc01dac /* DMA Channel 18 Peripheral Map Register */
821#define DMA18_CURR_X_COUNT 0xffc01db0 /* DMA Channel 18 Current X Count Register */
822#define DMA18_CURR_Y_COUNT 0xffc01db8 /* DMA Channel 18 Current Y Count Register */
823
824/* DMA Channel 19 Registers */
825
826#define DMA19_NEXT_DESC_PTR 0xffc01dc0 /* DMA Channel 19 Next Descriptor Pointer Register */
827#define DMA19_START_ADDR 0xffc01dc4 /* DMA Channel 19 Start Address Register */
828#define DMA19_CONFIG 0xffc01dc8 /* DMA Channel 19 Configuration Register */
829#define DMA19_X_COUNT 0xffc01dd0 /* DMA Channel 19 X Count Register */
830#define DMA19_X_MODIFY 0xffc01dd4 /* DMA Channel 19 X Modify Register */
831#define DMA19_Y_COUNT 0xffc01dd8 /* DMA Channel 19 Y Count Register */
832#define DMA19_Y_MODIFY 0xffc01ddc /* DMA Channel 19 Y Modify Register */
833#define DMA19_CURR_DESC_PTR 0xffc01de0 /* DMA Channel 19 Current Descriptor Pointer Register */
834#define DMA19_CURR_ADDR 0xffc01de4 /* DMA Channel 19 Current Address Register */
835#define DMA19_IRQ_STATUS 0xffc01de8 /* DMA Channel 19 Interrupt/Status Register */
836#define DMA19_PERIPHERAL_MAP 0xffc01dec /* DMA Channel 19 Peripheral Map Register */
837#define DMA19_CURR_X_COUNT 0xffc01df0 /* DMA Channel 19 Current X Count Register */
838#define DMA19_CURR_Y_COUNT 0xffc01df8 /* DMA Channel 19 Current Y Count Register */
839
840/* DMA Channel 20 Registers */
841
842#define DMA20_NEXT_DESC_PTR 0xffc01e00 /* DMA Channel 20 Next Descriptor Pointer Register */
843#define DMA20_START_ADDR 0xffc01e04 /* DMA Channel 20 Start Address Register */
844#define DMA20_CONFIG 0xffc01e08 /* DMA Channel 20 Configuration Register */
845#define DMA20_X_COUNT 0xffc01e10 /* DMA Channel 20 X Count Register */
846#define DMA20_X_MODIFY 0xffc01e14 /* DMA Channel 20 X Modify Register */
847#define DMA20_Y_COUNT 0xffc01e18 /* DMA Channel 20 Y Count Register */
848#define DMA20_Y_MODIFY 0xffc01e1c /* DMA Channel 20 Y Modify Register */
849#define DMA20_CURR_DESC_PTR 0xffc01e20 /* DMA Channel 20 Current Descriptor Pointer Register */
850#define DMA20_CURR_ADDR 0xffc01e24 /* DMA Channel 20 Current Address Register */
851#define DMA20_IRQ_STATUS 0xffc01e28 /* DMA Channel 20 Interrupt/Status Register */
852#define DMA20_PERIPHERAL_MAP 0xffc01e2c /* DMA Channel 20 Peripheral Map Register */
853#define DMA20_CURR_X_COUNT 0xffc01e30 /* DMA Channel 20 Current X Count Register */
854#define DMA20_CURR_Y_COUNT 0xffc01e38 /* DMA Channel 20 Current Y Count Register */
855
856/* DMA Channel 21 Registers */
857
858#define DMA21_NEXT_DESC_PTR 0xffc01e40 /* DMA Channel 21 Next Descriptor Pointer Register */
859#define DMA21_START_ADDR 0xffc01e44 /* DMA Channel 21 Start Address Register */
860#define DMA21_CONFIG 0xffc01e48 /* DMA Channel 21 Configuration Register */
861#define DMA21_X_COUNT 0xffc01e50 /* DMA Channel 21 X Count Register */
862#define DMA21_X_MODIFY 0xffc01e54 /* DMA Channel 21 X Modify Register */
863#define DMA21_Y_COUNT 0xffc01e58 /* DMA Channel 21 Y Count Register */
864#define DMA21_Y_MODIFY 0xffc01e5c /* DMA Channel 21 Y Modify Register */
865#define DMA21_CURR_DESC_PTR 0xffc01e60 /* DMA Channel 21 Current Descriptor Pointer Register */
866#define DMA21_CURR_ADDR 0xffc01e64 /* DMA Channel 21 Current Address Register */
867#define DMA21_IRQ_STATUS 0xffc01e68 /* DMA Channel 21 Interrupt/Status Register */
868#define DMA21_PERIPHERAL_MAP 0xffc01e6c /* DMA Channel 21 Peripheral Map Register */
869#define DMA21_CURR_X_COUNT 0xffc01e70 /* DMA Channel 21 Current X Count Register */
870#define DMA21_CURR_Y_COUNT 0xffc01e78 /* DMA Channel 21 Current Y Count Register */
871
872/* DMA Channel 22 Registers */
873
874#define DMA22_NEXT_DESC_PTR 0xffc01e80 /* DMA Channel 22 Next Descriptor Pointer Register */
875#define DMA22_START_ADDR 0xffc01e84 /* DMA Channel 22 Start Address Register */
876#define DMA22_CONFIG 0xffc01e88 /* DMA Channel 22 Configuration Register */
877#define DMA22_X_COUNT 0xffc01e90 /* DMA Channel 22 X Count Register */
878#define DMA22_X_MODIFY 0xffc01e94 /* DMA Channel 22 X Modify Register */
879#define DMA22_Y_COUNT 0xffc01e98 /* DMA Channel 22 Y Count Register */
880#define DMA22_Y_MODIFY 0xffc01e9c /* DMA Channel 22 Y Modify Register */
881#define DMA22_CURR_DESC_PTR 0xffc01ea0 /* DMA Channel 22 Current Descriptor Pointer Register */
882#define DMA22_CURR_ADDR 0xffc01ea4 /* DMA Channel 22 Current Address Register */
883#define DMA22_IRQ_STATUS 0xffc01ea8 /* DMA Channel 22 Interrupt/Status Register */
884#define DMA22_PERIPHERAL_MAP 0xffc01eac /* DMA Channel 22 Peripheral Map Register */
885#define DMA22_CURR_X_COUNT 0xffc01eb0 /* DMA Channel 22 Current X Count Register */
886#define DMA22_CURR_Y_COUNT 0xffc01eb8 /* DMA Channel 22 Current Y Count Register */
887
888/* DMA Channel 23 Registers */
889
890#define DMA23_NEXT_DESC_PTR 0xffc01ec0 /* DMA Channel 23 Next Descriptor Pointer Register */
891#define DMA23_START_ADDR 0xffc01ec4 /* DMA Channel 23 Start Address Register */
892#define DMA23_CONFIG 0xffc01ec8 /* DMA Channel 23 Configuration Register */
893#define DMA23_X_COUNT 0xffc01ed0 /* DMA Channel 23 X Count Register */
894#define DMA23_X_MODIFY 0xffc01ed4 /* DMA Channel 23 X Modify Register */
895#define DMA23_Y_COUNT 0xffc01ed8 /* DMA Channel 23 Y Count Register */
896#define DMA23_Y_MODIFY 0xffc01edc /* DMA Channel 23 Y Modify Register */
897#define DMA23_CURR_DESC_PTR 0xffc01ee0 /* DMA Channel 23 Current Descriptor Pointer Register */
898#define DMA23_CURR_ADDR 0xffc01ee4 /* DMA Channel 23 Current Address Register */
899#define DMA23_IRQ_STATUS 0xffc01ee8 /* DMA Channel 23 Interrupt/Status Register */
900#define DMA23_PERIPHERAL_MAP 0xffc01eec /* DMA Channel 23 Peripheral Map Register */
901#define DMA23_CURR_X_COUNT 0xffc01ef0 /* DMA Channel 23 Current X Count Register */
902#define DMA23_CURR_Y_COUNT 0xffc01ef8 /* DMA Channel 23 Current Y Count Register */
903
904/* MDMA Stream 2 Registers */
905
906#define MDMA_D2_NEXT_DESC_PTR 0xffc01f00 /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
907#define MDMA_D2_START_ADDR 0xffc01f04 /* Memory DMA Stream 2 Destination Start Address Register */
908#define MDMA_D2_CONFIG 0xffc01f08 /* Memory DMA Stream 2 Destination Configuration Register */
909#define MDMA_D2_X_COUNT 0xffc01f10 /* Memory DMA Stream 2 Destination X Count Register */
910#define MDMA_D2_X_MODIFY 0xffc01f14 /* Memory DMA Stream 2 Destination X Modify Register */
911#define MDMA_D2_Y_COUNT 0xffc01f18 /* Memory DMA Stream 2 Destination Y Count Register */
912#define MDMA_D2_Y_MODIFY 0xffc01f1c /* Memory DMA Stream 2 Destination Y Modify Register */
913#define MDMA_D2_CURR_DESC_PTR 0xffc01f20 /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
914#define MDMA_D2_CURR_ADDR 0xffc01f24 /* Memory DMA Stream 2 Destination Current Address Register */
915#define MDMA_D2_IRQ_STATUS 0xffc01f28 /* Memory DMA Stream 2 Destination Interrupt/Status Register */
916#define MDMA_D2_PERIPHERAL_MAP 0xffc01f2c /* Memory DMA Stream 2 Destination Peripheral Map Register */
917#define MDMA_D2_CURR_X_COUNT 0xffc01f30 /* Memory DMA Stream 2 Destination Current X Count Register */
918#define MDMA_D2_CURR_Y_COUNT 0xffc01f38 /* Memory DMA Stream 2 Destination Current Y Count Register */
919#define MDMA_S2_NEXT_DESC_PTR 0xffc01f40 /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
920#define MDMA_S2_START_ADDR 0xffc01f44 /* Memory DMA Stream 2 Source Start Address Register */
921#define MDMA_S2_CONFIG 0xffc01f48 /* Memory DMA Stream 2 Source Configuration Register */
922#define MDMA_S2_X_COUNT 0xffc01f50 /* Memory DMA Stream 2 Source X Count Register */
923#define MDMA_S2_X_MODIFY 0xffc01f54 /* Memory DMA Stream 2 Source X Modify Register */
924#define MDMA_S2_Y_COUNT 0xffc01f58 /* Memory DMA Stream 2 Source Y Count Register */
925#define MDMA_S2_Y_MODIFY 0xffc01f5c /* Memory DMA Stream 2 Source Y Modify Register */
926#define MDMA_S2_CURR_DESC_PTR 0xffc01f60 /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
927#define MDMA_S2_CURR_ADDR 0xffc01f64 /* Memory DMA Stream 2 Source Current Address Register */
928#define MDMA_S2_IRQ_STATUS 0xffc01f68 /* Memory DMA Stream 2 Source Interrupt/Status Register */
929#define MDMA_S2_PERIPHERAL_MAP 0xffc01f6c /* Memory DMA Stream 2 Source Peripheral Map Register */
930#define MDMA_S2_CURR_X_COUNT 0xffc01f70 /* Memory DMA Stream 2 Source Current X Count Register */
931#define MDMA_S2_CURR_Y_COUNT 0xffc01f78 /* Memory DMA Stream 2 Source Current Y Count Register */
932
933/* MDMA Stream 3 Registers */
934
935#define MDMA_D3_NEXT_DESC_PTR 0xffc01f80 /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
936#define MDMA_D3_START_ADDR 0xffc01f84 /* Memory DMA Stream 3 Destination Start Address Register */
937#define MDMA_D3_CONFIG 0xffc01f88 /* Memory DMA Stream 3 Destination Configuration Register */
938#define MDMA_D3_X_COUNT 0xffc01f90 /* Memory DMA Stream 3 Destination X Count Register */
939#define MDMA_D3_X_MODIFY 0xffc01f94 /* Memory DMA Stream 3 Destination X Modify Register */
940#define MDMA_D3_Y_COUNT 0xffc01f98 /* Memory DMA Stream 3 Destination Y Count Register */
941#define MDMA_D3_Y_MODIFY 0xffc01f9c /* Memory DMA Stream 3 Destination Y Modify Register */
942#define MDMA_D3_CURR_DESC_PTR 0xffc01fa0 /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
943#define MDMA_D3_CURR_ADDR 0xffc01fa4 /* Memory DMA Stream 3 Destination Current Address Register */
944#define MDMA_D3_IRQ_STATUS 0xffc01fa8 /* Memory DMA Stream 3 Destination Interrupt/Status Register */
945#define MDMA_D3_PERIPHERAL_MAP 0xffc01fac /* Memory DMA Stream 3 Destination Peripheral Map Register */
946#define MDMA_D3_CURR_X_COUNT 0xffc01fb0 /* Memory DMA Stream 3 Destination Current X Count Register */
947#define MDMA_D3_CURR_Y_COUNT 0xffc01fb8 /* Memory DMA Stream 3 Destination Current Y Count Register */
948#define MDMA_S3_NEXT_DESC_PTR 0xffc01fc0 /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
949#define MDMA_S3_START_ADDR 0xffc01fc4 /* Memory DMA Stream 3 Source Start Address Register */
950#define MDMA_S3_CONFIG 0xffc01fc8 /* Memory DMA Stream 3 Source Configuration Register */
951#define MDMA_S3_X_COUNT 0xffc01fd0 /* Memory DMA Stream 3 Source X Count Register */
952#define MDMA_S3_X_MODIFY 0xffc01fd4 /* Memory DMA Stream 3 Source X Modify Register */
953#define MDMA_S3_Y_COUNT 0xffc01fd8 /* Memory DMA Stream 3 Source Y Count Register */
954#define MDMA_S3_Y_MODIFY 0xffc01fdc /* Memory DMA Stream 3 Source Y Modify Register */
955#define MDMA_S3_CURR_DESC_PTR 0xffc01fe0 /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
956#define MDMA_S3_CURR_ADDR 0xffc01fe4 /* Memory DMA Stream 3 Source Current Address Register */
957#define MDMA_S3_IRQ_STATUS 0xffc01fe8 /* Memory DMA Stream 3 Source Interrupt/Status Register */
958#define MDMA_S3_PERIPHERAL_MAP 0xffc01fec /* Memory DMA Stream 3 Source Peripheral Map Register */
959#define MDMA_S3_CURR_X_COUNT 0xffc01ff0 /* Memory DMA Stream 3 Source Current X Count Register */
960#define MDMA_S3_CURR_Y_COUNT 0xffc01ff8 /* Memory DMA Stream 3 Source Current Y Count Register */
961
962/* UART1 Registers */
963
964#define UART1_DLL 0xffc02000 /* Divisor Latch Low Byte */
965#define UART1_DLH 0xffc02004 /* Divisor Latch High Byte */
966#define UART1_GCTL 0xffc02008 /* Global Control Register */
967#define UART1_LCR 0xffc0200c /* Line Control Register */
968#define UART1_MCR 0xffc02010 /* Modem Control Register */
969#define UART1_LSR 0xffc02014 /* Line Status Register */
970#define UART1_MSR 0xffc02018 /* Modem Status Register */
971#define UART1_SCR 0xffc0201c /* Scratch Register */
972#define UART1_IER_SET 0xffc02020 /* Interrupt Enable Register Set */
973#define UART1_IER_CLEAR 0xffc02024 /* Interrupt Enable Register Clear */
974#define UART1_THR 0xffc02028 /* Transmit Hold Register */
975#define UART1_RBR 0xffc0202c /* Receive Buffer Register */
976
977/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
978
979/* SPI1 Registers */
980
981#define SPI1_CTL 0xffc02300 /* SPI1 Control Register */
982#define SPI1_FLG 0xffc02304 /* SPI1 Flag Register */
983#define SPI1_STAT 0xffc02308 /* SPI1 Status Register */
984#define SPI1_TDBR 0xffc0230c /* SPI1 Transmit Data Buffer Register */
985#define SPI1_RDBR 0xffc02310 /* SPI1 Receive Data Buffer Register */
986#define SPI1_BAUD 0xffc02314 /* SPI1 Baud Rate Register */
987#define SPI1_SHADOW 0xffc02318 /* SPI1 Receive Data Buffer Shadow Register */
988
989/* SPORT2 Registers */
990
991#define SPORT2_TCR1 0xffc02500 /* SPORT2 Transmit Configuration 1 Register */
992#define SPORT2_TCR2 0xffc02504 /* SPORT2 Transmit Configuration 2 Register */
993#define SPORT2_TCLKDIV 0xffc02508 /* SPORT2 Transmit Serial Clock Divider Register */
994#define SPORT2_TFSDIV 0xffc0250c /* SPORT2 Transmit Frame Sync Divider Register */
995#define SPORT2_TX 0xffc02510 /* SPORT2 Transmit Data Register */
996#define SPORT2_RX 0xffc02518 /* SPORT2 Receive Data Register */
997#define SPORT2_RCR1 0xffc02520 /* SPORT2 Receive Configuration 1 Register */
998#define SPORT2_RCR2 0xffc02524 /* SPORT2 Receive Configuration 2 Register */
999#define SPORT2_RCLKDIV 0xffc02528 /* SPORT2 Receive Serial Clock Divider Register */
1000#define SPORT2_RFSDIV 0xffc0252c /* SPORT2 Receive Frame Sync Divider Register */
1001#define SPORT2_STAT 0xffc02530 /* SPORT2 Status Register */
1002#define SPORT2_CHNL 0xffc02534 /* SPORT2 Current Channel Register */
1003#define SPORT2_MCMC1 0xffc02538 /* SPORT2 Multi channel Configuration Register 1 */
1004#define SPORT2_MCMC2 0xffc0253c /* SPORT2 Multi channel Configuration Register 2 */
1005#define SPORT2_MTCS0 0xffc02540 /* SPORT2 Multi channel Transmit Select Register 0 */
1006#define SPORT2_MTCS1 0xffc02544 /* SPORT2 Multi channel Transmit Select Register 1 */
1007#define SPORT2_MTCS2 0xffc02548 /* SPORT2 Multi channel Transmit Select Register 2 */
1008#define SPORT2_MTCS3 0xffc0254c /* SPORT2 Multi channel Transmit Select Register 3 */
1009#define SPORT2_MRCS0 0xffc02550 /* SPORT2 Multi channel Receive Select Register 0 */
1010#define SPORT2_MRCS1 0xffc02554 /* SPORT2 Multi channel Receive Select Register 1 */
1011#define SPORT2_MRCS2 0xffc02558 /* SPORT2 Multi channel Receive Select Register 2 */
1012#define SPORT2_MRCS3 0xffc0255c /* SPORT2 Multi channel Receive Select Register 3 */
1013
1014/* SPORT3 Registers */
1015
1016#define SPORT3_TCR1 0xffc02600 /* SPORT3 Transmit Configuration 1 Register */
1017#define SPORT3_TCR2 0xffc02604 /* SPORT3 Transmit Configuration 2 Register */
1018#define SPORT3_TCLKDIV 0xffc02608 /* SPORT3 Transmit Serial Clock Divider Register */
1019#define SPORT3_TFSDIV 0xffc0260c /* SPORT3 Transmit Frame Sync Divider Register */
1020#define SPORT3_TX 0xffc02610 /* SPORT3 Transmit Data Register */
1021#define SPORT3_RX 0xffc02618 /* SPORT3 Receive Data Register */
1022#define SPORT3_RCR1 0xffc02620 /* SPORT3 Receive Configuration 1 Register */
1023#define SPORT3_RCR2 0xffc02624 /* SPORT3 Receive Configuration 2 Register */
1024#define SPORT3_RCLKDIV 0xffc02628 /* SPORT3 Receive Serial Clock Divider Register */
1025#define SPORT3_RFSDIV 0xffc0262c /* SPORT3 Receive Frame Sync Divider Register */
1026#define SPORT3_STAT 0xffc02630 /* SPORT3 Status Register */
1027#define SPORT3_CHNL 0xffc02634 /* SPORT3 Current Channel Register */
1028#define SPORT3_MCMC1 0xffc02638 /* SPORT3 Multi channel Configuration Register 1 */
1029#define SPORT3_MCMC2 0xffc0263c /* SPORT3 Multi channel Configuration Register 2 */
1030#define SPORT3_MTCS0 0xffc02640 /* SPORT3 Multi channel Transmit Select Register 0 */
1031#define SPORT3_MTCS1 0xffc02644 /* SPORT3 Multi channel Transmit Select Register 1 */
1032#define SPORT3_MTCS2 0xffc02648 /* SPORT3 Multi channel Transmit Select Register 2 */
1033#define SPORT3_MTCS3 0xffc0264c /* SPORT3 Multi channel Transmit Select Register 3 */
1034#define SPORT3_MRCS0 0xffc02650 /* SPORT3 Multi channel Receive Select Register 0 */
1035#define SPORT3_MRCS1 0xffc02654 /* SPORT3 Multi channel Receive Select Register 1 */
1036#define SPORT3_MRCS2 0xffc02658 /* SPORT3 Multi channel Receive Select Register 2 */
1037#define SPORT3_MRCS3 0xffc0265c /* SPORT3 Multi channel Receive Select Register 3 */
1038
1039/* EPPI2 Registers */
1040
1041#define EPPI2_STATUS 0xffc02900 /* EPPI2 Status Register */
1042#define EPPI2_HCOUNT 0xffc02904 /* EPPI2 Horizontal Transfer Count Register */
1043#define EPPI2_HDELAY 0xffc02908 /* EPPI2 Horizontal Delay Count Register */
1044#define EPPI2_VCOUNT 0xffc0290c /* EPPI2 Vertical Transfer Count Register */
1045#define EPPI2_VDELAY 0xffc02910 /* EPPI2 Vertical Delay Count Register */
1046#define EPPI2_FRAME 0xffc02914 /* EPPI2 Lines per Frame Register */
1047#define EPPI2_LINE 0xffc02918 /* EPPI2 Samples per Line Register */
1048#define EPPI2_CLKDIV 0xffc0291c /* EPPI2 Clock Divide Register */
1049#define EPPI2_CONTROL 0xffc02920 /* EPPI2 Control Register */
1050#define EPPI2_FS1W_HBL 0xffc02924 /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
1051#define EPPI2_FS1P_AVPL 0xffc02928 /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
1052#define EPPI2_FS2W_LVB 0xffc0292c /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
1053#define EPPI2_FS2P_LAVF 0xffc02930 /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
1054#define EPPI2_CLIP 0xffc02934 /* EPPI2 Clipping Register */
1055
1056/* CAN Controller 0 Config 1 Registers */
1057
1058#define CAN0_MC1 0xffc02a00 /* CAN Controller 0 Mailbox Configuration Register 1 */
1059#define CAN0_MD1 0xffc02a04 /* CAN Controller 0 Mailbox Direction Register 1 */
1060#define CAN0_TRS1 0xffc02a08 /* CAN Controller 0 Transmit Request Set Register 1 */
1061#define CAN0_TRR1 0xffc02a0c /* CAN Controller 0 Transmit Request Reset Register 1 */
1062#define CAN0_TA1 0xffc02a10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
1063#define CAN0_AA1 0xffc02a14 /* CAN Controller 0 Abort Acknowledge Register 1 */
1064#define CAN0_RMP1 0xffc02a18 /* CAN Controller 0 Receive Message Pending Register 1 */
1065#define CAN0_RML1 0xffc02a1c /* CAN Controller 0 Receive Message Lost Register 1 */
1066#define CAN0_MBTIF1 0xffc02a20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
1067#define CAN0_MBRIF1 0xffc02a24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
1068#define CAN0_MBIM1 0xffc02a28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
1069#define CAN0_RFH1 0xffc02a2c /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
1070#define CAN0_OPSS1 0xffc02a30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
1071
1072/* CAN Controller 0 Config 2 Registers */
1073
1074#define CAN0_MC2 0xffc02a40 /* CAN Controller 0 Mailbox Configuration Register 2 */
1075#define CAN0_MD2 0xffc02a44 /* CAN Controller 0 Mailbox Direction Register 2 */
1076#define CAN0_TRS2 0xffc02a48 /* CAN Controller 0 Transmit Request Set Register 2 */
1077#define CAN0_TRR2 0xffc02a4c /* CAN Controller 0 Transmit Request Reset Register 2 */
1078#define CAN0_TA2 0xffc02a50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
1079#define CAN0_AA2 0xffc02a54 /* CAN Controller 0 Abort Acknowledge Register 2 */
1080#define CAN0_RMP2 0xffc02a58 /* CAN Controller 0 Receive Message Pending Register 2 */
1081#define CAN0_RML2 0xffc02a5c /* CAN Controller 0 Receive Message Lost Register 2 */
1082#define CAN0_MBTIF2 0xffc02a60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
1083#define CAN0_MBRIF2 0xffc02a64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
1084#define CAN0_MBIM2 0xffc02a68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
1085#define CAN0_RFH2 0xffc02a6c /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
1086#define CAN0_OPSS2 0xffc02a70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
1087
1088/* CAN Controller 0 Clock/Interrupt/Counter Registers */
1089
1090#define CAN0_CLOCK 0xffc02a80 /* CAN Controller 0 Clock Register */
1091#define CAN0_TIMING 0xffc02a84 /* CAN Controller 0 Timing Register */
1092#define CAN0_DEBUG 0xffc02a88 /* CAN Controller 0 Debug Register */
1093#define CAN0_STATUS 0xffc02a8c /* CAN Controller 0 Global Status Register */
1094#define CAN0_CEC 0xffc02a90 /* CAN Controller 0 Error Counter Register */
1095#define CAN0_GIS 0xffc02a94 /* CAN Controller 0 Global Interrupt Status Register */
1096#define CAN0_GIM 0xffc02a98 /* CAN Controller 0 Global Interrupt Mask Register */
1097#define CAN0_GIF 0xffc02a9c /* CAN Controller 0 Global Interrupt Flag Register */
1098#define CAN0_CONTROL 0xffc02aa0 /* CAN Controller 0 Master Control Register */
1099#define CAN0_INTR 0xffc02aa4 /* CAN Controller 0 Interrupt Pending Register */
1100#define CAN0_MBTD 0xffc02aac /* CAN Controller 0 Mailbox Temporary Disable Register */
1101#define CAN0_EWR 0xffc02ab0 /* CAN Controller 0 Programmable Warning Level Register */
1102#define CAN0_ESR 0xffc02ab4 /* CAN Controller 0 Error Status Register */
1103#define CAN0_UCCNT 0xffc02ac4 /* CAN Controller 0 Universal Counter Register */
1104#define CAN0_UCRC 0xffc02ac8 /* CAN Controller 0 Universal Counter Force Reload Register */
1105#define CAN0_UCCNF 0xffc02acc /* CAN Controller 0 Universal Counter Configuration Register */
1106
1107/* CAN Controller 0 Acceptance Registers */
1108
1109#define CAN0_AM00L 0xffc02b00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
1110#define CAN0_AM00H 0xffc02b04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
1111#define CAN0_AM01L 0xffc02b08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
1112#define CAN0_AM01H 0xffc02b0c /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
1113#define CAN0_AM02L 0xffc02b10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
1114#define CAN0_AM02H 0xffc02b14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
1115#define CAN0_AM03L 0xffc02b18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
1116#define CAN0_AM03H 0xffc02b1c /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
1117#define CAN0_AM04L 0xffc02b20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
1118#define CAN0_AM04H 0xffc02b24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
1119#define CAN0_AM05L 0xffc02b28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
1120#define CAN0_AM05H 0xffc02b2c /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
1121#define CAN0_AM06L 0xffc02b30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
1122#define CAN0_AM06H 0xffc02b34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
1123#define CAN0_AM07L 0xffc02b38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
1124#define CAN0_AM07H 0xffc02b3c /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
1125#define CAN0_AM08L 0xffc02b40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
1126#define CAN0_AM08H 0xffc02b44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
1127#define CAN0_AM09L 0xffc02b48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
1128#define CAN0_AM09H 0xffc02b4c /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
1129#define CAN0_AM10L 0xffc02b50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
1130#define CAN0_AM10H 0xffc02b54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
1131#define CAN0_AM11L 0xffc02b58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
1132#define CAN0_AM11H 0xffc02b5c /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
1133#define CAN0_AM12L 0xffc02b60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
1134#define CAN0_AM12H 0xffc02b64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
1135#define CAN0_AM13L 0xffc02b68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
1136#define CAN0_AM13H 0xffc02b6c /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
1137#define CAN0_AM14L 0xffc02b70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
1138#define CAN0_AM14H 0xffc02b74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
1139#define CAN0_AM15L 0xffc02b78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
1140#define CAN0_AM15H 0xffc02b7c /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
1141
1142/* CAN Controller 0 Acceptance Registers */
1143
1144#define CAN0_AM16L 0xffc02b80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
1145#define CAN0_AM16H 0xffc02b84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
1146#define CAN0_AM17L 0xffc02b88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
1147#define CAN0_AM17H 0xffc02b8c /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
1148#define CAN0_AM18L 0xffc02b90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
1149#define CAN0_AM18H 0xffc02b94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
1150#define CAN0_AM19L 0xffc02b98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
1151#define CAN0_AM19H 0xffc02b9c /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
1152#define CAN0_AM20L 0xffc02ba0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
1153#define CAN0_AM20H 0xffc02ba4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
1154#define CAN0_AM21L 0xffc02ba8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
1155#define CAN0_AM21H 0xffc02bac /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
1156#define CAN0_AM22L 0xffc02bb0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
1157#define CAN0_AM22H 0xffc02bb4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
1158#define CAN0_AM23L 0xffc02bb8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
1159#define CAN0_AM23H 0xffc02bbc /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
1160#define CAN0_AM24L 0xffc02bc0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
1161#define CAN0_AM24H 0xffc02bc4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
1162#define CAN0_AM25L 0xffc02bc8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
1163#define CAN0_AM25H 0xffc02bcc /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
1164#define CAN0_AM26L 0xffc02bd0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
1165#define CAN0_AM26H 0xffc02bd4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
1166#define CAN0_AM27L 0xffc02bd8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
1167#define CAN0_AM27H 0xffc02bdc /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
1168#define CAN0_AM28L 0xffc02be0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
1169#define CAN0_AM28H 0xffc02be4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
1170#define CAN0_AM29L 0xffc02be8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
1171#define CAN0_AM29H 0xffc02bec /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
1172#define CAN0_AM30L 0xffc02bf0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
1173#define CAN0_AM30H 0xffc02bf4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
1174#define CAN0_AM31L 0xffc02bf8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
1175#define CAN0_AM31H 0xffc02bfc /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
1176
1177/* CAN Controller 0 Mailbox Data Registers */
1178
1179#define CAN0_MB00_DATA0 0xffc02c00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
1180#define CAN0_MB00_DATA1 0xffc02c04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
1181#define CAN0_MB00_DATA2 0xffc02c08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
1182#define CAN0_MB00_DATA3 0xffc02c0c /* CAN Controller 0 Mailbox 0 Data 3 Register */
1183#define CAN0_MB00_LENGTH 0xffc02c10 /* CAN Controller 0 Mailbox 0 Length Register */
1184#define CAN0_MB00_TIMESTAMP 0xffc02c14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
1185#define CAN0_MB00_ID0 0xffc02c18 /* CAN Controller 0 Mailbox 0 ID0 Register */
1186#define CAN0_MB00_ID1 0xffc02c1c /* CAN Controller 0 Mailbox 0 ID1 Register */
1187#define CAN0_MB01_DATA0 0xffc02c20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
1188#define CAN0_MB01_DATA1 0xffc02c24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
1189#define CAN0_MB01_DATA2 0xffc02c28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
1190#define CAN0_MB01_DATA3 0xffc02c2c /* CAN Controller 0 Mailbox 1 Data 3 Register */
1191#define CAN0_MB01_LENGTH 0xffc02c30 /* CAN Controller 0 Mailbox 1 Length Register */
1192#define CAN0_MB01_TIMESTAMP 0xffc02c34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
1193#define CAN0_MB01_ID0 0xffc02c38 /* CAN Controller 0 Mailbox 1 ID0 Register */
1194#define CAN0_MB01_ID1 0xffc02c3c /* CAN Controller 0 Mailbox 1 ID1 Register */
1195#define CAN0_MB02_DATA0 0xffc02c40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
1196#define CAN0_MB02_DATA1 0xffc02c44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
1197#define CAN0_MB02_DATA2 0xffc02c48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
1198#define CAN0_MB02_DATA3 0xffc02c4c /* CAN Controller 0 Mailbox 2 Data 3 Register */
1199#define CAN0_MB02_LENGTH 0xffc02c50 /* CAN Controller 0 Mailbox 2 Length Register */
1200#define CAN0_MB02_TIMESTAMP 0xffc02c54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
1201#define CAN0_MB02_ID0 0xffc02c58 /* CAN Controller 0 Mailbox 2 ID0 Register */
1202#define CAN0_MB02_ID1 0xffc02c5c /* CAN Controller 0 Mailbox 2 ID1 Register */
1203#define CAN0_MB03_DATA0 0xffc02c60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
1204#define CAN0_MB03_DATA1 0xffc02c64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
1205#define CAN0_MB03_DATA2 0xffc02c68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
1206#define CAN0_MB03_DATA3 0xffc02c6c /* CAN Controller 0 Mailbox 3 Data 3 Register */
1207#define CAN0_MB03_LENGTH 0xffc02c70 /* CAN Controller 0 Mailbox 3 Length Register */
1208#define CAN0_MB03_TIMESTAMP 0xffc02c74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
1209#define CAN0_MB03_ID0 0xffc02c78 /* CAN Controller 0 Mailbox 3 ID0 Register */
1210#define CAN0_MB03_ID1 0xffc02c7c /* CAN Controller 0 Mailbox 3 ID1 Register */
1211#define CAN0_MB04_DATA0 0xffc02c80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
1212#define CAN0_MB04_DATA1 0xffc02c84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
1213#define CAN0_MB04_DATA2 0xffc02c88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
1214#define CAN0_MB04_DATA3 0xffc02c8c /* CAN Controller 0 Mailbox 4 Data 3 Register */
1215#define CAN0_MB04_LENGTH 0xffc02c90 /* CAN Controller 0 Mailbox 4 Length Register */
1216#define CAN0_MB04_TIMESTAMP 0xffc02c94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
1217#define CAN0_MB04_ID0 0xffc02c98 /* CAN Controller 0 Mailbox 4 ID0 Register */
1218#define CAN0_MB04_ID1 0xffc02c9c /* CAN Controller 0 Mailbox 4 ID1 Register */
1219#define CAN0_MB05_DATA0 0xffc02ca0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
1220#define CAN0_MB05_DATA1 0xffc02ca4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
1221#define CAN0_MB05_DATA2 0xffc02ca8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
1222#define CAN0_MB05_DATA3 0xffc02cac /* CAN Controller 0 Mailbox 5 Data 3 Register */
1223#define CAN0_MB05_LENGTH 0xffc02cb0 /* CAN Controller 0 Mailbox 5 Length Register */
1224#define CAN0_MB05_TIMESTAMP 0xffc02cb4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
1225#define CAN0_MB05_ID0 0xffc02cb8 /* CAN Controller 0 Mailbox 5 ID0 Register */
1226#define CAN0_MB05_ID1 0xffc02cbc /* CAN Controller 0 Mailbox 5 ID1 Register */
1227#define CAN0_MB06_DATA0 0xffc02cc0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
1228#define CAN0_MB06_DATA1 0xffc02cc4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
1229#define CAN0_MB06_DATA2 0xffc02cc8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
1230#define CAN0_MB06_DATA3 0xffc02ccc /* CAN Controller 0 Mailbox 6 Data 3 Register */
1231#define CAN0_MB06_LENGTH 0xffc02cd0 /* CAN Controller 0 Mailbox 6 Length Register */
1232#define CAN0_MB06_TIMESTAMP 0xffc02cd4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
1233#define CAN0_MB06_ID0 0xffc02cd8 /* CAN Controller 0 Mailbox 6 ID0 Register */
1234#define CAN0_MB06_ID1 0xffc02cdc /* CAN Controller 0 Mailbox 6 ID1 Register */
1235#define CAN0_MB07_DATA0 0xffc02ce0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
1236#define CAN0_MB07_DATA1 0xffc02ce4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
1237#define CAN0_MB07_DATA2 0xffc02ce8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
1238#define CAN0_MB07_DATA3 0xffc02cec /* CAN Controller 0 Mailbox 7 Data 3 Register */
1239#define CAN0_MB07_LENGTH 0xffc02cf0 /* CAN Controller 0 Mailbox 7 Length Register */
1240#define CAN0_MB07_TIMESTAMP 0xffc02cf4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
1241#define CAN0_MB07_ID0 0xffc02cf8 /* CAN Controller 0 Mailbox 7 ID0 Register */
1242#define CAN0_MB07_ID1 0xffc02cfc /* CAN Controller 0 Mailbox 7 ID1 Register */
1243#define CAN0_MB08_DATA0 0xffc02d00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
1244#define CAN0_MB08_DATA1 0xffc02d04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
1245#define CAN0_MB08_DATA2 0xffc02d08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
1246#define CAN0_MB08_DATA3 0xffc02d0c /* CAN Controller 0 Mailbox 8 Data 3 Register */
1247#define CAN0_MB08_LENGTH 0xffc02d10 /* CAN Controller 0 Mailbox 8 Length Register */
1248#define CAN0_MB08_TIMESTAMP 0xffc02d14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
1249#define CAN0_MB08_ID0 0xffc02d18 /* CAN Controller 0 Mailbox 8 ID0 Register */
1250#define CAN0_MB08_ID1 0xffc02d1c /* CAN Controller 0 Mailbox 8 ID1 Register */
1251#define CAN0_MB09_DATA0 0xffc02d20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
1252#define CAN0_MB09_DATA1 0xffc02d24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
1253#define CAN0_MB09_DATA2 0xffc02d28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
1254#define CAN0_MB09_DATA3 0xffc02d2c /* CAN Controller 0 Mailbox 9 Data 3 Register */
1255#define CAN0_MB09_LENGTH 0xffc02d30 /* CAN Controller 0 Mailbox 9 Length Register */
1256#define CAN0_MB09_TIMESTAMP 0xffc02d34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
1257#define CAN0_MB09_ID0 0xffc02d38 /* CAN Controller 0 Mailbox 9 ID0 Register */
1258#define CAN0_MB09_ID1 0xffc02d3c /* CAN Controller 0 Mailbox 9 ID1 Register */
1259#define CAN0_MB10_DATA0 0xffc02d40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
1260#define CAN0_MB10_DATA1 0xffc02d44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
1261#define CAN0_MB10_DATA2 0xffc02d48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
1262#define CAN0_MB10_DATA3 0xffc02d4c /* CAN Controller 0 Mailbox 10 Data 3 Register */
1263#define CAN0_MB10_LENGTH 0xffc02d50 /* CAN Controller 0 Mailbox 10 Length Register */
1264#define CAN0_MB10_TIMESTAMP 0xffc02d54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
1265#define CAN0_MB10_ID0 0xffc02d58 /* CAN Controller 0 Mailbox 10 ID0 Register */
1266#define CAN0_MB10_ID1 0xffc02d5c /* CAN Controller 0 Mailbox 10 ID1 Register */
1267#define CAN0_MB11_DATA0 0xffc02d60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
1268#define CAN0_MB11_DATA1 0xffc02d64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
1269#define CAN0_MB11_DATA2 0xffc02d68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
1270#define CAN0_MB11_DATA3 0xffc02d6c /* CAN Controller 0 Mailbox 11 Data 3 Register */
1271#define CAN0_MB11_LENGTH 0xffc02d70 /* CAN Controller 0 Mailbox 11 Length Register */
1272#define CAN0_MB11_TIMESTAMP 0xffc02d74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
1273#define CAN0_MB11_ID0 0xffc02d78 /* CAN Controller 0 Mailbox 11 ID0 Register */
1274#define CAN0_MB11_ID1 0xffc02d7c /* CAN Controller 0 Mailbox 11 ID1 Register */
1275#define CAN0_MB12_DATA0 0xffc02d80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
1276#define CAN0_MB12_DATA1 0xffc02d84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
1277#define CAN0_MB12_DATA2 0xffc02d88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
1278#define CAN0_MB12_DATA3 0xffc02d8c /* CAN Controller 0 Mailbox 12 Data 3 Register */
1279#define CAN0_MB12_LENGTH 0xffc02d90 /* CAN Controller 0 Mailbox 12 Length Register */
1280#define CAN0_MB12_TIMESTAMP 0xffc02d94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
1281#define CAN0_MB12_ID0 0xffc02d98 /* CAN Controller 0 Mailbox 12 ID0 Register */
1282#define CAN0_MB12_ID1 0xffc02d9c /* CAN Controller 0 Mailbox 12 ID1 Register */
1283#define CAN0_MB13_DATA0 0xffc02da0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
1284#define CAN0_MB13_DATA1 0xffc02da4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
1285#define CAN0_MB13_DATA2 0xffc02da8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
1286#define CAN0_MB13_DATA3 0xffc02dac /* CAN Controller 0 Mailbox 13 Data 3 Register */
1287#define CAN0_MB13_LENGTH 0xffc02db0 /* CAN Controller 0 Mailbox 13 Length Register */
1288#define CAN0_MB13_TIMESTAMP 0xffc02db4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
1289#define CAN0_MB13_ID0 0xffc02db8 /* CAN Controller 0 Mailbox 13 ID0 Register */
1290#define CAN0_MB13_ID1 0xffc02dbc /* CAN Controller 0 Mailbox 13 ID1 Register */
1291#define CAN0_MB14_DATA0 0xffc02dc0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
1292#define CAN0_MB14_DATA1 0xffc02dc4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
1293#define CAN0_MB14_DATA2 0xffc02dc8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
1294#define CAN0_MB14_DATA3 0xffc02dcc /* CAN Controller 0 Mailbox 14 Data 3 Register */
1295#define CAN0_MB14_LENGTH 0xffc02dd0 /* CAN Controller 0 Mailbox 14 Length Register */
1296#define CAN0_MB14_TIMESTAMP 0xffc02dd4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
1297#define CAN0_MB14_ID0 0xffc02dd8 /* CAN Controller 0 Mailbox 14 ID0 Register */
1298#define CAN0_MB14_ID1 0xffc02ddc /* CAN Controller 0 Mailbox 14 ID1 Register */
1299#define CAN0_MB15_DATA0 0xffc02de0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
1300#define CAN0_MB15_DATA1 0xffc02de4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
1301#define CAN0_MB15_DATA2 0xffc02de8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
1302#define CAN0_MB15_DATA3 0xffc02dec /* CAN Controller 0 Mailbox 15 Data 3 Register */
1303#define CAN0_MB15_LENGTH 0xffc02df0 /* CAN Controller 0 Mailbox 15 Length Register */
1304#define CAN0_MB15_TIMESTAMP 0xffc02df4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
1305#define CAN0_MB15_ID0 0xffc02df8 /* CAN Controller 0 Mailbox 15 ID0 Register */
1306#define CAN0_MB15_ID1 0xffc02dfc /* CAN Controller 0 Mailbox 15 ID1 Register */
1307
1308/* CAN Controller 0 Mailbox Data Registers */
1309
1310#define CAN0_MB16_DATA0 0xffc02e00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
1311#define CAN0_MB16_DATA1 0xffc02e04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
1312#define CAN0_MB16_DATA2 0xffc02e08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
1313#define CAN0_MB16_DATA3 0xffc02e0c /* CAN Controller 0 Mailbox 16 Data 3 Register */
1314#define CAN0_MB16_LENGTH 0xffc02e10 /* CAN Controller 0 Mailbox 16 Length Register */
1315#define CAN0_MB16_TIMESTAMP 0xffc02e14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
1316#define CAN0_MB16_ID0 0xffc02e18 /* CAN Controller 0 Mailbox 16 ID0 Register */
1317#define CAN0_MB16_ID1 0xffc02e1c /* CAN Controller 0 Mailbox 16 ID1 Register */
1318#define CAN0_MB17_DATA0 0xffc02e20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
1319#define CAN0_MB17_DATA1 0xffc02e24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
1320#define CAN0_MB17_DATA2 0xffc02e28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
1321#define CAN0_MB17_DATA3 0xffc02e2c /* CAN Controller 0 Mailbox 17 Data 3 Register */
1322#define CAN0_MB17_LENGTH 0xffc02e30 /* CAN Controller 0 Mailbox 17 Length Register */
1323#define CAN0_MB17_TIMESTAMP 0xffc02e34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
1324#define CAN0_MB17_ID0 0xffc02e38 /* CAN Controller 0 Mailbox 17 ID0 Register */
1325#define CAN0_MB17_ID1 0xffc02e3c /* CAN Controller 0 Mailbox 17 ID1 Register */
1326#define CAN0_MB18_DATA0 0xffc02e40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
1327#define CAN0_MB18_DATA1 0xffc02e44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
1328#define CAN0_MB18_DATA2 0xffc02e48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
1329#define CAN0_MB18_DATA3 0xffc02e4c /* CAN Controller 0 Mailbox 18 Data 3 Register */
1330#define CAN0_MB18_LENGTH 0xffc02e50 /* CAN Controller 0 Mailbox 18 Length Register */
1331#define CAN0_MB18_TIMESTAMP 0xffc02e54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
1332#define CAN0_MB18_ID0 0xffc02e58 /* CAN Controller 0 Mailbox 18 ID0 Register */
1333#define CAN0_MB18_ID1 0xffc02e5c /* CAN Controller 0 Mailbox 18 ID1 Register */
1334#define CAN0_MB19_DATA0 0xffc02e60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
1335#define CAN0_MB19_DATA1 0xffc02e64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
1336#define CAN0_MB19_DATA2 0xffc02e68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
1337#define CAN0_MB19_DATA3 0xffc02e6c /* CAN Controller 0 Mailbox 19 Data 3 Register */
1338#define CAN0_MB19_LENGTH 0xffc02e70 /* CAN Controller 0 Mailbox 19 Length Register */
1339#define CAN0_MB19_TIMESTAMP 0xffc02e74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
1340#define CAN0_MB19_ID0 0xffc02e78 /* CAN Controller 0 Mailbox 19 ID0 Register */
1341#define CAN0_MB19_ID1 0xffc02e7c /* CAN Controller 0 Mailbox 19 ID1 Register */
1342#define CAN0_MB20_DATA0 0xffc02e80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
1343#define CAN0_MB20_DATA1 0xffc02e84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
1344#define CAN0_MB20_DATA2 0xffc02e88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
1345#define CAN0_MB20_DATA3 0xffc02e8c /* CAN Controller 0 Mailbox 20 Data 3 Register */
1346#define CAN0_MB20_LENGTH 0xffc02e90 /* CAN Controller 0 Mailbox 20 Length Register */
1347#define CAN0_MB20_TIMESTAMP 0xffc02e94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
1348#define CAN0_MB20_ID0 0xffc02e98 /* CAN Controller 0 Mailbox 20 ID0 Register */
1349#define CAN0_MB20_ID1 0xffc02e9c /* CAN Controller 0 Mailbox 20 ID1 Register */
1350#define CAN0_MB21_DATA0 0xffc02ea0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
1351#define CAN0_MB21_DATA1 0xffc02ea4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
1352#define CAN0_MB21_DATA2 0xffc02ea8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
1353#define CAN0_MB21_DATA3 0xffc02eac /* CAN Controller 0 Mailbox 21 Data 3 Register */
1354#define CAN0_MB21_LENGTH 0xffc02eb0 /* CAN Controller 0 Mailbox 21 Length Register */
1355#define CAN0_MB21_TIMESTAMP 0xffc02eb4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
1356#define CAN0_MB21_ID0 0xffc02eb8 /* CAN Controller 0 Mailbox 21 ID0 Register */
1357#define CAN0_MB21_ID1 0xffc02ebc /* CAN Controller 0 Mailbox 21 ID1 Register */
1358#define CAN0_MB22_DATA0 0xffc02ec0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
1359#define CAN0_MB22_DATA1 0xffc02ec4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
1360#define CAN0_MB22_DATA2 0xffc02ec8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
1361#define CAN0_MB22_DATA3 0xffc02ecc /* CAN Controller 0 Mailbox 22 Data 3 Register */
1362#define CAN0_MB22_LENGTH 0xffc02ed0 /* CAN Controller 0 Mailbox 22 Length Register */
1363#define CAN0_MB22_TIMESTAMP 0xffc02ed4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
1364#define CAN0_MB22_ID0 0xffc02ed8 /* CAN Controller 0 Mailbox 22 ID0 Register */
1365#define CAN0_MB22_ID1 0xffc02edc /* CAN Controller 0 Mailbox 22 ID1 Register */
1366#define CAN0_MB23_DATA0 0xffc02ee0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
1367#define CAN0_MB23_DATA1 0xffc02ee4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
1368#define CAN0_MB23_DATA2 0xffc02ee8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
1369#define CAN0_MB23_DATA3 0xffc02eec /* CAN Controller 0 Mailbox 23 Data 3 Register */
1370#define CAN0_MB23_LENGTH 0xffc02ef0 /* CAN Controller 0 Mailbox 23 Length Register */
1371#define CAN0_MB23_TIMESTAMP 0xffc02ef4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
1372#define CAN0_MB23_ID0 0xffc02ef8 /* CAN Controller 0 Mailbox 23 ID0 Register */
1373#define CAN0_MB23_ID1 0xffc02efc /* CAN Controller 0 Mailbox 23 ID1 Register */
1374#define CAN0_MB24_DATA0 0xffc02f00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
1375#define CAN0_MB24_DATA1 0xffc02f04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
1376#define CAN0_MB24_DATA2 0xffc02f08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
1377#define CAN0_MB24_DATA3 0xffc02f0c /* CAN Controller 0 Mailbox 24 Data 3 Register */
1378#define CAN0_MB24_LENGTH 0xffc02f10 /* CAN Controller 0 Mailbox 24 Length Register */
1379#define CAN0_MB24_TIMESTAMP 0xffc02f14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
1380#define CAN0_MB24_ID0 0xffc02f18 /* CAN Controller 0 Mailbox 24 ID0 Register */
1381#define CAN0_MB24_ID1 0xffc02f1c /* CAN Controller 0 Mailbox 24 ID1 Register */
1382#define CAN0_MB25_DATA0 0xffc02f20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
1383#define CAN0_MB25_DATA1 0xffc02f24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
1384#define CAN0_MB25_DATA2 0xffc02f28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
1385#define CAN0_MB25_DATA3 0xffc02f2c /* CAN Controller 0 Mailbox 25 Data 3 Register */
1386#define CAN0_MB25_LENGTH 0xffc02f30 /* CAN Controller 0 Mailbox 25 Length Register */
1387#define CAN0_MB25_TIMESTAMP 0xffc02f34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
1388#define CAN0_MB25_ID0 0xffc02f38 /* CAN Controller 0 Mailbox 25 ID0 Register */
1389#define CAN0_MB25_ID1 0xffc02f3c /* CAN Controller 0 Mailbox 25 ID1 Register */
1390#define CAN0_MB26_DATA0 0xffc02f40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
1391#define CAN0_MB26_DATA1 0xffc02f44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
1392#define CAN0_MB26_DATA2 0xffc02f48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
1393#define CAN0_MB26_DATA3 0xffc02f4c /* CAN Controller 0 Mailbox 26 Data 3 Register */
1394#define CAN0_MB26_LENGTH 0xffc02f50 /* CAN Controller 0 Mailbox 26 Length Register */
1395#define CAN0_MB26_TIMESTAMP 0xffc02f54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
1396#define CAN0_MB26_ID0 0xffc02f58 /* CAN Controller 0 Mailbox 26 ID0 Register */
1397#define CAN0_MB26_ID1 0xffc02f5c /* CAN Controller 0 Mailbox 26 ID1 Register */
1398#define CAN0_MB27_DATA0 0xffc02f60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
1399#define CAN0_MB27_DATA1 0xffc02f64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
1400#define CAN0_MB27_DATA2 0xffc02f68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
1401#define CAN0_MB27_DATA3 0xffc02f6c /* CAN Controller 0 Mailbox 27 Data 3 Register */
1402#define CAN0_MB27_LENGTH 0xffc02f70 /* CAN Controller 0 Mailbox 27 Length Register */
1403#define CAN0_MB27_TIMESTAMP 0xffc02f74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
1404#define CAN0_MB27_ID0 0xffc02f78 /* CAN Controller 0 Mailbox 27 ID0 Register */
1405#define CAN0_MB27_ID1 0xffc02f7c /* CAN Controller 0 Mailbox 27 ID1 Register */
1406#define CAN0_MB28_DATA0 0xffc02f80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
1407#define CAN0_MB28_DATA1 0xffc02f84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
1408#define CAN0_MB28_DATA2 0xffc02f88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
1409#define CAN0_MB28_DATA3 0xffc02f8c /* CAN Controller 0 Mailbox 28 Data 3 Register */
1410#define CAN0_MB28_LENGTH 0xffc02f90 /* CAN Controller 0 Mailbox 28 Length Register */
1411#define CAN0_MB28_TIMESTAMP 0xffc02f94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
1412#define CAN0_MB28_ID0 0xffc02f98 /* CAN Controller 0 Mailbox 28 ID0 Register */
1413#define CAN0_MB28_ID1 0xffc02f9c /* CAN Controller 0 Mailbox 28 ID1 Register */
1414#define CAN0_MB29_DATA0 0xffc02fa0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
1415#define CAN0_MB29_DATA1 0xffc02fa4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
1416#define CAN0_MB29_DATA2 0xffc02fa8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
1417#define CAN0_MB29_DATA3 0xffc02fac /* CAN Controller 0 Mailbox 29 Data 3 Register */
1418#define CAN0_MB29_LENGTH 0xffc02fb0 /* CAN Controller 0 Mailbox 29 Length Register */
1419#define CAN0_MB29_TIMESTAMP 0xffc02fb4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
1420#define CAN0_MB29_ID0 0xffc02fb8 /* CAN Controller 0 Mailbox 29 ID0 Register */
1421#define CAN0_MB29_ID1 0xffc02fbc /* CAN Controller 0 Mailbox 29 ID1 Register */
1422#define CAN0_MB30_DATA0 0xffc02fc0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
1423#define CAN0_MB30_DATA1 0xffc02fc4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
1424#define CAN0_MB30_DATA2 0xffc02fc8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
1425#define CAN0_MB30_DATA3 0xffc02fcc /* CAN Controller 0 Mailbox 30 Data 3 Register */
1426#define CAN0_MB30_LENGTH 0xffc02fd0 /* CAN Controller 0 Mailbox 30 Length Register */
1427#define CAN0_MB30_TIMESTAMP 0xffc02fd4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
1428#define CAN0_MB30_ID0 0xffc02fd8 /* CAN Controller 0 Mailbox 30 ID0 Register */
1429#define CAN0_MB30_ID1 0xffc02fdc /* CAN Controller 0 Mailbox 30 ID1 Register */
1430#define CAN0_MB31_DATA0 0xffc02fe0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
1431#define CAN0_MB31_DATA1 0xffc02fe4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
1432#define CAN0_MB31_DATA2 0xffc02fe8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
1433#define CAN0_MB31_DATA3 0xffc02fec /* CAN Controller 0 Mailbox 31 Data 3 Register */
1434#define CAN0_MB31_LENGTH 0xffc02ff0 /* CAN Controller 0 Mailbox 31 Length Register */
1435#define CAN0_MB31_TIMESTAMP 0xffc02ff4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
1436#define CAN0_MB31_ID0 0xffc02ff8 /* CAN Controller 0 Mailbox 31 ID0 Register */
1437#define CAN0_MB31_ID1 0xffc02ffc /* CAN Controller 0 Mailbox 31 ID1 Register */
1438
1439/* UART3 Registers */
1440
1441#define UART3_DLL 0xffc03100 /* Divisor Latch Low Byte */
1442#define UART3_DLH 0xffc03104 /* Divisor Latch High Byte */
1443#define UART3_GCTL 0xffc03108 /* Global Control Register */
1444#define UART3_LCR 0xffc0310c /* Line Control Register */
1445#define UART3_MCR 0xffc03110 /* Modem Control Register */
1446#define UART3_LSR 0xffc03114 /* Line Status Register */
1447#define UART3_MSR 0xffc03118 /* Modem Status Register */
1448#define UART3_SCR 0xffc0311c /* Scratch Register */
1449#define UART3_IER_SET 0xffc03120 /* Interrupt Enable Register Set */
1450#define UART3_IER_CLEAR 0xffc03124 /* Interrupt Enable Register Clear */
1451#define UART3_THR 0xffc03128 /* Transmit Hold Register */
1452#define UART3_RBR 0xffc0312c /* Receive Buffer Register */
1453
1454/* NFC Registers */
1455
1456#define NFC_CTL 0xffc03b00 /* NAND Control Register */
1457#define NFC_STAT 0xffc03b04 /* NAND Status Register */
1458#define NFC_IRQSTAT 0xffc03b08 /* NAND Interrupt Status Register */
1459#define NFC_IRQMASK 0xffc03b0c /* NAND Interrupt Mask Register */
1460#define NFC_ECC0 0xffc03b10 /* NAND ECC Register 0 */
1461#define NFC_ECC1 0xffc03b14 /* NAND ECC Register 1 */
1462#define NFC_ECC2 0xffc03b18 /* NAND ECC Register 2 */
1463#define NFC_ECC3 0xffc03b1c /* NAND ECC Register 3 */
1464#define NFC_COUNT 0xffc03b20 /* NAND ECC Count Register */
1465#define NFC_RST 0xffc03b24 /* NAND ECC Reset Register */
1466#define NFC_PGCTL 0xffc03b28 /* NAND Page Control Register */
1467#define NFC_READ 0xffc03b2c /* NAND Read Data Register */
1468#define NFC_ADDR 0xffc03b40 /* NAND Address Register */
1469#define NFC_CMD 0xffc03b44 /* NAND Command Register */
1470#define NFC_DATA_WR 0xffc03b48 /* NAND Data Write Register */
1471#define NFC_DATA_RD 0xffc03b4c /* NAND Data Read Register */
1472
1473/* Counter Registers */
1474
1475#define CNT_CONFIG 0xffc04200 /* Configuration Register */
1476#define CNT_IMASK 0xffc04204 /* Interrupt Mask Register */
1477#define CNT_STATUS 0xffc04208 /* Status Register */
1478#define CNT_COMMAND 0xffc0420c /* Command Register */
1479#define CNT_DEBOUNCE 0xffc04210 /* Debounce Register */
1480#define CNT_COUNTER 0xffc04214 /* Counter Register */
1481#define CNT_MAX 0xffc04218 /* Maximal Count Register */
1482#define CNT_MIN 0xffc0421c /* Minimal Count Register */
1483
1484/* OTP/FUSE Registers */
1485
1486#define OTP_CONTROL 0xffc04300 /* OTP/Fuse Control Register */
1487#define OTP_BEN 0xffc04304 /* OTP/Fuse Byte Enable */
1488#define OTP_STATUS 0xffc04308 /* OTP/Fuse Status */
1489#define OTP_TIMING 0xffc0430c /* OTP/Fuse Access Timing */
1490
1491/* Security Registers */
1492
1493#define SECURE_SYSSWT 0xffc04320 /* Secure System Switches */
1494#define SECURE_CONTROL 0xffc04324 /* Secure Control */
1495#define SECURE_STATUS 0xffc04328 /* Secure Status */
1496
1497/* DMA Peripheral Mux Register */
1498
1499#define DMAC1_PERIMUX 0xffc04340 /* DMA Controller 1 Peripheral Multiplexer Register */
1500
1501/* OTP Read/Write Data Buffer Registers */
1502
1503#define OTP_DATA0 0xffc04380 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1504#define OTP_DATA1 0xffc04384 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1505#define OTP_DATA2 0xffc04388 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1506#define OTP_DATA3 0xffc0438c /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
1507
1508/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
1509
1510/* ********************************************************** */
1511/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
1512/* and MULTI BIT READ MACROS */
1513/* ********************************************************** */
1514
1515/* Bit masks for SIC_IAR0 */
1516
1517#define IRQ_PLL_WAKEUP 0x1 /* PLL Wakeup */
1518#define nIRQ_PLL_WAKEUP 0x0
1519
1520/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
1521
1522#define IRQ_DMA0_ERR 0x2 /* DMA Controller 0 Error */
1523#define nIRQ_DMA0_ERR 0x0
1524#define IRQ_EPPI0_ERR 0x4 /* EPPI0 Error */
1525#define nIRQ_EPPI0_ERR 0x0
1526#define IRQ_SPORT0_ERR 0x8 /* SPORT0 Error */
1527#define nIRQ_SPORT0_ERR 0x0
1528#define IRQ_SPORT1_ERR 0x10 /* SPORT1 Error */
1529#define nIRQ_SPORT1_ERR 0x0
1530#define IRQ_SPI0_ERR 0x20 /* SPI0 Error */
1531#define nIRQ_SPI0_ERR 0x0
1532#define IRQ_UART0_ERR 0x40 /* UART0 Error */
1533#define nIRQ_UART0_ERR 0x0
1534#define IRQ_RTC 0x80 /* Real-Time Clock */
1535#define nIRQ_RTC 0x0
1536#define IRQ_DMA12 0x100 /* DMA Channel 12 */
1537#define nIRQ_DMA12 0x0
1538#define IRQ_DMA0 0x200 /* DMA Channel 0 */
1539#define nIRQ_DMA0 0x0
1540#define IRQ_DMA1 0x400 /* DMA Channel 1 */
1541#define nIRQ_DMA1 0x0
1542#define IRQ_DMA2 0x800 /* DMA Channel 2 */
1543#define nIRQ_DMA2 0x0
1544#define IRQ_DMA3 0x1000 /* DMA Channel 3 */
1545#define nIRQ_DMA3 0x0
1546#define IRQ_DMA4 0x2000 /* DMA Channel 4 */
1547#define nIRQ_DMA4 0x0
1548#define IRQ_DMA6 0x4000 /* DMA Channel 6 */
1549#define nIRQ_DMA6 0x0
1550#define IRQ_DMA7 0x8000 /* DMA Channel 7 */
1551#define nIRQ_DMA7 0x0
1552#define IRQ_PINT0 0x80000 /* Pin Interrupt 0 */
1553#define nIRQ_PINT0 0x0
1554#define IRQ_PINT1 0x100000 /* Pin Interrupt 1 */
1555#define nIRQ_PINT1 0x0
1556#define IRQ_MDMA0 0x200000 /* Memory DMA Stream 0 */
1557#define nIRQ_MDMA0 0x0
1558#define IRQ_MDMA1 0x400000 /* Memory DMA Stream 1 */
1559#define nIRQ_MDMA1 0x0
1560#define IRQ_WDOG 0x800000 /* Watchdog Timer */
1561#define nIRQ_WDOG 0x0
1562#define IRQ_DMA1_ERR 0x1000000 /* DMA Controller 1 Error */
1563#define nIRQ_DMA1_ERR 0x0
1564#define IRQ_SPORT2_ERR 0x2000000 /* SPORT2 Error */
1565#define nIRQ_SPORT2_ERR 0x0
1566#define IRQ_SPORT3_ERR 0x4000000 /* SPORT3 Error */
1567#define nIRQ_SPORT3_ERR 0x0
1568#define IRQ_MXVR_SD 0x8000000 /* MXVR Synchronous Data */
1569#define nIRQ_MXVR_SD 0x0
1570#define IRQ_SPI1_ERR 0x10000000 /* SPI1 Error */
1571#define nIRQ_SPI1_ERR 0x0
1572#define IRQ_SPI2_ERR 0x20000000 /* SPI2 Error */
1573#define nIRQ_SPI2_ERR 0x0
1574#define IRQ_UART1_ERR 0x40000000 /* UART1 Error */
1575#define nIRQ_UART1_ERR 0x0
1576#define IRQ_UART2_ERR 0x80000000 /* UART2 Error */
1577#define nIRQ_UART2_ERR 0x0
1578
1579/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
1580
1581#define IRQ_CAN0_ERR 0x1 /* CAN0 Error */
1582#define nIRQ_CAN0_ERR 0x0
1583#define IRQ_DMA18 0x2 /* DMA Channel 18 */
1584#define nIRQ_DMA18 0x0
1585#define IRQ_DMA19 0x4 /* DMA Channel 19 */
1586#define nIRQ_DMA19 0x0
1587#define IRQ_DMA20 0x8 /* DMA Channel 20 */
1588#define nIRQ_DMA20 0x0
1589#define IRQ_DMA21 0x10 /* DMA Channel 21 */
1590#define nIRQ_DMA21 0x0
1591#define IRQ_DMA13 0x20 /* DMA Channel 13 */
1592#define nIRQ_DMA13 0x0
1593#define IRQ_DMA14 0x40 /* DMA Channel 14 */
1594#define nIRQ_DMA14 0x0
1595#define IRQ_DMA5 0x80 /* DMA Channel 5 */
1596#define nIRQ_DMA5 0x0
1597#define IRQ_DMA23 0x100 /* DMA Channel 23 */
1598#define nIRQ_DMA23 0x0
1599#define IRQ_DMA8 0x200 /* DMA Channel 8 */
1600#define nIRQ_DMA8 0x0
1601#define IRQ_DMA9 0x400 /* DMA Channel 9 */
1602#define nIRQ_DMA9 0x0
1603#define IRQ_DMA10 0x800 /* DMA Channel 10 */
1604#define nIRQ_DMA10 0x0
1605#define IRQ_DMA11 0x1000 /* DMA Channel 11 */
1606#define nIRQ_DMA11 0x0
1607#define IRQ_TWI0 0x2000 /* TWI0 */
1608#define nIRQ_TWI0 0x0
1609#define IRQ_TWI1 0x4000 /* TWI1 */
1610#define nIRQ_TWI1 0x0
1611#define IRQ_CAN0_RX 0x8000 /* CAN0 Receive */
1612#define nIRQ_CAN0_RX 0x0
1613#define IRQ_CAN0_TX 0x10000 /* CAN0 Transmit */
1614#define nIRQ_CAN0_TX 0x0
1615#define IRQ_MDMA2 0x20000 /* Memory DMA Stream 0 */
1616#define nIRQ_MDMA2 0x0
1617#define IRQ_MDMA3 0x40000 /* Memory DMA Stream 1 */
1618#define nIRQ_MDMA3 0x0
1619#define IRQ_MXVR_STAT 0x80000 /* MXVR Status */
1620#define nIRQ_MXVR_STAT 0x0
1621#define IRQ_MXVR_CM 0x100000 /* MXVR Control Message */
1622#define nIRQ_MXVR_CM 0x0
1623#define IRQ_MXVR_AP 0x200000 /* MXVR Asynchronous Packet */
1624#define nIRQ_MXVR_AP 0x0
1625#define IRQ_EPPI1_ERR 0x400000 /* EPPI1 Error */
1626#define nIRQ_EPPI1_ERR 0x0
1627#define IRQ_EPPI2_ERR 0x800000 /* EPPI2 Error */
1628#define nIRQ_EPPI2_ERR 0x0
1629#define IRQ_UART3_ERR 0x1000000 /* UART3 Error */
1630#define nIRQ_UART3_ERR 0x0
1631#define IRQ_HOST_ERR 0x2000000 /* Host DMA Port Error */
1632#define nIRQ_HOST_ERR 0x0
1633#define IRQ_USB_ERR 0x4000000 /* USB Error */
1634#define nIRQ_USB_ERR 0x0
1635#define IRQ_PIXC_ERR 0x8000000 /* Pixel Compositor Error */
1636#define nIRQ_PIXC_ERR 0x0
1637#define IRQ_NFC_ERR 0x10000000 /* Nand Flash Controller Error */
1638#define nIRQ_NFC_ERR 0x0
1639#define IRQ_ATAPI_ERR 0x20000000 /* ATAPI Error */
1640#define nIRQ_ATAPI_ERR 0x0
1641#define IRQ_CAN1_ERR 0x40000000 /* CAN1 Error */
1642#define nIRQ_CAN1_ERR 0x0
1643#define IRQ_DMAR0_ERR 0x80000000 /* DMAR0 Overflow Error */
1644#define nIRQ_DMAR0_ERR 0x0
1645#define IRQ_DMAR1_ERR 0x80000000 /* DMAR1 Overflow Error */
1646#define nIRQ_DMAR1_ERR 0x0
1647#define IRQ_DMAR0 0x80000000 /* DMAR0 Block */
1648#define nIRQ_DMAR0 0x0
1649#define IRQ_DMAR1 0x80000000 /* DMAR1 Block */
1650#define nIRQ_DMAR1 0x0
1651
1652/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
1653
1654#define IRQ_DMA15 0x1 /* DMA Channel 15 */
1655#define nIRQ_DMA15 0x0
1656#define IRQ_DMA16 0x2 /* DMA Channel 16 */
1657#define nIRQ_DMA16 0x0
1658#define IRQ_DMA17 0x4 /* DMA Channel 17 */
1659#define nIRQ_DMA17 0x0
1660#define IRQ_DMA22 0x8 /* DMA Channel 22 */
1661#define nIRQ_DMA22 0x0
1662#define IRQ_CNT 0x10 /* Counter */
1663#define nIRQ_CNT 0x0
1664#define IRQ_KEY 0x20 /* Keypad */
1665#define nIRQ_KEY 0x0
1666#define IRQ_CAN1_RX 0x40 /* CAN1 Receive */
1667#define nIRQ_CAN1_RX 0x0
1668#define IRQ_CAN1_TX 0x80 /* CAN1 Transmit */
1669#define nIRQ_CAN1_TX 0x0
1670#define IRQ_SDH_MASK0 0x100 /* SDH Mask 0 */
1671#define nIRQ_SDH_MASK0 0x0
1672#define IRQ_SDH_MASK1 0x200 /* SDH Mask 1 */
1673#define nIRQ_SDH_MASK1 0x0
1674#define IRQ_USB_EINT 0x400 /* USB Exception */
1675#define nIRQ_USB_EINT 0x0
1676#define IRQ_USB_INT0 0x800 /* USB Interrupt 0 */
1677#define nIRQ_USB_INT0 0x0
1678#define IRQ_USB_INT1 0x1000 /* USB Interrupt 1 */
1679#define nIRQ_USB_INT1 0x0
1680#define IRQ_USB_INT2 0x2000 /* USB Interrupt 2 */
1681#define nIRQ_USB_INT2 0x0
1682#define IRQ_USB_DMAINT 0x4000 /* USB DMA */
1683#define nIRQ_USB_DMAINT 0x0
1684#define IRQ_OTPSEC 0x8000 /* OTP Access Complete */
1685#define nIRQ_OTPSEC 0x0
1686#define IRQ_TIMER0 0x400000 /* Timer 0 */
1687#define nIRQ_TIMER0 0x0
1688#define IRQ_TIMER1 0x800000 /* Timer 1 */
1689#define nIRQ_TIMER1 0x0
1690#define IRQ_TIMER2 0x1000000 /* Timer 2 */
1691#define nIRQ_TIMER2 0x0
1692#define IRQ_TIMER3 0x2000000 /* Timer 3 */
1693#define nIRQ_TIMER3 0x0
1694#define IRQ_TIMER4 0x4000000 /* Timer 4 */
1695#define nIRQ_TIMER4 0x0
1696#define IRQ_TIMER5 0x8000000 /* Timer 5 */
1697#define nIRQ_TIMER5 0x0
1698#define IRQ_TIMER6 0x10000000 /* Timer 6 */
1699#define nIRQ_TIMER6 0x0
1700#define IRQ_TIMER7 0x20000000 /* Timer 7 */
1701#define nIRQ_TIMER7 0x0
1702#define IRQ_PINT2 0x40000000 /* Pin Interrupt 2 */
1703#define nIRQ_PINT2 0x0
1704#define IRQ_PINT3 0x80000000 /* Pin Interrupt 3 */
1705#define nIRQ_PINT3 0x0
1706
1707/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
1708
1709#define DMAEN 0x1 /* DMA Channel Enable */
1710#define nDMAEN 0x0
1711#define WNR 0x2 /* DMA Direction */
1712#define nWNR 0x0
1713#define WDSIZE 0xc /* Transfer Word Size */
1714#define DMA2D 0x10 /* DMA Mode */
1715#define nDMA2D 0x0
1716#define RESTART 0x20 /* Work Unit Transitions */
1717#define nRESTART 0x0
1718#define DI_SEL 0x40 /* Data Interrupt Timing Select */
1719#define nDI_SEL 0x0
1720#define DI_EN 0x80 /* Data Interrupt Enable */
1721#define nDI_EN 0x0
1722#define NDSIZE 0xf00 /* Flex Descriptor Size */
1723#define DMAFLOW 0xf000 /* Next Operation */
1724
1725/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1726
1727#define DMA_DONE 0x1 /* DMA Completion Interrupt Status */
1728#define nDMA_DONE 0x0
1729#define DMA_ERR 0x2 /* DMA Error Interrupt Status */
1730#define nDMA_ERR 0x0
1731#define DFETCH 0x4 /* DMA Descriptor Fetch */
1732#define nDFETCH 0x0
1733#define DMA_RUN 0x8 /* DMA Channel Running */
1734#define nDMA_RUN 0x0
1735
1736/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
1737
1738#define CTYPE 0x40 /* DMA Channel Type */
1739#define nCTYPE 0x0
1740#define PMAP 0xf000 /* Peripheral Mapped To This Channel */
1741
1742/* Bit masks for DMACx_TCPER */
1743
1744#define DCB_TRAFFIC_PERIOD 0xf /* DCB Traffic Control Period */
1745#define DEB_TRAFFIC_PERIOD 0xf0 /* DEB Traffic Control Period */
1746#define DAB_TRAFFIC_PERIOD 0x700 /* DAB Traffic Control Period */
1747#define MDMA_ROUND_ROBIN_PERIOD 0xf800 /* MDMA Round Robin Period */
1748
1749/* Bit masks for DMACx_TCCNT */
1750
1751#define DCB_TRAFFIC_COUNT 0xf /* DCB Traffic Control Count */
1752#define DEB_TRAFFIC_COUNT 0xf0 /* DEB Traffic Control Count */
1753#define DAB_TRAFFIC_COUNT 0x700 /* DAB Traffic Control Count */
1754#define MDMA_ROUND_ROBIN_COUNT 0xf800 /* MDMA Round Robin Count */
1755
1756/* Bit masks for DMAC1_PERIMUX */
1757
1758#define PMUXSDH 0x1 /* Peripheral Select for DMA22 channel */
1759#define nPMUXSDH 0x0
1760
1761/* Bit masks for EBIU_AMGCTL */
1762
1763#define AMCKEN 0x1 /* Async Memory Enable */
1764#define nAMCKEN 0x0
1765#define AMBEN 0xe /* Async bank enable */
1766
1767/* Bit masks for EBIU_AMBCTL0 */
1768
1769#define B0RDYEN 0x1 /* Bank 0 ARDY Enable */
1770#define nB0RDYEN 0x0
1771#define B0RDYPOL 0x2 /* Bank 0 ARDY Polarity */
1772#define nB0RDYPOL 0x0
1773#define B0TT 0xc /* Bank 0 transition time */
1774#define B0ST 0x30 /* Bank 0 Setup time */
1775#define B0HT 0xc0 /* Bank 0 Hold time */
1776#define B0RAT 0xf00 /* Bank 0 Read access time */
1777#define B0WAT 0xf000 /* Bank 0 write access time */
1778#define B1RDYEN 0x10000 /* Bank 1 ARDY Enable */
1779#define nB1RDYEN 0x0
1780#define B1RDYPOL 0x20000 /* Bank 1 ARDY Polarity */
1781#define nB1RDYPOL 0x0
1782#define B1TT 0xc0000 /* Bank 1 transition time */
1783#define B1ST 0x300000 /* Bank 1 Setup time */
1784#define B1HT 0xc00000 /* Bank 1 Hold time */
1785#define B1RAT 0xf000000 /* Bank 1 Read access time */
1786#define B1WAT 0xf0000000 /* Bank 1 write access time */
1787
1788/* Bit masks for EBIU_AMBCTL1 */
1789
1790#define B2RDYEN 0x1 /* Bank 2 ARDY Enable */
1791#define nB2RDYEN 0x0
1792#define B2RDYPOL 0x2 /* Bank 2 ARDY Polarity */
1793#define nB2RDYPOL 0x0
1794#define B2TT 0xc /* Bank 2 transition time */
1795#define B2ST 0x30 /* Bank 2 Setup time */
1796#define B2HT 0xc0 /* Bank 2 Hold time */
1797#define B2RAT 0xf00 /* Bank 2 Read access time */
1798#define B2WAT 0xf000 /* Bank 2 write access time */
1799#define B3RDYEN 0x10000 /* Bank 3 ARDY Enable */
1800#define nB3RDYEN 0x0
1801#define B3RDYPOL 0x20000 /* Bank 3 ARDY Polarity */
1802#define nB3RDYPOL 0x0
1803#define B3TT 0xc0000 /* Bank 3 transition time */
1804#define B3ST 0x300000 /* Bank 3 Setup time */
1805#define B3HT 0xc00000 /* Bank 3 Hold time */
1806#define B3RAT 0xf000000 /* Bank 3 Read access time */
1807#define B3WAT 0xf0000000 /* Bank 3 write access time */
1808
1809/* Bit masks for EBIU_MBSCTL */
1810
1811#define AMSB0CTL 0x3 /* Async Memory Bank 0 select */
1812#define AMSB1CTL 0xc /* Async Memory Bank 1 select */
1813#define AMSB2CTL 0x30 /* Async Memory Bank 2 select */
1814#define AMSB3CTL 0xc0 /* Async Memory Bank 3 select */
1815
1816/* Bit masks for EBIU_MODE */
1817
1818#define B0MODE 0x3 /* Async Memory Bank 0 Access Mode */
1819#define B1MODE 0xc /* Async Memory Bank 1 Access Mode */
1820#define B2MODE 0x30 /* Async Memory Bank 2 Access Mode */
1821#define B3MODE 0xc0 /* Async Memory Bank 3 Access Mode */
1822
1823/* Bit masks for EBIU_FCTL */
1824
1825#define TESTSETLOCK 0x1 /* Test set lock */
1826#define nTESTSETLOCK 0x0
1827#define BCLK 0x6 /* Burst clock frequency */
1828#define PGWS 0x38 /* Page wait states */
1829#define PGSZ 0x40 /* Page size */
1830#define nPGSZ 0x0
1831#define RDDL 0x380 /* Read data delay */
1832
1833/* Bit masks for EBIU_ARBSTAT */
1834
1835#define ARBSTAT 0x1 /* Arbitration status */
1836#define nARBSTAT 0x0
1837#define BGSTAT 0x2 /* Bus grant status */
1838#define nBGSTAT 0x0
1839
1840/* Bit masks for EBIU_DDRCTL0 */
1841
1842#define TREFI 0x3fff /* Refresh Interval */
1843#define TRFC 0x3c000 /* Auto-refresh command period */
1844#define TRP 0x3c0000 /* Pre charge-to-active command period */
1845#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1846#define TRC 0x3c000000 /* Active-to-active time */
1847
1848/* Bit masks for EBIU_DDRCTL1 */
1849
1850#define TRCD 0xf /* Active-to-Read/write delay */
1851#define MRD 0xf0 /* Mode register set to active */
1852#define TWR 0x300 /* Write Recovery time */
1853#define DDRDATWIDTH 0x3000 /* DDR data width */
1854#define EXTBANKS 0xc000 /* External banks */
1855#define DDRDEVWIDTH 0x30000 /* DDR device width */
1856#define DDRDEVSIZE 0xc0000 /* DDR device size */
1857#define TWWTR 0xf0000000 /* Write-to-read delay */
1858
1859/* Bit masks for EBIU_DDRCTL2 */
1860
1861#define BURSTLENGTH 0x7 /* Burst length */
1862#define CASLATENCY 0x70 /* CAS latency */
1863#define DLLRESET 0x100 /* DLL Reset */
1864#define nDLLRESET 0x0
1865#define REGE 0x1000 /* Register mode enable */
1866#define nREGE 0x0
1867
1868/* Bit masks for EBIU_DDRCTL3 */
1869
1870#define PASR 0x7 /* Partial array self-refresh */
1871
1872/* Bit masks for EBIU_DDRQUE */
1873
1874#define DEB1_PFLEN 0x3 /* Pre fetch length for DEB1 accesses */
1875#define DEB2_PFLEN 0xc /* Pre fetch length for DEB2 accesses */
1876#define DEB3_PFLEN 0x30 /* Pre fetch length for DEB3 accesses */
1877#define DEB_ARB_PRIORITY 0x700 /* Arbitration between DEB busses */
1878#define DEB1_URGENT 0x1000 /* DEB1 Urgent */
1879#define nDEB1_URGENT 0x0
1880#define DEB2_URGENT 0x2000 /* DEB2 Urgent */
1881#define nDEB2_URGENT 0x0
1882#define DEB3_URGENT 0x4000 /* DEB3 Urgent */
1883#define nDEB3_URGENT 0x0
1884
1885/* Bit masks for EBIU_ERRMST */
1886
1887#define DEB1_ERROR 0x1 /* DEB1 Error */
1888#define nDEB1_ERROR 0x0
1889#define DEB2_ERROR 0x2 /* DEB2 Error */
1890#define nDEB2_ERROR 0x0
1891#define DEB3_ERROR 0x4 /* DEB3 Error */
1892#define nDEB3_ERROR 0x0
1893#define CORE_ERROR 0x8 /* Core error */
1894#define nCORE_ERROR 0x0
1895#define DEB_MERROR 0x10 /* DEB1 Error (2nd) */
1896#define nDEB_MERROR 0x0
1897#define DEB2_MERROR 0x20 /* DEB2 Error (2nd) */
1898#define nDEB2_MERROR 0x0
1899#define DEB3_MERROR 0x40 /* DEB3 Error (2nd) */
1900#define nDEB3_MERROR 0x0
1901#define CORE_MERROR 0x80 /* Core Error (2nd) */
1902#define nCORE_MERROR 0x0
1903
1904/* Bit masks for EBIU_ERRADD */
1905
1906#define ERROR_ADDRESS 0xffffffff /* Error Address */
1907
1908/* Bit masks for EBIU_RSTCTL */
1909
1910#define DDRSRESET 0x1 /* DDR soft reset */
1911#define nDDRSRESET 0x0
1912#define PFTCHSRESET 0x4 /* DDR prefetch reset */
1913#define nPFTCHSRESET 0x0
1914#define SRREQ 0x8 /* Self-refresh request */
1915#define nSRREQ 0x0
1916#define SRACK 0x10 /* Self-refresh acknowledge */
1917#define nSRACK 0x0
1918#define MDDRENABLE 0x20 /* Mobile DDR enable */
1919#define nMDDRENABLE 0x0
1920
1921/* Bit masks for EBIU_DDRBRC0 */
1922
1923#define BRC0 0xffffffff /* Count */
1924
1925/* Bit masks for EBIU_DDRBRC1 */
1926
1927#define BRC1 0xffffffff /* Count */
1928
1929/* Bit masks for EBIU_DDRBRC2 */
1930
1931#define BRC2 0xffffffff /* Count */
1932
1933/* Bit masks for EBIU_DDRBRC3 */
1934
1935#define BRC3 0xffffffff /* Count */
1936
1937/* Bit masks for EBIU_DDRBRC4 */
1938
1939#define BRC4 0xffffffff /* Count */
1940
1941/* Bit masks for EBIU_DDRBRC5 */
1942
1943#define BRC5 0xffffffff /* Count */
1944
1945/* Bit masks for EBIU_DDRBRC6 */
1946
1947#define BRC6 0xffffffff /* Count */
1948
1949/* Bit masks for EBIU_DDRBRC7 */
1950
1951#define BRC7 0xffffffff /* Count */
1952
1953/* Bit masks for EBIU_DDRBWC0 */
1954
1955#define BWC0 0xffffffff /* Count */
1956
1957/* Bit masks for EBIU_DDRBWC1 */
1958
1959#define BWC1 0xffffffff /* Count */
1960
1961/* Bit masks for EBIU_DDRBWC2 */
1962
1963#define BWC2 0xffffffff /* Count */
1964
1965/* Bit masks for EBIU_DDRBWC3 */
1966
1967#define BWC3 0xffffffff /* Count */
1968
1969/* Bit masks for EBIU_DDRBWC4 */
1970
1971#define BWC4 0xffffffff /* Count */
1972
1973/* Bit masks for EBIU_DDRBWC5 */
1974
1975#define BWC5 0xffffffff /* Count */
1976
1977/* Bit masks for EBIU_DDRBWC6 */
1978
1979#define BWC6 0xffffffff /* Count */
1980
1981/* Bit masks for EBIU_DDRBWC7 */
1982
1983#define BWC7 0xffffffff /* Count */
1984
1985/* Bit masks for EBIU_DDRACCT */
1986
1987#define ACCT 0xffffffff /* Count */
1988
1989/* Bit masks for EBIU_DDRTACT */
1990
1991#define TECT 0xffffffff /* Count */
1992
1993/* Bit masks for EBIU_DDRARCT */
1994
1995#define ARCT 0xffffffff /* Count */
1996
1997/* Bit masks for EBIU_DDRGC0 */
1998
1999#define GC0 0xffffffff /* Count */
2000
2001/* Bit masks for EBIU_DDRGC1 */
2002
2003#define GC1 0xffffffff /* Count */
2004
2005/* Bit masks for EBIU_DDRGC2 */
2006
2007#define GC2 0xffffffff /* Count */
2008
2009/* Bit masks for EBIU_DDRGC3 */
2010
2011#define GC3 0xffffffff /* Count */
2012
2013/* Bit masks for EBIU_DDRMCEN */
2014
2015#define B0WCENABLE 0x1 /* Bank 0 write count enable */
2016#define nB0WCENABLE 0x0
2017#define B1WCENABLE 0x2 /* Bank 1 write count enable */
2018#define nB1WCENABLE 0x0
2019#define B2WCENABLE 0x4 /* Bank 2 write count enable */
2020#define nB2WCENABLE 0x0
2021#define B3WCENABLE 0x8 /* Bank 3 write count enable */
2022#define nB3WCENABLE 0x0
2023#define B4WCENABLE 0x10 /* Bank 4 write count enable */
2024#define nB4WCENABLE 0x0
2025#define B5WCENABLE 0x20 /* Bank 5 write count enable */
2026#define nB5WCENABLE 0x0
2027#define B6WCENABLE 0x40 /* Bank 6 write count enable */
2028#define nB6WCENABLE 0x0
2029#define B7WCENABLE 0x80 /* Bank 7 write count enable */
2030#define nB7WCENABLE 0x0
2031#define B0RCENABLE 0x100 /* Bank 0 read count enable */
2032#define nB0RCENABLE 0x0
2033#define B1RCENABLE 0x200 /* Bank 1 read count enable */
2034#define nB1RCENABLE 0x0
2035#define B2RCENABLE 0x400 /* Bank 2 read count enable */
2036#define nB2RCENABLE 0x0
2037#define B3RCENABLE 0x800 /* Bank 3 read count enable */
2038#define nB3RCENABLE 0x0
2039#define B4RCENABLE 0x1000 /* Bank 4 read count enable */
2040#define nB4RCENABLE 0x0
2041#define B5RCENABLE 0x2000 /* Bank 5 read count enable */
2042#define nB5RCENABLE 0x0
2043#define B6RCENABLE 0x4000 /* Bank 6 read count enable */
2044#define nB6RCENABLE 0x0
2045#define B7RCENABLE 0x8000 /* Bank 7 read count enable */
2046#define nB7RCENABLE 0x0
2047#define ROWACTCENABLE 0x10000 /* DDR Row activate count enable */
2048#define nROWACTCENABLE 0x0
2049#define RWTCENABLE 0x20000 /* DDR R/W Turn around count enable */
2050#define nRWTCENABLE 0x0
2051#define ARCENABLE 0x40000 /* DDR Auto-refresh count enable */
2052#define nARCENABLE 0x0
2053#define GC0ENABLE 0x100000 /* DDR Grant count 0 enable */
2054#define nGC0ENABLE 0x0
2055#define GC1ENABLE 0x200000 /* DDR Grant count 1 enable */
2056#define nGC1ENABLE 0x0
2057#define GC2ENABLE 0x400000 /* DDR Grant count 2 enable */
2058#define nGC2ENABLE 0x0
2059#define GC3ENABLE 0x800000 /* DDR Grant count 3 enable */
2060#define nGC3ENABLE 0x0
2061#define GCCONTROL 0x3000000 /* DDR Grant Count Control */
2062
2063/* Bit masks for EBIU_DDRMCCL */
2064
2065#define CB0WCOUNT 0x1 /* Clear write count 0 */
2066#define nCB0WCOUNT 0x0
2067#define CB1WCOUNT 0x2 /* Clear write count 1 */
2068#define nCB1WCOUNT 0x0
2069#define CB2WCOUNT 0x4 /* Clear write count 2 */
2070#define nCB2WCOUNT 0x0
2071#define CB3WCOUNT 0x8 /* Clear write count 3 */
2072#define nCB3WCOUNT 0x0
2073#define CB4WCOUNT 0x10 /* Clear write count 4 */
2074#define nCB4WCOUNT 0x0
2075#define CB5WCOUNT 0x20 /* Clear write count 5 */
2076#define nCB5WCOUNT 0x0
2077#define CB6WCOUNT 0x40 /* Clear write count 6 */
2078#define nCB6WCOUNT 0x0
2079#define CB7WCOUNT 0x80 /* Clear write count 7 */
2080#define nCB7WCOUNT 0x0
2081#define CBRCOUNT 0x100 /* Clear read count 0 */
2082#define nCBRCOUNT 0x0
2083#define CB1RCOUNT 0x200 /* Clear read count 1 */
2084#define nCB1RCOUNT 0x0
2085#define CB2RCOUNT 0x400 /* Clear read count 2 */
2086#define nCB2RCOUNT 0x0
2087#define CB3RCOUNT 0x800 /* Clear read count 3 */
2088#define nCB3RCOUNT 0x0
2089#define CB4RCOUNT 0x1000 /* Clear read count 4 */
2090#define nCB4RCOUNT 0x0
2091#define CB5RCOUNT 0x2000 /* Clear read count 5 */
2092#define nCB5RCOUNT 0x0
2093#define CB6RCOUNT 0x4000 /* Clear read count 6 */
2094#define nCB6RCOUNT 0x0
2095#define CB7RCOUNT 0x8000 /* Clear read count 7 */
2096#define nCB7RCOUNT 0x0
2097#define CRACOUNT 0x10000 /* Clear row activation count */
2098#define nCRACOUNT 0x0
2099#define CRWTACOUNT 0x20000 /* Clear R/W turn-around count */
2100#define nCRWTACOUNT 0x0
2101#define CARCOUNT 0x40000 /* Clear auto-refresh count */
2102#define nCARCOUNT 0x0
2103#define CG0COUNT 0x100000 /* Clear grant count 0 */
2104#define nCG0COUNT 0x0
2105#define CG1COUNT 0x200000 /* Clear grant count 1 */
2106#define nCG1COUNT 0x0
2107#define CG2COUNT 0x400000 /* Clear grant count 2 */
2108#define nCG2COUNT 0x0
2109#define CG3COUNT 0x800000 /* Clear grant count 3 */
2110#define nCG3COUNT 0x0
2111
2112/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
2113
2114#define Px0 0x1 /* GPIO 0 */
2115#define nPx0 0x0
2116#define Px1 0x2 /* GPIO 1 */
2117#define nPx1 0x0
2118#define Px2 0x4 /* GPIO 2 */
2119#define nPx2 0x0
2120#define Px3 0x8 /* GPIO 3 */
2121#define nPx3 0x0
2122#define Px4 0x10 /* GPIO 4 */
2123#define nPx4 0x0
2124#define Px5 0x20 /* GPIO 5 */
2125#define nPx5 0x0
2126#define Px6 0x40 /* GPIO 6 */
2127#define nPx6 0x0
2128#define Px7 0x80 /* GPIO 7 */
2129#define nPx7 0x0
2130#define Px8 0x100 /* GPIO 8 */
2131#define nPx8 0x0
2132#define Px9 0x200 /* GPIO 9 */
2133#define nPx9 0x0
2134#define Px10 0x400 /* GPIO 10 */
2135#define nPx10 0x0
2136#define Px11 0x800 /* GPIO 11 */
2137#define nPx11 0x0
2138#define Px12 0x1000 /* GPIO 12 */
2139#define nPx12 0x0
2140#define Px13 0x2000 /* GPIO 13 */
2141#define nPx13 0x0
2142#define Px14 0x4000 /* GPIO 14 */
2143#define nPx14 0x0
2144#define Px15 0x8000 /* GPIO 15 */
2145#define nPx15 0x0
2146
2147/* Bit masks for PORTA_MUX - PORTJ_MUX */
2148
2149#define PxM0 0x3 /* GPIO Mux 0 */
2150#define PxM1 0xc /* GPIO Mux 1 */
2151#define PxM2 0x30 /* GPIO Mux 2 */
2152#define PxM3 0xc0 /* GPIO Mux 3 */
2153#define PxM4 0x300 /* GPIO Mux 4 */
2154#define PxM5 0xc00 /* GPIO Mux 5 */
2155#define PxM6 0x3000 /* GPIO Mux 6 */
2156#define PxM7 0xc000 /* GPIO Mux 7 */
2157#define PxM8 0x30000 /* GPIO Mux 8 */
2158#define PxM9 0xc0000 /* GPIO Mux 9 */
2159#define PxM10 0x300000 /* GPIO Mux 10 */
2160#define PxM11 0xc00000 /* GPIO Mux 11 */
2161#define PxM12 0x3000000 /* GPIO Mux 12 */
2162#define PxM13 0xc000000 /* GPIO Mux 13 */
2163#define PxM14 0x30000000 /* GPIO Mux 14 */
2164#define PxM15 0xc0000000 /* GPIO Mux 15 */
2165
2166
2167/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
2168
2169#define IB0 0x1 /* Interrupt Bit 0 */
2170#define nIB0 0x0
2171#define IB1 0x2 /* Interrupt Bit 1 */
2172#define nIB1 0x0
2173#define IB2 0x4 /* Interrupt Bit 2 */
2174#define nIB2 0x0
2175#define IB3 0x8 /* Interrupt Bit 3 */
2176#define nIB3 0x0
2177#define IB4 0x10 /* Interrupt Bit 4 */
2178#define nIB4 0x0
2179#define IB5 0x20 /* Interrupt Bit 5 */
2180#define nIB5 0x0
2181#define IB6 0x40 /* Interrupt Bit 6 */
2182#define nIB6 0x0
2183#define IB7 0x80 /* Interrupt Bit 7 */
2184#define nIB7 0x0
2185#define IB8 0x100 /* Interrupt Bit 8 */
2186#define nIB8 0x0
2187#define IB9 0x200 /* Interrupt Bit 9 */
2188#define nIB9 0x0
2189#define IB10 0x400 /* Interrupt Bit 10 */
2190#define nIB10 0x0
2191#define IB11 0x800 /* Interrupt Bit 11 */
2192#define nIB11 0x0
2193#define IB12 0x1000 /* Interrupt Bit 12 */
2194#define nIB12 0x0
2195#define IB13 0x2000 /* Interrupt Bit 13 */
2196#define nIB13 0x0
2197#define IB14 0x4000 /* Interrupt Bit 14 */
2198#define nIB14 0x0
2199#define IB15 0x8000 /* Interrupt Bit 15 */
2200#define nIB15 0x0
2201
2202/* Bit masks for TIMERx_CONFIG */
2203
2204#define TMODE 0x3 /* Timer Mode */
2205#define PULSE_HI 0x4 /* Pulse Polarity */
2206#define nPULSE_HI 0x0
2207#define PERIOD_CNT 0x8 /* Period Count */
2208#define nPERIOD_CNT 0x0
2209#define IRQ_ENA 0x10 /* Interrupt Request Enable */
2210#define nIRQ_ENA 0x0
2211#define TIN_SEL 0x20 /* Timer Input Select */
2212#define nTIN_SEL 0x0
2213#define OUT_DIS 0x40 /* Output Pad Disable */
2214#define nOUT_DIS 0x0
2215#define CLK_SEL 0x80 /* Timer Clock Select */
2216#define nCLK_SEL 0x0
2217#define TOGGLE_HI 0x100 /* Toggle Mode */
2218#define nTOGGLE_HI 0x0
2219#define EMU_RUN 0x200 /* Emulation Behavior Select */
2220#define nEMU_RUN 0x0
2221#define ERR_TYP 0xc000 /* Error Type */
2222
2223/* Bit masks for TIMER_ENABLE0 */
2224
2225#define TIMEN0 0x1 /* Timer 0 Enable */
2226#define nTIMEN0 0x0
2227#define TIMEN1 0x2 /* Timer 1 Enable */
2228#define nTIMEN1 0x0
2229#define TIMEN2 0x4 /* Timer 2 Enable */
2230#define nTIMEN2 0x0
2231#define TIMEN3 0x8 /* Timer 3 Enable */
2232#define nTIMEN3 0x0
2233#define TIMEN4 0x10 /* Timer 4 Enable */
2234#define nTIMEN4 0x0
2235#define TIMEN5 0x20 /* Timer 5 Enable */
2236#define nTIMEN5 0x0
2237#define TIMEN6 0x40 /* Timer 6 Enable */
2238#define nTIMEN6 0x0
2239#define TIMEN7 0x80 /* Timer 7 Enable */
2240#define nTIMEN7 0x0
2241
2242/* Bit masks for TIMER_DISABLE0 */
2243
2244#define TIMDIS0 0x1 /* Timer 0 Disable */
2245#define nTIMDIS0 0x0
2246#define TIMDIS1 0x2 /* Timer 1 Disable */
2247#define nTIMDIS1 0x0
2248#define TIMDIS2 0x4 /* Timer 2 Disable */
2249#define nTIMDIS2 0x0
2250#define TIMDIS3 0x8 /* Timer 3 Disable */
2251#define nTIMDIS3 0x0
2252#define TIMDIS4 0x10 /* Timer 4 Disable */
2253#define nTIMDIS4 0x0
2254#define TIMDIS5 0x20 /* Timer 5 Disable */
2255#define nTIMDIS5 0x0
2256#define TIMDIS6 0x40 /* Timer 6 Disable */
2257#define nTIMDIS6 0x0
2258#define TIMDIS7 0x80 /* Timer 7 Disable */
2259#define nTIMDIS7 0x0
2260
2261/* Bit masks for TIMER_STATUS0 */
2262
2263#define TIMIL0 0x1 /* Timer 0 Interrupt */
2264#define nTIMIL0 0x0
2265#define TIMIL1 0x2 /* Timer 1 Interrupt */
2266#define nTIMIL1 0x0
2267#define TIMIL2 0x4 /* Timer 2 Interrupt */
2268#define nTIMIL2 0x0
2269#define TIMIL3 0x8 /* Timer 3 Interrupt */
2270#define nTIMIL3 0x0
2271#define TOVF_ERR0 0x10 /* Timer 0 Counter Overflow */
2272#define nTOVF_ERR0 0x0
2273#define TOVF_ERR1 0x20 /* Timer 1 Counter Overflow */
2274#define nTOVF_ERR1 0x0
2275#define TOVF_ERR2 0x40 /* Timer 2 Counter Overflow */
2276#define nTOVF_ERR2 0x0
2277#define TOVF_ERR3 0x80 /* Timer 3 Counter Overflow */
2278#define nTOVF_ERR3 0x0
2279#define TRUN0 0x1000 /* Timer 0 Slave Enable Status */
2280#define nTRUN0 0x0
2281#define TRUN1 0x2000 /* Timer 1 Slave Enable Status */
2282#define nTRUN1 0x0
2283#define TRUN2 0x4000 /* Timer 2 Slave Enable Status */
2284#define nTRUN2 0x0
2285#define TRUN3 0x8000 /* Timer 3 Slave Enable Status */
2286#define nTRUN3 0x0
2287#define TIMIL4 0x10000 /* Timer 4 Interrupt */
2288#define nTIMIL4 0x0
2289#define TIMIL5 0x20000 /* Timer 5 Interrupt */
2290#define nTIMIL5 0x0
2291#define TIMIL6 0x40000 /* Timer 6 Interrupt */
2292#define nTIMIL6 0x0
2293#define TIMIL7 0x80000 /* Timer 7 Interrupt */
2294#define nTIMIL7 0x0
2295#define TOVF_ERR4 0x100000 /* Timer 4 Counter Overflow */
2296#define nTOVF_ERR4 0x0
2297#define TOVF_ERR5 0x200000 /* Timer 5 Counter Overflow */
2298#define nTOVF_ERR5 0x0
2299#define TOVF_ERR6 0x400000 /* Timer 6 Counter Overflow */
2300#define nTOVF_ERR6 0x0
2301#define TOVF_ERR7 0x800000 /* Timer 7 Counter Overflow */
2302#define nTOVF_ERR7 0x0
2303#define TRUN4 0x10000000 /* Timer 4 Slave Enable Status */
2304#define nTRUN4 0x0
2305#define TRUN5 0x20000000 /* Timer 5 Slave Enable Status */
2306#define nTRUN5 0x0
2307#define TRUN6 0x40000000 /* Timer 6 Slave Enable Status */
2308#define nTRUN6 0x0
2309#define TRUN7 0x80000000 /* Timer 7 Slave Enable Status */
2310#define nTRUN7 0x0
2311
2312/* Bit masks for WDOG_CTL */
2313
2314#define WDEV 0x6 /* Watchdog Event */
2315#define WDEN 0xff0 /* Watchdog Enable */
2316#define WDRO 0x8000 /* Watchdog Rolled Over */
2317#define nWDRO 0x0
2318
2319/* Bit masks for CNT_CONFIG */
2320
2321#define CNTE 0x1 /* Counter Enable */
2322#define nCNTE 0x0
2323#define DEBE 0x2 /* Debounce Enable */
2324#define nDEBE 0x0
2325#define CDGINV 0x10 /* CDG Pin Polarity Invert */
2326#define nCDGINV 0x0
2327#define CUDINV 0x20 /* CUD Pin Polarity Invert */
2328#define nCUDINV 0x0
2329#define CZMINV 0x40 /* CZM Pin Polarity Invert */
2330#define nCZMINV 0x0
2331#define CNTMODE 0x700 /* Counter Operating Mode */
2332#define ZMZC 0x800 /* CZM Zeroes Counter Enable */
2333#define nZMZC 0x0
2334#define BNDMODE 0x3000 /* Boundary register Mode */
2335#define INPDIS 0x8000 /* CUG and CDG Input Disable */
2336#define nINPDIS 0x0
2337
2338/* Bit masks for CNT_IMASK */
2339
2340#define ICIE 0x1 /* Illegal Gray/Binary Code Interrupt Enable */
2341#define nICIE 0x0
2342#define UCIE 0x2 /* Up count Interrupt Enable */
2343#define nUCIE 0x0
2344#define DCIE 0x4 /* Down count Interrupt Enable */
2345#define nDCIE 0x0
2346#define MINCIE 0x8 /* Min Count Interrupt Enable */
2347#define nMINCIE 0x0
2348#define MAXCIE 0x10 /* Max Count Interrupt Enable */
2349#define nMAXCIE 0x0
2350#define COV31IE 0x20 /* Bit 31 Overflow Interrupt Enable */
2351#define nCOV31IE 0x0
2352#define COV15IE 0x40 /* Bit 15 Overflow Interrupt Enable */
2353#define nCOV15IE 0x0
2354#define CZEROIE 0x80 /* Count to Zero Interrupt Enable */
2355#define nCZEROIE 0x0
2356#define CZMIE 0x100 /* CZM Pin Interrupt Enable */
2357#define nCZMIE 0x0
2358#define CZMEIE 0x200 /* CZM Error Interrupt Enable */
2359#define nCZMEIE 0x0
2360#define CZMZIE 0x400 /* CZM Zeroes Counter Interrupt Enable */
2361#define nCZMZIE 0x0
2362
2363/* Bit masks for CNT_STATUS */
2364
2365#define ICII 0x1 /* Illegal Gray/Binary Code Interrupt Identifier */
2366#define nICII 0x0
2367#define UCII 0x2 /* Up count Interrupt Identifier */
2368#define nUCII 0x0
2369#define DCII 0x4 /* Down count Interrupt Identifier */
2370#define nDCII 0x0
2371#define MINCII 0x8 /* Min Count Interrupt Identifier */
2372#define nMINCII 0x0
2373#define MAXCII 0x10 /* Max Count Interrupt Identifier */
2374#define nMAXCII 0x0
2375#define COV31II 0x20 /* Bit 31 Overflow Interrupt Identifier */
2376#define nCOV31II 0x0
2377#define COV15II 0x40 /* Bit 15 Overflow Interrupt Identifier */
2378#define nCOV15II 0x0
2379#define CZEROII 0x80 /* Count to Zero Interrupt Identifier */
2380#define nCZEROII 0x0
2381#define CZMII 0x100 /* CZM Pin Interrupt Identifier */
2382#define nCZMII 0x0
2383#define CZMEII 0x200 /* CZM Error Interrupt Identifier */
2384#define nCZMEII 0x0
2385#define CZMZII 0x400 /* CZM Zeroes Counter Interrupt Identifier */
2386#define nCZMZII 0x0
2387
2388/* Bit masks for CNT_COMMAND */
2389
2390#define W1LCNT 0xf /* Load Counter Register */
2391#define W1LMIN 0xf0 /* Load Min Register */
2392#define W1LMAX 0xf00 /* Load Max Register */
2393#define W1ZMONCE 0x1000 /* Enable CZM Clear Counter Once */
2394#define nW1ZMONCE 0x0
2395
2396/* Bit masks for CNT_DEBOUNCE */
2397
2398#define DPRESCALE 0xf /* Load Counter Register */
2399
2400/* Bit masks for RTC_STAT */
2401
2402#define SECONDS 0x3f /* Seconds */
2403#define MINUTES 0xfc0 /* Minutes */
2404#define HOURS 0x1f000 /* Hours */
2405#define DAY_COUNTER 0xfffe0000 /* Day Counter */
2406
2407/* Bit masks for RTC_ICTL */
2408
2409#define STOPWATCH_INTERRUPT_ENABLE 0x1 /* Stopwatch Interrupt Enable */
2410#define nSTOPWATCH_INTERRUPT_ENABLE 0x0
2411#define ALARM_INTERRUPT_ENABLE 0x2 /* Alarm Interrupt Enable */
2412#define nALARM_INTERRUPT_ENABLE 0x0
2413#define SECONDS_INTERRUPT_ENABLE 0x4 /* Seconds Interrupt Enable */
2414#define nSECONDS_INTERRUPT_ENABLE 0x0
2415#define MINUTES_INTERRUPT_ENABLE 0x8 /* Minutes Interrupt Enable */
2416#define nMINUTES_INTERRUPT_ENABLE 0x0
2417#define HOURS_INTERRUPT_ENABLE 0x10 /* Hours Interrupt Enable */
2418#define nHOURS_INTERRUPT_ENABLE 0x0
2419#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x20 /* 24 Hours Interrupt Enable */
2420#define nTWENTY_FOUR_HOURS_INTERRUPT_ENABLE 0x0
2421#define DAY_ALARM_INTERRUPT_ENABLE 0x40 /* Day Alarm Interrupt Enable */
2422#define nDAY_ALARM_INTERRUPT_ENABLE 0x0
2423#define WRITE_COMPLETE_INTERRUPT_ENABLE 0x8000 /* Write Complete Interrupt Enable */
2424#define nWRITE_COMPLETE_INTERRUPT_ENABLE 0x0
2425
2426/* Bit masks for RTC_ISTAT */
2427
2428#define STOPWATCH_EVENT_FLAG 0x1 /* Stopwatch Event Flag */
2429#define nSTOPWATCH_EVENT_FLAG 0x0
2430#define ALARM_EVENT_FLAG 0x2 /* Alarm Event Flag */
2431#define nALARM_EVENT_FLAG 0x0
2432#define SECONDS_EVENT_FLAG 0x4 /* Seconds Event Flag */
2433#define nSECONDS_EVENT_FLAG 0x0
2434#define MINUTES_EVENT_FLAG 0x8 /* Minutes Event Flag */
2435#define nMINUTES_EVENT_FLAG 0x0
2436#define HOURS_EVENT_FLAG 0x10 /* Hours Event Flag */
2437#define nHOURS_EVENT_FLAG 0x0
2438#define TWENTY_FOUR_HOURS_EVENT_FLAG 0x20 /* 24 Hours Event Flag */
2439#define nTWENTY_FOUR_HOURS_EVENT_FLAG 0x0
2440#define DAY_ALARM_EVENT_FLAG 0x40 /* Day Alarm Event Flag */
2441#define nDAY_ALARM_EVENT_FLAG 0x0
2442#define WRITE_PENDING__STATUS 0x4000 /* Write Pending Status */
2443#define nWRITE_PENDING__STATUS 0x0
2444#define WRITE_COMPLETE 0x8000 /* Write Complete */
2445#define nWRITE_COMPLETE 0x0
2446
2447/* Bit masks for RTC_SWCNT */
2448
2449#define STOPWATCH_COUNT 0xffff /* Stopwatch Count */
2450
2451/* Bit masks for RTC_ALARM */
2452
2453#define SECONDS 0x3f /* Seconds */
2454#define MINUTES 0xfc0 /* Minutes */
2455#define HOURS 0x1f000 /* Hours */
2456#define DAY 0xfffe0000 /* Day */
2457
2458/* Bit masks for RTC_PREN */
2459
2460#define PREN 0x1 /* Prescaler Enable */
2461#define nPREN 0x0
2462
2463/* Bit masks for OTP_CONTROL */
2464
2465#define FUSE_FADDR 0x1ff /* OTP/Fuse Address */
2466#define FIEN 0x800 /* OTP/Fuse Interrupt Enable */
2467#define nFIEN 0x0
2468#define FTESTDEC 0x1000 /* OTP/Fuse Test Decoder */
2469#define nFTESTDEC 0x0
2470#define FWRTEST 0x2000 /* OTP/Fuse Write Test */
2471#define nFWRTEST 0x0
2472#define FRDEN 0x4000 /* OTP/Fuse Read Enable */
2473#define nFRDEN 0x0
2474#define FWREN 0x8000 /* OTP/Fuse Write Enable */
2475#define nFWREN 0x0
2476
2477/* Bit masks for OTP_BEN */
2478
2479#define FBEN 0xffff /* OTP/Fuse Byte Enable */
2480
2481/* Bit masks for OTP_STATUS */
2482
2483#define FCOMP 0x1 /* OTP/Fuse Access Complete */
2484#define nFCOMP 0x0
2485#define FERROR 0x2 /* OTP/Fuse Access Error */
2486#define nFERROR 0x0
2487#define MMRGLOAD 0x10 /* Memory Mapped Register Gasket Load */
2488#define nMMRGLOAD 0x0
2489#define MMRGLOCK 0x20 /* Memory Mapped Register Gasket Lock */
2490#define nMMRGLOCK 0x0
2491#define FPGMEN 0x40 /* OTP/Fuse Program Enable */
2492#define nFPGMEN 0x0
2493
2494/* Bit masks for OTP_TIMING */
2495
2496#define USECDIV 0xff /* Micro Second Divider */
2497#define READACC 0x7f00 /* Read Access Time */
2498#define CPUMPRL 0x38000 /* Charge Pump Release Time */
2499#define CPUMPSU 0xc0000 /* Charge Pump Setup Time */
2500#define CPUMPHD 0xf00000 /* Charge Pump Hold Time */
2501#define PGMTIME 0xff000000 /* Program Time */
2502
2503/* Bit masks for SECURE_SYSSWT */
2504
2505#define EMUDABL 0x1 /* Emulation Disable. */
2506#define nEMUDABL 0x0
2507#define RSTDABL 0x2 /* Reset Disable */
2508#define nRSTDABL 0x0
2509#define L1IDABL 0x1c /* L1 Instruction Memory Disable. */
2510#define L1DADABL 0xe0 /* L1 Data Bank A Memory Disable. */
2511#define L1DBDABL 0x700 /* L1 Data Bank B Memory Disable. */
2512#define DMA0OVR 0x800 /* DMA0 Memory Access Override */
2513#define nDMA0OVR 0x0
2514#define DMA1OVR 0x1000 /* DMA1 Memory Access Override */
2515#define nDMA1OVR 0x0
2516#define EMUOVR 0x4000 /* Emulation Override */
2517#define nEMUOVR 0x0
2518#define OTPSEN 0x8000 /* OTP Secrets Enable. */
2519#define nOTPSEN 0x0
2520#define L2DABL 0x70000 /* L2 Memory Disable. */
2521
2522/* Bit masks for SECURE_CONTROL */
2523
2524#define SECURE0 0x1 /* SECURE 0 */
2525#define nSECURE0 0x0
2526#define SECURE1 0x2 /* SECURE 1 */
2527#define nSECURE1 0x0
2528#define SECURE2 0x4 /* SECURE 2 */
2529#define nSECURE2 0x0
2530#define SECURE3 0x8 /* SECURE 3 */
2531#define nSECURE3 0x0
2532
2533/* Bit masks for SECURE_STATUS */
2534
2535#define SECMODE 0x3 /* Secured Mode Control State */
2536#define NMI 0x4 /* Non Maskable Interrupt */
2537#define nNMI 0x0
2538#define AFVALID 0x8 /* Authentication Firmware Valid */
2539#define nAFVALID 0x0
2540#define AFEXIT 0x10 /* Authentication Firmware Exit */
2541#define nAFEXIT 0x0
2542#define SECSTAT 0xe0 /* Secure Status */
2543
2544/* Bit masks for PLL_DIV */
2545
2546#define CSEL 0x30 /* Core Select */
2547#define SSEL 0xf /* System Select */
2548
2549/* Bit masks for PLL_CTL */
2550
2551#define MSEL 0x7e00 /* Multiplier Select */
2552#define BYPASS 0x100 /* PLL Bypass Enable */
2553#define nBYPASS 0x0
2554#define OUTPUT_DELAY 0x80 /* External Memory Output Delay Enable */
2555#define nOUTPUT_DELAY 0x0
2556#define INPUT_DELAY 0x40 /* External Memory Input Delay Enable */
2557#define nINPUT_DELAY 0x0
2558#define PDWN 0x20 /* Power Down */
2559#define nPDWN 0x0
2560#define STOPCK 0x8 /* Stop Clock */
2561#define nSTOPCK 0x0
2562#define PLL_OFF 0x2 /* Disable PLL */
2563#define nPLL_OFF 0x0
2564#define DF 0x1 /* Divide Frequency */
2565#define nDF 0x0
2566
2567/* Bit masks for PLL_STAT */
2568
2569#define PLL_LOCKED 0x20 /* PLL Locked Status */
2570#define nPLL_LOCKED 0x0
2571#define ACTIVE_PLLDISABLED 0x4 /* Active Mode With PLL Disabled */
2572#define nACTIVE_PLLDISABLED 0x0
2573#define FULL_ON 0x2 /* Full-On Mode */
2574#define nFULL_ON 0x0
2575#define ACTIVE_PLLENABLED 0x1 /* Active Mode With PLL Enabled */
2576#define nACTIVE_PLLENABLED 0x0
2577#define RTCWS 0x400 /* RTC/Reset Wake-Up Status */
2578#define nRTCWS 0x0
2579#define CANWS 0x800 /* CAN Wake-Up Status */
2580#define nCANWS 0x0
2581#define USBWS 0x2000 /* USB Wake-Up Status */
2582#define nUSBWS 0x0
2583#define KPADWS 0x4000 /* Keypad Wake-Up Status */
2584#define nKPADWS 0x0
2585#define ROTWS 0x8000 /* Rotary Wake-Up Status */
2586#define nROTWS 0x0
2587#define GPWS 0x1000 /* General-Purpose Wake-Up Status */
2588#define nGPWS 0x0
2589
2590/* Bit masks for VR_CTL */
2591
2592#define FREQ 0x3 /* Regulator Switching Frequency */
2593#define GAIN 0xc /* Voltage Output Level Gain */
2594#define VLEV 0xf0 /* Internal Voltage Level */
2595#define SCKELOW 0x8000 /* Drive SCKE Low During Reset Enable */
2596#define nSCKELOW 0x0
2597#define WAKE 0x100 /* RTC/Reset Wake-Up Enable */
2598#define nWAKE 0x0
2599#define CANWE 0x200 /* CAN0/1 Wake-Up Enable */
2600#define nCANWE 0x0
2601#define GPWE 0x400 /* General-Purpose Wake-Up Enable */
2602#define nGPWE 0x0
2603#define USBWE 0x800 /* USB Wake-Up Enable */
2604#define nUSBWE 0x0
2605#define KPADWE 0x1000 /* Keypad Wake-Up Enable */
2606#define nKPADWE 0x0
2607#define ROTWE 0x2000 /* Rotary Wake-Up Enable */
2608#define nROTWE 0x0
2609
2610/* Bit masks for NFC_CTL */
2611
2612#define WR_DLY 0xf /* Write Strobe Delay */
2613#define RD_DLY 0xf0 /* Read Strobe Delay */
2614#define NWIDTH 0x100 /* NAND Data Width */
2615#define nNWIDTH 0x0
2616#define PG_SIZE 0x200 /* Page Size */
2617#define nPG_SIZE 0x0
2618
2619/* Bit masks for NFC_STAT */
2620
2621#define NBUSY 0x1 /* Not Busy */
2622#define nNBUSY 0x0
2623#define WB_FULL 0x2 /* Write Buffer Full */
2624#define nWB_FULL 0x0
2625#define PG_WR_STAT 0x4 /* Page Write Pending */
2626#define nPG_WR_STAT 0x0
2627#define PG_RD_STAT 0x8 /* Page Read Pending */
2628#define nPG_RD_STAT 0x0
2629#define WB_EMPTY 0x10 /* Write Buffer Empty */
2630#define nWB_EMPTY 0x0
2631
2632/* Bit masks for NFC_IRQSTAT */
2633
2634#define NBUSYIRQ 0x1 /* Not Busy IRQ */
2635#define nNBUSYIRQ 0x0
2636#define WB_OVF 0x2 /* Write Buffer Overflow */
2637#define nWB_OVF 0x0
2638#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
2639#define nWB_EDGE 0x0
2640#define RD_RDY 0x8 /* Read Data Ready */
2641#define nRD_RDY 0x0
2642#define WR_DONE 0x10 /* Page Write Done */
2643#define nWR_DONE 0x0
2644
2645/* Bit masks for NFC_IRQMASK */
2646
2647#define MASK_BUSYIRQ 0x1 /* Mask Not Busy IRQ */
2648#define nMASK_BUSYIRQ 0x0
2649#define MASK_WBOVF 0x2 /* Mask Write Buffer Overflow */
2650#define nMASK_WBOVF 0x0
2651#define MASK_WBEMPTY 0x4 /* Mask Write Buffer Empty */
2652#define nMASK_WBEMPTY 0x0
2653#define MASK_RDRDY 0x8 /* Mask Read Data Ready */
2654#define nMASK_RDRDY 0x0
2655#define MASK_WRDONE 0x10 /* Mask Write Done */
2656#define nMASK_WRDONE 0x0
2657
2658/* Bit masks for NFC_RST */
2659
2660#define ECC_RST 0x1 /* ECC (and NFC counters) Reset */
2661#define nECC_RST 0x0
2662
2663/* Bit masks for NFC_PGCTL */
2664
2665#define PG_RD_START 0x1 /* Page Read Start */
2666#define nPG_RD_START 0x0
2667#define PG_WR_START 0x2 /* Page Write Start */
2668#define nPG_WR_START 0x0
2669
2670/* Bit masks for NFC_ECC0 */
2671
2672#define ECC0 0x7ff /* Parity Calculation Result0 */
2673
2674/* Bit masks for NFC_ECC1 */
2675
2676#define ECC1 0x7ff /* Parity Calculation Result1 */
2677
2678/* Bit masks for NFC_ECC2 */
2679
2680#define ECC2 0x7ff /* Parity Calculation Result2 */
2681
2682/* Bit masks for NFC_ECC3 */
2683
2684#define ECC3 0x7ff /* Parity Calculation Result3 */
2685
2686/* Bit masks for NFC_COUNT */
2687
2688#define ECCCNT 0x3ff /* Transfer Count */
2689
2690/* Bit masks for CAN0_CONTROL */
2691
2692#define SRS 0x1 /* Software Reset */
2693#define nSRS 0x0
2694#define DNM 0x2 /* DeviceNet Mode */
2695#define nDNM 0x0
2696#define ABO 0x4 /* Auto Bus On */
2697#define nABO 0x0
2698#define WBA 0x10 /* Wakeup On CAN Bus Activity */
2699#define nWBA 0x0
2700#define SMR 0x20 /* Sleep Mode Request */
2701#define nSMR 0x0
2702#define CSR 0x40 /* CAN Suspend Mode Request */
2703#define nCSR 0x0
2704#define CCR 0x80 /* CAN Configuration Mode Request */
2705#define nCCR 0x0
2706
2707/* Bit masks for CAN0_STATUS */
2708
2709#define WT 0x1 /* CAN Transmit Warning Flag */
2710#define nWT 0x0
2711#define WR 0x2 /* CAN Receive Warning Flag */
2712#define nWR 0x0
2713#define EP 0x4 /* CAN Error Passive Mode */
2714#define nEP 0x0
2715#define EBO 0x8 /* CAN Error Bus Off Mode */
2716#define nEBO 0x0
2717#define CSA 0x40 /* CAN Suspend Mode Acknowledge */
2718#define nCSA 0x0
2719#define CCA 0x80 /* CAN Configuration Mode Acknowledge */
2720#define nCCA 0x0
2721#define MBPTR 0x1f00 /* Mailbox Pointer */
2722#define TRM 0x4000 /* Transmit Mode Status */
2723#define nTRM 0x0
2724#define REC 0x8000 /* Receive Mode Status */
2725#define nREC 0x0
2726
2727/* Bit masks for CAN0_DEBUG */
2728
2729#define DEC 0x1 /* Disable Transmit/Receive Error Counters */
2730#define nDEC 0x0
2731#define DRI 0x2 /* Disable CANRX Input Pin */
2732#define nDRI 0x0
2733#define DTO 0x4 /* Disable CANTX Output Pin */
2734#define nDTO 0x0
2735#define DIL 0x8 /* Disable Internal Loop */
2736#define nDIL 0x0
2737#define MAA 0x10 /* Mode Auto-Acknowledge */
2738#define nMAA 0x0
2739#define MRB 0x20 /* Mode Read Back */
2740#define nMRB 0x0
2741#define CDE 0x8000 /* CAN Debug Mode Enable */
2742#define nCDE 0x0
2743
2744/* Bit masks for CAN0_CLOCK */
2745
2746#define BRP 0x3ff /* CAN Bit Rate Prescaler */
2747
2748/* Bit masks for CAN0_TIMING */
2749
2750#define SJW 0x300 /* Synchronization Jump Width */
2751#define SAM 0x80 /* Sampling */
2752#define nSAM 0x0
2753#define TSEG2 0x70 /* Time Segment 2 */
2754#define TSEG1 0xf /* Time Segment 1 */
2755
2756/* Bit masks for CAN0_INTR */
2757
2758#define CANRX 0x80 /* Serial Input From Transceiver */
2759#define nCANRX 0x0
2760#define CANTX 0x40 /* Serial Output To Transceiver */
2761#define nCANTX 0x0
2762#define SMACK 0x8 /* Sleep Mode Acknowledge */
2763#define nSMACK 0x0
2764#define GIRQ 0x4 /* Global Interrupt Request Status */
2765#define nGIRQ 0x0
2766#define MBTIRQ 0x2 /* Mailbox Transmit Interrupt Request */
2767#define nMBTIRQ 0x0
2768#define MBRIRQ 0x1 /* Mailbox Receive Interrupt Request */
2769#define nMBRIRQ 0x0
2770
2771/* Bit masks for CAN0_GIM */
2772
2773#define EWTIM 0x1 /* Error Warning Transmit Interrupt Mask */
2774#define nEWTIM 0x0
2775#define EWRIM 0x2 /* Error Warning Receive Interrupt Mask */
2776#define nEWRIM 0x0
2777#define EPIM 0x4 /* Error Passive Interrupt Mask */
2778#define nEPIM 0x0
2779#define BOIM 0x8 /* Bus Off Interrupt Mask */
2780#define nBOIM 0x0
2781#define WUIM 0x10 /* Wakeup Interrupt Mask */
2782#define nWUIM 0x0
2783#define UIAIM 0x20 /* Unimplemented Address Interrupt Mask */
2784#define nUIAIM 0x0
2785#define AAIM 0x40 /* Abort Acknowledge Interrupt Mask */
2786#define nAAIM 0x0
2787#define RMLIM 0x80 /* Receive Message Lost Interrupt Mask */
2788#define nRMLIM 0x0
2789#define UCEIM 0x100 /* Universal Counter Exceeded Interrupt Mask */
2790#define nUCEIM 0x0
2791#define ADIM 0x400 /* Access Denied Interrupt Mask */
2792#define nADIM 0x0
2793
2794/* Bit masks for CAN0_GIS */
2795
2796#define EWTIS 0x1 /* Error Warning Transmit Interrupt Status */
2797#define nEWTIS 0x0
2798#define EWRIS 0x2 /* Error Warning Receive Interrupt Status */
2799#define nEWRIS 0x0
2800#define EPIS 0x4 /* Error Passive Interrupt Status */
2801#define nEPIS 0x0
2802#define BOIS 0x8 /* Bus Off Interrupt Status */
2803#define nBOIS 0x0
2804#define WUIS 0x10 /* Wakeup Interrupt Status */
2805#define nWUIS 0x0
2806#define UIAIS 0x20 /* Unimplemented Address Interrupt Status */
2807#define nUIAIS 0x0
2808#define AAIS 0x40 /* Abort Acknowledge Interrupt Status */
2809#define nAAIS 0x0
2810#define RMLIS 0x80 /* Receive Message Lost Interrupt Status */
2811#define nRMLIS 0x0
2812#define UCEIS 0x100 /* Universal Counter Exceeded Interrupt Status */
2813#define nUCEIS 0x0
2814#define ADIS 0x400 /* Access Denied Interrupt Status */
2815#define nADIS 0x0
2816
2817/* Bit masks for CAN0_GIF */
2818
2819#define EWTIF 0x1 /* Error Warning Transmit Interrupt Flag */
2820#define nEWTIF 0x0
2821#define EWRIF 0x2 /* Error Warning Receive Interrupt Flag */
2822#define nEWRIF 0x0
2823#define EPIF 0x4 /* Error Passive Interrupt Flag */
2824#define nEPIF 0x0
2825#define BOIF 0x8 /* Bus Off Interrupt Flag */
2826#define nBOIF 0x0
2827#define WUIF 0x10 /* Wakeup Interrupt Flag */
2828#define nWUIF 0x0
2829#define UIAIF 0x20 /* Unimplemented Address Interrupt Flag */
2830#define nUIAIF 0x0
2831#define AAIF 0x40 /* Abort Acknowledge Interrupt Flag */
2832#define nAAIF 0x0
2833#define RMLIF 0x80 /* Receive Message Lost Interrupt Flag */
2834#define nRMLIF 0x0
2835#define UCEIF 0x100 /* Universal Counter Exceeded Interrupt Flag */
2836#define nUCEIF 0x0
2837#define ADIF 0x400 /* Access Denied Interrupt Flag */
2838#define nADIF 0x0
2839
2840/* Bit masks for CAN0_MBTD */
2841
2842#define TDR 0x80 /* Temporary Disable Request */
2843#define nTDR 0x0
2844#define TDA 0x40 /* Temporary Disable Acknowledge */
2845#define nTDA 0x0
2846#define TDPTR 0x1f /* Temporary Disable Pointer */
2847
2848/* Bit masks for CAN0_UCCNF */
2849
2850#define UCCNF 0xf /* Universal Counter Configuration */
2851#define UCRC 0x20 /* Universal Counter Reload/Clear */
2852#define nUCRC 0x0
2853#define UCCT 0x40 /* Universal Counter CAN Trigger */
2854#define nUCCT 0x0
2855#define UCE 0x80 /* Universal Counter Enable */
2856#define nUCE 0x0
2857
2858/* Bit masks for CAN0_UCCNT */
2859
2860#define UCCNT 0xffff /* Universal Counter Count Value */
2861
2862/* Bit masks for CAN0_UCRC */
2863
2864#define UCVAL 0xffff /* Universal Counter Reload/Capture Value */
2865
2866/* Bit masks for CAN0_CEC */
2867
2868#define RXECNT 0xff /* Receive Error Counter */
2869#define TXECNT 0xff00 /* Transmit Error Counter */
2870
2871/* Bit masks for CAN0_ESR */
2872
2873#define FER 0x80 /* Form Error */
2874#define nFER 0x0
2875#define BEF 0x40 /* Bit Error Flag */
2876#define nBEF 0x0
2877#define SA0 0x20 /* Stuck At Dominant */
2878#define nSA0 0x0
2879#define CRCE 0x10 /* CRC Error */
2880#define nCRCE 0x0
2881#define SER 0x8 /* Stuff Bit Error */
2882#define nSER 0x0
2883#define ACKE 0x4 /* Acknowledge Error */
2884#define nACKE 0x0
2885
2886/* Bit masks for CAN0_EWR */
2887
2888#define EWLTEC 0xff00 /* Transmit Error Warning Limit */
2889#define EWLREC 0xff /* Receive Error Warning Limit */
2890
2891/* Bit masks for CAN0_AMxx_H */
2892
2893#define FDF 0x8000 /* Filter On Data Field */
2894#define nFDF 0x0
2895#define FMD 0x4000 /* Full Mask Data */
2896#define nFMD 0x0
2897#define AMIDE 0x2000 /* Acceptance Mask Identifier Extension */
2898#define nAMIDE 0x0
2899#define BASEID 0x1ffc /* Base Identifier */
2900#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2901
2902/* Bit masks for CAN0_AMxx_L */
2903
2904#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2905#define DFM 0xffff /* Data Field Mask */
2906
2907/* Bit masks for CAN0_MBxx_ID1 */
2908
2909#define AME 0x8000 /* Acceptance Mask Enable */
2910#define nAME 0x0
2911#define RTR 0x4000 /* Remote Transmission Request */
2912#define nRTR 0x0
2913#define IDE 0x2000 /* Identifier Extension */
2914#define nIDE 0x0
2915#define BASEID 0x1ffc /* Base Identifier */
2916#define EXTID_HI 0x3 /* Extended Identifier High Bits */
2917
2918/* Bit masks for CAN0_MBxx_ID0 */
2919
2920#define EXTID_LO 0xffff /* Extended Identifier Low Bits */
2921#define DFM 0xffff /* Data Field Mask */
2922
2923/* Bit masks for CAN0_MBxx_TIMESTAMP */
2924
2925#define TSV 0xffff /* Time Stamp Value */
2926
2927/* Bit masks for CAN0_MBxx_LENGTH */
2928
2929#define DLC 0xf /* Data Length Code */
2930
2931/* Bit masks for CAN0_MBxx_DATA3 */
2932
2933#define CAN_BYTE0 0xff00 /* Data Field Byte 0 */
2934#define CAN_BYTE1 0xff /* Data Field Byte 1 */
2935
2936/* Bit masks for CAN0_MBxx_DATA2 */
2937
2938#define CAN_BYTE2 0xff00 /* Data Field Byte 2 */
2939#define CAN_BYTE3 0xff /* Data Field Byte 3 */
2940
2941/* Bit masks for CAN0_MBxx_DATA1 */
2942
2943#define CAN_BYTE4 0xff00 /* Data Field Byte 4 */
2944#define CAN_BYTE5 0xff /* Data Field Byte 5 */
2945
2946/* Bit masks for CAN0_MBxx_DATA0 */
2947
2948#define CAN_BYTE6 0xff00 /* Data Field Byte 6 */
2949#define CAN_BYTE7 0xff /* Data Field Byte 7 */
2950
2951/* Bit masks for CAN0_MC1 */
2952
2953#define MC0 0x1 /* Mailbox 0 Enable */
2954#define nMC0 0x0
2955#define MC1 0x2 /* Mailbox 1 Enable */
2956#define nMC1 0x0
2957#define MC2 0x4 /* Mailbox 2 Enable */
2958#define nMC2 0x0
2959#define MC3 0x8 /* Mailbox 3 Enable */
2960#define nMC3 0x0
2961#define MC4 0x10 /* Mailbox 4 Enable */
2962#define nMC4 0x0
2963#define MC5 0x20 /* Mailbox 5 Enable */
2964#define nMC5 0x0
2965#define MC6 0x40 /* Mailbox 6 Enable */
2966#define nMC6 0x0
2967#define MC7 0x80 /* Mailbox 7 Enable */
2968#define nMC7 0x0
2969#define MC8 0x100 /* Mailbox 8 Enable */
2970#define nMC8 0x0
2971#define MC9 0x200 /* Mailbox 9 Enable */
2972#define nMC9 0x0
2973#define MC10 0x400 /* Mailbox 10 Enable */
2974#define nMC10 0x0
2975#define MC11 0x800 /* Mailbox 11 Enable */
2976#define nMC11 0x0
2977#define MC12 0x1000 /* Mailbox 12 Enable */
2978#define nMC12 0x0
2979#define MC13 0x2000 /* Mailbox 13 Enable */
2980#define nMC13 0x0
2981#define MC14 0x4000 /* Mailbox 14 Enable */
2982#define nMC14 0x0
2983#define MC15 0x8000 /* Mailbox 15 Enable */
2984#define nMC15 0x0
2985
2986/* Bit masks for CAN0_MC2 */
2987
2988#define MC16 0x1 /* Mailbox 16 Enable */
2989#define nMC16 0x0
2990#define MC17 0x2 /* Mailbox 17 Enable */
2991#define nMC17 0x0
2992#define MC18 0x4 /* Mailbox 18 Enable */
2993#define nMC18 0x0
2994#define MC19 0x8 /* Mailbox 19 Enable */
2995#define nMC19 0x0
2996#define MC20 0x10 /* Mailbox 20 Enable */
2997#define nMC20 0x0
2998#define MC21 0x20 /* Mailbox 21 Enable */
2999#define nMC21 0x0
3000#define MC22 0x40 /* Mailbox 22 Enable */
3001#define nMC22 0x0
3002#define MC23 0x80 /* Mailbox 23 Enable */
3003#define nMC23 0x0
3004#define MC24 0x100 /* Mailbox 24 Enable */
3005#define nMC24 0x0
3006#define MC25 0x200 /* Mailbox 25 Enable */
3007#define nMC25 0x0
3008#define MC26 0x400 /* Mailbox 26 Enable */
3009#define nMC26 0x0
3010#define MC27 0x800 /* Mailbox 27 Enable */
3011#define nMC27 0x0
3012#define MC28 0x1000 /* Mailbox 28 Enable */
3013#define nMC28 0x0
3014#define MC29 0x2000 /* Mailbox 29 Enable */
3015#define nMC29 0x0
3016#define MC30 0x4000 /* Mailbox 30 Enable */
3017#define nMC30 0x0
3018#define MC31 0x8000 /* Mailbox 31 Enable */
3019#define nMC31 0x0
3020
3021/* Bit masks for CAN0_MD1 */
3022
3023#define MD0 0x1 /* Mailbox 0 Receive Enable */
3024#define nMD0 0x0
3025#define MD1 0x2 /* Mailbox 1 Receive Enable */
3026#define nMD1 0x0
3027#define MD2 0x4 /* Mailbox 2 Receive Enable */
3028#define nMD2 0x0
3029#define MD3 0x8 /* Mailbox 3 Receive Enable */
3030#define nMD3 0x0
3031#define MD4 0x10 /* Mailbox 4 Receive Enable */
3032#define nMD4 0x0
3033#define MD5 0x20 /* Mailbox 5 Receive Enable */
3034#define nMD5 0x0
3035#define MD6 0x40 /* Mailbox 6 Receive Enable */
3036#define nMD6 0x0
3037#define MD7 0x80 /* Mailbox 7 Receive Enable */
3038#define nMD7 0x0
3039#define MD8 0x100 /* Mailbox 8 Receive Enable */
3040#define nMD8 0x0
3041#define MD9 0x200 /* Mailbox 9 Receive Enable */
3042#define nMD9 0x0
3043#define MD10 0x400 /* Mailbox 10 Receive Enable */
3044#define nMD10 0x0
3045#define MD11 0x800 /* Mailbox 11 Receive Enable */
3046#define nMD11 0x0
3047#define MD12 0x1000 /* Mailbox 12 Receive Enable */
3048#define nMD12 0x0
3049#define MD13 0x2000 /* Mailbox 13 Receive Enable */
3050#define nMD13 0x0
3051#define MD14 0x4000 /* Mailbox 14 Receive Enable */
3052#define nMD14 0x0
3053#define MD15 0x8000 /* Mailbox 15 Receive Enable */
3054#define nMD15 0x0
3055
3056/* Bit masks for CAN0_MD2 */
3057
3058#define MD16 0x1 /* Mailbox 16 Receive Enable */
3059#define nMD16 0x0
3060#define MD17 0x2 /* Mailbox 17 Receive Enable */
3061#define nMD17 0x0
3062#define MD18 0x4 /* Mailbox 18 Receive Enable */
3063#define nMD18 0x0
3064#define MD19 0x8 /* Mailbox 19 Receive Enable */
3065#define nMD19 0x0
3066#define MD20 0x10 /* Mailbox 20 Receive Enable */
3067#define nMD20 0x0
3068#define MD21 0x20 /* Mailbox 21 Receive Enable */
3069#define nMD21 0x0
3070#define MD22 0x40 /* Mailbox 22 Receive Enable */
3071#define nMD22 0x0
3072#define MD23 0x80 /* Mailbox 23 Receive Enable */
3073#define nMD23 0x0
3074#define MD24 0x100 /* Mailbox 24 Receive Enable */
3075#define nMD24 0x0
3076#define MD25 0x200 /* Mailbox 25 Receive Enable */
3077#define nMD25 0x0
3078#define MD26 0x400 /* Mailbox 26 Receive Enable */
3079#define nMD26 0x0
3080#define MD27 0x800 /* Mailbox 27 Receive Enable */
3081#define nMD27 0x0
3082#define MD28 0x1000 /* Mailbox 28 Receive Enable */
3083#define nMD28 0x0
3084#define MD29 0x2000 /* Mailbox 29 Receive Enable */
3085#define nMD29 0x0
3086#define MD30 0x4000 /* Mailbox 30 Receive Enable */
3087#define nMD30 0x0
3088#define MD31 0x8000 /* Mailbox 31 Receive Enable */
3089#define nMD31 0x0
3090
3091/* Bit masks for CAN0_RMP1 */
3092
3093#define RMP0 0x1 /* Mailbox 0 Receive Message Pending */
3094#define nRMP0 0x0
3095#define RMP1 0x2 /* Mailbox 1 Receive Message Pending */
3096#define nRMP1 0x0
3097#define RMP2 0x4 /* Mailbox 2 Receive Message Pending */
3098#define nRMP2 0x0
3099#define RMP3 0x8 /* Mailbox 3 Receive Message Pending */
3100#define nRMP3 0x0
3101#define RMP4 0x10 /* Mailbox 4 Receive Message Pending */
3102#define nRMP4 0x0
3103#define RMP5 0x20 /* Mailbox 5 Receive Message Pending */
3104#define nRMP5 0x0
3105#define RMP6 0x40 /* Mailbox 6 Receive Message Pending */
3106#define nRMP6 0x0
3107#define RMP7 0x80 /* Mailbox 7 Receive Message Pending */
3108#define nRMP7 0x0
3109#define RMP8 0x100 /* Mailbox 8 Receive Message Pending */
3110#define nRMP8 0x0
3111#define RMP9 0x200 /* Mailbox 9 Receive Message Pending */
3112#define nRMP9 0x0
3113#define RMP10 0x400 /* Mailbox 10 Receive Message Pending */
3114#define nRMP10 0x0
3115#define RMP11 0x800 /* Mailbox 11 Receive Message Pending */
3116#define nRMP11 0x0
3117#define RMP12 0x1000 /* Mailbox 12 Receive Message Pending */
3118#define nRMP12 0x0
3119#define RMP13 0x2000 /* Mailbox 13 Receive Message Pending */
3120#define nRMP13 0x0
3121#define RMP14 0x4000 /* Mailbox 14 Receive Message Pending */
3122#define nRMP14 0x0
3123#define RMP15 0x8000 /* Mailbox 15 Receive Message Pending */
3124#define nRMP15 0x0
3125
3126/* Bit masks for CAN0_RMP2 */
3127
3128#define RMP16 0x1 /* Mailbox 16 Receive Message Pending */
3129#define nRMP16 0x0
3130#define RMP17 0x2 /* Mailbox 17 Receive Message Pending */
3131#define nRMP17 0x0
3132#define RMP18 0x4 /* Mailbox 18 Receive Message Pending */
3133#define nRMP18 0x0
3134#define RMP19 0x8 /* Mailbox 19 Receive Message Pending */
3135#define nRMP19 0x0
3136#define RMP20 0x10 /* Mailbox 20 Receive Message Pending */
3137#define nRMP20 0x0
3138#define RMP21 0x20 /* Mailbox 21 Receive Message Pending */
3139#define nRMP21 0x0
3140#define RMP22 0x40 /* Mailbox 22 Receive Message Pending */
3141#define nRMP22 0x0
3142#define RMP23 0x80 /* Mailbox 23 Receive Message Pending */
3143#define nRMP23 0x0
3144#define RMP24 0x100 /* Mailbox 24 Receive Message Pending */
3145#define nRMP24 0x0
3146#define RMP25 0x200 /* Mailbox 25 Receive Message Pending */
3147#define nRMP25 0x0
3148#define RMP26 0x400 /* Mailbox 26 Receive Message Pending */
3149#define nRMP26 0x0
3150#define RMP27 0x800 /* Mailbox 27 Receive Message Pending */
3151#define nRMP27 0x0
3152#define RMP28 0x1000 /* Mailbox 28 Receive Message Pending */
3153#define nRMP28 0x0
3154#define RMP29 0x2000 /* Mailbox 29 Receive Message Pending */
3155#define nRMP29 0x0
3156#define RMP30 0x4000 /* Mailbox 30 Receive Message Pending */
3157#define nRMP30 0x0
3158#define RMP31 0x8000 /* Mailbox 31 Receive Message Pending */
3159#define nRMP31 0x0
3160
3161/* Bit masks for CAN0_RML1 */
3162
3163#define RML0 0x1 /* Mailbox 0 Receive Message Lost */
3164#define nRML0 0x0
3165#define RML1 0x2 /* Mailbox 1 Receive Message Lost */
3166#define nRML1 0x0
3167#define RML2 0x4 /* Mailbox 2 Receive Message Lost */
3168#define nRML2 0x0
3169#define RML3 0x8 /* Mailbox 3 Receive Message Lost */
3170#define nRML3 0x0
3171#define RML4 0x10 /* Mailbox 4 Receive Message Lost */
3172#define nRML4 0x0
3173#define RML5 0x20 /* Mailbox 5 Receive Message Lost */
3174#define nRML5 0x0
3175#define RML6 0x40 /* Mailbox 6 Receive Message Lost */
3176#define nRML6 0x0
3177#define RML7 0x80 /* Mailbox 7 Receive Message Lost */
3178#define nRML7 0x0
3179#define RML8 0x100 /* Mailbox 8 Receive Message Lost */
3180#define nRML8 0x0
3181#define RML9 0x200 /* Mailbox 9 Receive Message Lost */
3182#define nRML9 0x0
3183#define RML10 0x400 /* Mailbox 10 Receive Message Lost */
3184#define nRML10 0x0
3185#define RML11 0x800 /* Mailbox 11 Receive Message Lost */
3186#define nRML11 0x0
3187#define RML12 0x1000 /* Mailbox 12 Receive Message Lost */
3188#define nRML12 0x0
3189#define RML13 0x2000 /* Mailbox 13 Receive Message Lost */
3190#define nRML13 0x0
3191#define RML14 0x4000 /* Mailbox 14 Receive Message Lost */
3192#define nRML14 0x0
3193#define RML15 0x8000 /* Mailbox 15 Receive Message Lost */
3194#define nRML15 0x0
3195
3196/* Bit masks for CAN0_RML2 */
3197
3198#define RML16 0x1 /* Mailbox 16 Receive Message Lost */
3199#define nRML16 0x0
3200#define RML17 0x2 /* Mailbox 17 Receive Message Lost */
3201#define nRML17 0x0
3202#define RML18 0x4 /* Mailbox 18 Receive Message Lost */
3203#define nRML18 0x0
3204#define RML19 0x8 /* Mailbox 19 Receive Message Lost */
3205#define nRML19 0x0
3206#define RML20 0x10 /* Mailbox 20 Receive Message Lost */
3207#define nRML20 0x0
3208#define RML21 0x20 /* Mailbox 21 Receive Message Lost */
3209#define nRML21 0x0
3210#define RML22 0x40 /* Mailbox 22 Receive Message Lost */
3211#define nRML22 0x0
3212#define RML23 0x80 /* Mailbox 23 Receive Message Lost */
3213#define nRML23 0x0
3214#define RML24 0x100 /* Mailbox 24 Receive Message Lost */
3215#define nRML24 0x0
3216#define RML25 0x200 /* Mailbox 25 Receive Message Lost */
3217#define nRML25 0x0
3218#define RML26 0x400 /* Mailbox 26 Receive Message Lost */
3219#define nRML26 0x0
3220#define RML27 0x800 /* Mailbox 27 Receive Message Lost */
3221#define nRML27 0x0
3222#define RML28 0x1000 /* Mailbox 28 Receive Message Lost */
3223#define nRML28 0x0
3224#define RML29 0x2000 /* Mailbox 29 Receive Message Lost */
3225#define nRML29 0x0
3226#define RML30 0x4000 /* Mailbox 30 Receive Message Lost */
3227#define nRML30 0x0
3228#define RML31 0x8000 /* Mailbox 31 Receive Message Lost */
3229#define nRML31 0x0
3230
3231/* Bit masks for CAN0_OPSS1 */
3232
3233#define OPSS0 0x1 /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
3234#define nOPSS0 0x0
3235#define OPSS1 0x2 /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
3236#define nOPSS1 0x0
3237#define OPSS2 0x4 /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
3238#define nOPSS2 0x0
3239#define OPSS3 0x8 /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
3240#define nOPSS3 0x0
3241#define OPSS4 0x10 /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
3242#define nOPSS4 0x0
3243#define OPSS5 0x20 /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
3244#define nOPSS5 0x0
3245#define OPSS6 0x40 /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
3246#define nOPSS6 0x0
3247#define OPSS7 0x80 /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
3248#define nOPSS7 0x0
3249#define OPSS8 0x100 /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
3250#define nOPSS8 0x0
3251#define OPSS9 0x200 /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
3252#define nOPSS9 0x0
3253#define OPSS10 0x400 /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
3254#define nOPSS10 0x0
3255#define OPSS11 0x800 /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
3256#define nOPSS11 0x0
3257#define OPSS12 0x1000 /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
3258#define nOPSS12 0x0
3259#define OPSS13 0x2000 /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
3260#define nOPSS13 0x0
3261#define OPSS14 0x4000 /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
3262#define nOPSS14 0x0
3263#define OPSS15 0x8000 /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
3264#define nOPSS15 0x0
3265
3266/* Bit masks for CAN0_OPSS2 */
3267
3268#define OPSS16 0x1 /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
3269#define nOPSS16 0x0
3270#define OPSS17 0x2 /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
3271#define nOPSS17 0x0
3272#define OPSS18 0x4 /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
3273#define nOPSS18 0x0
3274#define OPSS19 0x8 /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
3275#define nOPSS19 0x0
3276#define OPSS20 0x10 /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
3277#define nOPSS20 0x0
3278#define OPSS21 0x20 /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
3279#define nOPSS21 0x0
3280#define OPSS22 0x40 /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
3281#define nOPSS22 0x0
3282#define OPSS23 0x80 /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
3283#define nOPSS23 0x0
3284#define OPSS24 0x100 /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
3285#define nOPSS24 0x0
3286#define OPSS25 0x200 /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
3287#define nOPSS25 0x0
3288#define OPSS26 0x400 /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
3289#define nOPSS26 0x0
3290#define OPSS27 0x800 /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
3291#define nOPSS27 0x0
3292#define OPSS28 0x1000 /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
3293#define nOPSS28 0x0
3294#define OPSS29 0x2000 /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
3295#define nOPSS29 0x0
3296#define OPSS30 0x4000 /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
3297#define nOPSS30 0x0
3298#define OPSS31 0x8000 /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
3299#define nOPSS31 0x0
3300
3301/* Bit masks for CAN0_TRS1 */
3302
3303#define TRS0 0x1 /* Mailbox 0 Transmit Request Set */
3304#define nTRS0 0x0
3305#define TRS1 0x2 /* Mailbox 1 Transmit Request Set */
3306#define nTRS1 0x0
3307#define TRS2 0x4 /* Mailbox 2 Transmit Request Set */
3308#define nTRS2 0x0
3309#define TRS3 0x8 /* Mailbox 3 Transmit Request Set */
3310#define nTRS3 0x0
3311#define TRS4 0x10 /* Mailbox 4 Transmit Request Set */
3312#define nTRS4 0x0
3313#define TRS5 0x20 /* Mailbox 5 Transmit Request Set */
3314#define nTRS5 0x0
3315#define TRS6 0x40 /* Mailbox 6 Transmit Request Set */
3316#define nTRS6 0x0
3317#define TRS7 0x80 /* Mailbox 7 Transmit Request Set */
3318#define nTRS7 0x0
3319#define TRS8 0x100 /* Mailbox 8 Transmit Request Set */
3320#define nTRS8 0x0
3321#define TRS9 0x200 /* Mailbox 9 Transmit Request Set */
3322#define nTRS9 0x0
3323#define TRS10 0x400 /* Mailbox 10 Transmit Request Set */
3324#define nTRS10 0x0
3325#define TRS11 0x800 /* Mailbox 11 Transmit Request Set */
3326#define nTRS11 0x0
3327#define TRS12 0x1000 /* Mailbox 12 Transmit Request Set */
3328#define nTRS12 0x0
3329#define TRS13 0x2000 /* Mailbox 13 Transmit Request Set */
3330#define nTRS13 0x0
3331#define TRS14 0x4000 /* Mailbox 14 Transmit Request Set */
3332#define nTRS14 0x0
3333#define TRS15 0x8000 /* Mailbox 15 Transmit Request Set */
3334#define nTRS15 0x0
3335
3336/* Bit masks for CAN0_TRS2 */
3337
3338#define TRS16 0x1 /* Mailbox 16 Transmit Request Set */
3339#define nTRS16 0x0
3340#define TRS17 0x2 /* Mailbox 17 Transmit Request Set */
3341#define nTRS17 0x0
3342#define TRS18 0x4 /* Mailbox 18 Transmit Request Set */
3343#define nTRS18 0x0
3344#define TRS19 0x8 /* Mailbox 19 Transmit Request Set */
3345#define nTRS19 0x0
3346#define TRS20 0x10 /* Mailbox 20 Transmit Request Set */
3347#define nTRS20 0x0
3348#define TRS21 0x20 /* Mailbox 21 Transmit Request Set */
3349#define nTRS21 0x0
3350#define TRS22 0x40 /* Mailbox 22 Transmit Request Set */
3351#define nTRS22 0x0
3352#define TRS23 0x80 /* Mailbox 23 Transmit Request Set */
3353#define nTRS23 0x0
3354#define TRS24 0x100 /* Mailbox 24 Transmit Request Set */
3355#define nTRS24 0x0
3356#define TRS25 0x200 /* Mailbox 25 Transmit Request Set */
3357#define nTRS25 0x0
3358#define TRS26 0x400 /* Mailbox 26 Transmit Request Set */
3359#define nTRS26 0x0
3360#define TRS27 0x800 /* Mailbox 27 Transmit Request Set */
3361#define nTRS27 0x0
3362#define TRS28 0x1000 /* Mailbox 28 Transmit Request Set */
3363#define nTRS28 0x0
3364#define TRS29 0x2000 /* Mailbox 29 Transmit Request Set */
3365#define nTRS29 0x0
3366#define TRS30 0x4000 /* Mailbox 30 Transmit Request Set */
3367#define nTRS30 0x0
3368#define TRS31 0x8000 /* Mailbox 31 Transmit Request Set */
3369#define nTRS31 0x0
3370
3371/* Bit masks for CAN0_TRR1 */
3372
3373#define TRR0 0x1 /* Mailbox 0 Transmit Request Reset */
3374#define nTRR0 0x0
3375#define TRR1 0x2 /* Mailbox 1 Transmit Request Reset */
3376#define nTRR1 0x0
3377#define TRR2 0x4 /* Mailbox 2 Transmit Request Reset */
3378#define nTRR2 0x0
3379#define TRR3 0x8 /* Mailbox 3 Transmit Request Reset */
3380#define nTRR3 0x0
3381#define TRR4 0x10 /* Mailbox 4 Transmit Request Reset */
3382#define nTRR4 0x0
3383#define TRR5 0x20 /* Mailbox 5 Transmit Request Reset */
3384#define nTRR5 0x0
3385#define TRR6 0x40 /* Mailbox 6 Transmit Request Reset */
3386#define nTRR6 0x0
3387#define TRR7 0x80 /* Mailbox 7 Transmit Request Reset */
3388#define nTRR7 0x0
3389#define TRR8 0x100 /* Mailbox 8 Transmit Request Reset */
3390#define nTRR8 0x0
3391#define TRR9 0x200 /* Mailbox 9 Transmit Request Reset */
3392#define nTRR9 0x0
3393#define TRR10 0x400 /* Mailbox 10 Transmit Request Reset */
3394#define nTRR10 0x0
3395#define TRR11 0x800 /* Mailbox 11 Transmit Request Reset */
3396#define nTRR11 0x0
3397#define TRR12 0x1000 /* Mailbox 12 Transmit Request Reset */
3398#define nTRR12 0x0
3399#define TRR13 0x2000 /* Mailbox 13 Transmit Request Reset */
3400#define nTRR13 0x0
3401#define TRR14 0x4000 /* Mailbox 14 Transmit Request Reset */
3402#define nTRR14 0x0
3403#define TRR15 0x8000 /* Mailbox 15 Transmit Request Reset */
3404#define nTRR15 0x0
3405
3406/* Bit masks for CAN0_TRR2 */
3407
3408#define TRR16 0x1 /* Mailbox 16 Transmit Request Reset */
3409#define nTRR16 0x0
3410#define TRR17 0x2 /* Mailbox 17 Transmit Request Reset */
3411#define nTRR17 0x0
3412#define TRR18 0x4 /* Mailbox 18 Transmit Request Reset */
3413#define nTRR18 0x0
3414#define TRR19 0x8 /* Mailbox 19 Transmit Request Reset */
3415#define nTRR19 0x0
3416#define TRR20 0x10 /* Mailbox 20 Transmit Request Reset */
3417#define nTRR20 0x0
3418#define TRR21 0x20 /* Mailbox 21 Transmit Request Reset */
3419#define nTRR21 0x0
3420#define TRR22 0x40 /* Mailbox 22 Transmit Request Reset */
3421#define nTRR22 0x0
3422#define TRR23 0x80 /* Mailbox 23 Transmit Request Reset */
3423#define nTRR23 0x0
3424#define TRR24 0x100 /* Mailbox 24 Transmit Request Reset */
3425#define nTRR24 0x0
3426#define TRR25 0x200 /* Mailbox 25 Transmit Request Reset */
3427#define nTRR25 0x0
3428#define TRR26 0x400 /* Mailbox 26 Transmit Request Reset */
3429#define nTRR26 0x0
3430#define TRR27 0x800 /* Mailbox 27 Transmit Request Reset */
3431#define nTRR27 0x0
3432#define TRR28 0x1000 /* Mailbox 28 Transmit Request Reset */
3433#define nTRR28 0x0
3434#define TRR29 0x2000 /* Mailbox 29 Transmit Request Reset */
3435#define nTRR29 0x0
3436#define TRR30 0x4000 /* Mailbox 30 Transmit Request Reset */
3437#define nTRR30 0x0
3438#define TRR31 0x8000 /* Mailbox 31 Transmit Request Reset */
3439#define nTRR31 0x0
3440
3441/* Bit masks for CAN0_AA1 */
3442
3443#define AA0 0x1 /* Mailbox 0 Abort Acknowledge */
3444#define nAA0 0x0
3445#define AA1 0x2 /* Mailbox 1 Abort Acknowledge */
3446#define nAA1 0x0
3447#define AA2 0x4 /* Mailbox 2 Abort Acknowledge */
3448#define nAA2 0x0
3449#define AA3 0x8 /* Mailbox 3 Abort Acknowledge */
3450#define nAA3 0x0
3451#define AA4 0x10 /* Mailbox 4 Abort Acknowledge */
3452#define nAA4 0x0
3453#define AA5 0x20 /* Mailbox 5 Abort Acknowledge */
3454#define nAA5 0x0
3455#define AA6 0x40 /* Mailbox 6 Abort Acknowledge */
3456#define nAA6 0x0
3457#define AA7 0x80 /* Mailbox 7 Abort Acknowledge */
3458#define nAA7 0x0
3459#define AA8 0x100 /* Mailbox 8 Abort Acknowledge */
3460#define nAA8 0x0
3461#define AA9 0x200 /* Mailbox 9 Abort Acknowledge */
3462#define nAA9 0x0
3463#define AA10 0x400 /* Mailbox 10 Abort Acknowledge */
3464#define nAA10 0x0
3465#define AA11 0x800 /* Mailbox 11 Abort Acknowledge */
3466#define nAA11 0x0
3467#define AA12 0x1000 /* Mailbox 12 Abort Acknowledge */
3468#define nAA12 0x0
3469#define AA13 0x2000 /* Mailbox 13 Abort Acknowledge */
3470#define nAA13 0x0
3471#define AA14 0x4000 /* Mailbox 14 Abort Acknowledge */
3472#define nAA14 0x0
3473#define AA15 0x8000 /* Mailbox 15 Abort Acknowledge */
3474#define nAA15 0x0
3475
3476/* Bit masks for CAN0_AA2 */
3477
3478#define AA16 0x1 /* Mailbox 16 Abort Acknowledge */
3479#define nAA16 0x0
3480#define AA17 0x2 /* Mailbox 17 Abort Acknowledge */
3481#define nAA17 0x0
3482#define AA18 0x4 /* Mailbox 18 Abort Acknowledge */
3483#define nAA18 0x0
3484#define AA19 0x8 /* Mailbox 19 Abort Acknowledge */
3485#define nAA19 0x0
3486#define AA20 0x10 /* Mailbox 20 Abort Acknowledge */
3487#define nAA20 0x0
3488#define AA21 0x20 /* Mailbox 21 Abort Acknowledge */
3489#define nAA21 0x0
3490#define AA22 0x40 /* Mailbox 22 Abort Acknowledge */
3491#define nAA22 0x0
3492#define AA23 0x80 /* Mailbox 23 Abort Acknowledge */
3493#define nAA23 0x0
3494#define AA24 0x100 /* Mailbox 24 Abort Acknowledge */
3495#define nAA24 0x0
3496#define AA25 0x200 /* Mailbox 25 Abort Acknowledge */
3497#define nAA25 0x0
3498#define AA26 0x400 /* Mailbox 26 Abort Acknowledge */
3499#define nAA26 0x0
3500#define AA27 0x800 /* Mailbox 27 Abort Acknowledge */
3501#define nAA27 0x0
3502#define AA28 0x1000 /* Mailbox 28 Abort Acknowledge */
3503#define nAA28 0x0
3504#define AA29 0x2000 /* Mailbox 29 Abort Acknowledge */
3505#define nAA29 0x0
3506#define AA30 0x4000 /* Mailbox 30 Abort Acknowledge */
3507#define nAA30 0x0
3508#define AA31 0x8000 /* Mailbox 31 Abort Acknowledge */
3509#define nAA31 0x0
3510
3511/* Bit masks for CAN0_TA1 */
3512
3513#define TA0 0x1 /* Mailbox 0 Transmit Acknowledge */
3514#define nTA0 0x0
3515#define TA1 0x2 /* Mailbox 1 Transmit Acknowledge */
3516#define nTA1 0x0
3517#define TA2 0x4 /* Mailbox 2 Transmit Acknowledge */
3518#define nTA2 0x0
3519#define TA3 0x8 /* Mailbox 3 Transmit Acknowledge */
3520#define nTA3 0x0
3521#define TA4 0x10 /* Mailbox 4 Transmit Acknowledge */
3522#define nTA4 0x0
3523#define TA5 0x20 /* Mailbox 5 Transmit Acknowledge */
3524#define nTA5 0x0
3525#define TA6 0x40 /* Mailbox 6 Transmit Acknowledge */
3526#define nTA6 0x0
3527#define TA7 0x80 /* Mailbox 7 Transmit Acknowledge */
3528#define nTA7 0x0
3529#define TA8 0x100 /* Mailbox 8 Transmit Acknowledge */
3530#define nTA8 0x0
3531#define TA9 0x200 /* Mailbox 9 Transmit Acknowledge */
3532#define nTA9 0x0
3533#define TA10 0x400 /* Mailbox 10 Transmit Acknowledge */
3534#define nTA10 0x0
3535#define TA11 0x800 /* Mailbox 11 Transmit Acknowledge */
3536#define nTA11 0x0
3537#define TA12 0x1000 /* Mailbox 12 Transmit Acknowledge */
3538#define nTA12 0x0
3539#define TA13 0x2000 /* Mailbox 13 Transmit Acknowledge */
3540#define nTA13 0x0
3541#define TA14 0x4000 /* Mailbox 14 Transmit Acknowledge */
3542#define nTA14 0x0
3543#define TA15 0x8000 /* Mailbox 15 Transmit Acknowledge */
3544#define nTA15 0x0
3545
3546/* Bit masks for CAN0_TA2 */
3547
3548#define TA16 0x1 /* Mailbox 16 Transmit Acknowledge */
3549#define nTA16 0x0
3550#define TA17 0x2 /* Mailbox 17 Transmit Acknowledge */
3551#define nTA17 0x0
3552#define TA18 0x4 /* Mailbox 18 Transmit Acknowledge */
3553#define nTA18 0x0
3554#define TA19 0x8 /* Mailbox 19 Transmit Acknowledge */
3555#define nTA19 0x0
3556#define TA20 0x10 /* Mailbox 20 Transmit Acknowledge */
3557#define nTA20 0x0
3558#define TA21 0x20 /* Mailbox 21 Transmit Acknowledge */
3559#define nTA21 0x0
3560#define TA22 0x40 /* Mailbox 22 Transmit Acknowledge */
3561#define nTA22 0x0
3562#define TA23 0x80 /* Mailbox 23 Transmit Acknowledge */
3563#define nTA23 0x0
3564#define TA24 0x100 /* Mailbox 24 Transmit Acknowledge */
3565#define nTA24 0x0
3566#define TA25 0x200 /* Mailbox 25 Transmit Acknowledge */
3567#define nTA25 0x0
3568#define TA26 0x400 /* Mailbox 26 Transmit Acknowledge */
3569#define nTA26 0x0
3570#define TA27 0x800 /* Mailbox 27 Transmit Acknowledge */
3571#define nTA27 0x0
3572#define TA28 0x1000 /* Mailbox 28 Transmit Acknowledge */
3573#define nTA28 0x0
3574#define TA29 0x2000 /* Mailbox 29 Transmit Acknowledge */
3575#define nTA29 0x0
3576#define TA30 0x4000 /* Mailbox 30 Transmit Acknowledge */
3577#define nTA30 0x0
3578#define TA31 0x8000 /* Mailbox 31 Transmit Acknowledge */
3579#define nTA31 0x0
3580
3581/* Bit masks for CAN0_RFH1 */
3582
3583#define RFH0 0x1 /* Mailbox 0 Remote Frame Handling Enable */
3584#define nRFH0 0x0
3585#define RFH1 0x2 /* Mailbox 1 Remote Frame Handling Enable */
3586#define nRFH1 0x0
3587#define RFH2 0x4 /* Mailbox 2 Remote Frame Handling Enable */
3588#define nRFH2 0x0
3589#define RFH3 0x8 /* Mailbox 3 Remote Frame Handling Enable */
3590#define nRFH3 0x0
3591#define RFH4 0x10 /* Mailbox 4 Remote Frame Handling Enable */
3592#define nRFH4 0x0
3593#define RFH5 0x20 /* Mailbox 5 Remote Frame Handling Enable */
3594#define nRFH5 0x0
3595#define RFH6 0x40 /* Mailbox 6 Remote Frame Handling Enable */
3596#define nRFH6 0x0
3597#define RFH7 0x80 /* Mailbox 7 Remote Frame Handling Enable */
3598#define nRFH7 0x0
3599#define RFH8 0x100 /* Mailbox 8 Remote Frame Handling Enable */
3600#define nRFH8 0x0
3601#define RFH9 0x200 /* Mailbox 9 Remote Frame Handling Enable */
3602#define nRFH9 0x0
3603#define RFH10 0x400 /* Mailbox 10 Remote Frame Handling Enable */
3604#define nRFH10 0x0
3605#define RFH11 0x800 /* Mailbox 11 Remote Frame Handling Enable */
3606#define nRFH11 0x0
3607#define RFH12 0x1000 /* Mailbox 12 Remote Frame Handling Enable */
3608#define nRFH12 0x0
3609#define RFH13 0x2000 /* Mailbox 13 Remote Frame Handling Enable */
3610#define nRFH13 0x0
3611#define RFH14 0x4000 /* Mailbox 14 Remote Frame Handling Enable */
3612#define nRFH14 0x0
3613#define RFH15 0x8000 /* Mailbox 15 Remote Frame Handling Enable */
3614#define nRFH15 0x0
3615
3616/* Bit masks for CAN0_RFH2 */
3617
3618#define RFH16 0x1 /* Mailbox 16 Remote Frame Handling Enable */
3619#define nRFH16 0x0
3620#define RFH17 0x2 /* Mailbox 17 Remote Frame Handling Enable */
3621#define nRFH17 0x0
3622#define RFH18 0x4 /* Mailbox 18 Remote Frame Handling Enable */
3623#define nRFH18 0x0
3624#define RFH19 0x8 /* Mailbox 19 Remote Frame Handling Enable */
3625#define nRFH19 0x0
3626#define RFH20 0x10 /* Mailbox 20 Remote Frame Handling Enable */
3627#define nRFH20 0x0
3628#define RFH21 0x20 /* Mailbox 21 Remote Frame Handling Enable */
3629#define nRFH21 0x0
3630#define RFH22 0x40 /* Mailbox 22 Remote Frame Handling Enable */
3631#define nRFH22 0x0
3632#define RFH23 0x80 /* Mailbox 23 Remote Frame Handling Enable */
3633#define nRFH23 0x0
3634#define RFH24 0x100 /* Mailbox 24 Remote Frame Handling Enable */
3635#define nRFH24 0x0
3636#define RFH25 0x200 /* Mailbox 25 Remote Frame Handling Enable */
3637#define nRFH25 0x0
3638#define RFH26 0x400 /* Mailbox 26 Remote Frame Handling Enable */
3639#define nRFH26 0x0
3640#define RFH27 0x800 /* Mailbox 27 Remote Frame Handling Enable */
3641#define nRFH27 0x0
3642#define RFH28 0x1000 /* Mailbox 28 Remote Frame Handling Enable */
3643#define nRFH28 0x0
3644#define RFH29 0x2000 /* Mailbox 29 Remote Frame Handling Enable */
3645#define nRFH29 0x0
3646#define RFH30 0x4000 /* Mailbox 30 Remote Frame Handling Enable */
3647#define nRFH30 0x0
3648#define RFH31 0x8000 /* Mailbox 31 Remote Frame Handling Enable */
3649#define nRFH31 0x0
3650
3651/* Bit masks for CAN0_MBIM1 */
3652
3653#define MBIM0 0x1 /* Mailbox 0 Mailbox Interrupt Mask */
3654#define nMBIM0 0x0
3655#define MBIM1 0x2 /* Mailbox 1 Mailbox Interrupt Mask */
3656#define nMBIM1 0x0
3657#define MBIM2 0x4 /* Mailbox 2 Mailbox Interrupt Mask */
3658#define nMBIM2 0x0
3659#define MBIM3 0x8 /* Mailbox 3 Mailbox Interrupt Mask */
3660#define nMBIM3 0x0
3661#define MBIM4 0x10 /* Mailbox 4 Mailbox Interrupt Mask */
3662#define nMBIM4 0x0
3663#define MBIM5 0x20 /* Mailbox 5 Mailbox Interrupt Mask */
3664#define nMBIM5 0x0
3665#define MBIM6 0x40 /* Mailbox 6 Mailbox Interrupt Mask */
3666#define nMBIM6 0x0
3667#define MBIM7 0x80 /* Mailbox 7 Mailbox Interrupt Mask */
3668#define nMBIM7 0x0
3669#define MBIM8 0x100 /* Mailbox 8 Mailbox Interrupt Mask */
3670#define nMBIM8 0x0
3671#define MBIM9 0x200 /* Mailbox 9 Mailbox Interrupt Mask */
3672#define nMBIM9 0x0
3673#define MBIM10 0x400 /* Mailbox 10 Mailbox Interrupt Mask */
3674#define nMBIM10 0x0
3675#define MBIM11 0x800 /* Mailbox 11 Mailbox Interrupt Mask */
3676#define nMBIM11 0x0
3677#define MBIM12 0x1000 /* Mailbox 12 Mailbox Interrupt Mask */
3678#define nMBIM12 0x0
3679#define MBIM13 0x2000 /* Mailbox 13 Mailbox Interrupt Mask */
3680#define nMBIM13 0x0
3681#define MBIM14 0x4000 /* Mailbox 14 Mailbox Interrupt Mask */
3682#define nMBIM14 0x0
3683#define MBIM15 0x8000 /* Mailbox 15 Mailbox Interrupt Mask */
3684#define nMBIM15 0x0
3685
3686/* Bit masks for CAN0_MBIM2 */
3687
3688#define MBIM16 0x1 /* Mailbox 16 Mailbox Interrupt Mask */
3689#define nMBIM16 0x0
3690#define MBIM17 0x2 /* Mailbox 17 Mailbox Interrupt Mask */
3691#define nMBIM17 0x0
3692#define MBIM18 0x4 /* Mailbox 18 Mailbox Interrupt Mask */
3693#define nMBIM18 0x0
3694#define MBIM19 0x8 /* Mailbox 19 Mailbox Interrupt Mask */
3695#define nMBIM19 0x0
3696#define MBIM20 0x10 /* Mailbox 20 Mailbox Interrupt Mask */
3697#define nMBIM20 0x0
3698#define MBIM21 0x20 /* Mailbox 21 Mailbox Interrupt Mask */
3699#define nMBIM21 0x0
3700#define MBIM22 0x40 /* Mailbox 22 Mailbox Interrupt Mask */
3701#define nMBIM22 0x0
3702#define MBIM23 0x80 /* Mailbox 23 Mailbox Interrupt Mask */
3703#define nMBIM23 0x0
3704#define MBIM24 0x100 /* Mailbox 24 Mailbox Interrupt Mask */
3705#define nMBIM24 0x0
3706#define MBIM25 0x200 /* Mailbox 25 Mailbox Interrupt Mask */
3707#define nMBIM25 0x0
3708#define MBIM26 0x400 /* Mailbox 26 Mailbox Interrupt Mask */
3709#define nMBIM26 0x0
3710#define MBIM27 0x800 /* Mailbox 27 Mailbox Interrupt Mask */
3711#define nMBIM27 0x0
3712#define MBIM28 0x1000 /* Mailbox 28 Mailbox Interrupt Mask */
3713#define nMBIM28 0x0
3714#define MBIM29 0x2000 /* Mailbox 29 Mailbox Interrupt Mask */
3715#define nMBIM29 0x0
3716#define MBIM30 0x4000 /* Mailbox 30 Mailbox Interrupt Mask */
3717#define nMBIM30 0x0
3718#define MBIM31 0x8000 /* Mailbox 31 Mailbox Interrupt Mask */
3719#define nMBIM31 0x0
3720
3721/* Bit masks for CAN0_MBTIF1 */
3722
3723#define MBTIF0 0x1 /* Mailbox 0 Mailbox Transmit Interrupt Flag */
3724#define nMBTIF0 0x0
3725#define MBTIF1 0x2 /* Mailbox 1 Mailbox Transmit Interrupt Flag */
3726#define nMBTIF1 0x0
3727#define MBTIF2 0x4 /* Mailbox 2 Mailbox Transmit Interrupt Flag */
3728#define nMBTIF2 0x0
3729#define MBTIF3 0x8 /* Mailbox 3 Mailbox Transmit Interrupt Flag */
3730#define nMBTIF3 0x0
3731#define MBTIF4 0x10 /* Mailbox 4 Mailbox Transmit Interrupt Flag */
3732#define nMBTIF4 0x0
3733#define MBTIF5 0x20 /* Mailbox 5 Mailbox Transmit Interrupt Flag */
3734#define nMBTIF5 0x0
3735#define MBTIF6 0x40 /* Mailbox 6 Mailbox Transmit Interrupt Flag */
3736#define nMBTIF6 0x0
3737#define MBTIF7 0x80 /* Mailbox 7 Mailbox Transmit Interrupt Flag */
3738#define nMBTIF7 0x0
3739#define MBTIF8 0x100 /* Mailbox 8 Mailbox Transmit Interrupt Flag */
3740#define nMBTIF8 0x0
3741#define MBTIF9 0x200 /* Mailbox 9 Mailbox Transmit Interrupt Flag */
3742#define nMBTIF9 0x0
3743#define MBTIF10 0x400 /* Mailbox 10 Mailbox Transmit Interrupt Flag */
3744#define nMBTIF10 0x0
3745#define MBTIF11 0x800 /* Mailbox 11 Mailbox Transmit Interrupt Flag */
3746#define nMBTIF11 0x0
3747#define MBTIF12 0x1000 /* Mailbox 12 Mailbox Transmit Interrupt Flag */
3748#define nMBTIF12 0x0
3749#define MBTIF13 0x2000 /* Mailbox 13 Mailbox Transmit Interrupt Flag */
3750#define nMBTIF13 0x0
3751#define MBTIF14 0x4000 /* Mailbox 14 Mailbox Transmit Interrupt Flag */
3752#define nMBTIF14 0x0
3753#define MBTIF15 0x8000 /* Mailbox 15 Mailbox Transmit Interrupt Flag */
3754#define nMBTIF15 0x0
3755
3756/* Bit masks for CAN0_MBTIF2 */
3757
3758#define MBTIF16 0x1 /* Mailbox 16 Mailbox Transmit Interrupt Flag */
3759#define nMBTIF16 0x0
3760#define MBTIF17 0x2 /* Mailbox 17 Mailbox Transmit Interrupt Flag */
3761#define nMBTIF17 0x0
3762#define MBTIF18 0x4 /* Mailbox 18 Mailbox Transmit Interrupt Flag */
3763#define nMBTIF18 0x0
3764#define MBTIF19 0x8 /* Mailbox 19 Mailbox Transmit Interrupt Flag */
3765#define nMBTIF19 0x0
3766#define MBTIF20 0x10 /* Mailbox 20 Mailbox Transmit Interrupt Flag */
3767#define nMBTIF20 0x0
3768#define MBTIF21 0x20 /* Mailbox 21 Mailbox Transmit Interrupt Flag */
3769#define nMBTIF21 0x0
3770#define MBTIF22 0x40 /* Mailbox 22 Mailbox Transmit Interrupt Flag */
3771#define nMBTIF22 0x0
3772#define MBTIF23 0x80 /* Mailbox 23 Mailbox Transmit Interrupt Flag */
3773#define nMBTIF23 0x0
3774#define MBTIF24 0x100 /* Mailbox 24 Mailbox Transmit Interrupt Flag */
3775#define nMBTIF24 0x0
3776#define MBTIF25 0x200 /* Mailbox 25 Mailbox Transmit Interrupt Flag */
3777#define nMBTIF25 0x0
3778#define MBTIF26 0x400 /* Mailbox 26 Mailbox Transmit Interrupt Flag */
3779#define nMBTIF26 0x0
3780#define MBTIF27 0x800 /* Mailbox 27 Mailbox Transmit Interrupt Flag */
3781#define nMBTIF27 0x0
3782#define MBTIF28 0x1000 /* Mailbox 28 Mailbox Transmit Interrupt Flag */
3783#define nMBTIF28 0x0
3784#define MBTIF29 0x2000 /* Mailbox 29 Mailbox Transmit Interrupt Flag */
3785#define nMBTIF29 0x0
3786#define MBTIF30 0x4000 /* Mailbox 30 Mailbox Transmit Interrupt Flag */
3787#define nMBTIF30 0x0
3788#define MBTIF31 0x8000 /* Mailbox 31 Mailbox Transmit Interrupt Flag */
3789#define nMBTIF31 0x0
3790
3791/* Bit masks for CAN0_MBRIF1 */
3792
3793#define MBRIF0 0x1 /* Mailbox 0 Mailbox Receive Interrupt Flag */
3794#define nMBRIF0 0x0
3795#define MBRIF1 0x2 /* Mailbox 1 Mailbox Receive Interrupt Flag */
3796#define nMBRIF1 0x0
3797#define MBRIF2 0x4 /* Mailbox 2 Mailbox Receive Interrupt Flag */
3798#define nMBRIF2 0x0
3799#define MBRIF3 0x8 /* Mailbox 3 Mailbox Receive Interrupt Flag */
3800#define nMBRIF3 0x0
3801#define MBRIF4 0x10 /* Mailbox 4 Mailbox Receive Interrupt Flag */
3802#define nMBRIF4 0x0
3803#define MBRIF5 0x20 /* Mailbox 5 Mailbox Receive Interrupt Flag */
3804#define nMBRIF5 0x0
3805#define MBRIF6 0x40 /* Mailbox 6 Mailbox Receive Interrupt Flag */
3806#define nMBRIF6 0x0
3807#define MBRIF7 0x80 /* Mailbox 7 Mailbox Receive Interrupt Flag */
3808#define nMBRIF7 0x0
3809#define MBRIF8 0x100 /* Mailbox 8 Mailbox Receive Interrupt Flag */
3810#define nMBRIF8 0x0
3811#define MBRIF9 0x200 /* Mailbox 9 Mailbox Receive Interrupt Flag */
3812#define nMBRIF9 0x0
3813#define MBRIF10 0x400 /* Mailbox 10 Mailbox Receive Interrupt Flag */
3814#define nMBRIF10 0x0
3815#define MBRIF11 0x800 /* Mailbox 11 Mailbox Receive Interrupt Flag */
3816#define nMBRIF11 0x0
3817#define MBRIF12 0x1000 /* Mailbox 12 Mailbox Receive Interrupt Flag */
3818#define nMBRIF12 0x0
3819#define MBRIF13 0x2000 /* Mailbox 13 Mailbox Receive Interrupt Flag */
3820#define nMBRIF13 0x0
3821#define MBRIF14 0x4000 /* Mailbox 14 Mailbox Receive Interrupt Flag */
3822#define nMBRIF14 0x0
3823#define MBRIF15 0x8000 /* Mailbox 15 Mailbox Receive Interrupt Flag */
3824#define nMBRIF15 0x0
3825
3826/* Bit masks for CAN0_MBRIF2 */
3827
3828#define MBRIF16 0x1 /* Mailbox 16 Mailbox Receive Interrupt Flag */
3829#define nMBRIF16 0x0
3830#define MBRIF17 0x2 /* Mailbox 17 Mailbox Receive Interrupt Flag */
3831#define nMBRIF17 0x0
3832#define MBRIF18 0x4 /* Mailbox 18 Mailbox Receive Interrupt Flag */
3833#define nMBRIF18 0x0
3834#define MBRIF19 0x8 /* Mailbox 19 Mailbox Receive Interrupt Flag */
3835#define nMBRIF19 0x0
3836#define MBRIF20 0x10 /* Mailbox 20 Mailbox Receive Interrupt Flag */
3837#define nMBRIF20 0x0
3838#define MBRIF21 0x20 /* Mailbox 21 Mailbox Receive Interrupt Flag */
3839#define nMBRIF21 0x0
3840#define MBRIF22 0x40 /* Mailbox 22 Mailbox Receive Interrupt Flag */
3841#define nMBRIF22 0x0
3842#define MBRIF23 0x80 /* Mailbox 23 Mailbox Receive Interrupt Flag */
3843#define nMBRIF23 0x0
3844#define MBRIF24 0x100 /* Mailbox 24 Mailbox Receive Interrupt Flag */
3845#define nMBRIF24 0x0
3846#define MBRIF25 0x200 /* Mailbox 25 Mailbox Receive Interrupt Flag */
3847#define nMBRIF25 0x0
3848#define MBRIF26 0x400 /* Mailbox 26 Mailbox Receive Interrupt Flag */
3849#define nMBRIF26 0x0
3850#define MBRIF27 0x800 /* Mailbox 27 Mailbox Receive Interrupt Flag */
3851#define nMBRIF27 0x0
3852#define MBRIF28 0x1000 /* Mailbox 28 Mailbox Receive Interrupt Flag */
3853#define nMBRIF28 0x0
3854#define MBRIF29 0x2000 /* Mailbox 29 Mailbox Receive Interrupt Flag */
3855#define nMBRIF29 0x0
3856#define MBRIF30 0x4000 /* Mailbox 30 Mailbox Receive Interrupt Flag */
3857#define nMBRIF30 0x0
3858#define MBRIF31 0x8000 /* Mailbox 31 Mailbox Receive Interrupt Flag */
3859#define nMBRIF31 0x0
3860
3861/* Bit masks for EPPIx_STATUS */
3862
3863#define CFIFO_ERR 0x1 /* Chroma FIFO Error */
3864#define nCFIFO_ERR 0x0
3865#define YFIFO_ERR 0x2 /* Luma FIFO Error */
3866#define nYFIFO_ERR 0x0
3867#define LTERR_OVR 0x4 /* Line Track Overflow */
3868#define nLTERR_OVR 0x0
3869#define LTERR_UNDR 0x8 /* Line Track Underflow */
3870#define nLTERR_UNDR 0x0
3871#define FTERR_OVR 0x10 /* Frame Track Overflow */
3872#define nFTERR_OVR 0x0
3873#define FTERR_UNDR 0x20 /* Frame Track Underflow */
3874#define nFTERR_UNDR 0x0
3875#define ERR_NCOR 0x40 /* Preamble Error Not Corrected */
3876#define nERR_NCOR 0x0
3877#define DMA1URQ 0x80 /* DMA1 Urgent Request */
3878#define nDMA1URQ 0x0
3879#define DMA0URQ 0x100 /* DMA0 Urgent Request */
3880#define nDMA0URQ 0x0
3881#define ERR_DET 0x4000 /* Preamble Error Detected */
3882#define nERR_DET 0x0
3883#define FLD 0x8000 /* Field */
3884#define nFLD 0x0
3885
3886/* Bit masks for EPPIx_CONTROL */
3887
3888#define EPPI_EN 0x1 /* Enable */
3889#define nEPPI_EN 0x0
3890#define EPPI_DIR 0x2 /* Direction */
3891#define nEPPI_DIR 0x0
3892#define XFR_TYPE 0xc /* Operating Mode */
3893#define FS_CFG 0x30 /* Frame Sync Configuration */
3894#define FLD_SEL 0x40 /* Field Select/Trigger */
3895#define nFLD_SEL 0x0
3896#define ITU_TYPE 0x80 /* ITU Interlaced or Progressive */
3897#define nITU_TYPE 0x0
3898#define BLANKGEN 0x100 /* ITU Output Mode with Internal Blanking Generation */
3899#define nBLANKGEN 0x0
3900#define ICLKGEN 0x200 /* Internal Clock Generation */
3901#define nICLKGEN 0x0
3902#define IFSGEN 0x400 /* Internal Frame Sync Generation */
3903#define nIFSGEN 0x0
3904#define POLC 0x1800 /* Frame Sync and Data Driving/Sampling Edges */
3905#define POLS 0x6000 /* Frame Sync Polarity */
3906#define DLENGTH 0x38000 /* Data Length */
3907#define SKIP_EN 0x40000 /* Skip Enable */
3908#define nSKIP_EN 0x0
3909#define SKIP_EO 0x80000 /* Skip Even or Odd */
3910#define nSKIP_EO 0x0
3911#define PACKEN 0x100000 /* Packing/Unpacking Enable */
3912#define nPACKEN 0x0
3913#define SWAPEN 0x200000 /* Swap Enable */
3914#define nSWAPEN 0x0
3915#define SIGN_EXT 0x400000 /* Sign Extension or Zero-filled / Data Split Format */
3916#define nSIGN_EXT 0x0
3917#define SPLT_EVEN_ODD 0x800000 /* Split Even and Odd Data Samples */
3918#define nSPLT_EVEN_ODD 0x0
3919#define SUBSPLT_ODD 0x1000000 /* Sub-split Odd Samples */
3920#define nSUBSPLT_ODD 0x0
3921#define DMACFG 0x2000000 /* One or Two DMA Channels Mode */
3922#define nDMACFG 0x0
3923#define RGB_FMT_EN 0x4000000 /* RGB Formatting Enable */
3924#define nRGB_FMT_EN 0x0
3925#define FIFO_RWM 0x18000000 /* FIFO Regular Watermarks */
3926#define FIFO_UWM 0x60000000 /* FIFO Urgent Watermarks */
3927
3928/* Bit masks for EPPIx_FS2W_LVB */
3929
3930#define F1VB_BD 0xff /* Vertical Blanking before Field 1 Active Data */
3931#define F1VB_AD 0xff00 /* Vertical Blanking after Field 1 Active Data */
3932#define F2VB_BD 0xff0000 /* Vertical Blanking before Field 2 Active Data */
3933#define F2VB_AD 0xff000000 /* Vertical Blanking after Field 2 Active Data */
3934
3935/* Bit masks for EPPIx_FS2W_LAVF */
3936
3937#define F1_ACT 0xffff /* Number of Lines of Active Data in Field 1 */
3938#define F2_ACT 0xffff0000 /* Number of Lines of Active Data in Field 2 */
3939
3940/* Bit masks for EPPIx_CLIP */
3941
3942#define LOW_ODD 0xff /* Lower Limit for Odd Bytes (Chroma) */
3943#define HIGH_ODD 0xff00 /* Upper Limit for Odd Bytes (Chroma) */
3944#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
3945#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
3946
3947/* Bit masks for SPIx_BAUD */
3948
3949#define SPI_BAUD 0xffff /* Baud Rate */
3950
3951/* Bit masks for SPIx_CTL */
3952
3953#define SPE 0x4000 /* SPI Enable */
3954#define nSPE 0x0
3955#define WOM 0x2000 /* Write Open Drain Master */
3956#define nWOM 0x0
3957#define MSTR 0x1000 /* Master Mode */
3958#define nMSTR 0x0
3959#define CPOL 0x800 /* Clock Polarity */
3960#define nCPOL 0x0
3961#define CPHA 0x400 /* Clock Phase */
3962#define nCPHA 0x0
3963#define LSBF 0x200 /* LSB First */
3964#define nLSBF 0x0
3965#define SIZE 0x100 /* Size of Words */
3966#define nSIZE 0x0
3967#define EMISO 0x20 /* Enable MISO Output */
3968#define nEMISO 0x0
3969#define PSSE 0x10 /* Slave-Select Enable */
3970#define nPSSE 0x0
3971#define GM 0x8 /* Get More Data */
3972#define nGM 0x0
3973#define SZ 0x4 /* Send Zero */
3974#define nSZ 0x0
3975#define TIMOD 0x3 /* Transfer Initiation Mode */
3976
3977/* Bit masks for SPIx_FLG */
3978
3979#define FLS1 0x2 /* Slave Select Enable 1 */
3980#define nFLS1 0x0
3981#define FLS2 0x4 /* Slave Select Enable 2 */
3982#define nFLS2 0x0
3983#define FLS3 0x8 /* Slave Select Enable 3 */
3984#define nFLS3 0x0
3985#define FLG1 0x200 /* Slave Select Value 1 */
3986#define nFLG1 0x0
3987#define FLG2 0x400 /* Slave Select Value 2 */
3988#define nFLG2 0x0
3989#define FLG3 0x800 /* Slave Select Value 3 */
3990#define nFLG3 0x0
3991
3992/* Bit masks for SPIx_STAT */
3993
3994#define TXCOL 0x40 /* Transmit Collision Error */
3995#define nTXCOL 0x0
3996#define RXS 0x20 /* RDBR Data Buffer Status */
3997#define nRXS 0x0
3998#define RBSY 0x10 /* Receive Error */
3999#define nRBSY 0x0
4000#define TXS 0x8 /* TDBR Data Buffer Status */
4001#define nTXS 0x0
4002#define TXE 0x4 /* Transmission Error */
4003#define nTXE 0x0
4004#define MODF 0x2 /* Mode Fault Error */
4005#define nMODF 0x0
4006#define SPIF 0x1 /* SPI Finished */
4007#define nSPIF 0x0
4008
4009/* Bit masks for SPIx_TDBR */
4010
4011#define TDBR 0xffff /* Transmit Data Buffer */
4012
4013/* Bit masks for SPIx_RDBR */
4014
4015#define RDBR 0xffff /* Receive Data Buffer */
4016
4017/* Bit masks for SPIx_SHADOW */
4018
4019#define SHADOW 0xffff /* RDBR Shadow */
4020
4021/* ************************************************ */
4022/* The TWI bit masks fields are from the ADSP-BF538 */
4023/* and they have not been verified as the final */
4024/* ones for the Moab processors ... bz 1/19/2007 */
4025/* ************************************************ */
4026
4027/* Bit masks for TWIx_CONTROL */
4028
4029#define PRESCALE 0x7f /* Prescale Value */
4030#define TWI_ENA 0x80 /* TWI Enable */
4031#define nTWI_ENA 0x0
4032#define SCCB 0x200 /* Serial Camera Control Bus */
4033#define nSCCB 0x0
4034
4035/* Bit maskes for TWIx_CLKDIV */
4036
4037#define CLKLOW 0xff /* Clock Low */
4038#define CLKHI 0xff00 /* Clock High */
4039
4040/* Bit maskes for TWIx_SLAVE_CTL */
4041
4042#define SEN 0x1 /* Slave Enable */
4043#define nSEN 0x0
4044#define STDVAL 0x4 /* Slave Transmit Data Valid */
4045#define nSTDVAL 0x0
4046#define NAK 0x8 /* Not Acknowledge */
4047#define nNAK 0x0
4048#define GEN 0x10 /* General Call Enable */
4049#define nGEN 0x0
4050
4051/* Bit maskes for TWIx_SLAVE_ADDR */
4052
4053#define SADDR 0x7f /* Slave Mode Address */
4054
4055/* Bit maskes for TWIx_SLAVE_STAT */
4056
4057#define SDIR 0x1 /* Slave Transfer Direction */
4058#define nSDIR 0x0
4059#define GCALL 0x2 /* General Call */
4060#define nGCALL 0x0
4061
4062/* Bit maskes for TWIx_MASTER_CTL */
4063
4064#define MEN 0x1 /* Master Mode Enable */
4065#define nMEN 0x0
4066#define MDIR 0x4 /* Master Transfer Direction */
4067#define nMDIR 0x0
4068#define FAST 0x8 /* Fast Mode */
4069#define nFAST 0x0
4070#define STOP 0x10 /* Issue Stop Condition */
4071#define nSTOP 0x0
4072#define RSTART 0x20 /* Repeat Start */
4073#define nRSTART 0x0
4074#define DCNT 0x3fc0 /* Data Transfer Count */
4075#define SDAOVR 0x4000 /* Serial Data Override */
4076#define nSDAOVR 0x0
4077#define SCLOVR 0x8000 /* Serial Clock Override */
4078#define nSCLOVR 0x0
4079
4080/* Bit maskes for TWIx_MASTER_ADDR */
4081
4082#define MADDR 0x7f /* Master Mode Address */
4083
4084/* Bit maskes for TWIx_MASTER_STAT */
4085
4086#define MPROG 0x1 /* Master Transfer in Progress */
4087#define nMPROG 0x0
4088#define LOSTARB 0x2 /* Lost Arbitration */
4089#define nLOSTARB 0x0
4090#define ANAK 0x4 /* Address Not Acknowledged */
4091#define nANAK 0x0
4092#define DNAK 0x8 /* Data Not Acknowledged */
4093#define nDNAK 0x0
4094#define BUFRDERR 0x10 /* Buffer Read Error */
4095#define nBUFRDERR 0x0
4096#define BUFWRERR 0x20 /* Buffer Write Error */
4097#define nBUFWRERR 0x0
4098#define SDASEN 0x40 /* Serial Data Sense */
4099#define nSDASEN 0x0
4100#define SCLSEN 0x80 /* Serial Clock Sense */
4101#define nSCLSEN 0x0
4102#define BUSBUSY 0x100 /* Bus Busy */
4103#define nBUSBUSY 0x0
4104
4105/* Bit maskes for TWIx_FIFO_CTL */
4106
4107#define XMTFLUSH 0x1 /* Transmit Buffer Flush */
4108#define nXMTFLUSH 0x0
4109#define RCVFLUSH 0x2 /* Receive Buffer Flush */
4110#define nRCVFLUSH 0x0
4111#define XMTINTLEN 0x4 /* Transmit Buffer Interrupt Length */
4112#define nXMTINTLEN 0x0
4113#define RCVINTLEN 0x8 /* Receive Buffer Interrupt Length */
4114#define nRCVINTLEN 0x0
4115
4116/* Bit maskes for TWIx_FIFO_STAT */
4117
4118#define XMTSTAT 0x3 /* Transmit FIFO Status */
4119#define RCVSTAT 0xc /* Receive FIFO Status */
4120
4121/* Bit maskes for TWIx_INT_MASK */
4122
4123#define SINITM 0x1 /* Slave Transfer Initiated Interrupt Mask */
4124#define nSINITM 0x0
4125#define SCOMPM 0x2 /* Slave Transfer Complete Interrupt Mask */
4126#define nSCOMPM 0x0
4127#define SERRM 0x4 /* Slave Transfer Error Interrupt Mask */
4128#define nSERRM 0x0
4129#define SOVFM 0x8 /* Slave Overflow Interrupt Mask */
4130#define nSOVFM 0x0
4131#define MCOMPM 0x10 /* Master Transfer Complete Interrupt Mask */
4132#define nMCOMPM 0x0
4133#define MERRM 0x20 /* Master Transfer Error Interrupt Mask */
4134#define nMERRM 0x0
4135#define XMTSERVM 0x40 /* Transmit FIFO Service Interrupt Mask */
4136#define nXMTSERVM 0x0
4137#define RCVSERVM 0x80 /* Receive FIFO Service Interrupt Mask */
4138#define nRCVSERVM 0x0
4139
4140/* Bit maskes for TWIx_INT_STAT */
4141
4142#define SINIT 0x1 /* Slave Transfer Initiated */
4143#define nSINIT 0x0
4144#define SCOMP 0x2 /* Slave Transfer Complete */
4145#define nSCOMP 0x0
4146#define SERR 0x4 /* Slave Transfer Error */
4147#define nSERR 0x0
4148#define SOVF 0x8 /* Slave Overflow */
4149#define nSOVF 0x0
4150#define MCOMP 0x10 /* Master Transfer Complete */
4151#define nMCOMP 0x0
4152#define MERR 0x20 /* Master Transfer Error */
4153#define nMERR 0x0
4154#define XMTSERV 0x40 /* Transmit FIFO Service */
4155#define nXMTSERV 0x0
4156#define RCVSERV 0x80 /* Receive FIFO Service */
4157#define nRCVSERV 0x0
4158
4159/* Bit maskes for TWIx_XMT_DATA8 */
4160
4161#define XMTDATA8 0xff /* Transmit FIFO 8-Bit Data */
4162
4163/* Bit maskes for TWIx_XMT_DATA16 */
4164
4165#define XMTDATA16 0xffff /* Transmit FIFO 16-Bit Data */
4166
4167/* Bit maskes for TWIx_RCV_DATA8 */
4168
4169#define RCVDATA8 0xff /* Receive FIFO 8-Bit Data */
4170
4171/* Bit maskes for TWIx_RCV_DATA16 */
4172
4173#define RCVDATA16 0xffff /* Receive FIFO 16-Bit Data */
4174
4175/* Bit masks for SPORTx_TCR1 */
4176
4177#define TCKFE 0x4000 /* Clock Falling Edge Select */
4178#define nTCKFE 0x0
4179#define LATFS 0x2000 /* Late Transmit Frame Sync */
4180#define nLATFS 0x0
4181#define LTFS 0x1000 /* Low Transmit Frame Sync Select */
4182#define nLTFS 0x0
4183#define DITFS 0x800 /* Data-Independent Transmit Frame Sync Select */
4184#define nDITFS 0x0
4185#define TFSR 0x400 /* Transmit Frame Sync Required Select */
4186#define nTFSR 0x0
4187#define ITFS 0x200 /* Internal Transmit Frame Sync Select */
4188#define nITFS 0x0
4189#define TLSBIT 0x10 /* Transmit Bit Order */
4190#define nTLSBIT 0x0
4191#define TDTYPE 0xc /* Data Formatting Type Select */
4192#define ITCLK 0x2 /* Internal Transmit Clock Select */
4193#define nITCLK 0x0
4194#define TSPEN 0x1 /* Transmit Enable */
4195#define nTSPEN 0x0
4196
4197/* Bit masks for SPORTx_TCR2 */
4198
4199#define TRFST 0x400 /* Left/Right Order */
4200#define nTRFST 0x0
4201#define TSFSE 0x200 /* Transmit Stereo Frame Sync Enable */
4202#define nTSFSE 0x0
4203#define TXSE 0x100 /* TxSEC Enable */
4204#define nTXSE 0x0
4205#define SLEN_T 0x1f /* SPORT Word Length */
4206
4207/* Bit masks for SPORTx_RCR1 */
4208
4209#define RCKFE 0x4000 /* Clock Falling Edge Select */
4210#define nRCKFE 0x0
4211#define LARFS 0x2000 /* Late Receive Frame Sync */
4212#define nLARFS 0x0
4213#define LRFS 0x1000 /* Low Receive Frame Sync Select */
4214#define nLRFS 0x0
4215#define RFSR 0x400 /* Receive Frame Sync Required Select */
4216#define nRFSR 0x0
4217#define IRFS 0x200 /* Internal Receive Frame Sync Select */
4218#define nIRFS 0x0
4219#define RLSBIT 0x10 /* Receive Bit Order */
4220#define nRLSBIT 0x0
4221#define RDTYPE 0xc /* Data Formatting Type Select */
4222#define IRCLK 0x2 /* Internal Receive Clock Select */
4223#define nIRCLK 0x0
4224#define RSPEN 0x1 /* Receive Enable */
4225#define nRSPEN 0x0
4226
4227/* Bit masks for SPORTx_RCR2 */
4228
4229#define RRFST 0x400 /* Left/Right Order */
4230#define nRRFST 0x0
4231#define RSFSE 0x200 /* Receive Stereo Frame Sync Enable */
4232#define nRSFSE 0x0
4233#define RXSE 0x100 /* RxSEC Enable */
4234#define nRXSE 0x0
4235#define SLEN_R 0x1f /* SPORT Word Length */
4236
4237/* Bit masks for SPORTx_STAT */
4238
4239#define TXHRE 0x40 /* Transmit Hold Register Empty */
4240#define nTXHRE 0x0
4241#define TOVF 0x20 /* Sticky Transmit Overflow Status */
4242#define nTOVF 0x0
4243#define TUVF 0x10 /* Sticky Transmit Underflow Status */
4244#define nTUVF 0x0
4245#define TXF 0x8 /* Transmit FIFO Full Status */
4246#define nTXF 0x0
4247#define ROVF 0x4 /* Sticky Receive Overflow Status */
4248#define nROVF 0x0
4249#define RUVF 0x2 /* Sticky Receive Underflow Status */
4250#define nRUVF 0x0
4251#define RXNE 0x1 /* Receive FIFO Not Empty Status */
4252#define nRXNE 0x0
4253
4254/* Bit masks for SPORTx_MCMC1 */
4255
4256#define SP_WSIZE 0xf000 /* Window Size */
4257#define SP_WOFF 0x3ff /* Windows Offset */
4258
4259/* Bit masks for SPORTx_MCMC2 */
4260
4261#define MFD 0xf000 /* Multi channel Frame Delay */
4262#define FSDR 0x80 /* Frame Sync to Data Relationship */
4263#define nFSDR 0x0
4264#define MCMEM 0x10 /* Multi channel Frame Mode Enable */
4265#define nMCMEM 0x0
4266#define MCDRXPE 0x8 /* Multi channel DMA Receive Packing */
4267#define nMCDRXPE 0x0
4268#define MCDTXPE 0x4 /* Multi channel DMA Transmit Packing */
4269#define nMCDTXPE 0x0
4270#define MCCRM 0x3 /* 2X Clock Recovery Mode */
4271
4272/* Bit masks for SPORTx_CHNL */
4273
4274#define CUR_CHNL 0x3ff /* Current Channel Indicator */
4275
4276/* Bit masks for UARTx_LCR */
4277
4278#if 0
4279/* conflicts with legacy one in last section */
4280#define WLS 0x3 /* Word Length Select */
4281#endif
4282#define STB 0x4 /* Stop Bits */
4283#define nSTB 0x0
4284#define PEN 0x8 /* Parity Enable */
4285#define nPEN 0x0
4286#define EPS 0x10 /* Even Parity Select */
4287#define nEPS 0x0
4288#define STP 0x20 /* Sticky Parity */
4289#define nSTP 0x0
4290#define SB 0x40 /* Set Break */
4291#define nSB 0x0
4292
4293/* Bit masks for UARTx_MCR */
4294
4295#define XOFF 0x1 /* Transmitter Off */
4296#define nXOFF 0x0
4297#define MRTS 0x2 /* Manual Request To Send */
4298#define nMRTS 0x0
4299#define RFIT 0x4 /* Receive FIFO IRQ Threshold */
4300#define nRFIT 0x0
4301#define RFRT 0x8 /* Receive FIFO RTS Threshold */
4302#define nRFRT 0x0
4303#define LOOP_ENA 0x10 /* Loopback Mode Enable */
4304#define nLOOP_ENA 0x0
4305#define FCPOL 0x20 /* Flow Control Pin Polarity */
4306#define nFCPOL 0x0
4307#define ARTS 0x40 /* Automatic Request To Send */
4308#define nARTS 0x0
4309#define ACTS 0x80 /* Automatic Clear To Send */
4310#define nACTS 0x0
4311
4312/* Bit masks for UARTx_LSR */
4313
4314#define DR 0x1 /* Data Ready */
4315#define nDR 0x0
4316#define OE 0x2 /* Overrun Error */
4317#define nOE 0x0
4318#define PE 0x4 /* Parity Error */
4319#define nPE 0x0
4320#define FE 0x8 /* Framing Error */
4321#define nFE 0x0
4322#define BI 0x10 /* Break Interrupt */
4323#define nBI 0x0
4324#define THRE 0x20 /* THR Empty */
4325#define nTHRE 0x0
4326#define TEMT 0x40 /* Transmitter Empty */
4327#define nTEMT 0x0
4328#define TFI 0x80 /* Transmission Finished Indicator */
4329#define nTFI 0x0
4330
4331/* Bit masks for UARTx_MSR */
4332
4333#define SCTS 0x1 /* Sticky CTS */
4334#define nSCTS 0x0
4335#define CTS 0x10 /* Clear To Send */
4336#define nCTS 0x0
4337#define RFCS 0x20 /* Receive FIFO Count Status */
4338#define nRFCS 0x0
4339
4340/* Bit masks for UARTx_IER_SET */
4341
4342#define ERBFI_S 0x1 /* Enable Receive Buffer Full Interrupt */
4343#define nERBFI_S 0x0
4344#define ETBEI_S 0x2 /* Enable Transmit Buffer Empty Interrupt */
4345#define nETBEI_S 0x0
4346#define ELSI_S 0x4 /* Enable Receive Status Interrupt */
4347#define nELSI_S 0x0
4348#define EDSSI_S 0x8 /* Enable Modem Status Interrupt */
4349#define nEDSSI_S 0x0
4350#define EDTPTI_S 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4351#define nEDTPTI_S 0x0
4352#define ETFI_S 0x20 /* Enable Transmission Finished Interrupt */
4353#define nETFI_S 0x0
4354#define ERFCI_S 0x40 /* Enable Receive FIFO Count Interrupt */
4355#define nERFCI_S 0x0
4356
4357/* Bit masks for UARTx_IER_CLEAR */
4358
4359#define ERBFI_C 0x1 /* Enable Receive Buffer Full Interrupt */
4360#define nERBFI_C 0x0
4361#define ETBEI_C 0x2 /* Enable Transmit Buffer Empty Interrupt */
4362#define nETBEI_C 0x0
4363#define ELSI_C 0x4 /* Enable Receive Status Interrupt */
4364#define nELSI_C 0x0
4365#define EDSSI_C 0x8 /* Enable Modem Status Interrupt */
4366#define nEDSSI_C 0x0
4367#define EDTPTI_C 0x10 /* Enable DMA Transmit PIRQ Interrupt */
4368#define nEDTPTI_C 0x0
4369#define ETFI_C 0x20 /* Enable Transmission Finished Interrupt */
4370#define nETFI_C 0x0
4371#define ERFCI_C 0x40 /* Enable Receive FIFO Count Interrupt */
4372#define nERFCI_C 0x0
4373
4374/* Bit masks for UARTx_GCTL */
4375
4376#define UCEN 0x1 /* UART Enable */
4377#define nUCEN 0x0
4378#define IREN 0x2 /* IrDA Mode Enable */
4379#define nIREN 0x0
4380#define TPOLC 0x4 /* IrDA TX Polarity Change */
4381#define nTPOLC 0x0
4382#define RPOLC 0x8 /* IrDA RX Polarity Change */
4383#define nRPOLC 0x0
4384#define FPE 0x10 /* Force Parity Error */
4385#define nFPE 0x0
4386#define FFE 0x20 /* Force Framing Error */
4387#define nFFE 0x0
4388#define EDBO 0x40 /* Enable Divide-by-One */
4389#define nEDBO 0x0
4390#define EGLSI 0x80 /* Enable Global LS Interrupt */
4391#define nEGLSI 0x0
4392
4393
4394/* ******************************************* */
4395/* MULTI BIT MACRO ENUMERATIONS */
4396/* ******************************************* */
4397
4398/* BCODE bit field options (SYSCFG register) */
4399
4400#define BCODE_WAKEUP 0x0000 /* boot according to wake-up condition */
4401#define BCODE_FULLBOOT 0x0010 /* always perform full boot */
4402#define BCODE_QUICKBOOT 0x0020 /* always perform quick boot */
4403#define BCODE_NOBOOT 0x0030 /* always perform full boot */
4404
4405/* CNT_COMMAND bit field options */
4406
4407#define W1LCNT_ZERO 0x0001 /* write 1 to load CNT_COUNTER with zero */
4408#define W1LCNT_MIN 0x0004 /* write 1 to load CNT_COUNTER from CNT_MIN */
4409#define W1LCNT_MAX 0x0008 /* write 1 to load CNT_COUNTER from CNT_MAX */
4410
4411#define W1LMIN_ZERO 0x0010 /* write 1 to load CNT_MIN with zero */
4412#define W1LMIN_CNT 0x0020 /* write 1 to load CNT_MIN from CNT_COUNTER */
4413#define W1LMIN_MAX 0x0080 /* write 1 to load CNT_MIN from CNT_MAX */
4414
4415#define W1LMAX_ZERO 0x0100 /* write 1 to load CNT_MAX with zero */
4416#define W1LMAX_CNT 0x0200 /* write 1 to load CNT_MAX from CNT_COUNTER */
4417#define W1LMAX_MIN 0x0400 /* write 1 to load CNT_MAX from CNT_MIN */
4418
4419/* CNT_CONFIG bit field options */
4420
4421#define CNTMODE_QUADENC 0x0000 /* quadrature encoder mode */
4422#define CNTMODE_BINENC 0x0100 /* binary encoder mode */
4423#define CNTMODE_UDCNT 0x0200 /* up/down counter mode */
4424#define CNTMODE_DIRCNT 0x0400 /* direction counter mode */
4425#define CNTMODE_DIRTMR 0x0500 /* direction timer mode */
4426
4427#define BNDMODE_COMP 0x0000 /* boundary compare mode */
4428#define BNDMODE_ZERO 0x1000 /* boundary compare and zero mode */
4429#define BNDMODE_CAPT 0x2000 /* boundary capture mode */
4430#define BNDMODE_AEXT 0x3000 /* boundary auto-extend mode */
4431
4432/* TMODE in TIMERx_CONFIG bit field options */
4433
4434#define PWM_OUT 0x0001
4435#define WDTH_CAP 0x0002
4436#define EXT_CLK 0x0003
4437
4438/* UARTx_LCR bit field options */
4439
4440#define WLS_5 0x0000 /* 5 data bits */
4441#define WLS_6 0x0001 /* 6 data bits */
4442#define WLS_7 0x0002 /* 7 data bits */
4443#define WLS_8 0x0003 /* 8 data bits */
4444
4445/* PINTx Register Bit Definitions */
4446
4447#define PIQ0 0x00000001
4448#define PIQ1 0x00000002
4449#define PIQ2 0x00000004
4450#define PIQ3 0x00000008
4451
4452#define PIQ4 0x00000010
4453#define PIQ5 0x00000020
4454#define PIQ6 0x00000040
4455#define PIQ7 0x00000080
4456
4457#define PIQ8 0x00000100
4458#define PIQ9 0x00000200
4459#define PIQ10 0x00000400
4460#define PIQ11 0x00000800
4461
4462#define PIQ12 0x00001000
4463#define PIQ13 0x00002000
4464#define PIQ14 0x00004000
4465#define PIQ15 0x00008000
4466
4467#define PIQ16 0x00010000
4468#define PIQ17 0x00020000
4469#define PIQ18 0x00040000
4470#define PIQ19 0x00080000
4471
4472#define PIQ20 0x00100000
4473#define PIQ21 0x00200000
4474#define PIQ22 0x00400000
4475#define PIQ23 0x00800000
4476
4477#define PIQ24 0x01000000
4478#define PIQ25 0x02000000
4479#define PIQ26 0x04000000
4480#define PIQ27 0x08000000
4481
4482#define PIQ28 0x10000000
4483#define PIQ29 0x20000000
4484#define PIQ30 0x40000000
4485#define PIQ31 0x80000000
4486
4487/* PORT A Bit Definitions for the registers
4488PORTA, PORTA_SET, PORTA_CLEAR,
4489PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
4490PORTA_FER registers
4491*/
4492
4493#define PA0 0x0001
4494#define PA1 0x0002
4495#define PA2 0x0004
4496#define PA3 0x0008
4497#define PA4 0x0010
4498#define PA5 0x0020
4499#define PA6 0x0040
4500#define PA7 0x0080
4501#define PA8 0x0100
4502#define PA9 0x0200
4503#define PA10 0x0400
4504#define PA11 0x0800
4505#define PA12 0x1000
4506#define PA13 0x2000
4507#define PA14 0x4000
4508#define PA15 0x8000
4509
4510/* PORT B Bit Definitions for the registers
4511PORTB, PORTB_SET, PORTB_CLEAR,
4512PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
4513PORTB_FER registers
4514*/
4515
4516#define PB0 0x0001
4517#define PB1 0x0002
4518#define PB2 0x0004
4519#define PB3 0x0008
4520#define PB4 0x0010
4521#define PB5 0x0020
4522#define PB6 0x0040
4523#define PB7 0x0080
4524#define PB8 0x0100
4525#define PB9 0x0200
4526#define PB10 0x0400
4527#define PB11 0x0800
4528#define PB12 0x1000
4529#define PB13 0x2000
4530#define PB14 0x4000
4531
4532
4533/* PORT C Bit Definitions for the registers
4534PORTC, PORTC_SET, PORTC_CLEAR,
4535PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
4536PORTC_FER registers
4537*/
4538
4539
4540#define PC0 0x0001
4541#define PC1 0x0002
4542#define PC2 0x0004
4543#define PC3 0x0008
4544#define PC4 0x0010
4545#define PC5 0x0020
4546#define PC6 0x0040
4547#define PC7 0x0080
4548#define PC8 0x0100
4549#define PC9 0x0200
4550#define PC10 0x0400
4551#define PC11 0x0800
4552#define PC12 0x1000
4553#define PC13 0x2000
4554
4555
4556/* PORT D Bit Definitions for the registers
4557PORTD, PORTD_SET, PORTD_CLEAR,
4558PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
4559PORTD_FER registers
4560*/
4561
4562#define PD0 0x0001
4563#define PD1 0x0002
4564#define PD2 0x0004
4565#define PD3 0x0008
4566#define PD4 0x0010
4567#define PD5 0x0020
4568#define PD6 0x0040
4569#define PD7 0x0080
4570#define PD8 0x0100
4571#define PD9 0x0200
4572#define PD10 0x0400
4573#define PD11 0x0800
4574#define PD12 0x1000
4575#define PD13 0x2000
4576#define PD14 0x4000
4577#define PD15 0x8000
4578
4579/* PORT E Bit Definitions for the registers
4580PORTE, PORTE_SET, PORTE_CLEAR,
4581PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
4582PORTE_FER registers
4583*/
4584
4585
4586#define PE0 0x0001
4587#define PE1 0x0002
4588#define PE2 0x0004
4589#define PE3 0x0008
4590#define PE4 0x0010
4591#define PE5 0x0020
4592#define PE6 0x0040
4593#define PE7 0x0080
4594#define PE8 0x0100
4595#define PE9 0x0200
4596#define PE10 0x0400
4597#define PE11 0x0800
4598#define PE12 0x1000
4599#define PE13 0x2000
4600#define PE14 0x4000
4601#define PE15 0x8000
4602
4603/* PORT F Bit Definitions for the registers
4604PORTF, PORTF_SET, PORTF_CLEAR,
4605PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
4606PORTF_FER registers
4607*/
4608
4609
4610#define PF0 0x0001
4611#define PF1 0x0002
4612#define PF2 0x0004
4613#define PF3 0x0008
4614#define PF4 0x0010
4615#define PF5 0x0020
4616#define PF6 0x0040
4617#define PF7 0x0080
4618#define PF8 0x0100
4619#define PF9 0x0200
4620#define PF10 0x0400
4621#define PF11 0x0800
4622#define PF12 0x1000
4623#define PF13 0x2000
4624#define PF14 0x4000
4625#define PF15 0x8000
4626
4627/* PORT G Bit Definitions for the registers
4628PORTG, PORTG_SET, PORTG_CLEAR,
4629PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
4630PORTG_FER registers
4631*/
4632
4633
4634#define PG0 0x0001
4635#define PG1 0x0002
4636#define PG2 0x0004
4637#define PG3 0x0008
4638#define PG4 0x0010
4639#define PG5 0x0020
4640#define PG6 0x0040
4641#define PG7 0x0080
4642#define PG8 0x0100
4643#define PG9 0x0200
4644#define PG10 0x0400
4645#define PG11 0x0800
4646#define PG12 0x1000
4647#define PG13 0x2000
4648#define PG14 0x4000
4649#define PG15 0x8000
4650
4651/* PORT H Bit Definitions for the registers
4652PORTH, PORTH_SET, PORTH_CLEAR,
4653PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
4654PORTH_FER registers
4655*/
4656
4657
4658#define PH0 0x0001
4659#define PH1 0x0002
4660#define PH2 0x0004
4661#define PH3 0x0008
4662#define PH4 0x0010
4663#define PH5 0x0020
4664#define PH6 0x0040
4665#define PH7 0x0080
4666#define PH8 0x0100
4667#define PH9 0x0200
4668#define PH10 0x0400
4669#define PH11 0x0800
4670#define PH12 0x1000
4671#define PH13 0x2000
4672
4673
4674/* PORT I Bit Definitions for the registers
4675PORTI, PORTI_SET, PORTI_CLEAR,
4676PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
4677PORTI_FER registers
4678*/
4679
4680
4681#define PI0 0x0001
4682#define PI1 0x0002
4683#define PI2 0x0004
4684#define PI3 0x0008
4685#define PI4 0x0010
4686#define PI5 0x0020
4687#define PI6 0x0040
4688#define PI7 0x0080
4689#define PI8 0x0100
4690#define PI9 0x0200
4691#define PI10 0x0400
4692#define PI11 0x0800
4693#define PI12 0x1000
4694#define PI13 0x2000
4695#define PI14 0x4000
4696#define PI15 0x8000
4697
4698/* PORT J Bit Definitions for the registers
4699PORTJ, PORTJ_SET, PORTJ_CLEAR,
4700PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
4701PORTJ_FER registers
4702*/
4703
4704
4705#define PJ0 0x0001
4706#define PJ1 0x0002
4707#define PJ2 0x0004
4708#define PJ3 0x0008
4709#define PJ4 0x0010
4710#define PJ5 0x0020
4711#define PJ6 0x0040
4712#define PJ7 0x0080
4713#define PJ8 0x0100
4714#define PJ9 0x0200
4715#define PJ10 0x0400
4716#define PJ11 0x0800
4717#define PJ12 0x1000
4718#define PJ13 0x2000
4719
4720
4721/* Port Muxing Bit Fields for PORTx_MUX Registers */
4722
4723#define MUX0 0x00000003
4724#define MUX0_0 0x00000000
4725#define MUX0_1 0x00000001
4726#define MUX0_2 0x00000002
4727#define MUX0_3 0x00000003
4728
4729#define MUX1 0x0000000C
4730#define MUX1_0 0x00000000
4731#define MUX1_1 0x00000004
4732#define MUX1_2 0x00000008
4733#define MUX1_3 0x0000000C
4734
4735#define MUX2 0x00000030
4736#define MUX2_0 0x00000000
4737#define MUX2_1 0x00000010
4738#define MUX2_2 0x00000020
4739#define MUX2_3 0x00000030
4740
4741#define MUX3 0x000000C0
4742#define MUX3_0 0x00000000
4743#define MUX3_1 0x00000040
4744#define MUX3_2 0x00000080
4745#define MUX3_3 0x000000C0
4746
4747#define MUX4 0x00000300
4748#define MUX4_0 0x00000000
4749#define MUX4_1 0x00000100
4750#define MUX4_2 0x00000200
4751#define MUX4_3 0x00000300
4752
4753#define MUX5 0x00000C00
4754#define MUX5_0 0x00000000
4755#define MUX5_1 0x00000400
4756#define MUX5_2 0x00000800
4757#define MUX5_3 0x00000C00
4758
4759#define MUX6 0x00003000
4760#define MUX6_0 0x00000000
4761#define MUX6_1 0x00001000
4762#define MUX6_2 0x00002000
4763#define MUX6_3 0x00003000
4764
4765#define MUX7 0x0000C000
4766#define MUX7_0 0x00000000
4767#define MUX7_1 0x00004000
4768#define MUX7_2 0x00008000
4769#define MUX7_3 0x0000C000
4770
4771#define MUX8 0x00030000
4772#define MUX8_0 0x00000000
4773#define MUX8_1 0x00010000
4774#define MUX8_2 0x00020000
4775#define MUX8_3 0x00030000
4776
4777#define MUX9 0x000C0000
4778#define MUX9_0 0x00000000
4779#define MUX9_1 0x00040000
4780#define MUX9_2 0x00080000
4781#define MUX9_3 0x000C0000
4782
4783#define MUX10 0x00300000
4784#define MUX10_0 0x00000000
4785#define MUX10_1 0x00100000
4786#define MUX10_2 0x00200000
4787#define MUX10_3 0x00300000
4788
4789#define MUX11 0x00C00000
4790#define MUX11_0 0x00000000
4791#define MUX11_1 0x00400000
4792#define MUX11_2 0x00800000
4793#define MUX11_3 0x00C00000
4794
4795#define MUX12 0x03000000
4796#define MUX12_0 0x00000000
4797#define MUX12_1 0x01000000
4798#define MUX12_2 0x02000000
4799#define MUX12_3 0x03000000
4800
4801#define MUX13 0x0C000000
4802#define MUX13_0 0x00000000
4803#define MUX13_1 0x04000000
4804#define MUX13_2 0x08000000
4805#define MUX13_3 0x0C000000
4806
4807#define MUX14 0x30000000
4808#define MUX14_0 0x00000000
4809#define MUX14_1 0x10000000
4810#define MUX14_2 0x20000000
4811#define MUX14_3 0x30000000
4812
4813#define MUX15 0xC0000000
4814#define MUX15_0 0x00000000
4815#define MUX15_1 0x40000000
4816#define MUX15_2 0x80000000
4817#define MUX15_3 0xC0000000
4818
4819#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
4820 ((((b15)&3) << 30) | \
4821 (((b14)&3) << 28) | \
4822 (((b13)&3) << 26) | \
4823 (((b12)&3) << 24) | \
4824 (((b11)&3) << 22) | \
4825 (((b10)&3) << 20) | \
4826 (((b9) &3) << 18) | \
4827 (((b8) &3) << 16) | \
4828 (((b7) &3) << 14) | \
4829 (((b6) &3) << 12) | \
4830 (((b5) &3) << 10) | \
4831 (((b4) &3) << 8) | \
4832 (((b3) &3) << 6) | \
4833 (((b2) &3) << 4) | \
4834 (((b1) &3) << 2) | \
4835 (((b0) &3)))
4836
4837/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
4838
4839#define B0MAP 0x000000FF /* Byte 0 Lower Half Port Mapping */
4840#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
4841#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
4842#define B1MAP 0x0000FF00 /* Byte 1 Upper Half Port Mapping */
4843#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
4844#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
4845#define B2MAP 0x00FF0000 /* Byte 2 Lower Half Port Mapping */
4846#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
4847#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
4848#define B3MAP 0xFF000000 /* Byte 3 Upper Half Port Mapping */
4849#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
4850#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
4851
4852/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
4853
4854#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
4855#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
4856#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
4857#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
4858#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
4859#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
4860#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
4861#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
4862
4863#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
4864#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
4865#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
4866#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
4867#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
4868#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
4869#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
4870#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
4871
4872#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
4873#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
4874#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
4875#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
4876#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
4877#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
4878#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
4879#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
4880
4881#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
4882#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
4883#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
4884#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
4885#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
4886#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
4887#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
4888#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
4889
4890
4891/* for legacy compatibility */
4892
4893#define WLS(x) (((x)-5) & 0x03) /* Word Length Select */
4894#define W1LMAX_MAX W1LMAX_MIN
4895#define EBIU_AMCBCTL0 EBIU_AMBCTL0
4896#define EBIU_AMCBCTL1 EBIU_AMBCTL1
4897#define PINT0_IRQ PINT0_REQUEST
4898#define PINT1_IRQ PINT1_REQUEST
4899#define PINT2_IRQ PINT2_REQUEST
4900#define PINT3_IRQ PINT3_REQUEST
4901
4902#endif /* _DEF_BF54X_H */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index a6de4c69ba55..89150ecb909d 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -904,23 +904,6 @@
904#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */ 904#define IWR_ENABLE(x) (1 << (x)) /* Wakeup Enable Peripheral #x */
905#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */ 905#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x))) /* Wakeup Disable Peripheral #x */
906 906
907/* ********* WATCHDOG TIMER MASKS ********************8 */
908
909/* Watchdog Timer WDOG_CTL Register */
910#define ICTL(x) ((x<<1) & 0x0006)
911#define ENABLE_RESET 0x00000000 /* Set Watchdog Timer to generate reset */
912#define ENABLE_NMI 0x00000002 /* Set Watchdog Timer to generate non-maskable interrupt */
913#define ENABLE_GPI 0x00000004 /* Set Watchdog Timer to generate general-purpose interrupt */
914#define DISABLE_EVT 0x00000006 /* Disable Watchdog Timer interrupts */
915
916#define TMR_EN 0x0000
917#define TMR_DIS 0x0AD0
918#define TRO 0x8000
919
920#define ICTL_P0 0x01
921#define ICTL_P1 0x02
922#define TRO_P 0x0F
923
924/* ***************************** UART CONTROLLER MASKS ********************** */ 907/* ***************************** UART CONTROLLER MASKS ********************** */
925 908
926/* UART_LCR Register */ 909/* UART_LCR Register */
@@ -1214,18 +1197,18 @@
1214#define TIMIL9 0x0002 1197#define TIMIL9 0x0002
1215#define TIMIL10 0x0004 1198#define TIMIL10 0x0004
1216#define TIMIL11 0x0008 1199#define TIMIL11 0x0008
1217#define TOVL_ERR0 0x00000010 1200#define TOVF_ERR0 0x00000010
1218#define TOVL_ERR1 0x00000020 1201#define TOVF_ERR1 0x00000020
1219#define TOVL_ERR2 0x00000040 1202#define TOVF_ERR2 0x00000040
1220#define TOVL_ERR3 0x00000080 1203#define TOVF_ERR3 0x00000080
1221#define TOVL_ERR4 0x00100000 1204#define TOVF_ERR4 0x00100000
1222#define TOVL_ERR5 0x00200000 1205#define TOVF_ERR5 0x00200000
1223#define TOVL_ERR6 0x00400000 1206#define TOVF_ERR6 0x00400000
1224#define TOVL_ERR7 0x00800000 1207#define TOVF_ERR7 0x00800000
1225#define TOVL_ERR8 0x0010 1208#define TOVF_ERR8 0x0010
1226#define TOVL_ERR9 0x0020 1209#define TOVF_ERR9 0x0020
1227#define TOVL_ERR10 0x0040 1210#define TOVF_ERR10 0x0040
1228#define TOVL_ERR11 0x0080 1211#define TOVF_ERR11 0x0080
1229#define TRUN0 0x00001000 1212#define TRUN0 0x00001000
1230#define TRUN1 0x00002000 1213#define TRUN1 0x00002000
1231#define TRUN2 0x00004000 1214#define TRUN2 0x00004000
@@ -1251,18 +1234,18 @@
1251#define TIMIL9_P 0x01 1234#define TIMIL9_P 0x01
1252#define TIMIL10_P 0x02 1235#define TIMIL10_P 0x02
1253#define TIMIL11_P 0x03 1236#define TIMIL11_P 0x03
1254#define TOVL_ERR0_P 0x04 1237#define TOVF_ERR0_P 0x04
1255#define TOVL_ERR1_P 0x05 1238#define TOVF_ERR1_P 0x05
1256#define TOVL_ERR2_P 0x06 1239#define TOVF_ERR2_P 0x06
1257#define TOVL_ERR3_P 0x07 1240#define TOVF_ERR3_P 0x07
1258#define TOVL_ERR4_P 0x14 1241#define TOVF_ERR4_P 0x14
1259#define TOVL_ERR5_P 0x15 1242#define TOVF_ERR5_P 0x15
1260#define TOVL_ERR6_P 0x16 1243#define TOVF_ERR6_P 0x16
1261#define TOVL_ERR7_P 0x17 1244#define TOVF_ERR7_P 0x17
1262#define TOVL_ERR8_P 0x04 1245#define TOVF_ERR8_P 0x04
1263#define TOVL_ERR9_P 0x05 1246#define TOVF_ERR9_P 0x05
1264#define TOVL_ERR10_P 0x06 1247#define TOVF_ERR10_P 0x06
1265#define TOVL_ERR11_P 0x07 1248#define TOVF_ERR11_P 0x07
1266#define TRUN0_P 0x0C 1249#define TRUN0_P 0x0C
1267#define TRUN1_P 0x0D 1250#define TRUN1_P 0x0D
1268#define TRUN2_P 0x0E 1251#define TRUN2_P 0x0E
@@ -1276,6 +1259,32 @@
1276#define TRUN10_P 0x0E 1259#define TRUN10_P 0x0E
1277#define TRUN11_P 0x0F 1260#define TRUN11_P 0x0F
1278 1261
1262/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
1263#define TOVL_ERR0 TOVF_ERR0
1264#define TOVL_ERR1 TOVF_ERR1
1265#define TOVL_ERR2 TOVF_ERR2
1266#define TOVL_ERR3 TOVF_ERR3
1267#define TOVL_ERR4 TOVF_ERR4
1268#define TOVL_ERR5 TOVF_ERR5
1269#define TOVL_ERR6 TOVF_ERR6
1270#define TOVL_ERR7 TOVF_ERR7
1271#define TOVL_ERR8 TOVF_ERR8
1272#define TOVL_ERR9 TOVF_ERR9
1273#define TOVL_ERR10 TOVF_ERR10
1274#define TOVL_ERR11 TOVF_ERR11
1275#define TOVL_ERR0_P TOVF_ERR0_P
1276#define TOVL_ERR1_P TOVF_ERR1_P
1277#define TOVL_ERR2_P TOVF_ERR2_P
1278#define TOVL_ERR3_P TOVF_ERR3_P
1279#define TOVL_ERR4_P TOVF_ERR4_P
1280#define TOVL_ERR5_P TOVF_ERR5_P
1281#define TOVL_ERR6_P TOVF_ERR6_P
1282#define TOVL_ERR7_P TOVF_ERR7_P
1283#define TOVL_ERR8_P TOVF_ERR8_P
1284#define TOVL_ERR9_P TOVF_ERR9_P
1285#define TOVL_ERR10_P TOVF_ERR10_P
1286#define TOVL_ERR11_P TOVF_ERR11_P
1287
1279/* TIMERx_CONFIG Registers */ 1288/* TIMERx_CONFIG Registers */
1280#define PWM_OUT 0x0001 1289#define PWM_OUT 0x0001
1281#define WDTH_CAP 0x0002 1290#define WDTH_CAP 0x0002
@@ -1700,18 +1709,4 @@
1700#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */ 1709#define SDEASE 0x00000010 /* SDRAM EAB sticky error status - W1C */
1701#define BGSTAT 0x00000020 /* Bus granted */ 1710#define BGSTAT 0x00000020 /* Bus granted */
1702 1711
1703/*VR_CTL Masks*/
1704#define WAKE 0x100
1705#define VLEV_6 0x60
1706#define VLEV_7 0x70
1707#define VLEV_8 0x80
1708#define VLEV_9 0x90
1709#define VLEV_10 0xA0
1710#define VLEV_11 0xB0
1711#define VLEV_12 0xC0
1712#define VLEV_13 0xD0
1713#define VLEV_14 0xE0
1714#define VLEV_15 0xF0
1715#define FREQ_3 0x03
1716
1717#endif /* _DEF_BF561_H */ 1712#endif /* _DEF_BF561_H */