Merge master.kernel.org:/home/rmk/linux-2.6-arm

6 files changed, 217 insertions, 1 deletions

diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
new file mode 100644
index 000000000000..ce1150d4438d
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * Peripheral Data Controller (PDC) registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_PDC_H
+#define AT91RM9200_PDC_H
+
+#define AT91_PDC_RPR            0x100   /* Receive Pointer Register */
+#define AT91_PDC_RCR            0x104   /* Receive Counter Register */
+#define AT91_PDC_TPR            0x108   /* Transmit Pointer Register */
+#define AT91_PDC_TCR            0x10c   /* Transmit Counter Register */
+#define AT91_PDC_RNPR           0x110   /* Receive Next Pointer Register */
+#define AT91_PDC_RNCR           0x114   /* Receive Next Counter Register */
+#define AT91_PDC_TNPR           0x118   /* Transmit Next Pointer Register */
+#define AT91_PDC_TNCR           0x11c   /* Transmit Next Counter Register */
+
+#define AT91_PDC_PTCR           0x120   /* Transfer Control Register */
+#define         AT91_PDC_RXTEN          (1 << 0)        /* Receiver Transfer Enable */
+#define         AT91_PDC_RXTDIS         (1 << 1)        /* Receiver Transfer Disable */
+#define         AT91_PDC_TXTEN          (1 << 8)        /* Transmitter Transfer Enable */
+#define         AT91_PDC_TXTDIS         (1 << 9)        /* Transmitter Transfer Disable */
+
+#define AT91_PDC_PTSR           0x124   /* Transfer Status Register */
+
+#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h b/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
new file mode 100644
index 000000000000..79f851e31b9c
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
@@ -0,0 +1,123 @@
+/*
+ * include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * USART registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_USART_H
+#define AT91RM9200_USART_H
+
+#define AT91_US_CR              0x00                    /* Control Register */
+#define         AT91_US_RSTRX           (1 <<  2)               /* Reset Receiver */
+#define         AT91_US_RSTTX           (1 <<  3)               /* Reset Transmitter */
+#define         AT91_US_RXEN            (1 <<  4)               /* Receiver Enable */
+#define         AT91_US_RXDIS           (1 <<  5)               /* Receiver Disable */
+#define         AT91_US_TXEN            (1 <<  6)               /* Transmitter Enable */
+#define         AT91_US_TXDIS           (1 <<  7)               /* Transmitter Disable */
+#define         AT91_US_RSTSTA          (1 <<  8)               /* Reset Status Bits */
+#define         AT91_US_STTBRK          (1 <<  9)               /* Start Break */
+#define         AT91_US_STPBRK          (1 << 10)               /* Stop Break */
+#define         AT91_US_STTTO           (1 << 11)               /* Start Time-out */
+#define         AT91_US_SENDA           (1 << 12)               /* Send Address */
+#define         AT91_US_RSTIT           (1 << 13)               /* Reset Iterations */
+#define         AT91_US_RSTNACK         (1 << 14)               /* Reset Non Acknowledge */
+#define         AT91_US_RETTO           (1 << 15)               /* Rearm Time-out */
+#define         AT91_US_DTREN           (1 << 16)               /* Data Terminal Ready Enable */
+#define         AT91_US_DTRDIS          (1 << 17)               /* Data Terminal Ready Disable */
+#define         AT91_US_RTSEN           (1 << 18)               /* Request To Send Enable */
+#define         AT91_US_RTSDIS          (1 << 19)               /* Request To Send Disable */
+
+#define AT91_US_MR              0x04                    /* Mode Register */
+#define         AT91_US_USMODE          (0xf <<  0)             /* Mode of the USART */
+#define                 AT91_US_USMODE_NORMAL           0
+#define                 AT91_US_USMODE_RS485            1
+#define                 AT91_US_USMODE_HWHS             2
+#define                 AT91_US_USMODE_MODEM            3
+#define                 AT91_US_USMODE_ISO7816_T0       4
+#define                 AT91_US_USMODE_ISO7816_T1       6
+#define                 AT91_US_USMODE_IRDA             8
+#define         AT91_US_USCLKS          (3   <<  4)             /* Clock Selection */
+#define         AT91_US_CHRL            (3   <<  6)             /* Character Length */
+#define                 AT91_US_CHRL_5                  (0 <<  6)
+#define                 AT91_US_CHRL_6                  (1 <<  6)
+#define                 AT91_US_CHRL_7                  (2 <<  6)
+#define                 AT91_US_CHRL_8                  (3 <<  6)
+#define         AT91_US_SYNC            (1 <<  8)               /* Synchronous Mode Select */
+#define         AT91_US_PAR             (7 <<  9)               /* Parity Type */
+#define                 AT91_US_PAR_EVEN                (0 <<  9)
+#define                 AT91_US_PAR_ODD                 (1 <<  9)
+#define                 AT91_US_PAR_SPACE               (2 <<  9)
+#define                 AT91_US_PAR_MARK                (3 <<  9)
+#define                 AT91_US_PAR_NONE                (4 <<  9)
+#define                 AT91_US_PAR_MULTI_DROP          (6 <<  9)
+#define         AT91_US_NBSTOP          (3 << 12)               /* Number of Stop Bits */
+#define                 AT91_US_NBSTOP_1                (0 << 12)
+#define                 AT91_US_NBSTOP_1_5              (1 << 12)
+#define                 AT91_US_NBSTOP_2                (2 << 12)
+#define         AT91_US_CHMODE          (3 << 14)               /* Channel Mode */
+#define                 AT91_US_CHMODE_NORMAL           (0 << 14)
+#define                 AT91_US_CHMODE_ECHO             (1 << 14)
+#define                 AT91_US_CHMODE_LOC_LOOP         (2 << 14)
+#define                 AT91_US_CHMODE_REM_LOOP         (3 << 14)
+#define         AT91_US_MSBF            (1 << 16)               /* Bit Order */
+#define         AT91_US_MODE9           (1 << 17)               /* 9-bit Character Length */
+#define         AT91_US_CLKO            (1 << 18)               /* Clock Output Select */
+#define         AT91_US_OVER            (1 << 19)               /* Oversampling Mode */
+#define         AT91_US_INACK           (1 << 20)               /* Inhibit Non Acknowledge */
+#define         AT91_US_DSNACK          (1 << 21)               /* Disable Successive NACK */
+#define         AT91_US_MAX_ITER        (7 << 24)               /* Max Iterations */
+#define         AT91_US_FILTER          (1 << 28)               /* Infrared Receive Line Filter */
+
+#define AT91_US_IER             0x08                    /* Interrupt Enable Register */
+#define         AT91_US_RXRDY           (1 <<  0)               /* Receiver Ready */
+#define         AT91_US_TXRDY           (1 <<  1)               /* Transmitter Ready */
+#define         AT91_US_RXBRK           (1 <<  2)               /* Break Received / End of Break */
+#define         AT91_US_ENDRX           (1 <<  3)               /* End of Receiver Transfer */
+#define         AT91_US_ENDTX           (1 <<  4)               /* End of Transmitter Transfer */
+#define         AT91_US_OVRE            (1 <<  5)               /* Overrun Error */
+#define         AT91_US_FRAME           (1 <<  6)               /* Framing Error */
+#define         AT91_US_PARE            (1 <<  7)               /* Parity Error */
+#define         AT91_US_TIMEOUT         (1 <<  8)               /* Receiver Time-out */
+#define         AT91_US_TXEMPTY         (1 <<  9)               /* Transmitter Empty */
+#define         AT91_US_ITERATION       (1 << 10)               /* Max number of Repetitions Reached */
+#define         AT91_US_TXBUFE          (1 << 11)               /* Transmission Buffer Empty */
+#define         AT91_US_RXBUFF          (1 << 12)               /* Reception Buffer Full */
+#define         AT91_US_NACK            (1 << 13)               /* Non Acknowledge */
+#define         AT91_US_RIIC            (1 << 16)               /* Ring Indicator Input Change */
+#define         AT91_US_DSRIC           (1 << 17)               /* Data Set Ready Input Change */
+#define         AT91_US_DCDIC           (1 << 18)               /* Data Carrier Detect Input Change */
+#define         AT91_US_CTSIC           (1 << 19)               /* Clear to Send Input Change */
+#define         AT91_US_RI              (1 << 20)               /* RI */
+#define         AT91_US_DSR             (1 << 21)               /* DSR */
+#define         AT91_US_DCD             (1 << 22)               /* DCD */
+#define         AT91_US_CTS             (1 << 23)               /* CTS */
+
+#define AT91_US_IDR             0x0c                    /* Interrupt Disable Register */
+#define AT91_US_IMR             0x10                    /* Interrupt Mask Register */
+#define AT91_US_CSR             0x14                    /* Channel Status Register */
+#define AT91_US_RHR             0x18                    /* Receiver Holding Register */
+#define AT91_US_THR             0x1c                    /* Transmitter Holding Register */
+
+#define AT91_US_BRGR            0x20                    /* Baud Rate Generator Register */
+#define         AT91_US_CD              (0xffff << 0)           /* Clock Divider */
+
+#define AT91_US_RTOR            0x24                    /* Receiver Time-out Register */
+#define         AT91_US_TO              (0xffff << 0)           /* Time-out Value */
+
+#define AT91_US_TTGR            0x28                    /* Transmitter Timeguard Register */
+#define         AT91_US_TG              (0xff << 0)             /* Timeguard Value */
+
+#define AT91_US_FIDI            0x40                    /* FI DI Ratio Register */
+#define AT91_US_NER             0x44                    /* Number of Errors Register */
+#define AT91_US_IF              0x4c                    /* IrDA Filter Register */
+
+#endif
diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h
index 741f5bc5d016..17eaf8bdf092 100644
--- a/include/asm-arm/byteorder.h
+++ b/include/asm-arm/byteorder.h
@@ -22,7 +22,16 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
 {
         __u32 t;
 
-        t = x ^ ((x << 16) | (x >> 16));        /* eor r1,r0,r0,ror #16  */
+        if (__builtin_constant_p(x)) {
+                t = x ^ ((x << 16) | (x >> 16)); /* eor r1,r0,r0,ror #16 */
+        } else {
+                /*
+                 * The compiler needs a bit of a hint here to always do the
+                 * right thing and not screw it up to different degrees
+                 * depending on the gcc version.
+                 */
+                asm ("eor\t%0, %1, %1, ror #16" : "=r" (t) : "r" (x));
+        }
         x = (x << 24) | (x >> 8);               /* mov r0,r0,ror #8      */
         t &= ~0x00FF0000;                       /* bic r1,r1,#0x00FF0000 */
         x ^= (t >> 8);                          /* eor r0,r0,r1,lsr #8   */
diff --git a/include/asm-arm/mach/serial_at91rm9200.h b/include/asm-arm/mach/serial_at91rm9200.h
new file mode 100644
index 000000000000..98f4b0cb883c
--- /dev/null
+++ b/include/asm-arm/mach/serial_at91rm9200.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/mach/serial_at91rm9200.h
+ *
+ *  Based on serial_sa1100.h  by Nicolas Pitre
+ *
+ *  Copyright (C) 2002 ATMEL Rousset
+ *
+ *  Low level machine dependent UART functions.
+ */
+#include <linux/config.h>
+
+struct uart_port;
+
+/*
+ * This is a temporary structure for registering these
+ * functions; it is intended to be discarded after boot.
+ */
+struct at91rm9200_port_fns {
+        void    (*set_mctrl)(struct uart_port *, u_int);
+        u_int   (*get_mctrl)(struct uart_port *);
+        void    (*enable_ms)(struct uart_port *);
+        void    (*pm)(struct uart_port *, u_int, u_int);
+        int     (*set_wake)(struct uart_port *, u_int);
+        int     (*open)(struct uart_port *);
+        void    (*close)(struct uart_port *);
+};
+
+#if defined(CONFIG_SERIAL_AT91)
+void at91_register_uart_fns(struct at91rm9200_port_fns *fns);
+void at91_register_uart(int idx, int port);
+#else
+#define at91_register_uart_fns(fns) do { } while (0)
+#define at91_register_uart(idx,port) do { } while (0)
+#endif
+
+
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
index 3d7f08bd9030..b4e1146ab682 100644
--- a/include/asm-arm/memory.h
+++ b/include/asm-arm/memory.h
@@ -25,6 +25,7 @@
 #include <linux/config.h>
 #include <linux/compiler.h>
 #include <asm/arch/memory.h>
+#include <asm/sizes.h>
 
 #ifndef TASK_SIZE
 /*
@@ -48,6 +49,14 @@
 #endif
 
 /*
+ * Size of DMA-consistent memory region.  Must be multiple of 2M,
+ * between 2MB and 14MB inclusive.
+ */
+#ifndef CONSISTENT_DMA_SIZE
+#define CONSISTENT_DMA_SIZE SZ_2M
+#endif
+
+/*
  * Physical vs virtual RAM address space conversion.  These are
  * private definitions which should NOT be used outside memory.h
  * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index e3710d7e260a..a8187c3c8a7b 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -67,6 +67,9 @@
 /* Parisc type numbers. */
 #define PORT_MUX        48
 
+/* Atmel AT91RM9200 SoC */
+#define PORT_AT91RM9200 49
+
 /* Macintosh Zilog type numbers */
 #define PORT_MAC_ZILOG  50      /* m68k : not yet implemented */
 #define PORT_PMAC_ZILOG 51