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authorHauke Mehrtens <hauke@hauke-m.de>2012-06-29 19:44:41 -0400
committerJohn W. Linville <linville@tuxdriver.com>2012-07-09 16:36:04 -0400
commitb9562545ef0b13c0440ccd8d6dd4111fb77cb17a (patch)
treedadc32d04a6be328ec69c3ab6e6199e110f1e2dd /include
parent02817be0b2cd42412cf3c09f8f1667f39b6d020d (diff)
bcma: complete workaround for BCMA43224 and BCM4313
This code is based on the Broadcom SDK and brcmsmac. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/bcma/bcma_driver_chipcommon.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/include/linux/bcma/bcma_driver_chipcommon.h b/include/linux/bcma/bcma_driver_chipcommon.h
index 1e523cc61860..09f31ade1410 100644
--- a/include/linux/bcma/bcma_driver_chipcommon.h
+++ b/include/linux/bcma/bcma_driver_chipcommon.h
@@ -325,6 +325,14 @@
325#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */ 325#define BCMA_CHIPCTL_4331_BT_SHD0_ON_GPIO4 BIT(16) /* enable bt_shd0 at gpio4 */
326#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */ 326#define BCMA_CHIPCTL_4331_BT_SHD1_ON_GPIO5 BIT(17) /* enable bt_shd1 at gpio5 */
327 327
328/* 43224 chip-specific ChipControl register bits */
329#define BCMA_CCTRL_43224_GPIO_TOGGLE 0x8000 /* gpio[3:0] pins as btcoex or s/w gpio */
330#define BCMA_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */
331#define BCMA_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */
332
333/* 4313 Chip specific ChipControl register bits */
334#define BCMA_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */
335
328/* Data for the PMU, if available. 336/* Data for the PMU, if available.
329 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU) 337 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
330 */ 338 */