Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

535 files changed, 1513 insertions, 76281 deletions

diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h
index 9ed70a050580..c34008507b69 100644
--- a/include/acpi/acnamesp.h
+++ b/include/acpi/acnamesp.h
@@ -182,7 +182,7 @@ acpi_status acpi_ns_evaluate(struct acpi_evaluate_info *info);
  */
 u32 acpi_ns_opens_scope(acpi_object_type type);
 
-void
+acpi_status
 acpi_ns_build_external_path(struct acpi_namespace_node *node,
                             acpi_size size, char *name_buffer);
 
diff --git a/include/asm-alpha/8253pit.h b/include/asm-alpha/8253pit.h
deleted file mode 100644
index fef5c1450e47..000000000000
--- a/include/asm-alpha/8253pit.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * 8253/8254 Programmable Interval Timer
- */
-
-#ifndef _8253PIT_H
-#define _8253PIT_H
-
-#define PIT_TICK_RATE   1193180UL
-
-#endif
diff --git a/include/asm-alpha/Kbuild b/include/asm-alpha/Kbuild
deleted file mode 100644
index b7c8f188b313..000000000000
--- a/include/asm-alpha/Kbuild
+++ /dev/null
@@ -1,11 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += gentrap.h
-header-y += regdef.h
-header-y += pal.h
-header-y += reg.h
-
-unifdef-y += console.h
-unifdef-y += fpu.h
-unifdef-y += sysinfo.h
-unifdef-y += compiler.h
diff --git a/include/asm-alpha/a.out-core.h b/include/asm-alpha/a.out-core.h
deleted file mode 100644
index 9e33e92e524c..000000000000
--- a/include/asm-alpha/a.out-core.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/* a.out coredump register dumper
- *
- * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
- * Written by David Howells (dhowells@redhat.com)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public Licence
- * as published by the Free Software Foundation; either version
- * 2 of the Licence, or (at your option) any later version.
- */
-
-#ifndef _ASM_A_OUT_CORE_H
-#define _ASM_A_OUT_CORE_H
-
-#ifdef __KERNEL__
-
-#include <linux/user.h>
-
-/*
- * Fill in the user structure for an ECOFF core dump.
- */
-static inline void aout_dump_thread(struct pt_regs *pt, struct user *dump)
-{
-        /* switch stack follows right below pt_regs: */
-        struct switch_stack * sw = ((struct switch_stack *) pt) - 1;
-
-        dump->magic = CMAGIC;
-        dump->start_code  = current->mm->start_code;
-        dump->start_data  = current->mm->start_data;
-        dump->start_stack = rdusp() & ~(PAGE_SIZE - 1);
-        dump->u_tsize = ((current->mm->end_code - dump->start_code)
-                         >> PAGE_SHIFT);
-        dump->u_dsize = ((current->mm->brk + PAGE_SIZE-1 - dump->start_data)
-                         >> PAGE_SHIFT);
-        dump->u_ssize = (current->mm->start_stack - dump->start_stack
-                         + PAGE_SIZE-1) >> PAGE_SHIFT;
-
-        /*
-         * We store the registers in an order/format that is
-         * compatible with DEC Unix/OSF/1 as this makes life easier
-         * for gdb.
-         */
-        dump->regs[EF_V0]  = pt->r0;
-        dump->regs[EF_T0]  = pt->r1;
-        dump->regs[EF_T1]  = pt->r2;
-        dump->regs[EF_T2]  = pt->r3;
-        dump->regs[EF_T3]  = pt->r4;
-        dump->regs[EF_T4]  = pt->r5;
-        dump->regs[EF_T5]  = pt->r6;
-        dump->regs[EF_T6]  = pt->r7;
-        dump->regs[EF_T7]  = pt->r8;
-        dump->regs[EF_S0]  = sw->r9;
-        dump->regs[EF_S1]  = sw->r10;
-        dump->regs[EF_S2]  = sw->r11;
-        dump->regs[EF_S3]  = sw->r12;
-        dump->regs[EF_S4]  = sw->r13;
-        dump->regs[EF_S5]  = sw->r14;
-        dump->regs[EF_S6]  = sw->r15;
-        dump->regs[EF_A3]  = pt->r19;
-        dump->regs[EF_A4]  = pt->r20;
-        dump->regs[EF_A5]  = pt->r21;
-        dump->regs[EF_T8]  = pt->r22;
-        dump->regs[EF_T9]  = pt->r23;
-        dump->regs[EF_T10] = pt->r24;
-        dump->regs[EF_T11] = pt->r25;
-        dump->regs[EF_RA]  = pt->r26;
-        dump->regs[EF_T12] = pt->r27;
-        dump->regs[EF_AT]  = pt->r28;
-        dump->regs[EF_SP]  = rdusp();
-        dump->regs[EF_PS]  = pt->ps;
-        dump->regs[EF_PC]  = pt->pc;
-        dump->regs[EF_GP]  = pt->gp;
-        dump->regs[EF_A0]  = pt->r16;
-        dump->regs[EF_A1]  = pt->r17;
-        dump->regs[EF_A2]  = pt->r18;
-        memcpy((char *)dump->regs + EF_SIZE, sw->fp, 32 * 8);
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_A_OUT_CORE_H */
diff --git a/include/asm-alpha/a.out.h b/include/asm-alpha/a.out.h
deleted file mode 100644
index 02ce8473870a..000000000000
--- a/include/asm-alpha/a.out.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef __ALPHA_A_OUT_H__
-#define __ALPHA_A_OUT_H__
-
-#include <linux/types.h>
-
-/*
- * OSF/1 ECOFF header structs.  ECOFF files consist of:
- *      - a file header (struct filehdr),
- *      - an a.out header (struct aouthdr),
- *      - one or more section headers (struct scnhdr). 
- *        The filhdr's "f_nscns" field contains the
- *        number of section headers.
- */
-
-struct filehdr
-{
-        /* OSF/1 "file" header */
-        __u16 f_magic, f_nscns;
-        __u32 f_timdat;
-        __u64 f_symptr;
-        __u32 f_nsyms;
-        __u16 f_opthdr, f_flags;
-};
-
-struct aouthdr
-{
-        __u64 info;             /* after that it looks quite normal.. */
-        __u64 tsize;
-        __u64 dsize;
-        __u64 bsize;
-        __u64 entry;
-        __u64 text_start;       /* with a few additions that actually make sense */
-        __u64 data_start;
-        __u64 bss_start;
-        __u32 gprmask, fprmask; /* bitmask of general & floating point regs used in binary */
-        __u64 gpvalue;
-};
-
-struct scnhdr
-{
-        char    s_name[8];
-        __u64   s_paddr;
-        __u64   s_vaddr;
-        __u64   s_size;
-        __u64   s_scnptr;
-        __u64   s_relptr;
-        __u64   s_lnnoptr;
-        __u16   s_nreloc;
-        __u16   s_nlnno;
-        __u32   s_flags;
-};
-
-struct exec
-{
-        /* OSF/1 "file" header */
-        struct filehdr          fh;
-        struct aouthdr          ah;
-};
-
-/*
- * Define's so that the kernel exec code can access the a.out header
- * fields...
- */
-#define a_info          ah.info
-#define a_text          ah.tsize
-#define a_data          ah.dsize
-#define a_bss           ah.bsize
-#define a_entry         ah.entry
-#define a_textstart     ah.text_start
-#define a_datastart     ah.data_start
-#define a_bssstart      ah.bss_start
-#define a_gprmask       ah.gprmask
-#define a_fprmask       ah.fprmask
-#define a_gpvalue       ah.gpvalue
-
-#define N_TXTADDR(x) ((x).a_textstart)
-#define N_DATADDR(x) ((x).a_datastart)
-#define N_BSSADDR(x) ((x).a_bssstart)
-#define N_DRSIZE(x) 0
-#define N_TRSIZE(x) 0
-#define N_SYMSIZE(x) 0
-
-#define AOUTHSZ         sizeof(struct aouthdr)
-#define SCNHSZ          sizeof(struct scnhdr)
-#define SCNROUND        16
-
-#define N_TXTOFF(x) \
-  ((long) N_MAGIC(x) == ZMAGIC ? 0 : \
-   (sizeof(struct exec) + (x).fh.f_nscns*SCNHSZ + SCNROUND - 1) & ~(SCNROUND - 1))
-
-#ifdef __KERNEL__
-
-/* Assume that start addresses below 4G belong to a TASO application.
-   Unfortunately, there is no proper bit in the exec header to check.
-   Worse, we have to notice the start address before swapping to use
-   /sbin/loader, which of course is _not_ a TASO application.  */
-#define SET_AOUT_PERSONALITY(BFPM, EX) \
-        set_personality (((BFPM->sh_bang || EX.ah.entry < 0x100000000L \
-                           ? ADDR_LIMIT_32BIT : 0) | PER_OSF4))
-
-#endif /* __KERNEL__ */
-#endif /* __A_OUT_GNU_H__ */
diff --git a/include/asm-alpha/agp.h b/include/asm-alpha/agp.h
deleted file mode 100644
index 26c179135293..000000000000
--- a/include/asm-alpha/agp.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef AGP_H
-#define AGP_H 1
-
-#include <asm/io.h>
-
-/* dummy for now */
-
-#define map_page_into_agp(page) 
-#define unmap_page_from_agp(page) 
-#define flush_agp_cache() mb()
-
-/* Convert a physical address to an address suitable for the GART. */
-#define phys_to_gart(x) (x)
-#define gart_to_phys(x) (x)
-
-/* GATT allocation. Returns/accepts GATT kernel virtual address. */
-#define alloc_gatt_pages(order)         \
-        ((char *)__get_free_pages(GFP_KERNEL, (order)))
-#define free_gatt_pages(table, order)   \
-        free_pages((unsigned long)(table), (order))
-
-#endif
diff --git a/include/asm-alpha/agp_backend.h b/include/asm-alpha/agp_backend.h
deleted file mode 100644
index 55dd44a2cea7..000000000000
--- a/include/asm-alpha/agp_backend.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _ALPHA_AGP_BACKEND_H
-#define _ALPHA_AGP_BACKEND_H 1
-
-typedef union _alpha_agp_mode {
-        struct {
-                u32 rate : 3;
-                u32 reserved0 : 1;
-                u32 fw : 1;
-                u32 fourgb : 1;
-                u32 reserved1 : 2;
-                u32 enable : 1;
-                u32 sba : 1;
-                u32 reserved2 : 14;
-                u32 rq : 8;
-        } bits;
-        u32 lw;
-} alpha_agp_mode;
-
-typedef struct _alpha_agp_info {
-        struct pci_controller *hose;
-        struct {
-                dma_addr_t bus_base;
-                unsigned long size;
-                void *sysdata;
-        } aperture;
-        alpha_agp_mode capability;
-        alpha_agp_mode mode;
-        void *private;
-        struct alpha_agp_ops *ops;
-} alpha_agp_info;
-
-struct alpha_agp_ops {
-        int (*setup)(alpha_agp_info *);
-        void (*cleanup)(alpha_agp_info *);
-        int (*configure)(alpha_agp_info *);
-        int (*bind)(alpha_agp_info *, off_t, struct agp_memory *);
-        int (*unbind)(alpha_agp_info *, off_t, struct agp_memory *);
-        unsigned long (*translate)(alpha_agp_info *, dma_addr_t);
-};
-
-
-#endif /* _ALPHA_AGP_BACKEND_H */
diff --git a/include/asm-alpha/atomic.h b/include/asm-alpha/atomic.h
deleted file mode 100644
index ca88e54dec93..000000000000
--- a/include/asm-alpha/atomic.h
+++ /dev/null
@@ -1,267 +0,0 @@
-#ifndef _ALPHA_ATOMIC_H
-#define _ALPHA_ATOMIC_H
-
-#include <asm/barrier.h>
-#include <asm/system.h>
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc...
- *
- * But use these as seldom as possible since they are much slower
- * than regular operations.
- */
-
-
-/*
- * Counter is volatile to make sure gcc doesn't try to be clever
- * and move things around on us. We need to use _exactly_ the address
- * the user gave us, not some alias that contains the same information.
- */
-typedef struct { volatile int counter; } atomic_t;
-typedef struct { volatile long counter; } atomic64_t;
-
-#define ATOMIC_INIT(i)          ( (atomic_t) { (i) } )
-#define ATOMIC64_INIT(i)        ( (atomic64_t) { (i) } )
-
-#define atomic_read(v)          ((v)->counter + 0)
-#define atomic64_read(v)        ((v)->counter + 0)
-
-#define atomic_set(v,i)         ((v)->counter = (i))
-#define atomic64_set(v,i)       ((v)->counter = (i))
-
-/*
- * To get proper branch prediction for the main line, we must branch
- * forward to code at the end of this object's .text section, then
- * branch back to restart the operation.
- */
-
-static __inline__ void atomic_add(int i, atomic_t * v)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%1\n"
-        "       addl %0,%2,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter)
-        :"Ir" (i), "m" (v->counter));
-}
-
-static __inline__ void atomic64_add(long i, atomic64_t * v)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%1\n"
-        "       addq %0,%2,%0\n"
-        "       stq_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter)
-        :"Ir" (i), "m" (v->counter));
-}
-
-static __inline__ void atomic_sub(int i, atomic_t * v)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%1\n"
-        "       subl %0,%2,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter)
-        :"Ir" (i), "m" (v->counter));
-}
-
-static __inline__ void atomic64_sub(long i, atomic64_t * v)
-{
-        unsigned long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%1\n"
-        "       subq %0,%2,%0\n"
-        "       stq_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter)
-        :"Ir" (i), "m" (v->counter));
-}
-
-
-/*
- * Same as above, but return the result value
- */
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-        long temp, result;
-        smp_mb();
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%1\n"
-        "       addl %0,%3,%2\n"
-        "       addl %0,%3,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter), "=&r" (result)
-        :"Ir" (i), "m" (v->counter) : "memory");
-        smp_mb();
-        return result;
-}
-
-static __inline__ long atomic64_add_return(long i, atomic64_t * v)
-{
-        long temp, result;
-        smp_mb();
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%1\n"
-        "       addq %0,%3,%2\n"
-        "       addq %0,%3,%0\n"
-        "       stq_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter), "=&r" (result)
-        :"Ir" (i), "m" (v->counter) : "memory");
-        smp_mb();
-        return result;
-}
-
-static __inline__ long atomic_sub_return(int i, atomic_t * v)
-{
-        long temp, result;
-        smp_mb();
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%1\n"
-        "       subl %0,%3,%2\n"
-        "       subl %0,%3,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter), "=&r" (result)
-        :"Ir" (i), "m" (v->counter) : "memory");
-        smp_mb();
-        return result;
-}
-
-static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
-{
-        long temp, result;
-        smp_mb();
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%1\n"
-        "       subq %0,%3,%2\n"
-        "       subq %0,%3,%0\n"
-        "       stq_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (v->counter), "=&r" (result)
-        :"Ir" (i), "m" (v->counter) : "memory");
-        smp_mb();
-        return result;
-}
-
-#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
-
-#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int c, old;
-        c = atomic_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
-        long c, old;
-        c = atomic64_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic64_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
-#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
-
-#define atomic_dec_return(v) atomic_sub_return(1,(v))
-#define atomic64_dec_return(v) atomic64_sub_return(1,(v))
-
-#define atomic_inc_return(v) atomic_add_return(1,(v))
-#define atomic64_inc_return(v) atomic64_add_return(1,(v))
-
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
-
-#define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
-#define atomic64_inc_and_test(v) (atomic64_add_return(1, (v)) == 0)
-
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
-
-#define atomic_inc(v) atomic_add(1,(v))
-#define atomic64_inc(v) atomic64_add(1,(v))
-
-#define atomic_dec(v) atomic_sub(1,(v))
-#define atomic64_dec(v) atomic64_sub(1,(v))
-
-#define smp_mb__before_atomic_dec()     smp_mb()
-#define smp_mb__after_atomic_dec()      smp_mb()
-#define smp_mb__before_atomic_inc()     smp_mb()
-#define smp_mb__after_atomic_inc()      smp_mb()
-
-#include <asm-generic/atomic.h>
-#endif /* _ALPHA_ATOMIC_H */
diff --git a/include/asm-alpha/auxvec.h b/include/asm-alpha/auxvec.h
deleted file mode 100644
index e96fe880e310..000000000000
--- a/include/asm-alpha/auxvec.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __ASM_ALPHA_AUXVEC_H
-#define __ASM_ALPHA_AUXVEC_H
-
-/* Reserve these numbers for any future use of a VDSO.  */
-#if 0
-#define AT_SYSINFO              32
-#define AT_SYSINFO_EHDR         33
-#endif
-
-/* More complete cache descriptions than AT_[DIU]CACHEBSIZE.  If the
-   value is -1, then the cache doesn't exist.  Otherwise:
-
-      bit 0-3:    Cache set-associativity; 0 means fully associative.
-      bit 4-7:    Log2 of cacheline size.
-      bit 8-31:   Size of the entire cache >> 8.
-      bit 32-63:  Reserved.
-*/
-
-#define AT_L1I_CACHESHAPE       34
-#define AT_L1D_CACHESHAPE       35
-#define AT_L2_CACHESHAPE        36
-#define AT_L3_CACHESHAPE        37
-
-#endif /* __ASM_ALPHA_AUXVEC_H */
diff --git a/include/asm-alpha/barrier.h b/include/asm-alpha/barrier.h
deleted file mode 100644
index ac78eba909bc..000000000000
--- a/include/asm-alpha/barrier.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __BARRIER_H
-#define __BARRIER_H
-
-#include <asm/compiler.h>
-
-#define mb() \
-__asm__ __volatile__("mb": : :"memory")
-
-#define rmb() \
-__asm__ __volatile__("mb": : :"memory")
-
-#define wmb() \
-__asm__ __volatile__("wmb": : :"memory")
-
-#define read_barrier_depends() \
-__asm__ __volatile__("mb": : :"memory")
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while (0)
-#endif
-
-#define set_mb(var, value) \
-do { var = value; mb(); } while (0)
-
-#endif          /* __BARRIER_H */
diff --git a/include/asm-alpha/bitops.h b/include/asm-alpha/bitops.h
deleted file mode 100644
index 15f3ae25c511..000000000000
--- a/include/asm-alpha/bitops.h
+++ /dev/null
@@ -1,466 +0,0 @@
-#ifndef _ALPHA_BITOPS_H
-#define _ALPHA_BITOPS_H
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm/compiler.h>
-#include <asm/barrier.h>
-
-/*
- * Copyright 1994, Linus Torvalds.
- */
-
-/*
- * These have to be done with inline assembly: that way the bit-setting
- * is guaranteed to be atomic. All bit operations return 0 if the bit
- * was cleared before the operation and != 0 if it was not.
- *
- * To get proper branch prediction for the main line, we must branch
- * forward to code at the end of this object's .text section, then
- * branch back to restart the operation.
- *
- * bit 0 is the LSB of addr; bit 64 is the LSB of (addr+1).
- */
-
-static inline void
-set_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%3\n"
-        "       bis %0,%2,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m)
-        :"Ir" (1UL << (nr & 31)), "m" (*m));
-}
-
-/*
- * WARNING: non atomic version.
- */
-static inline void
-__set_bit(unsigned long nr, volatile void * addr)
-{
-        int *m = ((int *) addr) + (nr >> 5);
-
-        *m |= 1 << (nr & 31);
-}
-
-#define smp_mb__before_clear_bit()      smp_mb()
-#define smp_mb__after_clear_bit()       smp_mb()
-
-static inline void
-clear_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%3\n"
-        "       bic %0,%2,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m)
-        :"Ir" (1UL << (nr & 31)), "m" (*m));
-}
-
-static inline void
-clear_bit_unlock(unsigned long nr, volatile void * addr)
-{
-        smp_mb();
-        clear_bit(nr, addr);
-}
-
-/*
- * WARNING: non atomic version.
- */
-static __inline__ void
-__clear_bit(unsigned long nr, volatile void * addr)
-{
-        int *m = ((int *) addr) + (nr >> 5);
-
-        *m &= ~(1 << (nr & 31));
-}
-
-static inline void
-__clear_bit_unlock(unsigned long nr, volatile void * addr)
-{
-        smp_mb();
-        __clear_bit(nr, addr);
-}
-
-static inline void
-change_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%3\n"
-        "       xor %0,%2,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m)
-        :"Ir" (1UL << (nr & 31)), "m" (*m));
-}
-
-/*
- * WARNING: non atomic version.
- */
-static __inline__ void
-__change_bit(unsigned long nr, volatile void * addr)
-{
-        int *m = ((int *) addr) + (nr >> 5);
-
-        *m ^= 1 << (nr & 31);
-}
-
-static inline int
-test_and_set_bit(unsigned long nr, volatile void *addr)
-{
-        unsigned long oldbit;
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "1:     ldl_l %0,%4\n"
-        "       and %0,%3,%2\n"
-        "       bne %2,2f\n"
-        "       xor %0,%3,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,3f\n"
-        "2:\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m), "=&r" (oldbit)
-        :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
-
-        return oldbit != 0;
-}
-
-static inline int
-test_and_set_bit_lock(unsigned long nr, volatile void *addr)
-{
-        unsigned long oldbit;
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%4\n"
-        "       and %0,%3,%2\n"
-        "       bne %2,2f\n"
-        "       xor %0,%3,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,3f\n"
-        "2:\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m), "=&r" (oldbit)
-        :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
-
-        return oldbit != 0;
-}
-
-/*
- * WARNING: non atomic version.
- */
-static inline int
-__test_and_set_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        int *m = ((int *) addr) + (nr >> 5);
-        int old = *m;
-
-        *m = old | mask;
-        return (old & mask) != 0;
-}
-
-static inline int
-test_and_clear_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long oldbit;
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "1:     ldl_l %0,%4\n"
-        "       and %0,%3,%2\n"
-        "       beq %2,2f\n"
-        "       xor %0,%3,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,3f\n"
-        "2:\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m), "=&r" (oldbit)
-        :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
-
-        return oldbit != 0;
-}
-
-/*
- * WARNING: non atomic version.
- */
-static inline int
-__test_and_clear_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        int *m = ((int *) addr) + (nr >> 5);
-        int old = *m;
-
-        *m = old & ~mask;
-        return (old & mask) != 0;
-}
-
-static inline int
-test_and_change_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long oldbit;
-        unsigned long temp;
-        int *m = ((int *) addr) + (nr >> 5);
-
-        __asm__ __volatile__(
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "1:     ldl_l %0,%4\n"
-        "       and %0,%3,%2\n"
-        "       xor %0,%3,%0\n"
-        "       stl_c %0,%1\n"
-        "       beq %0,3f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (*m), "=&r" (oldbit)
-        :"Ir" (1UL << (nr & 31)), "m" (*m) : "memory");
-
-        return oldbit != 0;
-}
-
-/*
- * WARNING: non atomic version.
- */
-static __inline__ int
-__test_and_change_bit(unsigned long nr, volatile void * addr)
-{
-        unsigned long mask = 1 << (nr & 0x1f);
-        int *m = ((int *) addr) + (nr >> 5);
-        int old = *m;
-
-        *m = old ^ mask;
-        return (old & mask) != 0;
-}
-
-static inline int
-test_bit(int nr, const volatile void * addr)
-{
-        return (1UL & (((const int *) addr)[nr >> 5] >> (nr & 31))) != 0UL;
-}
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- *
- * Do a binary search on the bits.  Due to the nature of large
- * constants on the alpha, it is worthwhile to split the search.
- */
-static inline unsigned long ffz_b(unsigned long x)
-{
-        unsigned long sum, x1, x2, x4;
-
-        x = ~x & -~x;           /* set first 0 bit, clear others */
-        x1 = x & 0xAA;
-        x2 = x & 0xCC;
-        x4 = x & 0xF0;
-        sum = x2 ? 2 : 0;
-        sum += (x4 != 0) * 4;
-        sum += (x1 != 0);
-
-        return sum;
-}
-
-static inline unsigned long ffz(unsigned long word)
-{
-#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
-        /* Whee.  EV67 can calculate it directly.  */
-        return __kernel_cttz(~word);
-#else
-        unsigned long bits, qofs, bofs;
-
-        bits = __kernel_cmpbge(word, ~0UL);
-        qofs = ffz_b(bits);
-        bits = __kernel_extbl(word, qofs);
-        bofs = ffz_b(bits);
-
-        return qofs*8 + bofs;
-#endif
-}
-
-/*
- * __ffs = Find First set bit in word.  Undefined if no set bit exists.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
-#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
-        /* Whee.  EV67 can calculate it directly.  */
-        return __kernel_cttz(word);
-#else
-        unsigned long bits, qofs, bofs;
-
-        bits = __kernel_cmpbge(0, word);
-        qofs = ffz_b(bits);
-        bits = __kernel_extbl(word, qofs);
-        bofs = ffz_b(~bits);
-
-        return qofs*8 + bofs;
-#endif
-}
-
-#ifdef __KERNEL__
-
-/*
- * ffs: find first bit set. This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above __ffs.
- */
-
-static inline int ffs(int word)
-{
-        int result = __ffs(word) + 1;
-        return word ? result : 0;
-}
-
-/*
- * fls: find last bit set.
- */
-#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
-static inline int fls64(unsigned long word)
-{
-        return 64 - __kernel_ctlz(word);
-}
-#else
-extern const unsigned char __flsm1_tab[256];
-
-static inline int fls64(unsigned long x)
-{
-        unsigned long t, a, r;
-
-        t = __kernel_cmpbge (x, 0x0101010101010101UL);
-        a = __flsm1_tab[t];
-        t = __kernel_extbl (x, a);
-        r = a*8 + __flsm1_tab[t] + (x != 0);
-
-        return r;
-}
-#endif
-
-static inline unsigned long __fls(unsigned long x)
-{
-        return fls64(x) - 1;
-}
-
-static inline int fls(int x)
-{
-        return fls64((unsigned int) x);
-}
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#if defined(CONFIG_ALPHA_EV6) && defined(CONFIG_ALPHA_EV67)
-/* Whee.  EV67 can calculate it directly.  */
-static inline unsigned long hweight64(unsigned long w)
-{
-        return __kernel_ctpop(w);
-}
-
-static inline unsigned int hweight32(unsigned int w)
-{
-        return hweight64(w);
-}
-
-static inline unsigned int hweight16(unsigned int w)
-{
-        return hweight64(w & 0xffff);
-}
-
-static inline unsigned int hweight8(unsigned int w)
-{
-        return hweight64(w & 0xff);
-}
-#else
-#include <asm-generic/bitops/hweight.h>
-#endif
-
-#endif /* __KERNEL__ */
-
-#include <asm-generic/bitops/find.h>
-
-#ifdef __KERNEL__
-
-/*
- * Every architecture must define this function. It's the fastest
- * way of searching a 140-bit bitmap where the first 100 bits are
- * unlikely to be set. It's guaranteed that at least one of the 140
- * bits is set.
- */
-static inline unsigned long
-sched_find_first_bit(unsigned long b[3])
-{
-        unsigned long b0 = b[0], b1 = b[1], b2 = b[2];
-        unsigned long ofs;
-
-        ofs = (b1 ? 64 : 128);
-        b1 = (b1 ? b1 : b2);
-        ofs = (b0 ? 0 : ofs);
-        b0 = (b0 ? b0 : b1);
-
-        return __ffs(b0) + ofs;
-}
-
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-#define ext2_set_bit_atomic(l,n,a)   test_and_set_bit(n,a)
-#define ext2_clear_bit_atomic(l,n,a) test_and_clear_bit(n,a)
-
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ALPHA_BITOPS_H */
diff --git a/include/asm-alpha/bug.h b/include/asm-alpha/bug.h
deleted file mode 100644
index 695a5ee4b5d3..000000000000
--- a/include/asm-alpha/bug.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _ALPHA_BUG_H
-#define _ALPHA_BUG_H
-
-#include <linux/linkage.h>
-
-#ifdef CONFIG_BUG
-#include <asm/pal.h>
-
-/* ??? Would be nice to use .gprel32 here, but we can't be sure that the
-   function loaded the GP, so this could fail in modules.  */
-static inline void ATTRIB_NORET __BUG(const char *file, int line)
-{
-        __asm__ __volatile__(
-                "call_pal %0  # bugchk\n\t"
-                ".long %1\n\t.8byte %2"
-                       : : "i" (PAL_bugchk), "i"(line), "i"(file));
-        for ( ; ; )
-                ;
-}
-
-#define BUG() __BUG(__FILE__, __LINE__)
-
-#define HAVE_ARCH_BUG
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-alpha/bugs.h b/include/asm-alpha/bugs.h
deleted file mode 100644
index 78030d1c7e7e..000000000000
--- a/include/asm-alpha/bugs.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *  include/asm-alpha/bugs.h
- *
- *  Copyright (C) 1994  Linus Torvalds
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *      void check_bugs(void);
- */
-
-/*
- * I don't know of any alpha bugs yet.. Nice chip
- */
-
-static void check_bugs(void)
-{
-}
diff --git a/include/asm-alpha/byteorder.h b/include/asm-alpha/byteorder.h
deleted file mode 100644
index 58e958fc7f1b..000000000000
--- a/include/asm-alpha/byteorder.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef _ALPHA_BYTEORDER_H
-#define _ALPHA_BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-#include <asm/compiler.h>
-
-#ifdef __GNUC__
-
-static inline __attribute_const__ __u32 __arch__swab32(__u32 x)
-{
-        /*
-         * Unfortunately, we can't use the 6 instruction sequence
-         * on ev6 since the latency of the UNPKBW is 3, which is
-         * pretty hard to hide.  Just in case a future implementation
-         * has a lower latency, here's the sequence (also by Mike Burrows)
-         *
-         * UNPKBW a0, v0       v0: 00AA00BB00CC00DD
-         * SLL v0, 24, a0      a0: BB00CC00DD000000
-         * BIS v0, a0, a0      a0: BBAACCBBDDCC00DD
-         * EXTWL a0, 6, v0     v0: 000000000000BBAA
-         * ZAP a0, 0xf3, a0    a0: 00000000DDCC0000
-         * ADDL a0, v0, v0     v0: ssssssssDDCCBBAA
-         */
-
-        __u64 t0, t1, t2, t3;
-
-        t0 = __kernel_inslh(x, 7);      /* t0 : 0000000000AABBCC */
-        t1 = __kernel_inswl(x, 3);      /* t1 : 000000CCDD000000 */
-        t1 |= t0;                       /* t1 : 000000CCDDAABBCC */
-        t2 = t1 >> 16;                  /* t2 : 0000000000CCDDAA */
-        t0 = t1 & 0xFF00FF00;           /* t0 : 00000000DD00BB00 */
-        t3 = t2 & 0x00FF00FF;           /* t3 : 0000000000CC00AA */
-        t1 = t0 + t3;                   /* t1 : ssssssssDDCCBBAA */
-
-        return t1;
-}
-
-#define __arch__swab32 __arch__swab32
-
-#endif /* __GNUC__ */
-
-#define __BYTEORDER_HAS_U64__
-
-#include <linux/byteorder/little_endian.h>
-
-#endif /* _ALPHA_BYTEORDER_H */
diff --git a/include/asm-alpha/cache.h b/include/asm-alpha/cache.h
deleted file mode 100644
index f199e69a5d0b..000000000000
--- a/include/asm-alpha/cache.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * include/asm-alpha/cache.h
- */
-#ifndef __ARCH_ALPHA_CACHE_H
-#define __ARCH_ALPHA_CACHE_H
-
-
-/* Bytes per L1 (data) cache line. */
-#if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_EV6)
-# define L1_CACHE_BYTES     64
-# define L1_CACHE_SHIFT     6
-#else
-/* Both EV4 and EV5 are write-through, read-allocate,
-   direct-mapped, physical.
-*/
-# define L1_CACHE_BYTES     32
-# define L1_CACHE_SHIFT     5
-#endif
-
-#define L1_CACHE_ALIGN(x)  (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
-#define SMP_CACHE_BYTES    L1_CACHE_BYTES
-
-#endif
diff --git a/include/asm-alpha/cacheflush.h b/include/asm-alpha/cacheflush.h
deleted file mode 100644
index b686cc7fc44e..000000000000
--- a/include/asm-alpha/cacheflush.h
+++ /dev/null
@@ -1,74 +0,0 @@
-#ifndef _ALPHA_CACHEFLUSH_H
-#define _ALPHA_CACHEFLUSH_H
-
-#include <linux/mm.h>
-
-/* Caches aren't brain-dead on the Alpha. */
-#define flush_cache_all()                       do { } while (0)
-#define flush_cache_mm(mm)                      do { } while (0)
-#define flush_cache_dup_mm(mm)                  do { } while (0)
-#define flush_cache_range(vma, start, end)      do { } while (0)
-#define flush_cache_page(vma, vmaddr, pfn)      do { } while (0)
-#define flush_dcache_page(page)                 do { } while (0)
-#define flush_dcache_mmap_lock(mapping)         do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
-#define flush_cache_vmap(start, end)            do { } while (0)
-#define flush_cache_vunmap(start, end)          do { } while (0)
-
-/* Note that the following two definitions are _highly_ dependent
-   on the contexts in which they are used in the kernel.  I personally
-   think it is criminal how loosely defined these macros are.  */
-
-/* We need to flush the kernel's icache after loading modules.  The
-   only other use of this macro is in load_aout_interp which is not
-   used on Alpha. 
-
-   Note that this definition should *not* be used for userspace
-   icache flushing.  While functional, it is _way_ overkill.  The
-   icache is tagged with ASNs and it suffices to allocate a new ASN
-   for the process.  */
-#ifndef CONFIG_SMP
-#define flush_icache_range(start, end)          imb()
-#else
-#define flush_icache_range(start, end)          smp_imb()
-extern void smp_imb(void);
-#endif
-
-/* We need to flush the userspace icache after setting breakpoints in
-   ptrace.
-
-   Instead of indiscriminately using imb, take advantage of the fact
-   that icache entries are tagged with the ASN and load a new mm context.  */
-/* ??? Ought to use this in arch/alpha/kernel/signal.c too.  */
-
-#ifndef CONFIG_SMP
-extern void __load_new_mm_context(struct mm_struct *);
-static inline void
-flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
-                        unsigned long addr, int len)
-{
-        if (vma->vm_flags & VM_EXEC) {
-                struct mm_struct *mm = vma->vm_mm;
-                if (current->active_mm == mm)
-                        __load_new_mm_context(mm);
-                else
-                        mm->context[smp_processor_id()] = 0;
-        }
-}
-#else
-extern void flush_icache_user_range(struct vm_area_struct *vma,
-                struct page *page, unsigned long addr, int len);
-#endif
-
-/* This is used only in do_no_page and do_swap_page.  */
-#define flush_icache_page(vma, page) \
-  flush_icache_user_range((vma), (page), 0, 0)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
-     flush_icache_user_range(vma, page, vaddr, len); \
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-        memcpy(dst, src, len)
-
-#endif /* _ALPHA_CACHEFLUSH_H */
diff --git a/include/asm-alpha/checksum.h b/include/asm-alpha/checksum.h
deleted file mode 100644
index d3854bbf0a9e..000000000000
--- a/include/asm-alpha/checksum.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef _ALPHA_CHECKSUM_H
-#define _ALPHA_CHECKSUM_H
-
-#include <linux/in6.h>
-
-/*
- *      This is a version of ip_compute_csum() optimized for IP headers,
- *      which always checksum on 4 octet boundaries.
- */
-extern __sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-extern __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-                                           unsigned short len,
-                                           unsigned short proto,
-                                           __wsum sum);
-
-__wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
-                                unsigned short len, unsigned short proto,
-                                __wsum sum);
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-extern __wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len, __wsum sum, int *errp);
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum);
-
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-/*
- *      Fold a partial checksum without adding pseudo headers
- */
-
-static inline __sum16 csum_fold(__wsum csum)
-{
-        u32 sum = (__force u32)csum;
-        sum = (sum & 0xffff) + (sum >> 16);
-        sum = (sum & 0xffff) + (sum >> 16);
-        return (__force __sum16)~sum;
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-extern __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
-                               const struct in6_addr *daddr,
-                               __u32 len, unsigned short proto,
-                               __wsum sum);
-#endif
diff --git a/include/asm-alpha/compiler.h b/include/asm-alpha/compiler.h
deleted file mode 100644
index da6bb199839c..000000000000
--- a/include/asm-alpha/compiler.h
+++ /dev/null
@@ -1,130 +0,0 @@
-#ifndef __ALPHA_COMPILER_H
-#define __ALPHA_COMPILER_H
-
-/* 
- * Herein are macros we use when describing various patterns we want to GCC.
- * In all cases we can get better schedules out of the compiler if we hide
- * as little as possible inside inline assembly.  However, we want to be
- * able to know what we'll get out before giving up inline assembly.  Thus
- * these tests and macros.
- */
-
-#if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 || __GNUC__ > 3
-# define __kernel_insbl(val, shift)     __builtin_alpha_insbl(val, shift)
-# define __kernel_inswl(val, shift)     __builtin_alpha_inswl(val, shift)
-# define __kernel_insql(val, shift)     __builtin_alpha_insql(val, shift)
-# define __kernel_inslh(val, shift)     __builtin_alpha_inslh(val, shift)
-# define __kernel_extbl(val, shift)     __builtin_alpha_extbl(val, shift)
-# define __kernel_extwl(val, shift)     __builtin_alpha_extwl(val, shift)
-# define __kernel_cmpbge(a, b)          __builtin_alpha_cmpbge(a, b)
-#else
-# define __kernel_insbl(val, shift)                                     \
-  ({ unsigned long __kir;                                               \
-     __asm__("insbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));   \
-     __kir; })
-# define __kernel_inswl(val, shift)                                     \
-  ({ unsigned long __kir;                                               \
-     __asm__("inswl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));   \
-     __kir; })
-# define __kernel_insql(val, shift)                                     \
-  ({ unsigned long __kir;                                               \
-     __asm__("insql %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));   \
-     __kir; })
-# define __kernel_inslh(val, shift)                                     \
-  ({ unsigned long __kir;                                               \
-     __asm__("inslh %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));   \
-     __kir; })
-# define __kernel_extbl(val, shift)                                     \
-  ({ unsigned long __kir;                                               \
-     __asm__("extbl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));   \
-     __kir; })
-# define __kernel_extwl(val, shift)                                     \
-  ({ unsigned long __kir;                                               \
-     __asm__("extwl %2,%1,%0" : "=r"(__kir) : "rI"(shift), "r"(val));   \
-     __kir; })
-# define __kernel_cmpbge(a, b)                                          \
-  ({ unsigned long __kir;                                               \
-     __asm__("cmpbge %r2,%1,%0" : "=r"(__kir) : "rI"(b), "rJ"(a));      \
-     __kir; })
-#endif
-
-#ifdef __alpha_cix__
-# if __GNUC__ == 3 && __GNUC_MINOR__ >= 4 || __GNUC__ > 3
-#  define __kernel_cttz(x)              __builtin_ctzl(x)
-#  define __kernel_ctlz(x)              __builtin_clzl(x)
-#  define __kernel_ctpop(x)             __builtin_popcountl(x)
-# else
-#  define __kernel_cttz(x)                                              \
-   ({ unsigned long __kir;                                              \
-      __asm__("cttz %1,%0" : "=r"(__kir) : "r"(x));                     \
-      __kir; })
-#  define __kernel_ctlz(x)                                              \
-   ({ unsigned long __kir;                                              \
-      __asm__("ctlz %1,%0" : "=r"(__kir) : "r"(x));                     \
-      __kir; })
-#  define __kernel_ctpop(x)                                             \
-   ({ unsigned long __kir;                                              \
-      __asm__("ctpop %1,%0" : "=r"(__kir) : "r"(x));                    \
-      __kir; })
-# endif
-#else
-# define __kernel_cttz(x)                                               \
-  ({ unsigned long __kir;                                               \
-     __asm__(".arch ev67; cttz %1,%0" : "=r"(__kir) : "r"(x));          \
-     __kir; })
-# define __kernel_ctlz(x)                                               \
-  ({ unsigned long __kir;                                               \
-     __asm__(".arch ev67; ctlz %1,%0" : "=r"(__kir) : "r"(x));          \
-     __kir; })
-# define __kernel_ctpop(x)                                              \
-  ({ unsigned long __kir;                                               \
-     __asm__(".arch ev67; ctpop %1,%0" : "=r"(__kir) : "r"(x));         \
-     __kir; })
-#endif
-
-
-/* 
- * Beginning with EGCS 1.1, GCC defines __alpha_bwx__ when the BWX 
- * extension is enabled.  Previous versions did not define anything
- * we could test during compilation -- too bad, so sad.
- */
-
-#if defined(__alpha_bwx__)
-#define __kernel_ldbu(mem)      (mem)
-#define __kernel_ldwu(mem)      (mem)
-#define __kernel_stb(val,mem)   ((mem) = (val))
-#define __kernel_stw(val,mem)   ((mem) = (val))
-#else
-#define __kernel_ldbu(mem)                              \
-  ({ unsigned char __kir;                               \
-     __asm__(".arch ev56;                               \
-              ldbu %0,%1" : "=r"(__kir) : "m"(mem));    \
-     __kir; })
-#define __kernel_ldwu(mem)                              \
-  ({ unsigned short __kir;                              \
-     __asm__(".arch ev56;                               \
-              ldwu %0,%1" : "=r"(__kir) : "m"(mem));    \
-     __kir; })
-#define __kernel_stb(val,mem)                           \
-  __asm__(".arch ev56;                                  \
-           stb %1,%0" : "=m"(mem) : "r"(val))
-#define __kernel_stw(val,mem)                           \
-  __asm__(".arch ev56;                                  \
-           stw %1,%0" : "=m"(mem) : "r"(val))
-#endif
-
-#ifdef __KERNEL__
-/* Some idiots over in <linux/compiler.h> thought inline should imply
-   always_inline.  This breaks stuff.  We'll include this file whenever
-   we run into such problems.  */
-
-#include <linux/compiler.h>
-#undef inline
-#undef __inline__
-#undef __inline
-#undef __always_inline
-#define __always_inline         inline __attribute__((always_inline))
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_COMPILER_H */
diff --git a/include/asm-alpha/console.h b/include/asm-alpha/console.h
deleted file mode 100644
index a3ce4e62249b..000000000000
--- a/include/asm-alpha/console.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __AXP_CONSOLE_H
-#define __AXP_CONSOLE_H
-
-/*
- * Console callback routine numbers
- */
-#define CCB_GETC                0x01
-#define CCB_PUTS                0x02
-#define CCB_RESET_TERM          0x03
-#define CCB_SET_TERM_INT        0x04
-#define CCB_SET_TERM_CTL        0x05
-#define CCB_PROCESS_KEYCODE     0x06
-#define CCB_OPEN_CONSOLE        0x07
-#define CCB_CLOSE_CONSOLE       0x08
-
-#define CCB_OPEN                0x10
-#define CCB_CLOSE               0x11
-#define CCB_IOCTL               0x12
-#define CCB_READ                0x13
-#define CCB_WRITE               0x14
-
-#define CCB_SET_ENV             0x20
-#define CCB_RESET_ENV           0x21
-#define CCB_GET_ENV             0x22
-#define CCB_SAVE_ENV            0x23
-
-#define CCB_PSWITCH             0x30
-#define CCB_BIOS_EMUL           0x32
-
-/*
- * Environment variable numbers
- */
-#define ENV_AUTO_ACTION         0x01
-#define ENV_BOOT_DEV            0x02
-#define ENV_BOOTDEF_DEV         0x03
-#define ENV_BOOTED_DEV          0x04
-#define ENV_BOOT_FILE           0x05
-#define ENV_BOOTED_FILE         0x06
-#define ENV_BOOT_OSFLAGS        0x07
-#define ENV_BOOTED_OSFLAGS      0x08
-#define ENV_BOOT_RESET          0x09
-#define ENV_DUMP_DEV            0x0A
-#define ENV_ENABLE_AUDIT        0x0B
-#define ENV_LICENSE             0x0C
-#define ENV_CHAR_SET            0x0D
-#define ENV_LANGUAGE            0x0E
-#define ENV_TTY_DEV             0x0F
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-extern long callback_puts(long unit, const char *s, long length);
-extern long callback_getc(long unit);
-extern long callback_open_console(void);
-extern long callback_close_console(void);
-extern long callback_open(const char *device, long length);
-extern long callback_close(long unit);
-extern long callback_read(long channel, long count, const char *buf, long lbn);
-extern long callback_getenv(long id, const char *buf, unsigned long buf_size);
-extern long callback_setenv(long id, const char *buf, unsigned long buf_size);
-extern long callback_save_env(void);
-
-extern int srm_fixup(unsigned long new_callback_addr,
-                     unsigned long new_hwrpb_addr);
-extern long srm_puts(const char *, long);
-extern long srm_printk(const char *, ...)
-        __attribute__ ((format (printf, 1, 2)));
-
-struct crb_struct;
-struct hwrpb_struct;
-extern int callback_init_done;
-extern void * callback_init(void *);
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-
-#endif /* __AXP_CONSOLE_H */
diff --git a/include/asm-alpha/core_apecs.h b/include/asm-alpha/core_apecs.h
deleted file mode 100644
index 6785ff7e02bc..000000000000
--- a/include/asm-alpha/core_apecs.h
+++ /dev/null
@@ -1,517 +0,0 @@
-#ifndef __ALPHA_APECS__H__
-#define __ALPHA_APECS__H__
-
-#include <linux/types.h>
-#include <asm/compiler.h>
-
-/*
- * APECS is the internal name for the 2107x chipset which provides
- * memory controller and PCI access for the 21064 chip based systems.
- *
- * This file is based on:
- *
- * DECchip 21071-AA and DECchip 21072-AA Core Logic Chipsets
- * Data Sheet
- *
- * EC-N0648-72
- *
- *
- * david.rusling@reo.mts.dec.com Initial Version.
- *
- */
-
-/*
-   An AVANTI *might* be an XL, and an XL has only 27 bits of ISA address
-   that get passed through the PCI<->ISA bridge chip. So we've gotta use
-   both windows to max out the physical memory we can DMA to. Sigh...
-
-   If we try a window at 0 for 1GB as a work-around, we run into conflicts
-   with ISA/PCI bus memory which can't be relocated, like VGA aperture and
-   BIOS ROMs. So we must put the windows high enough to avoid these areas.
-
-   We put window 1 at BUS 64Mb for 64Mb, mapping physical 0 to 64Mb-1,
-   and window 2 at BUS 1Gb for 1Gb, mapping physical 0 to 1Gb-1.
-   Yes, this does map 0 to 64Mb-1 twice, but only window 1 will actually
-   be used for that range (via virt_to_bus()).
-
-   Note that we actually fudge the window 1 maximum as 48Mb instead of 64Mb,
-   to keep virt_to_bus() from returning an address in the first window, for
-   a data area that goes beyond the 64Mb first DMA window.  Sigh...
-   The fudge factor MUST match with <asm/dma.h> MAX_DMA_ADDRESS, but
-   we can't just use that here, because of header file looping... :-(
-
-   Window 1 will be used for all DMA from the ISA bus; yes, that does
-   limit what memory an ISA floppy or sound card or Ethernet can touch, but
-   it's also a known limitation on other platforms as well. We use the
-   same technique that is used on INTEL platforms with similar limitation:
-   set MAX_DMA_ADDRESS and clear some pages' DMAable flags during mem_init().
-   We trust that any ISA bus device drivers will *always* ask for DMAable
-   memory explicitly via kmalloc()/get_free_pages() flags arguments.
-
-   Note that most PCI bus devices' drivers do *not* explicitly ask for
-   DMAable memory; they count on being able to DMA to any memory they
-   get from kmalloc()/get_free_pages(). They will also use window 1 for
-   any physical memory accesses below 64Mb; the rest will be handled by
-   window 2, maxing out at 1Gb of memory. I trust this is enough... :-)
-
-   We hope that the area before the first window is large enough so that
-   there will be no overlap at the top end (64Mb). We *must* locate the
-   PCI cards' memory just below window 1, so that there's still the
-   possibility of being able to access it via SPARSE space. This is
-   important for cards such as the Matrox Millennium, whose Xserver
-   wants to access memory-mapped registers in byte and short lengths.
-
-   Note that the XL is treated differently from the AVANTI, even though
-   for most other things they are identical. It didn't seem reasonable to
-   make the AVANTI support pay for the limitations of the XL. It is true,
-   however, that an XL kernel will run on an AVANTI without problems.
-
-   %%% All of this should be obviated by the ability to route
-   everything through the iommu.
-*/
-
-/*
- * 21071-DA Control and Status registers.
- * These are used for PCI memory access.
- */
-#define APECS_IOC_DCSR                  (IDENT_ADDR + 0x1A0000000UL)
-#define APECS_IOC_PEAR                  (IDENT_ADDR + 0x1A0000020UL)
-#define APECS_IOC_SEAR                  (IDENT_ADDR + 0x1A0000040UL)
-#define APECS_IOC_DR1                   (IDENT_ADDR + 0x1A0000060UL)
-#define APECS_IOC_DR2                   (IDENT_ADDR + 0x1A0000080UL)
-#define APECS_IOC_DR3                   (IDENT_ADDR + 0x1A00000A0UL)
-
-#define APECS_IOC_TB1R                  (IDENT_ADDR + 0x1A00000C0UL)
-#define APECS_IOC_TB2R                  (IDENT_ADDR + 0x1A00000E0UL)
-
-#define APECS_IOC_PB1R                  (IDENT_ADDR + 0x1A0000100UL)
-#define APECS_IOC_PB2R                  (IDENT_ADDR + 0x1A0000120UL)
-
-#define APECS_IOC_PM1R                  (IDENT_ADDR + 0x1A0000140UL)
-#define APECS_IOC_PM2R                  (IDENT_ADDR + 0x1A0000160UL)
-
-#define APECS_IOC_HAXR0                 (IDENT_ADDR + 0x1A0000180UL)
-#define APECS_IOC_HAXR1                 (IDENT_ADDR + 0x1A00001A0UL)
-#define APECS_IOC_HAXR2                 (IDENT_ADDR + 0x1A00001C0UL)
-
-#define APECS_IOC_PMLT                  (IDENT_ADDR + 0x1A00001E0UL)
-
-#define APECS_IOC_TLBTAG0               (IDENT_ADDR + 0x1A0000200UL)
-#define APECS_IOC_TLBTAG1               (IDENT_ADDR + 0x1A0000220UL)
-#define APECS_IOC_TLBTAG2               (IDENT_ADDR + 0x1A0000240UL)
-#define APECS_IOC_TLBTAG3               (IDENT_ADDR + 0x1A0000260UL)
-#define APECS_IOC_TLBTAG4               (IDENT_ADDR + 0x1A0000280UL)
-#define APECS_IOC_TLBTAG5               (IDENT_ADDR + 0x1A00002A0UL)
-#define APECS_IOC_TLBTAG6               (IDENT_ADDR + 0x1A00002C0UL)
-#define APECS_IOC_TLBTAG7               (IDENT_ADDR + 0x1A00002E0UL)
-
-#define APECS_IOC_TLBDATA0              (IDENT_ADDR + 0x1A0000300UL)
-#define APECS_IOC_TLBDATA1              (IDENT_ADDR + 0x1A0000320UL)
-#define APECS_IOC_TLBDATA2              (IDENT_ADDR + 0x1A0000340UL)
-#define APECS_IOC_TLBDATA3              (IDENT_ADDR + 0x1A0000360UL)
-#define APECS_IOC_TLBDATA4              (IDENT_ADDR + 0x1A0000380UL)
-#define APECS_IOC_TLBDATA5              (IDENT_ADDR + 0x1A00003A0UL)
-#define APECS_IOC_TLBDATA6              (IDENT_ADDR + 0x1A00003C0UL)
-#define APECS_IOC_TLBDATA7              (IDENT_ADDR + 0x1A00003E0UL)
-
-#define APECS_IOC_TBIA                  (IDENT_ADDR + 0x1A0000400UL)
-
-
-/*
- * 21071-CA Control and Status registers.
- * These are used to program memory timing,
- *  configure memory and initialise the B-Cache.
- */
-#define APECS_MEM_GCR                   (IDENT_ADDR + 0x180000000UL)
-#define APECS_MEM_EDSR                  (IDENT_ADDR + 0x180000040UL)
-#define APECS_MEM_TAR                   (IDENT_ADDR + 0x180000060UL)
-#define APECS_MEM_ELAR                  (IDENT_ADDR + 0x180000080UL)
-#define APECS_MEM_EHAR                  (IDENT_ADDR + 0x1800000a0UL)
-#define APECS_MEM_SFT_RST               (IDENT_ADDR + 0x1800000c0UL)
-#define APECS_MEM_LDxLAR                (IDENT_ADDR + 0x1800000e0UL)
-#define APECS_MEM_LDxHAR                (IDENT_ADDR + 0x180000100UL)
-#define APECS_MEM_GTR                   (IDENT_ADDR + 0x180000200UL)
-#define APECS_MEM_RTR                   (IDENT_ADDR + 0x180000220UL)
-#define APECS_MEM_VFPR                  (IDENT_ADDR + 0x180000240UL)
-#define APECS_MEM_PDLDR                 (IDENT_ADDR + 0x180000260UL)
-#define APECS_MEM_PDhDR                 (IDENT_ADDR + 0x180000280UL)
-
-/* Bank x Base Address Register */
-#define APECS_MEM_B0BAR                 (IDENT_ADDR + 0x180000800UL)
-#define APECS_MEM_B1BAR                 (IDENT_ADDR + 0x180000820UL)
-#define APECS_MEM_B2BAR                 (IDENT_ADDR + 0x180000840UL)
-#define APECS_MEM_B3BAR                 (IDENT_ADDR + 0x180000860UL)
-#define APECS_MEM_B4BAR                 (IDENT_ADDR + 0x180000880UL)
-#define APECS_MEM_B5BAR                 (IDENT_ADDR + 0x1800008A0UL)
-#define APECS_MEM_B6BAR                 (IDENT_ADDR + 0x1800008C0UL)
-#define APECS_MEM_B7BAR                 (IDENT_ADDR + 0x1800008E0UL)
-#define APECS_MEM_B8BAR                 (IDENT_ADDR + 0x180000900UL)
-
-/* Bank x Configuration Register */
-#define APECS_MEM_B0BCR                 (IDENT_ADDR + 0x180000A00UL)
-#define APECS_MEM_B1BCR                 (IDENT_ADDR + 0x180000A20UL)
-#define APECS_MEM_B2BCR                 (IDENT_ADDR + 0x180000A40UL)
-#define APECS_MEM_B3BCR                 (IDENT_ADDR + 0x180000A60UL)
-#define APECS_MEM_B4BCR                 (IDENT_ADDR + 0x180000A80UL)
-#define APECS_MEM_B5BCR                 (IDENT_ADDR + 0x180000AA0UL)
-#define APECS_MEM_B6BCR                 (IDENT_ADDR + 0x180000AC0UL)
-#define APECS_MEM_B7BCR                 (IDENT_ADDR + 0x180000AE0UL)
-#define APECS_MEM_B8BCR                 (IDENT_ADDR + 0x180000B00UL)
-
-/* Bank x Timing Register A */
-#define APECS_MEM_B0TRA                 (IDENT_ADDR + 0x180000C00UL)
-#define APECS_MEM_B1TRA                 (IDENT_ADDR + 0x180000C20UL)
-#define APECS_MEM_B2TRA                 (IDENT_ADDR + 0x180000C40UL)
-#define APECS_MEM_B3TRA                 (IDENT_ADDR + 0x180000C60UL)
-#define APECS_MEM_B4TRA                 (IDENT_ADDR + 0x180000C80UL)
-#define APECS_MEM_B5TRA                 (IDENT_ADDR + 0x180000CA0UL)
-#define APECS_MEM_B6TRA                 (IDENT_ADDR + 0x180000CC0UL)
-#define APECS_MEM_B7TRA                 (IDENT_ADDR + 0x180000CE0UL)
-#define APECS_MEM_B8TRA                 (IDENT_ADDR + 0x180000D00UL)
-
-/* Bank x Timing Register B */
-#define APECS_MEM_B0TRB                 (IDENT_ADDR + 0x180000E00UL)
-#define APECS_MEM_B1TRB                 (IDENT_ADDR + 0x180000E20UL)
-#define APECS_MEM_B2TRB                 (IDENT_ADDR + 0x180000E40UL)
-#define APECS_MEM_B3TRB                 (IDENT_ADDR + 0x180000E60UL)
-#define APECS_MEM_B4TRB                 (IDENT_ADDR + 0x180000E80UL)
-#define APECS_MEM_B5TRB                 (IDENT_ADDR + 0x180000EA0UL)
-#define APECS_MEM_B6TRB                 (IDENT_ADDR + 0x180000EC0UL)
-#define APECS_MEM_B7TRB                 (IDENT_ADDR + 0x180000EE0UL)
-#define APECS_MEM_B8TRB                 (IDENT_ADDR + 0x180000F00UL)
-
-
-/*
- * Memory spaces:
- */
-#define APECS_IACK_SC                   (IDENT_ADDR + 0x1b0000000UL)
-#define APECS_CONF                      (IDENT_ADDR + 0x1e0000000UL)
-#define APECS_IO                        (IDENT_ADDR + 0x1c0000000UL)
-#define APECS_SPARSE_MEM                (IDENT_ADDR + 0x200000000UL)
-#define APECS_DENSE_MEM                 (IDENT_ADDR + 0x300000000UL)
-
-
-/*
- * Bit definitions for I/O Controller status register 0:
- */
-#define APECS_IOC_STAT0_CMD             0xf
-#define APECS_IOC_STAT0_ERR             (1<<4)
-#define APECS_IOC_STAT0_LOST            (1<<5)
-#define APECS_IOC_STAT0_THIT            (1<<6)
-#define APECS_IOC_STAT0_TREF            (1<<7)
-#define APECS_IOC_STAT0_CODE_SHIFT      8
-#define APECS_IOC_STAT0_CODE_MASK       0x7
-#define APECS_IOC_STAT0_P_NBR_SHIFT     13
-#define APECS_IOC_STAT0_P_NBR_MASK      0x7ffff
-
-#define APECS_HAE_ADDRESS               APECS_IOC_HAXR1
-
-
-/*
- * Data structure for handling APECS machine checks:
- */
-
-struct el_apecs_mikasa_sysdata_mcheck
-{
-        unsigned long coma_gcr;
-        unsigned long coma_edsr;
-        unsigned long coma_ter;
-        unsigned long coma_elar;
-        unsigned long coma_ehar;
-        unsigned long coma_ldlr;
-        unsigned long coma_ldhr;
-        unsigned long coma_base0;
-        unsigned long coma_base1;
-        unsigned long coma_base2;
-        unsigned long coma_base3;
-        unsigned long coma_cnfg0;
-        unsigned long coma_cnfg1;
-        unsigned long coma_cnfg2;
-        unsigned long coma_cnfg3;
-        unsigned long epic_dcsr;
-        unsigned long epic_pear;
-        unsigned long epic_sear;
-        unsigned long epic_tbr1;
-        unsigned long epic_tbr2;
-        unsigned long epic_pbr1;
-        unsigned long epic_pbr2;
-        unsigned long epic_pmr1;
-        unsigned long epic_pmr2;
-        unsigned long epic_harx1;
-        unsigned long epic_harx2;
-        unsigned long epic_pmlt;
-        unsigned long epic_tag0;
-        unsigned long epic_tag1;
-        unsigned long epic_tag2;
-        unsigned long epic_tag3;
-        unsigned long epic_tag4;
-        unsigned long epic_tag5;
-        unsigned long epic_tag6;
-        unsigned long epic_tag7;
-        unsigned long epic_data0;
-        unsigned long epic_data1;
-        unsigned long epic_data2;
-        unsigned long epic_data3;
-        unsigned long epic_data4;
-        unsigned long epic_data5;
-        unsigned long epic_data6;
-        unsigned long epic_data7;
-
-        unsigned long pceb_vid;
-        unsigned long pceb_did;
-        unsigned long pceb_revision;
-        unsigned long pceb_command;
-        unsigned long pceb_status;
-        unsigned long pceb_latency;
-        unsigned long pceb_control;
-        unsigned long pceb_arbcon;
-        unsigned long pceb_arbpri;
-
-        unsigned long esc_id;
-        unsigned long esc_revision;
-        unsigned long esc_int0;
-        unsigned long esc_int1;
-        unsigned long esc_elcr0;
-        unsigned long esc_elcr1;
-        unsigned long esc_last_eisa;
-        unsigned long esc_nmi_stat;
-
-        unsigned long pci_ir;
-        unsigned long pci_imr;
-        unsigned long svr_mgr;
-};
-
-/* This for the normal APECS machines.  */
-struct el_apecs_sysdata_mcheck
-{
-        unsigned long coma_gcr;
-        unsigned long coma_edsr;
-        unsigned long coma_ter;
-        unsigned long coma_elar;
-        unsigned long coma_ehar;
-        unsigned long coma_ldlr;
-        unsigned long coma_ldhr;
-        unsigned long coma_base0;
-        unsigned long coma_base1;
-        unsigned long coma_base2;
-        unsigned long coma_cnfg0;
-        unsigned long coma_cnfg1;
-        unsigned long coma_cnfg2;
-        unsigned long epic_dcsr;
-        unsigned long epic_pear;
-        unsigned long epic_sear;
-        unsigned long epic_tbr1;
-        unsigned long epic_tbr2;
-        unsigned long epic_pbr1;
-        unsigned long epic_pbr2;
-        unsigned long epic_pmr1;
-        unsigned long epic_pmr2;
-        unsigned long epic_harx1;
-        unsigned long epic_harx2;
-        unsigned long epic_pmlt;
-        unsigned long epic_tag0;
-        unsigned long epic_tag1;
-        unsigned long epic_tag2;
-        unsigned long epic_tag3;
-        unsigned long epic_tag4;
-        unsigned long epic_tag5;
-        unsigned long epic_tag6;
-        unsigned long epic_tag7;
-        unsigned long epic_data0;
-        unsigned long epic_data1;
-        unsigned long epic_data2;
-        unsigned long epic_data3;
-        unsigned long epic_data4;
-        unsigned long epic_data5;
-        unsigned long epic_data6;
-        unsigned long epic_data7;
-};
-
-struct el_apecs_procdata
-{
-        unsigned long paltemp[32];  /* PAL TEMP REGS. */
-        /* EV4-specific fields */
-        unsigned long exc_addr;     /* Address of excepting instruction. */
-        unsigned long exc_sum;      /* Summary of arithmetic traps. */
-        unsigned long exc_mask;     /* Exception mask (from exc_sum). */
-        unsigned long iccsr;        /* IBox hardware enables. */
-        unsigned long pal_base;     /* Base address for PALcode. */
-        unsigned long hier;         /* Hardware Interrupt Enable. */
-        unsigned long hirr;         /* Hardware Interrupt Request. */
-        unsigned long csr;          /* D-stream fault info. */
-        unsigned long dc_stat;      /* D-cache status (ECC/Parity Err). */
-        unsigned long dc_addr;      /* EV3 Phys Addr for ECC/DPERR. */
-        unsigned long abox_ctl;     /* ABox Control Register. */
-        unsigned long biu_stat;     /* BIU Status. */
-        unsigned long biu_addr;     /* BUI Address. */
-        unsigned long biu_ctl;      /* BIU Control. */
-        unsigned long fill_syndrome;/* For correcting ECC errors. */
-        unsigned long fill_addr;    /* Cache block which was being read */
-        unsigned long va;           /* Effective VA of fault or miss. */
-        unsigned long bc_tag;       /* Backup Cache Tag Probe Results.*/
-};
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * Unlike Jensen, the APECS machines have no concept of local
- * I/O---everything goes over the PCI bus.
- *
- * There is plenty room for optimization here.  In particular,
- * the Alpha's insb/insw/extb/extw should be useful in moving
- * data to/from the right byte-lanes.
- */
-
-#define vip     volatile int __force *
-#define vuip    volatile unsigned int __force *
-#define vulp    volatile unsigned long __force *
-
-#define APECS_SET_HAE                                           \
-        do {                                                    \
-                if (addr >= (1UL << 24)) {                      \
-                        unsigned long msb = addr & 0xf8000000;  \
-                        addr -= msb;                            \
-                        set_hae(msb);                           \
-                }                                               \
-        } while (0)
-
-__EXTERN_INLINE unsigned int apecs_ioread8(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long result, base_and_type;
-
-        if (addr >= APECS_DENSE_MEM) {
-                addr -= APECS_DENSE_MEM;
-                APECS_SET_HAE;
-                base_and_type = APECS_SPARSE_MEM + 0x00;
-        } else {
-                addr -= APECS_IO;
-                base_and_type = APECS_IO + 0x00;
-        }
-
-        result = *(vip) ((addr << 5) + base_and_type);
-        return __kernel_extbl(result, addr & 3);
-}
-
-__EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long w, base_and_type;
-
-        if (addr >= APECS_DENSE_MEM) {
-                addr -= APECS_DENSE_MEM;
-                APECS_SET_HAE;
-                base_and_type = APECS_SPARSE_MEM + 0x00;
-        } else {
-                addr -= APECS_IO;
-                base_and_type = APECS_IO + 0x00;
-        }
-
-        w = __kernel_insbl(b, addr & 3);
-        *(vuip) ((addr << 5) + base_and_type) = w;
-}
-
-__EXTERN_INLINE unsigned int apecs_ioread16(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long result, base_and_type;
-
-        if (addr >= APECS_DENSE_MEM) {
-                addr -= APECS_DENSE_MEM;
-                APECS_SET_HAE;
-                base_and_type = APECS_SPARSE_MEM + 0x08;
-        } else {
-                addr -= APECS_IO;
-                base_and_type = APECS_IO + 0x08;
-        }
-
-        result = *(vip) ((addr << 5) + base_and_type);
-        return __kernel_extwl(result, addr & 3);
-}
-
-__EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long w, base_and_type;
-
-        if (addr >= APECS_DENSE_MEM) {
-                addr -= APECS_DENSE_MEM;
-                APECS_SET_HAE;
-                base_and_type = APECS_SPARSE_MEM + 0x08;
-        } else {
-                addr -= APECS_IO;
-                base_and_type = APECS_IO + 0x08;
-        }
-
-        w = __kernel_inswl(b, addr & 3);
-        *(vuip) ((addr << 5) + base_and_type) = w;
-}
-
-__EXTERN_INLINE unsigned int apecs_ioread32(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        if (addr < APECS_DENSE_MEM)
-                addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
-        return *(vuip)addr;
-}
-
-__EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        if (addr < APECS_DENSE_MEM)
-                addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
-        *(vuip)addr = b;
-}
-
-__EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + APECS_IO);
-}
-
-__EXTERN_INLINE void __iomem *apecs_ioremap(unsigned long addr,
-                                            unsigned long size)
-{
-        return (void __iomem *)(addr + APECS_DENSE_MEM);
-}
-
-__EXTERN_INLINE int apecs_is_ioaddr(unsigned long addr)
-{
-        return addr >= IDENT_ADDR + 0x180000000UL;
-}
-
-__EXTERN_INLINE int apecs_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >= APECS_DENSE_MEM;
-}
-
-#undef APECS_SET_HAE
-
-#undef vip
-#undef vuip
-#undef vulp
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             apecs
-#define apecs_trivial_io_bw     0
-#define apecs_trivial_io_lq     0
-#define apecs_trivial_rw_bw     2
-#define apecs_trivial_rw_lq     1
-#define apecs_trivial_iounmap   1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_APECS__H__ */
diff --git a/include/asm-alpha/core_cia.h b/include/asm-alpha/core_cia.h
deleted file mode 100644
index 9e0516c0ca27..000000000000
--- a/include/asm-alpha/core_cia.h
+++ /dev/null
@@ -1,500 +0,0 @@
-#ifndef __ALPHA_CIA__H__
-#define __ALPHA_CIA__H__
-
-/* Define to experiment with fitting everything into one 512MB HAE window.  */
-#define CIA_ONE_HAE_WINDOW 1
-
-#include <linux/types.h>
-#include <asm/compiler.h>
-
-/*
- * CIA is the internal name for the 21171 chipset which provides
- * memory controller and PCI access for the 21164 chip based systems.
- * Also supported here is the 21172 (CIA-2) and 21174 (PYXIS).
- *
- * The lineage is a bit confused, since the 21174 was reportedly started
- * from the 21171 Pass 1 mask, and so is missing bug fixes that appear
- * in 21171 Pass 2 and 21172, but it also contains additional features.
- *
- * This file is based on:
- *
- * DECchip 21171 Core Logic Chipset
- * Technical Reference Manual
- *
- * EC-QE18B-TE
- *
- * david.rusling@reo.mts.dec.com Initial Version.
- *
- */
-
-/*
- * CIA ADDRESS BIT DEFINITIONS
- *
- *  3333 3333 3322 2222 2222 1111 1111 11
- *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
- *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
- *  1                                             000
- *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
- *  |                                             |\|
- *  |                               Byte Enable --+ |
- *  |                             Transfer Length --+
- *  +-- IO space, not cached
- *
- *   Byte      Transfer
- *   Enable    Length    Transfer  Byte    Address
- *   adr<6:5>  adr<4:3>  Length    Enable  Adder
- *   ---------------------------------------------
- *      00        00      Byte      1110   0x000
- *      01        00      Byte      1101   0x020
- *      10        00      Byte      1011   0x040
- *      11        00      Byte      0111   0x060
- *
- *      00        01      Word      1100   0x008
- *      01        01      Word      1001   0x028 <= Not supported in this code.
- *      10        01      Word      0011   0x048
- *
- *      00        10      Tribyte   1000   0x010
- *      01        10      Tribyte   0001   0x030
- *
- *      10        11      Longword  0000   0x058
- *
- *      Note that byte enables are asserted low.
- *
- */
-
-#define CIA_MEM_R1_MASK 0x1fffffff  /* SPARSE Mem region 1 mask is 29 bits */
-#define CIA_MEM_R2_MASK 0x07ffffff  /* SPARSE Mem region 2 mask is 27 bits */
-#define CIA_MEM_R3_MASK 0x03ffffff  /* SPARSE Mem region 3 mask is 26 bits */
-
-/*
- * 21171-CA Control and Status Registers
- */
-#define CIA_IOC_CIA_REV                 (IDENT_ADDR + 0x8740000080UL)
-#  define CIA_REV_MASK                  0xff
-#define CIA_IOC_PCI_LAT                 (IDENT_ADDR + 0x87400000C0UL)
-#define CIA_IOC_CIA_CTRL                (IDENT_ADDR + 0x8740000100UL)
-#  define CIA_CTRL_PCI_EN               (1 << 0)
-#  define CIA_CTRL_PCI_LOCK_EN          (1 << 1)
-#  define CIA_CTRL_PCI_LOOP_EN          (1 << 2)
-#  define CIA_CTRL_FST_BB_EN            (1 << 3)
-#  define CIA_CTRL_PCI_MST_EN           (1 << 4)
-#  define CIA_CTRL_PCI_MEM_EN           (1 << 5)
-#  define CIA_CTRL_PCI_REQ64_EN         (1 << 6)
-#  define CIA_CTRL_PCI_ACK64_EN         (1 << 7)
-#  define CIA_CTRL_ADDR_PE_EN           (1 << 8)
-#  define CIA_CTRL_PERR_EN              (1 << 9)
-#  define CIA_CTRL_FILL_ERR_EN          (1 << 10)
-#  define CIA_CTRL_MCHK_ERR_EN          (1 << 11)
-#  define CIA_CTRL_ECC_CHK_EN           (1 << 12)
-#  define CIA_CTRL_ASSERT_IDLE_BC       (1 << 13)
-#  define CIA_CTRL_COM_IDLE_BC          (1 << 14)
-#  define CIA_CTRL_CSR_IOA_BYPASS       (1 << 15)
-#  define CIA_CTRL_IO_FLUSHREQ_EN       (1 << 16)
-#  define CIA_CTRL_CPU_FLUSHREQ_EN      (1 << 17)
-#  define CIA_CTRL_ARB_CPU_EN           (1 << 18)
-#  define CIA_CTRL_EN_ARB_LINK          (1 << 19)
-#  define CIA_CTRL_RD_TYPE_SHIFT        20
-#  define CIA_CTRL_RL_TYPE_SHIFT        24
-#  define CIA_CTRL_RM_TYPE_SHIFT        28
-#  define CIA_CTRL_EN_DMA_RD_PERF       (1 << 31)
-#define CIA_IOC_CIA_CNFG                (IDENT_ADDR + 0x8740000140UL)
-#  define CIA_CNFG_IOA_BWEN             (1 << 0)
-#  define CIA_CNFG_PCI_MWEN             (1 << 4)
-#  define CIA_CNFG_PCI_DWEN             (1 << 5)
-#  define CIA_CNFG_PCI_WLEN             (1 << 8)
-#define CIA_IOC_FLASH_CTRL              (IDENT_ADDR + 0x8740000200UL)
-#define CIA_IOC_HAE_MEM                 (IDENT_ADDR + 0x8740000400UL)
-#define CIA_IOC_HAE_IO                  (IDENT_ADDR + 0x8740000440UL)
-#define CIA_IOC_CFG                     (IDENT_ADDR + 0x8740000480UL)
-#define CIA_IOC_CACK_EN                 (IDENT_ADDR + 0x8740000600UL)
-#  define CIA_CACK_EN_LOCK_EN           (1 << 0)
-#  define CIA_CACK_EN_MB_EN             (1 << 1)
-#  define CIA_CACK_EN_SET_DIRTY_EN      (1 << 2)
-#  define CIA_CACK_EN_BC_VICTIM_EN      (1 << 3)
-
-
-/*
- * 21171-CA Diagnostic Registers
- */
-#define CIA_IOC_CIA_DIAG                (IDENT_ADDR + 0x8740002000UL)
-#define CIA_IOC_DIAG_CHECK              (IDENT_ADDR + 0x8740003000UL)
-
-/*
- * 21171-CA Performance Monitor registers
- */
-#define CIA_IOC_PERF_MONITOR            (IDENT_ADDR + 0x8740004000UL)
-#define CIA_IOC_PERF_CONTROL            (IDENT_ADDR + 0x8740004040UL)
-
-/*
- * 21171-CA Error registers
- */
-#define CIA_IOC_CPU_ERR0                (IDENT_ADDR + 0x8740008000UL)
-#define CIA_IOC_CPU_ERR1                (IDENT_ADDR + 0x8740008040UL)
-#define CIA_IOC_CIA_ERR                 (IDENT_ADDR + 0x8740008200UL)
-#  define CIA_ERR_COR_ERR               (1 << 0)
-#  define CIA_ERR_UN_COR_ERR            (1 << 1)
-#  define CIA_ERR_CPU_PE                (1 << 2)
-#  define CIA_ERR_MEM_NEM               (1 << 3)
-#  define CIA_ERR_PCI_SERR              (1 << 4)
-#  define CIA_ERR_PERR                  (1 << 5)
-#  define CIA_ERR_PCI_ADDR_PE           (1 << 6)
-#  define CIA_ERR_RCVD_MAS_ABT          (1 << 7)
-#  define CIA_ERR_RCVD_TAR_ABT          (1 << 8)
-#  define CIA_ERR_PA_PTE_INV            (1 << 9)
-#  define CIA_ERR_FROM_WRT_ERR          (1 << 10)
-#  define CIA_ERR_IOA_TIMEOUT           (1 << 11)
-#  define CIA_ERR_LOST_CORR_ERR         (1 << 16)
-#  define CIA_ERR_LOST_UN_CORR_ERR      (1 << 17)
-#  define CIA_ERR_LOST_CPU_PE           (1 << 18)
-#  define CIA_ERR_LOST_MEM_NEM          (1 << 19)
-#  define CIA_ERR_LOST_PERR             (1 << 21)
-#  define CIA_ERR_LOST_PCI_ADDR_PE      (1 << 22)
-#  define CIA_ERR_LOST_RCVD_MAS_ABT     (1 << 23)
-#  define CIA_ERR_LOST_RCVD_TAR_ABT     (1 << 24)
-#  define CIA_ERR_LOST_PA_PTE_INV       (1 << 25)
-#  define CIA_ERR_LOST_FROM_WRT_ERR     (1 << 26)
-#  define CIA_ERR_LOST_IOA_TIMEOUT      (1 << 27)
-#  define CIA_ERR_VALID                 (1 << 31)
-#define CIA_IOC_CIA_STAT                (IDENT_ADDR + 0x8740008240UL)
-#define CIA_IOC_ERR_MASK                (IDENT_ADDR + 0x8740008280UL)
-#define CIA_IOC_CIA_SYN                 (IDENT_ADDR + 0x8740008300UL)
-#define CIA_IOC_MEM_ERR0                (IDENT_ADDR + 0x8740008400UL)
-#define CIA_IOC_MEM_ERR1                (IDENT_ADDR + 0x8740008440UL)
-#define CIA_IOC_PCI_ERR0                (IDENT_ADDR + 0x8740008800UL)
-#define CIA_IOC_PCI_ERR1                (IDENT_ADDR + 0x8740008840UL)
-#define CIA_IOC_PCI_ERR3                (IDENT_ADDR + 0x8740008880UL)
-
-/*
- * 21171-CA System configuration registers
- */
-#define CIA_IOC_MCR                     (IDENT_ADDR + 0x8750000000UL)
-#define CIA_IOC_MBA0                    (IDENT_ADDR + 0x8750000600UL)
-#define CIA_IOC_MBA2                    (IDENT_ADDR + 0x8750000680UL)
-#define CIA_IOC_MBA4                    (IDENT_ADDR + 0x8750000700UL)
-#define CIA_IOC_MBA6                    (IDENT_ADDR + 0x8750000780UL)
-#define CIA_IOC_MBA8                    (IDENT_ADDR + 0x8750000800UL)
-#define CIA_IOC_MBAA                    (IDENT_ADDR + 0x8750000880UL)
-#define CIA_IOC_MBAC                    (IDENT_ADDR + 0x8750000900UL)
-#define CIA_IOC_MBAE                    (IDENT_ADDR + 0x8750000980UL)
-#define CIA_IOC_TMG0                    (IDENT_ADDR + 0x8750000B00UL)
-#define CIA_IOC_TMG1                    (IDENT_ADDR + 0x8750000B40UL)
-#define CIA_IOC_TMG2                    (IDENT_ADDR + 0x8750000B80UL)
-
-/*
- * 2117A-CA PCI Address and Scatter-Gather Registers.
- */
-#define CIA_IOC_PCI_TBIA                (IDENT_ADDR + 0x8760000100UL)
-
-#define CIA_IOC_PCI_W0_BASE             (IDENT_ADDR + 0x8760000400UL)
-#define CIA_IOC_PCI_W0_MASK             (IDENT_ADDR + 0x8760000440UL)
-#define CIA_IOC_PCI_T0_BASE             (IDENT_ADDR + 0x8760000480UL)
-
-#define CIA_IOC_PCI_W1_BASE             (IDENT_ADDR + 0x8760000500UL)
-#define CIA_IOC_PCI_W1_MASK             (IDENT_ADDR + 0x8760000540UL)
-#define CIA_IOC_PCI_T1_BASE             (IDENT_ADDR + 0x8760000580UL)
-
-#define CIA_IOC_PCI_W2_BASE             (IDENT_ADDR + 0x8760000600UL)
-#define CIA_IOC_PCI_W2_MASK             (IDENT_ADDR + 0x8760000640UL)
-#define CIA_IOC_PCI_T2_BASE             (IDENT_ADDR + 0x8760000680UL)
-
-#define CIA_IOC_PCI_W3_BASE             (IDENT_ADDR + 0x8760000700UL)
-#define CIA_IOC_PCI_W3_MASK             (IDENT_ADDR + 0x8760000740UL)
-#define CIA_IOC_PCI_T3_BASE             (IDENT_ADDR + 0x8760000780UL)
-
-#define CIA_IOC_PCI_Wn_BASE(N)  (IDENT_ADDR + 0x8760000400UL + (N)*0x100) 
-#define CIA_IOC_PCI_Wn_MASK(N)  (IDENT_ADDR + 0x8760000440UL + (N)*0x100) 
-#define CIA_IOC_PCI_Tn_BASE(N)  (IDENT_ADDR + 0x8760000480UL + (N)*0x100) 
-
-#define CIA_IOC_PCI_W_DAC               (IDENT_ADDR + 0x87600007C0UL)
-
-/*
- * 2117A-CA Address Translation Registers.
- */
-
-/* 8 tag registers, the first 4 of which are lockable.  */
-#define CIA_IOC_TB_TAGn(n) \
-        (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
-
-/* 4 page registers per tag register.  */
-#define CIA_IOC_TBn_PAGEm(n,m) \
-        (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
-
-/*
- * Memory spaces:
- */
-#define CIA_IACK_SC                     (IDENT_ADDR + 0x8720000000UL)
-#define CIA_CONF                        (IDENT_ADDR + 0x8700000000UL)
-#define CIA_IO                          (IDENT_ADDR + 0x8580000000UL)
-#define CIA_SPARSE_MEM                  (IDENT_ADDR + 0x8000000000UL)
-#define CIA_SPARSE_MEM_R2               (IDENT_ADDR + 0x8400000000UL)
-#define CIA_SPARSE_MEM_R3               (IDENT_ADDR + 0x8500000000UL)
-#define CIA_DENSE_MEM                   (IDENT_ADDR + 0x8600000000UL)
-#define CIA_BW_MEM                      (IDENT_ADDR + 0x8800000000UL)
-#define CIA_BW_IO                       (IDENT_ADDR + 0x8900000000UL)
-#define CIA_BW_CFG_0                    (IDENT_ADDR + 0x8a00000000UL)
-#define CIA_BW_CFG_1                    (IDENT_ADDR + 0x8b00000000UL)
-
-/*
- * ALCOR's GRU ASIC registers
- */
-#define GRU_INT_REQ                     (IDENT_ADDR + 0x8780000000UL)
-#define GRU_INT_MASK                    (IDENT_ADDR + 0x8780000040UL)
-#define GRU_INT_EDGE                    (IDENT_ADDR + 0x8780000080UL)
-#define GRU_INT_HILO                    (IDENT_ADDR + 0x87800000C0UL)
-#define GRU_INT_CLEAR                   (IDENT_ADDR + 0x8780000100UL)
-
-#define GRU_CACHE_CNFG                  (IDENT_ADDR + 0x8780000200UL)
-#define GRU_SCR                         (IDENT_ADDR + 0x8780000300UL)
-#define GRU_LED                         (IDENT_ADDR + 0x8780000800UL)
-#define GRU_RESET                       (IDENT_ADDR + 0x8780000900UL)
-
-#define ALCOR_GRU_INT_REQ_BITS          0x800fffffUL
-#define XLT_GRU_INT_REQ_BITS            0x80003fffUL
-#define GRU_INT_REQ_BITS                (alpha_mv.sys.cia.gru_int_req_bits+0)
-
-/*
- * PYXIS interrupt control registers
- */
-#define PYXIS_INT_REQ                   (IDENT_ADDR + 0x87A0000000UL)
-#define PYXIS_INT_MASK                  (IDENT_ADDR + 0x87A0000040UL)
-#define PYXIS_INT_HILO                  (IDENT_ADDR + 0x87A00000C0UL)
-#define PYXIS_INT_ROUTE                 (IDENT_ADDR + 0x87A0000140UL)
-#define PYXIS_GPO                       (IDENT_ADDR + 0x87A0000180UL)
-#define PYXIS_INT_CNFG                  (IDENT_ADDR + 0x87A00001C0UL)
-#define PYXIS_RT_COUNT                  (IDENT_ADDR + 0x87A0000200UL)
-#define PYXIS_INT_TIME                  (IDENT_ADDR + 0x87A0000240UL)
-#define PYXIS_IIC_CTRL                  (IDENT_ADDR + 0x87A00002C0UL)
-#define PYXIS_RESET                     (IDENT_ADDR + 0x8780000900UL)
-
-/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
-#define PYXIS_DAC_OFFSET                (1UL << 40)
-
-/*
- * Data structure for handling CIA machine checks.
- */
-
-/* System-specific info.  */
-struct el_CIA_sysdata_mcheck {
-        unsigned long   cpu_err0;
-        unsigned long   cpu_err1;
-        unsigned long   cia_err;
-        unsigned long   cia_stat;
-        unsigned long   err_mask;
-        unsigned long   cia_syn;
-        unsigned long   mem_err0;
-        unsigned long   mem_err1;
-        unsigned long   pci_err0;
-        unsigned long   pci_err1;
-        unsigned long   pci_err2;
-};
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-/* Do not touch, this should *NOT* be static inline */
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * CIA (the 2117x PCI/memory support chipset for the EV5 (21164)
- * series of processors uses a sparse address mapping scheme to
- * get at PCI memory and I/O.
- */
-
-/*
- * Memory functions.  64-bit and 32-bit accesses are done through
- * dense memory space, everything else through sparse space.
- *
- * For reading and writing 8 and 16 bit quantities we need to
- * go through one of the three sparse address mapping regions
- * and use the HAE_MEM CSR to provide some bits of the address.
- * The following few routines use only sparse address region 1
- * which gives 1Gbyte of accessible space which relates exactly
- * to the amount of PCI memory mapping *into* system address space.
- * See p 6-17 of the specification but it looks something like this:
- *
- * 21164 Address:
- *
- *          3         2         1
- * 9876543210987654321098765432109876543210
- * 1ZZZZ0.PCI.QW.Address............BBLL
- *
- * ZZ = SBZ
- * BB = Byte offset
- * LL = Transfer length
- *
- * PCI Address:
- *
- * 3         2         1
- * 10987654321098765432109876543210
- * HHH....PCI.QW.Address........ 00
- *
- * HHH = 31:29 HAE_MEM CSR
- *
- */
-
-#define vip     volatile int __force *
-#define vuip    volatile unsigned int __force *
-#define vulp    volatile unsigned long __force *
-
-__EXTERN_INLINE unsigned int cia_ioread8(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long result, base_and_type;
-
-        if (addr >= CIA_DENSE_MEM)
-                base_and_type = CIA_SPARSE_MEM + 0x00;
-        else
-                base_and_type = CIA_IO + 0x00;
-
-        /* We can use CIA_MEM_R1_MASK for io ports too, since it is large
-           enough to cover all io ports, and smaller than CIA_IO.  */
-        addr &= CIA_MEM_R1_MASK;
-        result = *(vip) ((addr << 5) + base_and_type);
-        return __kernel_extbl(result, addr & 3);
-}
-
-__EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long w, base_and_type;
-
-        if (addr >= CIA_DENSE_MEM)
-                base_and_type = CIA_SPARSE_MEM + 0x00;
-        else
-                base_and_type = CIA_IO + 0x00;
-
-        addr &= CIA_MEM_R1_MASK;
-        w = __kernel_insbl(b, addr & 3);
-        *(vuip) ((addr << 5) + base_and_type) = w;
-}
-
-__EXTERN_INLINE unsigned int cia_ioread16(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long result, base_and_type;
-
-        if (addr >= CIA_DENSE_MEM)
-                base_and_type = CIA_SPARSE_MEM + 0x08;
-        else
-                base_and_type = CIA_IO + 0x08;
-
-        addr &= CIA_MEM_R1_MASK;
-        result = *(vip) ((addr << 5) + base_and_type);
-        return __kernel_extwl(result, addr & 3);
-}
-
-__EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long w, base_and_type;
-
-        if (addr >= CIA_DENSE_MEM)
-                base_and_type = CIA_SPARSE_MEM + 0x08;
-        else
-                base_and_type = CIA_IO + 0x08;
-
-        addr &= CIA_MEM_R1_MASK;
-        w = __kernel_inswl(b, addr & 3);
-        *(vuip) ((addr << 5) + base_and_type) = w;
-}
-
-__EXTERN_INLINE unsigned int cia_ioread32(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        if (addr < CIA_DENSE_MEM)
-                addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
-        return *(vuip)addr;
-}
-
-__EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        if (addr < CIA_DENSE_MEM)
-                addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
-        *(vuip)addr = b;
-}
-
-__EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + CIA_IO);
-}
-
-__EXTERN_INLINE void __iomem *cia_ioremap(unsigned long addr,
-                                          unsigned long size)
-{
-        return (void __iomem *)(addr + CIA_DENSE_MEM);
-}
-
-__EXTERN_INLINE int cia_is_ioaddr(unsigned long addr)
-{
-        return addr >= IDENT_ADDR + 0x8000000000UL;
-}
-
-__EXTERN_INLINE int cia_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >= CIA_DENSE_MEM;
-}
-
-__EXTERN_INLINE void __iomem *cia_bwx_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + CIA_BW_IO);
-}
-
-__EXTERN_INLINE void __iomem *cia_bwx_ioremap(unsigned long addr,
-                                              unsigned long size)
-{
-        return (void __iomem *)(addr + CIA_BW_MEM);
-}
-
-__EXTERN_INLINE int cia_bwx_is_ioaddr(unsigned long addr)
-{
-        return addr >= IDENT_ADDR + 0x8000000000UL;
-}
-
-__EXTERN_INLINE int cia_bwx_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr < CIA_BW_IO;
-}
-
-#undef vip
-#undef vuip
-#undef vulp
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             cia
-#define cia_trivial_rw_bw       2
-#define cia_trivial_rw_lq       1
-#define cia_trivial_io_bw       0
-#define cia_trivial_io_lq       0
-#define cia_trivial_iounmap     1
-#include <asm/io_trivial.h>
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             cia_bwx
-#define cia_bwx_trivial_rw_bw   1
-#define cia_bwx_trivial_rw_lq   1
-#define cia_bwx_trivial_io_bw   1
-#define cia_bwx_trivial_io_lq   1
-#define cia_bwx_trivial_iounmap 1
-#include <asm/io_trivial.h>
-
-#undef __IO_PREFIX
-#ifdef CONFIG_ALPHA_PYXIS
-#define __IO_PREFIX             cia_bwx
-#else
-#define __IO_PREFIX             cia
-#endif
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_CIA__H__ */
diff --git a/include/asm-alpha/core_irongate.h b/include/asm-alpha/core_irongate.h
deleted file mode 100644
index 24b2db541501..000000000000
--- a/include/asm-alpha/core_irongate.h
+++ /dev/null
@@ -1,232 +0,0 @@
-#ifndef __ALPHA_IRONGATE__H__
-#define __ALPHA_IRONGATE__H__
-
-#include <linux/types.h>
-#include <asm/compiler.h>
-
-/*
- * IRONGATE is the internal name for the AMD-751 K7 core logic chipset
- * which provides memory controller and PCI access for NAUTILUS-based
- * EV6 (21264) systems.
- *
- * This file is based on:
- *
- * IronGate management library, (c) 1999 Alpha Processor, Inc.
- * Copyright (C) 1999 Alpha Processor, Inc.,
- *      (David Daniel, Stig Telfer, Soohoon Lee)
- */
-
-/*
- * The 21264 supports, and internally recognizes, a 44-bit physical
- * address space that is divided equally between memory address space
- * and I/O address space. Memory address space resides in the lower
- * half of the physical address space (PA[43]=0) and I/O address space
- * resides in the upper half of the physical address space (PA[43]=1).
- */
-
-/*
- * Irongate CSR map.  Some of the CSRs are 8 or 16 bits, but all access
- * through the routines given is 32-bit.
- *
- * The first 0x40 bytes are standard as per the PCI spec.
- */
-
-typedef volatile __u32  igcsr32;
-
-typedef struct {
-        igcsr32 dev_vendor;             /* 0x00 - device ID, vendor ID */
-        igcsr32 stat_cmd;               /* 0x04 - status, command */
-        igcsr32 class;                  /* 0x08 - class code, rev ID */
-        igcsr32 latency;                /* 0x0C - header type, PCI latency */
-        igcsr32 bar0;                   /* 0x10 - BAR0 - AGP */
-        igcsr32 bar1;                   /* 0x14 - BAR1 - GART */
-        igcsr32 bar2;                   /* 0x18 - Power Management reg block */
-
-        igcsr32 rsrvd0[6];              /* 0x1C-0x33 reserved */
-
-        igcsr32 capptr;                 /* 0x34 - Capabilities pointer */
-
-        igcsr32 rsrvd1[2];              /* 0x38-0x3F reserved */
-
-        igcsr32 bacsr10;                /* 0x40 - base address chip selects */
-        igcsr32 bacsr32;                /* 0x44 - base address chip selects */
-        igcsr32 bacsr54_eccms761;       /* 0x48 - 751: base addr. chip selects
-                                                  761: ECC, mode/status */
-
-        igcsr32 rsrvd2[1];              /* 0x4C-0x4F reserved */
-
-        igcsr32 drammap;                /* 0x50 - address mapping control */
-        igcsr32 dramtm;                 /* 0x54 - timing, driver strength */
-        igcsr32 dramms;                 /* 0x58 - DRAM mode/status */
-
-        igcsr32 rsrvd3[1];              /* 0x5C-0x5F reserved */
-
-        igcsr32 biu0;                   /* 0x60 - bus interface unit */
-        igcsr32 biusip;                 /* 0x64 - Serial initialisation pkt */
-
-        igcsr32 rsrvd4[2];              /* 0x68-0x6F reserved */
-
-        igcsr32 mro;                    /* 0x70 - memory request optimiser */
-
-        igcsr32 rsrvd5[3];              /* 0x74-0x7F reserved */
-
-        igcsr32 whami;                  /* 0x80 - who am I */
-        igcsr32 pciarb;                 /* 0x84 - PCI arbitration control */
-        igcsr32 pcicfg;                 /* 0x88 - PCI config status */
-
-        igcsr32 rsrvd6[4];              /* 0x8C-0x9B reserved */
-
-        igcsr32 pci_mem;                /* 0x9C - PCI top of memory,
-                                                  761 only */
-
-        /* AGP (bus 1) control registers */
-        igcsr32 agpcap;                 /* 0xA0 - AGP Capability Identifier */
-        igcsr32 agpstat;                /* 0xA4 - AGP status register */
-        igcsr32 agpcmd;                 /* 0xA8 - AGP control register */
-        igcsr32 agpva;                  /* 0xAC - AGP Virtual Address Space */
-        igcsr32 agpmode;                /* 0xB0 - AGP/GART mode control */
-} Irongate0;
-
-
-typedef struct {
-
-        igcsr32 dev_vendor;             /* 0x00 - Device and Vendor IDs */
-        igcsr32 stat_cmd;               /* 0x04 - Status and Command regs */
-        igcsr32 class;                  /* 0x08 - subclass, baseclass etc */
-        igcsr32 htype;                  /* 0x0C - header type (at 0x0E) */
-        igcsr32 rsrvd0[2];              /* 0x10-0x17 reserved */
-        igcsr32 busnos;                 /* 0x18 - Primary, secondary bus nos */
-        igcsr32 io_baselim_regs;        /* 0x1C - IO base, IO lim, AGP status */
-        igcsr32 mem_baselim;            /* 0x20 - memory base, memory lim */
-        igcsr32 pfmem_baselim;          /* 0x24 - prefetchable base, lim */
-        igcsr32 rsrvd1[2];              /* 0x28-0x2F reserved */
-        igcsr32 io_baselim;             /* 0x30 - IO base, IO limit */
-        igcsr32 rsrvd2[2];              /* 0x34-0x3B - reserved */
-        igcsr32 interrupt;              /* 0x3C - interrupt, PCI bridge ctrl */
-
-} Irongate1;
-
-extern igcsr32 *IronECC;
-
-/*
- * Memory spaces:
- */
-
-/* Irongate is consistent with a subset of the Tsunami memory map */
-#ifdef USE_48_BIT_KSEG
-#define IRONGATE_BIAS 0x80000000000UL
-#else
-#define IRONGATE_BIAS 0x10000000000UL
-#endif
-
-
-#define IRONGATE_MEM            (IDENT_ADDR | IRONGATE_BIAS | 0x000000000UL)
-#define IRONGATE_IACK_SC        (IDENT_ADDR | IRONGATE_BIAS | 0x1F8000000UL)
-#define IRONGATE_IO             (IDENT_ADDR | IRONGATE_BIAS | 0x1FC000000UL)
-#define IRONGATE_CONF           (IDENT_ADDR | IRONGATE_BIAS | 0x1FE000000UL)
-
-/*
- * PCI Configuration space accesses are formed like so:
- *
- * 0x1FE << 24 |  : 2 2 2 2 1 1 1 1 : 1 1 1 1 1 1 0 0 : 0 0 0 0 0 0 0 0 :
- *                : 3 2 1 0 9 8 7 6 : 5 4 3 2 1 0 9 8 : 7 6 5 4 3 2 1 0 :
- *                  ---bus numer---   -device-- -fun-   ---register----
- */
-
-#define IGCSR(dev,fun,reg)      ( IRONGATE_CONF | \
-                                ((dev)<<11) | \
-                                ((fun)<<8) | \
-                                (reg) )
-
-#define IRONGATE0               ((Irongate0 *) IGCSR(0, 0, 0))
-#define IRONGATE1               ((Irongate1 *) IGCSR(1, 0, 0))
-
-/*
- * Data structure for handling IRONGATE machine checks:
- * This is the standard OSF logout frame
- */
-
-#define SCB_Q_SYSERR    0x620                   /* OSF definitions */
-#define SCB_Q_PROCERR   0x630
-#define SCB_Q_SYSMCHK   0x660
-#define SCB_Q_PROCMCHK  0x670
-
-struct el_IRONGATE_sysdata_mcheck {
-        __u32 FrameSize;                 /* Bytes, including this field */
-        __u32 FrameFlags;                /* <31> = Retry, <30> = Second Error */
-        __u32 CpuOffset;                 /* Offset to CPU-specific into */
-        __u32 SystemOffset;              /* Offset to system-specific info */
-        __u32 MCHK_Code;
-        __u32 MCHK_Frame_Rev;
-        __u64 I_STAT;
-        __u64 DC_STAT;
-        __u64 C_ADDR;
-        __u64 DC1_SYNDROME;
-        __u64 DC0_SYNDROME;
-        __u64 C_STAT;
-        __u64 C_STS;
-        __u64 RESERVED0;
-        __u64 EXC_ADDR;
-        __u64 IER_CM;
-        __u64 ISUM;
-        __u64 MM_STAT;
-        __u64 PAL_BASE;
-        __u64 I_CTL;
-        __u64 PCTX;
-};
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * IRONGATE (AMD-751) PCI/memory support chip for the EV6 (21264) and
- * K7 can only use linear accesses to get at PCI memory and I/O spaces.
- */
-
-/*
- * Memory functions.  All accesses are done through linear space.
- */
-
-__EXTERN_INLINE void __iomem *irongate_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + IRONGATE_IO);
-}
-
-extern void __iomem *irongate_ioremap(unsigned long addr, unsigned long size);
-extern void irongate_iounmap(volatile void __iomem *addr);
-
-__EXTERN_INLINE int irongate_is_ioaddr(unsigned long addr)
-{
-        return addr >= IRONGATE_MEM;
-}
-
-__EXTERN_INLINE int irongate_is_mmio(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr;
-        return addr < IRONGATE_IO || addr >= IRONGATE_CONF;
-}
-
-#undef __IO_PREFIX
-#define __IO_PREFIX                     irongate
-#define irongate_trivial_rw_bw          1
-#define irongate_trivial_rw_lq          1
-#define irongate_trivial_io_bw          1
-#define irongate_trivial_io_lq          1
-#define irongate_trivial_iounmap        0
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_IRONGATE__H__ */
diff --git a/include/asm-alpha/core_lca.h b/include/asm-alpha/core_lca.h
deleted file mode 100644
index f7cb4b460954..000000000000
--- a/include/asm-alpha/core_lca.h
+++ /dev/null
@@ -1,361 +0,0 @@
-#ifndef __ALPHA_LCA__H__
-#define __ALPHA_LCA__H__
-
-#include <asm/system.h>
-#include <asm/compiler.h>
-
-/*
- * Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068,
- * for example).
- *
- * This file is based on:
- *
- *      DECchip 21066 and DECchip 21068 Alpha AXP Microprocessors
- *      Hardware Reference Manual; Digital Equipment Corp.; May 1994;
- *      Maynard, MA; Order Number: EC-N2681-71.
- */
-
-/*
- * NOTE: The LCA uses a Host Address Extension (HAE) register to access
- *       PCI addresses that are beyond the first 27 bits of address
- *       space.  Updating the HAE requires an external cycle (and
- *       a memory barrier), which tends to be slow.  Instead of updating
- *       it on each sparse memory access, we keep the current HAE value
- *       cached in variable cache_hae.  Only if the cached HAE differs
- *       from the desired HAE value do we actually updated HAE register.
- *       The HAE register is preserved by the interrupt handler entry/exit
- *       code, so this scheme works even in the presence of interrupts.
- *
- * Dense memory space doesn't require the HAE, but is restricted to
- * aligned 32 and 64 bit accesses.  Special Cycle and Interrupt
- * Acknowledge cycles may also require the use of the HAE.  The LCA
- * limits I/O address space to the bottom 24 bits of address space,
- * but this easily covers the 16 bit ISA I/O address space.
- */
-
-/*
- * NOTE 2! The memory operations do not set any memory barriers, as
- * it's not needed for cases like a frame buffer that is essentially
- * memory-like.  You need to do them by hand if the operations depend
- * on ordering.
- *
- * Similarly, the port I/O operations do a "mb" only after a write
- * operation: if an mb is needed before (as in the case of doing
- * memory mapped I/O first, and then a port I/O operation to the same
- * device), it needs to be done by hand.
- *
- * After the above has bitten me 100 times, I'll give up and just do
- * the mb all the time, but right now I'm hoping this will work out.
- * Avoiding mb's may potentially be a noticeable speed improvement,
- * but I can't honestly say I've tested it.
- *
- * Handling interrupts that need to do mb's to synchronize to
- * non-interrupts is another fun race area.  Don't do it (because if
- * you do, I'll have to do *everything* with interrupts disabled,
- * ugh).
- */
-
-/*
- * Memory Controller registers:
- */
-#define LCA_MEM_BCR0            (IDENT_ADDR + 0x120000000UL)
-#define LCA_MEM_BCR1            (IDENT_ADDR + 0x120000008UL)
-#define LCA_MEM_BCR2            (IDENT_ADDR + 0x120000010UL)
-#define LCA_MEM_BCR3            (IDENT_ADDR + 0x120000018UL)
-#define LCA_MEM_BMR0            (IDENT_ADDR + 0x120000020UL)
-#define LCA_MEM_BMR1            (IDENT_ADDR + 0x120000028UL)
-#define LCA_MEM_BMR2            (IDENT_ADDR + 0x120000030UL)
-#define LCA_MEM_BMR3            (IDENT_ADDR + 0x120000038UL)
-#define LCA_MEM_BTR0            (IDENT_ADDR + 0x120000040UL)
-#define LCA_MEM_BTR1            (IDENT_ADDR + 0x120000048UL)
-#define LCA_MEM_BTR2            (IDENT_ADDR + 0x120000050UL)
-#define LCA_MEM_BTR3            (IDENT_ADDR + 0x120000058UL)
-#define LCA_MEM_GTR             (IDENT_ADDR + 0x120000060UL)
-#define LCA_MEM_ESR             (IDENT_ADDR + 0x120000068UL)
-#define LCA_MEM_EAR             (IDENT_ADDR + 0x120000070UL)
-#define LCA_MEM_CAR             (IDENT_ADDR + 0x120000078UL)
-#define LCA_MEM_VGR             (IDENT_ADDR + 0x120000080UL)
-#define LCA_MEM_PLM             (IDENT_ADDR + 0x120000088UL)
-#define LCA_MEM_FOR             (IDENT_ADDR + 0x120000090UL)
-
-/*
- * I/O Controller registers:
- */
-#define LCA_IOC_HAE             (IDENT_ADDR + 0x180000000UL)
-#define LCA_IOC_CONF            (IDENT_ADDR + 0x180000020UL)
-#define LCA_IOC_STAT0           (IDENT_ADDR + 0x180000040UL)
-#define LCA_IOC_STAT1           (IDENT_ADDR + 0x180000060UL)
-#define LCA_IOC_TBIA            (IDENT_ADDR + 0x180000080UL)
-#define LCA_IOC_TB_ENA          (IDENT_ADDR + 0x1800000a0UL)
-#define LCA_IOC_SFT_RST         (IDENT_ADDR + 0x1800000c0UL)
-#define LCA_IOC_PAR_DIS         (IDENT_ADDR + 0x1800000e0UL)
-#define LCA_IOC_W_BASE0         (IDENT_ADDR + 0x180000100UL)
-#define LCA_IOC_W_BASE1         (IDENT_ADDR + 0x180000120UL)
-#define LCA_IOC_W_MASK0         (IDENT_ADDR + 0x180000140UL)
-#define LCA_IOC_W_MASK1         (IDENT_ADDR + 0x180000160UL)
-#define LCA_IOC_T_BASE0         (IDENT_ADDR + 0x180000180UL)
-#define LCA_IOC_T_BASE1         (IDENT_ADDR + 0x1800001a0UL)
-#define LCA_IOC_TB_TAG0         (IDENT_ADDR + 0x188000000UL)
-#define LCA_IOC_TB_TAG1         (IDENT_ADDR + 0x188000020UL)
-#define LCA_IOC_TB_TAG2         (IDENT_ADDR + 0x188000040UL)
-#define LCA_IOC_TB_TAG3         (IDENT_ADDR + 0x188000060UL)
-#define LCA_IOC_TB_TAG4         (IDENT_ADDR + 0x188000070UL)
-#define LCA_IOC_TB_TAG5         (IDENT_ADDR + 0x1880000a0UL)
-#define LCA_IOC_TB_TAG6         (IDENT_ADDR + 0x1880000c0UL)
-#define LCA_IOC_TB_TAG7         (IDENT_ADDR + 0x1880000e0UL)
-
-/*
- * Memory spaces:
- */
-#define LCA_IACK_SC             (IDENT_ADDR + 0x1a0000000UL)
-#define LCA_CONF                (IDENT_ADDR + 0x1e0000000UL)
-#define LCA_IO                  (IDENT_ADDR + 0x1c0000000UL)
-#define LCA_SPARSE_MEM          (IDENT_ADDR + 0x200000000UL)
-#define LCA_DENSE_MEM           (IDENT_ADDR + 0x300000000UL)
-
-/*
- * Bit definitions for I/O Controller status register 0:
- */
-#define LCA_IOC_STAT0_CMD               0xf
-#define LCA_IOC_STAT0_ERR               (1<<4)
-#define LCA_IOC_STAT0_LOST              (1<<5)
-#define LCA_IOC_STAT0_THIT              (1<<6)
-#define LCA_IOC_STAT0_TREF              (1<<7)
-#define LCA_IOC_STAT0_CODE_SHIFT        8
-#define LCA_IOC_STAT0_CODE_MASK         0x7
-#define LCA_IOC_STAT0_P_NBR_SHIFT       13
-#define LCA_IOC_STAT0_P_NBR_MASK        0x7ffff
-
-#define LCA_HAE_ADDRESS         LCA_IOC_HAE
-
-/* LCA PMR Power Management register defines */
-#define LCA_PMR_ADDR    (IDENT_ADDR + 0x120000098UL)
-#define LCA_PMR_PDIV    0x7                     /* Primary clock divisor */
-#define LCA_PMR_ODIV    0x38                    /* Override clock divisor */
-#define LCA_PMR_INTO    0x40                    /* Interrupt override */
-#define LCA_PMR_DMAO    0x80                    /* DMA override */
-#define LCA_PMR_OCCEB   0xffff0000L             /* Override cycle counter - even bits */
-#define LCA_PMR_OCCOB   0xffff000000000000L     /* Override cycle counter - even bits */
-#define LCA_PMR_PRIMARY_MASK    0xfffffffffffffff8L
-
-/* LCA PMR Macros */
-
-#define LCA_READ_PMR        (*(volatile unsigned long *)LCA_PMR_ADDR)
-#define LCA_WRITE_PMR(d)    (*((volatile unsigned long *)LCA_PMR_ADDR) = (d))
-
-#define LCA_GET_PRIMARY(r)  ((r) & LCA_PMR_PDIV)
-#define LCA_GET_OVERRIDE(r) (((r) >> 3) & LCA_PMR_PDIV)
-#define LCA_SET_PRIMARY_CLOCK(r, c) ((r) = (((r) & LCA_PMR_PRIMARY_MASK)|(c)))
-
-/* LCA PMR Divisor values */
-#define LCA_PMR_DIV_1   0x0
-#define LCA_PMR_DIV_1_5 0x1
-#define LCA_PMR_DIV_2   0x2
-#define LCA_PMR_DIV_4   0x3
-#define LCA_PMR_DIV_8   0x4
-#define LCA_PMR_DIV_16  0x5
-#define LCA_PMR_DIV_MIN DIV_1
-#define LCA_PMR_DIV_MAX DIV_16
-
-
-/*
- * Data structure for handling LCA machine checks.  Correctable errors
- * result in a short logout frame, uncorrectable ones in a long one.
- */
-struct el_lca_mcheck_short {
-        struct el_common        h;              /* common logout header */
-        unsigned long           esr;            /* error-status register */
-        unsigned long           ear;            /* error-address register */
-        unsigned long           dc_stat;        /* dcache status register */
-        unsigned long           ioc_stat0;      /* I/O controller status register 0 */
-        unsigned long           ioc_stat1;      /* I/O controller status register 1 */
-};
-
-struct el_lca_mcheck_long {
-        struct el_common        h;              /* common logout header */
-        unsigned long           pt[31];         /* PAL temps */
-        unsigned long           exc_addr;       /* exception address */
-        unsigned long           pad1[3];
-        unsigned long           pal_base;       /* PALcode base address */
-        unsigned long           hier;           /* hw interrupt enable */
-        unsigned long           hirr;           /* hw interrupt request */
-        unsigned long           mm_csr;         /* MMU control & status */
-        unsigned long           dc_stat;        /* data cache status */
-        unsigned long           dc_addr;        /* data cache addr register */
-        unsigned long           abox_ctl;       /* address box control register */
-        unsigned long           esr;            /* error status register */
-        unsigned long           ear;            /* error address register */
-        unsigned long           car;            /* cache control register */
-        unsigned long           ioc_stat0;      /* I/O controller status register 0 */
-        unsigned long           ioc_stat1;      /* I/O controller status register 1 */
-        unsigned long           va;             /* virtual address register */
-};
-
-union el_lca {
-        struct el_common *              c;
-        struct el_lca_mcheck_long *     l;
-        struct el_lca_mcheck_short *    s;
-};
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * Unlike Jensen, the Noname machines have no concept of local
- * I/O---everything goes over the PCI bus.
- *
- * There is plenty room for optimization here.  In particular,
- * the Alpha's insb/insw/extb/extw should be useful in moving
- * data to/from the right byte-lanes.
- */
-
-#define vip     volatile int __force *
-#define vuip    volatile unsigned int __force *
-#define vulp    volatile unsigned long __force *
-
-#define LCA_SET_HAE                                             \
-        do {                                                    \
-                if (addr >= (1UL << 24)) {                      \
-                        unsigned long msb = addr & 0xf8000000;  \
-                        addr -= msb;                            \
-                        set_hae(msb);                           \
-                }                                               \
-        } while (0)
-
-
-__EXTERN_INLINE unsigned int lca_ioread8(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long result, base_and_type;
-
-        if (addr >= LCA_DENSE_MEM) {
-                addr -= LCA_DENSE_MEM;
-                LCA_SET_HAE;
-                base_and_type = LCA_SPARSE_MEM + 0x00;
-        } else {
-                addr -= LCA_IO;
-                base_and_type = LCA_IO + 0x00;
-        }
-
-        result = *(vip) ((addr << 5) + base_and_type);
-        return __kernel_extbl(result, addr & 3);
-}
-
-__EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long w, base_and_type;
-
-        if (addr >= LCA_DENSE_MEM) {
-                addr -= LCA_DENSE_MEM;
-                LCA_SET_HAE;
-                base_and_type = LCA_SPARSE_MEM + 0x00;
-        } else {
-                addr -= LCA_IO;
-                base_and_type = LCA_IO + 0x00;
-        }
-
-        w = __kernel_insbl(b, addr & 3);
-        *(vuip) ((addr << 5) + base_and_type) = w;
-}
-
-__EXTERN_INLINE unsigned int lca_ioread16(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long result, base_and_type;
-
-        if (addr >= LCA_DENSE_MEM) {
-                addr -= LCA_DENSE_MEM;
-                LCA_SET_HAE;
-                base_and_type = LCA_SPARSE_MEM + 0x08;
-        } else {
-                addr -= LCA_IO;
-                base_and_type = LCA_IO + 0x08;
-        }
-
-        result = *(vip) ((addr << 5) + base_and_type);
-        return __kernel_extwl(result, addr & 3);
-}
-
-__EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long w, base_and_type;
-
-        if (addr >= LCA_DENSE_MEM) {
-                addr -= LCA_DENSE_MEM;
-                LCA_SET_HAE;
-                base_and_type = LCA_SPARSE_MEM + 0x08;
-        } else {
-                addr -= LCA_IO;
-                base_and_type = LCA_IO + 0x08;
-        }
-
-        w = __kernel_inswl(b, addr & 3);
-        *(vuip) ((addr << 5) + base_and_type) = w;
-}
-
-__EXTERN_INLINE unsigned int lca_ioread32(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        if (addr < LCA_DENSE_MEM)
-                addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
-        return *(vuip)addr;
-}
-
-__EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        if (addr < LCA_DENSE_MEM)
-                addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
-        *(vuip)addr = b;
-}
-
-__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + LCA_IO);
-}
-
-__EXTERN_INLINE void __iomem *lca_ioremap(unsigned long addr,
-                                          unsigned long size)
-{
-        return (void __iomem *)(addr + LCA_DENSE_MEM);
-}
-
-__EXTERN_INLINE int lca_is_ioaddr(unsigned long addr)
-{
-        return addr >= IDENT_ADDR + 0x120000000UL;
-}
-
-__EXTERN_INLINE int lca_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >= LCA_DENSE_MEM;
-}
-
-#undef vip
-#undef vuip
-#undef vulp
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             lca
-#define lca_trivial_rw_bw       2
-#define lca_trivial_rw_lq       1
-#define lca_trivial_io_bw       0
-#define lca_trivial_io_lq       0
-#define lca_trivial_iounmap     1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_LCA__H__ */
diff --git a/include/asm-alpha/core_marvel.h b/include/asm-alpha/core_marvel.h
deleted file mode 100644
index 30d55fe7aaf6..000000000000
--- a/include/asm-alpha/core_marvel.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Marvel systems use the IO7 I/O chip provides PCI/PCIX/AGP access
- *
- * This file is based on:
- *
- * Marvel / EV7 System Programmer's Manual
- * Revision 1.00
- * 14 May 2001
- */
-
-#ifndef __ALPHA_MARVEL__H__
-#define __ALPHA_MARVEL__H__
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/spinlock.h>
-
-#include <asm/compiler.h>
-
-#define MARVEL_MAX_PIDS          32 /* as long as we rely on 43-bit superpage */
-#define MARVEL_IRQ_VEC_PE_SHIFT (10)
-#define MARVEL_IRQ_VEC_IRQ_MASK ((1 << MARVEL_IRQ_VEC_PE_SHIFT) - 1)
-#define MARVEL_NR_IRQS          \
-        (16 + (MARVEL_MAX_PIDS * (1 << MARVEL_IRQ_VEC_PE_SHIFT)))
-
-/*
- * EV7 RBOX Registers
- */
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(16)));
-} ev7_csr;
-
-typedef struct {
-        ev7_csr RBOX_CFG;               /* 0x0000 */
-        ev7_csr RBOX_NSVC;
-        ev7_csr RBOX_EWVC;
-        ev7_csr RBOX_WHAMI;
-        ev7_csr RBOX_TCTL;              /* 0x0040 */
-        ev7_csr RBOX_INT;
-        ev7_csr RBOX_IMASK;
-        ev7_csr RBOX_IREQ;
-        ev7_csr RBOX_INTQ;              /* 0x0080 */
-        ev7_csr RBOX_INTA;
-        ev7_csr RBOX_IT;
-        ev7_csr RBOX_SCRATCH1;
-        ev7_csr RBOX_SCRATCH2;          /* 0x00c0 */
-        ev7_csr RBOX_L_ERR;
-} ev7_csrs;
-
-/*
- * EV7 CSR addressing macros
- */
-#define EV7_MASK40(addr)        ((addr) & ((1UL << 41) - 1))
-#define EV7_KERN_ADDR(addr)     ((void *)(IDENT_ADDR | EV7_MASK40(addr)))
-
-#define EV7_PE_MASK             0x1ffUL /* 9 bits ( 256 + mem/io ) */
-#define EV7_IPE(pe)             ((~((long)(pe)) & EV7_PE_MASK) << 35)
-
-#define EV7_CSR_PHYS(pe, off)   (EV7_IPE(pe) | (0x7FFCUL << 20) | (off))
-#define EV7_CSRS_PHYS(pe)       (EV7_CSR_PHYS(pe, 0UL))
-
-#define EV7_CSR_KERN(pe, off)   (EV7_KERN_ADDR(EV7_CSR_PHYS(pe, off)))
-#define EV7_CSRS_KERN(pe)       (EV7_KERN_ADDR(EV7_CSRS_PHYS(pe)))
-
-#define EV7_CSR_OFFSET(name)    ((unsigned long)&((ev7_csrs *)NULL)->name.csr)
-
-/*
- * IO7 registers
- */
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(64)));
-} io7_csr;
-
-typedef struct {
-        /* I/O Port Control Registers */
-        io7_csr POx_CTRL;               /* 0x0000 */
-        io7_csr POx_CACHE_CTL;
-        io7_csr POx_TIMER;
-        io7_csr POx_IO_ADR_EXT;
-        io7_csr POx_MEM_ADR_EXT;        /* 0x0100 */
-        io7_csr POx_XCAL_CTRL;
-        io7_csr rsvd1[2];       /* ?? spec doesn't show 0x180 */
-        io7_csr POx_DM_SOURCE;          /* 0x0200 */
-        io7_csr POx_DM_DEST;
-        io7_csr POx_DM_SIZE;
-        io7_csr POx_DM_CTRL;
-        io7_csr rsvd2[4];               /* 0x0300 */
-
-        /* AGP Control Registers -- port 3 only */
-        io7_csr AGP_CAP_ID;             /* 0x0400 */
-        io7_csr AGP_STAT;
-        io7_csr AGP_CMD;
-        io7_csr rsvd3;
-
-        /* I/O Port Monitor Registers */
-        io7_csr POx_MONCTL;             /* 0x0500 */
-        io7_csr POx_CTRA;
-        io7_csr POx_CTRB;
-        io7_csr POx_CTR56;
-        io7_csr POx_SCRATCH;            /* 0x0600 */
-        io7_csr POx_XTRA_A;
-        io7_csr POx_XTRA_TS;
-        io7_csr POx_XTRA_Z;
-        io7_csr rsvd4;                  /* 0x0700 */
-        io7_csr POx_THRESHA;
-        io7_csr POx_THRESHB;
-        io7_csr rsvd5[33];
-
-        /* System Address Space Window Control Registers */
-
-        io7_csr POx_WBASE[4];           /* 0x1000 */
-        io7_csr POx_WMASK[4];
-        io7_csr POx_TBASE[4];
-        io7_csr POx_SG_TBIA;
-        io7_csr POx_MSI_WBASE;
-        io7_csr rsvd6[50];
-
-        /* I/O Port Error Registers */
-        io7_csr POx_ERR_SUM;
-        io7_csr POx_FIRST_ERR;
-        io7_csr POx_MSK_HEI;
-        io7_csr POx_TLB_ERR;
-        io7_csr POx_SPL_COMPLT;
-        io7_csr POx_TRANS_SUM;
-        io7_csr POx_FRC_PCI_ERR;
-        io7_csr POx_MULT_ERR;
-        io7_csr rsvd7[8];
-
-        /* I/O Port End of Interrupt Registers */
-        io7_csr EOI_DAT;
-        io7_csr rsvd8[7];
-        io7_csr POx_IACK_SPECIAL;
-        io7_csr rsvd9[103];
-} io7_ioport_csrs;
-
-typedef struct {
-        io7_csr IO_ASIC_REV;            /* 0x30.0000 */
-        io7_csr IO_SYS_REV;
-        io7_csr SER_CHAIN3;
-        io7_csr PO7_RST1;
-        io7_csr PO7_RST2;               /* 0x30.0100 */
-        io7_csr POx_RST[4];
-        io7_csr IO7_DWNH;
-        io7_csr IO7_MAF;
-        io7_csr IO7_MAF_TO;
-        io7_csr IO7_ACC_CLUMP;          /* 0x30.0300 */
-        io7_csr IO7_PMASK;
-        io7_csr IO7_IOMASK;
-        io7_csr IO7_UPH;
-        io7_csr IO7_UPH_TO;             /* 0x30.0400 */
-        io7_csr RBX_IREQ_OFF;
-        io7_csr RBX_INTA_OFF;
-        io7_csr INT_RTY;
-        io7_csr PO7_MONCTL;             /* 0x30.0500 */
-        io7_csr PO7_CTRA;
-        io7_csr PO7_CTRB;
-        io7_csr PO7_CTR56;
-        io7_csr PO7_SCRATCH;            /* 0x30.0600 */
-        io7_csr PO7_XTRA_A;
-        io7_csr PO7_XTRA_TS;
-        io7_csr PO7_XTRA_Z;
-        io7_csr PO7_PMASK;              /* 0x30.0700 */
-        io7_csr PO7_THRESHA;
-        io7_csr PO7_THRESHB;
-        io7_csr rsvd1[97];
-        io7_csr PO7_ERROR_SUM;          /* 0x30.2000 */
-        io7_csr PO7_BHOLE_MASK;
-        io7_csr PO7_HEI_MSK;
-        io7_csr PO7_CRD_MSK;
-        io7_csr PO7_UNCRR_SYM;          /* 0x30.2100 */
-        io7_csr PO7_CRRCT_SYM;
-        io7_csr PO7_ERR_PKT[2];
-        io7_csr PO7_UGBGE_SYM;          /* 0x30.2200 */
-        io7_csr rsbv2[887];
-        io7_csr PO7_LSI_CTL[128];       /* 0x31.0000 */
-        io7_csr rsvd3[123];
-        io7_csr HLT_CTL;                /* 0x31.3ec0 */
-        io7_csr HPI_CTL;                /* 0x31.3f00 */
-        io7_csr CRD_CTL;
-        io7_csr STV_CTL;
-        io7_csr HEI_CTL;
-        io7_csr PO7_MSI_CTL[16];        /* 0x31.4000 */
-        io7_csr rsvd4[240];
-
-        /*
-         * Interrupt Diagnostic / Test
-         */
-        struct {
-                io7_csr INT_PND;
-                io7_csr INT_CLR;
-                io7_csr INT_EOI;
-                io7_csr rsvd[29];
-        } INT_DIAG[4];
-        io7_csr rsvd5[125];             /* 0x31.a000 */
-        io7_csr MISC_PND;               /* 0x31.b800 */
-        io7_csr rsvd6[31];
-        io7_csr MSI_PND[16];            /* 0x31.c000 */
-        io7_csr rsvd7[16];
-        io7_csr MSI_CLR[16];            /* 0x31.c800 */
-} io7_port7_csrs;
-
-/* 
- * IO7 DMA Window Base register (POx_WBASEx)
- */
-#define wbase_m_ena  0x1
-#define wbase_m_sg   0x2
-#define wbase_m_dac  0x4
-#define wbase_m_addr 0xFFF00000
-union IO7_POx_WBASE {
-        struct {
-                unsigned ena : 1;       /* <0>                  */
-                unsigned sg : 1;        /* <1>                  */
-                unsigned dac : 1;       /* <2> -- window 3 only */
-                unsigned rsvd1 : 17; 
-                unsigned addr : 12;     /* <31:20>              */
-                unsigned rsvd2 : 32;
-        } bits;
-        unsigned as_long[2];
-        unsigned as_quad;
-};
-
-/*
- * IO7 IID (Interrupt IDentifier) format
- *
- * For level-sensative interrupts, int_num is encoded as:
- *
- *      bus/port        slot/device     INTx
- *      <7:5>           <4:2>           <1:0>
- */
-union IO7_IID {
-        struct {
-                unsigned int_num : 9;           /* <8:0>        */
-                unsigned tpu_mask : 4;          /* <12:9> rsvd  */
-                unsigned msi : 1;               /* 13           */
-                unsigned ipe : 10;              /* <23:14>      */
-                unsigned long rsvd : 40;                
-        } bits;
-        unsigned int as_long[2];
-        unsigned long as_quad;
-};
-
-/*
- * IO7 addressing macros
- */
-#define IO7_KERN_ADDR(addr)     (EV7_KERN_ADDR(addr))
-
-#define IO7_PORT_MASK           0x07UL  /* 3 bits of port          */
-
-#define IO7_IPE(pe)             (EV7_IPE(pe))
-#define IO7_IPORT(port)         ((~((long)(port)) & IO7_PORT_MASK) << 32)
-
-#define IO7_HOSE(pe, port)      (IO7_IPE(pe) | IO7_IPORT(port))
-
-#define IO7_MEM_PHYS(pe, port)  (IO7_HOSE(pe, port) | 0x00000000UL)
-#define IO7_CONF_PHYS(pe, port) (IO7_HOSE(pe, port) | 0xFE000000UL)
-#define IO7_IO_PHYS(pe, port)   (IO7_HOSE(pe, port) | 0xFF000000UL)
-#define IO7_CSR_PHYS(pe, port, off) \
-                                (IO7_HOSE(pe, port) | 0xFF800000UL | (off))
-#define IO7_CSRS_PHYS(pe, port) (IO7_CSR_PHYS(pe, port, 0UL))
-#define IO7_PORT7_CSRS_PHYS(pe) (IO7_CSR_PHYS(pe, 7, 0x300000UL))
-
-#define IO7_MEM_KERN(pe, port)      (IO7_KERN_ADDR(IO7_MEM_PHYS(pe, port)))
-#define IO7_CONF_KERN(pe, port)     (IO7_KERN_ADDR(IO7_CONF_PHYS(pe, port)))
-#define IO7_IO_KERN(pe, port)       (IO7_KERN_ADDR(IO7_IO_PHYS(pe, port)))
-#define IO7_CSR_KERN(pe, port, off) (IO7_KERN_ADDR(IO7_CSR_PHYS(pe,port,off)))
-#define IO7_CSRS_KERN(pe, port)     (IO7_KERN_ADDR(IO7_CSRS_PHYS(pe, port)))
-#define IO7_PORT7_CSRS_KERN(pe)     (IO7_KERN_ADDR(IO7_PORT7_CSRS_PHYS(pe)))
-
-#define IO7_PLL_RNGA(pll)       (((pll) >> 3) & 0x7)
-#define IO7_PLL_RNGB(pll)       (((pll) >> 6) & 0x7)
-
-#define IO7_MEM_SPACE           (2UL * 1024 * 1024 * 1024)      /* 2GB MEM */
-#define IO7_IO_SPACE            (8UL * 1024 * 1024)             /* 8MB I/O */
-
- 
-/* 
- * Offset between ram physical addresses and pci64 DAC addresses
- */
-#define IO7_DAC_OFFSET          (1UL << 49)
-
-/*
- * This is needed to satisify the IO() macro used in initializing the machvec
- */
-#define MARVEL_IACK_SC                                                  \
-        ((unsigned long)                                                \
-         (&(((io7_ioport_csrs *)IO7_CSRS_KERN(0, 0))->POx_IACK_SPECIAL)))
-
-#ifdef __KERNEL__
-
-/*
- * IO7 structs
- */
-#define IO7_NUM_PORTS 4
-#define IO7_AGP_PORT  3
-
-struct io7_port {
-        struct io7 *io7;
-        struct pci_controller *hose;
-
-        int enabled;
-        unsigned int port;
-        io7_ioport_csrs *csrs;
-
-        unsigned long saved_wbase[4];
-        unsigned long saved_wmask[4];
-        unsigned long saved_tbase[4];
-};
-
-struct io7 {
-        struct io7 *next;
-
-        unsigned int pe;
-        io7_port7_csrs *csrs;
-        struct io7_port ports[IO7_NUM_PORTS];
-
-        spinlock_t irq_lock;
-};
-
-#ifndef __EXTERN_INLINE
-# define __EXTERN_INLINE extern inline
-# define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions. All access through linear space.
- */
-
-/*
- * Memory functions.  All accesses through linear space.
- */
-
-#define vucp    volatile unsigned char __force *
-#define vusp    volatile unsigned short __force *
-
-extern unsigned int marvel_ioread8(void __iomem *);
-extern void marvel_iowrite8(u8 b, void __iomem *);
-
-__EXTERN_INLINE unsigned int marvel_ioread16(void __iomem *addr)
-{
-        return __kernel_ldwu(*(vusp)addr);
-}
-
-__EXTERN_INLINE void marvel_iowrite16(u16 b, void __iomem *addr)
-{
-        __kernel_stw(b, *(vusp)addr);
-}
-
-extern void __iomem *marvel_ioremap(unsigned long addr, unsigned long size);
-extern void marvel_iounmap(volatile void __iomem *addr);
-extern void __iomem *marvel_ioportmap (unsigned long addr);
-
-__EXTERN_INLINE int marvel_is_ioaddr(unsigned long addr)
-{
-        return (addr >> 40) & 1;
-}
-
-extern int marvel_is_mmio(const volatile void __iomem *);
-
-#undef vucp
-#undef vusp
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             marvel
-#define marvel_trivial_rw_bw    1
-#define marvel_trivial_rw_lq    1
-#define marvel_trivial_io_bw    0
-#define marvel_trivial_io_lq    1
-#define marvel_trivial_iounmap  0
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-# undef __EXTERN_INLINE
-# undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_MARVEL__H__ */
diff --git a/include/asm-alpha/core_mcpcia.h b/include/asm-alpha/core_mcpcia.h
deleted file mode 100644
index acf55b483472..000000000000
--- a/include/asm-alpha/core_mcpcia.h
+++ /dev/null
@@ -1,381 +0,0 @@
-#ifndef __ALPHA_MCPCIA__H__
-#define __ALPHA_MCPCIA__H__
-
-/* Define to experiment with fitting everything into one 128MB HAE window.
-   One window per bus, that is.  */
-#define MCPCIA_ONE_HAE_WINDOW 1
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/compiler.h>
-
-/*
- * MCPCIA is the internal name for a core logic chipset which provides
- * PCI access for the RAWHIDE family of systems.
- *
- * This file is based on:
- *
- * RAWHIDE System Programmer's Manual
- * 16-May-96
- * Rev. 1.4
- *
- */
-
-/*------------------------------------------------------------------------**
-**                                                                        **
-**  I/O procedures                                                        **
-**                                                                        **
-**      inport[b|w|t|l], outport[b|w|t|l] 8:16:24:32 IO xfers             **
-**      inportbxt: 8 bits only                                            **
-**      inport:    alias of inportw                                       **
-**      outport:   alias of outportw                                      **
-**                                                                        **
-**      inmem[b|w|t|l], outmem[b|w|t|l] 8:16:24:32 ISA memory xfers       **
-**      inmembxt: 8 bits only                                             **
-**      inmem:    alias of inmemw                                         **
-**      outmem:   alias of outmemw                                        **
-**                                                                        **
-**------------------------------------------------------------------------*/
-
-
-/* MCPCIA ADDRESS BIT DEFINITIONS
- *
- *  3333 3333 3322 2222 2222 1111 1111 11
- *  9876 5432 1098 7654 3210 9876 5432 1098 7654 3210
- *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
- *  1                                             000
- *  ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
- *  |                                             |\|
- *  |                               Byte Enable --+ |
- *  |                             Transfer Length --+
- *  +-- IO space, not cached
- *
- *   Byte      Transfer
- *   Enable    Length    Transfer  Byte    Address
- *   adr<6:5>  adr<4:3>  Length    Enable  Adder
- *   ---------------------------------------------
- *      00        00      Byte      1110   0x000
- *      01        00      Byte      1101   0x020
- *      10        00      Byte      1011   0x040
- *      11        00      Byte      0111   0x060
- *
- *      00        01      Word      1100   0x008
- *      01        01      Word      1001   0x028 <= Not supported in this code.
- *      10        01      Word      0011   0x048
- *
- *      00        10      Tribyte   1000   0x010
- *      01        10      Tribyte   0001   0x030
- *
- *      10        11      Longword  0000   0x058
- *
- *      Note that byte enables are asserted low.
- *
- */
-
-#define MCPCIA_MAX_HOSES 4
-
-#define MCPCIA_MID(m)           ((unsigned long)(m) << 33)
-
-/* Dodge has PCI0 and PCI1 at MID 4 and 5 respectively. 
-   Durango adds PCI2 and PCI3 at MID 6 and 7 respectively.  */
-#define MCPCIA_HOSE2MID(h)      ((h) + 4)
-
-#define MCPCIA_MEM_MASK 0x07ffffff /* SPARSE Mem region mask is 27 bits */
-
-/*
- * Memory spaces:
- */
-#define MCPCIA_SPARSE(m)        (IDENT_ADDR + 0xf000000000UL + MCPCIA_MID(m))
-#define MCPCIA_DENSE(m)         (IDENT_ADDR + 0xf100000000UL + MCPCIA_MID(m))
-#define MCPCIA_IO(m)            (IDENT_ADDR + 0xf180000000UL + MCPCIA_MID(m))
-#define MCPCIA_CONF(m)          (IDENT_ADDR + 0xf1c0000000UL + MCPCIA_MID(m))
-#define MCPCIA_CSR(m)           (IDENT_ADDR + 0xf1e0000000UL + MCPCIA_MID(m))
-#define MCPCIA_IO_IACK(m)       (IDENT_ADDR + 0xf1f0000000UL + MCPCIA_MID(m))
-#define MCPCIA_DENSE_IO(m)      (IDENT_ADDR + 0xe1fc000000UL + MCPCIA_MID(m))
-#define MCPCIA_DENSE_CONF(m)    (IDENT_ADDR + 0xe1fe000000UL + MCPCIA_MID(m))
-
-/*
- *  General Registers
- */
-#define MCPCIA_REV(m)           (MCPCIA_CSR(m) + 0x000)
-#define MCPCIA_WHOAMI(m)        (MCPCIA_CSR(m) + 0x040)
-#define MCPCIA_PCI_LAT(m)       (MCPCIA_CSR(m) + 0x080)
-#define MCPCIA_CAP_CTRL(m)      (MCPCIA_CSR(m) + 0x100)
-#define MCPCIA_HAE_MEM(m)       (MCPCIA_CSR(m) + 0x400)
-#define MCPCIA_HAE_IO(m)        (MCPCIA_CSR(m) + 0x440)
-#define _MCPCIA_IACK_SC(m)      (MCPCIA_CSR(m) + 0x480)
-#define MCPCIA_HAE_DENSE(m)     (MCPCIA_CSR(m) + 0x4C0)
-
-/*
- * Interrupt Control registers
- */
-#define MCPCIA_INT_CTL(m)       (MCPCIA_CSR(m) + 0x500)
-#define MCPCIA_INT_REQ(m)       (MCPCIA_CSR(m) + 0x540)
-#define MCPCIA_INT_TARG(m)      (MCPCIA_CSR(m) + 0x580)
-#define MCPCIA_INT_ADR(m)       (MCPCIA_CSR(m) + 0x5C0)
-#define MCPCIA_INT_ADR_EXT(m)   (MCPCIA_CSR(m) + 0x600)
-#define MCPCIA_INT_MASK0(m)     (MCPCIA_CSR(m) + 0x640)
-#define MCPCIA_INT_MASK1(m)     (MCPCIA_CSR(m) + 0x680)
-#define MCPCIA_INT_ACK0(m)      (MCPCIA_CSR(m) + 0x10003f00)
-#define MCPCIA_INT_ACK1(m)      (MCPCIA_CSR(m) + 0x10003f40)
-
-/*
- * Performance Monitor registers
- */
-#define MCPCIA_PERF_MON(m)      (MCPCIA_CSR(m) + 0x300)
-#define MCPCIA_PERF_CONT(m)     (MCPCIA_CSR(m) + 0x340)
-
-/*
- * Diagnostic Registers
- */
-#define MCPCIA_CAP_DIAG(m)      (MCPCIA_CSR(m) + 0x700)
-#define MCPCIA_TOP_OF_MEM(m)    (MCPCIA_CSR(m) + 0x7C0)
-
-/*
- * Error registers
- */
-#define MCPCIA_MC_ERR0(m)       (MCPCIA_CSR(m) + 0x800)
-#define MCPCIA_MC_ERR1(m)       (MCPCIA_CSR(m) + 0x840)
-#define MCPCIA_CAP_ERR(m)       (MCPCIA_CSR(m) + 0x880)
-#define MCPCIA_PCI_ERR1(m)      (MCPCIA_CSR(m) + 0x1040)
-#define MCPCIA_MDPA_STAT(m)     (MCPCIA_CSR(m) + 0x4000)
-#define MCPCIA_MDPA_SYN(m)      (MCPCIA_CSR(m) + 0x4040)
-#define MCPCIA_MDPA_DIAG(m)     (MCPCIA_CSR(m) + 0x4080)
-#define MCPCIA_MDPB_STAT(m)     (MCPCIA_CSR(m) + 0x8000)
-#define MCPCIA_MDPB_SYN(m)      (MCPCIA_CSR(m) + 0x8040)
-#define MCPCIA_MDPB_DIAG(m)     (MCPCIA_CSR(m) + 0x8080)
-
-/*
- * PCI Address Translation Registers.
- */
-#define MCPCIA_SG_TBIA(m)       (MCPCIA_CSR(m) + 0x1300)
-#define MCPCIA_HBASE(m)         (MCPCIA_CSR(m) + 0x1340)
-
-#define MCPCIA_W0_BASE(m)       (MCPCIA_CSR(m) + 0x1400)
-#define MCPCIA_W0_MASK(m)       (MCPCIA_CSR(m) + 0x1440)
-#define MCPCIA_T0_BASE(m)       (MCPCIA_CSR(m) + 0x1480)
-
-#define MCPCIA_W1_BASE(m)       (MCPCIA_CSR(m) + 0x1500)
-#define MCPCIA_W1_MASK(m)       (MCPCIA_CSR(m) + 0x1540)
-#define MCPCIA_T1_BASE(m)       (MCPCIA_CSR(m) + 0x1580)
-
-#define MCPCIA_W2_BASE(m)       (MCPCIA_CSR(m) + 0x1600)
-#define MCPCIA_W2_MASK(m)       (MCPCIA_CSR(m) + 0x1640)
-#define MCPCIA_T2_BASE(m)       (MCPCIA_CSR(m) + 0x1680)
-
-#define MCPCIA_W3_BASE(m)       (MCPCIA_CSR(m) + 0x1700)
-#define MCPCIA_W3_MASK(m)       (MCPCIA_CSR(m) + 0x1740)
-#define MCPCIA_T3_BASE(m)       (MCPCIA_CSR(m) + 0x1780)
-
-/* Hack!  Only words for bus 0.  */
-
-#ifndef MCPCIA_ONE_HAE_WINDOW
-#define MCPCIA_HAE_ADDRESS      MCPCIA_HAE_MEM(4)
-#endif
-#define MCPCIA_IACK_SC          _MCPCIA_IACK_SC(4)
-
-/* 
- * The canonical non-remaped I/O and MEM addresses have these values
- * subtracted out.  This is arranged so that folks manipulating ISA
- * devices can use their familiar numbers and have them map to bus 0.
- */
-
-#define MCPCIA_IO_BIAS          MCPCIA_IO(4)
-#define MCPCIA_MEM_BIAS         MCPCIA_DENSE(4)
-
-/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
-#define MCPCIA_DAC_OFFSET       (1UL << 40)
-
-/*
- * Data structure for handling MCPCIA machine checks:
- */
-struct el_MCPCIA_uncorrected_frame_mcheck {
-        struct el_common header;
-        struct el_common_EV5_uncorrectable_mcheck procdata;
-};
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * MCPCIA, the RAWHIDE family PCI/memory support chipset for the EV5 (21164)
- * and EV56 (21164a) processors, can use either a sparse address mapping
- * scheme, or the so-called byte-word PCI address space, to get at PCI memory
- * and I/O.
- *
- * Unfortunately, we can't use BWIO with EV5, so for now, we always use SPARSE.
- */
-
-/*
- * Memory functions.  64-bit and 32-bit accesses are done through
- * dense memory space, everything else through sparse space.
- *
- * For reading and writing 8 and 16 bit quantities we need to
- * go through one of the three sparse address mapping regions
- * and use the HAE_MEM CSR to provide some bits of the address.
- * The following few routines use only sparse address region 1
- * which gives 1Gbyte of accessible space which relates exactly
- * to the amount of PCI memory mapping *into* system address space.
- * See p 6-17 of the specification but it looks something like this:
- *
- * 21164 Address:
- *
- *          3         2         1
- * 9876543210987654321098765432109876543210
- * 1ZZZZ0.PCI.QW.Address............BBLL
- *
- * ZZ = SBZ
- * BB = Byte offset
- * LL = Transfer length
- *
- * PCI Address:
- *
- * 3         2         1
- * 10987654321098765432109876543210
- * HHH....PCI.QW.Address........ 00
- *
- * HHH = 31:29 HAE_MEM CSR
- *
- */
-
-#define vip     volatile int __force *
-#define vuip    volatile unsigned int __force *
-
-#ifdef MCPCIA_ONE_HAE_WINDOW
-#define MCPCIA_FROB_MMIO                                                \
-        if (__mcpcia_is_mmio(hose)) {                                   \
-                set_hae(hose & 0xffffffff);                             \
-                hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);       \
-        }
-#else
-#define MCPCIA_FROB_MMIO                                                \
-        if (__mcpcia_is_mmio(hose)) {                                   \
-                hose = hose - MCPCIA_DENSE(4) + MCPCIA_SPARSE(4);       \
-        }
-#endif
-
-extern inline int __mcpcia_is_mmio(unsigned long addr)
-{
-        return (addr & 0x80000000UL) == 0;
-}
-
-__EXTERN_INLINE unsigned int mcpcia_ioread8(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
-        unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
-        unsigned long result;
-
-        MCPCIA_FROB_MMIO;
-
-        result = *(vip) ((addr << 5) + hose + 0x00);
-        return __kernel_extbl(result, addr & 3);
-}
-
-__EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
-        unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
-        unsigned long w;
-
-        MCPCIA_FROB_MMIO;
-
-        w = __kernel_insbl(b, addr & 3);
-        *(vuip) ((addr << 5) + hose + 0x00) = w;
-}
-
-__EXTERN_INLINE unsigned int mcpcia_ioread16(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
-        unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
-        unsigned long result;
-
-        MCPCIA_FROB_MMIO;
-
-        result = *(vip) ((addr << 5) + hose + 0x08);
-        return __kernel_extwl(result, addr & 3);
-}
-
-__EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
-        unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
-        unsigned long w;
-
-        MCPCIA_FROB_MMIO;
-
-        w = __kernel_inswl(b, addr & 3);
-        *(vuip) ((addr << 5) + hose + 0x08) = w;
-}
-
-__EXTERN_INLINE unsigned int mcpcia_ioread32(void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr;
-
-        if (!__mcpcia_is_mmio(addr))
-                addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
-
-        return *(vuip)addr;
-}
-
-__EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr;
-
-        if (!__mcpcia_is_mmio(addr))
-                addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
-
-        *(vuip)addr = b;
-}
-
-
-__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + MCPCIA_IO_BIAS);
-}
-
-__EXTERN_INLINE void __iomem *mcpcia_ioremap(unsigned long addr,
-                                             unsigned long size)
-{
-        return (void __iomem *)(addr + MCPCIA_MEM_BIAS);
-}
-
-__EXTERN_INLINE int mcpcia_is_ioaddr(unsigned long addr)
-{
-        return addr >= MCPCIA_SPARSE(0);
-}
-
-__EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        return __mcpcia_is_mmio(addr);
-}
-
-#undef MCPCIA_FROB_MMIO
-
-#undef vip
-#undef vuip
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             mcpcia
-#define mcpcia_trivial_rw_bw    2
-#define mcpcia_trivial_rw_lq    1
-#define mcpcia_trivial_io_bw    0
-#define mcpcia_trivial_io_lq    0
-#define mcpcia_trivial_iounmap  1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_MCPCIA__H__ */
diff --git a/include/asm-alpha/core_polaris.h b/include/asm-alpha/core_polaris.h
deleted file mode 100644
index 2f966b64659d..000000000000
--- a/include/asm-alpha/core_polaris.h
+++ /dev/null
@@ -1,110 +0,0 @@
-#ifndef __ALPHA_POLARIS__H__
-#define __ALPHA_POLARIS__H__
-
-#include <linux/types.h>
-#include <asm/compiler.h>
-
-/*
- * POLARIS is the internal name for a core logic chipset which provides
- * memory controller and PCI access for the 21164PC chip based systems.
- *
- * This file is based on:
- *
- * Polaris System Controller
- * Device Functional Specification
- * 22-Jan-98
- * Rev. 4.2
- *
- */
-
-/* Polaris memory regions */
-#define POLARIS_SPARSE_MEM_BASE         (IDENT_ADDR + 0xf800000000UL)
-#define POLARIS_DENSE_MEM_BASE          (IDENT_ADDR + 0xf900000000UL)
-#define POLARIS_SPARSE_IO_BASE          (IDENT_ADDR + 0xf980000000UL)
-#define POLARIS_SPARSE_CONFIG_BASE      (IDENT_ADDR + 0xf9c0000000UL)
-#define POLARIS_IACK_BASE               (IDENT_ADDR + 0xf9f8000000UL)
-#define POLARIS_DENSE_IO_BASE           (IDENT_ADDR + 0xf9fc000000UL)
-#define POLARIS_DENSE_CONFIG_BASE       (IDENT_ADDR + 0xf9fe000000UL)
-
-#define POLARIS_IACK_SC                 POLARIS_IACK_BASE
-
-/* The Polaris command/status registers live in PCI Config space for
- * bus 0/device 0.  As such, they may be bytes, words, or doublewords.
- */
-#define POLARIS_W_VENID         (POLARIS_DENSE_CONFIG_BASE)
-#define POLARIS_W_DEVID         (POLARIS_DENSE_CONFIG_BASE+2)
-#define POLARIS_W_CMD           (POLARIS_DENSE_CONFIG_BASE+4)
-#define POLARIS_W_STATUS        (POLARIS_DENSE_CONFIG_BASE+6)
-
-/*
- * Data structure for handling POLARIS machine checks:
- */
-struct el_POLARIS_sysdata_mcheck {
-    u_long      psc_status;
-    u_long      psc_pcictl0;
-    u_long      psc_pcictl1;
-    u_long      psc_pcictl2;
-};
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * POLARIS, the PCI/memory support chipset for the PCA56 (21164PC)
- * processors, can use either a sparse address  mapping scheme, or the 
- * so-called byte-word PCI address space, to get at PCI memory and I/O.
- *
- * However, we will support only the BWX form.
- */
-
-/*
- * Memory functions.  Polaris allows all accesses (byte/word
- * as well as long/quad) to be done through dense space.
- *
- * We will only support DENSE access via BWX insns.
- */
-
-__EXTERN_INLINE void __iomem *polaris_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + POLARIS_DENSE_IO_BASE);
-}
-
-__EXTERN_INLINE void __iomem *polaris_ioremap(unsigned long addr,
-                                              unsigned long size)
-{
-        return (void __iomem *)(addr + POLARIS_DENSE_MEM_BASE);
-}
-
-__EXTERN_INLINE int polaris_is_ioaddr(unsigned long addr)
-{
-        return addr >= POLARIS_SPARSE_MEM_BASE;
-}
-
-__EXTERN_INLINE int polaris_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr < POLARIS_SPARSE_IO_BASE;
-}
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             polaris
-#define polaris_trivial_rw_bw   1
-#define polaris_trivial_rw_lq   1
-#define polaris_trivial_io_bw   1
-#define polaris_trivial_io_lq   1
-#define polaris_trivial_iounmap 1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_POLARIS__H__ */
diff --git a/include/asm-alpha/core_t2.h b/include/asm-alpha/core_t2.h
deleted file mode 100644
index 46bfff58f670..000000000000
--- a/include/asm-alpha/core_t2.h
+++ /dev/null
@@ -1,633 +0,0 @@
-#ifndef __ALPHA_T2__H__
-#define __ALPHA_T2__H__
-
-#include <linux/types.h>
-#include <linux/spinlock.h>
-#include <asm/compiler.h>
-#include <asm/system.h>
-
-/*
- * T2 is the internal name for the core logic chipset which provides
- * memory controller and PCI access for the SABLE-based systems.
- *
- * This file is based on:
- *
- * SABLE I/O Specification
- * Revision/Update Information: 1.3
- *
- * jestabro@amt.tay1.dec.com Initial Version.
- *
- */
-
-#define T2_MEM_R1_MASK 0x07ffffff  /* Mem sparse region 1 mask is 26 bits */
-
-/* GAMMA-SABLE is a SABLE with EV5-based CPUs */
-/* All LYNX machines, EV4 or EV5, use the GAMMA bias also */
-#define _GAMMA_BIAS             0x8000000000UL
-
-#if defined(CONFIG_ALPHA_GENERIC)
-#define GAMMA_BIAS              alpha_mv.sys.t2.gamma_bias
-#elif defined(CONFIG_ALPHA_GAMMA)
-#define GAMMA_BIAS              _GAMMA_BIAS
-#else
-#define GAMMA_BIAS              0
-#endif
-
-/*
- * Memory spaces:
- */
-#define T2_CONF                 (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL)
-#define T2_IO                   (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL)
-#define T2_SPARSE_MEM           (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL)
-#define T2_DENSE_MEM            (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL)
-
-#define T2_IOCSR                (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL)
-#define T2_CERR1                (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL)
-#define T2_CERR2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL)
-#define T2_CERR3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL)
-#define T2_PERR1                (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL)
-#define T2_PERR2                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL)
-#define T2_PSCR                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL)
-#define T2_HAE_1                (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL)
-#define T2_HAE_2                (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL)
-#define T2_HBASE                (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL)
-#define T2_WBASE1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL)
-#define T2_WMASK1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL)
-#define T2_TBASE1               (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL)
-#define T2_WBASE2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL)
-#define T2_WMASK2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL)
-#define T2_TBASE2               (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL)
-#define T2_TLBBR                (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL)
-#define T2_IVR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL)
-#define T2_HAE_3                (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL)
-#define T2_HAE_4                (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL)
-
-/* The CSRs below are T3/T4 only */
-#define T2_WBASE3               (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL)
-#define T2_WMASK3               (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL)
-#define T2_TBASE3               (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL)
-
-#define T2_TDR0                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL)
-#define T2_TDR1                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL)
-#define T2_TDR2                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL)
-#define T2_TDR3                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL)
-#define T2_TDR4                 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL)
-#define T2_TDR5                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL)
-#define T2_TDR6                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL)
-#define T2_TDR7                 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL)
-
-#define T2_WBASE4               (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL)
-#define T2_WMASK4               (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL)
-#define T2_TBASE4               (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL)
-
-#define T2_AIR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL)
-#define T2_VAR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL)
-#define T2_DIR                  (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL)
-#define T2_ICE                  (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL)
-
-#define T2_HAE_ADDRESS          T2_HAE_1
-
-/*  T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to
- 3.8fff.ffff
- *
- *  +--------------+ 3 8000 0000
- *  | CPU 0 CSRs   |
- *  +--------------+ 3 8100 0000
- *  | CPU 1 CSRs   |
- *  +--------------+ 3 8200 0000
- *  | CPU 2 CSRs   |
- *  +--------------+ 3 8300 0000
- *  | CPU 3 CSRs   |
- *  +--------------+ 3 8400 0000
- *  | CPU Reserved |
- *  +--------------+ 3 8700 0000
- *  | Mem Reserved |
- *  +--------------+ 3 8800 0000
- *  | Mem 0 CSRs   |
- *  +--------------+ 3 8900 0000
- *  | Mem 1 CSRs   |
- *  +--------------+ 3 8a00 0000
- *  | Mem 2 CSRs   |
- *  +--------------+ 3 8b00 0000
- *  | Mem 3 CSRs   |
- *  +--------------+ 3 8c00 0000
- *  | Mem Reserved |
- *  +--------------+ 3 8e00 0000
- *  | PCI Bridge   |
- *  +--------------+ 3 8f00 0000
- *  | Expansion IO |
- *  +--------------+ 3 9000 0000
- *
- *
- */
-#define T2_CPU0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x380000000L)
-#define T2_CPU1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x381000000L)
-#define T2_CPU2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x382000000L)
-#define T2_CPU3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x383000000L)
-
-#define T2_CPUn_BASE(n)         (T2_CPU0_BASE + (((n)&3) * 0x001000000L))
-
-#define T2_MEM0_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x388000000L)
-#define T2_MEM1_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x389000000L)
-#define T2_MEM2_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L)
-#define T2_MEM3_BASE            (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L)
-
-
-/*
- * Sable CPU Module CSRS
- *
- * These are CSRs for hardware other than the CPU chip on the CPU module.
- * The CPU module has Backup Cache control logic, Cbus control logic, and
- * interrupt control logic on it.  There is a duplicate tag store to speed
- * up maintaining cache coherency.
- */
-
-struct sable_cpu_csr {
-  unsigned long bcc;     long fill_00[3]; /* Backup Cache Control */
-  unsigned long bcce;    long fill_01[3]; /* Backup Cache Correctable Error */
-  unsigned long bccea;   long fill_02[3]; /* B-Cache Corr Err Address Latch */
-  unsigned long bcue;    long fill_03[3]; /* B-Cache Uncorrectable Error */
-  unsigned long bcuea;   long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */
-  unsigned long dter;    long fill_05[3]; /* Duplicate Tag Error */
-  unsigned long cbctl;   long fill_06[3]; /* CBus Control */
-  unsigned long cbe;     long fill_07[3]; /* CBus Error */
-  unsigned long cbeal;   long fill_08[3]; /* CBus Error Addr Latch low */
-  unsigned long cbeah;   long fill_09[3]; /* CBus Error Addr Latch high */
-  unsigned long pmbx;    long fill_10[3]; /* Processor Mailbox */
-  unsigned long ipir;    long fill_11[3]; /* Inter-Processor Int Request */
-  unsigned long sic;     long fill_12[3]; /* System Interrupt Clear */
-  unsigned long adlk;    long fill_13[3]; /* Address Lock (LDxL/STxC) */
-  unsigned long madrl;   long fill_14[3]; /* CBus Miss Address */
-  unsigned long rev;     long fill_15[3]; /* CMIC Revision */
-};
-
-/*
- * Data structure for handling T2 machine checks:
- */
-struct el_t2_frame_header {
-        unsigned int    elcf_fid;       /* Frame ID (from above) */
-        unsigned int    elcf_size;      /* Size of frame in bytes */
-};
-
-struct el_t2_procdata_mcheck {
-        unsigned long   elfmc_paltemp[32];      /* PAL TEMP REGS. */
-        /* EV4-specific fields */
-        unsigned long   elfmc_exc_addr; /* Addr of excepting insn. */
-        unsigned long   elfmc_exc_sum;  /* Summary of arith traps. */
-        unsigned long   elfmc_exc_mask; /* Exception mask (from exc_sum). */
-        unsigned long   elfmc_iccsr;    /* IBox hardware enables. */
-        unsigned long   elfmc_pal_base; /* Base address for PALcode. */
-        unsigned long   elfmc_hier;     /* Hardware Interrupt Enable. */
-        unsigned long   elfmc_hirr;     /* Hardware Interrupt Request. */
-        unsigned long   elfmc_mm_csr;   /* D-stream fault info. */
-        unsigned long   elfmc_dc_stat;  /* D-cache status (ECC/Parity Err). */
-        unsigned long   elfmc_dc_addr;  /* EV3 Phys Addr for ECC/DPERR. */
-        unsigned long   elfmc_abox_ctl; /* ABox Control Register. */
-        unsigned long   elfmc_biu_stat; /* BIU Status. */
-        unsigned long   elfmc_biu_addr; /* BUI Address. */
-        unsigned long   elfmc_biu_ctl;  /* BIU Control. */
-        unsigned long   elfmc_fill_syndrome; /* For correcting ECC errors. */
-        unsigned long   elfmc_fill_addr;/* Cache block which was being read. */
-        unsigned long   elfmc_va;       /* Effective VA of fault or miss. */
-        unsigned long   elfmc_bc_tag;   /* Backup Cache Tag Probe Results. */
-};
-
-/*
- * Sable processor specific Machine Check Data segment.
- */
-
-struct el_t2_logout_header {
-        unsigned int    elfl_size;      /* size in bytes of logout area. */
-        unsigned int    elfl_sbz1:31;   /* Should be zero. */
-        unsigned int    elfl_retry:1;   /* Retry flag. */
-        unsigned int    elfl_procoffset; /* Processor-specific offset. */
-        unsigned int    elfl_sysoffset;  /* Offset of system-specific. */
-        unsigned int    elfl_error_type;        /* PAL error type code. */
-        unsigned int    elfl_frame_rev;         /* PAL Frame revision. */
-};
-struct el_t2_sysdata_mcheck {
-        unsigned long    elcmc_bcc;           /* CSR 0 */
-        unsigned long    elcmc_bcce;          /* CSR 1 */
-        unsigned long    elcmc_bccea;      /* CSR 2 */
-        unsigned long    elcmc_bcue;          /* CSR 3 */
-        unsigned long    elcmc_bcuea;      /* CSR 4 */
-        unsigned long    elcmc_dter;          /* CSR 5 */
-        unsigned long    elcmc_cbctl;      /* CSR 6 */
-        unsigned long    elcmc_cbe;           /* CSR 7 */
-        unsigned long    elcmc_cbeal;      /* CSR 8 */
-        unsigned long    elcmc_cbeah;      /* CSR 9 */
-        unsigned long    elcmc_pmbx;          /* CSR 10 */
-        unsigned long    elcmc_ipir;          /* CSR 11 */
-        unsigned long    elcmc_sic;           /* CSR 12 */
-        unsigned long    elcmc_adlk;          /* CSR 13 */
-        unsigned long    elcmc_madrl;      /* CSR 14 */
-        unsigned long    elcmc_crrev4;     /* CSR 15 */
-};
-
-/*
- * Sable memory error frame - sable pfms section 3.42
- */
-struct el_t2_data_memory {
-        struct  el_t2_frame_header elcm_hdr;    /* ID$MEM-FERR = 0x08 */
-        unsigned int  elcm_module;      /* Module id. */
-        unsigned int  elcm_res04;       /* Reserved. */
-        unsigned long elcm_merr;        /* CSR0: Error Reg 1. */
-        unsigned long elcm_mcmd1;       /* CSR1: Command Trap 1. */
-        unsigned long elcm_mcmd2;       /* CSR2: Command Trap 2. */
-        unsigned long elcm_mconf;       /* CSR3: Configuration. */
-        unsigned long elcm_medc1;       /* CSR4: EDC Status 1. */
-        unsigned long elcm_medc2;       /* CSR5: EDC Status 2. */
-        unsigned long elcm_medcc;       /* CSR6: EDC Control. */
-        unsigned long elcm_msctl;       /* CSR7: Stream Buffer Control. */
-        unsigned long elcm_mref;        /* CSR8: Refresh Control. */
-        unsigned long elcm_filter;      /* CSR9: CRD Filter Control. */
-};
-
-
-/*
- * Sable other CPU error frame - sable pfms section 3.43
- */
-struct el_t2_data_other_cpu {
-        short         elco_cpuid;       /* CPU ID */
-        short         elco_res02[3];
-        unsigned long elco_bcc; /* CSR 0 */
-        unsigned long elco_bcce;        /* CSR 1 */
-        unsigned long elco_bccea;       /* CSR 2 */
-        unsigned long elco_bcue;        /* CSR 3 */
-        unsigned long elco_bcuea;       /* CSR 4 */
-        unsigned long elco_dter;        /* CSR 5 */
-        unsigned long elco_cbctl;       /* CSR 6 */
-        unsigned long elco_cbe; /* CSR 7 */
-        unsigned long elco_cbeal;       /* CSR 8 */
-        unsigned long elco_cbeah;       /* CSR 9 */
-        unsigned long elco_pmbx;        /* CSR 10 */
-        unsigned long elco_ipir;        /* CSR 11 */
-        unsigned long elco_sic; /* CSR 12 */
-        unsigned long elco_adlk;        /* CSR 13 */
-        unsigned long elco_madrl;       /* CSR 14 */
-        unsigned long elco_crrev4;      /* CSR 15 */
-};
-
-/*
- * Sable other CPU error frame - sable pfms section 3.44
- */
-struct el_t2_data_t2{
-        struct el_t2_frame_header elct_hdr;     /* ID$T2-FRAME */
-        unsigned long elct_iocsr;       /* IO Control and Status Register */
-        unsigned long elct_cerr1;       /* Cbus Error Register 1 */
-        unsigned long elct_cerr2;       /* Cbus Error Register 2 */
-        unsigned long elct_cerr3;       /* Cbus Error Register 3 */
-        unsigned long elct_perr1;       /* PCI Error Register 1 */
-        unsigned long elct_perr2;       /* PCI Error Register 2 */
-        unsigned long elct_hae0_1;      /* High Address Extension Register 1 */
-        unsigned long elct_hae0_2;      /* High Address Extension Register 2 */
-        unsigned long elct_hbase;       /* High Base Register */
-        unsigned long elct_wbase1;      /* Window Base Register 1 */
-        unsigned long elct_wmask1;      /* Window Mask Register 1 */
-        unsigned long elct_tbase1;      /* Translated Base Register 1 */
-        unsigned long elct_wbase2;      /* Window Base Register 2 */
-        unsigned long elct_wmask2;      /* Window Mask Register 2 */
-        unsigned long elct_tbase2;      /* Translated Base Register 2 */
-        unsigned long elct_tdr0;        /* TLB Data Register 0 */
-        unsigned long elct_tdr1;        /* TLB Data Register 1 */
-        unsigned long elct_tdr2;        /* TLB Data Register 2 */
-        unsigned long elct_tdr3;        /* TLB Data Register 3 */
-        unsigned long elct_tdr4;        /* TLB Data Register 4 */
-        unsigned long elct_tdr5;        /* TLB Data Register 5 */
-        unsigned long elct_tdr6;        /* TLB Data Register 6 */
-        unsigned long elct_tdr7;        /* TLB Data Register 7 */
-};
-
-/*
- * Sable error log data structure - sable pfms section 3.40
- */
-struct el_t2_data_corrected {
-        unsigned long elcpb_biu_stat;
-        unsigned long elcpb_biu_addr;
-        unsigned long elcpb_biu_ctl;
-        unsigned long elcpb_fill_syndrome;
-        unsigned long elcpb_fill_addr;
-        unsigned long elcpb_bc_tag;
-};
-
-/*
- * Sable error log data structure
- * Note there are 4 memory slots on sable (see t2.h)
- */
-struct el_t2_frame_mcheck {
-        struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */
-        struct el_t2_logout_header elfmc_hdr;
-        struct el_t2_procdata_mcheck elfmc_procdata;
-        struct el_t2_sysdata_mcheck elfmc_sysdata;
-        struct el_t2_data_t2 elfmc_t2data;
-        struct el_t2_data_memory elfmc_memdata[4];
-        struct el_t2_frame_header elfmc_footer; /* empty */
-};
-
-
-/*
- * Sable error log data structures on memory errors
- */
-struct el_t2_frame_corrected {
-        struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */
-        struct el_t2_logout_header elfcc_hdr;
-        struct el_t2_data_corrected elfcc_procdata;
-/*      struct el_t2_data_t2 elfcc_t2data;              */
-/*      struct el_t2_data_memory elfcc_memdata[4];      */
-        struct el_t2_frame_header elfcc_footer; /* empty */
-};
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * T2 (the core logic PCI/memory support chipset for the SABLE
- * series of processors uses a sparse address mapping scheme to
- * get at PCI memory and I/O.
- */
-
-#define vip     volatile int *
-#define vuip    volatile unsigned int *
-
-extern inline u8 t2_inb(unsigned long addr)
-{
-        long result = *(vip) ((addr << 5) + T2_IO + 0x00);
-        return __kernel_extbl(result, addr & 3);
-}
-
-extern inline void t2_outb(u8 b, unsigned long addr)
-{
-        unsigned long w;
-
-        w = __kernel_insbl(b, addr & 3);
-        *(vuip) ((addr << 5) + T2_IO + 0x00) = w;
-        mb();
-}
-
-extern inline u16 t2_inw(unsigned long addr)
-{
-        long result = *(vip) ((addr << 5) + T2_IO + 0x08);
-        return __kernel_extwl(result, addr & 3);
-}
-
-extern inline void t2_outw(u16 b, unsigned long addr)
-{
-        unsigned long w;
-
-        w = __kernel_inswl(b, addr & 3);
-        *(vuip) ((addr << 5) + T2_IO + 0x08) = w;
-        mb();
-}
-
-extern inline u32 t2_inl(unsigned long addr)
-{
-        return *(vuip) ((addr << 5) + T2_IO + 0x18);
-}
-
-extern inline void t2_outl(u32 b, unsigned long addr)
-{
-        *(vuip) ((addr << 5) + T2_IO + 0x18) = b;
-        mb();
-}
-
-
-/*
- * Memory functions.
- *
- * For reading and writing 8 and 16 bit quantities we need to
- * go through one of the three sparse address mapping regions
- * and use the HAE_MEM CSR to provide some bits of the address.
- * The following few routines use only sparse address region 1
- * which gives 1Gbyte of accessible space which relates exactly
- * to the amount of PCI memory mapping *into* system address space.
- * See p 6-17 of the specification but it looks something like this:
- *
- * 21164 Address:
- *
- *          3         2         1
- * 9876543210987654321098765432109876543210
- * 1ZZZZ0.PCI.QW.Address............BBLL
- *
- * ZZ = SBZ
- * BB = Byte offset
- * LL = Transfer length
- *
- * PCI Address:
- *
- * 3         2         1
- * 10987654321098765432109876543210
- * HHH....PCI.QW.Address........ 00
- *
- * HHH = 31:29 HAE_MEM CSR
- *
- */
-
-#define t2_set_hae { \
-        msb = addr  >> 27; \
-        addr &= T2_MEM_R1_MASK; \
-        set_hae(msb); \
-}
-
-extern spinlock_t t2_hae_lock;
-
-/*
- * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since
- *       they may be called directly, rather than through the
- *       ioreadNN/iowriteNN routines.
- */
-
-__EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long result, msb;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00);
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-        return __kernel_extbl(result, addr & 3);
-}
-
-__EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long result, msb;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08);
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-        return __kernel_extwl(result, addr & 3);
-}
-
-/*
- * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
- * because we cannot access all of DENSE without changing its HAE.
- */
-__EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long result, msb;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18);
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-        return result & 0xffffffffUL;
-}
-
-__EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long r0, r1, work, msb;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        work = (addr << 5) + T2_SPARSE_MEM + 0x18;
-        r0 = *(vuip)(work);
-        r1 = *(vuip)(work + (4 << 5));
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-        return r1 << 32 | r0;
-}
-
-__EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long msb, w;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        w = __kernel_insbl(b, addr & 3);
-        *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-}
-
-__EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long msb, w;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        w = __kernel_inswl(b, addr & 3);
-        *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-}
-
-/*
- * On SABLE with T2, we must use SPARSE memory even for 32-bit access,
- * because we cannot access all of DENSE without changing its HAE.
- */
-__EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long msb;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-}
-
-__EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM;
-        unsigned long msb, work;
-        unsigned long flags;
-        spin_lock_irqsave(&t2_hae_lock, flags);
-
-        t2_set_hae;
-
-        work = (addr << 5) + T2_SPARSE_MEM + 0x18;
-        *(vuip)work = b;
-        *(vuip)(work + (4 << 5)) = b >> 32;
-        spin_unlock_irqrestore(&t2_hae_lock, flags);
-}
-
-__EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + T2_IO);
-}
-
-__EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr, 
-                                         unsigned long size)
-{
-        return (void __iomem *)(addr + T2_DENSE_MEM);
-}
-
-__EXTERN_INLINE int t2_is_ioaddr(unsigned long addr)
-{
-        return (long)addr >= 0;
-}
-
-__EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >= T2_DENSE_MEM;
-}
-
-/* New-style ioread interface.  The mmio routines are so ugly for T2 that
-   it doesn't make sense to merge the pio and mmio routines.  */
-
-#define IOPORT(OS, NS)                                                  \
-__EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr)         \
-{                                                                       \
-        if (t2_is_mmio(xaddr))                                          \
-                return t2_read##OS(xaddr);                              \
-        else                                                            \
-                return t2_in##OS((unsigned long)xaddr - T2_IO);         \
-}                                                                       \
-__EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr)       \
-{                                                                       \
-        if (t2_is_mmio(xaddr))                                          \
-                t2_write##OS(b, xaddr);                                 \
-        else                                                            \
-                t2_out##OS(b, (unsigned long)xaddr - T2_IO);            \
-}
-
-IOPORT(b, 8)
-IOPORT(w, 16)
-IOPORT(l, 32)
-
-#undef IOPORT
-
-#undef vip
-#undef vuip
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             t2
-#define t2_trivial_rw_bw        0
-#define t2_trivial_rw_lq        0
-#define t2_trivial_io_bw        0
-#define t2_trivial_io_lq        0
-#define t2_trivial_iounmap      1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_T2__H__ */
diff --git a/include/asm-alpha/core_titan.h b/include/asm-alpha/core_titan.h
deleted file mode 100644
index a17f6f33b68e..000000000000
--- a/include/asm-alpha/core_titan.h
+++ /dev/null
@@ -1,410 +0,0 @@
-#ifndef __ALPHA_TITAN__H__
-#define __ALPHA_TITAN__H__
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/compiler.h>
-
-/*
- * TITAN is the internal names for a core logic chipset which provides
- * memory controller and PCI/AGP access for 21264 based systems.
- *
- * This file is based on:
- *
- * Titan Chipset Engineering Specification
- * Revision 0.12
- * 13 July 1999
- *
- */
-
-/* XXX: Do we need to conditionalize on this?  */
-#ifdef USE_48_BIT_KSEG
-#define TI_BIAS 0x80000000000UL
-#else
-#define TI_BIAS 0x10000000000UL
-#endif
-
-/*
- * CChip, DChip, and PChip registers
- */
-
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(64)));
-} titan_64;
-
-typedef struct {
-        titan_64        csc;
-        titan_64        mtr;
-        titan_64        misc;
-        titan_64        mpd;
-        titan_64        aar0;
-        titan_64        aar1;
-        titan_64        aar2;
-        titan_64        aar3;
-        titan_64        dim0;
-        titan_64        dim1;
-        titan_64        dir0;
-        titan_64        dir1;
-        titan_64        drir;
-        titan_64        prben;
-        titan_64        iic0;
-        titan_64        iic1;
-        titan_64        mpr0;
-        titan_64        mpr1;
-        titan_64        mpr2;
-        titan_64        mpr3;
-        titan_64        rsvd[2];
-        titan_64        ttr;
-        titan_64        tdr;
-        titan_64        dim2;
-        titan_64        dim3;
-        titan_64        dir2;
-        titan_64        dir3;
-        titan_64        iic2;
-        titan_64        iic3;
-        titan_64        pwr;
-        titan_64        reserved[17];
-        titan_64        cmonctla;
-        titan_64        cmonctlb;
-        titan_64        cmoncnt01;
-        titan_64        cmoncnt23;
-        titan_64        cpen;
-} titan_cchip;
-
-typedef struct {
-        titan_64        dsc;
-        titan_64        str;
-        titan_64        drev;
-        titan_64        dsc2;
-} titan_dchip;
-
-typedef struct {
-        titan_64        wsba[4];
-        titan_64        wsm[4];
-        titan_64        tba[4];
-        titan_64        pctl;
-        titan_64        plat;
-        titan_64        reserved0[2];
-        union {
-                struct {
-                        titan_64        serror;
-                        titan_64        serren;
-                        titan_64        serrset;
-                        titan_64        reserved0;
-                        titan_64        gperror;
-                        titan_64        gperren;
-                        titan_64        gperrset;
-                        titan_64        reserved1;
-                        titan_64        gtlbiv;
-                        titan_64        gtlbia;
-                        titan_64        reserved2[2];
-                        titan_64        sctl;
-                        titan_64        reserved3[3];
-                } g;
-                struct {
-                        titan_64        agperror;
-                        titan_64        agperren;
-                        titan_64        agperrset;
-                        titan_64        agplastwr;
-                        titan_64        aperror;
-                        titan_64        aperren;
-                        titan_64        aperrset;
-                        titan_64        reserved0;
-                        titan_64        atlbiv;
-                        titan_64        atlbia;
-                        titan_64        reserved1[6];
-                } a;
-        } port_specific;
-        titan_64        sprst;
-        titan_64        reserved1[31];
-} titan_pachip_port;
-
-typedef struct {
-        titan_pachip_port       g_port;
-        titan_pachip_port       a_port;
-} titan_pachip;
-
-#define TITAN_cchip     ((titan_cchip  *)(IDENT_ADDR+TI_BIAS+0x1A0000000UL))
-#define TITAN_dchip     ((titan_dchip  *)(IDENT_ADDR+TI_BIAS+0x1B0000800UL))
-#define TITAN_pachip0   ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x180000000UL))
-#define TITAN_pachip1   ((titan_pachip *)(IDENT_ADDR+TI_BIAS+0x380000000UL))
-extern unsigned TITAN_agp;
-extern int TITAN_bootcpu;
-
-/*
- * TITAN PA-chip Window Space Base Address register.
- * (WSBA[0-2])
- */
-#define wsba_m_ena 0x1                
-#define wsba_m_sg 0x2
-#define wsba_m_addr 0xFFF00000  
-#define wmask_k_sz1gb 0x3FF00000                   
-union TPAchipWSBA {
-        struct  {
-                unsigned wsba_v_ena : 1;
-                unsigned wsba_v_sg : 1;
-                unsigned wsba_v_rsvd1 : 18;
-                unsigned wsba_v_addr : 12;
-                unsigned wsba_v_rsvd2 : 32;
-        } wsba_r_bits;
-        int wsba_q_whole [2];
-};
-
-/*
- * TITAN PA-chip Control Register
- * This definition covers both the G-Port GPCTL and the A-PORT APCTL.
- * Bits <51:0> are the same in both cases. APCTL<63:52> are only 
- * applicable to AGP.
- */
-#define pctl_m_fbtb                     0x00000001
-#define pctl_m_thdis                    0x00000002
-#define pctl_m_chaindis                 0x00000004
-#define pctl_m_tgtlat                   0x00000018
-#define pctl_m_hole                     0x00000020
-#define pctl_m_mwin                     0x00000040
-#define pctl_m_arbena                   0x00000080
-#define pctl_m_prigrp                   0x0000FF00
-#define pctl_m_ppri                     0x00010000
-#define pctl_m_pcispd66                 0x00020000
-#define pctl_m_cngstlt                  0x003C0000
-#define pctl_m_ptpdesten                0x3FC00000
-#define pctl_m_dpcen                    0x40000000
-#define pctl_m_apcen            0x0000000080000000UL
-#define pctl_m_dcrtv            0x0000000300000000UL
-#define pctl_m_en_stepping      0x0000000400000000UL
-#define apctl_m_rsvd1           0x000FFFF800000000UL
-#define apctl_m_agp_rate        0x0030000000000000UL
-#define apctl_m_agp_sba_en      0x0040000000000000UL
-#define apctl_m_agp_en          0x0080000000000000UL
-#define apctl_m_rsvd2           0x0100000000000000UL
-#define apctl_m_agp_present     0x0200000000000000UL
-#define apctl_agp_hp_rd         0x1C00000000000000UL
-#define apctl_agp_lp_rd         0xE000000000000000UL
-#define gpctl_m_rsvd            0xFFFFFFF800000000UL
-union TPAchipPCTL {
-        struct {
-                unsigned pctl_v_fbtb : 1;               /* A/G [0]     */
-                unsigned pctl_v_thdis : 1;              /* A/G [1]     */
-                unsigned pctl_v_chaindis : 1;           /* A/G [2]     */
-                unsigned pctl_v_tgtlat : 2;             /* A/G [4:3]   */
-                unsigned pctl_v_hole : 1;               /* A/G [5]     */
-                unsigned pctl_v_mwin : 1;               /* A/G [6]     */
-                unsigned pctl_v_arbena : 1;             /* A/G [7]     */
-                unsigned pctl_v_prigrp : 8;             /* A/G [15:8]  */
-                unsigned pctl_v_ppri : 1;               /* A/G [16]    */
-                unsigned pctl_v_pcispd66 : 1;           /* A/G [17]    */
-                unsigned pctl_v_cngstlt : 4;            /* A/G [21:18] */
-                unsigned pctl_v_ptpdesten : 8;          /* A/G [29:22] */
-                unsigned pctl_v_dpcen : 1;              /* A/G [30]    */
-                unsigned pctl_v_apcen : 1;              /* A/G [31]    */
-                unsigned pctl_v_dcrtv : 2;              /* A/G [33:32] */
-                unsigned pctl_v_en_stepping :1;         /* A/G [34]    */
-                unsigned apctl_v_rsvd1 : 17;            /* A   [51:35] */
-                unsigned apctl_v_agp_rate : 2;          /* A   [53:52] */
-                unsigned apctl_v_agp_sba_en : 1;        /* A   [54]    */
-                unsigned apctl_v_agp_en : 1;            /* A   [55]    */
-                unsigned apctl_v_rsvd2 : 1;             /* A   [56]    */
-                unsigned apctl_v_agp_present : 1;       /* A   [57]    */
-                unsigned apctl_v_agp_hp_rd : 3;         /* A   [60:58] */
-                unsigned apctl_v_agp_lp_rd : 3;         /* A   [63:61] */
-        } pctl_r_bits;
-        unsigned int pctl_l_whole [2];
-        unsigned long pctl_q_whole;
-};
-
-/*
- * SERROR / SERREN / SERRSET
- */
-union TPAchipSERR {
-        struct {
-                unsigned serr_v_lost_uecc : 1;          /* [0]          */
-                unsigned serr_v_uecc : 1;               /* [1]          */
-                unsigned serr_v_cre : 1;                /* [2]          */
-                unsigned serr_v_nxio : 1;               /* [3]          */
-                unsigned serr_v_lost_cre : 1;           /* [4]          */
-                unsigned serr_v_rsvd0 : 10;             /* [14:5]       */
-                unsigned serr_v_addr : 32;              /* [46:15]      */
-                unsigned serr_v_rsvd1 : 5;              /* [51:47]      */
-                unsigned serr_v_source : 2;             /* [53:52]      */
-                unsigned serr_v_cmd : 2;                /* [55:54]      */
-                unsigned serr_v_syn : 8;                /* [63:56]      */
-        } serr_r_bits;
-        unsigned int serr_l_whole[2];
-        unsigned long serr_q_whole;
-};
-
-/*
- * GPERROR / APERROR / GPERREN / APERREN / GPERRSET / APERRSET
- */
-union TPAchipPERR {
-        struct {
-                unsigned long perr_v_lost : 1;          /* [0]          */
-                unsigned long perr_v_serr : 1;          /* [1]          */
-                unsigned long perr_v_perr : 1;          /* [2]          */
-                unsigned long perr_v_dcrto : 1;         /* [3]          */
-                unsigned long perr_v_sge : 1;           /* [4]          */
-                unsigned long perr_v_ape : 1;           /* [5]          */
-                unsigned long perr_v_ta : 1;            /* [6]          */
-                unsigned long perr_v_dpe : 1;           /* [7]          */
-                unsigned long perr_v_nds : 1;           /* [8]          */
-                unsigned long perr_v_iptpr : 1;         /* [9]          */
-                unsigned long perr_v_iptpw : 1;         /* [10]         */
-                unsigned long perr_v_rsvd0 : 3;         /* [13:11]      */
-                unsigned long perr_v_addr : 33;         /* [46:14]      */
-                unsigned long perr_v_dac : 1;           /* [47]         */
-                unsigned long perr_v_mwin : 1;          /* [48]         */
-                unsigned long perr_v_rsvd1 : 3;         /* [51:49]      */
-                unsigned long perr_v_cmd : 4;           /* [55:52]      */
-                unsigned long perr_v_rsvd2 : 8;         /* [63:56]      */
-        } perr_r_bits;
-        unsigned int perr_l_whole[2];
-        unsigned long perr_q_whole;
-};
-
-/*
- * AGPERROR / AGPERREN / AGPERRSET
- */
-union TPAchipAGPERR {
-        struct {
-                unsigned agperr_v_lost : 1;             /* [0]          */
-                unsigned agperr_v_lpqfull : 1;          /* [1]          */
-                unsigned apgerr_v_hpqfull : 1;          /* [2]          */
-                unsigned agperr_v_rescmd : 1;           /* [3]          */
-                unsigned agperr_v_ipte : 1;             /* [4]          */
-                unsigned agperr_v_ptp : 1;              /* [5]          */
-                unsigned agperr_v_nowindow : 1;         /* [6]          */
-                unsigned agperr_v_rsvd0 : 8;            /* [14:7]       */
-                unsigned agperr_v_addr : 32;            /* [46:15]      */
-                unsigned agperr_v_rsvd1 : 1;            /* [47]         */
-                unsigned agperr_v_dac : 1;              /* [48]         */
-                unsigned agperr_v_mwin : 1;             /* [49]         */
-                unsigned agperr_v_cmd : 3;              /* [52:50]      */
-                unsigned agperr_v_length : 6;           /* [58:53]      */
-                unsigned agperr_v_fence : 1;            /* [59]         */
-                unsigned agperr_v_rsvd2 : 4;            /* [63:60]      */
-        } agperr_r_bits;
-        unsigned int agperr_l_whole[2];
-        unsigned long agperr_q_whole;
-};
-/*
- * Memory spaces:
- * Hose numbers are assigned as follows:
- *              0 - pachip 0 / G Port
- *              1 - pachip 1 / G Port
- *              2 - pachip 0 / A Port
- *              3 - pachip 1 / A Port
- */
-#define TITAN_HOSE_SHIFT       (33) 
-#define TITAN_HOSE(h)           (((unsigned long)(h)) << TITAN_HOSE_SHIFT)
-#define TITAN_BASE              (IDENT_ADDR + TI_BIAS)
-#define TITAN_MEM(h)            (TITAN_BASE+TITAN_HOSE(h)+0x000000000UL)
-#define _TITAN_IACK_SC(h)       (TITAN_BASE+TITAN_HOSE(h)+0x1F8000000UL)
-#define TITAN_IO(h)             (TITAN_BASE+TITAN_HOSE(h)+0x1FC000000UL)
-#define TITAN_CONF(h)           (TITAN_BASE+TITAN_HOSE(h)+0x1FE000000UL)
-
-#define TITAN_HOSE_MASK         TITAN_HOSE(3)
-#define TITAN_IACK_SC           _TITAN_IACK_SC(0) /* hack! */
-
-/* 
- * The canonical non-remaped I/O and MEM addresses have these values
- * subtracted out.  This is arranged so that folks manipulating ISA
- * devices can use their familiar numbers and have them map to bus 0.
- */
-
-#define TITAN_IO_BIAS           TITAN_IO(0)
-#define TITAN_MEM_BIAS          TITAN_MEM(0)
-
-/* The IO address space is larger than 0xffff */
-#define TITAN_IO_SPACE          (TITAN_CONF(0) - TITAN_IO(0))
-
-/* TIG Space */
-#define TITAN_TIG_SPACE         (TITAN_BASE + 0x100000000UL)
-
-/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
-/* ??? Just a guess.  Ought to confirm it hasn't been moved.  */
-#define TITAN_DAC_OFFSET        (1UL << 40)
-
-/*
- * Data structure for handling TITAN machine checks:
- */
-#define SCB_Q_SYSERR    0x620
-#define SCB_Q_PROCERR   0x630
-#define SCB_Q_SYSMCHK   0x660
-#define SCB_Q_PROCMCHK  0x670
-#define SCB_Q_SYSEVENT  0x680   /* environmental / system management */
-struct el_TITAN_sysdata_mcheck {
-        u64 summary;    /* 0x00 */
-        u64 c_dirx;     /* 0x08 */
-        u64 c_misc;     /* 0x10 */
-        u64 p0_serror;  /* 0x18 */
-        u64 p0_gperror; /* 0x20 */
-        u64 p0_aperror; /* 0x28 */
-        u64 p0_agperror;/* 0x30 */
-        u64 p1_serror;  /* 0x38 */
-        u64 p1_gperror; /* 0x40 */
-        u64 p1_aperror; /* 0x48 */
-        u64 p1_agperror;/* 0x50 */
-};
-
-/*
- * System area for a privateer 680 environmental/system management mcheck 
- */
-struct el_PRIVATEER_envdata_mcheck {
-        u64 summary;    /* 0x00 */
-        u64 c_dirx;     /* 0x08 */
-        u64 smir;       /* 0x10 */
-        u64 cpuir;      /* 0x18 */
-        u64 psir;       /* 0x20 */
-        u64 fault;      /* 0x28 */
-        u64 sys_doors;  /* 0x30 */
-        u64 temp_warn;  /* 0x38 */
-        u64 fan_ctrl;   /* 0x40 */
-        u64 code;       /* 0x48 */
-        u64 reserved;   /* 0x50 */
-};
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * TITAN, a 21??? PCI/memory support chipset for the EV6 (21264)
- * can only use linear accesses to get at PCI/AGP memory and I/O spaces.
- */
-
-/*
- * Memory functions.  all accesses are done through linear space.
- */
-extern void __iomem *titan_ioportmap(unsigned long addr);
-extern void __iomem *titan_ioremap(unsigned long addr, unsigned long size);
-extern void titan_iounmap(volatile void __iomem *addr);
-
-__EXTERN_INLINE int titan_is_ioaddr(unsigned long addr)
-{
-        return addr >= TITAN_BASE;
-}
-
-extern int titan_is_mmio(const volatile void __iomem *addr);
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             titan
-#define titan_trivial_rw_bw     1
-#define titan_trivial_rw_lq     1
-#define titan_trivial_io_bw     1
-#define titan_trivial_io_lq     1
-#define titan_trivial_iounmap   0
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_TITAN__H__ */
diff --git a/include/asm-alpha/core_tsunami.h b/include/asm-alpha/core_tsunami.h
deleted file mode 100644
index 58d4fe48742c..000000000000
--- a/include/asm-alpha/core_tsunami.h
+++ /dev/null
@@ -1,335 +0,0 @@
-#ifndef __ALPHA_TSUNAMI__H__
-#define __ALPHA_TSUNAMI__H__
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/compiler.h>
-
-/*
- * TSUNAMI/TYPHOON are the internal names for the core logic chipset which
- * provides memory controller and PCI access for the 21264 based systems.
- *
- * This file is based on:
- *
- * Tsunami System Programmers Manual
- * Preliminary, Chapters 2-5
- *
- */
-
-/* XXX: Do we need to conditionalize on this?  */
-#ifdef USE_48_BIT_KSEG
-#define TS_BIAS 0x80000000000UL
-#else
-#define TS_BIAS 0x10000000000UL
-#endif
-
-/*
- * CChip, DChip, and PChip registers
- */
-
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(64)));
-} tsunami_64;
-
-typedef struct {
-        tsunami_64      csc;
-        tsunami_64      mtr;
-        tsunami_64      misc;
-        tsunami_64      mpd;
-        tsunami_64      aar0;
-        tsunami_64      aar1;
-        tsunami_64      aar2;
-        tsunami_64      aar3;
-        tsunami_64      dim0;
-        tsunami_64      dim1;
-        tsunami_64      dir0;
-        tsunami_64      dir1;
-        tsunami_64      drir;
-        tsunami_64      prben;
-        tsunami_64      iic;    /* a.k.a. iic0 */
-        tsunami_64      wdr;    /* a.k.a. iic1 */
-        tsunami_64      mpr0;
-        tsunami_64      mpr1;
-        tsunami_64      mpr2;
-        tsunami_64      mpr3;
-        tsunami_64      mctl;
-        tsunami_64      __pad1;
-        tsunami_64      ttr;
-        tsunami_64      tdr;
-        tsunami_64      dim2;
-        tsunami_64      dim3;
-        tsunami_64      dir2;
-        tsunami_64      dir3;
-        tsunami_64      iic2;
-        tsunami_64      iic3;
-} tsunami_cchip;
-
-typedef struct {
-        tsunami_64      dsc;
-        tsunami_64      str;
-        tsunami_64      drev;
-} tsunami_dchip;
-
-typedef struct {
-        tsunami_64      wsba[4];
-        tsunami_64      wsm[4];
-        tsunami_64      tba[4];
-        tsunami_64      pctl;
-        tsunami_64      plat;
-        tsunami_64      reserved;
-        tsunami_64      perror;
-        tsunami_64      perrmask;
-        tsunami_64      perrset;
-        tsunami_64      tlbiv;
-        tsunami_64      tlbia;
-        tsunami_64      pmonctl;
-        tsunami_64      pmoncnt;
-} tsunami_pchip;
-
-#define TSUNAMI_cchip  ((tsunami_cchip *)(IDENT_ADDR+TS_BIAS+0x1A0000000UL))
-#define TSUNAMI_dchip  ((tsunami_dchip *)(IDENT_ADDR+TS_BIAS+0x1B0000800UL))
-#define TSUNAMI_pchip0 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x180000000UL))
-#define TSUNAMI_pchip1 ((tsunami_pchip *)(IDENT_ADDR+TS_BIAS+0x380000000UL))
-extern int TSUNAMI_bootcpu;
-
-/*
- * TSUNAMI Pchip Error register.
- */
-
-#define perror_m_lost 0x1
-#define perror_m_serr 0x2
-#define perror_m_perr 0x4
-#define perror_m_dcrto 0x8
-#define perror_m_sge 0x10
-#define perror_m_ape 0x20
-#define perror_m_ta 0x40
-#define perror_m_rdpe 0x80
-#define perror_m_nds 0x100
-#define perror_m_rto 0x200
-#define perror_m_uecc 0x400
-#define perror_m_cre 0x800
-#define perror_m_addrl 0xFFFFFFFF0000UL
-#define perror_m_addrh 0x7000000000000UL
-#define perror_m_cmd 0xF0000000000000UL
-#define perror_m_syn 0xFF00000000000000UL
-union TPchipPERROR {   
-        struct  {
-                unsigned int perror_v_lost : 1;
-                unsigned perror_v_serr : 1;
-                unsigned perror_v_perr : 1;
-                unsigned perror_v_dcrto : 1;
-                unsigned perror_v_sge : 1;
-                unsigned perror_v_ape : 1;
-                unsigned perror_v_ta : 1;
-                unsigned perror_v_rdpe : 1;
-                unsigned perror_v_nds : 1;
-                unsigned perror_v_rto : 1;
-                unsigned perror_v_uecc : 1;
-                unsigned perror_v_cre : 1;                 
-                unsigned perror_v_rsvd1 : 4;
-                unsigned perror_v_addrl : 32;
-                unsigned perror_v_addrh : 3;
-                unsigned perror_v_rsvd2 : 1;
-                unsigned perror_v_cmd : 4;
-                unsigned perror_v_syn : 8;
-        } perror_r_bits;
-        int perror_q_whole [2];
-};                       
-
-/*
- * TSUNAMI Pchip Window Space Base Address register.
- */
-#define wsba_m_ena 0x1                
-#define wsba_m_sg 0x2
-#define wsba_m_ptp 0x4
-#define wsba_m_addr 0xFFF00000  
-#define wmask_k_sz1gb 0x3FF00000                   
-union TPchipWSBA {
-        struct  {
-                unsigned wsba_v_ena : 1;
-                unsigned wsba_v_sg : 1;
-                unsigned wsba_v_ptp : 1;
-                unsigned wsba_v_rsvd1 : 17;
-                unsigned wsba_v_addr : 12;
-                unsigned wsba_v_rsvd2 : 32;
-        } wsba_r_bits;
-        int wsba_q_whole [2];
-};
-
-/*
- * TSUNAMI Pchip Control Register
- */
-#define pctl_m_fdsc 0x1
-#define pctl_m_fbtb 0x2
-#define pctl_m_thdis 0x4
-#define pctl_m_chaindis 0x8
-#define pctl_m_tgtlat 0x10
-#define pctl_m_hole 0x20
-#define pctl_m_mwin 0x40
-#define pctl_m_arbena 0x80
-#define pctl_m_prigrp 0x7F00
-#define pctl_m_ppri 0x8000
-#define pctl_m_rsvd1 0x30000
-#define pctl_m_eccen 0x40000
-#define pctl_m_padm 0x80000
-#define pctl_m_cdqmax 0xF00000
-#define pctl_m_rev 0xFF000000
-#define pctl_m_crqmax 0xF00000000UL
-#define pctl_m_ptpmax 0xF000000000UL
-#define pctl_m_pclkx 0x30000000000UL
-#define pctl_m_fdsdis 0x40000000000UL
-#define pctl_m_fdwdis 0x80000000000UL
-#define pctl_m_ptevrfy 0x100000000000UL
-#define pctl_m_rpp 0x200000000000UL
-#define pctl_m_pid 0xC00000000000UL
-#define pctl_m_rsvd2 0xFFFF000000000000UL
-
-union TPchipPCTL {
-        struct {
-                unsigned pctl_v_fdsc : 1;
-                unsigned pctl_v_fbtb : 1;
-                unsigned pctl_v_thdis : 1;
-                unsigned pctl_v_chaindis : 1;
-                unsigned pctl_v_tgtlat : 1;
-                unsigned pctl_v_hole : 1;
-                unsigned pctl_v_mwin : 1;
-                unsigned pctl_v_arbena : 1;
-                unsigned pctl_v_prigrp : 7;
-                unsigned pctl_v_ppri : 1;
-                unsigned pctl_v_rsvd1 : 2;
-                unsigned pctl_v_eccen : 1;
-                unsigned pctl_v_padm : 1;
-                unsigned pctl_v_cdqmax : 4;
-                unsigned pctl_v_rev : 8;
-                unsigned pctl_v_crqmax : 4;
-                unsigned pctl_v_ptpmax : 4;
-                unsigned pctl_v_pclkx : 2;
-                unsigned pctl_v_fdsdis : 1;
-                unsigned pctl_v_fdwdis : 1;
-                unsigned pctl_v_ptevrfy : 1;
-                unsigned pctl_v_rpp : 1;
-                unsigned pctl_v_pid : 2;
-                unsigned pctl_v_rsvd2 : 16;
-        } pctl_r_bits;
-        int pctl_q_whole [2];
-};
-
-/*
- * TSUNAMI Pchip Error Mask Register.
- */
-#define perrmask_m_lost 0x1
-#define perrmask_m_serr 0x2
-#define perrmask_m_perr 0x4
-#define perrmask_m_dcrto 0x8
-#define perrmask_m_sge 0x10
-#define perrmask_m_ape 0x20
-#define perrmask_m_ta 0x40
-#define perrmask_m_rdpe 0x80
-#define perrmask_m_nds 0x100
-#define perrmask_m_rto 0x200
-#define perrmask_m_uecc 0x400
-#define perrmask_m_cre 0x800
-#define perrmask_m_rsvd 0xFFFFFFFFFFFFF000UL
-union TPchipPERRMASK {   
-        struct  {
-                unsigned int perrmask_v_lost : 1;
-                unsigned perrmask_v_serr : 1;
-                unsigned perrmask_v_perr : 1;
-                unsigned perrmask_v_dcrto : 1;
-                unsigned perrmask_v_sge : 1;
-                unsigned perrmask_v_ape : 1;
-                unsigned perrmask_v_ta : 1;
-                unsigned perrmask_v_rdpe : 1;
-                unsigned perrmask_v_nds : 1;
-                unsigned perrmask_v_rto : 1;
-                unsigned perrmask_v_uecc : 1;
-                unsigned perrmask_v_cre : 1;                 
-                unsigned perrmask_v_rsvd1 : 20;
-                unsigned perrmask_v_rsvd2 : 32;
-        } perrmask_r_bits;
-        int perrmask_q_whole [2];
-};                       
-
-/*
- * Memory spaces:
- */
-#define TSUNAMI_HOSE(h)         (((unsigned long)(h)) << 33)
-#define TSUNAMI_BASE            (IDENT_ADDR + TS_BIAS)
-
-#define TSUNAMI_MEM(h)          (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x000000000UL)
-#define _TSUNAMI_IACK_SC(h)     (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1F8000000UL)
-#define TSUNAMI_IO(h)           (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FC000000UL)
-#define TSUNAMI_CONF(h)         (TSUNAMI_BASE+TSUNAMI_HOSE(h) + 0x1FE000000UL)
-
-#define TSUNAMI_IACK_SC         _TSUNAMI_IACK_SC(0) /* hack! */
-
-
-/* 
- * The canonical non-remaped I/O and MEM addresses have these values
- * subtracted out.  This is arranged so that folks manipulating ISA
- * devices can use their familiar numbers and have them map to bus 0.
- */
-
-#define TSUNAMI_IO_BIAS          TSUNAMI_IO(0)
-#define TSUNAMI_MEM_BIAS         TSUNAMI_MEM(0)
-
-/* The IO address space is larger than 0xffff */
-#define TSUNAMI_IO_SPACE        (TSUNAMI_CONF(0) - TSUNAMI_IO(0))
-
-/* Offset between ram physical addresses and pci64 DAC bus addresses.  */
-#define TSUNAMI_DAC_OFFSET      (1UL << 40)
-
-/*
- * Data structure for handling TSUNAMI machine checks:
- */
-struct el_TSUNAMI_sysdata_mcheck {
-};
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * I/O functions:
- *
- * TSUNAMI, the 21??? PCI/memory support chipset for the EV6 (21264)
- * can only use linear accesses to get at PCI memory and I/O spaces.
- */
-
-/*
- * Memory functions.  all accesses are done through linear space.
- */
-extern void __iomem *tsunami_ioportmap(unsigned long addr);
-extern void __iomem *tsunami_ioremap(unsigned long addr, unsigned long size);
-__EXTERN_INLINE int tsunami_is_ioaddr(unsigned long addr)
-{
-        return addr >= TSUNAMI_BASE;
-}
-
-__EXTERN_INLINE int tsunami_is_mmio(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        return (addr & 0x100000000UL) == 0;
-}
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             tsunami
-#define tsunami_trivial_rw_bw   1
-#define tsunami_trivial_rw_lq   1
-#define tsunami_trivial_io_bw   1
-#define tsunami_trivial_io_lq   1
-#define tsunami_trivial_iounmap 1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_TSUNAMI__H__ */
diff --git a/include/asm-alpha/core_wildfire.h b/include/asm-alpha/core_wildfire.h
deleted file mode 100644
index cd562f544ba2..000000000000
--- a/include/asm-alpha/core_wildfire.h
+++ /dev/null
@@ -1,318 +0,0 @@
-#ifndef __ALPHA_WILDFIRE__H__
-#define __ALPHA_WILDFIRE__H__
-
-#include <linux/types.h>
-#include <asm/compiler.h>
-
-#define WILDFIRE_MAX_QBB        8       /* more than 8 requires other mods */
-#define WILDFIRE_PCA_PER_QBB    4
-#define WILDFIRE_IRQ_PER_PCA    64
-
-#define WILDFIRE_NR_IRQS \
-  (WILDFIRE_MAX_QBB * WILDFIRE_PCA_PER_QBB * WILDFIRE_IRQ_PER_PCA)
-
-extern unsigned char wildfire_hard_qbb_map[WILDFIRE_MAX_QBB];
-extern unsigned char wildfire_soft_qbb_map[WILDFIRE_MAX_QBB];
-#define QBB_MAP_EMPTY   0xff
-
-extern unsigned long wildfire_hard_qbb_mask;
-extern unsigned long wildfire_soft_qbb_mask;
-extern unsigned long wildfire_gp_mask;
-extern unsigned long wildfire_hs_mask;
-extern unsigned long wildfire_iop_mask;
-extern unsigned long wildfire_ior_mask;
-extern unsigned long wildfire_pca_mask;
-extern unsigned long wildfire_cpu_mask;
-extern unsigned long wildfire_mem_mask;
-
-#define WILDFIRE_QBB_EXISTS(qbbno) (wildfire_soft_qbb_mask & (1 << (qbbno)))
-
-#define WILDFIRE_MEM_EXISTS(qbbno) (wildfire_mem_mask & (0xf << ((qbbno) << 2)))
-
-#define WILDFIRE_PCA_EXISTS(qbbno, pcano) \
-                (wildfire_pca_mask & (1 << (((qbbno) << 2) + (pcano))))
-
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(64)));
-} wildfire_64;
-
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(256)));
-} wildfire_256;
-
-typedef struct {
-        volatile unsigned long csr __attribute__((aligned(2048)));
-} wildfire_2k;
-
-typedef struct {
-        wildfire_64     qsd_whami;
-        wildfire_64     qsd_rev;
-        wildfire_64     qsd_port_present;
-        wildfire_64     qsd_port_active;
-        wildfire_64     qsd_fault_ena;
-        wildfire_64     qsd_cpu_int_ena;
-        wildfire_64     qsd_mem_config;
-        wildfire_64     qsd_err_sum;
-        wildfire_64     ce_sum[4];
-        wildfire_64     dev_init[4];
-        wildfire_64     it_int[4];
-        wildfire_64     ip_int[4];
-        wildfire_64     uce_sum[4];
-        wildfire_64     se_sum__non_dev_int[4];
-        wildfire_64     scratch[4];
-        wildfire_64     qsd_timer;
-        wildfire_64     qsd_diag;
-} wildfire_qsd;
-
-typedef struct {
-        wildfire_256    qsd_whami;
-        wildfire_256    __pad1;
-        wildfire_256    ce_sum;
-        wildfire_256    dev_init;
-        wildfire_256    it_int;
-        wildfire_256    ip_int;
-        wildfire_256    uce_sum;
-        wildfire_256    se_sum;
-} wildfire_fast_qsd;
-
-typedef struct {
-        wildfire_2k     qsa_qbb_id;
-        wildfire_2k     __pad1;
-        wildfire_2k     qsa_port_ena;
-        wildfire_2k     qsa_scratch;
-        wildfire_2k     qsa_config[5];
-        wildfire_2k     qsa_ref_int;
-        wildfire_2k     qsa_qbb_pop[2];
-        wildfire_2k     qsa_dtag_fc;
-        wildfire_2k     __pad2[3];
-        wildfire_2k     qsa_diag;
-        wildfire_2k     qsa_diag_lock[4];
-        wildfire_2k     __pad3[11];
-        wildfire_2k     qsa_cpu_err_sum;
-        wildfire_2k     qsa_misc_err_sum;
-        wildfire_2k     qsa_tmo_err_sum;
-        wildfire_2k     qsa_err_ena;
-        wildfire_2k     qsa_tmo_config;
-        wildfire_2k     qsa_ill_cmd_err_sum;
-        wildfire_2k     __pad4[26];
-        wildfire_2k     qsa_busy_mask;
-        wildfire_2k     qsa_arr_valid;
-        wildfire_2k     __pad5[2];
-        wildfire_2k     qsa_port_map[4];
-        wildfire_2k     qsa_arr_addr[8];
-        wildfire_2k     qsa_arr_mask[8];
-} wildfire_qsa;
-
-typedef struct {
-        wildfire_64     ioa_config;
-        wildfire_64     iod_config;
-        wildfire_64     iop_switch_credits;
-        wildfire_64     __pad1;
-        wildfire_64     iop_hose_credits;
-        wildfire_64     __pad2[11];
-        struct {
-                wildfire_64     __pad3;
-                wildfire_64     init;
-        } iop_hose[4];
-        wildfire_64     ioa_hose_0_ctrl;
-        wildfire_64     iod_hose_0_ctrl;
-        wildfire_64     ioa_hose_1_ctrl;
-        wildfire_64     iod_hose_1_ctrl;
-        wildfire_64     ioa_hose_2_ctrl;
-        wildfire_64     iod_hose_2_ctrl;
-        wildfire_64     ioa_hose_3_ctrl;
-        wildfire_64     iod_hose_3_ctrl;
-        struct {
-                wildfire_64     target;
-                wildfire_64     __pad4;
-        } iop_dev_int[4];
-
-        wildfire_64     iop_err_int_target;
-        wildfire_64     __pad5[7];
-        wildfire_64     iop_qbb_err_sum;
-        wildfire_64     __pad6;
-        wildfire_64     iop_qbb_se_sum;
-        wildfire_64     __pad7;
-        wildfire_64     ioa_err_sum;
-        wildfire_64     iod_err_sum;
-        wildfire_64     __pad8[4];
-        wildfire_64     ioa_diag_force_err;
-        wildfire_64     iod_diag_force_err;
-        wildfire_64     __pad9[4];
-        wildfire_64     iop_diag_send_err_int;
-        wildfire_64     __pad10[15];
-        wildfire_64     ioa_scratch;
-        wildfire_64     iod_scratch;
-} wildfire_iop;
-
-typedef struct {
-        wildfire_2k     gpa_qbb_map[4];
-        wildfire_2k     gpa_mem_pop_map;
-        wildfire_2k     gpa_scratch;
-        wildfire_2k     gpa_diag;
-        wildfire_2k     gpa_config_0;
-        wildfire_2k     __pad1;
-        wildfire_2k     gpa_init_id;
-        wildfire_2k     gpa_config_2;
-        /* not complete */
-} wildfire_gp;
-
-typedef struct {
-        wildfire_64     pca_what_am_i;
-        wildfire_64     pca_err_sum;
-        wildfire_64     pca_diag_force_err;
-        wildfire_64     pca_diag_send_err_int;
-        wildfire_64     pca_hose_credits;
-        wildfire_64     pca_scratch;
-        wildfire_64     pca_micro_addr;
-        wildfire_64     pca_micro_data;
-        wildfire_64     pca_pend_int;
-        wildfire_64     pca_sent_int;
-        wildfire_64     __pad1;
-        wildfire_64     pca_stdio_edge_level;
-        wildfire_64     __pad2[52];
-        struct {
-                wildfire_64     target;
-                wildfire_64     enable;
-        } pca_int[4];
-        wildfire_64     __pad3[56];
-        wildfire_64     pca_alt_sent_int[32];
-} wildfire_pca;
-
-typedef struct {
-        wildfire_64     ne_what_am_i;
-        /* not complete */
-} wildfire_ne;
-
-typedef struct {
-        wildfire_64     fe_what_am_i;
-        /* not complete */
-} wildfire_fe;
-
-typedef struct {
-        wildfire_64     pci_io_addr_ext;
-        wildfire_64     pci_ctrl;
-        wildfire_64     pci_err_sum;
-        wildfire_64     pci_err_addr;
-        wildfire_64     pci_stall_cnt;
-        wildfire_64     pci_iack_special;
-        wildfire_64     __pad1[2];
-        wildfire_64     pci_pend_int;
-        wildfire_64     pci_sent_int;
-        wildfire_64     __pad2[54];
-        struct {
-                wildfire_64     wbase;
-                wildfire_64     wmask;
-                wildfire_64     tbase;
-        } pci_window[4];
-        wildfire_64     pci_flush_tlb;
-        wildfire_64     pci_perf_mon;
-} wildfire_pci;
-
-#define WILDFIRE_ENTITY_SHIFT           18
-
-#define WILDFIRE_GP_ENTITY              (0x10UL << WILDFIRE_ENTITY_SHIFT)
-#define WILDFIRE_IOP_ENTITY             (0x08UL << WILDFIRE_ENTITY_SHIFT)
-#define WILDFIRE_QSA_ENTITY             (0x04UL << WILDFIRE_ENTITY_SHIFT)
-#define WILDFIRE_QSD_ENTITY_SLOW        (0x05UL << WILDFIRE_ENTITY_SHIFT)
-#define WILDFIRE_QSD_ENTITY_FAST        (0x01UL << WILDFIRE_ENTITY_SHIFT)
-
-#define WILDFIRE_PCA_ENTITY(pca)        ((0xc|(pca))<<WILDFIRE_ENTITY_SHIFT)
-
-#define WILDFIRE_BASE           (IDENT_ADDR | (1UL << 40))
-
-#define WILDFIRE_QBB_MASK       0x0fUL  /* for now, only 4 bits/16 QBBs */
-
-#define WILDFIRE_QBB(q)         ((~((long)(q)) & WILDFIRE_QBB_MASK) << 36)
-#define WILDFIRE_HOSE(h)        ((long)(h) << 33)
-
-#define WILDFIRE_QBB_IO(q)      (WILDFIRE_BASE | WILDFIRE_QBB(q))
-#define WILDFIRE_QBB_HOSE(q,h)  (WILDFIRE_QBB_IO(q) | WILDFIRE_HOSE(h))
-
-#define WILDFIRE_MEM(q,h)       (WILDFIRE_QBB_HOSE(q,h) | 0x000000000UL)
-#define WILDFIRE_CONF(q,h)      (WILDFIRE_QBB_HOSE(q,h) | 0x1FE000000UL)
-#define WILDFIRE_IO(q,h)        (WILDFIRE_QBB_HOSE(q,h) | 0x1FF000000UL)
-
-#define WILDFIRE_qsd(q) \
- ((wildfire_qsd *)(WILDFIRE_QBB_IO(q)|WILDFIRE_QSD_ENTITY_SLOW|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_fast_qsd() \
- ((wildfire_fast_qsd *)(WILDFIRE_QBB_IO(0)|WILDFIRE_QSD_ENTITY_FAST|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_qsa(q) \
- ((wildfire_qsa *)(WILDFIRE_QBB_IO(q)|WILDFIRE_QSA_ENTITY|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_iop(q) \
- ((wildfire_iop *)(WILDFIRE_QBB_IO(q)|WILDFIRE_IOP_ENTITY|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_gp(q) \
- ((wildfire_gp *)(WILDFIRE_QBB_IO(q)|WILDFIRE_GP_ENTITY|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_pca(q,pca) \
- ((wildfire_pca *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(pca)|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_ne(q,pca) \
- ((wildfire_ne *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(pca)|(((1UL<<13)-1)<<23)|(1UL<<16)))
-
-#define WILDFIRE_fe(q,pca) \
- ((wildfire_fe *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(pca)|(((1UL<<13)-1)<<23)|(3UL<<15)))
-
-#define WILDFIRE_pci(q,h) \
- ((wildfire_pci *)(WILDFIRE_QBB_IO(q)|WILDFIRE_PCA_ENTITY(((h)&6)>>1)|((((h)&1)|2)<<16)|(((1UL<<13)-1)<<23)))
-
-#define WILDFIRE_IO_BIAS        WILDFIRE_IO(0,0)
-#define WILDFIRE_MEM_BIAS       WILDFIRE_MEM(0,0) /* ??? */
-
-/* The IO address space is larger than 0xffff */
-#define WILDFIRE_IO_SPACE       (8UL*1024*1024)
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * Memory functions.  all accesses are done through linear space.
- */
-
-__EXTERN_INLINE void __iomem *wildfire_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)(addr + WILDFIRE_IO_BIAS);
-}
-
-__EXTERN_INLINE void __iomem *wildfire_ioremap(unsigned long addr, 
-                                               unsigned long size)
-{
-        return (void __iomem *)(addr + WILDFIRE_MEM_BIAS);
-}
-
-__EXTERN_INLINE int wildfire_is_ioaddr(unsigned long addr)
-{
-        return addr >= WILDFIRE_BASE;
-}
-
-__EXTERN_INLINE int wildfire_is_mmio(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long)xaddr;
-        return (addr & 0x100000000UL) == 0;
-}
-
-#undef __IO_PREFIX
-#define __IO_PREFIX                     wildfire
-#define wildfire_trivial_rw_bw          1
-#define wildfire_trivial_rw_lq          1
-#define wildfire_trivial_io_bw          1
-#define wildfire_trivial_io_lq          1
-#define wildfire_trivial_iounmap        1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_WILDFIRE__H__ */
diff --git a/include/asm-alpha/cputime.h b/include/asm-alpha/cputime.h
deleted file mode 100644
index 19577fd93230..000000000000
--- a/include/asm-alpha/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ALPHA_CPUTIME_H
-#define __ALPHA_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __ALPHA_CPUTIME_H */
diff --git a/include/asm-alpha/current.h b/include/asm-alpha/current.h
deleted file mode 100644
index 094d285a1b34..000000000000
--- a/include/asm-alpha/current.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _ALPHA_CURRENT_H
-#define _ALPHA_CURRENT_H
-
-#include <linux/thread_info.h>
-
-#define get_current()   (current_thread_info()->task)
-#define current         get_current()
-
-#endif /* _ALPHA_CURRENT_H */
diff --git a/include/asm-alpha/delay.h b/include/asm-alpha/delay.h
deleted file mode 100644
index 2aa3f410f7e6..000000000000
--- a/include/asm-alpha/delay.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __ALPHA_DELAY_H
-#define __ALPHA_DELAY_H
-
-extern void __delay(int loops);
-extern void udelay(unsigned long usecs);
-
-extern void ndelay(unsigned long nsecs);
-#define ndelay ndelay
-
-#endif /* defined(__ALPHA_DELAY_H) */
diff --git a/include/asm-alpha/device.h b/include/asm-alpha/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-alpha/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-alpha/div64.h b/include/asm-alpha/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-alpha/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-alpha/dma-mapping.h b/include/asm-alpha/dma-mapping.h
deleted file mode 100644
index a5801ae02e4b..000000000000
--- a/include/asm-alpha/dma-mapping.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _ALPHA_DMA_MAPPING_H
-#define _ALPHA_DMA_MAPPING_H
-
-
-#ifdef CONFIG_PCI
-
-#include <linux/pci.h>
-
-#define dma_map_single(dev, va, size, dir)              \
-                pci_map_single(alpha_gendev_to_pci(dev), va, size, dir)
-#define dma_unmap_single(dev, addr, size, dir)          \
-                pci_unmap_single(alpha_gendev_to_pci(dev), addr, size, dir)
-#define dma_alloc_coherent(dev, size, addr, gfp)        \
-              __pci_alloc_consistent(alpha_gendev_to_pci(dev), size, addr, gfp)
-#define dma_free_coherent(dev, size, va, addr)          \
-                pci_free_consistent(alpha_gendev_to_pci(dev), size, va, addr)
-#define dma_map_page(dev, page, off, size, dir)         \
-                pci_map_page(alpha_gendev_to_pci(dev), page, off, size, dir)
-#define dma_unmap_page(dev, addr, size, dir)            \
-                pci_unmap_page(alpha_gendev_to_pci(dev), addr, size, dir)
-#define dma_map_sg(dev, sg, nents, dir)                 \
-                pci_map_sg(alpha_gendev_to_pci(dev), sg, nents, dir)
-#define dma_unmap_sg(dev, sg, nents, dir)               \
-                pci_unmap_sg(alpha_gendev_to_pci(dev), sg, nents, dir)
-#define dma_supported(dev, mask)                        \
-                pci_dma_supported(alpha_gendev_to_pci(dev), mask)
-#define dma_mapping_error(dev, addr)                            \
-                pci_dma_mapping_error(alpha_gendev_to_pci(dev), addr)
-
-#else   /* no PCI - no IOMMU. */
-
-struct scatterlist;
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, gfp_t gfp);
-int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-               enum dma_data_direction direction);
-
-#define dma_free_coherent(dev, size, va, addr)          \
-                free_pages((unsigned long)va, get_order(size))
-#define dma_supported(dev, mask)                (mask < 0x00ffffffUL ? 0 : 1)
-#define dma_map_single(dev, va, size, dir)      virt_to_phys(va)
-#define dma_map_page(dev, page, off, size, dir) (page_to_pa(page) + off)
-
-#define dma_unmap_single(dev, addr, size, dir)  ((void)0)
-#define dma_unmap_page(dev, addr, size, dir)    ((void)0)
-#define dma_unmap_sg(dev, sg, nents, dir)       ((void)0)
-
-#define dma_mapping_error(dev, addr)  (0)
-
-#endif  /* !CONFIG_PCI */
-
-#define dma_alloc_noncoherent(d, s, h, f)       dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h)        dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d, h)                 (1)
-
-int dma_set_mask(struct device *dev, u64 mask);
-
-#define dma_sync_single_for_cpu(dev, addr, size, dir)     ((void)0)
-#define dma_sync_single_for_device(dev, addr, size, dir)  ((void)0)
-#define dma_sync_single_range(dev, addr, off, size, dir)  ((void)0)
-#define dma_sync_sg_for_cpu(dev, sg, nents, dir)          ((void)0)
-#define dma_sync_sg_for_device(dev, sg, nents, dir)       ((void)0)
-#define dma_cache_sync(dev, va, size, dir)                ((void)0)
-#define dma_sync_single_range_for_cpu(dev, addr, offset, size, dir)     ((void)0)
-#define dma_sync_single_range_for_device(dev, addr, offset, size, dir)  ((void)0)
-
-#define dma_get_cache_alignment()                         L1_CACHE_BYTES
-
-#endif  /* _ALPHA_DMA_MAPPING_H */
diff --git a/include/asm-alpha/dma.h b/include/asm-alpha/dma.h
deleted file mode 100644
index 87cfdbdf08fc..000000000000
--- a/include/asm-alpha/dma.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * include/asm-alpha/dma.h
- *
- * This is essentially the same as the i386 DMA stuff, as the AlphaPCs
- * use ISA-compatible dma.  The only extension is support for high-page
- * registers that allow to set the top 8 bits of a 32-bit DMA address.
- * This register should be written last when setting up a DMA address
- * as this will also enable DMA across 64 KB boundaries.
- */
-
-/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <linux/spinlock.h>
-#include <asm/io.h>
-
-#define dma_outb        outb
-#define dma_inb         inb
-
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.  
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0   
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0   
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation. 
- *
- */
-
-#define MAX_DMA_CHANNELS        8
-
-/*
-  ISA DMA limitations on Alpha platforms,
-
-  These may be due to SIO (PCI<->ISA bridge) chipset limitation, or
-  just a wiring limit.
-*/
-
-/* The maximum address for ISA DMA transfer on Alpha XL, due to an
-   hardware SIO limitation, is 64MB.
-*/
-#define ALPHA_XL_MAX_ISA_DMA_ADDRESS            0x04000000UL
-
-/* The maximum address for ISA DMA transfer on RUFFIAN,
-   due to an hardware SIO limitation, is 16MB.
-*/
-#define ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS       0x01000000UL
-
-/* The maximum address for ISA DMA transfer on SABLE, and some ALCORs,
-   due to an hardware SIO chip limitation, is 2GB.
-*/
-#define ALPHA_SABLE_MAX_ISA_DMA_ADDRESS         0x80000000UL
-#define ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS         0x80000000UL
-
-/*
-  Maximum address for all the others is the complete 32-bit bus
-  address space.
-*/
-#define ALPHA_MAX_ISA_DMA_ADDRESS               0x100000000UL
-
-#ifdef CONFIG_ALPHA_GENERIC
-# define MAX_ISA_DMA_ADDRESS            (alpha_mv.max_isa_dma_address)
-#else
-# if defined(CONFIG_ALPHA_XL)
-#  define MAX_ISA_DMA_ADDRESS           ALPHA_XL_MAX_ISA_DMA_ADDRESS
-# elif defined(CONFIG_ALPHA_RUFFIAN)
-#  define MAX_ISA_DMA_ADDRESS           ALPHA_RUFFIAN_MAX_ISA_DMA_ADDRESS
-# elif defined(CONFIG_ALPHA_SABLE)
-#  define MAX_ISA_DMA_ADDRESS           ALPHA_SABLE_MAX_ISA_DMA_ADDRESS
-# elif defined(CONFIG_ALPHA_ALCOR)
-#  define MAX_ISA_DMA_ADDRESS           ALPHA_ALCOR_MAX_ISA_DMA_ADDRESS
-# else
-#  define MAX_ISA_DMA_ADDRESS           ALPHA_MAX_ISA_DMA_ADDRESS
-# endif
-#endif
-
-/* If we have the iommu, we don't have any address limitations on DMA.
-   Otherwise (Nautilus, RX164), we have to have 0-16 Mb DMA zone
-   like i386. */
-#define MAX_DMA_ADDRESS         (alpha_mv.mv_pci_tbi ?  \
-                                 ~0UL : IDENT_ADDR + 0x01000000)
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG            0x08    /* command register (w) */
-#define DMA1_STAT_REG           0x08    /* status register (r) */
-#define DMA1_REQ_REG            0x09    /* request register (w) */
-#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
-#define DMA1_MODE_REG           0x0B    /* mode register (w) */
-#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-#define DMA1_EXT_MODE_REG       (0x400 | DMA1_MODE_REG)
-
-#define DMA2_CMD_REG            0xD0    /* command register (w) */
-#define DMA2_STAT_REG           0xD0    /* status register (r) */
-#define DMA2_REQ_REG            0xD2    /* request register (w) */
-#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
-#define DMA2_MODE_REG           0xD6    /* mode register (w) */
-#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-#define DMA2_EXT_MODE_REG       (0x400 | DMA2_MODE_REG)
-
-#define DMA_ADDR_0              0x00    /* DMA address registers */
-#define DMA_ADDR_1              0x02
-#define DMA_ADDR_2              0x04
-#define DMA_ADDR_3              0x06
-#define DMA_ADDR_4              0xC0
-#define DMA_ADDR_5              0xC4
-#define DMA_ADDR_6              0xC8
-#define DMA_ADDR_7              0xCC
-
-#define DMA_CNT_0               0x01    /* DMA count registers */
-#define DMA_CNT_1               0x03
-#define DMA_CNT_2               0x05
-#define DMA_CNT_3               0x07
-#define DMA_CNT_4               0xC2
-#define DMA_CNT_5               0xC6
-#define DMA_CNT_6               0xCA
-#define DMA_CNT_7               0xCE
-
-#define DMA_PAGE_0              0x87    /* DMA page registers */
-#define DMA_PAGE_1              0x83
-#define DMA_PAGE_2              0x81
-#define DMA_PAGE_3              0x82
-#define DMA_PAGE_5              0x8B
-#define DMA_PAGE_6              0x89
-#define DMA_PAGE_7              0x8A
-
-#define DMA_HIPAGE_0            (0x400 | DMA_PAGE_0)
-#define DMA_HIPAGE_1            (0x400 | DMA_PAGE_1)
-#define DMA_HIPAGE_2            (0x400 | DMA_PAGE_2)
-#define DMA_HIPAGE_3            (0x400 | DMA_PAGE_3)
-#define DMA_HIPAGE_4            (0x400 | DMA_PAGE_4)
-#define DMA_HIPAGE_5            (0x400 | DMA_PAGE_5)
-#define DMA_HIPAGE_6            (0x400 | DMA_PAGE_6)
-#define DMA_HIPAGE_7            (0x400 | DMA_PAGE_7)
-
-#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT    0x10
-
-extern spinlock_t  dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&dma_spin_lock, flags);
-        return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr,  DMA1_MASK_REG);
-        else
-                dma_outb(dmanr & 3,  DMA2_MASK_REG);
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr | 4,  DMA1_MASK_REG);
-        else
-                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while interrupts are disabled! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(0,  DMA1_CLEAR_FF_REG);
-        else
-                dma_outb(0,  DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-        if (dmanr<=3)
-                dma_outb(mode | dmanr,  DMA1_MODE_REG);
-        else
-                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
-}
-
-/* set extended mode for a specific DMA channel */
-static __inline__ void set_dma_ext_mode(unsigned int dmanr, char ext_mode)
-{
-        if (dmanr<=3)
-                dma_outb(ext_mode | dmanr,  DMA1_EXT_MODE_REG);
-        else
-                dma_outb(ext_mode | (dmanr&3),  DMA2_EXT_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr)
-{
-        switch(dmanr) {
-                case 0:
-                        dma_outb(pagenr, DMA_PAGE_0);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_0);
-                        break;
-                case 1:
-                        dma_outb(pagenr, DMA_PAGE_1);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_1);
-                        break;
-                case 2:
-                        dma_outb(pagenr, DMA_PAGE_2);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_2);
-                        break;
-                case 3:
-                        dma_outb(pagenr, DMA_PAGE_3);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_3);
-                        break;
-                case 5:
-                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_5);
-                        break;
-                case 6:
-                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_6);
-                        break;
-                case 7:
-                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
-                        dma_outb((pagenr >> 8), DMA_HIPAGE_7);
-                        break;
-        }
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-        if (dmanr <= 3)  {
-            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-        }  else  {
-            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-        }
-        set_dma_page(dmanr, a>>16);     /* set hipage last to enable 32-bit mode */
-}
-
-
-/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        count--;
-        if (dmanr <= 3)  {
-            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-        } else {
-            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-        }
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
-        /* using short to get 16-bit wrap around */
-        unsigned short count;
-
-        count = 1 + dma_inb(io_port);
-        count += dma_inb(io_port) << 8;
-        
-        return (dmanr<=3)? count : (count<<1);
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
-#define KERNEL_HAVE_CHECK_DMA
-extern int check_dma(unsigned int dmanr);
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy    (0)
-#endif
-
-
-#endif /* _ASM_DMA_H */
diff --git a/include/asm-alpha/elf.h b/include/asm-alpha/elf.h
deleted file mode 100644
index fc1002ea1e0c..000000000000
--- a/include/asm-alpha/elf.h
+++ /dev/null
@@ -1,165 +0,0 @@
-#ifndef __ASM_ALPHA_ELF_H
-#define __ASM_ALPHA_ELF_H
-
-#include <asm/auxvec.h>
-
-/* Special values for the st_other field in the symbol table.  */
-
-#define STO_ALPHA_NOPV          0x80
-#define STO_ALPHA_STD_GPLOAD    0x88
-
-/*
- * Alpha ELF relocation types
- */
-#define R_ALPHA_NONE            0       /* No reloc */
-#define R_ALPHA_REFLONG         1       /* Direct 32 bit */
-#define R_ALPHA_REFQUAD         2       /* Direct 64 bit */
-#define R_ALPHA_GPREL32         3       /* GP relative 32 bit */
-#define R_ALPHA_LITERAL         4       /* GP relative 16 bit w/optimization */
-#define R_ALPHA_LITUSE          5       /* Optimization hint for LITERAL */
-#define R_ALPHA_GPDISP          6       /* Add displacement to GP */
-#define R_ALPHA_BRADDR          7       /* PC+4 relative 23 bit shifted */
-#define R_ALPHA_HINT            8       /* PC+4 relative 16 bit shifted */
-#define R_ALPHA_SREL16          9       /* PC relative 16 bit */
-#define R_ALPHA_SREL32          10      /* PC relative 32 bit */
-#define R_ALPHA_SREL64          11      /* PC relative 64 bit */
-#define R_ALPHA_GPRELHIGH       17      /* GP relative 32 bit, high 16 bits */
-#define R_ALPHA_GPRELLOW        18      /* GP relative 32 bit, low 16 bits */
-#define R_ALPHA_GPREL16         19      /* GP relative 16 bit */
-#define R_ALPHA_COPY            24      /* Copy symbol at runtime */
-#define R_ALPHA_GLOB_DAT        25      /* Create GOT entry */
-#define R_ALPHA_JMP_SLOT        26      /* Create PLT entry */
-#define R_ALPHA_RELATIVE        27      /* Adjust by program base */
-#define R_ALPHA_BRSGP           28
-#define R_ALPHA_TLSGD           29
-#define R_ALPHA_TLS_LDM         30
-#define R_ALPHA_DTPMOD64        31
-#define R_ALPHA_GOTDTPREL       32
-#define R_ALPHA_DTPREL64        33
-#define R_ALPHA_DTPRELHI        34
-#define R_ALPHA_DTPRELLO        35
-#define R_ALPHA_DTPREL16        36
-#define R_ALPHA_GOTTPREL        37
-#define R_ALPHA_TPREL64         38
-#define R_ALPHA_TPRELHI         39
-#define R_ALPHA_TPRELLO         40
-#define R_ALPHA_TPREL16         41
-
-#define SHF_ALPHA_GPREL         0x10000000
-
-/* Legal values for e_flags field of Elf64_Ehdr.  */
-
-#define EF_ALPHA_32BIT          1       /* All addresses are below 2GB */
-
-/*
- * ELF register definitions..
- */
-
-/*
- * The OSF/1 version of <sys/procfs.h> makes gregset_t 46 entries long.
- * I have no idea why that is so.  For now, we just leave it at 33
- * (32 general regs + processor status word). 
- */
-#define ELF_NGREG       33
-#define ELF_NFPREG      32
-
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_ALPHA)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS64
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_ALPHA
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       8192
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         (TASK_UNMAPPED_BASE + 0x1000000)
-
-/* $0 is set by ld.so to a pointer to a function which might be 
-   registered using atexit.  This provides a mean for the dynamic
-   linker to call DT_FINI functions for shared libraries that have
-   been loaded before the code runs.
-
-   So that we can use the same startup file with static executables,
-   we start programs with a value of 0 to indicate that there is no
-   such function.  */
-
-#define ELF_PLAT_INIT(_r, load_addr)    _r->r0 = 0
-
-/* The registers are layed out in pt_regs for PAL and syscall
-   convenience.  Re-order them for the linear elf_gregset_t.  */
-
-struct pt_regs;
-struct thread_info;
-struct task_struct;
-extern void dump_elf_thread(elf_greg_t *dest, struct pt_regs *pt,
-                            struct thread_info *ti);
-#define ELF_CORE_COPY_REGS(DEST, REGS) \
-        dump_elf_thread(DEST, REGS, current_thread_info());
-
-/* Similar, but for a thread other than current.  */
-
-extern int dump_elf_task(elf_greg_t *dest, struct task_struct *task);
-#define ELF_CORE_COPY_TASK_REGS(TASK, DEST) \
-        dump_elf_task(*(DEST), TASK)
-
-/* Similar, but for the FP registers.  */
-
-extern int dump_elf_task_fp(elf_fpreg_t *dest, struct task_struct *task);
-#define ELF_CORE_COPY_FPREGS(TASK, DEST) \
-        dump_elf_task_fp(*(DEST), TASK)
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this CPU supports.  This is trivial on Alpha, 
-   but not so on other machines. */
-
-#define ELF_HWCAP  (~amask(-1))
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM                            \
-({                                              \
-        enum implver_enum i_ = implver();       \
-        ( i_ == IMPLVER_EV4 ? "ev4"             \
-        : i_ == IMPLVER_EV5                     \
-          ? (amask(AMASK_BWX) ? "ev5" : "ev56") \
-        : amask (AMASK_CIX) ? "ev6" : "ev67");  \
-})
-
-#define SET_PERSONALITY(EX, IBCS2)                              \
-        set_personality(((EX).e_flags & EF_ALPHA_32BIT)         \
-           ? PER_LINUX_32BIT : (IBCS2) ? PER_SVR4 : PER_LINUX)
-
-extern int alpha_l1i_cacheshape;
-extern int alpha_l1d_cacheshape;
-extern int alpha_l2_cacheshape;
-extern int alpha_l3_cacheshape;
-
-/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
-#define ARCH_DLINFO                                             \
-  do {                                                          \
-    NEW_AUX_ENT(AT_L1I_CACHESHAPE, alpha_l1i_cacheshape);       \
-    NEW_AUX_ENT(AT_L1D_CACHESHAPE, alpha_l1d_cacheshape);       \
-    NEW_AUX_ENT(AT_L2_CACHESHAPE, alpha_l2_cacheshape);         \
-    NEW_AUX_ENT(AT_L3_CACHESHAPE, alpha_l3_cacheshape);         \
-  } while (0)
-
-#endif /* __ASM_ALPHA_ELF_H */
diff --git a/include/asm-alpha/emergency-restart.h b/include/asm-alpha/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-alpha/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-alpha/err_common.h b/include/asm-alpha/err_common.h
deleted file mode 100644
index c25095942107..000000000000
--- a/include/asm-alpha/err_common.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- *      linux/include/asm-alpha/err_common.h
- *
- *      Copyright (C) 2000 Jeff Wiedemeier (Compaq Computer Corporation)
- *
- *      Contains declarations and macros to support Alpha error handling
- *      implementations.
- */
-
-#ifndef __ALPHA_ERR_COMMON_H
-#define __ALPHA_ERR_COMMON_H 1
-
-/*
- * SCB Vector definitions
- */
-#define SCB_Q_SYSERR    0x620
-#define SCB_Q_PROCERR   0x630
-#define SCB_Q_SYSMCHK   0x660
-#define SCB_Q_PROCMCHK  0x670
-#define SCB_Q_SYSEVENT  0x680
-
-/*
- * Disposition definitions for logout frame parser
- */
-#define MCHK_DISPOSITION_UNKNOWN_ERROR          0x00
-#define MCHK_DISPOSITION_REPORT                 0x01
-#define MCHK_DISPOSITION_DISMISS                0x02
-
-/*
- * Error Log definitions
- */
-/*
- * Types
- */
-
-#define EL_CLASS__TERMINATION           (0)
-#  define EL_TYPE__TERMINATION__TERMINATION             (0)
-#define EL_CLASS__HEADER                (5)
-#  define EL_TYPE__HEADER__SYSTEM_ERROR_FRAME           (1)
-#  define EL_TYPE__HEADER__SYSTEM_EVENT_FRAME           (2)
-#  define EL_TYPE__HEADER__HALT_FRAME                   (3)
-#  define EL_TYPE__HEADER__LOGOUT_FRAME                 (19)
-#define EL_CLASS__GENERAL_NOTIFICATION  (9)
-#define EL_CLASS__PCI_ERROR_FRAME       (11)
-#define EL_CLASS__REGATTA_FAMILY        (12)
-#  define EL_TYPE__REGATTA__PROCESSOR_ERROR_FRAME       (1)
-#  define EL_TYPE__REGATTA__SYSTEM_ERROR_FRAME          (2)
-#  define EL_TYPE__REGATTA__ENVIRONMENTAL_FRAME         (3)
-#  define EL_TYPE__REGATTA__TITAN_PCHIP0_EXTENDED       (8)
-#  define EL_TYPE__REGATTA__TITAN_PCHIP1_EXTENDED       (9)
-#  define EL_TYPE__REGATTA__TITAN_MEMORY_EXTENDED       (10)
-#  define EL_TYPE__REGATTA__PROCESSOR_DBL_ERROR_HALT    (11)
-#  define EL_TYPE__REGATTA__SYSTEM_DBL_ERROR_HALT       (12)
-#define EL_CLASS__PAL                   (14)
-#  define EL_TYPE__PAL__LOGOUT_FRAME                    (1)
-#  define EL_TYPE__PAL__EV7_PROCESSOR                   (4)
-#  define EL_TYPE__PAL__EV7_ZBOX                        (5)
-#  define EL_TYPE__PAL__EV7_RBOX                        (6)
-#  define EL_TYPE__PAL__EV7_IO                          (7)
-#  define EL_TYPE__PAL__ENV__AMBIENT_TEMPERATURE        (10)
-#  define EL_TYPE__PAL__ENV__AIRMOVER_FAN               (11)
-#  define EL_TYPE__PAL__ENV__VOLTAGE                    (12)
-#  define EL_TYPE__PAL__ENV__INTRUSION                  (13)
-#  define EL_TYPE__PAL__ENV__POWER_SUPPLY               (14)
-#  define EL_TYPE__PAL__ENV__LAN                        (15)
-#  define EL_TYPE__PAL__ENV__HOT_PLUG                   (16)
-
-union el_timestamp {
-        struct {
-                u8 second;
-                u8 minute;
-                u8 hour;
-                u8 day;
-                u8 month;
-                u8 year;
-        } b;
-        u64 as_int;
-};
-
-struct el_subpacket {
-        u16 length;             /* length of header (in bytes)  */
-        u16 class;              /* header class and type...     */
-        u16 type;               /* ...determine content         */
-        u16 revision;           /* header revision              */
-        union {
-                struct {        /* Class 5, Type 1 - System Error       */
-                        u32 frame_length;
-                        u32 frame_packet_count;                 
-                } sys_err;                      
-                struct {        /* Class 5, Type 2 - System Event       */
-                        union el_timestamp timestamp;
-                        u32 frame_length;
-                        u32 frame_packet_count;                 
-                } sys_event;
-                struct {        /* Class 5, Type 3 - Double Error Halt  */
-                        u16 halt_code;
-                        u16 reserved;
-                        union el_timestamp timestamp;
-                        u32 frame_length;
-                        u32 frame_packet_count;
-                } err_halt;
-                struct {        /* Clasee 5, Type 19 - Logout Frame Header */
-                        u32 frame_length;
-                        u32 frame_flags;
-                        u32 cpu_offset; 
-                        u32 system_offset;
-                } logout_header;
-                struct {        /* Class 12 - Regatta                   */
-                        u64 cpuid;
-                        u64 data_start[1];
-                } regatta_frame;
-                struct {        /* Raw                                  */
-                        u64 data_start[1];
-                } raw;
-        } by_type;
-};
-
-#endif /* __ALPHA_ERR_COMMON_H */
diff --git a/include/asm-alpha/err_ev6.h b/include/asm-alpha/err_ev6.h
deleted file mode 100644
index ea637791e4a9..000000000000
--- a/include/asm-alpha/err_ev6.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ALPHA_ERR_EV6_H
-#define __ALPHA_ERR_EV6_H 1
-
-/* Dummy include for now. */
-
-#endif /* __ALPHA_ERR_EV6_H */
diff --git a/include/asm-alpha/err_ev7.h b/include/asm-alpha/err_ev7.h
deleted file mode 100644
index 87f99777c2e4..000000000000
--- a/include/asm-alpha/err_ev7.h
+++ /dev/null
@@ -1,202 +0,0 @@
-#ifndef __ALPHA_ERR_EV7_H
-#define __ALPHA_ERR_EV7_H 1
-
-/*
- * Data for el packet class PAL (14), type LOGOUT_FRAME (1)
- */
-struct ev7_pal_logout_subpacket {
-        u32 mchk_code;
-        u32 subpacket_count;
-        u64 whami;
-        u64 rbox_whami;
-        u64 rbox_int;
-        u64 exc_addr;
-        union el_timestamp timestamp;
-        u64 halt_code;
-        u64 reserved;
-};
-
-/*
- * Data for el packet class PAL (14), type EV7_PROCESSOR (4)
- */
-struct ev7_pal_processor_subpacket {
-        u64 i_stat;
-        u64 dc_stat;
-        u64 c_addr;
-        u64 c_syndrome_1;
-        u64 c_syndrome_0;
-        u64 c_stat;
-        u64 c_sts;
-        u64 mm_stat;
-        u64 exc_addr;
-        u64 ier_cm;
-        u64 isum;
-        u64 pal_base;
-        u64 i_ctl;
-        u64 process_context;
-        u64 cbox_ctl;
-        u64 cbox_stp_ctl;
-        u64 cbox_acc_ctl;
-        u64 cbox_lcl_set;
-        u64 cbox_gbl_set;
-        u64 bbox_ctl;
-        u64 bbox_err_sts;
-        u64 bbox_err_idx;
-        u64 cbox_ddp_err_sts;
-        u64 bbox_dat_rmp;
-        u64 reserved[2];
-};
-
-/*
- * Data for el packet class PAL (14), type EV7_ZBOX (5)
- */
-struct ev7_pal_zbox_subpacket {
-        u32 zbox0_dram_err_status_1;
-        u32 zbox0_dram_err_status_2;
-        u32 zbox0_dram_err_status_3;
-        u32 zbox0_dram_err_ctl;
-        u32 zbox0_dram_err_adr;
-        u32 zbox0_dift_timeout;
-        u32 zbox0_dram_mapper_ctl;
-        u32 zbox0_frc_err_adr;
-        u32 zbox0_dift_err_status;
-        u32 reserved1;
-        u32 zbox1_dram_err_status_1;
-        u32 zbox1_dram_err_status_2;
-        u32 zbox1_dram_err_status_3;
-        u32 zbox1_dram_err_ctl;
-        u32 zbox1_dram_err_adr;
-        u32 zbox1_dift_timeout;
-        u32 zbox1_dram_mapper_ctl;
-        u32 zbox1_frc_err_adr;
-        u32 zbox1_dift_err_status;
-        u32 reserved2;
-        u64 cbox_ctl;
-        u64 cbox_stp_ctl;
-        u64 zbox0_error_pa;
-        u64 zbox1_error_pa;
-        u64 zbox0_ored_syndrome;
-        u64 zbox1_ored_syndrome;
-        u64 reserved3[2];
-};
-
-/*
- * Data for el packet class PAL (14), type EV7_RBOX (6)
- */
-struct ev7_pal_rbox_subpacket {
-        u64 rbox_cfg;
-        u64 rbox_n_cfg;
-        u64 rbox_s_cfg;
-        u64 rbox_e_cfg;
-        u64 rbox_w_cfg;
-        u64 rbox_n_err;
-        u64 rbox_s_err;
-        u64 rbox_e_err;
-        u64 rbox_w_err;
-        u64 rbox_io_cfg;
-        u64 rbox_io_err;
-        u64 rbox_l_err;
-        u64 rbox_whoami;
-        u64 rbox_imask;
-        u64 rbox_intq;
-        u64 rbox_int;
-        u64 reserved[2];
-};
-
-/*
- * Data for el packet class PAL (14), type EV7_IO (7)
- */
-struct ev7_pal_io_one_port {
-        u64 pox_err_sum;
-        u64 pox_tlb_err;
-        u64 pox_spl_cmplt;
-        u64 pox_trans_sum;
-        u64 pox_first_err;
-        u64 pox_mult_err;
-        u64 pox_dm_source;
-        u64 pox_dm_dest;
-        u64 pox_dm_size;
-        u64 pox_dm_ctrl;
-        u64 reserved;
-};
-
-struct ev7_pal_io_subpacket {
-        u64 io_asic_rev;
-        u64 io_sys_rev;
-        u64 io7_uph;
-        u64 hpi_ctl;
-        u64 crd_ctl;
-        u64 hei_ctl;
-        u64 po7_error_sum;
-        u64 po7_uncrr_sym;
-        u64 po7_crrct_sym;
-        u64 po7_ugbge_sym;
-        u64 po7_err_pkt0;
-        u64 po7_err_pkt1;
-        u64 reserved[2];
-        struct ev7_pal_io_one_port ports[4];
-};
-
-/*
- * Environmental subpacket. Data used for el packets:
- *         class PAL (14), type AMBIENT_TEMPERATURE (10)
- *         class PAL (14), type AIRMOVER_FAN (11)
- *         class PAL (14), type VOLTAGE (12)
- *         class PAL (14), type INTRUSION (13)
- *         class PAL (14), type POWER_SUPPLY (14)
- *         class PAL (14), type LAN (15)
- *         class PAL (14), type HOT_PLUG (16)
- */
-struct ev7_pal_environmental_subpacket {
-        u16 cabinet;
-        u16 drawer;
-        u16 reserved1[2];
-        u8 module_type;
-        u8 unit_id;             /* unit reporting condition */
-        u8 reserved2;
-        u8 condition;           /* condition reported       */
-};
-
-/*
- * Convert environmental type to index
- */
-static inline int ev7_lf_env_index(int type)
-{
-        BUG_ON((type < EL_TYPE__PAL__ENV__AMBIENT_TEMPERATURE) 
-               || (type > EL_TYPE__PAL__ENV__HOT_PLUG));
-
-        return type - EL_TYPE__PAL__ENV__AMBIENT_TEMPERATURE;
-}
-
-/*
- * Data for generic el packet class PAL.
- */
-struct ev7_pal_subpacket {
-        union {
-                struct ev7_pal_logout_subpacket logout;      /* Type     1 */
-                struct ev7_pal_processor_subpacket ev7;      /* Type     4 */
-                struct ev7_pal_zbox_subpacket zbox;          /* Type     5 */
-                struct ev7_pal_rbox_subpacket rbox;          /* Type     6 */
-                struct ev7_pal_io_subpacket io;              /* Type     7 */
-                struct ev7_pal_environmental_subpacket env;  /* Type 10-16 */
-                u64 as_quad[1];                              /* Raw u64    */
-        } by_type;
-};
-
-/*
- * Struct to contain collected logout from subpackets.
- */
-struct ev7_lf_subpackets {
-        struct ev7_pal_logout_subpacket *logout;                /* Type  1 */
-        struct ev7_pal_processor_subpacket *ev7;                /* Type  4 */
-        struct ev7_pal_zbox_subpacket *zbox;                    /* Type  5 */
-        struct ev7_pal_rbox_subpacket *rbox;                    /* Type  6 */
-        struct ev7_pal_io_subpacket *io;                        /* Type  7 */
-        struct ev7_pal_environmental_subpacket *env[7];      /* Type 10-16 */
-
-        unsigned int io_pid;
-};
-
-#endif /* __ALPHA_ERR_EV7_H */
-
-
diff --git a/include/asm-alpha/errno.h b/include/asm-alpha/errno.h
deleted file mode 100644
index 69e2655249d2..000000000000
--- a/include/asm-alpha/errno.h
+++ /dev/null
@@ -1,123 +0,0 @@
-#ifndef _ALPHA_ERRNO_H
-#define _ALPHA_ERRNO_H
-
-#include <asm-generic/errno-base.h>
-
-#undef  EAGAIN                  /* 11 in errno-base.h */
-
-#define EDEADLK         11      /* Resource deadlock would occur */
-
-#define EAGAIN          35      /* Try again */
-#define EWOULDBLOCK     EAGAIN  /* Operation would block */
-#define EINPROGRESS     36      /* Operation now in progress */
-#define EALREADY        37      /* Operation already in progress */
-#define ENOTSOCK        38      /* Socket operation on non-socket */
-#define EDESTADDRREQ    39      /* Destination address required */
-#define EMSGSIZE        40      /* Message too long */
-#define EPROTOTYPE      41      /* Protocol wrong type for socket */
-#define ENOPROTOOPT     42      /* Protocol not available */
-#define EPROTONOSUPPORT 43      /* Protocol not supported */
-#define ESOCKTNOSUPPORT 44      /* Socket type not supported */
-#define EOPNOTSUPP      45      /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT    46      /* Protocol family not supported */
-#define EAFNOSUPPORT    47      /* Address family not supported by protocol */
-#define EADDRINUSE      48      /* Address already in use */
-#define EADDRNOTAVAIL   49      /* Cannot assign requested address */
-#define ENETDOWN        50      /* Network is down */
-#define ENETUNREACH     51      /* Network is unreachable */
-#define ENETRESET       52      /* Network dropped connection because of reset */
-#define ECONNABORTED    53      /* Software caused connection abort */
-#define ECONNRESET      54      /* Connection reset by peer */
-#define ENOBUFS         55      /* No buffer space available */
-#define EISCONN         56      /* Transport endpoint is already connected */
-#define ENOTCONN        57      /* Transport endpoint is not connected */
-#define ESHUTDOWN       58      /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS    59      /* Too many references: cannot splice */
-#define ETIMEDOUT       60      /* Connection timed out */
-#define ECONNREFUSED    61      /* Connection refused */
-#define ELOOP           62      /* Too many symbolic links encountered */
-#define ENAMETOOLONG    63      /* File name too long */
-#define EHOSTDOWN       64      /* Host is down */
-#define EHOSTUNREACH    65      /* No route to host */
-#define ENOTEMPTY       66      /* Directory not empty */
-
-#define EUSERS          68      /* Too many users */
-#define EDQUOT          69      /* Quota exceeded */
-#define ESTALE          70      /* Stale NFS file handle */
-#define EREMOTE         71      /* Object is remote */
-
-#define ENOLCK          77      /* No record locks available */
-#define ENOSYS          78      /* Function not implemented */
-
-#define ENOMSG          80      /* No message of desired type */
-#define EIDRM           81      /* Identifier removed */
-#define ENOSR           82      /* Out of streams resources */
-#define ETIME           83      /* Timer expired */
-#define EBADMSG         84      /* Not a data message */
-#define EPROTO          85      /* Protocol error */
-#define ENODATA         86      /* No data available */
-#define ENOSTR          87      /* Device not a stream */
-
-#define ENOPKG          92      /* Package not installed */
-
-#define EILSEQ          116     /* Illegal byte sequence */
-
-/* The following are just random noise.. */
-#define ECHRNG          88      /* Channel number out of range */
-#define EL2NSYNC        89      /* Level 2 not synchronized */
-#define EL3HLT          90      /* Level 3 halted */
-#define EL3RST          91      /* Level 3 reset */
-
-#define ELNRNG          93      /* Link number out of range */
-#define EUNATCH         94      /* Protocol driver not attached */
-#define ENOCSI          95      /* No CSI structure available */
-#define EL2HLT          96      /* Level 2 halted */
-#define EBADE           97      /* Invalid exchange */
-#define EBADR           98      /* Invalid request descriptor */
-#define EXFULL          99      /* Exchange full */
-#define ENOANO          100     /* No anode */
-#define EBADRQC         101     /* Invalid request code */
-#define EBADSLT         102     /* Invalid slot */
-
-#define EDEADLOCK       EDEADLK
-
-#define EBFONT          104     /* Bad font file format */
-#define ENONET          105     /* Machine is not on the network */
-#define ENOLINK         106     /* Link has been severed */
-#define EADV            107     /* Advertise error */
-#define ESRMNT          108     /* Srmount error */
-#define ECOMM           109     /* Communication error on send */
-#define EMULTIHOP       110     /* Multihop attempted */
-#define EDOTDOT         111     /* RFS specific error */
-#define EOVERFLOW       112     /* Value too large for defined data type */
-#define ENOTUNIQ        113     /* Name not unique on network */
-#define EBADFD          114     /* File descriptor in bad state */
-#define EREMCHG         115     /* Remote address changed */
-
-#define EUCLEAN         117     /* Structure needs cleaning */
-#define ENOTNAM         118     /* Not a XENIX named type file */
-#define ENAVAIL         119     /* No XENIX semaphores available */
-#define EISNAM          120     /* Is a named type file */
-#define EREMOTEIO       121     /* Remote I/O error */
-
-#define ELIBACC         122     /* Can not access a needed shared library */
-#define ELIBBAD         123     /* Accessing a corrupted shared library */
-#define ELIBSCN         124     /* .lib section in a.out corrupted */
-#define ELIBMAX         125     /* Attempting to link in too many shared libraries */
-#define ELIBEXEC        126     /* Cannot exec a shared library directly */
-#define ERESTART        127     /* Interrupted system call should be restarted */
-#define ESTRPIPE        128     /* Streams pipe error */
-
-#define ENOMEDIUM       129     /* No medium found */
-#define EMEDIUMTYPE     130     /* Wrong medium type */
-#define ECANCELED       131     /* Operation Cancelled */
-#define ENOKEY          132     /* Required key not available */
-#define EKEYEXPIRED     133     /* Key has expired */
-#define EKEYREVOKED     134     /* Key has been revoked */
-#define EKEYREJECTED    135     /* Key was rejected by service */
-
-/* for robust mutexes */
-#define EOWNERDEAD      136     /* Owner died */
-#define ENOTRECOVERABLE 137     /* State not recoverable */
-
-#endif
diff --git a/include/asm-alpha/fb.h b/include/asm-alpha/fb.h
deleted file mode 100644
index fa9bbb96b2b3..000000000000
--- a/include/asm-alpha/fb.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/device.h>
-
-/* Caching is off in the I/O space quadrant by design.  */
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-        return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-alpha/fcntl.h b/include/asm-alpha/fcntl.h
deleted file mode 100644
index 25da0017ec87..000000000000
--- a/include/asm-alpha/fcntl.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef _ALPHA_FCNTL_H
-#define _ALPHA_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_CREAT          01000  /* not fcntl */
-#define O_TRUNC          02000  /* not fcntl */
-#define O_EXCL           04000  /* not fcntl */
-#define O_NOCTTY        010000  /* not fcntl */
-
-#define O_NONBLOCK       00004
-#define O_APPEND         00010
-#define O_SYNC          040000
-#define O_DIRECTORY     0100000 /* must be a directory */
-#define O_NOFOLLOW      0200000 /* don't follow links */
-#define O_LARGEFILE     0400000 /* will be set by the kernel on every open */
-#define O_DIRECT        02000000 /* direct disk access - should check with OSF/1 */
-#define O_NOATIME       04000000
-#define O_CLOEXEC       010000000 /* set close_on_exec */
-
-#define F_GETLK         7
-#define F_SETLK         8
-#define F_SETLKW        9
-
-#define F_SETOWN        5       /*  for sockets. */
-#define F_GETOWN        6       /*  for sockets. */
-#define F_SETSIG        10      /*  for sockets. */
-#define F_GETSIG        11      /*  for sockets. */
-
-/* for posix fcntl() and lockf() */
-#define F_RDLCK         1
-#define F_WRLCK         2
-#define F_UNLCK         8
-
-/* for old implementation of bsd flock () */
-#define F_EXLCK         16      /* or 3 */
-#define F_SHLCK         32      /* or 4 */
-
-#define F_INPROGRESS    64
-
-#include <asm-generic/fcntl.h>
-
-#endif
diff --git a/include/asm-alpha/floppy.h b/include/asm-alpha/floppy.h
deleted file mode 100644
index 0be50413b2b5..000000000000
--- a/include/asm-alpha/floppy.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Architecture specific parts of the Floppy driver
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995
- */
-#ifndef __ASM_ALPHA_FLOPPY_H
-#define __ASM_ALPHA_FLOPPY_H
-
-
-#define fd_inb(port)                    inb_p(port)
-#define fd_outb(value,port)             outb_p(value,port)
-
-#define fd_enable_dma()         enable_dma(FLOPPY_DMA)
-#define fd_disable_dma()        disable_dma(FLOPPY_DMA)
-#define fd_request_dma()        request_dma(FLOPPY_DMA,"floppy")
-#define fd_free_dma()           free_dma(FLOPPY_DMA)
-#define fd_clear_dma_ff()       clear_dma_ff(FLOPPY_DMA)
-#define fd_set_dma_mode(mode)   set_dma_mode(FLOPPY_DMA,mode)
-#define fd_set_dma_addr(addr)   set_dma_addr(FLOPPY_DMA,virt_to_bus(addr))
-#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA,count)
-#define fd_enable_irq()         enable_irq(FLOPPY_IRQ)
-#define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
-#define fd_cacheflush(addr,size) /* nothing */
-#define fd_request_irq()        request_irq(FLOPPY_IRQ, floppy_interrupt,\
-                                            IRQF_DISABLED, "floppy", NULL)
-#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
-
-#ifdef CONFIG_PCI
-
-#include <linux/pci.h>
-
-#define fd_dma_setup(addr,size,mode,io) alpha_fd_dma_setup(addr,size,mode,io)
-
-static __inline__ int 
-alpha_fd_dma_setup(char *addr, unsigned long size, int mode, int io)
-{
-        static unsigned long prev_size;
-        static dma_addr_t bus_addr = 0;
-        static char *prev_addr;
-        static int prev_dir;
-        int dir;
-
-        dir = (mode != DMA_MODE_READ) ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE;
-
-        if (bus_addr 
-            && (addr != prev_addr || size != prev_size || dir != prev_dir)) {
-                /* different from last time -- unmap prev */
-                pci_unmap_single(isa_bridge, bus_addr, prev_size, prev_dir);
-                bus_addr = 0;
-        }
-
-        if (!bus_addr)  /* need to map it */
-                bus_addr = pci_map_single(isa_bridge, addr, size, dir);
-
-        /* remember this one as prev */
-        prev_addr = addr;
-        prev_size = size;
-        prev_dir = dir;
-
-        fd_clear_dma_ff();
-        fd_cacheflush(addr, size);
-        fd_set_dma_mode(mode);
-        set_dma_addr(FLOPPY_DMA, bus_addr);
-        fd_set_dma_count(size);
-        virtual_dma_port = io;
-        fd_enable_dma();
-
-        return 0;
-}
-
-#endif /* CONFIG_PCI */
-
-__inline__ void virtual_dma_init(void)
-{
-        /* Nothing to do on an Alpha */
-}
-
-static int FDC1 = 0x3f0;
-static int FDC2 = -1;
-
-/*
- * Again, the CMOS information doesn't work on the alpha..
- */
-#define FLOPPY0_TYPE 6
-#define FLOPPY1_TYPE 0
-
-#define N_FDC 2
-#define N_DRIVE 8
-
-/*
- * Most Alphas have no problems with floppy DMA crossing 64k borders,
- * except for certain ones, like XL and RUFFIAN.
- *
- * However, the test is simple and fast, and this *is* floppy, after all,
- * so we do it for all platforms, just to make sure.
- *
- * This is advantageous in other circumstances as well, as in moving
- * about the PCI DMA windows and forcing the floppy to start doing
- * scatter-gather when it never had before, and there *is* a problem
- * on that platform... ;-}
- */
-
-static inline unsigned long CROSS_64KB(void *a, unsigned long s)
-{
-        unsigned long p = (unsigned long)a;
-        return ((p + s - 1) ^ p) & ~0xffffUL;
-}
-
-#define EXTRA_FLOPPY_PARAMS
-
-#endif /* __ASM_ALPHA_FLOPPY_H */
diff --git a/include/asm-alpha/fpu.h b/include/asm-alpha/fpu.h
deleted file mode 100644
index ecb17a72acc3..000000000000
--- a/include/asm-alpha/fpu.h
+++ /dev/null
@@ -1,193 +0,0 @@
-#ifndef __ASM_ALPHA_FPU_H
-#define __ASM_ALPHA_FPU_H
-
-/*
- * Alpha floating-point control register defines:
- */
-#define FPCR_DNOD       (1UL<<47)       /* denorm INV trap disable */
-#define FPCR_DNZ        (1UL<<48)       /* denorms to zero */
-#define FPCR_INVD       (1UL<<49)       /* invalid op disable (opt.) */
-#define FPCR_DZED       (1UL<<50)       /* division by zero disable (opt.) */
-#define FPCR_OVFD       (1UL<<51)       /* overflow disable (optional) */
-#define FPCR_INV        (1UL<<52)       /* invalid operation */
-#define FPCR_DZE        (1UL<<53)       /* division by zero */
-#define FPCR_OVF        (1UL<<54)       /* overflow */
-#define FPCR_UNF        (1UL<<55)       /* underflow */
-#define FPCR_INE        (1UL<<56)       /* inexact */
-#define FPCR_IOV        (1UL<<57)       /* integer overflow */
-#define FPCR_UNDZ       (1UL<<60)       /* underflow to zero (opt.) */
-#define FPCR_UNFD       (1UL<<61)       /* underflow disable (opt.) */
-#define FPCR_INED       (1UL<<62)       /* inexact disable (opt.) */
-#define FPCR_SUM        (1UL<<63)       /* summary bit */
-
-#define FPCR_DYN_SHIFT  58              /* first dynamic rounding mode bit */
-#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT)      /* towards 0 */
-#define FPCR_DYN_MINUS   (0x1UL << FPCR_DYN_SHIFT)      /* towards -INF */
-#define FPCR_DYN_NORMAL  (0x2UL << FPCR_DYN_SHIFT)      /* towards nearest */
-#define FPCR_DYN_PLUS    (0x3UL << FPCR_DYN_SHIFT)      /* towards +INF */
-#define FPCR_DYN_MASK    (0x3UL << FPCR_DYN_SHIFT)
-
-#define FPCR_MASK       0xffff800000000000L
-
-/*
- * IEEE trap enables are implemented in software.  These per-thread
- * bits are stored in the "ieee_state" field of "struct thread_info".
- * Thus, the bits are defined so as not to conflict with the
- * floating-point enable bit (which is architected).  On top of that,
- * we want to make these bits compatible with OSF/1 so
- * ieee_set_fp_control() etc. can be implemented easily and
- * compatibly.  The corresponding definitions are in
- * /usr/include/machine/fpu.h under OSF/1.
- */
-#define IEEE_TRAP_ENABLE_INV    (1UL<<1)        /* invalid op */
-#define IEEE_TRAP_ENABLE_DZE    (1UL<<2)        /* division by zero */
-#define IEEE_TRAP_ENABLE_OVF    (1UL<<3)        /* overflow */
-#define IEEE_TRAP_ENABLE_UNF    (1UL<<4)        /* underflow */
-#define IEEE_TRAP_ENABLE_INE    (1UL<<5)        /* inexact */
-#define IEEE_TRAP_ENABLE_DNO    (1UL<<6)        /* denorm */
-#define IEEE_TRAP_ENABLE_MASK   (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\
-                                 IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\
-                                 IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO)
-
-/* Denorm and Underflow flushing */
-#define IEEE_MAP_DMZ            (1UL<<12)       /* Map denorm inputs to zero */
-#define IEEE_MAP_UMZ            (1UL<<13)       /* Map underflowed outputs to zero */
-
-#define IEEE_MAP_MASK           (IEEE_MAP_DMZ | IEEE_MAP_UMZ)
-
-/* status bits coming from fpcr: */
-#define IEEE_STATUS_INV         (1UL<<17)
-#define IEEE_STATUS_DZE         (1UL<<18)
-#define IEEE_STATUS_OVF         (1UL<<19)
-#define IEEE_STATUS_UNF         (1UL<<20)
-#define IEEE_STATUS_INE         (1UL<<21)
-#define IEEE_STATUS_DNO         (1UL<<22)
-
-#define IEEE_STATUS_MASK        (IEEE_STATUS_INV | IEEE_STATUS_DZE |    \
-                                 IEEE_STATUS_OVF | IEEE_STATUS_UNF |    \
-                                 IEEE_STATUS_INE | IEEE_STATUS_DNO)
-
-#define IEEE_SW_MASK            (IEEE_TRAP_ENABLE_MASK |                \
-                                 IEEE_STATUS_MASK | IEEE_MAP_MASK)
-
-#define IEEE_CURRENT_RM_SHIFT   32
-#define IEEE_CURRENT_RM_MASK    (3UL<<IEEE_CURRENT_RM_SHIFT)
-
-#define IEEE_STATUS_TO_EXCSUM_SHIFT     16
-
-#define IEEE_INHERIT    (1UL<<63)       /* inherit on thread create? */
-
-/*
- * Convert the software IEEE trap enable and status bits into the
- * hardware fpcr format. 
- *
- * Digital Unix engineers receive my thanks for not defining the
- * software bits identical to the hardware bits.  The chip designers
- * receive my thanks for making all the not-implemented fpcr bits
- * RAZ forcing us to use system calls to read/write this value.
- */
-
-static inline unsigned long
-ieee_swcr_to_fpcr(unsigned long sw)
-{
-        unsigned long fp;
-        fp = (sw & IEEE_STATUS_MASK) << 35;
-        fp |= (sw & IEEE_MAP_DMZ) << 36;
-        fp |= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0);
-        fp |= (~sw & (IEEE_TRAP_ENABLE_INV
-                      | IEEE_TRAP_ENABLE_DZE
-                      | IEEE_TRAP_ENABLE_OVF)) << 48;
-        fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57;
-        fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0);
-        fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41;
-        return fp;
-}
-
-static inline unsigned long
-ieee_fpcr_to_swcr(unsigned long fp)
-{
-        unsigned long sw;
-        sw = (fp >> 35) & IEEE_STATUS_MASK;
-        sw |= (fp >> 36) & IEEE_MAP_DMZ;
-        sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV
-                             | IEEE_TRAP_ENABLE_DZE
-                             | IEEE_TRAP_ENABLE_OVF);
-        sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE);
-        sw |= (fp >> 47) & IEEE_MAP_UMZ;
-        sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO;
-        return sw;
-}
-
-#ifdef __KERNEL__
-
-/* The following two functions don't need trapb/excb instructions
-   around the mf_fpcr/mt_fpcr instructions because (a) the kernel
-   never generates arithmetic faults and (b) call_pal instructions
-   are implied trap barriers.  */
-
-static inline unsigned long
-rdfpcr(void)
-{
-        unsigned long tmp, ret;
-
-#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
-        __asm__ __volatile__ (
-                "ftoit $f0,%0\n\t"
-                "mf_fpcr $f0\n\t"
-                "ftoit $f0,%1\n\t"
-                "itoft %0,$f0"
-                : "=r"(tmp), "=r"(ret));
-#else
-        __asm__ __volatile__ (
-                "stt $f0,%0\n\t"
-                "mf_fpcr $f0\n\t"
-                "stt $f0,%1\n\t"
-                "ldt $f0,%0"
-                : "=m"(tmp), "=m"(ret));
-#endif
-
-        return ret;
-}
-
-static inline void
-wrfpcr(unsigned long val)
-{
-        unsigned long tmp;
-
-#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
-        __asm__ __volatile__ (
-                "ftoit $f0,%0\n\t"
-                "itoft %1,$f0\n\t"
-                "mt_fpcr $f0\n\t"
-                "itoft %0,$f0"
-                : "=&r"(tmp) : "r"(val));
-#else
-        __asm__ __volatile__ (
-                "stt $f0,%0\n\t"
-                "ldt $f0,%1\n\t"
-                "mt_fpcr $f0\n\t"
-                "ldt $f0,%0"
-                : "=m"(tmp) : "m"(val));
-#endif
-}
-
-static inline unsigned long
-swcr_update_status(unsigned long swcr, unsigned long fpcr)
-{
-        /* EV6 implements most of the bits in hardware.  Collect
-           the acrued exception bits from the real fpcr.  */
-        if (implver() == IMPLVER_EV6) {
-                swcr &= ~IEEE_STATUS_MASK;
-                swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
-        }
-        return swcr;
-}
-
-extern unsigned long alpha_read_fp_reg (unsigned long reg);
-extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
-extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
-extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_ALPHA_FPU_H */
diff --git a/include/asm-alpha/futex.h b/include/asm-alpha/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/include/asm-alpha/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/include/asm-alpha/gct.h b/include/asm-alpha/gct.h
deleted file mode 100644
index 3504c704927c..000000000000
--- a/include/asm-alpha/gct.h
+++ /dev/null
@@ -1,58 +0,0 @@
-#ifndef __ALPHA_GCT_H
-#define __ALPHA_GCT_H
-
-typedef u64 gct_id;
-typedef u64 gct6_handle;
-
-typedef struct __gct6_node {
-        u8 type;        
-        u8 subtype;
-        u16 size;
-        u32 hd_extension;
-        gct6_handle owner;
-        gct6_handle active_user;
-        gct_id id;
-        u64 flags;
-        u16 rev;
-        u16 change_counter;
-        u16 max_child;
-        u16 reserved1;
-        gct6_handle saved_owner;
-        gct6_handle affinity;
-        gct6_handle parent;
-        gct6_handle next;
-        gct6_handle prev;
-        gct6_handle child;
-        u64 fw_flags;
-        u64 os_usage;
-        u64 fru_id;
-        u32 checksum;
-        u32 magic;      /* 'GLXY' */
-} gct6_node;
-
-typedef struct {
-        u8 type;        
-        u8 subtype;
-        void (*callout)(gct6_node *);
-} gct6_search_struct;
-
-#define GCT_NODE_MAGIC    0x59584c47    /* 'GLXY' */
-
-/* 
- * node types 
- */
-#define GCT_TYPE_HOSE                   0x0E
-
-/*
- * node subtypes
- */
-#define GCT_SUBTYPE_IO_PORT_MODULE      0x2C
-
-#define GCT_NODE_PTR(off) ((gct6_node *)((char *)hwrpb +                \
-                                         hwrpb->frut_offset +           \
-                                         (gct6_handle)(off)))           \
-
-int gct6_find_nodes(gct6_node *, gct6_search_struct *);
-
-#endif /* __ALPHA_GCT_H */
-
diff --git a/include/asm-alpha/gentrap.h b/include/asm-alpha/gentrap.h
deleted file mode 100644
index ae50cc3192c7..000000000000
--- a/include/asm-alpha/gentrap.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef _ASMAXP_GENTRAP_H
-#define _ASMAXP_GENTRAP_H
-
-/*
- * Definitions for gentrap causes.  They are generated by user-level
- * programs and therefore should be compatible with the corresponding
- * OSF/1 definitions.
- */
-#define GEN_INTOVF      -1      /* integer overflow */
-#define GEN_INTDIV      -2      /* integer division by zero */
-#define GEN_FLTOVF      -3      /* fp overflow */
-#define GEN_FLTDIV      -4      /* fp division by zero */
-#define GEN_FLTUND      -5      /* fp underflow */
-#define GEN_FLTINV      -6      /* invalid fp operand */
-#define GEN_FLTINE      -7      /* inexact fp operand */
-#define GEN_DECOVF      -8      /* decimal overflow (for COBOL??) */
-#define GEN_DECDIV      -9      /* decimal division by zero */
-#define GEN_DECINV      -10     /* invalid decimal operand */
-#define GEN_ROPRAND     -11     /* reserved operand */
-#define GEN_ASSERTERR   -12     /* assertion error */
-#define GEN_NULPTRERR   -13     /* null pointer error */
-#define GEN_STKOVF      -14     /* stack overflow */
-#define GEN_STRLENERR   -15     /* string length error */
-#define GEN_SUBSTRERR   -16     /* substring error */
-#define GEN_RANGERR     -17     /* range error */
-#define GEN_SUBRNG      -18
-#define GEN_SUBRNG1     -19      
-#define GEN_SUBRNG2     -20
-#define GEN_SUBRNG3     -21     /* these report range errors for */
-#define GEN_SUBRNG4     -22     /* subscripting (indexing) at levels 0..7 */
-#define GEN_SUBRNG5     -23
-#define GEN_SUBRNG6     -24
-#define GEN_SUBRNG7     -25
-
-/* the remaining codes (-26..-1023) are reserved. */
-
-#endif /* _ASMAXP_GENTRAP_H */
diff --git a/include/asm-alpha/hardirq.h b/include/asm-alpha/hardirq.h
deleted file mode 100644
index d953e234daa8..000000000000
--- a/include/asm-alpha/hardirq.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ALPHA_HARDIRQ_H
-#define _ALPHA_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/cache.h>
-
-
-/* entry.S is sensitive to the offsets of these fields */
-typedef struct {
-        unsigned long __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-void ack_bad_irq(unsigned int irq);
-
-#define HARDIRQ_BITS    12
-
-/*
- * The hardirq mask has to be large enough to have
- * space for potentially nestable IRQ sources in the system
- * to nest on a single CPU. On Alpha, interrupts are masked at the CPU
- * by IPL as well as at the system level. We only have 8 IPLs (UNIX PALcode)
- * so we really only have 8 nestable IRQs, but allow some overhead
- */
-#if (1 << HARDIRQ_BITS) < 16
-#error HARDIRQ_BITS is too low!
-#endif
-
-#endif /* _ALPHA_HARDIRQ_H */
diff --git a/include/asm-alpha/hw_irq.h b/include/asm-alpha/hw_irq.h
deleted file mode 100644
index a37db0f95092..000000000000
--- a/include/asm-alpha/hw_irq.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ALPHA_HW_IRQ_H
-#define _ALPHA_HW_IRQ_H
-
-
-extern volatile unsigned long irq_err_count;
-
-#ifdef CONFIG_ALPHA_GENERIC
-#define ACTUAL_NR_IRQS  alpha_mv.nr_irqs
-#else
-#define ACTUAL_NR_IRQS  NR_IRQS
-#endif
-
-#endif
diff --git a/include/asm-alpha/hwrpb.h b/include/asm-alpha/hwrpb.h
deleted file mode 100644
index 8e8f871af7cf..000000000000
--- a/include/asm-alpha/hwrpb.h
+++ /dev/null
@@ -1,220 +0,0 @@
-#ifndef __ALPHA_HWRPB_H
-#define __ALPHA_HWRPB_H
-
-#define INIT_HWRPB ((struct hwrpb_struct *) 0x10000000)
-
-/*
- * DEC processor types for Alpha systems.  Found in HWRPB.
- * These values are architected.
- */
-
-#define EV3_CPU                 1       /* EV3                  */
-#define EV4_CPU                 2       /* EV4 (21064)          */
-#define LCA4_CPU                4       /* LCA4 (21066/21068)   */
-#define EV5_CPU                 5       /* EV5 (21164)          */
-#define EV45_CPU                6       /* EV4.5 (21064/xxx)    */
-#define EV56_CPU                7       /* EV5.6 (21164)        */
-#define EV6_CPU                 8       /* EV6 (21264)          */
-#define PCA56_CPU               9       /* PCA56 (21164PC)      */
-#define PCA57_CPU               10      /* PCA57 (notyet)       */
-#define EV67_CPU                11      /* EV67 (21264A)        */
-#define EV68CB_CPU              12      /* EV68CB (21264C)      */
-#define EV68AL_CPU              13      /* EV68AL (21264B)      */
-#define EV68CX_CPU              14      /* EV68CX (21264D)      */
-#define EV7_CPU                 15      /* EV7 (21364)          */
-#define EV79_CPU                16      /* EV79 (21364??)       */
-#define EV69_CPU                17      /* EV69 (21264/EV69A)   */
-
-/*
- * DEC system types for Alpha systems.  Found in HWRPB.
- * These values are architected.
- */
-
-#define ST_ADU                    1     /* Alpha ADU systype    */
-#define ST_DEC_4000               2     /* Cobra systype        */
-#define ST_DEC_7000               3     /* Ruby systype         */
-#define ST_DEC_3000_500           4     /* Flamingo systype     */
-#define ST_DEC_2000_300           6     /* Jensen systype       */
-#define ST_DEC_3000_300           7     /* Pelican systype      */
-#define ST_DEC_2100_A500          9     /* Sable systype        */
-#define ST_DEC_AXPVME_64         10     /* AXPvme system type   */
-#define ST_DEC_AXPPCI_33         11     /* NoName system type   */
-#define ST_DEC_TLASER            12     /* Turbolaser systype   */
-#define ST_DEC_2100_A50          13     /* Avanti systype       */
-#define ST_DEC_MUSTANG           14     /* Mustang systype      */
-#define ST_DEC_ALCOR             15     /* Alcor (EV5) systype  */
-#define ST_DEC_1000              17     /* Mikasa systype       */
-#define ST_DEC_EB64              18     /* EB64 systype         */
-#define ST_DEC_EB66              19     /* EB66 systype         */
-#define ST_DEC_EB64P             20     /* EB64+ systype        */
-#define ST_DEC_BURNS             21     /* laptop systype       */
-#define ST_DEC_RAWHIDE           22     /* Rawhide systype      */
-#define ST_DEC_K2                23     /* K2 systype           */
-#define ST_DEC_LYNX              24     /* Lynx systype         */
-#define ST_DEC_XL                25     /* Alpha XL systype     */
-#define ST_DEC_EB164             26     /* EB164 systype        */
-#define ST_DEC_NORITAKE          27     /* Noritake systype     */
-#define ST_DEC_CORTEX            28     /* Cortex systype       */
-#define ST_DEC_MIATA             30     /* Miata systype        */
-#define ST_DEC_XXM               31     /* XXM systype          */
-#define ST_DEC_TAKARA            32     /* Takara systype       */
-#define ST_DEC_YUKON             33     /* Yukon systype        */
-#define ST_DEC_TSUNAMI           34     /* Tsunami systype      */
-#define ST_DEC_WILDFIRE          35     /* Wildfire systype     */
-#define ST_DEC_CUSCO             36     /* CUSCO systype        */
-#define ST_DEC_EIGER             37     /* Eiger systype        */
-#define ST_DEC_TITAN             38     /* Titan systype        */
-#define ST_DEC_MARVEL            39     /* Marvel systype       */
-
-/* UNOFFICIAL!!! */
-#define ST_UNOFFICIAL_BIAS      100
-#define ST_DTI_RUFFIAN          101     /* RUFFIAN systype      */
-
-/* Alpha Processor, Inc. systems */
-#define ST_API_BIAS             200
-#define ST_API_NAUTILUS         201     /* UP1000 systype       */
-
-struct pcb_struct {
-        unsigned long ksp;
-        unsigned long usp;
-        unsigned long ptbr;
-        unsigned int pcc;
-        unsigned int asn;
-        unsigned long unique;
-        unsigned long flags;
-        unsigned long res1, res2;
-};
-
-struct percpu_struct {
-        unsigned long hwpcb[16];
-        unsigned long flags;
-        unsigned long pal_mem_size;
-        unsigned long pal_scratch_size;
-        unsigned long pal_mem_pa;
-        unsigned long pal_scratch_pa;
-        unsigned long pal_revision;
-        unsigned long type;
-        unsigned long variation;
-        unsigned long revision;
-        unsigned long serial_no[2];
-        unsigned long logout_area_pa;
-        unsigned long logout_area_len;
-        unsigned long halt_PCBB;
-        unsigned long halt_PC;
-        unsigned long halt_PS;
-        unsigned long halt_arg;
-        unsigned long halt_ra;
-        unsigned long halt_pv;
-        unsigned long halt_reason;
-        unsigned long res;
-        unsigned long ipc_buffer[21];
-        unsigned long palcode_avail[16];
-        unsigned long compatibility;
-        unsigned long console_data_log_pa;
-        unsigned long console_data_log_length;
-        unsigned long bcache_info;
-};
-
-struct procdesc_struct {
-        unsigned long weird_vms_stuff;
-        unsigned long address;
-};
-
-struct vf_map_struct {
-        unsigned long va;
-        unsigned long pa;
-        unsigned long count;
-};
-
-struct crb_struct {
-        struct procdesc_struct * dispatch_va;
-        struct procdesc_struct * dispatch_pa;
-        struct procdesc_struct * fixup_va;
-        struct procdesc_struct * fixup_pa;
-        /* virtual->physical map */
-        unsigned long map_entries;
-        unsigned long map_pages;
-        struct vf_map_struct map[1];
-};
-
-struct memclust_struct {
-        unsigned long start_pfn;
-        unsigned long numpages;
-        unsigned long numtested;
-        unsigned long bitmap_va;
-        unsigned long bitmap_pa;
-        unsigned long bitmap_chksum;
-        unsigned long usage;
-};
-
-struct memdesc_struct {
-        unsigned long chksum;
-        unsigned long optional_pa;
-        unsigned long numclusters;
-        struct memclust_struct cluster[0];
-};
-
-struct dsr_struct {
-        long smm;                       /* SMM nubber used by LMF       */
-        unsigned long  lurt_off;        /* offset to LURT table         */
-        unsigned long  sysname_off;     /* offset to sysname char count */
-};
-
-struct hwrpb_struct {
-        unsigned long phys_addr;        /* check: physical address of the hwrpb */
-        unsigned long id;               /* check: "HWRPB\0\0\0" */
-        unsigned long revision; 
-        unsigned long size;             /* size of hwrpb */
-        unsigned long cpuid;
-        unsigned long pagesize;         /* 8192, I hope */
-        unsigned long pa_bits;          /* number of physical address bits */
-        unsigned long max_asn;
-        unsigned char ssn[16];          /* system serial number: big bother is watching */
-        unsigned long sys_type;
-        unsigned long sys_variation;
-        unsigned long sys_revision;
-        unsigned long intr_freq;        /* interval clock frequency * 4096 */
-        unsigned long cycle_freq;       /* cycle counter frequency */
-        unsigned long vptb;             /* Virtual Page Table Base address */
-        unsigned long res1;
-        unsigned long tbhb_offset;      /* Translation Buffer Hint Block */
-        unsigned long nr_processors;
-        unsigned long processor_size;
-        unsigned long processor_offset;
-        unsigned long ctb_nr;
-        unsigned long ctb_size;         /* console terminal block size */
-        unsigned long ctbt_offset;      /* console terminal block table offset */
-        unsigned long crb_offset;       /* console callback routine block */
-        unsigned long mddt_offset;      /* memory data descriptor table */
-        unsigned long cdb_offset;       /* configuration data block (or NULL) */
-        unsigned long frut_offset;      /* FRU table (or NULL) */
-        void (*save_terminal)(unsigned long);
-        unsigned long save_terminal_data;
-        void (*restore_terminal)(unsigned long);
-        unsigned long restore_terminal_data;
-        void (*CPU_restart)(unsigned long);
-        unsigned long CPU_restart_data;
-        unsigned long res2;
-        unsigned long res3;
-        unsigned long chksum;
-        unsigned long rxrdy;
-        unsigned long txrdy;
-        unsigned long dsr_offset;       /* "Dynamic System Recognition Data Block Table" */
-};
-
-#ifdef __KERNEL__
-
-extern struct hwrpb_struct *hwrpb;
-
-static inline void
-hwrpb_update_checksum(struct hwrpb_struct *h)
-{
-        unsigned long sum = 0, *l;
-        for (l = (unsigned long *) h; l < (unsigned long *) &h->chksum; ++l)
-                sum += *l;
-        h->chksum = sum;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_HWRPB_H */
diff --git a/include/asm-alpha/io.h b/include/asm-alpha/io.h
deleted file mode 100644
index e971ab000f95..000000000000
--- a/include/asm-alpha/io.h
+++ /dev/null
@@ -1,577 +0,0 @@
-#ifndef __ALPHA_IO_H
-#define __ALPHA_IO_H
-
-#ifdef __KERNEL__
-
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include <asm/compiler.h>
-#include <asm/system.h>
-#include <asm/pgtable.h>
-#include <asm/machvec.h>
-#include <asm/hwrpb.h>
-
-/* The generic header contains only prototypes.  Including it ensures that
-   the implementation we have here matches that interface.  */
-#include <asm-generic/iomap.h>
-
-/* We don't use IO slowdowns on the Alpha, but.. */
-#define __SLOW_DOWN_IO  do { } while (0)
-#define SLOW_DOWN_IO    do { } while (0)
-
-/*
- * Virtual -> physical identity mapping starts at this offset
- */
-#ifdef USE_48_BIT_KSEG
-#define IDENT_ADDR     0xffff800000000000UL
-#else
-#define IDENT_ADDR     0xfffffc0000000000UL
-#endif
-
-/*
- * We try to avoid hae updates (thus the cache), but when we
- * do need to update the hae, we need to do it atomically, so
- * that any interrupts wouldn't get confused with the hae
- * register not being up-to-date with respect to the hardware
- * value.
- */
-extern inline void __set_hae(unsigned long new_hae)
-{
-        unsigned long flags;
-        local_irq_save(flags);
-
-        alpha_mv.hae_cache = new_hae;
-        *alpha_mv.hae_register = new_hae;
-        mb();
-        /* Re-read to make sure it was written.  */
-        new_hae = *alpha_mv.hae_register;
-
-        local_irq_restore(flags);
-}
-
-extern inline void set_hae(unsigned long new_hae)
-{
-        if (new_hae != alpha_mv.hae_cache)
-                __set_hae(new_hae);
-}
-
-/*
- * Change virtual addresses to physical addresses and vv.
- */
-#ifdef USE_48_BIT_KSEG
-static inline unsigned long virt_to_phys(void *address)
-{
-        return (unsigned long)address - IDENT_ADDR;
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-        return (void *) (address + IDENT_ADDR);
-}
-#else
-static inline unsigned long virt_to_phys(void *address)
-{
-        unsigned long phys = (unsigned long)address;
-
-        /* Sign-extend from bit 41.  */
-        phys <<= (64 - 41);
-        phys = (long)phys >> (64 - 41);
-
-        /* Crop to the physical address width of the processor.  */
-        phys &= (1ul << hwrpb->pa_bits) - 1;
-
-        return phys;
-}
-
-static inline void * phys_to_virt(unsigned long address)
-{
-        return (void *)(IDENT_ADDR + (address & ((1ul << 41) - 1)));
-}
-#endif
-
-#define page_to_phys(page)      page_to_pa(page)
-
-static inline dma_addr_t __deprecated isa_page_to_bus(struct page *page)
-{
-        return page_to_phys(page);
-}
-
-/* This depends on working iommu.  */
-#define BIO_VMERGE_BOUNDARY     (alpha_mv.mv_pci_tbi ? PAGE_SIZE : 0)
-
-/* Maximum PIO space address supported?  */
-#define IO_SPACE_LIMIT 0xffff
-
-/*
- * Change addresses as seen by the kernel (virtual) to addresses as
- * seen by a device (bus), and vice versa.
- *
- * Note that this only works for a limited range of kernel addresses,
- * and very well may not span all memory.  Consider this interface 
- * deprecated in favour of the DMA-mapping API.
- */
-extern unsigned long __direct_map_base;
-extern unsigned long __direct_map_size;
-
-static inline unsigned long __deprecated virt_to_bus(void *address)
-{
-        unsigned long phys = virt_to_phys(address);
-        unsigned long bus = phys + __direct_map_base;
-        return phys <= __direct_map_size ? bus : 0;
-}
-#define isa_virt_to_bus virt_to_bus
-
-static inline void * __deprecated bus_to_virt(unsigned long address)
-{
-        void *virt;
-
-        /* This check is a sanity check but also ensures that bus address 0
-           maps to virtual address 0 which is useful to detect null pointers
-           (the NCR driver is much simpler if NULL pointers are preserved).  */
-        address -= __direct_map_base;
-        virt = phys_to_virt(address);
-        return (long)address <= 0 ? NULL : virt;
-}
-#define isa_bus_to_virt bus_to_virt
-
-/*
- * There are different chipsets to interface the Alpha CPUs to the world.
- */
-
-#define IO_CONCAT(a,b)  _IO_CONCAT(a,b)
-#define _IO_CONCAT(a,b) a ## _ ## b
-
-#ifdef CONFIG_ALPHA_GENERIC
-
-/* In a generic kernel, we always go through the machine vector.  */
-
-#define REMAP1(TYPE, NAME, QUAL)                                        \
-static inline TYPE generic_##NAME(QUAL void __iomem *addr)              \
-{                                                                       \
-        return alpha_mv.mv_##NAME(addr);                                \
-}
-
-#define REMAP2(TYPE, NAME, QUAL)                                        \
-static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr)      \
-{                                                                       \
-        alpha_mv.mv_##NAME(b, addr);                                    \
-}
-
-REMAP1(unsigned int, ioread8, /**/)
-REMAP1(unsigned int, ioread16, /**/)
-REMAP1(unsigned int, ioread32, /**/)
-REMAP1(u8, readb, const volatile)
-REMAP1(u16, readw, const volatile)
-REMAP1(u32, readl, const volatile)
-REMAP1(u64, readq, const volatile)
-
-REMAP2(u8, iowrite8, /**/)
-REMAP2(u16, iowrite16, /**/)
-REMAP2(u32, iowrite32, /**/)
-REMAP2(u8, writeb, volatile)
-REMAP2(u16, writew, volatile)
-REMAP2(u32, writel, volatile)
-REMAP2(u64, writeq, volatile)
-
-#undef REMAP1
-#undef REMAP2
-
-extern inline void __iomem *generic_ioportmap(unsigned long a)
-{
-        return alpha_mv.mv_ioportmap(a);
-}
-
-static inline void __iomem *generic_ioremap(unsigned long a, unsigned long s)
-{
-        return alpha_mv.mv_ioremap(a, s);
-}
-
-static inline void generic_iounmap(volatile void __iomem *a)
-{
-        return alpha_mv.mv_iounmap(a);
-}
-
-static inline int generic_is_ioaddr(unsigned long a)
-{
-        return alpha_mv.mv_is_ioaddr(a);
-}
-
-static inline int generic_is_mmio(const volatile void __iomem *a)
-{
-        return alpha_mv.mv_is_mmio(a);
-}
-
-#define __IO_PREFIX             generic
-#define generic_trivial_rw_bw   0
-#define generic_trivial_rw_lq   0
-#define generic_trivial_io_bw   0
-#define generic_trivial_io_lq   0
-#define generic_trivial_iounmap 0
-
-#else
-
-#if defined(CONFIG_ALPHA_APECS)
-# include <asm/core_apecs.h>
-#elif defined(CONFIG_ALPHA_CIA)
-# include <asm/core_cia.h>
-#elif defined(CONFIG_ALPHA_IRONGATE)
-# include <asm/core_irongate.h>
-#elif defined(CONFIG_ALPHA_JENSEN)
-# include <asm/jensen.h>
-#elif defined(CONFIG_ALPHA_LCA)
-# include <asm/core_lca.h>
-#elif defined(CONFIG_ALPHA_MARVEL)
-# include <asm/core_marvel.h>
-#elif defined(CONFIG_ALPHA_MCPCIA)
-# include <asm/core_mcpcia.h>
-#elif defined(CONFIG_ALPHA_POLARIS)
-# include <asm/core_polaris.h>
-#elif defined(CONFIG_ALPHA_T2)
-# include <asm/core_t2.h>
-#elif defined(CONFIG_ALPHA_TSUNAMI)
-# include <asm/core_tsunami.h>
-#elif defined(CONFIG_ALPHA_TITAN)
-# include <asm/core_titan.h>
-#elif defined(CONFIG_ALPHA_WILDFIRE)
-# include <asm/core_wildfire.h>
-#else
-#error "What system is this?"
-#endif
-
-#endif /* GENERIC */
-
-/*
- * We always have external versions of these routines.
- */
-extern u8               inb(unsigned long port);
-extern u16              inw(unsigned long port);
-extern u32              inl(unsigned long port);
-extern void             outb(u8 b, unsigned long port);
-extern void             outw(u16 b, unsigned long port);
-extern void             outl(u32 b, unsigned long port);
-
-extern u8               readb(const volatile void __iomem *addr);
-extern u16              readw(const volatile void __iomem *addr);
-extern u32              readl(const volatile void __iomem *addr);
-extern u64              readq(const volatile void __iomem *addr);
-extern void             writeb(u8 b, volatile void __iomem *addr);
-extern void             writew(u16 b, volatile void __iomem *addr);
-extern void             writel(u32 b, volatile void __iomem *addr);
-extern void             writeq(u64 b, volatile void __iomem *addr);
-
-extern u8               __raw_readb(const volatile void __iomem *addr);
-extern u16              __raw_readw(const volatile void __iomem *addr);
-extern u32              __raw_readl(const volatile void __iomem *addr);
-extern u64              __raw_readq(const volatile void __iomem *addr);
-extern void             __raw_writeb(u8 b, volatile void __iomem *addr);
-extern void             __raw_writew(u16 b, volatile void __iomem *addr);
-extern void             __raw_writel(u32 b, volatile void __iomem *addr);
-extern void             __raw_writeq(u64 b, volatile void __iomem *addr);
-
-/*
- * Mapping from port numbers to __iomem space is pretty easy.
- */
-
-/* These two have to be extern inline because of the extern prototype from
-   <asm-generic/iomap.h>.  It is not legal to mix "extern" and "static" for
-   the same declaration.  */
-extern inline void __iomem *ioport_map(unsigned long port, unsigned int size)
-{
-        return IO_CONCAT(__IO_PREFIX,ioportmap) (port);
-}
-
-extern inline void ioport_unmap(void __iomem *addr)
-{
-}
-
-static inline void __iomem *ioremap(unsigned long port, unsigned long size)
-{
-        return IO_CONCAT(__IO_PREFIX,ioremap) (port, size);
-}
-
-static inline void __iomem *__ioremap(unsigned long port, unsigned long size,
-                                      unsigned long flags)
-{
-        return ioremap(port, size);
-}
-
-static inline void __iomem * ioremap_nocache(unsigned long offset,
-                                             unsigned long size)
-{
-        return ioremap(offset, size);
-} 
-
-static inline void iounmap(volatile void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,iounmap)(addr);
-}
-
-static inline int __is_ioaddr(unsigned long addr)
-{
-        return IO_CONCAT(__IO_PREFIX,is_ioaddr)(addr);
-}
-#define __is_ioaddr(a)          __is_ioaddr((unsigned long)(a))
-
-static inline int __is_mmio(const volatile void __iomem *addr)
-{
-        return IO_CONCAT(__IO_PREFIX,is_mmio)(addr);
-}
-
-
-/*
- * If the actual I/O bits are sufficiently trivial, then expand inline.
- */
-
-#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
-extern inline unsigned int ioread8(void __iomem *addr)
-{
-        unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread8)(addr);
-        mb();
-        return ret;
-}
-
-extern inline unsigned int ioread16(void __iomem *addr)
-{
-        unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread16)(addr);
-        mb();
-        return ret;
-}
-
-extern inline void iowrite8(u8 b, void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr);
-        mb();
-}
-
-extern inline void iowrite16(u16 b, void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr);
-        mb();
-}
-
-extern inline u8 inb(unsigned long port)
-{
-        return ioread8(ioport_map(port, 1));
-}
-
-extern inline u16 inw(unsigned long port)
-{
-        return ioread16(ioport_map(port, 2));
-}
-
-extern inline void outb(u8 b, unsigned long port)
-{
-        iowrite8(b, ioport_map(port, 1));
-}
-
-extern inline void outw(u16 b, unsigned long port)
-{
-        iowrite16(b, ioport_map(port, 2));
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
-extern inline unsigned int ioread32(void __iomem *addr)
-{
-        unsigned int ret = IO_CONCAT(__IO_PREFIX,ioread32)(addr);
-        mb();
-        return ret;
-}
-
-extern inline void iowrite32(u32 b, void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
-        mb();
-}
-
-extern inline u32 inl(unsigned long port)
-{
-        return ioread32(ioport_map(port, 4));
-}
-
-extern inline void outl(u32 b, unsigned long port)
-{
-        iowrite32(b, ioport_map(port, 4));
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
-extern inline u8 __raw_readb(const volatile void __iomem *addr)
-{
-        return IO_CONCAT(__IO_PREFIX,readb)(addr);
-}
-
-extern inline u16 __raw_readw(const volatile void __iomem *addr)
-{
-        return IO_CONCAT(__IO_PREFIX,readw)(addr);
-}
-
-extern inline void __raw_writeb(u8 b, volatile void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,writeb)(b, addr);
-}
-
-extern inline void __raw_writew(u16 b, volatile void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,writew)(b, addr);
-}
-
-extern inline u8 readb(const volatile void __iomem *addr)
-{
-        u8 ret = __raw_readb(addr);
-        mb();
-        return ret;
-}
-
-extern inline u16 readw(const volatile void __iomem *addr)
-{
-        u16 ret = __raw_readw(addr);
-        mb();
-        return ret;
-}
-
-extern inline void writeb(u8 b, volatile void __iomem *addr)
-{
-        __raw_writeb(b, addr);
-        mb();
-}
-
-extern inline void writew(u16 b, volatile void __iomem *addr)
-{
-        __raw_writew(b, addr);
-        mb();
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1
-extern inline u32 __raw_readl(const volatile void __iomem *addr)
-{
-        return IO_CONCAT(__IO_PREFIX,readl)(addr);
-}
-
-extern inline u64 __raw_readq(const volatile void __iomem *addr)
-{
-        return IO_CONCAT(__IO_PREFIX,readq)(addr);
-}
-
-extern inline void __raw_writel(u32 b, volatile void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,writel)(b, addr);
-}
-
-extern inline void __raw_writeq(u64 b, volatile void __iomem *addr)
-{
-        IO_CONCAT(__IO_PREFIX,writeq)(b, addr);
-}
-
-extern inline u32 readl(const volatile void __iomem *addr)
-{
-        u32 ret = __raw_readl(addr);
-        mb();
-        return ret;
-}
-
-extern inline u64 readq(const volatile void __iomem *addr)
-{
-        u64 ret = __raw_readq(addr);
-        mb();
-        return ret;
-}
-
-extern inline void writel(u32 b, volatile void __iomem *addr)
-{
-        __raw_writel(b, addr);
-        mb();
-}
-
-extern inline void writeq(u64 b, volatile void __iomem *addr)
-{
-        __raw_writeq(b, addr);
-        mb();
-}
-#endif
-
-#define inb_p           inb
-#define inw_p           inw
-#define inl_p           inl
-#define outb_p          outb
-#define outw_p          outw
-#define outl_p          outl
-#define readb_relaxed(addr) __raw_readb(addr)
-#define readw_relaxed(addr) __raw_readw(addr)
-#define readl_relaxed(addr) __raw_readl(addr)
-#define readq_relaxed(addr) __raw_readq(addr)
-
-#define mmiowb()
-
-/*
- * String version of IO memory access ops:
- */
-extern void memcpy_fromio(void *, const volatile void __iomem *, long);
-extern void memcpy_toio(volatile void __iomem *, const void *, long);
-extern void _memset_c_io(volatile void __iomem *, unsigned long, long);
-
-static inline void memset_io(volatile void __iomem *addr, u8 c, long len)
-{
-        _memset_c_io(addr, 0x0101010101010101UL * c, len);
-}
-
-#define __HAVE_ARCH_MEMSETW_IO
-static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len)
-{
-        _memset_c_io(addr, 0x0001000100010001UL * c, len);
-}
-
-/*
- * String versions of in/out ops:
- */
-extern void insb (unsigned long port, void *dst, unsigned long count);
-extern void insw (unsigned long port, void *dst, unsigned long count);
-extern void insl (unsigned long port, void *dst, unsigned long count);
-extern void outsb (unsigned long port, const void *src, unsigned long count);
-extern void outsw (unsigned long port, const void *src, unsigned long count);
-extern void outsl (unsigned long port, const void *src, unsigned long count);
-
-/*
- * The Alpha Jensen hardware for some rather strange reason puts
- * the RTC clock at 0x170 instead of 0x70. Probably due to some
- * misguided idea about using 0x70 for NMI stuff.
- *
- * These defines will override the defaults when doing RTC queries
- */
-
-#ifdef CONFIG_ALPHA_GENERIC
-# define RTC_PORT(x)    ((x) + alpha_mv.rtc_port)
-#else
-# ifdef CONFIG_ALPHA_JENSEN
-#  define RTC_PORT(x)   (0x170+(x))
-# else
-#  define RTC_PORT(x)   (0x70 + (x))
-# endif
-#endif
-#define RTC_ALWAYS_BCD  0
-
-/*
- * Some mucking forons use if[n]def writeq to check if platform has it.
- * It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them
- * to play with; for now just use cpp anti-recursion logics and make sure
- * that damn thing is defined and expands to itself.
- */
-
-#define writeq writeq
-#define readq readq
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_IO_H */
diff --git a/include/asm-alpha/io_trivial.h b/include/asm-alpha/io_trivial.h
deleted file mode 100644
index 1c77f10b4b36..000000000000
--- a/include/asm-alpha/io_trivial.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/* Trivial implementations of basic i/o routines.  Assumes that all
-   of the hard work has been done by ioremap and ioportmap, and that
-   access to i/o space is linear.  */
-
-/* This file may be included multiple times.  */
-
-#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
-__EXTERN_INLINE unsigned int
-IO_CONCAT(__IO_PREFIX,ioread8)(void __iomem *a)
-{
-        return __kernel_ldbu(*(volatile u8 __force *)a);
-}
-
-__EXTERN_INLINE unsigned int
-IO_CONCAT(__IO_PREFIX,ioread16)(void __iomem *a)
-{
-        return __kernel_ldwu(*(volatile u16 __force *)a);
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,iowrite8)(u8 b, void __iomem *a)
-{
-        __kernel_stb(b, *(volatile u8 __force *)a);
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,iowrite16)(u16 b, void __iomem *a)
-{
-        __kernel_stw(b, *(volatile u16 __force *)a);
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
-__EXTERN_INLINE unsigned int
-IO_CONCAT(__IO_PREFIX,ioread32)(void __iomem *a)
-{
-        return *(volatile u32 __force *)a;
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,iowrite32)(u32 b, void __iomem *a)
-{
-        *(volatile u32 __force *)a = b;
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
-__EXTERN_INLINE u8
-IO_CONCAT(__IO_PREFIX,readb)(const volatile void __iomem *a)
-{
-        return __kernel_ldbu(*(const volatile u8 __force *)a);
-}
-
-__EXTERN_INLINE u16
-IO_CONCAT(__IO_PREFIX,readw)(const volatile void __iomem *a)
-{
-        return __kernel_ldwu(*(const volatile u16 __force *)a);
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,writeb)(u8 b, volatile void __iomem *a)
-{
-        __kernel_stb(b, *(volatile u8 __force *)a);
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a)
-{
-        __kernel_stw(b, *(volatile u16 __force *)a);
-}
-#elif IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 2
-__EXTERN_INLINE u8
-IO_CONCAT(__IO_PREFIX,readb)(const volatile void __iomem *a)
-{
-        void __iomem *addr = (void __iomem *)a;
-        return IO_CONCAT(__IO_PREFIX,ioread8)(addr);
-}
-
-__EXTERN_INLINE u16
-IO_CONCAT(__IO_PREFIX,readw)(const volatile void __iomem *a)
-{
-        void __iomem *addr = (void __iomem *)a;
-        return IO_CONCAT(__IO_PREFIX,ioread16)(addr);
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,writeb)(u8 b, volatile void __iomem *a)
-{
-        void __iomem *addr = (void __iomem *)a;
-        IO_CONCAT(__IO_PREFIX,iowrite8)(b, addr);
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,writew)(u16 b, volatile void __iomem *a)
-{
-        void __iomem *addr = (void __iomem *)a;
-        IO_CONCAT(__IO_PREFIX,iowrite16)(b, addr);
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_rw_lq) == 1
-__EXTERN_INLINE u32
-IO_CONCAT(__IO_PREFIX,readl)(const volatile void __iomem *a)
-{
-        return *(const volatile u32 __force *)a;
-}
-
-__EXTERN_INLINE u64
-IO_CONCAT(__IO_PREFIX,readq)(const volatile void __iomem *a)
-{
-        return *(const volatile u64 __force *)a;
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,writel)(u32 b, volatile void __iomem *a)
-{
-        *(volatile u32 __force *)a = b;
-}
-
-__EXTERN_INLINE void
-IO_CONCAT(__IO_PREFIX,writeq)(u64 b, volatile void __iomem *a)
-{
-        *(volatile u64 __force *)a = b;
-}
-#endif
-
-#if IO_CONCAT(__IO_PREFIX,trivial_iounmap)
-__EXTERN_INLINE void IO_CONCAT(__IO_PREFIX,iounmap)(volatile void __iomem *a)
-{
-}
-#endif
diff --git a/include/asm-alpha/ioctl.h b/include/asm-alpha/ioctl.h
deleted file mode 100644
index fc63727f4178..000000000000
--- a/include/asm-alpha/ioctl.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef _ALPHA_IOCTL_H
-#define _ALPHA_IOCTL_H
-
-/*
- * The original linux ioctl numbering scheme was just a general
- * "anything goes" setup, where more or less random numbers were
- * assigned.  Sorry, I was clueless when I started out on this.
- *
- * On the alpha, we'll try to clean it up a bit, using a more sane
- * ioctl numbering, and also trying to be compatible with OSF/1 in
- * the process. I'd like to clean it up for the i386 as well, but
- * it's so painful recognizing both the new and the old numbers..
- */
-
-#define _IOC_NRBITS     8
-#define _IOC_TYPEBITS   8
-#define _IOC_SIZEBITS   13
-#define _IOC_DIRBITS    3
-
-#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
-
-#define _IOC_NRSHIFT    0
-#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
-#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
-#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
-
-/*
- * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
- * And this turns out useful to catch old ioctl numbers in header
- * files for us.
- */
-#define _IOC_NONE       1U
-#define _IOC_READ       2U
-#define _IOC_WRITE      4U
-
-#define _IOC(dir,type,nr,size)                  \
-        ((unsigned int)                         \
-         (((dir)  << _IOC_DIRSHIFT) |           \
-          ((type) << _IOC_TYPESHIFT) |          \
-          ((nr)   << _IOC_NRSHIFT) |            \
-          ((size) << _IOC_SIZESHIFT)))
-
-/* used to create numbers */
-#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
-#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),sizeof(size))
-#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
-#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
-
-/* used to decode them.. */
-#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
-#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
-
-/* ...and for the drivers/sound files... */
-
-#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
-
-#endif /* _ALPHA_IOCTL_H */
diff --git a/include/asm-alpha/ioctls.h b/include/asm-alpha/ioctls.h
deleted file mode 100644
index 67bb9f6fdbe4..000000000000
--- a/include/asm-alpha/ioctls.h
+++ /dev/null
@@ -1,112 +0,0 @@
-#ifndef _ASM_ALPHA_IOCTLS_H
-#define _ASM_ALPHA_IOCTLS_H
-
-#include <asm/ioctl.h>
-
-#define FIOCLEX         _IO('f', 1)
-#define FIONCLEX        _IO('f', 2)
-#define FIOASYNC        _IOW('f', 125, int)
-#define FIONBIO         _IOW('f', 126, int)
-#define FIONREAD        _IOR('f', 127, int)
-#define TIOCINQ         FIONREAD
-#define FIOQSIZE        _IOR('f', 128, loff_t)
-
-#define TIOCGETP        _IOR('t', 8, struct sgttyb)
-#define TIOCSETP        _IOW('t', 9, struct sgttyb)
-#define TIOCSETN        _IOW('t', 10, struct sgttyb)    /* TIOCSETP wo flush */
-
-#define TIOCSETC        _IOW('t', 17, struct tchars)
-#define TIOCGETC        _IOR('t', 18, struct tchars)
-#define TCGETS          _IOR('t', 19, struct termios)
-#define TCSETS          _IOW('t', 20, struct termios)
-#define TCSETSW         _IOW('t', 21, struct termios)
-#define TCSETSF         _IOW('t', 22, struct termios)
-
-#define TCGETA          _IOR('t', 23, struct termio)
-#define TCSETA          _IOW('t', 24, struct termio)
-#define TCSETAW         _IOW('t', 25, struct termio)
-#define TCSETAF         _IOW('t', 28, struct termio)
-
-#define TCSBRK          _IO('t', 29)
-#define TCXONC          _IO('t', 30)
-#define TCFLSH          _IO('t', 31)
-
-#define TIOCSWINSZ      _IOW('t', 103, struct winsize)
-#define TIOCGWINSZ      _IOR('t', 104, struct winsize)
-#define TIOCSTART       _IO('t', 110)           /* start output, like ^Q */
-#define TIOCSTOP        _IO('t', 111)           /* stop output, like ^S */
-#define TIOCOUTQ        _IOR('t', 115, int)     /* output queue size */
-
-#define TIOCGLTC        _IOR('t', 116, struct ltchars)
-#define TIOCSLTC        _IOW('t', 117, struct ltchars)
-#define TIOCSPGRP       _IOW('t', 118, int)
-#define TIOCGPGRP       _IOR('t', 119, int)
-
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-
-#define TIOCSTI         0x5412
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-# define TIOCM_LE       0x001
-# define TIOCM_DTR      0x002
-# define TIOCM_RTS      0x004
-# define TIOCM_ST       0x008
-# define TIOCM_SR       0x010
-# define TIOCM_CTS      0x020
-# define TIOCM_CAR      0x040
-# define TIOCM_RNG      0x080
-# define TIOCM_DSR      0x100
-# define TIOCM_CD       TIOCM_CAR
-# define TIOCM_RI       TIOCM_RNG
-# define TIOCM_OUT1     0x2000
-# define TIOCM_OUT2     0x4000
-# define TIOCM_LOOP     0x8000
-
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-# define TIOCPKT_DATA            0
-# define TIOCPKT_FLUSHREAD       1
-# define TIOCPKT_FLUSHWRITE      2
-# define TIOCPKT_STOP            4
-# define TIOCPKT_START           8
-# define TIOCPKT_NOSTOP         16
-# define TIOCPKT_DOSTOP         32
-
-
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
-
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-  /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-# define TIOCSER_TEMT    0x01   /* Transmitter physically empty */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x545E  /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x545F  /* Set Hayes ESP configuration */
-
-#endif /* _ASM_ALPHA_IOCTLS_H */
diff --git a/include/asm-alpha/ipcbuf.h b/include/asm-alpha/ipcbuf.h
deleted file mode 100644
index d9c0e1a50702..000000000000
--- a/include/asm-alpha/ipcbuf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _ALPHA_IPCBUF_H
-#define _ALPHA_IPCBUF_H
-
-/* 
- * The ipc64_perm structure for alpha architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit seq
- * - 2 miscellaneous 64-bit values
- */
-
-struct ipc64_perm
-{
-        __kernel_key_t  key;
-        __kernel_uid_t  uid;
-        __kernel_gid_t  gid;
-        __kernel_uid_t  cuid;
-        __kernel_gid_t  cgid;
-        __kernel_mode_t mode; 
-        unsigned short  seq;
-        unsigned short  __pad1;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-};
-
-#endif /* _ALPHA_IPCBUF_H */
diff --git a/include/asm-alpha/irq.h b/include/asm-alpha/irq.h
deleted file mode 100644
index 06377400dc09..000000000000
--- a/include/asm-alpha/irq.h
+++ /dev/null
@@ -1,91 +0,0 @@
-#ifndef _ALPHA_IRQ_H
-#define _ALPHA_IRQ_H
-
-/*
- *      linux/include/alpha/irq.h
- *
- *      (C) 1994 Linus Torvalds
- */
-
-#include <linux/linkage.h>
-
-#if   defined(CONFIG_ALPHA_GENERIC)
-
-/* Here NR_IRQS is not exact, but rather an upper bound.  This is used
-   many places throughout the kernel to size static arrays.  That's ok,
-   we'll use alpha_mv.nr_irqs when we want the real thing.  */
-
-/* When LEGACY_START_ADDRESS is selected, we leave out:
-     TITAN
-     WILDFIRE
-     MARVEL
-
-   This helps keep the kernel object size reasonable for the majority
-   of machines.
-*/
-
-# if defined(CONFIG_ALPHA_LEGACY_START_ADDRESS)
-#  define NR_IRQS      (128)           /* max is RAWHIDE/TAKARA */
-# else
-#  define NR_IRQS      (32768 + 16)    /* marvel - 32 pids */
-# endif
-
-#elif defined(CONFIG_ALPHA_CABRIOLET) || \
-      defined(CONFIG_ALPHA_EB66P)     || \
-      defined(CONFIG_ALPHA_EB164)     || \
-      defined(CONFIG_ALPHA_PC164)     || \
-      defined(CONFIG_ALPHA_LX164)
-# define NR_IRQS        35
-
-#elif defined(CONFIG_ALPHA_EB66)      || \
-      defined(CONFIG_ALPHA_EB64P)     || \
-      defined(CONFIG_ALPHA_MIKASA)
-# define NR_IRQS        32
-
-#elif defined(CONFIG_ALPHA_ALCOR)     || \
-      defined(CONFIG_ALPHA_MIATA)     || \
-      defined(CONFIG_ALPHA_RUFFIAN)   || \
-      defined(CONFIG_ALPHA_RX164)     || \
-      defined(CONFIG_ALPHA_NORITAKE)
-# define NR_IRQS        48
-
-#elif defined(CONFIG_ALPHA_SABLE)     || \
-      defined(CONFIG_ALPHA_SX164)
-# define NR_IRQS        40
-
-#elif defined(CONFIG_ALPHA_DP264) || \
-      defined(CONFIG_ALPHA_LYNX)  || \
-      defined(CONFIG_ALPHA_SHARK) || \
-      defined(CONFIG_ALPHA_EIGER)
-# define NR_IRQS        64
-
-#elif defined(CONFIG_ALPHA_TITAN)
-#define NR_IRQS         80
-
-#elif defined(CONFIG_ALPHA_RAWHIDE) || \
-        defined(CONFIG_ALPHA_TAKARA)
-# define NR_IRQS        128
-
-#elif defined(CONFIG_ALPHA_WILDFIRE)
-# define NR_IRQS        2048 /* enuff for 8 QBBs */
-
-#elif defined(CONFIG_ALPHA_MARVEL)
-# define NR_IRQS        (32768 + 16)    /* marvel - 32 pids*/
-
-#else /* everyone else */
-# define NR_IRQS        16
-#endif
-
-static __inline__ int irq_canonicalize(int irq)
-{
-        /*
-         * XXX is this true for all Alpha's?  The old serial driver
-         * did it this way for years without any complaints, so....
-         */
-        return ((irq == 2) ? 9 : irq);
-}
-
-struct pt_regs;
-extern void (*perf_irq)(unsigned long, struct pt_regs *);
-
-#endif /* _ALPHA_IRQ_H */
diff --git a/include/asm-alpha/irq_regs.h b/include/asm-alpha/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-alpha/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-alpha/jensen.h b/include/asm-alpha/jensen.h
deleted file mode 100644
index 964b06ead43b..000000000000
--- a/include/asm-alpha/jensen.h
+++ /dev/null
@@ -1,346 +0,0 @@
-#ifndef __ALPHA_JENSEN_H
-#define __ALPHA_JENSEN_H
-
-#include <asm/compiler.h>
-
-/*
- * Defines for the AlphaPC EISA IO and memory address space.
- */
-
-/*
- * NOTE! The memory operations do not set any memory barriers, as it's
- * not needed for cases like a frame buffer that is essentially memory-like.
- * You need to do them by hand if the operations depend on ordering.
- *
- * Similarly, the port IO operations do a "mb" only after a write operation:
- * if an mb is needed before (as in the case of doing memory mapped IO
- * first, and then a port IO operation to the same device), it needs to be
- * done by hand.
- *
- * After the above has bitten me 100 times, I'll give up and just do the
- * mb all the time, but right now I'm hoping this will work out.  Avoiding
- * mb's may potentially be a noticeable speed improvement, but I can't
- * honestly say I've tested it.
- *
- * Handling interrupts that need to do mb's to synchronize to non-interrupts
- * is another fun race area.  Don't do it (because if you do, I'll have to
- * do *everything* with interrupts disabled, ugh).
- */
-
-/*
- * EISA Interrupt Acknowledge address
- */
-#define EISA_INTA               (IDENT_ADDR + 0x100000000UL)
-
-/*
- * FEPROM addresses
- */
-#define EISA_FEPROM0            (IDENT_ADDR + 0x180000000UL)
-#define EISA_FEPROM1            (IDENT_ADDR + 0x1A0000000UL)
-
-/*
- * VL82C106 base address
- */
-#define EISA_VL82C106           (IDENT_ADDR + 0x1C0000000UL)
-
-/*
- * EISA "Host Address Extension" address (bits 25-31 of the EISA address)
- */
-#define EISA_HAE                (IDENT_ADDR + 0x1D0000000UL)
-
-/*
- * "SYSCTL" register address
- */
-#define EISA_SYSCTL             (IDENT_ADDR + 0x1E0000000UL)
-
-/*
- * "spare" register address
- */
-#define EISA_SPARE              (IDENT_ADDR + 0x1F0000000UL)
-
-/*
- * EISA memory address offset
- */
-#define EISA_MEM                (IDENT_ADDR + 0x200000000UL)
-
-/*
- * EISA IO address offset
- */
-#define EISA_IO                 (IDENT_ADDR + 0x300000000UL)
-
-
-#ifdef __KERNEL__
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __IO_EXTERN_INLINE
-#endif
-
-/*
- * Handle the "host address register". This needs to be set
- * to the high 7 bits of the EISA address.  This is also needed
- * for EISA IO addresses, which are only 16 bits wide (the
- * hae needs to be set to 0).
- *
- * HAE isn't needed for the local IO operations, though.
- */
-
-#define JENSEN_HAE_ADDRESS      EISA_HAE
-#define JENSEN_HAE_MASK         0x1ffffff
-
-__EXTERN_INLINE void jensen_set_hae(unsigned long addr)
-{
-        /* hae on the Jensen is bits 31:25 shifted right */
-        addr >>= 25;
-        if (addr != alpha_mv.hae_cache)
-                set_hae(addr);
-}
-
-#define vuip    volatile unsigned int *
-
-/*
- * IO functions
- *
- * The "local" functions are those that don't go out to the EISA bus,
- * but instead act on the VL82C106 chip directly.. This is mainly the
- * keyboard, RTC,  printer and first two serial lines..
- *
- * The local stuff makes for some complications, but it seems to be
- * gone in the PCI version. I hope I can get DEC suckered^H^H^H^H^H^H^H^H
- * convinced that I need one of the newer machines.
- */
-
-static inline unsigned int jensen_local_inb(unsigned long addr)
-{
-        return 0xff & *(vuip)((addr << 9) + EISA_VL82C106);
-}
-
-static inline void jensen_local_outb(u8 b, unsigned long addr)
-{
-        *(vuip)((addr << 9) + EISA_VL82C106) = b;
-        mb();
-}
-
-static inline unsigned int jensen_bus_inb(unsigned long addr)
-{
-        long result;
-
-        jensen_set_hae(0);
-        result = *(volatile int *)((addr << 7) + EISA_IO + 0x00);
-        return __kernel_extbl(result, addr & 3);
-}
-
-static inline void jensen_bus_outb(u8 b, unsigned long addr)
-{
-        jensen_set_hae(0);
-        *(vuip)((addr << 7) + EISA_IO + 0x00) = b * 0x01010101;
-        mb();
-}
-
-/*
- * It seems gcc is not very good at optimizing away logical
- * operations that result in operations across inline functions.
- * Which is why this is a macro.
- */
-
-#define jensen_is_local(addr) ( \
-/* keyboard */  (addr == 0x60 || addr == 0x64) || \
-/* RTC */       (addr == 0x170 || addr == 0x171) || \
-/* mb COM2 */   (addr >= 0x2f8 && addr <= 0x2ff) || \
-/* mb LPT1 */   (addr >= 0x3bc && addr <= 0x3be) || \
-/* mb COM2 */   (addr >= 0x3f8 && addr <= 0x3ff))
-
-__EXTERN_INLINE u8 jensen_inb(unsigned long addr)
-{
-        if (jensen_is_local(addr))
-                return jensen_local_inb(addr);
-        else
-                return jensen_bus_inb(addr);
-}
-
-__EXTERN_INLINE void jensen_outb(u8 b, unsigned long addr)
-{
-        if (jensen_is_local(addr))
-                jensen_local_outb(b, addr);
-        else
-                jensen_bus_outb(b, addr);
-}
-
-__EXTERN_INLINE u16 jensen_inw(unsigned long addr)
-{
-        long result;
-
-        jensen_set_hae(0);
-        result = *(volatile int *) ((addr << 7) + EISA_IO + 0x20);
-        result >>= (addr & 3) * 8;
-        return 0xffffUL & result;
-}
-
-__EXTERN_INLINE u32 jensen_inl(unsigned long addr)
-{
-        jensen_set_hae(0);
-        return *(vuip) ((addr << 7) + EISA_IO + 0x60);
-}
-
-__EXTERN_INLINE void jensen_outw(u16 b, unsigned long addr)
-{
-        jensen_set_hae(0);
-        *(vuip) ((addr << 7) + EISA_IO + 0x20) = b * 0x00010001;
-        mb();
-}
-
-__EXTERN_INLINE void jensen_outl(u32 b, unsigned long addr)
-{
-        jensen_set_hae(0);
-        *(vuip) ((addr << 7) + EISA_IO + 0x60) = b;
-        mb();
-}
-
-/*
- * Memory functions.
- */
-
-__EXTERN_INLINE u8 jensen_readb(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        long result;
-
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        result = *(volatile int *) ((addr << 7) + EISA_MEM + 0x00);
-        result >>= (addr & 3) * 8;
-        return 0xffUL & result;
-}
-
-__EXTERN_INLINE u16 jensen_readw(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        long result;
-
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        result = *(volatile int *) ((addr << 7) + EISA_MEM + 0x20);
-        result >>= (addr & 3) * 8;
-        return 0xffffUL & result;
-}
-
-__EXTERN_INLINE u32 jensen_readl(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        return *(vuip) ((addr << 7) + EISA_MEM + 0x60);
-}
-
-__EXTERN_INLINE u64 jensen_readq(const volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        unsigned long r0, r1;
-
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        addr = (addr << 7) + EISA_MEM + 0x60;
-        r0 = *(vuip) (addr);
-        r1 = *(vuip) (addr + (4 << 7));
-        return r1 << 32 | r0;
-}
-
-__EXTERN_INLINE void jensen_writeb(u8 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        *(vuip) ((addr << 7) + EISA_MEM + 0x00) = b * 0x01010101;
-}
-
-__EXTERN_INLINE void jensen_writew(u16 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        *(vuip) ((addr << 7) + EISA_MEM + 0x20) = b * 0x00010001;
-}
-
-__EXTERN_INLINE void jensen_writel(u32 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        *(vuip) ((addr << 7) + EISA_MEM + 0x60) = b;
-}
-
-__EXTERN_INLINE void jensen_writeq(u64 b, volatile void __iomem *xaddr)
-{
-        unsigned long addr = (unsigned long) xaddr;
-        jensen_set_hae(addr);
-        addr &= JENSEN_HAE_MASK;
-        addr = (addr << 7) + EISA_MEM + 0x60;
-        *(vuip) (addr) = b;
-        *(vuip) (addr + (4 << 7)) = b >> 32;
-}
-
-__EXTERN_INLINE void __iomem *jensen_ioportmap(unsigned long addr)
-{
-        return (void __iomem *)addr;
-}
-
-__EXTERN_INLINE void __iomem *jensen_ioremap(unsigned long addr,
-                                             unsigned long size)
-{
-        return (void __iomem *)(addr + 0x100000000ul);
-}
-
-__EXTERN_INLINE int jensen_is_ioaddr(unsigned long addr)
-{
-        return (long)addr >= 0;
-}
-
-__EXTERN_INLINE int jensen_is_mmio(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >= 0x100000000ul;
-}
-
-/* New-style ioread interface.  All the routines are so ugly for Jensen
-   that it doesn't make sense to merge them.  */
-
-#define IOPORT(OS, NS)                                                  \
-__EXTERN_INLINE unsigned int jensen_ioread##NS(void __iomem *xaddr)     \
-{                                                                       \
-        if (jensen_is_mmio(xaddr))                                      \
-                return jensen_read##OS(xaddr - 0x100000000ul);          \
-        else                                                            \
-                return jensen_in##OS((unsigned long)xaddr);             \
-}                                                                       \
-__EXTERN_INLINE void jensen_iowrite##NS(u##NS b, void __iomem *xaddr)   \
-{                                                                       \
-        if (jensen_is_mmio(xaddr))                                      \
-                jensen_write##OS(b, xaddr - 0x100000000ul);             \
-        else                                                            \
-                jensen_out##OS(b, (unsigned long)xaddr);                \
-}
-
-IOPORT(b, 8)
-IOPORT(w, 16)
-IOPORT(l, 32)
-
-#undef IOPORT
-
-#undef vuip
-
-#undef __IO_PREFIX
-#define __IO_PREFIX             jensen
-#define jensen_trivial_rw_bw    0
-#define jensen_trivial_rw_lq    0
-#define jensen_trivial_io_bw    0
-#define jensen_trivial_io_lq    0
-#define jensen_trivial_iounmap  1
-#include <asm/io_trivial.h>
-
-#ifdef __IO_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __IO_EXTERN_INLINE
-#endif
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_JENSEN_H */
diff --git a/include/asm-alpha/kdebug.h b/include/asm-alpha/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-alpha/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-alpha/kmap_types.h b/include/asm-alpha/kmap_types.h
deleted file mode 100644
index 3e6735a34c57..000000000000
--- a/include/asm-alpha/kmap_types.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-/* Dummy header just to define km_type. */
-
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
-#else
-# define D(n)
-#endif
-
-enum km_type {
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-
-#undef D
-
-#endif
diff --git a/include/asm-alpha/linkage.h b/include/asm-alpha/linkage.h
deleted file mode 100644
index 291c2d01c44f..000000000000
--- a/include/asm-alpha/linkage.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-/* Nothing to see here... */
-
-#endif
diff --git a/include/asm-alpha/local.h b/include/asm-alpha/local.h
deleted file mode 100644
index 6ad3ea696421..000000000000
--- a/include/asm-alpha/local.h
+++ /dev/null
@@ -1,118 +0,0 @@
-#ifndef _ALPHA_LOCAL_H
-#define _ALPHA_LOCAL_H
-
-#include <linux/percpu.h>
-#include <asm/atomic.h>
-
-typedef struct
-{
-        atomic_long_t a;
-} local_t;
-
-#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
-#define local_read(l)   atomic_long_read(&(l)->a)
-#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
-#define local_inc(l)    atomic_long_inc(&(l)->a)
-#define local_dec(l)    atomic_long_dec(&(l)->a)
-#define local_add(i,l)  atomic_long_add((i),(&(l)->a))
-#define local_sub(i,l)  atomic_long_sub((i),(&(l)->a))
-
-static __inline__ long local_add_return(long i, local_t * l)
-{
-        long temp, result;
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%1\n"
-        "       addq %0,%3,%2\n"
-        "       addq %0,%3,%0\n"
-        "       stq_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (l->a.counter), "=&r" (result)
-        :"Ir" (i), "m" (l->a.counter) : "memory");
-        return result;
-}
-
-static __inline__ long local_sub_return(long i, local_t * l)
-{
-        long temp, result;
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%1\n"
-        "       subq %0,%3,%2\n"
-        "       subq %0,%3,%0\n"
-        "       stq_c %0,%1\n"
-        "       beq %0,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (l->a.counter), "=&r" (result)
-        :"Ir" (i), "m" (l->a.counter) : "memory");
-        return result;
-}
-
-#define local_cmpxchg(l, o, n) \
-        (cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
-
-/**
- * local_add_unless - add unless the number is a given value
- * @l: pointer of type local_t
- * @a: the amount to add to l...
- * @u: ...unless l is equal to u.
- *
- * Atomically adds @a to @l, so long as it was not @u.
- * Returns non-zero if @l was not @u, and zero otherwise.
- */
-#define local_add_unless(l, a, u)                               \
-({                                                              \
-        long c, old;                                            \
-        c = local_read(l);                                      \
-        for (;;) {                                              \
-                if (unlikely(c == (u)))                         \
-                        break;                                  \
-                old = local_cmpxchg((l), c, c + (a));   \
-                if (likely(old == c))                           \
-                        break;                                  \
-                c = old;                                        \
-        }                                                       \
-        c != (u);                                               \
-})
-#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
-
-#define local_add_negative(a, l) (local_add_return((a), (l)) < 0)
-
-#define local_dec_return(l) local_sub_return(1,(l))
-
-#define local_inc_return(l) local_add_return(1,(l))
-
-#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0)
-
-#define local_inc_and_test(l) (local_add_return(1, (l)) == 0)
-
-#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
-
-/* Verify if faster than atomic ops */
-#define __local_inc(l)          ((l)->a.counter++)
-#define __local_dec(l)          ((l)->a.counter++)
-#define __local_add(i,l)        ((l)->a.counter+=(i))
-#define __local_sub(i,l)        ((l)->a.counter-=(i))
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations.  Note they take
- * a variable, not an address.
- */
-#define cpu_local_read(l)       local_read(&__get_cpu_var(l))
-#define cpu_local_set(l, i)     local_set(&__get_cpu_var(l), (i))
-
-#define cpu_local_inc(l)        local_inc(&__get_cpu_var(l))
-#define cpu_local_dec(l)        local_dec(&__get_cpu_var(l))
-#define cpu_local_add(i, l)     local_add((i), &__get_cpu_var(l))
-#define cpu_local_sub(i, l)     local_sub((i), &__get_cpu_var(l))
-
-#define __cpu_local_inc(l)      __local_inc(&__get_cpu_var(l))
-#define __cpu_local_dec(l)      __local_dec(&__get_cpu_var(l))
-#define __cpu_local_add(i, l)   __local_add((i), &__get_cpu_var(l))
-#define __cpu_local_sub(i, l)   __local_sub((i), &__get_cpu_var(l))
-
-#endif /* _ALPHA_LOCAL_H */
diff --git a/include/asm-alpha/machvec.h b/include/asm-alpha/machvec.h
deleted file mode 100644
index a86c083cdf7f..000000000000
--- a/include/asm-alpha/machvec.h
+++ /dev/null
@@ -1,134 +0,0 @@
-#ifndef __ALPHA_MACHVEC_H
-#define __ALPHA_MACHVEC_H 1
-
-#include <linux/types.h>
-
-/*
- *      This file gets pulled in by asm/io.h from user space. We don't
- *      want most of this escaping.
- */
- 
-#ifdef __KERNEL__
-
-/* The following structure vectors all of the I/O and IRQ manipulation
-   from the generic kernel to the hardware specific backend.  */
-
-struct task_struct;
-struct mm_struct;
-struct vm_area_struct;
-struct linux_hose_info;
-struct pci_dev;
-struct pci_ops;
-struct pci_controller;
-struct _alpha_agp_info;
-
-struct alpha_machine_vector
-{
-        /* This "belongs" down below with the rest of the runtime
-           variables, but it is convenient for entry.S if these 
-           two slots are at the beginning of the struct.  */
-        unsigned long hae_cache;
-        unsigned long *hae_register;
-
-        int nr_irqs;
-        int rtc_port;
-        unsigned int max_asn;
-        unsigned long max_isa_dma_address;
-        unsigned long irq_probe_mask;
-        unsigned long iack_sc;
-        unsigned long min_io_address;
-        unsigned long min_mem_address;
-        unsigned long pci_dac_offset;
-
-        void (*mv_pci_tbi)(struct pci_controller *hose,
-                           dma_addr_t start, dma_addr_t end);
-
-        unsigned int (*mv_ioread8)(void __iomem *);
-        unsigned int (*mv_ioread16)(void __iomem *);
-        unsigned int (*mv_ioread32)(void __iomem *);
-
-        void (*mv_iowrite8)(u8, void __iomem *);
-        void (*mv_iowrite16)(u16, void __iomem *);
-        void (*mv_iowrite32)(u32, void __iomem *);
-
-        u8 (*mv_readb)(const volatile void __iomem *);
-        u16 (*mv_readw)(const volatile void __iomem *);
-        u32 (*mv_readl)(const volatile void __iomem *);
-        u64 (*mv_readq)(const volatile void __iomem *);
-
-        void (*mv_writeb)(u8, volatile void __iomem *);
-        void (*mv_writew)(u16, volatile void __iomem *);
-        void (*mv_writel)(u32, volatile void __iomem *);
-        void (*mv_writeq)(u64, volatile void __iomem *);
-
-        void __iomem *(*mv_ioportmap)(unsigned long);
-        void __iomem *(*mv_ioremap)(unsigned long, unsigned long);
-        void (*mv_iounmap)(volatile void __iomem *);
-        int (*mv_is_ioaddr)(unsigned long);
-        int (*mv_is_mmio)(const volatile void __iomem *);
-
-        void (*mv_switch_mm)(struct mm_struct *, struct mm_struct *,
-                             struct task_struct *);
-        void (*mv_activate_mm)(struct mm_struct *, struct mm_struct *);
-
-        void (*mv_flush_tlb_current)(struct mm_struct *);
-        void (*mv_flush_tlb_current_page)(struct mm_struct * mm,
-                                          struct vm_area_struct *vma,
-                                          unsigned long addr);
-
-        void (*update_irq_hw)(unsigned long, unsigned long, int);
-        void (*ack_irq)(unsigned long);
-        void (*device_interrupt)(unsigned long vector);
-        void (*machine_check)(u64 vector, u64 la);
-
-        void (*smp_callin)(void);
-        void (*init_arch)(void);
-        void (*init_irq)(void);
-        void (*init_rtc)(void);
-        void (*init_pci)(void);
-        void (*kill_arch)(int);
-
-        u8 (*pci_swizzle)(struct pci_dev *, u8 *);
-        int (*pci_map_irq)(struct pci_dev *, u8, u8);
-        struct pci_ops *pci_ops;
-
-        struct _alpha_agp_info *(*agp_info)(void);
-
-        const char *vector_name;
-
-        /* NUMA information */
-        int (*pa_to_nid)(unsigned long);
-        int (*cpuid_to_nid)(int);
-        unsigned long (*node_mem_start)(int);
-        unsigned long (*node_mem_size)(int);
-
-        /* System specific parameters.  */
-        union {
-            struct {
-                unsigned long gru_int_req_bits;
-            } cia;
-
-            struct {
-                unsigned long gamma_bias;
-            } t2;
-
-            struct {
-                unsigned int route_tab;
-            } sio;
-        } sys;
-};
-
-extern struct alpha_machine_vector alpha_mv;
-
-#ifdef CONFIG_ALPHA_GENERIC
-extern int alpha_using_srm;
-#else
-#ifdef CONFIG_ALPHA_SRM
-#define alpha_using_srm 1
-#else
-#define alpha_using_srm 0
-#endif
-#endif /* GENERIC */
-
-#endif
-#endif /* __ALPHA_MACHVEC_H */
diff --git a/include/asm-alpha/mc146818rtc.h b/include/asm-alpha/mc146818rtc.h
deleted file mode 100644
index 097703f1c8cb..000000000000
--- a/include/asm-alpha/mc146818rtc.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef __ASM_ALPHA_MC146818RTC_H
-#define __ASM_ALPHA_MC146818RTC_H
-
-#include <asm/io.h>
-
-#ifndef RTC_PORT
-#define RTC_PORT(x)     (0x70 + (x))
-#define RTC_ALWAYS_BCD  1       /* RTC operates in binary mode */
-#endif
-
-/*
- * The yet supported machines all access the RTC index register via
- * an ISA port access but the way to access the date register differs ...
- */
-#define CMOS_READ(addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-inb_p(RTC_PORT(1)); \
-})
-#define CMOS_WRITE(val, addr) ({ \
-outb_p((addr),RTC_PORT(0)); \
-outb_p((val),RTC_PORT(1)); \
-})
-
-#endif /* __ASM_ALPHA_MC146818RTC_H */
diff --git a/include/asm-alpha/md.h b/include/asm-alpha/md.h
deleted file mode 100644
index 6c9b8222a4f2..000000000000
--- a/include/asm-alpha/md.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* $Id: md.h,v 1.1 1997/12/15 15:11:48 jj Exp $
- * md.h: High speed xor_block operation for RAID4/5 
- *
- */
- 
-#ifndef __ASM_MD_H
-#define __ASM_MD_H
-
-/* #define HAVE_ARCH_XORBLOCK */
-
-#define MD_XORBLOCK_ALIGNMENT   sizeof(long)
-
-#endif /* __ASM_MD_H */
diff --git a/include/asm-alpha/mman.h b/include/asm-alpha/mman.h
deleted file mode 100644
index 90d7c35d2867..000000000000
--- a/include/asm-alpha/mman.h
+++ /dev/null
@@ -1,54 +0,0 @@
-#ifndef __ALPHA_MMAN_H__
-#define __ALPHA_MMAN_H__
-
-#define PROT_READ       0x1             /* page can be read */
-#define PROT_WRITE      0x2             /* page can be written */
-#define PROT_EXEC       0x4             /* page can be executed */
-#define PROT_SEM        0x8             /* page may be used for atomic ops */
-#define PROT_NONE       0x0             /* page can not be accessed */
-#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
-#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
-
-#define MAP_SHARED      0x01            /* Share changes */
-#define MAP_PRIVATE     0x02            /* Changes are private */
-#define MAP_TYPE        0x0f            /* Mask for type of mapping (OSF/1 is _wrong_) */
-#define MAP_FIXED       0x100           /* Interpret addr exactly */
-#define MAP_ANONYMOUS   0x10            /* don't use a file */
-
-/* not used by linux, but here to make sure we don't clash with OSF/1 defines */
-#define _MAP_HASSEMAPHORE 0x0200
-#define _MAP_INHERIT    0x0400
-#define _MAP_UNALIGNED  0x0800
-
-/* These are linux-specific */
-#define MAP_GROWSDOWN   0x01000         /* stack-like segment */
-#define MAP_DENYWRITE   0x02000         /* ETXTBSY */
-#define MAP_EXECUTABLE  0x04000         /* mark it as an executable */
-#define MAP_LOCKED      0x08000         /* lock the mapping */
-#define MAP_NORESERVE   0x10000         /* don't check for reservations */
-#define MAP_POPULATE    0x20000         /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x40000         /* do not block on IO */
-
-#define MS_ASYNC        1               /* sync memory asynchronously */
-#define MS_SYNC         2               /* synchronous memory sync */
-#define MS_INVALIDATE   4               /* invalidate the caches */
-
-#define MCL_CURRENT      8192           /* lock all currently mapped pages */
-#define MCL_FUTURE      16384           /* lock all additions to address space */
-
-#define MADV_NORMAL     0               /* no further special treatment */
-#define MADV_RANDOM     1               /* expect random page references */
-#define MADV_SEQUENTIAL 2               /* expect sequential page references */
-#define MADV_WILLNEED   3               /* will need these pages */
-#define MADV_SPACEAVAIL 5               /* ensure resources are available */
-#define MADV_DONTNEED   6               /* don't need these pages */
-
-/* common/generic parameters */
-#define MADV_REMOVE     9               /* remove these pages & resources */
-#define MADV_DONTFORK   10              /* don't inherit across fork */
-#define MADV_DOFORK     11              /* do inherit across fork */
-
-/* compatibility flags */
-#define MAP_FILE        0
-
-#endif /* __ALPHA_MMAN_H__ */
diff --git a/include/asm-alpha/mmu.h b/include/asm-alpha/mmu.h
deleted file mode 100644
index 3dc127779329..000000000000
--- a/include/asm-alpha/mmu.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ALPHA_MMU_H
-#define __ALPHA_MMU_H
-
-/* The alpha MMU context is one "unsigned long" bitmap per CPU */
-typedef unsigned long mm_context_t[NR_CPUS];
-
-#endif
diff --git a/include/asm-alpha/mmu_context.h b/include/asm-alpha/mmu_context.h
deleted file mode 100644
index 86c08a02d239..000000000000
--- a/include/asm-alpha/mmu_context.h
+++ /dev/null
@@ -1,260 +0,0 @@
-#ifndef __ALPHA_MMU_CONTEXT_H
-#define __ALPHA_MMU_CONTEXT_H
-
-/*
- * get a new mmu context..
- *
- * Copyright (C) 1996, Linus Torvalds
- */
-
-#include <asm/system.h>
-#include <asm/machvec.h>
-#include <asm/compiler.h>
-#include <asm-generic/mm_hooks.h>
-
-/*
- * Force a context reload. This is needed when we change the page
- * table pointer or when we update the ASN of the current process.
- */
-
-/* Don't get into trouble with dueling __EXTERN_INLINEs.  */
-#ifndef __EXTERN_INLINE
-#include <asm/io.h>
-#endif
-
-
-static inline unsigned long
-__reload_thread(struct pcb_struct *pcb)
-{
-        register unsigned long a0 __asm__("$16");
-        register unsigned long v0 __asm__("$0");
-
-        a0 = virt_to_phys(pcb);
-        __asm__ __volatile__(
-                "call_pal %2 #__reload_thread"
-                : "=r"(v0), "=r"(a0)
-                : "i"(PAL_swpctx), "r"(a0)
-                : "$1", "$22", "$23", "$24", "$25");
-
-        return v0;
-}
-
-
-/*
- * The maximum ASN's the processor supports.  On the EV4 this is 63
- * but the PAL-code doesn't actually use this information.  On the
- * EV5 this is 127, and EV6 has 255.
- *
- * On the EV4, the ASNs are more-or-less useless anyway, as they are
- * only used as an icache tag, not for TB entries.  On the EV5 and EV6,
- * ASN's also validate the TB entries, and thus make a lot more sense.
- *
- * The EV4 ASN's don't even match the architecture manual, ugh.  And
- * I quote: "If a processor implements address space numbers (ASNs),
- * and the old PTE has the Address Space Match (ASM) bit clear (ASNs
- * in use) and the Valid bit set, then entries can also effectively be
- * made coherent by assigning a new, unused ASN to the currently
- * running process and not reusing the previous ASN before calling the
- * appropriate PALcode routine to invalidate the translation buffer (TB)". 
- *
- * In short, the EV4 has a "kind of" ASN capability, but it doesn't actually
- * work correctly and can thus not be used (explaining the lack of PAL-code
- * support).
- */
-#define EV4_MAX_ASN 63
-#define EV5_MAX_ASN 127
-#define EV6_MAX_ASN 255
-
-#ifdef CONFIG_ALPHA_GENERIC
-# define MAX_ASN        (alpha_mv.max_asn)
-#else
-# ifdef CONFIG_ALPHA_EV4
-#  define MAX_ASN       EV4_MAX_ASN
-# elif defined(CONFIG_ALPHA_EV5)
-#  define MAX_ASN       EV5_MAX_ASN
-# else
-#  define MAX_ASN       EV6_MAX_ASN
-# endif
-#endif
-
-/*
- * cpu_last_asn(processor):
- * 63                                            0
- * +-------------+----------------+--------------+
- * | asn version | this processor | hardware asn |
- * +-------------+----------------+--------------+
- */
-
-#include <asm/smp.h>
-#ifdef CONFIG_SMP
-#define cpu_last_asn(cpuid)     (cpu_data[cpuid].last_asn)
-#else
-extern unsigned long last_asn;
-#define cpu_last_asn(cpuid)     last_asn
-#endif /* CONFIG_SMP */
-
-#define WIDTH_HARDWARE_ASN      8
-#define ASN_FIRST_VERSION (1UL << WIDTH_HARDWARE_ASN)
-#define HARDWARE_ASN_MASK ((1UL << WIDTH_HARDWARE_ASN) - 1)
-
-/*
- * NOTE! The way this is set up, the high bits of the "asn_cache" (and
- * the "mm->context") are the ASN _version_ code. A version of 0 is
- * always considered invalid, so to invalidate another process you only
- * need to do "p->mm->context = 0".
- *
- * If we need more ASN's than the processor has, we invalidate the old
- * user TLB's (tbiap()) and start a new ASN version. That will automatically
- * force a new asn for any other processes the next time they want to
- * run.
- */
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __MMU_EXTERN_INLINE
-#endif
-
-extern inline unsigned long
-__get_new_mm_context(struct mm_struct *mm, long cpu)
-{
-        unsigned long asn = cpu_last_asn(cpu);
-        unsigned long next = asn + 1;
-
-        if ((asn & HARDWARE_ASN_MASK) >= MAX_ASN) {
-                tbiap();
-                imb();
-                next = (asn & ~HARDWARE_ASN_MASK) + ASN_FIRST_VERSION;
-        }
-        cpu_last_asn(cpu) = next;
-        return next;
-}
-
-__EXTERN_INLINE void
-ev5_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-              struct task_struct *next)
-{
-        /* Check if our ASN is of an older version, and thus invalid. */
-        unsigned long asn;
-        unsigned long mmc;
-        long cpu = smp_processor_id();
-
-#ifdef CONFIG_SMP
-        cpu_data[cpu].asn_lock = 1;
-        barrier();
-#endif
-        asn = cpu_last_asn(cpu);
-        mmc = next_mm->context[cpu];
-        if ((mmc ^ asn) & ~HARDWARE_ASN_MASK) {
-                mmc = __get_new_mm_context(next_mm, cpu);
-                next_mm->context[cpu] = mmc;
-        }
-#ifdef CONFIG_SMP
-        else
-                cpu_data[cpu].need_new_asn = 1;
-#endif
-
-        /* Always update the PCB ASN.  Another thread may have allocated
-           a new mm->context (via flush_tlb_mm) without the ASN serial
-           number wrapping.  We have no way to detect when this is needed.  */
-        task_thread_info(next)->pcb.asn = mmc & HARDWARE_ASN_MASK;
-}
-
-__EXTERN_INLINE void
-ev4_switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-              struct task_struct *next)
-{
-        /* As described, ASN's are broken for TLB usage.  But we can
-           optimize for switching between threads -- if the mm is
-           unchanged from current we needn't flush.  */
-        /* ??? May not be needed because EV4 PALcode recognizes that
-           ASN's are broken and does a tbiap itself on swpctx, under
-           the "Must set ASN or flush" rule.  At least this is true
-           for a 1992 SRM, reports Joseph Martin (jmartin@hlo.dec.com).
-           I'm going to leave this here anyway, just to Be Sure.  -- r~  */
-        if (prev_mm != next_mm)
-                tbiap();
-
-        /* Do continue to allocate ASNs, because we can still use them
-           to avoid flushing the icache.  */
-        ev5_switch_mm(prev_mm, next_mm, next);
-}
-
-extern void __load_new_mm_context(struct mm_struct *);
-
-#ifdef CONFIG_SMP
-#define check_mmu_context()                                     \
-do {                                                            \
-        int cpu = smp_processor_id();                           \
-        cpu_data[cpu].asn_lock = 0;                             \
-        barrier();                                              \
-        if (cpu_data[cpu].need_new_asn) {                       \
-                struct mm_struct * mm = current->active_mm;     \
-                cpu_data[cpu].need_new_asn = 0;                 \
-                if (!mm->context[cpu])                  \
-                        __load_new_mm_context(mm);              \
-        }                                                       \
-} while(0)
-#else
-#define check_mmu_context()  do { } while(0)
-#endif
-
-__EXTERN_INLINE void
-ev5_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
-{
-        __load_new_mm_context(next_mm);
-}
-
-__EXTERN_INLINE void
-ev4_activate_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm)
-{
-        __load_new_mm_context(next_mm);
-        tbiap();
-}
-
-#define deactivate_mm(tsk,mm)   do { } while (0)
-
-#ifdef CONFIG_ALPHA_GENERIC
-# define switch_mm(a,b,c)       alpha_mv.mv_switch_mm((a),(b),(c))
-# define activate_mm(x,y)       alpha_mv.mv_activate_mm((x),(y))
-#else
-# ifdef CONFIG_ALPHA_EV4
-#  define switch_mm(a,b,c)      ev4_switch_mm((a),(b),(c))
-#  define activate_mm(x,y)      ev4_activate_mm((x),(y))
-# else
-#  define switch_mm(a,b,c)      ev5_switch_mm((a),(b),(c))
-#  define activate_mm(x,y)      ev5_activate_mm((x),(y))
-# endif
-#endif
-
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-        int i;
-
-        for_each_online_cpu(i)
-                mm->context[i] = 0;
-        if (tsk != current)
-                task_thread_info(tsk)->pcb.ptbr
-                  = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
-        return 0;
-}
-
-extern inline void
-destroy_context(struct mm_struct *mm)
-{
-        /* Nothing to do.  */
-}
-
-static inline void
-enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-        task_thread_info(tsk)->pcb.ptbr
-          = ((unsigned long)mm->pgd - IDENT_ADDR) >> PAGE_SHIFT;
-}
-
-#ifdef __MMU_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __MMU_EXTERN_INLINE
-#endif
-
-#endif /* __ALPHA_MMU_CONTEXT_H */
diff --git a/include/asm-alpha/mmzone.h b/include/asm-alpha/mmzone.h
deleted file mode 100644
index 8af56ce346ad..000000000000
--- a/include/asm-alpha/mmzone.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
- * Adapted for the alpha wildfire architecture Jan 2001.
- */
-#ifndef _ASM_MMZONE_H_
-#define _ASM_MMZONE_H_
-
-#include <asm/smp.h>
-
-struct bootmem_data_t; /* stupid forward decl. */
-
-/*
- * Following are macros that are specific to this numa platform.
- */
-
-extern pg_data_t node_data[];
-
-#define alpha_pa_to_nid(pa)             \
-        (alpha_mv.pa_to_nid             \
-         ? alpha_mv.pa_to_nid(pa)       \
-         : (0))
-#define node_mem_start(nid)             \
-        (alpha_mv.node_mem_start        \
-         ? alpha_mv.node_mem_start(nid) \
-         : (0UL))
-#define node_mem_size(nid)              \
-        (alpha_mv.node_mem_size         \
-         ? alpha_mv.node_mem_size(nid)  \
-         : ((nid) ? (0UL) : (~0UL)))
-
-#define pa_to_nid(pa)           alpha_pa_to_nid(pa)
-#define NODE_DATA(nid)          (&node_data[(nid)])
-
-#define node_localnr(pfn, nid)  ((pfn) - NODE_DATA(nid)->node_start_pfn)
-
-#if 1
-#define PLAT_NODE_DATA_LOCALNR(p, n)    \
-        (((p) >> PAGE_SHIFT) - PLAT_NODE_DATA(n)->gendata.node_start_pfn)
-#else
-static inline unsigned long
-PLAT_NODE_DATA_LOCALNR(unsigned long p, int n)
-{
-        unsigned long temp;
-        temp = p >> PAGE_SHIFT;
-        return temp - PLAT_NODE_DATA(n)->gendata.node_start_pfn;
-}
-#endif
-
-#ifdef CONFIG_DISCONTIGMEM
-
-/*
- * Following are macros that each numa implementation must define.
- */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define kvaddr_to_nid(kaddr)    pa_to_nid(__pa(kaddr))
-#define node_start_pfn(nid)     (NODE_DATA(nid)->node_start_pfn)
-
-/*
- * Given a kaddr, LOCAL_BASE_ADDR finds the owning node of the memory
- * and returns the kaddr corresponding to first physical page in the
- * node's mem_map.
- */
-#define LOCAL_BASE_ADDR(kaddr)                                            \
-    ((unsigned long)__va(NODE_DATA(kvaddr_to_nid(kaddr))->node_start_pfn  \
-                         << PAGE_SHIFT))
-
-/* XXX: FIXME -- wli */
-#define kern_addr_valid(kaddr)  (0)
-
-#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-
-#define VALID_PAGE(page)        (((page) - mem_map) < max_mapnr)
-
-#define pmd_page(pmd)           (pfn_to_page(pmd_val(pmd) >> 32))
-#define pgd_page(pgd)           (pfn_to_page(pgd_val(pgd) >> 32))
-#define pte_pfn(pte)            (pte_val(pte) >> 32)
-
-#define mk_pte(page, pgprot)                                                 \
-({                                                                           \
-        pte_t pte;                                                           \
-        unsigned long pfn;                                                   \
-                                                                             \
-        pfn = page_to_pfn(page) << 32; \
-        pte_val(pte) = pfn | pgprot_val(pgprot);                             \
-                                                                             \
-        pte;                                                                 \
-})
-
-#define pte_page(x)                                                     \
-({                                                                      \
-        unsigned long kvirt;                                            \
-        struct page * __xx;                                             \
-                                                                        \
-        kvirt = (unsigned long)__va(pte_val(x) >> (32-PAGE_SHIFT));     \
-        __xx = virt_to_page(kvirt);                                     \
-                                                                        \
-        __xx;                                                           \
-})
-
-#define page_to_pa(page)                                                \
-        (page_to_pfn(page) << PAGE_SHIFT)
-
-#define pfn_to_nid(pfn)         pa_to_nid(((u64)(pfn) << PAGE_SHIFT))
-#define pfn_valid(pfn)                                                  \
-        (((pfn) - node_start_pfn(pfn_to_nid(pfn))) <                    \
-         node_spanned_pages(pfn_to_nid(pfn)))                                   \
-
-#define virt_addr_valid(kaddr)  pfn_valid((__pa(kaddr) >> PAGE_SHIFT))
-
-#endif /* CONFIG_DISCONTIGMEM */
-
-#endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-alpha/module.h b/include/asm-alpha/module.h
deleted file mode 100644
index 7b63743c534a..000000000000
--- a/include/asm-alpha/module.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _ALPHA_MODULE_H
-#define _ALPHA_MODULE_H
-
-struct mod_arch_specific
-{
-        unsigned int gotsecindex;
-};
-
-#define Elf_Sym Elf64_Sym
-#define Elf_Shdr Elf64_Shdr
-#define Elf_Ehdr Elf64_Ehdr
-#define Elf_Phdr Elf64_Phdr
-#define Elf_Dyn Elf64_Dyn
-#define Elf_Rel Elf64_Rel
-#define Elf_Rela Elf64_Rela
-
-#define ARCH_SHF_SMALL SHF_ALPHA_GPREL
-
-#ifdef MODULE
-asm(".section .got,\"aws\",@progbits; .align 3; .previous");
-#endif
-
-#endif /*_ALPHA_MODULE_H*/
diff --git a/include/asm-alpha/msgbuf.h b/include/asm-alpha/msgbuf.h
deleted file mode 100644
index 98496501a2bb..000000000000
--- a/include/asm-alpha/msgbuf.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _ALPHA_MSGBUF_H
-#define _ALPHA_MSGBUF_H
-
-/* 
- * The msqid64_ds structure for alpha architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 2 miscellaneous 64-bit values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused1;
-        unsigned long  __unused2;
-};
-
-#endif /* _ALPHA_MSGBUF_H */
diff --git a/include/asm-alpha/mutex.h b/include/asm-alpha/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-alpha/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-alpha/page.h b/include/asm-alpha/page.h
deleted file mode 100644
index 0995f9d13417..000000000000
--- a/include/asm-alpha/page.h
+++ /dev/null
@@ -1,98 +0,0 @@
-#ifndef _ALPHA_PAGE_H
-#define _ALPHA_PAGE_H
-
-#include <linux/const.h>
-#include <asm/pal.h>
-
-/* PAGE_SHIFT determines the page size */
-#define PAGE_SHIFT      13
-#define PAGE_SIZE       (_AC(1,UL) << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE-1))
-
-#ifndef __ASSEMBLY__
-
-#define STRICT_MM_TYPECHECKS
-
-extern void clear_page(void *page);
-#define clear_user_page(page, vaddr, pg)        clear_page(page)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
-        alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vmaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-extern void copy_page(void * _to, void * _from);
-#define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
-
-#ifdef STRICT_MM_TYPECHECKS
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-
-#define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((x).pmd)
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-#else
-/*
- * .. while these make it easier on the compiler
- */
-typedef unsigned long pte_t;
-typedef unsigned long pmd_t;
-typedef unsigned long pgd_t;
-typedef unsigned long pgprot_t;
-
-#define pte_val(x)      (x)
-#define pmd_val(x)      (x)
-#define pgd_val(x)      (x)
-#define pgprot_val(x)   (x)
-
-#define __pte(x)        (x)
-#define __pgd(x)        (x)
-#define __pgprot(x)     (x)
-
-#endif /* STRICT_MM_TYPECHECKS */
-
-typedef struct page *pgtable_t;
-
-#ifdef USE_48_BIT_KSEG
-#define PAGE_OFFSET             0xffff800000000000UL
-#else
-#define PAGE_OFFSET             0xfffffc0000000000UL
-#endif
-
-#else
-
-#ifdef USE_48_BIT_KSEG
-#define PAGE_OFFSET             0xffff800000000000
-#else
-#define PAGE_OFFSET             0xfffffc0000000000
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-#define __pa(x)                 ((unsigned long) (x) - PAGE_OFFSET)
-#define __va(x)                 ((void *)((unsigned long) (x) + PAGE_OFFSET))
-#ifndef CONFIG_DISCONTIGMEM
-#define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-
-#define pfn_valid(pfn)          ((pfn) < max_mapnr)
-#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
-#endif /* CONFIG_DISCONTIGMEM */
-
-#define VM_DATA_DEFAULT_FLAGS           (VM_READ | VM_WRITE | VM_EXEC | \
-                                         VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif /* _ALPHA_PAGE_H */
diff --git a/include/asm-alpha/pal.h b/include/asm-alpha/pal.h
deleted file mode 100644
index 9b4ba0d6f00b..000000000000
--- a/include/asm-alpha/pal.h
+++ /dev/null
@@ -1,51 +0,0 @@
-#ifndef __ALPHA_PAL_H
-#define __ALPHA_PAL_H
-
-/*
- * Common PAL-code
- */
-#define PAL_halt          0
-#define PAL_cflush        1
-#define PAL_draina        2
-#define PAL_bpt         128
-#define PAL_bugchk      129
-#define PAL_chmk        131
-#define PAL_callsys     131
-#define PAL_imb         134
-#define PAL_rduniq      158
-#define PAL_wruniq      159
-#define PAL_gentrap     170
-#define PAL_nphalt      190
-
-/*
- * VMS specific PAL-code
- */
-#define PAL_swppal      10
-#define PAL_mfpr_vptb   41
-
-/*
- * OSF specific PAL-code
- */
-#define PAL_cserve       9
-#define PAL_wripir      13
-#define PAL_rdmces      16
-#define PAL_wrmces      17
-#define PAL_wrfen       43
-#define PAL_wrvptptr    45
-#define PAL_jtopal      46
-#define PAL_swpctx      48
-#define PAL_wrval       49
-#define PAL_rdval       50
-#define PAL_tbi         51
-#define PAL_wrent       52
-#define PAL_swpipl      53
-#define PAL_rdps        54
-#define PAL_wrkgp       55
-#define PAL_wrusp       56
-#define PAL_wrperfmon   57
-#define PAL_rdusp       58
-#define PAL_whami       60
-#define PAL_retsys      61
-#define PAL_rti         63
-
-#endif /* __ALPHA_PAL_H */
diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h
deleted file mode 100644
index e691ecfedb2c..000000000000
--- a/include/asm-alpha/param.h
+++ /dev/null
@@ -1,27 +0,0 @@
-#ifndef _ASM_ALPHA_PARAM_H
-#define _ASM_ALPHA_PARAM_H
-
-/* ??? Gross.  I don't want to parameterize this, and supposedly the
-   hardware ignores reprogramming.  We also need userland buy-in to the 
-   change in HZ, since this is visible in the wait4 resources etc.  */
-
-#ifdef __KERNEL__
-#define HZ              CONFIG_HZ
-#define USER_HZ         HZ
-#else
-#define HZ              1024
-#endif
-
-#define EXEC_PAGESIZE   8192
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#ifdef __KERNEL__
-# define CLOCKS_PER_SEC HZ      /* frequency at which times() counts */
-#endif
-
-#endif /* _ASM_ALPHA_PARAM_H */
diff --git a/include/asm-alpha/parport.h b/include/asm-alpha/parport.h
deleted file mode 100644
index c5ee7cbb2fcd..000000000000
--- a/include/asm-alpha/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * parport.h: platform-specific PC-style parport initialisation
- *
- * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-
-#ifndef _ASM_AXP_PARPORT_H
-#define _ASM_AXP_PARPORT_H 1
-
-static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports (autoirq, autodma);
-}
-
-#endif /* !(_ASM_AXP_PARPORT_H) */
diff --git a/include/asm-alpha/pci.h b/include/asm-alpha/pci.h
deleted file mode 100644
index 2a14302c17a3..000000000000
--- a/include/asm-alpha/pci.h
+++ /dev/null
@@ -1,276 +0,0 @@
-#ifndef __ALPHA_PCI_H
-#define __ALPHA_PCI_H
-
-#ifdef __KERNEL__
-
-#include <linux/spinlock.h>
-#include <linux/dma-mapping.h>
-#include <asm/scatterlist.h>
-#include <asm/machvec.h>
-
-/*
- * The following structure is used to manage multiple PCI busses.
- */
-
-struct pci_dev;
-struct pci_bus;
-struct resource;
-struct pci_iommu_arena;
-struct page;
-
-/* A controller.  Used to manage multiple PCI busses.  */
-
-struct pci_controller {
-        struct pci_controller *next;
-        struct pci_bus *bus;
-        struct resource *io_space;
-        struct resource *mem_space;
-
-        /* The following are for reporting to userland.  The invariant is
-           that if we report a BWX-capable dense memory, we do not report
-           a sparse memory at all, even if it exists.  */
-        unsigned long sparse_mem_base;
-        unsigned long dense_mem_base;
-        unsigned long sparse_io_base;
-        unsigned long dense_io_base;
-
-        /* This one's for the kernel only.  It's in KSEG somewhere.  */
-        unsigned long config_space_base;
-
-        unsigned int index;
-        /* For compatibility with current (as of July 2003) pciutils
-           and XFree86. Eventually will be removed. */
-        unsigned int need_domain_info;
-
-        struct pci_iommu_arena *sg_pci;
-        struct pci_iommu_arena *sg_isa;
-
-        void *sysdata;
-};
-
-/* Override the logic in pci_scan_bus for skipping already-configured
-   bus numbers.  */
-
-#define pcibios_assign_all_busses()     1
-#define pcibios_scan_all_fns(a, b)      0
-
-#define PCIBIOS_MIN_IO          alpha_mv.min_io_address
-#define PCIBIOS_MIN_MEM         alpha_mv.min_mem_address
-
-extern void pcibios_set_master(struct pci_dev *dev);
-
-extern inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-        /* We don't do dynamic PCI IRQ allocation */
-}
-
-/* IOMMU controls.  */
-
-/* The PCI address space does not equal the physical memory address space.
-   The networking and block device layers use this boolean for bounce buffer
-   decisions.  */
-#define PCI_DMA_BUS_IS_PHYS  0
-
-/* Allocate and map kernel buffer using consistent mode DMA for PCI
-   device.  Returns non-NULL cpu-view pointer to the buffer if
-   successful and sets *DMA_ADDRP to the pci side dma address as well,
-   else DMA_ADDRP is undefined.  */
-
-extern void *__pci_alloc_consistent(struct pci_dev *, size_t,
-                                    dma_addr_t *, gfp_t);
-static inline void *
-pci_alloc_consistent(struct pci_dev *dev, size_t size, dma_addr_t *dma)
-{
-        return __pci_alloc_consistent(dev, size, dma, GFP_ATOMIC);
-}
-
-/* Free and unmap a consistent DMA buffer.  CPU_ADDR and DMA_ADDR must
-   be values that were returned from pci_alloc_consistent.  SIZE must
-   be the same as what as passed into pci_alloc_consistent.
-   References to the memory and mappings associated with CPU_ADDR or
-   DMA_ADDR past this call are illegal.  */
-
-extern void pci_free_consistent(struct pci_dev *, size_t, void *, dma_addr_t);
-
-/* Map a single buffer of the indicate size for PCI DMA in streaming mode.
-   The 32-bit PCI bus mastering address to use is returned.  Once the device
-   is given the dma address, the device owns this memory until either
-   pci_unmap_single or pci_dma_sync_single_for_cpu is performed.  */
-
-extern dma_addr_t pci_map_single(struct pci_dev *, void *, size_t, int);
-
-/* Likewise, but for a page instead of an address.  */
-extern dma_addr_t pci_map_page(struct pci_dev *, struct page *,
-                               unsigned long, size_t, int);
-
-/* Test for pci_map_single or pci_map_page having generated an error.  */
-
-static inline int
-pci_dma_mapping_error(struct pci_dev *pdev, dma_addr_t dma_addr)
-{
-        return dma_addr == 0;
-}
-
-/* Unmap a single streaming mode DMA translation.  The DMA_ADDR and
-   SIZE must match what was provided for in a previous pci_map_single
-   call.  All other usages are undefined.  After this call, reads by
-   the cpu to the buffer are guaranteed to see whatever the device
-   wrote there.  */
-
-extern void pci_unmap_single(struct pci_dev *, dma_addr_t, size_t, int);
-extern void pci_unmap_page(struct pci_dev *, dma_addr_t, size_t, int);
-
-/* pci_unmap_{single,page} is not a nop, thus... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       \
-        dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         \
-        __u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME)                  \
-        ((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL)         \
-        (((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME)                    \
-        ((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)           \
-        (((PTR)->LEN_NAME) = (VAL))
-
-/* Map a set of buffers described by scatterlist in streaming mode for
-   PCI DMA.  This is the scatter-gather version of the above
-   pci_map_single interface.  Here the scatter gather list elements
-   are each tagged with the appropriate PCI dma address and length.
-   They are obtained via sg_dma_{address,length}(SG).
-
-   NOTE: An implementation may be able to use a smaller number of DMA
-   address/length pairs than there are SG table elements.  (for
-   example via virtual mapping capabilities) The routine returns the
-   number of addr/length pairs actually used, at most nents.
-
-   Device ownership issues as mentioned above for pci_map_single are
-   the same here.  */
-
-extern int pci_map_sg(struct pci_dev *, struct scatterlist *, int, int);
-
-/* Unmap a set of streaming mode DMA translations.  Again, cpu read
-   rules concerning calls here are the same as for pci_unmap_single()
-   above.  */
-
-extern void pci_unmap_sg(struct pci_dev *, struct scatterlist *, int, int);
-
-/* Make physical memory consistent for a single streaming mode DMA
-   translation after a transfer and device currently has ownership
-   of the buffer.
-
-   If you perform a pci_map_single() but wish to interrogate the
-   buffer using the cpu, yet do not wish to teardown the PCI dma
-   mapping, you must call this function before doing so.  At the next
-   point you give the PCI dma address back to the card, you must first
-   perform a pci_dma_sync_for_device, and then the device again owns
-   the buffer.  */
-
-static inline void
-pci_dma_sync_single_for_cpu(struct pci_dev *dev, dma_addr_t dma_addr,
-                            long size, int direction)
-{
-        /* Nothing to do.  */
-}
-
-static inline void
-pci_dma_sync_single_for_device(struct pci_dev *dev, dma_addr_t dma_addr,
-                               size_t size, int direction)
-{
-        /* Nothing to do.  */
-}
-
-/* Make physical memory consistent for a set of streaming mode DMA
-   translations after a transfer.  The same as pci_dma_sync_single_*
-   but for a scatter-gather list, same rules and usage.  */
-
-static inline void
-pci_dma_sync_sg_for_cpu(struct pci_dev *dev, struct scatterlist *sg,
-                        int nents, int direction)
-{
-        /* Nothing to do.  */
-}
-
-static inline void
-pci_dma_sync_sg_for_device(struct pci_dev *dev, struct scatterlist *sg,
-                           int nents, int direction)
-{
-        /* Nothing to do.  */
-}
-
-/* Return whether the given PCI device DMA address mask can
-   be supported properly.  For example, if your device can
-   only drive the low 24-bits during PCI bus mastering, then
-   you would pass 0x00ffffff as the mask to this function.  */
-
-extern int pci_dma_supported(struct pci_dev *hwdev, u64 mask);
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-                                        enum pci_dma_burst_strategy *strat,
-                                        unsigned long *strategy_parameter)
-{
-        unsigned long cacheline_size;
-        u8 byte;
-
-        pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
-        if (byte == 0)
-                cacheline_size = 1024;
-        else
-                cacheline_size = (int) byte * 4;
-
-        *strat = PCI_DMA_BURST_BOUNDARY;
-        *strategy_parameter = cacheline_size;
-}
-#endif
-
-/* TODO: integrate with include/asm-generic/pci.h ? */
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
-        return channel ? 15 : 14;
-}
-
-extern void pcibios_resource_to_bus(struct pci_dev *, struct pci_bus_region *,
-                                    struct resource *);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-        struct resource *root = NULL;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &ioport_resource;
-        if (res->flags & IORESOURCE_MEM)
-                root = &iomem_resource;
-
-        return root;
-}
-
-#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
-
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
-        struct pci_controller *hose = bus->sysdata;
-        return hose->need_domain_info;
-}
-
-struct pci_dev *alpha_gendev_to_pci(struct device *dev);
-
-#endif /* __KERNEL__ */
-
-/* Values for the `which' argument to sys_pciconfig_iobase.  */
-#define IOBASE_HOSE             0
-#define IOBASE_SPARSE_MEM       1
-#define IOBASE_DENSE_MEM        2
-#define IOBASE_SPARSE_IO        3
-#define IOBASE_DENSE_IO         4
-#define IOBASE_ROOT_BUS         5
-#define IOBASE_FROM_HOSE        0x10000
-
-extern struct pci_dev *isa_bridge;
-
-#endif /* __ALPHA_PCI_H */
diff --git a/include/asm-alpha/percpu.h b/include/asm-alpha/percpu.h
deleted file mode 100644
index 3495e8e00d70..000000000000
--- a/include/asm-alpha/percpu.h
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef __ALPHA_PERCPU_H
-#define __ALPHA_PERCPU_H
-#include <linux/compiler.h>
-#include <linux/threads.h>
-
-/*
- * Determine the real variable name from the name visible in the
- * kernel sources.
- */
-#define per_cpu_var(var) per_cpu__##var
-
-#ifdef CONFIG_SMP
-
-/*
- * per_cpu_offset() is the offset that has to be added to a
- * percpu variable to get to the instance for a certain processor.
- */
-extern unsigned long __per_cpu_offset[NR_CPUS];
-
-#define per_cpu_offset(x) (__per_cpu_offset[x])
-
-#define __my_cpu_offset per_cpu_offset(raw_smp_processor_id())
-#ifdef CONFIG_DEBUG_PREEMPT
-#define my_cpu_offset per_cpu_offset(smp_processor_id())
-#else
-#define my_cpu_offset __my_cpu_offset
-#endif
-
-#ifndef MODULE
-#define SHIFT_PERCPU_PTR(var, offset) RELOC_HIDE(&per_cpu_var(var), (offset))
-#define PER_CPU_ATTRIBUTES
-#else
-/*
- * To calculate addresses of locally defined variables, GCC uses 32-bit
- * displacement from the GP. Which doesn't work for per cpu variables in
- * modules, as an offset to the kernel per cpu area is way above 4G.
- *
- * This forces allocation of a GOT entry for per cpu variable using
- * ldq instruction with a 'literal' relocation.
- */
-#define SHIFT_PERCPU_PTR(var, offset) ({                \
-        extern int simple_identifier_##var(void);       \
-        unsigned long __ptr, tmp_gp;                    \
-        asm (  "br      %1, 1f                        \n\
-        1:      ldgp    %1, 0(%1)                     \n\
-                ldq %0, per_cpu__" #var"(%1)\t!literal"         \
-                : "=&r"(__ptr), "=&r"(tmp_gp));         \
-        (typeof(&per_cpu_var(var)))(__ptr + (offset)); })
-
-#define PER_CPU_ATTRIBUTES      __used
-
-#endif /* MODULE */
-
-/*
- * A percpu variable may point to a discarded regions. The following are
- * established ways to produce a usable pointer from the percpu variable
- * offset.
- */
-#define per_cpu(var, cpu) \
-        (*SHIFT_PERCPU_PTR(var, per_cpu_offset(cpu)))
-#define __get_cpu_var(var) \
-        (*SHIFT_PERCPU_PTR(var, my_cpu_offset))
-#define __raw_get_cpu_var(var) \
-        (*SHIFT_PERCPU_PTR(var, __my_cpu_offset))
-
-#else /* ! SMP */
-
-#define per_cpu(var, cpu)               (*((void)(cpu), &per_cpu_var(var)))
-#define __get_cpu_var(var)              per_cpu_var(var)
-#define __raw_get_cpu_var(var)          per_cpu_var(var)
-
-#define PER_CPU_ATTRIBUTES
-
-#endif /* SMP */
-
-#define DECLARE_PER_CPU(type, name) extern __typeof__(type) per_cpu_var(name)
-
-#endif /* __ALPHA_PERCPU_H */
diff --git a/include/asm-alpha/pgalloc.h b/include/asm-alpha/pgalloc.h
deleted file mode 100644
index fd090155dccd..000000000000
--- a/include/asm-alpha/pgalloc.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _ALPHA_PGALLOC_H
-#define _ALPHA_PGALLOC_H
-
-#include <linux/mm.h>
-#include <linux/mmzone.h>
-
-/*      
- * Allocate and free page tables. The xxx_kernel() versions are
- * used to allocate a kernel page table - this turns on ASN bits
- * if any.
- */
-
-static inline void
-pmd_populate(struct mm_struct *mm, pmd_t *pmd, pgtable_t pte)
-{
-        pmd_set(pmd, (pte_t *)(page_to_pa(pte) + PAGE_OFFSET));
-}
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-static inline void
-pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd, pte_t *pte)
-{
-        pmd_set(pmd, pte);
-}
-
-static inline void
-pgd_populate(struct mm_struct *mm, pgd_t *pgd, pmd_t *pmd)
-{
-        pgd_set(pgd, pmd);
-}
-
-extern pgd_t *pgd_alloc(struct mm_struct *mm);
-
-static inline void
-pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-        free_page((unsigned long)pgd);
-}
-
-static inline pmd_t *
-pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        pmd_t *ret = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
-        return ret;
-}
-
-static inline void
-pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
-        free_page((unsigned long)pmd);
-}
-
-extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
-
-static inline void
-pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-        free_page((unsigned long)pte);
-}
-
-static inline pgtable_t
-pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        pte_t *pte = pte_alloc_one_kernel(mm, address);
-        struct page *page;
-
-        if (!pte)
-                return NULL;
-        page = virt_to_page(pte);
-        pgtable_page_ctor(page);
-        return page;
-}
-
-static inline void
-pte_free(struct mm_struct *mm, pgtable_t page)
-{
-        pgtable_page_dtor(page);
-        __free_page(page);
-}
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif /* _ALPHA_PGALLOC_H */
diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h
deleted file mode 100644
index 3f0c59f6d8aa..000000000000
--- a/include/asm-alpha/pgtable.h
+++ /dev/null
@@ -1,380 +0,0 @@
-#ifndef _ALPHA_PGTABLE_H
-#define _ALPHA_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-/*
- * This file contains the functions and defines necessary to modify and use
- * the Alpha page table tree.
- *
- * This hopefully works with any standard Alpha page-size, as defined
- * in <asm/page.h> (currently 8192).
- */
-#include <linux/mmzone.h>
-
-#include <asm/page.h>
-#include <asm/processor.h>      /* For TASK_SIZE */
-#include <asm/machvec.h>
-
-struct mm_struct;
-struct vm_area_struct;
-
-/* Certain architectures need to do special things when PTEs
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-#define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
-#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
-
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT-3))
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (PAGE_SHIFT + 2*(PAGE_SHIFT-3))
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK      (~(PGDIR_SIZE-1))
-
-/*
- * Entries per page directory level:  the Alpha is three-level, with
- * all levels having a one-page page table.
- */
-#define PTRS_PER_PTE    (1UL << (PAGE_SHIFT-3))
-#define PTRS_PER_PMD    (1UL << (PAGE_SHIFT-3))
-#define PTRS_PER_PGD    (1UL << (PAGE_SHIFT-3))
-#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
-#define FIRST_USER_ADDRESS      0
-
-/* Number of pointers that fit on a page:  this will go away. */
-#define PTRS_PER_PAGE   (1UL << (PAGE_SHIFT-3))
-
-#ifdef CONFIG_ALPHA_LARGE_VMALLOC
-#define VMALLOC_START           0xfffffe0000000000
-#else
-#define VMALLOC_START           (-2*PGDIR_SIZE)
-#endif
-#define VMALLOC_END             (-PGDIR_SIZE)
-
-/*
- * OSF/1 PAL-code-imposed page table bits
- */
-#define _PAGE_VALID     0x0001
-#define _PAGE_FOR       0x0002  /* used for page protection (fault on read) */
-#define _PAGE_FOW       0x0004  /* used for page protection (fault on write) */
-#define _PAGE_FOE       0x0008  /* used for page protection (fault on exec) */
-#define _PAGE_ASM       0x0010
-#define _PAGE_KRE       0x0100  /* xxx - see below on the "accessed" bit */
-#define _PAGE_URE       0x0200  /* xxx */
-#define _PAGE_KWE       0x1000  /* used to do the dirty bit in software */
-#define _PAGE_UWE       0x2000  /* used to do the dirty bit in software */
-
-/* .. and these are ours ... */
-#define _PAGE_DIRTY     0x20000
-#define _PAGE_ACCESSED  0x40000
-#define _PAGE_FILE      0x80000 /* set:pagecache, unset:swap */
-
-/*
- * NOTE! The "accessed" bit isn't necessarily exact:  it can be kept exactly
- * by software (use the KRE/URE/KWE/UWE bits appropriately), but I'll fake it.
- * Under Linux/AXP, the "accessed" bit just means "read", and I'll just use
- * the KRE/URE bits to watch for it. That way we don't need to overload the
- * KWE/UWE bits with both handling dirty and accessed.
- *
- * Note that the kernel uses the accessed bit just to check whether to page
- * out a page or not, so it doesn't have to be exact anyway.
- */
-
-#define __DIRTY_BITS    (_PAGE_DIRTY | _PAGE_KWE | _PAGE_UWE)
-#define __ACCESS_BITS   (_PAGE_ACCESSED | _PAGE_KRE | _PAGE_URE)
-
-#define _PFN_MASK       0xFFFFFFFF00000000UL
-
-#define _PAGE_TABLE     (_PAGE_VALID | __DIRTY_BITS | __ACCESS_BITS)
-#define _PAGE_CHG_MASK  (_PFN_MASK | __DIRTY_BITS | __ACCESS_BITS)
-
-/*
- * All the normal masks have the "page accessed" bits on, as any time they are used,
- * the page is accessed. They are cleared only by the page-out routines
- */
-#define PAGE_NONE       __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOR | _PAGE_FOW | _PAGE_FOE)
-#define PAGE_SHARED     __pgprot(_PAGE_VALID | __ACCESS_BITS)
-#define PAGE_COPY       __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
-#define PAGE_READONLY   __pgprot(_PAGE_VALID | __ACCESS_BITS | _PAGE_FOW)
-#define PAGE_KERNEL     __pgprot(_PAGE_VALID | _PAGE_ASM | _PAGE_KRE | _PAGE_KWE)
-
-#define _PAGE_NORMAL(x) __pgprot(_PAGE_VALID | __ACCESS_BITS | (x))
-
-#define _PAGE_P(x) _PAGE_NORMAL((x) | (((x) & _PAGE_FOW)?0:_PAGE_FOW))
-#define _PAGE_S(x) _PAGE_NORMAL(x)
-
-/*
- * The hardware can handle write-only mappings, but as the Alpha
- * architecture does byte-wide writes with a read-modify-write
- * sequence, it's not practical to have write-without-read privs.
- * Thus the "-w- -> rw-" and "-wx -> rwx" mapping here (and in
- * arch/alpha/mm/fault.c)
- */
-        /* xwr */
-#define __P000  _PAGE_P(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
-#define __P001  _PAGE_P(_PAGE_FOE | _PAGE_FOW)
-#define __P010  _PAGE_P(_PAGE_FOE)
-#define __P011  _PAGE_P(_PAGE_FOE)
-#define __P100  _PAGE_P(_PAGE_FOW | _PAGE_FOR)
-#define __P101  _PAGE_P(_PAGE_FOW)
-#define __P110  _PAGE_P(0)
-#define __P111  _PAGE_P(0)
-
-#define __S000  _PAGE_S(_PAGE_FOE | _PAGE_FOW | _PAGE_FOR)
-#define __S001  _PAGE_S(_PAGE_FOE | _PAGE_FOW)
-#define __S010  _PAGE_S(_PAGE_FOE)
-#define __S011  _PAGE_S(_PAGE_FOE)
-#define __S100  _PAGE_S(_PAGE_FOW | _PAGE_FOR)
-#define __S101  _PAGE_S(_PAGE_FOW)
-#define __S110  _PAGE_S(0)
-#define __S111  _PAGE_S(0)
-
-/*
- * pgprot_noncached() is only for infiniband pci support, and a real
- * implementation for RAM would be more complicated.
- */
-#define pgprot_noncached(prot)  (prot)
-
-/*
- * BAD_PAGETABLE is used when we need a bogus page-table, while
- * BAD_PAGE is used for a bogus page.
- *
- * ZERO_PAGE is a global shared page that is always zero:  used
- * for zero-mapped memory areas etc..
- */
-extern pte_t __bad_page(void);
-extern pmd_t * __bad_pagetable(void);
-
-extern unsigned long __zero_page(void);
-
-#define BAD_PAGETABLE   __bad_pagetable()
-#define BAD_PAGE        __bad_page()
-#define ZERO_PAGE(vaddr)        (virt_to_page(ZERO_PGE))
-
-/* number of bits that fit into a memory pointer */
-#define BITS_PER_PTR                    (8*sizeof(unsigned long))
-
-/* to align the pointer to a pointer address */
-#define PTR_MASK                        (~(sizeof(void*)-1))
-
-/* sizeof(void*)==1<<SIZEOF_PTR_LOG2 */
-#define SIZEOF_PTR_LOG2                 3
-
-/* to find an entry in a page-table */
-#define PAGE_PTR(address)               \
-  ((unsigned long)(address)>>(PAGE_SHIFT-SIZEOF_PTR_LOG2)&PTR_MASK&~PAGE_MASK)
-
-/*
- * On certain platforms whose physical address space can overlap KSEG,
- * namely EV6 and above, we must re-twiddle the physaddr to restore the
- * correct high-order bits.
- *
- * This is extremely confusing until you realize that this is actually
- * just working around a userspace bug.  The X server was intending to
- * provide the physical address but instead provided the KSEG address.
- * Or tried to, except it's not representable.
- * 
- * On Tsunami there's nothing meaningful at 0x40000000000, so this is
- * a safe thing to do.  Come the first core logic that does put something
- * in this area -- memory or whathaveyou -- then this hack will have
- * to go away.  So be prepared!
- */
-
-#if defined(CONFIG_ALPHA_GENERIC) && defined(USE_48_BIT_KSEG)
-#error "EV6-only feature in a generic kernel"
-#endif
-#if defined(CONFIG_ALPHA_GENERIC) || \
-    (defined(CONFIG_ALPHA_EV6) && !defined(USE_48_BIT_KSEG))
-#define KSEG_PFN        (0xc0000000000UL >> PAGE_SHIFT)
-#define PHYS_TWIDDLE(pfn) \
-  ((((pfn) & KSEG_PFN) == (0x40000000000UL >> PAGE_SHIFT)) \
-  ? ((pfn) ^= KSEG_PFN) : (pfn))
-#else
-#define PHYS_TWIDDLE(pfn) (pfn)
-#endif
-
-/*
- * Conversion functions:  convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#ifndef CONFIG_DISCONTIGMEM
-#define page_to_pa(page)        (((page) - mem_map) << PAGE_SHIFT)
-
-#define pte_pfn(pte)    (pte_val(pte) >> 32)
-#define pte_page(pte)   pfn_to_page(pte_pfn(pte))
-#define mk_pte(page, pgprot)                                            \
-({                                                                      \
-        pte_t pte;                                                      \
-                                                                        \
-        pte_val(pte) = (page_to_pfn(page) << 32) | pgprot_val(pgprot);  \
-        pte;                                                            \
-})
-#endif
-
-extern inline pte_t pfn_pte(unsigned long physpfn, pgprot_t pgprot)
-{ pte_t pte; pte_val(pte) = (PHYS_TWIDDLE(physpfn) << 32) | pgprot_val(pgprot); return pte; }
-
-extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
-
-extern inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
-{ pmd_val(*pmdp) = _PAGE_TABLE | ((((unsigned long) ptep) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
-
-extern inline void pgd_set(pgd_t * pgdp, pmd_t * pmdp)
-{ pgd_val(*pgdp) = _PAGE_TABLE | ((((unsigned long) pmdp) - PAGE_OFFSET) << (32-PAGE_SHIFT)); }
-
-
-extern inline unsigned long
-pmd_page_vaddr(pmd_t pmd)
-{
-        return ((pmd_val(pmd) & _PFN_MASK) >> (32-PAGE_SHIFT)) + PAGE_OFFSET;
-}
-
-#ifndef CONFIG_DISCONTIGMEM
-#define pmd_page(pmd)   (mem_map + ((pmd_val(pmd) & _PFN_MASK) >> 32))
-#define pgd_page(pgd)   (mem_map + ((pgd_val(pgd) & _PFN_MASK) >> 32))
-#endif
-
-extern inline unsigned long pgd_page_vaddr(pgd_t pgd)
-{ return PAGE_OFFSET + ((pgd_val(pgd) & _PFN_MASK) >> (32-PAGE_SHIFT)); }
-
-extern inline int pte_none(pte_t pte)           { return !pte_val(pte); }
-extern inline int pte_present(pte_t pte)        { return pte_val(pte) & _PAGE_VALID; }
-extern inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
-        pte_val(*ptep) = 0;
-}
-
-extern inline int pmd_none(pmd_t pmd)           { return !pmd_val(pmd); }
-extern inline int pmd_bad(pmd_t pmd)            { return (pmd_val(pmd) & ~_PFN_MASK) != _PAGE_TABLE; }
-extern inline int pmd_present(pmd_t pmd)        { return pmd_val(pmd) & _PAGE_VALID; }
-extern inline void pmd_clear(pmd_t * pmdp)      { pmd_val(*pmdp) = 0; }
-
-extern inline int pgd_none(pgd_t pgd)           { return !pgd_val(pgd); }
-extern inline int pgd_bad(pgd_t pgd)            { return (pgd_val(pgd) & ~_PFN_MASK) != _PAGE_TABLE; }
-extern inline int pgd_present(pgd_t pgd)        { return pgd_val(pgd) & _PAGE_VALID; }
-extern inline void pgd_clear(pgd_t * pgdp)      { pgd_val(*pgdp) = 0; }
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-extern inline int pte_write(pte_t pte)          { return !(pte_val(pte) & _PAGE_FOW); }
-extern inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
-extern inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
-extern inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
-extern inline int pte_special(pte_t pte)        { return 0; }
-
-extern inline pte_t pte_wrprotect(pte_t pte)    { pte_val(pte) |= _PAGE_FOW; return pte; }
-extern inline pte_t pte_mkclean(pte_t pte)      { pte_val(pte) &= ~(__DIRTY_BITS); return pte; }
-extern inline pte_t pte_mkold(pte_t pte)        { pte_val(pte) &= ~(__ACCESS_BITS); return pte; }
-extern inline pte_t pte_mkwrite(pte_t pte)      { pte_val(pte) &= ~_PAGE_FOW; return pte; }
-extern inline pte_t pte_mkdirty(pte_t pte)      { pte_val(pte) |= __DIRTY_BITS; return pte; }
-extern inline pte_t pte_mkyoung(pte_t pte)      { pte_val(pte) |= __ACCESS_BITS; return pte; }
-extern inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
-
-#define PAGE_DIR_OFFSET(tsk,address) pgd_offset((tsk),(address))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, (address))
-
-/* to find an entry in a page-table-directory. */
-#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
-
-/*
- * The smp_read_barrier_depends() in the following functions are required to
- * order the load of *dir (the pointer in the top level page table) with any
- * subsequent load of the returned pmd_t *ret (ret is data dependent on *dir).
- *
- * If this ordering is not enforced, the CPU might load an older value of
- * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
- * more details.
- *
- * Note that we never change the mm->pgd pointer after the task is running, so
- * pgd_offset does not require such a barrier.
- */
-
-/* Find an entry in the second-level page table.. */
-extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
-{
-        pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
-        smp_read_barrier_depends(); /* see above */
-        return ret;
-}
-
-/* Find an entry in the third-level page table.. */
-extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
-{
-        pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
-                + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
-        smp_read_barrier_depends(); /* see above */
-        return ret;
-}
-
-#define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
-#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
-#define pte_unmap(pte)                  do { } while (0)
-#define pte_unmap_nested(pte)           do { } while (0)
-
-extern pgd_t swapper_pg_dir[1024];
-
-/*
- * The Alpha doesn't have any external MMU info:  the kernel page
- * tables contain all the necessary information.
- */
-extern inline void update_mmu_cache(struct vm_area_struct * vma,
-        unsigned long address, pte_t pte)
-{
-}
-
-/*
- * Non-present pages:  high 24 bits are offset, next 8 bits type,
- * low 32 bits zero.
- */
-extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
-{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
-
-#define __swp_type(x)           (((x).val >> 32) & 0xff)
-#define __swp_offset(x)         ((x).val >> 40)
-#define __swp_entry(type, off)  ((swp_entry_t) { pte_val(mk_swap_pte((type), (off))) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-
-#define pte_to_pgoff(pte)       (pte_val(pte) >> 32)
-#define pgoff_to_pte(off)       ((pte_t) { ((off) << 32) | _PAGE_FILE })
-
-#define PTE_FILE_MAX_BITS       32
-
-#ifndef CONFIG_DISCONTIGMEM
-#define kern_addr_valid(addr)   (1)
-#endif
-
-#define io_remap_pfn_range(vma, start, pfn, size, prot) \
-                remap_pfn_range(vma, start, pfn, size, prot)
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-extern void paging_init(void);
-
-#include <asm-generic/pgtable.h>
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()    do { } while (0)
-
-/* We have our own get_unmapped_area to cope with ADDR_LIMIT_32BIT.  */
-#define HAVE_ARCH_UNMAPPED_AREA
-
-#endif /* _ALPHA_PGTABLE_H */
diff --git a/include/asm-alpha/poll.h b/include/asm-alpha/poll.h
deleted file mode 100644
index c98509d3149e..000000000000
--- a/include/asm-alpha/poll.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/poll.h>
diff --git a/include/asm-alpha/posix_types.h b/include/asm-alpha/posix_types.h
deleted file mode 100644
index db167413300b..000000000000
--- a/include/asm-alpha/posix_types.h
+++ /dev/null
@@ -1,123 +0,0 @@
-#ifndef _ALPHA_POSIX_TYPES_H
-#define _ALPHA_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned int    __kernel_ino_t;
-typedef unsigned int    __kernel_mode_t;
-typedef unsigned int    __kernel_nlink_t;
-typedef long            __kernel_off_t;
-typedef long long       __kernel_loff_t;
-typedef int             __kernel_pid_t;
-typedef int             __kernel_ipc_pid_t;
-typedef unsigned int    __kernel_uid_t;
-typedef unsigned int    __kernel_gid_t;
-typedef unsigned long   __kernel_size_t;
-typedef long            __kernel_ssize_t;
-typedef long            __kernel_ptrdiff_t;
-typedef long            __kernel_time_t;
-typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
-typedef int             __kernel_daddr_t;
-typedef char *          __kernel_caddr_t;
-typedef unsigned long   __kernel_sigset_t;      /* at least 32 bits */
-typedef unsigned short  __kernel_uid16_t;
-typedef unsigned short  __kernel_gid16_t;
-typedef int             __kernel_clockid_t;
-typedef int             __kernel_timer_t;
-
-typedef struct {
-        int     val[2];
-} __kernel_fsid_t;
-
-typedef __kernel_uid_t __kernel_old_uid_t;
-typedef __kernel_gid_t __kernel_old_gid_t;
-typedef __kernel_uid_t __kernel_uid32_t;
-typedef __kernel_gid_t __kernel_gid32_t;
-
-typedef unsigned int    __kernel_old_dev_t;
-
-#ifdef __KERNEL__
-
-#ifndef __GNUC__
-
-#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-#define __FD_ISSET(d, set)      (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
-#define __FD_ZERO(set)  \
-  ((void) memset ((void *) (set), 0, sizeof (__kernel_fd_set)))
-
-#else /* __GNUC__ */
-
-/* With GNU C, use inline functions instead so args are evaluated only once: */
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
-{
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long fd, const __kernel_fd_set *p)
-{ 
-        unsigned long _tmp = fd / __NFDBITS;
-        unsigned long _rem = fd % __NFDBITS;
-        return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *p)
-{
-        unsigned long *tmp = p->fds_bits;
-        int i;
-
-        if (__builtin_constant_p(__FDSET_LONGS)) {
-                switch (__FDSET_LONGS) {
-                      case 16:
-                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-                        tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
-                        tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
-                        tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
-                        return;
-
-                      case 8:
-                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-                        tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
-                        return;
-
-                      case 4:
-                        tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
-                        return;
-                }
-        }
-        i = __FDSET_LONGS;
-        while (i) {
-                i--;
-                *tmp = 0;
-                tmp++;
-        }
-}
-
-#endif /* __GNUC__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ALPHA_POSIX_TYPES_H */
diff --git a/include/asm-alpha/processor.h b/include/asm-alpha/processor.h
deleted file mode 100644
index 94afe5859301..000000000000
--- a/include/asm-alpha/processor.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * include/asm-alpha/processor.h
- *
- * Copyright (C) 1994 Linus Torvalds
- */
-
-#ifndef __ASM_ALPHA_PROCESSOR_H
-#define __ASM_ALPHA_PROCESSOR_H
-
-#include <linux/personality.h>  /* for ADDR_LIMIT_32BIT */
-
-/*
- * Returns current instruction pointer ("program counter").
- */
-#define current_text_addr() \
-  ({ void *__pc; __asm__ ("br %0,.+4" : "=r"(__pc)); __pc; })
-
-/*
- * We have a 42-bit user address space: 4TB user VM...
- */
-#define TASK_SIZE (0x40000000000UL)
-
-#define STACK_TOP \
-  (current->personality & ADDR_LIMIT_32BIT ? 0x80000000 : 0x00120000000UL)
-
-#define STACK_TOP_MAX   0x00120000000UL
-
-/* This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE \
-  ((current->personality & ADDR_LIMIT_32BIT) ? 0x40000000 : TASK_SIZE / 2)
-
-typedef struct {
-        unsigned long seg;
-} mm_segment_t;
-
-/* This is dead.  Everything has been moved to thread_info.  */
-struct thread_struct { };
-#define INIT_THREAD  { }
-
-/* Return saved PC of a blocked thread.  */
-struct task_struct;
-extern unsigned long thread_saved_pc(struct task_struct *);
-
-/* Do necessary setup to start up a newly executed thread.  */
-extern void start_thread(struct pt_regs *, unsigned long, unsigned long);
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk)    do { } while (0)
-
-/* Create a kernel thread without removing it from tasklists.  */
-extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)
-
-#define KSTK_ESP(tsk) \
-  ((tsk) == current ? rdusp() : task_thread_info(tsk)->pcb.usp)
-
-#define cpu_relax()     barrier()
-
-#define ARCH_HAS_PREFETCH
-#define ARCH_HAS_PREFETCHW
-#define ARCH_HAS_SPINLOCK_PREFETCH
-
-#ifndef CONFIG_SMP
-/* Nothing to prefetch. */
-#define spin_lock_prefetch(lock)        do { } while (0)
-#endif
-
-extern inline void prefetch(const void *ptr)  
-{ 
-        __builtin_prefetch(ptr, 0, 3);
-}
-
-extern inline void prefetchw(const void *ptr)  
-{
-        __builtin_prefetch(ptr, 1, 3);
-}
-
-#ifdef CONFIG_SMP
-extern inline void spin_lock_prefetch(const void *ptr)  
-{
-        __builtin_prefetch(ptr, 1, 3);
-}
-#endif
-
-#endif /* __ASM_ALPHA_PROCESSOR_H */
diff --git a/include/asm-alpha/ptrace.h b/include/asm-alpha/ptrace.h
deleted file mode 100644
index 32c7a5cddd59..000000000000
--- a/include/asm-alpha/ptrace.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _ASMAXP_PTRACE_H
-#define _ASMAXP_PTRACE_H
-
-
-/*
- * This struct defines the way the registers are stored on the
- * kernel stack during a system call or other kernel entry
- *
- * NOTE! I want to minimize the overhead of system calls, so this
- * struct has as little information as possible.  I does not have
- *
- *  - floating point regs: the kernel doesn't change those
- *  - r9-15: saved by the C compiler
- *
- * This makes "fork()" and "exec()" a bit more complex, but should
- * give us low system call latency.
- */
-
-struct pt_regs {
-        unsigned long r0;
-        unsigned long r1;
-        unsigned long r2;
-        unsigned long r3;
-        unsigned long r4;
-        unsigned long r5;
-        unsigned long r6;
-        unsigned long r7;
-        unsigned long r8;
-        unsigned long r19;
-        unsigned long r20;
-        unsigned long r21;
-        unsigned long r22;
-        unsigned long r23;
-        unsigned long r24;
-        unsigned long r25;
-        unsigned long r26;
-        unsigned long r27;
-        unsigned long r28;
-        unsigned long hae;
-/* JRP - These are the values provided to a0-a2 by PALcode */
-        unsigned long trap_a0;
-        unsigned long trap_a1;
-        unsigned long trap_a2;
-/* These are saved by PAL-code: */
-        unsigned long ps;
-        unsigned long pc;
-        unsigned long gp;
-        unsigned long r16;
-        unsigned long r17;
-        unsigned long r18;
-};
-
-/*
- * This is the extended stack used by signal handlers and the context
- * switcher: it's pushed after the normal "struct pt_regs".
- */
-struct switch_stack {
-        unsigned long r9;
-        unsigned long r10;
-        unsigned long r11;
-        unsigned long r12;
-        unsigned long r13;
-        unsigned long r14;
-        unsigned long r15;
-        unsigned long r26;
-        unsigned long fp[32];   /* fp[31] is fpcr */
-};
-
-#ifdef __KERNEL__
-
-#define user_mode(regs) (((regs)->ps & 8) != 0)
-#define instruction_pointer(regs) ((regs)->pc)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-
-#define task_pt_regs(task) \
-  ((struct pt_regs *) (task_stack_page(task) + 2*PAGE_SIZE) - 1)
-
-#define force_successful_syscall_return() (task_pt_regs(current)->r0 = 0)
-
-#endif
-
-#endif
diff --git a/include/asm-alpha/reg.h b/include/asm-alpha/reg.h
deleted file mode 100644
index 86ff916fb069..000000000000
--- a/include/asm-alpha/reg.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef __reg_h__
-#define __reg_h__
-
-/*
- * Exception frame offsets.
- */
-#define EF_V0           0
-#define EF_T0           1
-#define EF_T1           2
-#define EF_T2           3
-#define EF_T3           4
-#define EF_T4           5
-#define EF_T5           6
-#define EF_T6           7
-#define EF_T7           8
-#define EF_S0           9
-#define EF_S1           10
-#define EF_S2           11
-#define EF_S3           12
-#define EF_S4           13
-#define EF_S5           14
-#define EF_S6           15
-#define EF_A3           16
-#define EF_A4           17
-#define EF_A5           18
-#define EF_T8           19
-#define EF_T9           20
-#define EF_T10          21
-#define EF_T11          22
-#define EF_RA           23
-#define EF_T12          24
-#define EF_AT           25
-#define EF_SP           26
-#define EF_PS           27
-#define EF_PC           28
-#define EF_GP           29
-#define EF_A0           30
-#define EF_A1           31
-#define EF_A2           32
-
-#define EF_SIZE         (33*8)
-#define HWEF_SIZE       (6*8)           /* size of PAL frame (PS-A2) */
-
-#define EF_SSIZE        (EF_SIZE - HWEF_SIZE)
-
-/*
- * Map register number into core file offset.
- */
-#define CORE_REG(reg, ubase) \
-        (((unsigned long *)((unsigned long)(ubase)))[reg])
-
-#endif /* __reg_h__ */
diff --git a/include/asm-alpha/regdef.h b/include/asm-alpha/regdef.h
deleted file mode 100644
index 142df9c4f8b8..000000000000
--- a/include/asm-alpha/regdef.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __alpha_regdef_h__
-#define __alpha_regdef_h__
-
-#define v0      $0      /* function return value */
-
-#define t0      $1      /* temporary registers (caller-saved) */
-#define t1      $2
-#define t2      $3
-#define t3      $4
-#define t4      $5
-#define t5      $6
-#define t6      $7
-#define t7      $8
-
-#define s0      $9      /* saved-registers (callee-saved registers) */
-#define s1      $10
-#define s2      $11
-#define s3      $12
-#define s4      $13
-#define s5      $14
-#define s6      $15
-#define fp      s6      /* frame-pointer (s6 in frame-less procedures) */
-
-#define a0      $16     /* argument registers (caller-saved) */
-#define a1      $17
-#define a2      $18
-#define a3      $19
-#define a4      $20
-#define a5      $21
-
-#define t8      $22     /* more temps (caller-saved) */
-#define t9      $23
-#define t10     $24
-#define t11     $25
-#define ra      $26     /* return address register */
-#define t12     $27
-
-#define pv      t12     /* procedure-variable register */
-#define AT      $at     /* assembler temporary */
-#define gp      $29     /* global pointer */
-#define sp      $30     /* stack pointer */
-#define zero    $31     /* reads as zero, writes are noops */
-
-#endif /* __alpha_regdef_h__ */
diff --git a/include/asm-alpha/resource.h b/include/asm-alpha/resource.h
deleted file mode 100644
index c10874ff5973..000000000000
--- a/include/asm-alpha/resource.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ALPHA_RESOURCE_H
-#define _ALPHA_RESOURCE_H
-
-/*
- * Alpha/Linux-specific ordering of these four resource limit IDs,
- * the rest comes from the generic header:
- */
-#define RLIMIT_NOFILE           6       /* max number of open files */
-#define RLIMIT_AS               7       /* address space limit */
-#define RLIMIT_NPROC            8       /* max number of processes */
-#define RLIMIT_MEMLOCK          9       /* max locked-in-memory address space */
-
-/*
- * SuS says limits have to be unsigned.  Fine, it's unsigned, but
- * we retain the old value for compatibility, especially with DU. 
- * When you run into the 2^63 barrier, you call me.
- */
-#define RLIM_INFINITY           0x7ffffffffffffffful
-
-#include <asm-generic/resource.h>
-
-#endif /* _ALPHA_RESOURCE_H */
diff --git a/include/asm-alpha/rtc.h b/include/asm-alpha/rtc.h
deleted file mode 100644
index 4e854b1333eb..000000000000
--- a/include/asm-alpha/rtc.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _ALPHA_RTC_H
-#define _ALPHA_RTC_H
-
-/*
- * Alpha uses the default access methods for the RTC.
- */
-
-#include <asm-generic/rtc.h>
-
-#endif
diff --git a/include/asm-alpha/rwsem.h b/include/asm-alpha/rwsem.h
deleted file mode 100644
index 1570c0b54336..000000000000
--- a/include/asm-alpha/rwsem.h
+++ /dev/null
@@ -1,259 +0,0 @@
-#ifndef _ALPHA_RWSEM_H
-#define _ALPHA_RWSEM_H
-
-/*
- * Written by Ivan Kokshaysky <ink@jurassic.park.msu.ru>, 2001.
- * Based on asm-alpha/semaphore.h and asm-i386/rwsem.h
- */
-
-#ifndef _LINUX_RWSEM_H
-#error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
-#endif
-
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-
-struct rwsem_waiter;
-
-extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
-extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *);
-extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
-
-/*
- * the semaphore definition
- */
-struct rw_semaphore {
-        long                    count;
-#define RWSEM_UNLOCKED_VALUE            0x0000000000000000L
-#define RWSEM_ACTIVE_BIAS               0x0000000000000001L
-#define RWSEM_ACTIVE_MASK               0x00000000ffffffffL
-#define RWSEM_WAITING_BIAS              (-0x0000000100000000L)
-#define RWSEM_ACTIVE_READ_BIAS          RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
-        spinlock_t              wait_lock;
-        struct list_head        wait_list;
-};
-
-#define __RWSEM_INITIALIZER(name) \
-        { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-        LIST_HEAD_INIT((name).wait_list) }
-
-#define DECLARE_RWSEM(name) \
-        struct rw_semaphore name = __RWSEM_INITIALIZER(name)
-
-static inline void init_rwsem(struct rw_semaphore *sem)
-{
-        sem->count = RWSEM_UNLOCKED_VALUE;
-        spin_lock_init(&sem->wait_lock);
-        INIT_LIST_HEAD(&sem->wait_list);
-}
-
-static inline void __down_read(struct rw_semaphore *sem)
-{
-        long oldcount;
-#ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count += RWSEM_ACTIVE_READ_BIAS;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%3,%2\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        "       mb\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (RWSEM_ACTIVE_READ_BIAS), "m" (sem->count) : "memory");
-#endif
-        if (unlikely(oldcount < 0))
-                rwsem_down_read_failed(sem);
-}
-
-/*
- * trylock for reading -- returns 1 if successful, 0 if contention
- */
-static inline int __down_read_trylock(struct rw_semaphore *sem)
-{
-        long old, new, res;
-
-        res = sem->count;
-        do {
-                new = res + RWSEM_ACTIVE_READ_BIAS;
-                if (new <= 0)
-                        break;
-                old = res;
-                res = cmpxchg(&sem->count, old, new);
-        } while (res != old);
-        return res >= 0 ? 1 : 0;
-}
-
-static inline void __down_write(struct rw_semaphore *sem)
-{
-        long oldcount;
-#ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count += RWSEM_ACTIVE_WRITE_BIAS;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%3,%2\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        "       mb\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (RWSEM_ACTIVE_WRITE_BIAS), "m" (sem->count) : "memory");
-#endif
-        if (unlikely(oldcount))
-                rwsem_down_write_failed(sem);
-}
-
-/*
- * trylock for writing -- returns 1 if successful, 0 if contention
- */
-static inline int __down_write_trylock(struct rw_semaphore *sem)
-{
-        long ret = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
-                           RWSEM_ACTIVE_WRITE_BIAS);
-        if (ret == RWSEM_UNLOCKED_VALUE)
-                return 1;
-        return 0;
-}
-
-static inline void __up_read(struct rw_semaphore *sem)
-{
-        long oldcount;
-#ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count -= RWSEM_ACTIVE_READ_BIAS;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "       mb\n"
-        "1:     ldq_l   %0,%1\n"
-        "       subq    %0,%3,%2\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (RWSEM_ACTIVE_READ_BIAS), "m" (sem->count) : "memory");
-#endif
-        if (unlikely(oldcount < 0))
-                if ((int)oldcount - RWSEM_ACTIVE_READ_BIAS == 0)
-                        rwsem_wake(sem);
-}
-
-static inline void __up_write(struct rw_semaphore *sem)
-{
-        long count;
-#ifndef CONFIG_SMP
-        sem->count -= RWSEM_ACTIVE_WRITE_BIAS;
-        count = sem->count;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "       mb\n"
-        "1:     ldq_l   %0,%1\n"
-        "       subq    %0,%3,%2\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        "       subq    %0,%3,%0\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (count), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (RWSEM_ACTIVE_WRITE_BIAS), "m" (sem->count) : "memory");
-#endif
-        if (unlikely(count))
-                if ((int)count == 0)
-                        rwsem_wake(sem);
-}
-
-/*
- * downgrade write lock to read lock
- */
-static inline void __downgrade_write(struct rw_semaphore *sem)
-{
-        long oldcount;
-#ifndef CONFIG_SMP
-        oldcount = sem->count;
-        sem->count -= RWSEM_WAITING_BIAS;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%3,%2\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        "       mb\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (oldcount), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (-RWSEM_WAITING_BIAS), "m" (sem->count) : "memory");
-#endif
-        if (unlikely(oldcount < 0))
-                rwsem_downgrade_wake(sem);
-}
-
-static inline void rwsem_atomic_add(long val, struct rw_semaphore *sem)
-{
-#ifndef CONFIG_SMP
-        sem->count += val;
-#else
-        long temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%2,%0\n"
-        "       stq_c   %0,%1\n"
-        "       beq     %0,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (temp), "=m" (sem->count)
-        :"Ir" (val), "m" (sem->count));
-#endif
-}
-
-static inline long rwsem_atomic_update(long val, struct rw_semaphore *sem)
-{
-#ifndef CONFIG_SMP
-        sem->count += val;
-        return sem->count;
-#else
-        long ret, temp;
-        __asm__ __volatile__(
-        "1:     ldq_l   %0,%1\n"
-        "       addq    %0,%3,%2\n"
-        "       addq    %0,%3,%0\n"
-        "       stq_c   %2,%1\n"
-        "       beq     %2,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        :"=&r" (ret), "=m" (sem->count), "=&r" (temp)
-        :"Ir" (val), "m" (sem->count));
-
-        return ret;
-#endif
-}
-
-static inline int rwsem_is_locked(struct rw_semaphore *sem)
-{
-        return (sem->count != 0);
-}
-
-#endif /* __KERNEL__ */
-#endif /* _ALPHA_RWSEM_H */
diff --git a/include/asm-alpha/scatterlist.h b/include/asm-alpha/scatterlist.h
deleted file mode 100644
index 440747ca6349..000000000000
--- a/include/asm-alpha/scatterlist.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ALPHA_SCATTERLIST_H
-#define _ALPHA_SCATTERLIST_H
-
-#include <asm/page.h>
-#include <asm/types.h>
-  
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long sg_magic;
-#endif
-        unsigned long page_link;
-        unsigned int offset;
-
-        unsigned int length;
-
-        dma_addr_t dma_address;
-        __u32 dma_length;
-};
-
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->dma_length)
-
-#define ISA_DMA_THRESHOLD (~0UL)
-
-#endif /* !(_ALPHA_SCATTERLIST_H) */
diff --git a/include/asm-alpha/sections.h b/include/asm-alpha/sections.h
deleted file mode 100644
index 43b40edd6e44..000000000000
--- a/include/asm-alpha/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _ALPHA_SECTIONS_H
-#define _ALPHA_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/include/asm-alpha/segment.h b/include/asm-alpha/segment.h
deleted file mode 100644
index 0453d97daae7..000000000000
--- a/include/asm-alpha/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ALPHA_SEGMENT_H
-#define __ALPHA_SEGMENT_H
-
-/* Only here because we have some old header files that expect it.. */
-
-#endif
diff --git a/include/asm-alpha/sembuf.h b/include/asm-alpha/sembuf.h
deleted file mode 100644
index 7b38b1534784..000000000000
--- a/include/asm-alpha/sembuf.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ALPHA_SEMBUF_H
-#define _ALPHA_SEMBUF_H
-
-/* 
- * The semid64_ds structure for alpha architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 2 miscellaneous 64-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;              /* last semop time */
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-};
-
-#endif /* _ALPHA_SEMBUF_H */
diff --git a/include/asm-alpha/serial.h b/include/asm-alpha/serial.h
deleted file mode 100644
index 9d263e8d8ccc..000000000000
--- a/include/asm-alpha/serial.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * include/asm-alpha/serial.h
- */
-
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD ( 1843200 / 16 )
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-
-#define SERIAL_PORT_DFNS                        \
-        /* UART CLK   PORT IRQ     FLAGS        */                      \
-        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
-        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
-        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
-        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
diff --git a/include/asm-alpha/setup.h b/include/asm-alpha/setup.h
deleted file mode 100644
index 2e023a4aa317..000000000000
--- a/include/asm-alpha/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ALPHA_SETUP_H
-#define __ALPHA_SETUP_H
-
-#define COMMAND_LINE_SIZE       256
-
-#endif
diff --git a/include/asm-alpha/sfp-machine.h b/include/asm-alpha/sfp-machine.h
deleted file mode 100644
index 5fe63afbd474..000000000000
--- a/include/asm-alpha/sfp-machine.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Machine-dependent software floating-point definitions.
-   Alpha kernel version.
-   Copyright (C) 1997,1998,1999 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-   Contributed by Richard Henderson (rth@cygnus.com),
-                  Jakub Jelinek (jakub@redhat.com) and
-                  David S. Miller (davem@redhat.com).
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Library General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Library General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If
-   not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-#ifndef _SFP_MACHINE_H
-#define _SFP_MACHINE_H
-   
-#define _FP_W_TYPE_SIZE         64
-#define _FP_W_TYPE              unsigned long
-#define _FP_WS_TYPE             signed long
-#define _FP_I_TYPE              long
-
-#define _FP_MUL_MEAT_S(R,X,Y)                                   \
-  _FP_MUL_MEAT_1_imm(_FP_WFRACBITS_S,R,X,Y)
-#define _FP_MUL_MEAT_D(R,X,Y)                                   \
-  _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
-#define _FP_MUL_MEAT_Q(R,X,Y)                                   \
-  _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
-
-#define _FP_DIV_MEAT_S(R,X,Y)   _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
-#define _FP_DIV_MEAT_D(R,X,Y)   _FP_DIV_MEAT_1_udiv(D,R,X,Y)
-#define _FP_DIV_MEAT_Q(R,X,Y)   _FP_DIV_MEAT_2_udiv(Q,R,X,Y)
-
-#define _FP_NANFRAC_S           _FP_QNANBIT_S
-#define _FP_NANFRAC_D           _FP_QNANBIT_D
-#define _FP_NANFRAC_Q           _FP_QNANBIT_Q
-#define _FP_NANSIGN_S           1
-#define _FP_NANSIGN_D           1
-#define _FP_NANSIGN_Q           1
-
-#define _FP_KEEPNANFRACP 1
-
-/* Alpha Architecture Handbook, 4.7.10.4 sais that
- * we should prefer any type of NaN in Fb, then Fa.
- */
-#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP)                      \
-  do {                                                          \
-    R##_s = Y##_s;                                              \
-    _FP_FRAC_COPY_##wc(R,X);                                    \
-    R##_c = FP_CLS_NAN;                                         \
-  } while (0)
-
-/* Obtain the current rounding mode. */
-#define FP_ROUNDMODE    mode
-#define FP_RND_NEAREST  (FPCR_DYN_NORMAL >> FPCR_DYN_SHIFT)
-#define FP_RND_ZERO     (FPCR_DYN_CHOPPED >> FPCR_DYN_SHIFT)
-#define FP_RND_PINF     (FPCR_DYN_PLUS >> FPCR_DYN_SHIFT)
-#define FP_RND_MINF     (FPCR_DYN_MINUS >> FPCR_DYN_SHIFT)
-
-/* Exception flags. */
-#define FP_EX_INVALID           IEEE_TRAP_ENABLE_INV
-#define FP_EX_OVERFLOW          IEEE_TRAP_ENABLE_OVF
-#define FP_EX_UNDERFLOW         IEEE_TRAP_ENABLE_UNF
-#define FP_EX_DIVZERO           IEEE_TRAP_ENABLE_DZE
-#define FP_EX_INEXACT           IEEE_TRAP_ENABLE_INE
-#define FP_EX_DENORM            IEEE_TRAP_ENABLE_DNO
-
-#define FP_DENORM_ZERO          (swcr & IEEE_MAP_DMZ)
-
-/* We write the results always */
-#define FP_INHIBIT_RESULTS 0
-
-#endif
diff --git a/include/asm-alpha/shmbuf.h b/include/asm-alpha/shmbuf.h
deleted file mode 100644
index 37ee84f05085..000000000000
--- a/include/asm-alpha/shmbuf.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef _ALPHA_SHMBUF_H
-#define _ALPHA_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for alpha architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 2 miscellaneous 64-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-        __kernel_time_t         shm_dtime;      /* last detach time */
-        __kernel_time_t         shm_ctime;      /* last change time */
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused1;
-        unsigned long           __unused2;
-};
-
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ALPHA_SHMBUF_H */
diff --git a/include/asm-alpha/shmparam.h b/include/asm-alpha/shmparam.h
deleted file mode 100644
index cc901d58aebb..000000000000
--- a/include/asm-alpha/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASMAXP_SHMPARAM_H
-#define _ASMAXP_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
-
-#endif /* _ASMAXP_SHMPARAM_H */
diff --git a/include/asm-alpha/sigcontext.h b/include/asm-alpha/sigcontext.h
deleted file mode 100644
index 323cdb026198..000000000000
--- a/include/asm-alpha/sigcontext.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef _ASMAXP_SIGCONTEXT_H
-#define _ASMAXP_SIGCONTEXT_H
-
-struct sigcontext {
-        /*
-         * What should we have here? I'd probably better use the same
-         * stack layout as OSF/1, just in case we ever want to try
-         * running their binaries.. 
-         *
-         * This is the basic layout, but I don't know if we'll ever
-         * actually fill in all the values..
-         */
-         long           sc_onstack;
-         long           sc_mask;
-         long           sc_pc;
-         long           sc_ps;
-         long           sc_regs[32];
-         long           sc_ownedfp;
-         long           sc_fpregs[32];
-         unsigned long  sc_fpcr;
-         unsigned long  sc_fp_control;
-         unsigned long  sc_reserved1, sc_reserved2;
-         unsigned long  sc_ssize;
-         char *         sc_sbase;
-         unsigned long  sc_traparg_a0;
-         unsigned long  sc_traparg_a1;
-         unsigned long  sc_traparg_a2;
-         unsigned long  sc_fp_trap_pc;
-         unsigned long  sc_fp_trigger_sum;
-         unsigned long  sc_fp_trigger_inst;
-};
-
-
-#endif
diff --git a/include/asm-alpha/siginfo.h b/include/asm-alpha/siginfo.h
deleted file mode 100644
index 9822362a8424..000000000000
--- a/include/asm-alpha/siginfo.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef _ALPHA_SIGINFO_H
-#define _ALPHA_SIGINFO_H
-
-#define __ARCH_SI_PREAMBLE_SIZE         (4 * sizeof(int))
-#define __ARCH_SI_TRAPNO
-
-#include <asm-generic/siginfo.h>
-
-#endif
diff --git a/include/asm-alpha/signal.h b/include/asm-alpha/signal.h
deleted file mode 100644
index 13c2305d35ef..000000000000
--- a/include/asm-alpha/signal.h
+++ /dev/null
@@ -1,172 +0,0 @@
-#ifndef _ASMAXP_SIGNAL_H
-#define _ASMAXP_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-/* Digital Unix defines 64 signals.  Most things should be clean enough
-   to redefine this at will, if care is taken to make libc match.  */
-
-#define _NSIG           64
-#define _NSIG_BPW       64
-#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;             /* at least 32 bits */
-
-typedef struct {
-        unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG            32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-
-/*
- * Linux/AXP has different signal numbers that Linux/i386: I'm trying
- * to make it OSF/1 binary compatible, at least for normal binaries.
- */
-#define SIGHUP           1
-#define SIGINT           2
-#define SIGQUIT          3
-#define SIGILL           4
-#define SIGTRAP          5
-#define SIGABRT          6
-#define SIGEMT           7
-#define SIGFPE           8
-#define SIGKILL          9
-#define SIGBUS          10
-#define SIGSEGV         11
-#define SIGSYS          12
-#define SIGPIPE         13
-#define SIGALRM         14
-#define SIGTERM         15
-#define SIGURG          16
-#define SIGSTOP         17
-#define SIGTSTP         18
-#define SIGCONT         19
-#define SIGCHLD         20
-#define SIGTTIN         21
-#define SIGTTOU         22
-#define SIGIO           23
-#define SIGXCPU         24
-#define SIGXFSZ         25
-#define SIGVTALRM       26
-#define SIGPROF         27
-#define SIGWINCH        28
-#define SIGINFO         29
-#define SIGUSR1         30
-#define SIGUSR2         31
-
-#define SIGPOLL SIGIO
-#define SIGPWR  SIGINFO
-#define SIGIOT  SIGABRT
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-
-#define SA_ONSTACK      0x00000001
-#define SA_RESTART      0x00000002
-#define SA_NOCLDSTOP    0x00000004
-#define SA_NODEFER      0x00000008
-#define SA_RESETHAND    0x00000010
-#define SA_NOCLDWAIT    0x00000020
-#define SA_SIGINFO      0x00000040
-
-#define SA_ONESHOT      SA_RESETHAND
-#define SA_NOMASK       SA_NODEFER
-
-/* 
- * sigaltstack controls
- */
-#define SS_ONSTACK      1
-#define SS_DISABLE      2
-
-#define MINSIGSTKSZ     4096
-#define SIGSTKSZ        16384
-
-#define SIG_BLOCK          1    /* for blocking signals */
-#define SIG_UNBLOCK        2    /* for unblocking signals */
-#define SIG_SETMASK        3    /* for setting the signal mask */
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct osf_sigaction {
-        __sighandler_t  sa_handler;
-        old_sigset_t    sa_mask;
-        int             sa_flags;
-};
-
-struct sigaction {
-        __sighandler_t  sa_handler;
-        unsigned long   sa_flags;
-        sigset_t        sa_mask;        /* mask last for extensibility */
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-        __sigrestore_t ka_restorer;
-};
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-        union {
-          __sighandler_t        _sa_handler;
-          void (*_sa_sigaction)(int, struct siginfo *, void *);
-        } _u;
-        sigset_t        sa_mask;
-        int             sa_flags;
-};
-
-#define sa_handler      _u._sa_handler
-#define sa_sigaction    _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
-        void __user *ss_sp;
-        int ss_flags;
-        size_t ss_size;
-} stack_t;
-
-/* sigstack(2) is deprecated, and will be withdrawn in a future version
-   of the X/Open CAE Specification.  Use sigaltstack instead.  It is only
-   implemented here for OSF/1 compatibility.  */
-
-struct sigstack {
-        void __user *ss_sp;
-        int ss_onstack;
-};
-
-#ifdef __KERNEL__
-#include <asm/sigcontext.h>
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif
-
-#endif
diff --git a/include/asm-alpha/smp.h b/include/asm-alpha/smp.h
deleted file mode 100644
index 544c69af8168..000000000000
--- a/include/asm-alpha/smp.h
+++ /dev/null
@@ -1,62 +0,0 @@
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-#include <linux/bitops.h>
-#include <asm/pal.h>
-
-/* HACK: Cabrio WHAMI return value is bogus if more than 8 bits used.. :-( */
-
-static __inline__ unsigned char
-__hard_smp_processor_id(void)
-{
-        register unsigned char __r0 __asm__("$0");
-        __asm__ __volatile__(
-                "call_pal %1 #whami"
-                : "=r"(__r0)
-                :"i" (PAL_whami)
-                : "$1", "$22", "$23", "$24", "$25");
-        return __r0;
-}
-
-#ifdef CONFIG_SMP
-
-#include <asm/irq.h>
-
-struct cpuinfo_alpha {
-        unsigned long loops_per_jiffy;
-        unsigned long last_asn;
-        int need_new_asn;
-        int asn_lock;
-        unsigned long ipi_count;
-        unsigned long prof_multiplier;
-        unsigned long prof_counter;
-        unsigned char mcheck_expected;
-        unsigned char mcheck_taken;
-        unsigned char mcheck_extra;
-} __attribute__((aligned(64)));
-
-extern struct cpuinfo_alpha cpu_data[NR_CPUS];
-
-#define PROC_CHANGE_PENALTY     20
-
-#define hard_smp_processor_id() __hard_smp_processor_id()
-#define raw_smp_processor_id()  (current_thread_info()->cpu)
-
-extern int smp_num_cpus;
-#define cpu_possible_map        cpu_present_map
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi(cpumask_t mask);
-
-#else /* CONFIG_SMP */
-
-#define hard_smp_processor_id()         0
-#define smp_call_function_on_cpu(func,info,wait,cpu)    ({ 0; })
-
-#endif /* CONFIG_SMP */
-
-#define NO_PROC_ID      (-1)
-
-#endif
diff --git a/include/asm-alpha/socket.h b/include/asm-alpha/socket.h
deleted file mode 100644
index a1057c2d95e7..000000000000
--- a/include/asm-alpha/socket.h
+++ /dev/null
@@ -1,70 +0,0 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockopt(2) */
-/*
- * Note: we only bother about making the SOL_SOCKET options
- * same as OSF/1, as that's all that "normal" programs are
- * likely to set.  We don't necessarily want to be binary
- * compatible with _everything_. 
- */
-#define SOL_SOCKET      0xffff
-
-#define SO_DEBUG        0x0001
-#define SO_REUSEADDR    0x0004
-#define SO_KEEPALIVE    0x0008
-#define SO_DONTROUTE    0x0010
-#define SO_BROADCAST    0x0020
-#define SO_LINGER       0x0080
-#define SO_OOBINLINE    0x0100
-/* To add :#define SO_REUSEPORT 0x0200 */
-
-#define SO_TYPE         0x1008
-#define SO_ERROR        0x1007
-#define SO_SNDBUF       0x1001
-#define SO_RCVBUF       0x1002
-#define SO_SNDBUFFORCE  0x100a
-#define SO_RCVBUFFORCE  0x100b
-#define SO_RCVLOWAT     0x1010
-#define SO_SNDLOWAT     0x1011
-#define SO_RCVTIMEO     0x1012
-#define SO_SNDTIMEO     0x1013
-#define SO_ACCEPTCONN   0x1014
-
-/* linux-specific, might as well be the same as on i386 */
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_BSDCOMPAT    14
-
-#define SO_PASSCRED     17
-#define SO_PEERCRED     18
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_PEERSEC              30
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              19
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        20
-#define SO_SECURITY_ENCRYPTION_NETWORK          21
-
-#define SO_MARK                 36
-
-/* O_NONBLOCK clashes with the bits used for socket types.  Therefore we
- * have to define SOCK_NONBLOCK to a different value here.
- */
-#define SOCK_NONBLOCK   0x40000000
-
-#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-alpha/sockios.h b/include/asm-alpha/sockios.h
deleted file mode 100644
index 7932c7ab4a4d..000000000000
--- a/include/asm-alpha/sockios.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _ASM_ALPHA_SOCKIOS_H
-#define _ASM_ALPHA_SOCKIOS_H
-
-/* Socket-level I/O control calls. */
-
-#define FIOGETOWN       _IOR('f', 123, int)
-#define FIOSETOWN       _IOW('f', 124, int)
-
-#define SIOCATMARK      _IOR('s', 7, int)
-#define SIOCSPGRP       _IOW('s', 8, pid_t)
-#define SIOCGPGRP       _IOR('s', 9, pid_t)
-
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-
-#endif /* _ASM_ALPHA_SOCKIOS_H */
diff --git a/include/asm-alpha/spinlock.h b/include/asm-alpha/spinlock.h
deleted file mode 100644
index aeeb125f6851..000000000000
--- a/include/asm-alpha/spinlock.h
+++ /dev/null
@@ -1,173 +0,0 @@
-#ifndef _ALPHA_SPINLOCK_H
-#define _ALPHA_SPINLOCK_H
-
-#include <asm/system.h>
-#include <linux/kernel.h>
-#include <asm/current.h>
-
-/*
- * Simple spin lock operations.  There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * We make no fairness assumptions. They have a cost.
- */
-
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_spin_is_locked(x) ((x)->lock != 0)
-#define __raw_spin_unlock_wait(x) \
-                do { cpu_relax(); } while ((x)->lock)
-
-static inline void __raw_spin_unlock(raw_spinlock_t * lock)
-{
-        mb();
-        lock->lock = 0;
-}
-
-static inline void __raw_spin_lock(raw_spinlock_t * lock)
-{
-        long tmp;
-
-        __asm__ __volatile__(
-        "1:     ldl_l   %0,%1\n"
-        "       bne     %0,2f\n"
-        "       lda     %0,1\n"
-        "       stl_c   %0,%1\n"
-        "       beq     %0,2f\n"
-        "       mb\n"
-        ".subsection 2\n"
-        "2:     ldl     %0,%1\n"
-        "       bne     %0,2b\n"
-        "       br      1b\n"
-        ".previous"
-        : "=&r" (tmp), "=m" (lock->lock)
-        : "m"(lock->lock) : "memory");
-}
-
-static inline int __raw_spin_trylock(raw_spinlock_t *lock)
-{
-        return !test_and_set_bit(0, &lock->lock);
-}
-
-/***********************************************************/
-
-static inline int __raw_read_can_lock(raw_rwlock_t *lock)
-{
-        return (lock->lock & 1) == 0;
-}
-
-static inline int __raw_write_can_lock(raw_rwlock_t *lock)
-{
-        return lock->lock == 0;
-}
-
-static inline void __raw_read_lock(raw_rwlock_t *lock)
-{
-        long regx;
-
-        __asm__ __volatile__(
-        "1:     ldl_l   %1,%0\n"
-        "       blbs    %1,6f\n"
-        "       subl    %1,2,%1\n"
-        "       stl_c   %1,%0\n"
-        "       beq     %1,6f\n"
-        "       mb\n"
-        ".subsection 2\n"
-        "6:     ldl     %1,%0\n"
-        "       blbs    %1,6b\n"
-        "       br      1b\n"
-        ".previous"
-        : "=m" (*lock), "=&r" (regx)
-        : "m" (*lock) : "memory");
-}
-
-static inline void __raw_write_lock(raw_rwlock_t *lock)
-{
-        long regx;
-
-        __asm__ __volatile__(
-        "1:     ldl_l   %1,%0\n"
-        "       bne     %1,6f\n"
-        "       lda     %1,1\n"
-        "       stl_c   %1,%0\n"
-        "       beq     %1,6f\n"
-        "       mb\n"
-        ".subsection 2\n"
-        "6:     ldl     %1,%0\n"
-        "       bne     %1,6b\n"
-        "       br      1b\n"
-        ".previous"
-        : "=m" (*lock), "=&r" (regx)
-        : "m" (*lock) : "memory");
-}
-
-static inline int __raw_read_trylock(raw_rwlock_t * lock)
-{
-        long regx;
-        int success;
-
-        __asm__ __volatile__(
-        "1:     ldl_l   %1,%0\n"
-        "       lda     %2,0\n"
-        "       blbs    %1,2f\n"
-        "       subl    %1,2,%2\n"
-        "       stl_c   %2,%0\n"
-        "       beq     %2,6f\n"
-        "2:     mb\n"
-        ".subsection 2\n"
-        "6:     br      1b\n"
-        ".previous"
-        : "=m" (*lock), "=&r" (regx), "=&r" (success)
-        : "m" (*lock) : "memory");
-
-        return success;
-}
-
-static inline int __raw_write_trylock(raw_rwlock_t * lock)
-{
-        long regx;
-        int success;
-
-        __asm__ __volatile__(
-        "1:     ldl_l   %1,%0\n"
-        "       lda     %2,0\n"
-        "       bne     %1,2f\n"
-        "       lda     %2,1\n"
-        "       stl_c   %2,%0\n"
-        "       beq     %2,6f\n"
-        "2:     mb\n"
-        ".subsection 2\n"
-        "6:     br      1b\n"
-        ".previous"
-        : "=m" (*lock), "=&r" (regx), "=&r" (success)
-        : "m" (*lock) : "memory");
-
-        return success;
-}
-
-static inline void __raw_read_unlock(raw_rwlock_t * lock)
-{
-        long regx;
-        __asm__ __volatile__(
-        "       mb\n"
-        "1:     ldl_l   %1,%0\n"
-        "       addl    %1,2,%1\n"
-        "       stl_c   %1,%0\n"
-        "       beq     %1,6f\n"
-        ".subsection 2\n"
-        "6:     br      1b\n"
-        ".previous"
-        : "=m" (*lock), "=&r" (regx)
-        : "m" (*lock) : "memory");
-}
-
-static inline void __raw_write_unlock(raw_rwlock_t * lock)
-{
-        mb();
-        lock->lock = 0;
-}
-
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
-
-#endif /* _ALPHA_SPINLOCK_H */
diff --git a/include/asm-alpha/spinlock_types.h b/include/asm-alpha/spinlock_types.h
deleted file mode 100644
index 8141eb5ebf0d..000000000000
--- a/include/asm-alpha/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ALPHA_SPINLOCK_TYPES_H
-#define _ALPHA_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
-        volatile unsigned int lock;
-} raw_spinlock_t;
-
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
-
-typedef struct {
-        volatile unsigned int lock;
-} raw_rwlock_t;
-
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
-
-#endif
diff --git a/include/asm-alpha/stat.h b/include/asm-alpha/stat.h
deleted file mode 100644
index 07ad3e6b3f3e..000000000000
--- a/include/asm-alpha/stat.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef _ALPHA_STAT_H
-#define _ALPHA_STAT_H
-
-struct stat {
-        unsigned int    st_dev;
-        unsigned int    st_ino;
-        unsigned int    st_mode;
-        unsigned int    st_nlink;
-        unsigned int    st_uid;
-        unsigned int    st_gid;
-        unsigned int    st_rdev;
-        long            st_size;
-        unsigned long   st_atime;
-        unsigned long   st_mtime;
-        unsigned long   st_ctime;
-        unsigned int    st_blksize;
-        unsigned int    st_blocks;
-        unsigned int    st_flags;
-        unsigned int    st_gen;
-};
-
-/* The stat64 structure increases the size of dev_t, blkcnt_t, adds
-   nanosecond resolution times, and padding for expansion.  */
-
-struct stat64 {
-        unsigned long   st_dev;
-        unsigned long   st_ino;
-        unsigned long   st_rdev;
-        long            st_size;
-        unsigned long   st_blocks;
-
-        unsigned int    st_mode;
-        unsigned int    st_uid;
-        unsigned int    st_gid;
-        unsigned int    st_blksize;
-        unsigned int    st_nlink;
-        unsigned int    __pad0;
-
-        unsigned long   st_atime;
-        unsigned long   st_atime_nsec; 
-        unsigned long   st_mtime;
-        unsigned long   st_mtime_nsec;
-        unsigned long   st_ctime;
-        unsigned long   st_ctime_nsec;
-        long            __unused[3];
-};
-
-#endif
diff --git a/include/asm-alpha/statfs.h b/include/asm-alpha/statfs.h
deleted file mode 100644
index ad15830baefe..000000000000
--- a/include/asm-alpha/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ALPHA_STATFS_H
-#define _ALPHA_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif
diff --git a/include/asm-alpha/string.h b/include/asm-alpha/string.h
deleted file mode 100644
index b02b8a282940..000000000000
--- a/include/asm-alpha/string.h
+++ /dev/null
@@ -1,66 +0,0 @@
-#ifndef __ALPHA_STRING_H__
-#define __ALPHA_STRING_H__
-
-#ifdef __KERNEL__
-
-/*
- * GCC of any recent vintage doesn't do stupid things with bcopy.
- * EGCS 1.1 knows all about expanding memcpy inline, others don't.
- *
- * Similarly for a memset with data = 0.
- */
-
-#define __HAVE_ARCH_MEMCPY
-extern void * memcpy(void *, const void *, size_t);
-#define __HAVE_ARCH_MEMMOVE
-extern void * memmove(void *, const void *, size_t);
-
-/* For backward compatibility with modules.  Unused otherwise.  */
-extern void * __memcpy(void *, const void *, size_t);
-
-#define memcpy __builtin_memcpy
-
-#define __HAVE_ARCH_MEMSET
-extern void * __constant_c_memset(void *, unsigned long, size_t);
-extern void * __memset(void *, int, size_t);
-extern void * memset(void *, int, size_t);
-
-#define memset(s, c, n)                                                     \
-(__builtin_constant_p(c)                                                    \
- ? (__builtin_constant_p(n) && (c) == 0                                     \
-    ? __builtin_memset((s),0,(n))                                           \
-    : __constant_c_memset((s),0x0101010101010101UL*(unsigned char)(c),(n))) \
- : __memset((s),(c),(n)))
-
-#define __HAVE_ARCH_STRCPY
-extern char * strcpy(char *,const char *);
-#define __HAVE_ARCH_STRNCPY
-extern char * strncpy(char *, const char *, size_t);
-#define __HAVE_ARCH_STRCAT
-extern char * strcat(char *, const char *);
-#define __HAVE_ARCH_STRNCAT
-extern char * strncat(char *, const char *, size_t);
-#define __HAVE_ARCH_STRCHR
-extern char * strchr(const char *,int);
-#define __HAVE_ARCH_STRRCHR
-extern char * strrchr(const char *,int);
-#define __HAVE_ARCH_STRLEN
-extern size_t strlen(const char *);
-#define __HAVE_ARCH_MEMCHR
-extern void * memchr(const void *, int, size_t);
-
-/* The following routine is like memset except that it writes 16-bit
-   aligned values.  The DEST and COUNT parameters must be even for 
-   correct operation.  */
-
-#define __HAVE_ARCH_MEMSETW
-extern void * __memsetw(void *dest, unsigned short, size_t count);
-
-#define memsetw(s, c, n)                                                 \
-(__builtin_constant_p(c)                                                 \
- ? __constant_c_memset((s),0x0001000100010001UL*(unsigned short)(c),(n)) \
- : __memsetw((s),(c),(n)))
-
-#endif /* __KERNEL__ */
-
-#endif /* __ALPHA_STRING_H__ */
diff --git a/include/asm-alpha/suspend.h b/include/asm-alpha/suspend.h
deleted file mode 100644
index c7042d575851..000000000000
--- a/include/asm-alpha/suspend.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ALPHA_SUSPEND_H
-#define __ALPHA_SUSPEND_H
-
-/* Dummy include. */
-
-#endif  /* __ALPHA_SUSPEND_H */
diff --git a/include/asm-alpha/sysinfo.h b/include/asm-alpha/sysinfo.h
deleted file mode 100644
index 086aba284df2..000000000000
--- a/include/asm-alpha/sysinfo.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * include/asm-alpha/sysinfo.h
- */
-
-#ifndef __ASM_ALPHA_SYSINFO_H
-#define __ASM_ALPHA_SYSINFO_H
-
-/* This defines the subset of the OSF/1 getsysinfo/setsysinfo calls
-   that we support.  */
-
-#define GSI_UACPROC                     8
-#define GSI_IEEE_FP_CONTROL             45
-#define GSI_IEEE_STATE_AT_SIGNAL        46
-#define GSI_PROC_TYPE                   60
-#define GSI_GET_HWRPB                   101
-
-#define SSI_NVPAIRS                     1
-#define SSI_IEEE_FP_CONTROL             14
-#define SSI_IEEE_STATE_AT_SIGNAL        15
-#define SSI_IEEE_IGNORE_STATE_AT_SIGNAL 16
-#define SSI_IEEE_RAISE_EXCEPTION        1001    /* linux specific */
-
-#define SSIN_UACPROC                    6
-
-#define UAC_BITMASK                     7
-#define UAC_NOPRINT                     1
-#define UAC_NOFIX                       2
-#define UAC_SIGBUS                      4
-
-
-#ifdef __KERNEL__
-
-/* This is the shift that is applied to the UAC bits as stored in the
-   per-thread flags.  See thread_info.h.  */
-#define UAC_SHIFT                       6
-
-#endif
-
-#endif /* __ASM_ALPHA_SYSINFO_H */
diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h
deleted file mode 100644
index afe20fa58c99..000000000000
--- a/include/asm-alpha/system.h
+++ /dev/null
@@ -1,829 +0,0 @@
-#ifndef __ALPHA_SYSTEM_H
-#define __ALPHA_SYSTEM_H
-
-#include <asm/pal.h>
-#include <asm/page.h>
-#include <asm/barrier.h>
-
-/*
- * System defines.. Note that this is included both from .c and .S
- * files, so it does only defines, not any C code.
- */
-
-/*
- * We leave one page for the initial stack page, and one page for
- * the initial process structure. Also, the console eats 3 MB for
- * the initial bootloader (one of which we can reclaim later).
- */
-#define BOOT_PCB        0x20000000
-#define BOOT_ADDR       0x20000000
-/* Remove when official MILO sources have ELF support: */
-#define BOOT_SIZE       (16*1024)
-
-#ifdef CONFIG_ALPHA_LEGACY_START_ADDRESS
-#define KERNEL_START_PHYS       0x300000 /* Old bootloaders hardcoded this.  */
-#else
-#define KERNEL_START_PHYS       0x1000000 /* required: Wildfire/Titan/Marvel */
-#endif
-
-#define KERNEL_START    (PAGE_OFFSET+KERNEL_START_PHYS)
-#define SWAPPER_PGD     KERNEL_START
-#define INIT_STACK      (PAGE_OFFSET+KERNEL_START_PHYS+0x02000)
-#define EMPTY_PGT       (PAGE_OFFSET+KERNEL_START_PHYS+0x04000)
-#define EMPTY_PGE       (PAGE_OFFSET+KERNEL_START_PHYS+0x08000)
-#define ZERO_PGE        (PAGE_OFFSET+KERNEL_START_PHYS+0x0A000)
-
-#define START_ADDR      (PAGE_OFFSET+KERNEL_START_PHYS+0x10000)
-
-/*
- * This is setup by the secondary bootstrap loader.  Because
- * the zero page is zeroed out as soon as the vm system is
- * initialized, we need to copy things out into a more permanent
- * place.
- */
-#define PARAM                   ZERO_PGE
-#define COMMAND_LINE            ((char*)(PARAM + 0x0000))
-#define INITRD_START            (*(unsigned long *) (PARAM+0x100))
-#define INITRD_SIZE             (*(unsigned long *) (PARAM+0x108))
-
-#ifndef __ASSEMBLY__
-#include <linux/kernel.h>
-#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */
-
-/*
- * This is the logout header that should be common to all platforms
- * (assuming they are running OSF/1 PALcode, I guess).
- */
-struct el_common {
-        unsigned int    size;           /* size in bytes of logout area */
-        unsigned int    sbz1    : 30;   /* should be zero */
-        unsigned int    err2    :  1;   /* second error */
-        unsigned int    retry   :  1;   /* retry flag */
-        unsigned int    proc_offset;    /* processor-specific offset */
-        unsigned int    sys_offset;     /* system-specific offset */
-        unsigned int    code;           /* machine check code */
-        unsigned int    frame_rev;      /* frame revision */
-};
-
-/* Machine Check Frame for uncorrectable errors (Large format)
- *      --- This is used to log uncorrectable errors such as
- *          double bit ECC errors.
- *      --- These errors are detected by both processor and systems.
- */
-struct el_common_EV5_uncorrectable_mcheck {
-        unsigned long   shadow[8];        /* Shadow reg. 8-14, 25           */
-        unsigned long   paltemp[24];      /* PAL TEMP REGS.                 */
-        unsigned long   exc_addr;         /* Address of excepting instruction*/
-        unsigned long   exc_sum;          /* Summary of arithmetic traps.   */
-        unsigned long   exc_mask;         /* Exception mask (from exc_sum). */
-        unsigned long   pal_base;         /* Base address for PALcode.      */
-        unsigned long   isr;              /* Interrupt Status Reg.          */
-        unsigned long   icsr;             /* CURRENT SETUP OF EV5 IBOX      */
-        unsigned long   ic_perr_stat;     /* I-CACHE Reg. <11> set Data parity
-                                                         <12> set TAG parity*/
-        unsigned long   dc_perr_stat;     /* D-CACHE error Reg. Bits set to 1:
-                                                     <2> Data error in bank 0
-                                                     <3> Data error in bank 1
-                                                     <4> Tag error in bank 0
-                                                     <5> Tag error in bank 1 */
-        unsigned long   va;               /* Effective VA of fault or miss. */
-        unsigned long   mm_stat;          /* Holds the reason for D-stream 
-                                             fault or D-cache parity errors */
-        unsigned long   sc_addr;          /* Address that was being accessed
-                                             when EV5 detected Secondary cache
-                                             failure.                 */
-        unsigned long   sc_stat;          /* Helps determine if the error was
-                                             TAG/Data parity(Secondary Cache)*/
-        unsigned long   bc_tag_addr;      /* Contents of EV5 BC_TAG_ADDR    */
-        unsigned long   ei_addr;          /* Physical address of any transfer
-                                             that is logged in EV5 EI_STAT */
-        unsigned long   fill_syndrome;    /* For correcting ECC errors.     */
-        unsigned long   ei_stat;          /* Helps identify reason of any 
-                                             processor uncorrectable error
-                                             at its external interface.     */
-        unsigned long   ld_lock;          /* Contents of EV5 LD_LOCK register*/
-};
-
-struct el_common_EV6_mcheck {
-        unsigned int FrameSize;         /* Bytes, including this field */
-        unsigned int FrameFlags;        /* <31> = Retry, <30> = Second Error */
-        unsigned int CpuOffset;         /* Offset to CPU-specific info */
-        unsigned int SystemOffset;      /* Offset to system-specific info */
-        unsigned int MCHK_Code;
-        unsigned int MCHK_Frame_Rev;
-        unsigned long I_STAT;           /* EV6 Internal Processor Registers */
-        unsigned long DC_STAT;          /* (See the 21264 Spec) */
-        unsigned long C_ADDR;
-        unsigned long DC1_SYNDROME;
-        unsigned long DC0_SYNDROME;
-        unsigned long C_STAT;
-        unsigned long C_STS;
-        unsigned long MM_STAT;
-        unsigned long EXC_ADDR;
-        unsigned long IER_CM;
-        unsigned long ISUM;
-        unsigned long RESERVED0;
-        unsigned long PAL_BASE;
-        unsigned long I_CTL;
-        unsigned long PCTX;
-};
-
-extern void halt(void) __attribute__((noreturn));
-#define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt))
-
-#define switch_to(P,N,L)                                                 \
-  do {                                                                   \
-    (L) = alpha_switch_to(virt_to_phys(&task_thread_info(N)->pcb), (P)); \
-    check_mmu_context();                                                 \
-  } while (0)
-
-struct task_struct;
-extern struct task_struct *alpha_switch_to(unsigned long, struct task_struct*);
-
-#define imb() \
-__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
-
-#define draina() \
-__asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory")
-
-enum implver_enum {
-        IMPLVER_EV4,
-        IMPLVER_EV5,
-        IMPLVER_EV6
-};
-
-#ifdef CONFIG_ALPHA_GENERIC
-#define implver()                               \
-({ unsigned long __implver;                     \
-   __asm__ ("implver %0" : "=r"(__implver));    \
-   (enum implver_enum) __implver; })
-#else
-/* Try to eliminate some dead code.  */
-#ifdef CONFIG_ALPHA_EV4
-#define implver() IMPLVER_EV4
-#endif
-#ifdef CONFIG_ALPHA_EV5
-#define implver() IMPLVER_EV5
-#endif
-#if defined(CONFIG_ALPHA_EV6)
-#define implver() IMPLVER_EV6
-#endif
-#endif
-
-enum amask_enum {
-        AMASK_BWX = (1UL << 0),
-        AMASK_FIX = (1UL << 1),
-        AMASK_CIX = (1UL << 2),
-        AMASK_MAX = (1UL << 8),
-        AMASK_PRECISE_TRAP = (1UL << 9),
-};
-
-#define amask(mask)                                             \
-({ unsigned long __amask, __input = (mask);                     \
-   __asm__ ("amask %1,%0" : "=r"(__amask) : "rI"(__input));     \
-   __amask; })
-
-#define __CALL_PAL_R0(NAME, TYPE)                               \
-extern inline TYPE NAME(void)                                   \
-{                                                               \
-        register TYPE __r0 __asm__("$0");                       \
-        __asm__ __volatile__(                                   \
-                "call_pal %1 # " #NAME                          \
-                :"=r" (__r0)                                    \
-                :"i" (PAL_ ## NAME)                             \
-                :"$1", "$16", "$22", "$23", "$24", "$25");      \
-        return __r0;                                            \
-}
-
-#define __CALL_PAL_W1(NAME, TYPE0)                              \
-extern inline void NAME(TYPE0 arg0)                             \
-{                                                               \
-        register TYPE0 __r16 __asm__("$16") = arg0;             \
-        __asm__ __volatile__(                                   \
-                "call_pal %1 # "#NAME                           \
-                : "=r"(__r16)                                   \
-                : "i"(PAL_ ## NAME), "0"(__r16)                 \
-                : "$1", "$22", "$23", "$24", "$25");            \
-}
-
-#define __CALL_PAL_W2(NAME, TYPE0, TYPE1)                       \
-extern inline void NAME(TYPE0 arg0, TYPE1 arg1)                 \
-{                                                               \
-        register TYPE0 __r16 __asm__("$16") = arg0;             \
-        register TYPE1 __r17 __asm__("$17") = arg1;             \
-        __asm__ __volatile__(                                   \
-                "call_pal %2 # "#NAME                           \
-                : "=r"(__r16), "=r"(__r17)                      \
-                : "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17)     \
-                : "$1", "$22", "$23", "$24", "$25");            \
-}
-
-#define __CALL_PAL_RW1(NAME, RTYPE, TYPE0)                      \
-extern inline RTYPE NAME(TYPE0 arg0)                            \
-{                                                               \
-        register RTYPE __r0 __asm__("$0");                      \
-        register TYPE0 __r16 __asm__("$16") = arg0;             \
-        __asm__ __volatile__(                                   \
-                "call_pal %2 # "#NAME                           \
-                : "=r"(__r16), "=r"(__r0)                       \
-                : "i"(PAL_ ## NAME), "0"(__r16)                 \
-                : "$1", "$22", "$23", "$24", "$25");            \
-        return __r0;                                            \
-}
-
-#define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1)               \
-extern inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1)                \
-{                                                               \
-        register RTYPE __r0 __asm__("$0");                      \
-        register TYPE0 __r16 __asm__("$16") = arg0;             \
-        register TYPE1 __r17 __asm__("$17") = arg1;             \
-        __asm__ __volatile__(                                   \
-                "call_pal %3 # "#NAME                           \
-                : "=r"(__r16), "=r"(__r17), "=r"(__r0)          \
-                : "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17)     \
-                : "$1", "$22", "$23", "$24", "$25");            \
-        return __r0;                                            \
-}
-
-__CALL_PAL_W1(cflush, unsigned long);
-__CALL_PAL_R0(rdmces, unsigned long);
-__CALL_PAL_R0(rdps, unsigned long);
-__CALL_PAL_R0(rdusp, unsigned long);
-__CALL_PAL_RW1(swpipl, unsigned long, unsigned long);
-__CALL_PAL_R0(whami, unsigned long);
-__CALL_PAL_W2(wrent, void*, unsigned long);
-__CALL_PAL_W1(wripir, unsigned long);
-__CALL_PAL_W1(wrkgp, unsigned long);
-__CALL_PAL_W1(wrmces, unsigned long);
-__CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
-__CALL_PAL_W1(wrusp, unsigned long);
-__CALL_PAL_W1(wrvptptr, unsigned long);
-
-#define IPL_MIN         0
-#define IPL_SW0         1
-#define IPL_SW1         2
-#define IPL_DEV0        3
-#define IPL_DEV1        4
-#define IPL_TIMER       5
-#define IPL_PERF        6
-#define IPL_POWERFAIL   6
-#define IPL_MCHECK      7
-#define IPL_MAX         7
-
-#ifdef CONFIG_ALPHA_BROKEN_IRQ_MASK
-#undef IPL_MIN
-#define IPL_MIN         __min_ipl
-extern int __min_ipl;
-#endif
-
-#define getipl()                (rdps() & 7)
-#define setipl(ipl)             ((void) swpipl(ipl))
-
-#define local_irq_disable()                     do { setipl(IPL_MAX); barrier(); } while(0)
-#define local_irq_enable()                      do { barrier(); setipl(IPL_MIN); } while(0)
-#define local_save_flags(flags) ((flags) = rdps())
-#define local_irq_save(flags)   do { (flags) = swpipl(IPL_MAX); barrier(); } while(0)
-#define local_irq_restore(flags)        do { barrier(); setipl(flags); barrier(); } while(0)
-
-#define irqs_disabled() (getipl() == IPL_MAX)
-
-/*
- * TB routines..
- */
-#define __tbi(nr,arg,arg1...)                                   \
-({                                                              \
-        register unsigned long __r16 __asm__("$16") = (nr);     \
-        register unsigned long __r17 __asm__("$17"); arg;       \
-        __asm__ __volatile__(                                   \
-                "call_pal %3 #__tbi"                            \
-                :"=r" (__r16),"=r" (__r17)                      \
-                :"0" (__r16),"i" (PAL_tbi) ,##arg1              \
-                :"$0", "$1", "$22", "$23", "$24", "$25");       \
-})
-
-#define tbi(x,y)        __tbi(x,__r17=(y),"1" (__r17))
-#define tbisi(x)        __tbi(1,__r17=(x),"1" (__r17))
-#define tbisd(x)        __tbi(2,__r17=(x),"1" (__r17))
-#define tbis(x)         __tbi(3,__r17=(x),"1" (__r17))
-#define tbiap()         __tbi(-1, /* no second argument */)
-#define tbia()          __tbi(-2, /* no second argument */)
-
-/*
- * Atomic exchange.
- * Since it can be used to implement critical sections
- * it must clobber "memory" (also for interrupts in UP).
- */
-
-static inline unsigned long
-__xchg_u8(volatile char *m, unsigned long val)
-{
-        unsigned long ret, tmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %4,7,%3\n"
-        "       insbl   %1,%4,%1\n"
-        "1:     ldq_l   %2,0(%3)\n"
-        "       extbl   %2,%4,%0\n"
-        "       mskbl   %2,%4,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%3)\n"
-        "       beq     %2,2f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
-        : "r" ((long)m), "1" (val) : "memory");
-
-        return ret;
-}
-
-static inline unsigned long
-__xchg_u16(volatile short *m, unsigned long val)
-{
-        unsigned long ret, tmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %4,7,%3\n"
-        "       inswl   %1,%4,%1\n"
-        "1:     ldq_l   %2,0(%3)\n"
-        "       extwl   %2,%4,%0\n"
-        "       mskwl   %2,%4,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%3)\n"
-        "       beq     %2,2f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
-        : "r" ((long)m), "1" (val) : "memory");
-
-        return ret;
-}
-
-static inline unsigned long
-__xchg_u32(volatile int *m, unsigned long val)
-{
-        unsigned long dummy;
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%4\n"
-        "       bis $31,%3,%1\n"
-        "       stl_c %1,%2\n"
-        "       beq %1,2f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        : "=&r" (val), "=&r" (dummy), "=m" (*m)
-        : "rI" (val), "m" (*m) : "memory");
-
-        return val;
-}
-
-static inline unsigned long
-__xchg_u64(volatile long *m, unsigned long val)
-{
-        unsigned long dummy;
-
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%4\n"
-        "       bis $31,%3,%1\n"
-        "       stq_c %1,%2\n"
-        "       beq %1,2f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        : "=&r" (val), "=&r" (dummy), "=m" (*m)
-        : "rI" (val), "m" (*m) : "memory");
-
-        return val;
-}
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid xchg().  */
-extern void __xchg_called_with_bad_pointer(void);
-
-#define __xchg(ptr, x, size) \
-({ \
-        unsigned long __xchg__res; \
-        volatile void *__xchg__ptr = (ptr); \
-        switch (size) { \
-                case 1: __xchg__res = __xchg_u8(__xchg__ptr, x); break; \
-                case 2: __xchg__res = __xchg_u16(__xchg__ptr, x); break; \
-                case 4: __xchg__res = __xchg_u32(__xchg__ptr, x); break; \
-                case 8: __xchg__res = __xchg_u64(__xchg__ptr, x); break; \
-                default: __xchg_called_with_bad_pointer(); __xchg__res = x; \
-        } \
-        __xchg__res; \
-})
-
-#define xchg(ptr,x)                                                          \
-  ({                                                                         \
-     __typeof__(*(ptr)) _x_ = (x);                                           \
-     (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
-  })
-
-static inline unsigned long
-__xchg_u8_local(volatile char *m, unsigned long val)
-{
-        unsigned long ret, tmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %4,7,%3\n"
-        "       insbl   %1,%4,%1\n"
-        "1:     ldq_l   %2,0(%3)\n"
-        "       extbl   %2,%4,%0\n"
-        "       mskbl   %2,%4,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%3)\n"
-        "       beq     %2,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
-        : "r" ((long)m), "1" (val) : "memory");
-
-        return ret;
-}
-
-static inline unsigned long
-__xchg_u16_local(volatile short *m, unsigned long val)
-{
-        unsigned long ret, tmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %4,7,%3\n"
-        "       inswl   %1,%4,%1\n"
-        "1:     ldq_l   %2,0(%3)\n"
-        "       extwl   %2,%4,%0\n"
-        "       mskwl   %2,%4,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%3)\n"
-        "       beq     %2,2f\n"
-        ".subsection 2\n"
-        "2:     br      1b\n"
-        ".previous"
-        : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
-        : "r" ((long)m), "1" (val) : "memory");
-
-        return ret;
-}
-
-static inline unsigned long
-__xchg_u32_local(volatile int *m, unsigned long val)
-{
-        unsigned long dummy;
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%4\n"
-        "       bis $31,%3,%1\n"
-        "       stl_c %1,%2\n"
-        "       beq %1,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        : "=&r" (val), "=&r" (dummy), "=m" (*m)
-        : "rI" (val), "m" (*m) : "memory");
-
-        return val;
-}
-
-static inline unsigned long
-__xchg_u64_local(volatile long *m, unsigned long val)
-{
-        unsigned long dummy;
-
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%4\n"
-        "       bis $31,%3,%1\n"
-        "       stq_c %1,%2\n"
-        "       beq %1,2f\n"
-        ".subsection 2\n"
-        "2:     br 1b\n"
-        ".previous"
-        : "=&r" (val), "=&r" (dummy), "=m" (*m)
-        : "rI" (val), "m" (*m) : "memory");
-
-        return val;
-}
-
-#define __xchg_local(ptr, x, size) \
-({ \
-        unsigned long __xchg__res; \
-        volatile void *__xchg__ptr = (ptr); \
-        switch (size) { \
-                case 1: __xchg__res = __xchg_u8_local(__xchg__ptr, x); break; \
-                case 2: __xchg__res = __xchg_u16_local(__xchg__ptr, x); break; \
-                case 4: __xchg__res = __xchg_u32_local(__xchg__ptr, x); break; \
-                case 8: __xchg__res = __xchg_u64_local(__xchg__ptr, x); break; \
-                default: __xchg_called_with_bad_pointer(); __xchg__res = x; \
-        } \
-        __xchg__res; \
-})
-
-#define xchg_local(ptr,x)                                                    \
-  ({                                                                         \
-     __typeof__(*(ptr)) _x_ = (x);                                           \
-     (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_,            \
-                sizeof(*(ptr))); \
-  })
-
-/* 
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- *
- * The memory barrier should be placed in SMP only when we actually
- * make the change. If we don't change anything (so if the returned
- * prev is equal to old) then we aren't acquiring anything new and
- * we don't need any memory barrier as far I can tell.
- */
-
-#define __HAVE_ARCH_CMPXCHG 1
-
-static inline unsigned long
-__cmpxchg_u8(volatile char *m, long old, long new)
-{
-        unsigned long prev, tmp, cmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %5,7,%4\n"
-        "       insbl   %1,%5,%1\n"
-        "1:     ldq_l   %2,0(%4)\n"
-        "       extbl   %2,%5,%0\n"
-        "       cmpeq   %0,%6,%3\n"
-        "       beq     %3,2f\n"
-        "       mskbl   %2,%5,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%4)\n"
-        "       beq     %2,3f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br      1b\n"
-        ".previous"
-        : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
-        : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u16(volatile short *m, long old, long new)
-{
-        unsigned long prev, tmp, cmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %5,7,%4\n"
-        "       inswl   %1,%5,%1\n"
-        "1:     ldq_l   %2,0(%4)\n"
-        "       extwl   %2,%5,%0\n"
-        "       cmpeq   %0,%6,%3\n"
-        "       beq     %3,2f\n"
-        "       mskwl   %2,%5,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%4)\n"
-        "       beq     %2,3f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br      1b\n"
-        ".previous"
-        : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
-        : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u32(volatile int *m, int old, int new)
-{
-        unsigned long prev, cmp;
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%5\n"
-        "       cmpeq %0,%3,%1\n"
-        "       beq %1,2f\n"
-        "       mov %4,%1\n"
-        "       stl_c %1,%2\n"
-        "       beq %1,3f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        : "=&r"(prev), "=&r"(cmp), "=m"(*m)
-        : "r"((long) old), "r"(new), "m"(*m) : "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u64(volatile long *m, unsigned long old, unsigned long new)
-{
-        unsigned long prev, cmp;
-
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%5\n"
-        "       cmpeq %0,%3,%1\n"
-        "       beq %1,2f\n"
-        "       mov %4,%1\n"
-        "       stq_c %1,%2\n"
-        "       beq %1,3f\n"
-#ifdef CONFIG_SMP
-        "       mb\n"
-#endif
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        : "=&r"(prev), "=&r"(cmp), "=m"(*m)
-        : "r"((long) old), "r"(new), "m"(*m) : "memory");
-
-        return prev;
-}
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid cmpxchg().  */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-static __always_inline unsigned long
-__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
-{
-        switch (size) {
-                case 1:
-                        return __cmpxchg_u8(ptr, old, new);
-                case 2:
-                        return __cmpxchg_u16(ptr, old, new);
-                case 4:
-                        return __cmpxchg_u32(ptr, old, new);
-                case 8:
-                        return __cmpxchg_u64(ptr, old, new);
-        }
-        __cmpxchg_called_with_bad_pointer();
-        return old;
-}
-
-#define cmpxchg(ptr, o, n)                                               \
-  ({                                                                     \
-     __typeof__(*(ptr)) _o_ = (o);                                       \
-     __typeof__(*(ptr)) _n_ = (n);                                       \
-     (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_,           \
-                                    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-#define cmpxchg64(ptr, o, n)                                             \
-  ({                                                                     \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                               \
-        cmpxchg((ptr), (o), (n));                                        \
-  })
-
-static inline unsigned long
-__cmpxchg_u8_local(volatile char *m, long old, long new)
-{
-        unsigned long prev, tmp, cmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %5,7,%4\n"
-        "       insbl   %1,%5,%1\n"
-        "1:     ldq_l   %2,0(%4)\n"
-        "       extbl   %2,%5,%0\n"
-        "       cmpeq   %0,%6,%3\n"
-        "       beq     %3,2f\n"
-        "       mskbl   %2,%5,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%4)\n"
-        "       beq     %2,3f\n"
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br      1b\n"
-        ".previous"
-        : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
-        : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u16_local(volatile short *m, long old, long new)
-{
-        unsigned long prev, tmp, cmp, addr64;
-
-        __asm__ __volatile__(
-        "       andnot  %5,7,%4\n"
-        "       inswl   %1,%5,%1\n"
-        "1:     ldq_l   %2,0(%4)\n"
-        "       extwl   %2,%5,%0\n"
-        "       cmpeq   %0,%6,%3\n"
-        "       beq     %3,2f\n"
-        "       mskwl   %2,%5,%2\n"
-        "       or      %1,%2,%2\n"
-        "       stq_c   %2,0(%4)\n"
-        "       beq     %2,3f\n"
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br      1b\n"
-        ".previous"
-        : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
-        : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u32_local(volatile int *m, int old, int new)
-{
-        unsigned long prev, cmp;
-
-        __asm__ __volatile__(
-        "1:     ldl_l %0,%5\n"
-        "       cmpeq %0,%3,%1\n"
-        "       beq %1,2f\n"
-        "       mov %4,%1\n"
-        "       stl_c %1,%2\n"
-        "       beq %1,3f\n"
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        : "=&r"(prev), "=&r"(cmp), "=m"(*m)
-        : "r"((long) old), "r"(new), "m"(*m) : "memory");
-
-        return prev;
-}
-
-static inline unsigned long
-__cmpxchg_u64_local(volatile long *m, unsigned long old, unsigned long new)
-{
-        unsigned long prev, cmp;
-
-        __asm__ __volatile__(
-        "1:     ldq_l %0,%5\n"
-        "       cmpeq %0,%3,%1\n"
-        "       beq %1,2f\n"
-        "       mov %4,%1\n"
-        "       stq_c %1,%2\n"
-        "       beq %1,3f\n"
-        "2:\n"
-        ".subsection 2\n"
-        "3:     br 1b\n"
-        ".previous"
-        : "=&r"(prev), "=&r"(cmp), "=m"(*m)
-        : "r"((long) old), "r"(new), "m"(*m) : "memory");
-
-        return prev;
-}
-
-static __always_inline unsigned long
-__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
-                int size)
-{
-        switch (size) {
-                case 1:
-                        return __cmpxchg_u8_local(ptr, old, new);
-                case 2:
-                        return __cmpxchg_u16_local(ptr, old, new);
-                case 4:
-                        return __cmpxchg_u32_local(ptr, old, new);
-                case 8:
-                        return __cmpxchg_u64_local(ptr, old, new);
-        }
-        __cmpxchg_called_with_bad_pointer();
-        return old;
-}
-
-#define cmpxchg_local(ptr, o, n)                                         \
-  ({                                                                     \
-     __typeof__(*(ptr)) _o_ = (o);                                       \
-     __typeof__(*(ptr)) _n_ = (n);                                       \
-     (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
-                                    (unsigned long)_n_, sizeof(*(ptr))); \
-  })
-#define cmpxchg64_local(ptr, o, n)                                       \
-  ({                                                                     \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                               \
-        cmpxchg_local((ptr), (o), (n));                                  \
-  })
-
-
-#endif /* __ASSEMBLY__ */
-
-#define arch_align_stack(x) (x)
-
-#endif
diff --git a/include/asm-alpha/termbits.h b/include/asm-alpha/termbits.h
deleted file mode 100644
index ad854a4a3af6..000000000000
--- a/include/asm-alpha/termbits.h
+++ /dev/null
@@ -1,200 +0,0 @@
-#ifndef _ALPHA_TERMBITS_H
-#define _ALPHA_TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-
-/*
- * termios type and macro definitions.  Be careful about adding stuff
- * to this file since it's used in GNU libc and there are strict rules
- * concerning namespace pollution.
- */
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_cc[NCCS];                /* control characters */
-        cc_t c_line;                    /* line discipline (== c_cc[19]) */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* Alpha has matching termios and ktermios */
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_cc[NCCS];                /* control characters */
-        cc_t c_line;                    /* line discipline (== c_cc[19]) */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* c_cc characters */
-#define VEOF 0
-#define VEOL 1
-#define VEOL2 2
-#define VERASE 3
-#define VWERASE 4
-#define VKILL 5
-#define VREPRINT 6
-#define VSWTC 7
-#define VINTR 8
-#define VQUIT 9
-#define VSUSP 10
-#define VSTART 12
-#define VSTOP 13
-#define VLNEXT 14
-#define VDISCARD 15
-#define VMIN 16
-#define VTIME 17
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IXON    0001000
-#define IXOFF   0002000
-#define IXANY   0004000
-#define IUCLC   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define ONLCR   0000002
-#define OLCUC   0000004
-
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-
-#define OFILL   00000100
-#define OFDEL   00000200
-#define NLDLY   00001400
-#define   NL0   00000000
-#define   NL1   00000400
-#define   NL2   00001000
-#define   NL3   00001400
-#define TABDLY  00006000
-#define   TAB0  00000000
-#define   TAB1  00002000
-#define   TAB2  00004000
-#define   TAB3  00006000
-#define CRDLY   00030000
-#define   CR0   00000000
-#define   CR1   00010000
-#define   CR2   00020000
-#define   CR3   00030000
-#define FFDLY   00040000
-#define   FF0   00000000
-#define   FF1   00040000
-#define BSDLY   00100000
-#define   BS0   00000000
-#define   BS1   00100000
-#define VTDLY   00200000
-#define   VT0   00000000
-#define   VT1   00200000
-#define XTABS   01000000 /* Hmm.. Linux/i386 considers this part of TABDLY.. */
-
-/* c_cflag bit meaning */
-#define CBAUD   0000037
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CBAUDEX 0000000
-#define  B57600   00020
-#define  B115200  00021
-#define  B230400  00022
-#define  B460800  00023
-#define  B500000  00024
-#define  B576000  00025
-#define  B921600  00026
-#define B1000000  00027
-#define B1152000  00030
-#define B1500000  00031
-#define B2000000  00032
-#define B2500000  00033
-#define B3000000  00034
-#define B3500000  00035
-#define B4000000  00036
-
-#define CSIZE   00001400
-#define   CS5   00000000
-#define   CS6   00000400
-#define   CS7   00001000
-#define   CS8   00001400
-
-#define CSTOPB  00002000
-#define CREAD   00004000
-#define PARENB  00010000
-#define PARODD  00020000
-#define HUPCL   00040000
-
-#define CLOCAL  00100000
-#define CMSPAR    010000000000          /* mark or space (stick) parity */
-#define CRTSCTS   020000000000          /* flow control */
-
-/* c_lflag bits */
-#define ISIG    0x00000080
-#define ICANON  0x00000100
-#define XCASE   0x00004000
-#define ECHO    0x00000008
-#define ECHOE   0x00000002
-#define ECHOK   0x00000004
-#define ECHONL  0x00000010
-#define NOFLSH  0x80000000
-#define TOSTOP  0x00400000
-#define ECHOCTL 0x00000040
-#define ECHOPRT 0x00000020
-#define ECHOKE  0x00000001
-#define FLUSHO  0x00800000
-#define PENDIN  0x20000000
-#define IEXTEN  0x00000400
-
-/* Values for the ACTION argument to `tcflow'.  */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* Values for the QUEUE_SELECTOR argument to `tcflush'.  */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* Values for the OPTIONAL_ACTIONS argument to `tcsetattr'.  */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif /* _ALPHA_TERMBITS_H */
diff --git a/include/asm-alpha/termios.h b/include/asm-alpha/termios.h
deleted file mode 100644
index fa13716a11c3..000000000000
--- a/include/asm-alpha/termios.h
+++ /dev/null
@@ -1,146 +0,0 @@
-#ifndef _ALPHA_TERMIOS_H
-#define _ALPHA_TERMIOS_H
-
-#include <asm/ioctls.h>
-#include <asm/termbits.h>
-
-struct sgttyb {
-        char    sg_ispeed;
-        char    sg_ospeed;
-        char    sg_erase;
-        char    sg_kill;
-        short   sg_flags;
-};
-
-struct tchars {
-        char    t_intrc;
-        char    t_quitc;
-        char    t_startc;
-        char    t_stopc;
-        char    t_eofc;
-        char    t_brkc;
-};
-
-struct ltchars {
-        char    t_suspc;
-        char    t_dsuspc;
-        char    t_rprntc;
-        char    t_flushc;
-        char    t_werasc;
-        char    t_lnextc;
-};
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-/*
- * c_cc characters in the termio structure.  Oh, how I love being
- * backwardly compatible.  Notice that character 4 and 5 are
- * interpreted differently depending on whether ICANON is set in
- * c_lflag.  If it's set, they are used as _VEOF and _VEOL, otherwise
- * as _VMIN and V_TIME.  This is for compatibility with OSF/1 (which
- * is compatible with sysV)...
- */
-#define _VINTR  0
-#define _VQUIT  1
-#define _VERASE 2
-#define _VKILL  3
-#define _VEOF   4
-#define _VMIN   4
-#define _VEOL   5
-#define _VTIME  5
-#define _VEOL2  6
-#define _VSWTC  7
-
-#ifdef __KERNEL__
-/*      eof=^D          eol=\0          eol2=\0         erase=del
-        werase=^W       kill=^U         reprint=^R      sxtc=\0
-        intr=^C         quit=^\         susp=^Z         <OSF/1 VDSUSP>
-        start=^Q        stop=^S         lnext=^V        discard=^U
-        vmin=\1         vtime=\0
-*/
-#define INIT_C_CC "\004\000\000\177\027\025\022\000\003\034\032\000\021\023\026\025\001\000"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-
-#define user_termio_to_kernel_termios(a_termios, u_termio)                      \
-({                                                                              \
-        struct ktermios *k_termios = (a_termios);                               \
-        struct termio k_termio;                                                 \
-        int canon, ret;                                                         \
-                                                                                \
-        ret = copy_from_user(&k_termio, u_termio, sizeof(k_termio));            \
-        if (!ret) {                                                             \
-                /* Overwrite only the low bits.  */                             \
-                *(unsigned short *)&k_termios->c_iflag = k_termio.c_iflag;      \
-                *(unsigned short *)&k_termios->c_oflag = k_termio.c_oflag;      \
-                *(unsigned short *)&k_termios->c_cflag = k_termio.c_cflag;      \
-                *(unsigned short *)&k_termios->c_lflag = k_termio.c_lflag;      \
-                canon = k_termio.c_lflag & ICANON;                              \
-                                                                                \
-                k_termios->c_cc[VINTR]  = k_termio.c_cc[_VINTR];                \
-                k_termios->c_cc[VQUIT]  = k_termio.c_cc[_VQUIT];                \
-                k_termios->c_cc[VERASE] = k_termio.c_cc[_VERASE];               \
-                k_termios->c_cc[VKILL]  = k_termio.c_cc[_VKILL];                \
-                k_termios->c_cc[VEOL2]  = k_termio.c_cc[_VEOL2];                \
-                k_termios->c_cc[VSWTC]  = k_termio.c_cc[_VSWTC];                \
-                k_termios->c_cc[canon ? VEOF : VMIN]  = k_termio.c_cc[_VEOF];   \
-                k_termios->c_cc[canon ? VEOL : VTIME] = k_termio.c_cc[_VEOL];   \
-        }                                                                       \
-        ret;                                                                    \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- *
- * Note the "fun" _VMIN overloading.
- */
-#define kernel_termios_to_user_termio(u_termio, a_termios)              \
-({                                                                      \
-        struct ktermios *k_termios = (a_termios);                       \
-        struct termio k_termio;                                         \
-        int canon;                                                      \
-                                                                        \
-        k_termio.c_iflag = k_termios->c_iflag;                          \
-        k_termio.c_oflag = k_termios->c_oflag;                          \
-        k_termio.c_cflag = k_termios->c_cflag;                          \
-        canon = (k_termio.c_lflag = k_termios->c_lflag) & ICANON;       \
-                                                                        \
-        k_termio.c_line = k_termios->c_line;                            \
-        k_termio.c_cc[_VINTR]  = k_termios->c_cc[VINTR];                \
-        k_termio.c_cc[_VQUIT]  = k_termios->c_cc[VQUIT];                \
-        k_termio.c_cc[_VERASE] = k_termios->c_cc[VERASE];               \
-        k_termio.c_cc[_VKILL]  = k_termios->c_cc[VKILL];                \
-        k_termio.c_cc[_VEOF]   = k_termios->c_cc[canon ? VEOF : VMIN];  \
-        k_termio.c_cc[_VEOL]   = k_termios->c_cc[canon ? VEOL : VTIME]; \
-        k_termio.c_cc[_VEOL2]  = k_termios->c_cc[VEOL2];                \
-        k_termio.c_cc[_VSWTC]  = k_termios->c_cc[VSWTC];                \
-                                                                        \
-        copy_to_user(u_termio, &k_termio, sizeof(k_termio));            \
-})
-
-#define user_termios_to_kernel_termios(k, u) \
-        copy_from_user(k, u, sizeof(struct termios))
-
-#define kernel_termios_to_user_termios(u, k) \
-        copy_to_user(u, k, sizeof(struct termios))
-
-#endif  /* __KERNEL__ */
-
-#endif  /* _ALPHA_TERMIOS_H */
diff --git a/include/asm-alpha/thread_info.h b/include/asm-alpha/thread_info.h
deleted file mode 100644
index 15fda4344424..000000000000
--- a/include/asm-alpha/thread_info.h
+++ /dev/null
@@ -1,114 +0,0 @@
-#ifndef _ALPHA_THREAD_INFO_H
-#define _ALPHA_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <asm/processor.h>
-#include <asm/types.h>
-#include <asm/hwrpb.h>
-#endif
-
-#ifndef __ASSEMBLY__
-struct thread_info {
-        struct pcb_struct       pcb;            /* palcode state */
-
-        struct task_struct      *task;          /* main task structure */
-        unsigned int            flags;          /* low level flags */
-        unsigned int            ieee_state;     /* see fpu.h */
-
-        struct exec_domain      *exec_domain;   /* execution domain */
-        mm_segment_t            addr_limit;     /* thread address space */
-        unsigned                cpu;            /* current CPU */
-        int                     preempt_count; /* 0 => preemptable, <0 => BUG */
-
-        int bpt_nsaved;
-        unsigned long bpt_addr[2];              /* breakpoint handling  */
-        unsigned int bpt_insn[2];
-
-        struct restart_block    restart_block;
-};
-
-/*
- * Macros/functions for gaining access to the thread information structure.
- */
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task           = &tsk,                 \
-        .exec_domain    = &default_exec_domain, \
-        .addr_limit     = KERNEL_DS,            \
-        .restart_block = {                      \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-/* How to get the thread information struct from C.  */
-register struct thread_info *__current_thread_info __asm__("$8");
-#define current_thread_info()  __current_thread_info
-
-/* Thread information allocation.  */
-#define THREAD_SIZE_ORDER 1
-#define THREAD_SIZE (2*PAGE_SIZE)
-
-#endif /* __ASSEMBLY__ */
-
-#define PREEMPT_ACTIVE          0x40000000
-
-/*
- * Thread information flags:
- * - these are process state flags and used from assembly
- * - pending work-to-be-done flags come first to fit in and immediate operand.
- *
- * TIF_SYSCALL_TRACE is known to be 0 via blbs.
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_SIGPENDING          1       /* signal pending */
-#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      3       /* poll_idle is polling NEED_RESCHED */
-#define TIF_DIE_IF_KERNEL       4       /* dik recursion lock */
-#define TIF_UAC_NOPRINT         5       /* see sysinfo.h */
-#define TIF_UAC_NOFIX           6
-#define TIF_UAC_SIGBUS          7
-#define TIF_MEMDIE              8
-#define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal */
-
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-
-/* Work to do on interrupt/exception return.  */
-#define _TIF_WORK_MASK          (_TIF_SIGPENDING | _TIF_NEED_RESCHED)
-
-/* Work to do on any return to userspace.  */
-#define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK         \
-                                 | _TIF_SYSCALL_TRACE)
-
-#define ALPHA_UAC_SHIFT         6
-#define ALPHA_UAC_MASK          (1 << TIF_UAC_NOPRINT | 1 << TIF_UAC_NOFIX | \
-                                 1 << TIF_UAC_SIGBUS)
-
-#define SET_UNALIGN_CTL(task,value)     ({                                   \
-        task_thread_info(task)->flags = ((task_thread_info(task)->flags &    \
-                ~ALPHA_UAC_MASK)                                             \
-                | (((value) << ALPHA_UAC_SHIFT)       & (1<<TIF_UAC_NOPRINT))\
-                | (((value) << (ALPHA_UAC_SHIFT + 1)) & (1<<TIF_UAC_SIGBUS)) \
-                | (((value) << (ALPHA_UAC_SHIFT - 1)) & (1<<TIF_UAC_NOFIX)));\
-        0; })
-
-#define GET_UNALIGN_CTL(task,value)     ({                              \
-        put_user((task_thread_info(task)->flags & (1 << TIF_UAC_NOPRINT))\
-                  >> ALPHA_UAC_SHIFT                                    \
-                 | (task_thread_info(task)->flags & (1 << TIF_UAC_SIGBUS))\
-                 >> (ALPHA_UAC_SHIFT + 1)                               \
-                 | (task_thread_info(task)->flags & (1 << TIF_UAC_NOFIX))\
-                 >> (ALPHA_UAC_SHIFT - 1),                              \
-                 (int __user *)(value));                                \
-        })
-
-#endif /* __KERNEL__ */
-#endif /* _ALPHA_THREAD_INFO_H */
diff --git a/include/asm-alpha/timex.h b/include/asm-alpha/timex.h
deleted file mode 100644
index afa0c45e3e98..000000000000
--- a/include/asm-alpha/timex.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * linux/include/asm-alpha/timex.h
- *
- * ALPHA architecture timex specifications
- */
-#ifndef _ASMALPHA_TIMEX_H
-#define _ASMALPHA_TIMEX_H
-
-/* With only one or two oddballs, we use the RTC as the ticker, selecting
-   the 32.768kHz reference clock, which nicely divides down to our HZ.  */
-#define CLOCK_TICK_RATE 32768
-
-/*
- * Standard way to access the cycle counter.
- * Currently only used on SMP for scheduling.
- *
- * Only the low 32 bits are available as a continuously counting entity. 
- * But this only means we'll force a reschedule every 8 seconds or so,
- * which isn't an evil thing.
- */
-
-typedef unsigned int cycles_t;
-
-static inline cycles_t get_cycles (void)
-{
-        cycles_t ret;
-        __asm__ __volatile__ ("rpcc %0" : "=r"(ret));
-        return ret;
-}
-
-#endif
diff --git a/include/asm-alpha/tlb.h b/include/asm-alpha/tlb.h
deleted file mode 100644
index c13636575fba..000000000000
--- a/include/asm-alpha/tlb.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _ALPHA_TLB_H
-#define _ALPHA_TLB_H
-
-#define tlb_start_vma(tlb, vma)                 do { } while (0)
-#define tlb_end_vma(tlb, vma)                   do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, pte, addr)  do { } while (0)
-
-#define tlb_flush(tlb)                          flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#define __pte_free_tlb(tlb, pte)                        pte_free((tlb)->mm, pte)
-#define __pmd_free_tlb(tlb, pmd)                        pmd_free((tlb)->mm, pmd)
- 
-#endif
diff --git a/include/asm-alpha/tlbflush.h b/include/asm-alpha/tlbflush.h
deleted file mode 100644
index 9d87aaa08c0d..000000000000
--- a/include/asm-alpha/tlbflush.h
+++ /dev/null
@@ -1,151 +0,0 @@
-#ifndef _ALPHA_TLBFLUSH_H
-#define _ALPHA_TLBFLUSH_H
-
-#include <linux/mm.h>
-#include <asm/compiler.h>
-#include <asm/pgalloc.h>
-
-#ifndef __EXTERN_INLINE
-#define __EXTERN_INLINE extern inline
-#define __MMU_EXTERN_INLINE
-#endif
-
-extern void __load_new_mm_context(struct mm_struct *);
-
-
-/* Use a few helper functions to hide the ugly broken ASN
-   numbers on early Alphas (ev4 and ev45).  */
-
-__EXTERN_INLINE void
-ev4_flush_tlb_current(struct mm_struct *mm)
-{
-        __load_new_mm_context(mm);
-        tbiap();
-}
-
-__EXTERN_INLINE void
-ev5_flush_tlb_current(struct mm_struct *mm)
-{
-        __load_new_mm_context(mm);
-}
-
-/* Flush just one page in the current TLB set.  We need to be very
-   careful about the icache here, there is no way to invalidate a
-   specific icache page.  */
-
-__EXTERN_INLINE void
-ev4_flush_tlb_current_page(struct mm_struct * mm,
-                           struct vm_area_struct *vma,
-                           unsigned long addr)
-{
-        int tbi_flag = 2;
-        if (vma->vm_flags & VM_EXEC) {
-                __load_new_mm_context(mm);
-                tbi_flag = 3;
-        }
-        tbi(tbi_flag, addr);
-}
-
-__EXTERN_INLINE void
-ev5_flush_tlb_current_page(struct mm_struct * mm,
-                           struct vm_area_struct *vma,
-                           unsigned long addr)
-{
-        if (vma->vm_flags & VM_EXEC)
-                __load_new_mm_context(mm);
-        else
-                tbi(2, addr);
-}
-
-
-#ifdef CONFIG_ALPHA_GENERIC
-# define flush_tlb_current              alpha_mv.mv_flush_tlb_current
-# define flush_tlb_current_page         alpha_mv.mv_flush_tlb_current_page
-#else
-# ifdef CONFIG_ALPHA_EV4
-#  define flush_tlb_current             ev4_flush_tlb_current
-#  define flush_tlb_current_page        ev4_flush_tlb_current_page
-# else
-#  define flush_tlb_current             ev5_flush_tlb_current
-#  define flush_tlb_current_page        ev5_flush_tlb_current_page
-# endif
-#endif
-
-#ifdef __MMU_EXTERN_INLINE
-#undef __EXTERN_INLINE
-#undef __MMU_EXTERN_INLINE
-#endif
-
-/* Flush current user mapping.  */
-static inline void
-flush_tlb(void)
-{
-        flush_tlb_current(current->active_mm);
-}
-
-/* Flush someone else's user mapping.  */
-static inline void
-flush_tlb_other(struct mm_struct *mm)
-{
-        unsigned long *mmc = &mm->context[smp_processor_id()];
-        /* Check it's not zero first to avoid cacheline ping pong
-           when possible.  */
-        if (*mmc) *mmc = 0;
-}
-
-#ifndef CONFIG_SMP
-/* Flush everything (kernel mapping may also have changed
-   due to vmalloc/vfree).  */
-static inline void flush_tlb_all(void)
-{
-        tbia();
-}
-
-/* Flush a specified user mapping.  */
-static inline void
-flush_tlb_mm(struct mm_struct *mm)
-{
-        if (mm == current->active_mm)
-                flush_tlb_current(mm);
-        else
-                flush_tlb_other(mm);
-}
-
-/* Page-granular tlb flush.  */
-static inline void
-flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
-        struct mm_struct *mm = vma->vm_mm;
-
-        if (mm == current->active_mm)
-                flush_tlb_current_page(mm, vma, addr);
-        else
-                flush_tlb_other(mm);
-}
-
-/* Flush a specified range of user mapping.  On the Alpha we flush
-   the whole user tlb.  */
-static inline void
-flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
-                unsigned long end)
-{
-        flush_tlb_mm(vma->vm_mm);
-}
-
-#else /* CONFIG_SMP */
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_mm(struct mm_struct *);
-extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void flush_tlb_range(struct vm_area_struct *, unsigned long,
-                            unsigned long);
-
-#endif /* CONFIG_SMP */
-
-static inline void flush_tlb_kernel_range(unsigned long start,
-                                        unsigned long end)
-{
-        flush_tlb_all();
-}
-
-#endif /* _ALPHA_TLBFLUSH_H */
diff --git a/include/asm-alpha/topology.h b/include/asm-alpha/topology.h
deleted file mode 100644
index 149532e162c4..000000000000
--- a/include/asm-alpha/topology.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef _ASM_ALPHA_TOPOLOGY_H
-#define _ASM_ALPHA_TOPOLOGY_H
-
-#include <linux/smp.h>
-#include <linux/threads.h>
-#include <asm/machvec.h>
-
-#ifdef CONFIG_NUMA
-static inline int cpu_to_node(int cpu)
-{
-        int node;
-        
-        if (!alpha_mv.cpuid_to_nid)
-                return 0;
-
-        node = alpha_mv.cpuid_to_nid(cpu);
-
-#ifdef DEBUG_NUMA
-        BUG_ON(node < 0);
-#endif
-
-        return node;
-}
-
-static inline cpumask_t node_to_cpumask(int node)
-{
-        cpumask_t node_cpu_mask = CPU_MASK_NONE;
-        int cpu;
-
-        for_each_online_cpu(cpu) {
-                if (cpu_to_node(cpu) == node)
-                        cpu_set(cpu, node_cpu_mask);
-        }
-
-#ifdef DEBUG_NUMA
-        printk("node %d: cpu_mask: %016lx\n", node, node_cpu_mask);
-#endif
-
-        return node_cpu_mask;
-}
-
-#define pcibus_to_cpumask(bus)  (cpu_online_map)
-
-#endif /* !CONFIG_NUMA */
-# include <asm-generic/topology.h>
-
-#endif /* _ASM_ALPHA_TOPOLOGY_H */
diff --git a/include/asm-alpha/types.h b/include/asm-alpha/types.h
deleted file mode 100644
index c1541353ccef..000000000000
--- a/include/asm-alpha/types.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _ALPHA_TYPES_H
-#define _ALPHA_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-#include <asm-generic/int-l64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned int umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 64
-
-#ifndef __ASSEMBLY__
-
-typedef u64 dma_addr_t;
-typedef u64 dma64_addr_t;
-
-#endif /* __ASSEMBLY__ */
-#endif /* __KERNEL__ */
-#endif /* _ALPHA_TYPES_H */
diff --git a/include/asm-alpha/uaccess.h b/include/asm-alpha/uaccess.h
deleted file mode 100644
index 22de3b434a22..000000000000
--- a/include/asm-alpha/uaccess.h
+++ /dev/null
@@ -1,511 +0,0 @@
-#ifndef __ALPHA_UACCESS_H
-#define __ALPHA_UACCESS_H
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * Or at least it did once upon a time.  Nowadays it is a mask that
- * defines which bits of the address space are off limits.  This is a
- * wee bit faster than the above.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-
-#define KERNEL_DS       ((mm_segment_t) { 0UL })
-#define USER_DS         ((mm_segment_t) { -0x40000000000UL })
-
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-
-#define get_fs()  (current_thread_info()->addr_limit)
-#define get_ds()  (KERNEL_DS)
-#define set_fs(x) (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a,b) ((a).seg == (b).seg)
-
-/*
- * Is a address valid? This does a straightforward calculation rather
- * than tests.
- *
- * Address valid if:
- *  - "addr" doesn't have any high-bits set
- *  - AND "size" doesn't have any high-bits set
- *  - AND "addr+size" doesn't have any high-bits set
- *  - OR we are in kernel mode.
- */
-#define __access_ok(addr,size,segment) \
-        (((segment).seg & (addr | size | (addr+size))) == 0)
-
-#define access_ok(type,addr,size)                               \
-({                                                              \
-        __chk_user_ptr(addr);                                   \
-        __access_ok(((unsigned long)(addr)),(size),get_fs());   \
-})
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- *
- * As the alpha uses the same address space for kernel and user
- * data, we can just do these as direct assignments.  (Of course, the
- * exception handling means that it's no longer "just"...)
- *
- * Careful to not
- * (a) re-use the arguments for side effects (sizeof/typeof is ok)
- * (b) require any knowledge of processes at this stage
- */
-#define put_user(x,ptr) \
-  __put_user_check((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)),get_fs())
-#define get_user(x,ptr) \
-  __get_user_check((x),(ptr),sizeof(*(ptr)),get_fs())
-
-/*
- * The "__xxx" versions do not do address space checking, useful when
- * doing multiple accesses to the same area (the programmer has to do the
- * checks by hand with "access_ok()")
- */
-#define __put_user(x,ptr) \
-  __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr)))
-#define __get_user(x,ptr) \
-  __get_user_nocheck((x),(ptr),sizeof(*(ptr)))
-  
-/*
- * The "lda %1, 2b-1b(%0)" bits are magic to get the assembler to
- * encode the bits we need for resolving the exception.  See the
- * more extensive comments with fixup_inline_exception below for
- * more information.
- */
-
-extern void __get_user_unknown(void);
-
-#define __get_user_nocheck(x,ptr,size)                          \
-({                                                              \
-        long __gu_err = 0;                                      \
-        unsigned long __gu_val;                                 \
-        __chk_user_ptr(ptr);                                    \
-        switch (size) {                                         \
-          case 1: __get_user_8(ptr); break;                     \
-          case 2: __get_user_16(ptr); break;                    \
-          case 4: __get_user_32(ptr); break;                    \
-          case 8: __get_user_64(ptr); break;                    \
-          default: __get_user_unknown(); break;                 \
-        }                                                       \
-        (x) = (__typeof__(*(ptr))) __gu_val;                    \
-        __gu_err;                                               \
-})
-
-#define __get_user_check(x,ptr,size,segment)                            \
-({                                                                      \
-        long __gu_err = -EFAULT;                                        \
-        unsigned long __gu_val = 0;                                     \
-        const __typeof__(*(ptr)) __user *__gu_addr = (ptr);             \
-        if (__access_ok((unsigned long)__gu_addr,size,segment)) {       \
-                __gu_err = 0;                                           \
-                switch (size) {                                         \
-                  case 1: __get_user_8(__gu_addr); break;               \
-                  case 2: __get_user_16(__gu_addr); break;              \
-                  case 4: __get_user_32(__gu_addr); break;              \
-                  case 8: __get_user_64(__gu_addr); break;              \
-                  default: __get_user_unknown(); break;                 \
-                }                                                       \
-        }                                                               \
-        (x) = (__typeof__(*(ptr))) __gu_val;                            \
-        __gu_err;                                                       \
-})
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct __user *)(x))
-
-#define __get_user_64(addr)                             \
-        __asm__("1: ldq %0,%2\n"                        \
-        "2:\n"                                          \
-        ".section __ex_table,\"a\"\n"                   \
-        "       .long 1b - .\n"                         \
-        "       lda %0, 2b-1b(%1)\n"                    \
-        ".previous"                                     \
-                : "=r"(__gu_val), "=r"(__gu_err)        \
-                : "m"(__m(addr)), "1"(__gu_err))
-
-#define __get_user_32(addr)                             \
-        __asm__("1: ldl %0,%2\n"                        \
-        "2:\n"                                          \
-        ".section __ex_table,\"a\"\n"                   \
-        "       .long 1b - .\n"                         \
-        "       lda %0, 2b-1b(%1)\n"                    \
-        ".previous"                                     \
-                : "=r"(__gu_val), "=r"(__gu_err)        \
-                : "m"(__m(addr)), "1"(__gu_err))
-
-#ifdef __alpha_bwx__
-/* Those lucky bastards with ev56 and later CPUs can do byte/word moves.  */
-
-#define __get_user_16(addr)                             \
-        __asm__("1: ldwu %0,%2\n"                       \
-        "2:\n"                                          \
-        ".section __ex_table,\"a\"\n"                   \
-        "       .long 1b - .\n"                         \
-        "       lda %0, 2b-1b(%1)\n"                    \
-        ".previous"                                     \
-                : "=r"(__gu_val), "=r"(__gu_err)        \
-                : "m"(__m(addr)), "1"(__gu_err))
-
-#define __get_user_8(addr)                              \
-        __asm__("1: ldbu %0,%2\n"                       \
-        "2:\n"                                          \
-        ".section __ex_table,\"a\"\n"                   \
-        "       .long 1b - .\n"                         \
-        "       lda %0, 2b-1b(%1)\n"                    \
-        ".previous"                                     \
-                : "=r"(__gu_val), "=r"(__gu_err)        \
-                : "m"(__m(addr)), "1"(__gu_err))
-#else
-/* Unfortunately, we can't get an unaligned access trap for the sub-word
-   load, so we have to do a general unaligned operation.  */
-
-#define __get_user_16(addr)                                             \
-{                                                                       \
-        long __gu_tmp;                                                  \
-        __asm__("1: ldq_u %0,0(%3)\n"                                   \
-        "2:     ldq_u %1,1(%3)\n"                                       \
-        "       extwl %0,%3,%0\n"                                       \
-        "       extwh %1,%3,%1\n"                                       \
-        "       or %0,%1,%0\n"                                          \
-        "3:\n"                                                          \
-        ".section __ex_table,\"a\"\n"                                   \
-        "       .long 1b - .\n"                                         \
-        "       lda %0, 3b-1b(%2)\n"                                    \
-        "       .long 2b - .\n"                                         \
-        "       lda %0, 3b-2b(%2)\n"                                    \
-        ".previous"                                                     \
-                : "=&r"(__gu_val), "=&r"(__gu_tmp), "=r"(__gu_err)      \
-                : "r"(addr), "2"(__gu_err));                            \
-}
-
-#define __get_user_8(addr)                                              \
-        __asm__("1: ldq_u %0,0(%2)\n"                                   \
-        "       extbl %0,%2,%0\n"                                       \
-        "2:\n"                                                          \
-        ".section __ex_table,\"a\"\n"                                   \
-        "       .long 1b - .\n"                                         \
-        "       lda %0, 2b-1b(%1)\n"                                    \
-        ".previous"                                                     \
-                : "=&r"(__gu_val), "=r"(__gu_err)                       \
-                : "r"(addr), "1"(__gu_err))
-#endif
-
-extern void __put_user_unknown(void);
-
-#define __put_user_nocheck(x,ptr,size)                          \
-({                                                              \
-        long __pu_err = 0;                                      \
-        __chk_user_ptr(ptr);                                    \
-        switch (size) {                                         \
-          case 1: __put_user_8(x,ptr); break;                   \
-          case 2: __put_user_16(x,ptr); break;                  \
-          case 4: __put_user_32(x,ptr); break;                  \
-          case 8: __put_user_64(x,ptr); break;                  \
-          default: __put_user_unknown(); break;                 \
-        }                                                       \
-        __pu_err;                                               \
-})
-
-#define __put_user_check(x,ptr,size,segment)                            \
-({                                                                      \
-        long __pu_err = -EFAULT;                                        \
-        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
-        if (__access_ok((unsigned long)__pu_addr,size,segment)) {       \
-                __pu_err = 0;                                           \
-                switch (size) {                                         \
-                  case 1: __put_user_8(x,__pu_addr); break;             \
-                  case 2: __put_user_16(x,__pu_addr); break;            \
-                  case 4: __put_user_32(x,__pu_addr); break;            \
-                  case 8: __put_user_64(x,__pu_addr); break;            \
-                  default: __put_user_unknown(); break;                 \
-                }                                                       \
-        }                                                               \
-        __pu_err;                                                       \
-})
-
-/*
- * The "__put_user_xx()" macros tell gcc they read from memory
- * instead of writing: this is because they do not write to
- * any memory gcc knows about, so there are no aliasing issues
- */
-#define __put_user_64(x,addr)                                   \
-__asm__ __volatile__("1: stq %r2,%1\n"                          \
-        "2:\n"                                                  \
-        ".section __ex_table,\"a\"\n"                           \
-        "       .long 1b - .\n"                                 \
-        "       lda $31,2b-1b(%0)\n"                            \
-        ".previous"                                             \
-                : "=r"(__pu_err)                                \
-                : "m" (__m(addr)), "rJ" (x), "0"(__pu_err))
-
-#define __put_user_32(x,addr)                                   \
-__asm__ __volatile__("1: stl %r2,%1\n"                          \
-        "2:\n"                                                  \
-        ".section __ex_table,\"a\"\n"                           \
-        "       .long 1b - .\n"                                 \
-        "       lda $31,2b-1b(%0)\n"                            \
-        ".previous"                                             \
-                : "=r"(__pu_err)                                \
-                : "m"(__m(addr)), "rJ"(x), "0"(__pu_err))
-
-#ifdef __alpha_bwx__
-/* Those lucky bastards with ev56 and later CPUs can do byte/word moves.  */
-
-#define __put_user_16(x,addr)                                   \
-__asm__ __volatile__("1: stw %r2,%1\n"                          \
-        "2:\n"                                                  \
-        ".section __ex_table,\"a\"\n"                           \
-        "       .long 1b - .\n"                                 \
-        "       lda $31,2b-1b(%0)\n"                            \
-        ".previous"                                             \
-                : "=r"(__pu_err)                                \
-                : "m"(__m(addr)), "rJ"(x), "0"(__pu_err))
-
-#define __put_user_8(x,addr)                                    \
-__asm__ __volatile__("1: stb %r2,%1\n"                          \
-        "2:\n"                                                  \
-        ".section __ex_table,\"a\"\n"                           \
-        "       .long 1b - .\n"                                 \
-        "       lda $31,2b-1b(%0)\n"                            \
-        ".previous"                                             \
-                : "=r"(__pu_err)                                \
-                : "m"(__m(addr)), "rJ"(x), "0"(__pu_err))
-#else
-/* Unfortunately, we can't get an unaligned access trap for the sub-word
-   write, so we have to do a general unaligned operation.  */
-
-#define __put_user_16(x,addr)                                   \
-{                                                               \
-        long __pu_tmp1, __pu_tmp2, __pu_tmp3, __pu_tmp4;        \
-        __asm__ __volatile__(                                   \
-        "1:     ldq_u %2,1(%5)\n"                               \
-        "2:     ldq_u %1,0(%5)\n"                               \
-        "       inswh %6,%5,%4\n"                               \
-        "       inswl %6,%5,%3\n"                               \
-        "       mskwh %2,%5,%2\n"                               \
-        "       mskwl %1,%5,%1\n"                               \
-        "       or %2,%4,%2\n"                                  \
-        "       or %1,%3,%1\n"                                  \
-        "3:     stq_u %2,1(%5)\n"                               \
-        "4:     stq_u %1,0(%5)\n"                               \
-        "5:\n"                                                  \
-        ".section __ex_table,\"a\"\n"                           \
-        "       .long 1b - .\n"                                 \
-        "       lda $31, 5b-1b(%0)\n"                           \
-        "       .long 2b - .\n"                                 \
-        "       lda $31, 5b-2b(%0)\n"                           \
-        "       .long 3b - .\n"                                 \
-        "       lda $31, 5b-3b(%0)\n"                           \
-        "       .long 4b - .\n"                                 \
-        "       lda $31, 5b-4b(%0)\n"                           \
-        ".previous"                                             \
-                : "=r"(__pu_err), "=&r"(__pu_tmp1),             \
-                  "=&r"(__pu_tmp2), "=&r"(__pu_tmp3),           \
-                  "=&r"(__pu_tmp4)                              \
-                : "r"(addr), "r"((unsigned long)(x)), "0"(__pu_err)); \
-}
-
-#define __put_user_8(x,addr)                                    \
-{                                                               \
-        long __pu_tmp1, __pu_tmp2;                              \
-        __asm__ __volatile__(                                   \
-        "1:     ldq_u %1,0(%4)\n"                               \
-        "       insbl %3,%4,%2\n"                               \
-        "       mskbl %1,%4,%1\n"                               \
-        "       or %1,%2,%1\n"                                  \
-        "2:     stq_u %1,0(%4)\n"                               \
-        "3:\n"                                                  \
-        ".section __ex_table,\"a\"\n"                           \
-        "       .long 1b - .\n"                                 \
-        "       lda $31, 3b-1b(%0)\n"                           \
-        "       .long 2b - .\n"                                 \
-        "       lda $31, 3b-2b(%0)\n"                           \
-        ".previous"                                             \
-                : "=r"(__pu_err),                               \
-                  "=&r"(__pu_tmp1), "=&r"(__pu_tmp2)            \
-                : "r"((unsigned long)(x)), "r"(addr), "0"(__pu_err)); \
-}
-#endif
-
-
-/*
- * Complex access routines
- */
-
-/* This little bit of silliness is to get the GP loaded for a function
-   that ordinarily wouldn't.  Otherwise we could have it done by the macro
-   directly, which can be optimized the linker.  */
-#ifdef MODULE
-#define __module_address(sym)           "r"(sym),
-#define __module_call(ra, arg, sym)     "jsr $" #ra ",(%" #arg ")," #sym
-#else
-#define __module_address(sym)
-#define __module_call(ra, arg, sym)     "bsr $" #ra "," #sym " !samegp"
-#endif
-
-extern void __copy_user(void);
-
-extern inline long
-__copy_tofrom_user_nocheck(void *to, const void *from, long len)
-{
-        register void * __cu_to __asm__("$6") = to;
-        register const void * __cu_from __asm__("$7") = from;
-        register long __cu_len __asm__("$0") = len;
-
-        __asm__ __volatile__(
-                __module_call(28, 3, __copy_user)
-                : "=r" (__cu_len), "=r" (__cu_from), "=r" (__cu_to)
-                : __module_address(__copy_user)
-                  "0" (__cu_len), "1" (__cu_from), "2" (__cu_to)
-                : "$1","$2","$3","$4","$5","$28","memory");
-
-        return __cu_len;
-}
-
-extern inline long
-__copy_tofrom_user(void *to, const void *from, long len, const void __user *validate)
-{
-        if (__access_ok((unsigned long)validate, len, get_fs()))
-                len = __copy_tofrom_user_nocheck(to, from, len);
-        return len;
-}
-
-#define __copy_to_user(to,from,n)                                       \
-({                                                                      \
-        __chk_user_ptr(to);                                             \
-        __copy_tofrom_user_nocheck((__force void *)(to),(from),(n));    \
-})
-#define __copy_from_user(to,from,n)                                     \
-({                                                                      \
-        __chk_user_ptr(from);                                           \
-        __copy_tofrom_user_nocheck((to),(__force void *)(from),(n));    \
-})
-
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-
-extern inline long
-copy_to_user(void __user *to, const void *from, long n)
-{
-        return __copy_tofrom_user((__force void *)to, from, n, to);
-}
-
-extern inline long
-copy_from_user(void *to, const void __user *from, long n)
-{
-        return __copy_tofrom_user(to, (__force void *)from, n, from);
-}
-
-extern void __do_clear_user(void);
-
-extern inline long
-__clear_user(void __user *to, long len)
-{
-        register void __user * __cl_to __asm__("$6") = to;
-        register long __cl_len __asm__("$0") = len;
-        __asm__ __volatile__(
-                __module_call(28, 2, __do_clear_user)
-                : "=r"(__cl_len), "=r"(__cl_to)
-                : __module_address(__do_clear_user)
-                  "0"(__cl_len), "1"(__cl_to)
-                : "$1","$2","$3","$4","$5","$28","memory");
-        return __cl_len;
-}
-
-extern inline long
-clear_user(void __user *to, long len)
-{
-        if (__access_ok((unsigned long)to, len, get_fs()))
-                len = __clear_user(to, len);
-        return len;
-}
-
-#undef __module_address
-#undef __module_call
-
-/* Returns: -EFAULT if exception before terminator, N if the entire
-   buffer filled, else strlen.  */
-
-extern long __strncpy_from_user(char *__to, const char __user *__from, long __to_len);
-
-extern inline long
-strncpy_from_user(char *to, const char __user *from, long n)
-{
-        long ret = -EFAULT;
-        if (__access_ok((unsigned long)from, 0, get_fs()))
-                ret = __strncpy_from_user(to, from, n);
-        return ret;
-}
-
-/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-extern long __strlen_user(const char __user *);
-
-extern inline long strlen_user(const char __user *str)
-{
-        return access_ok(VERIFY_READ,str,0) ? __strlen_user(str) : 0;
-}
-
-/* Returns: 0 if exception before NUL or reaching the supplied limit (N),
- * a value greater than N if the limit would be exceeded, else strlen.  */
-extern long __strnlen_user(const char __user *, long);
-
-extern inline long strnlen_user(const char __user *str, long n)
-{
-        return access_ok(VERIFY_READ,str,0) ? __strnlen_user(str, n) : 0;
-}
-
-/*
- * About the exception table:
- *
- * - insn is a 32-bit pc-relative offset from the faulting insn.
- * - nextinsn is a 16-bit offset off of the faulting instruction
- *   (not off of the *next* instruction as branches are).
- * - errreg is the register in which to place -EFAULT.
- * - valreg is the final target register for the load sequence
- *   and will be zeroed.
- *
- * Either errreg or valreg may be $31, in which case nothing happens.
- *
- * The exception fixup information "just so happens" to be arranged
- * as in a MEM format instruction.  This lets us emit our three
- * values like so:
- *
- *      lda valreg, nextinsn(errreg)
- *
- */
-
-struct exception_table_entry
-{
-        signed int insn;
-        union exception_fixup {
-                unsigned unit;
-                struct {
-                        signed int nextinsn : 16;
-                        unsigned int errreg : 5;
-                        unsigned int valreg : 5;
-                } bits;
-        } fixup;
-};
-
-/* Returns the new pc */
-#define fixup_exception(map_reg, fixup, pc)                     \
-({                                                              \
-        if ((fixup)->fixup.bits.valreg != 31)                   \
-                map_reg((fixup)->fixup.bits.valreg) = 0;        \
-        if ((fixup)->fixup.bits.errreg != 31)                   \
-                map_reg((fixup)->fixup.bits.errreg) = -EFAULT;  \
-        (pc) + (fixup)->fixup.bits.nextinsn;                    \
-})
-
-
-#endif /* __ALPHA_UACCESS_H */
diff --git a/include/asm-alpha/ucontext.h b/include/asm-alpha/ucontext.h
deleted file mode 100644
index 47578ab42152..000000000000
--- a/include/asm-alpha/ucontext.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASMAXP_UCONTEXT_H
-#define _ASMAXP_UCONTEXT_H
-
-struct ucontext {
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        old_sigset_t      uc_osf_sigmask;
-        stack_t           uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
-
-#endif /* !_ASMAXP_UCONTEXT_H */
diff --git a/include/asm-alpha/unaligned.h b/include/asm-alpha/unaligned.h
deleted file mode 100644
index 3787c60aed3f..000000000000
--- a/include/asm-alpha/unaligned.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_ALPHA_UNALIGNED_H
-#define _ASM_ALPHA_UNALIGNED_H
-
-#include <linux/unaligned/le_struct.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned __get_unaligned_le
-#define put_unaligned __put_unaligned_le
-
-#endif /* _ASM_ALPHA_UNALIGNED_H */
diff --git a/include/asm-alpha/unistd.h b/include/asm-alpha/unistd.h
deleted file mode 100644
index 5b5c17485942..000000000000
--- a/include/asm-alpha/unistd.h
+++ /dev/null
@@ -1,464 +0,0 @@
-#ifndef _ALPHA_UNISTD_H
-#define _ALPHA_UNISTD_H
-
-#define __NR_osf_syscall          0     /* not implemented */
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_osf_old_open         5     /* not implemented */
-#define __NR_close                6
-#define __NR_osf_wait4            7
-#define __NR_osf_old_creat        8     /* not implemented */
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_osf_execve          11     /* not implemented */
-#define __NR_chdir               12
-#define __NR_fchdir              13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_chown               16
-#define __NR_brk                 17
-#define __NR_osf_getfsstat       18     /* not implemented */
-#define __NR_lseek               19
-#define __NR_getxpid             20
-#define __NR_osf_mount           21
-#define __NR_umount              22
-#define __NR_setuid              23
-#define __NR_getxuid             24
-#define __NR_exec_with_loader    25     /* not implemented */
-#define __NR_ptrace              26
-#define __NR_osf_nrecvmsg        27     /* not implemented */
-#define __NR_osf_nsendmsg        28     /* not implemented */
-#define __NR_osf_nrecvfrom       29     /* not implemented */
-#define __NR_osf_naccept         30     /* not implemented */
-#define __NR_osf_ngetpeername    31     /* not implemented */
-#define __NR_osf_ngetsockname    32     /* not implemented */
-#define __NR_access              33
-#define __NR_osf_chflags         34     /* not implemented */
-#define __NR_osf_fchflags        35     /* not implemented */
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_osf_old_stat        38     /* not implemented */
-#define __NR_setpgid             39
-#define __NR_osf_old_lstat       40     /* not implemented */
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_osf_set_program_attributes 43
-#define __NR_osf_profil          44     /* not implemented */
-#define __NR_open                45
-#define __NR_osf_old_sigaction   46     /* not implemented */
-#define __NR_getxgid             47
-#define __NR_osf_sigprocmask     48
-#define __NR_osf_getlogin        49     /* not implemented */
-#define __NR_osf_setlogin        50     /* not implemented */
-#define __NR_acct                51
-#define __NR_sigpending          52
-
-#define __NR_ioctl               54
-#define __NR_osf_reboot          55     /* not implemented */
-#define __NR_osf_revoke          56     /* not implemented */
-#define __NR_symlink             57
-#define __NR_readlink            58
-#define __NR_execve              59
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_osf_old_fstat       62     /* not implemented */
-#define __NR_getpgrp             63
-#define __NR_getpagesize         64
-#define __NR_osf_mremap          65     /* not implemented */
-#define __NR_vfork               66
-#define __NR_stat                67
-#define __NR_lstat               68
-#define __NR_osf_sbrk            69     /* not implemented */
-#define __NR_osf_sstk            70     /* not implemented */
-#define __NR_mmap                71     /* OSF/1 mmap is superset of Linux */
-#define __NR_osf_old_vadvise     72     /* not implemented */
-#define __NR_munmap              73
-#define __NR_mprotect            74
-#define __NR_madvise             75
-#define __NR_vhangup             76
-#define __NR_osf_kmodcall        77     /* not implemented */
-#define __NR_osf_mincore         78     /* not implemented */
-#define __NR_getgroups           79
-#define __NR_setgroups           80
-#define __NR_osf_old_getpgrp     81     /* not implemented */
-#define __NR_setpgrp             82     /* BSD alias for setpgid */
-#define __NR_osf_setitimer       83
-#define __NR_osf_old_wait        84     /* not implemented */
-#define __NR_osf_table           85     /* not implemented */
-#define __NR_osf_getitimer       86
-#define __NR_gethostname         87
-#define __NR_sethostname         88
-#define __NR_getdtablesize       89
-#define __NR_dup2                90
-#define __NR_fstat               91
-#define __NR_fcntl               92
-#define __NR_osf_select          93
-#define __NR_poll                94
-#define __NR_fsync               95
-#define __NR_setpriority         96
-#define __NR_socket              97
-#define __NR_connect             98
-#define __NR_accept              99
-#define __NR_getpriority        100
-#define __NR_send               101
-#define __NR_recv               102
-#define __NR_sigreturn          103
-#define __NR_bind               104
-#define __NR_setsockopt         105
-#define __NR_listen             106
-#define __NR_osf_plock          107     /* not implemented */
-#define __NR_osf_old_sigvec     108     /* not implemented */
-#define __NR_osf_old_sigblock   109     /* not implemented */
-#define __NR_osf_old_sigsetmask 110     /* not implemented */
-#define __NR_sigsuspend         111
-#define __NR_osf_sigstack       112
-#define __NR_recvmsg            113
-#define __NR_sendmsg            114
-#define __NR_osf_old_vtrace     115     /* not implemented */
-#define __NR_osf_gettimeofday   116
-#define __NR_osf_getrusage      117
-#define __NR_getsockopt         118
-
-#define __NR_readv              120
-#define __NR_writev             121
-#define __NR_osf_settimeofday   122
-#define __NR_fchown             123
-#define __NR_fchmod             124
-#define __NR_recvfrom           125
-#define __NR_setreuid           126
-#define __NR_setregid           127
-#define __NR_rename             128
-#define __NR_truncate           129
-#define __NR_ftruncate          130
-#define __NR_flock              131
-#define __NR_setgid             132
-#define __NR_sendto             133
-#define __NR_shutdown           134
-#define __NR_socketpair         135
-#define __NR_mkdir              136
-#define __NR_rmdir              137
-#define __NR_osf_utimes         138
-#define __NR_osf_old_sigreturn  139     /* not implemented */
-#define __NR_osf_adjtime        140     /* not implemented */
-#define __NR_getpeername        141
-#define __NR_osf_gethostid      142     /* not implemented */
-#define __NR_osf_sethostid      143     /* not implemented */
-#define __NR_getrlimit          144
-#define __NR_setrlimit          145
-#define __NR_osf_old_killpg     146     /* not implemented */
-#define __NR_setsid             147
-#define __NR_quotactl           148
-#define __NR_osf_oldquota       149     /* not implemented */
-#define __NR_getsockname        150
-
-#define __NR_osf_pid_block      153     /* not implemented */
-#define __NR_osf_pid_unblock    154     /* not implemented */
-
-#define __NR_sigaction          156
-#define __NR_osf_sigwaitprim    157     /* not implemented */
-#define __NR_osf_nfssvc         158     /* not implemented */
-#define __NR_osf_getdirentries  159
-#define __NR_osf_statfs         160
-#define __NR_osf_fstatfs        161
-
-#define __NR_osf_asynch_daemon  163     /* not implemented */
-#define __NR_osf_getfh          164     /* not implemented */   
-#define __NR_osf_getdomainname  165
-#define __NR_setdomainname      166
-
-#define __NR_osf_exportfs       169     /* not implemented */
-
-#define __NR_osf_alt_plock      181     /* not implemented */
-
-#define __NR_osf_getmnt         184     /* not implemented */
-
-#define __NR_osf_alt_sigpending 187     /* not implemented */
-#define __NR_osf_alt_setsid     188     /* not implemented */
-
-#define __NR_osf_swapon         199
-#define __NR_msgctl             200
-#define __NR_msgget             201
-#define __NR_msgrcv             202
-#define __NR_msgsnd             203
-#define __NR_semctl             204
-#define __NR_semget             205
-#define __NR_semop              206
-#define __NR_osf_utsname        207
-#define __NR_lchown             208
-#define __NR_osf_shmat          209
-#define __NR_shmctl             210
-#define __NR_shmdt              211
-#define __NR_shmget             212
-#define __NR_osf_mvalid         213     /* not implemented */
-#define __NR_osf_getaddressconf 214     /* not implemented */
-#define __NR_osf_msleep         215     /* not implemented */
-#define __NR_osf_mwakeup        216     /* not implemented */
-#define __NR_msync              217
-#define __NR_osf_signal         218     /* not implemented */
-#define __NR_osf_utc_gettime    219     /* not implemented */
-#define __NR_osf_utc_adjtime    220     /* not implemented */
-
-#define __NR_osf_security       222     /* not implemented */
-#define __NR_osf_kloadcall      223     /* not implemented */
-
-#define __NR_getpgid            233
-#define __NR_getsid             234
-#define __NR_sigaltstack        235
-#define __NR_osf_waitid         236     /* not implemented */
-#define __NR_osf_priocntlset    237     /* not implemented */
-#define __NR_osf_sigsendset     238     /* not implemented */
-#define __NR_osf_set_speculative        239     /* not implemented */
-#define __NR_osf_msfs_syscall   240     /* not implemented */
-#define __NR_osf_sysinfo        241
-#define __NR_osf_uadmin         242     /* not implemented */
-#define __NR_osf_fuser          243     /* not implemented */
-#define __NR_osf_proplist_syscall    244
-#define __NR_osf_ntp_adjtime    245     /* not implemented */
-#define __NR_osf_ntp_gettime    246     /* not implemented */
-#define __NR_osf_pathconf       247     /* not implemented */
-#define __NR_osf_fpathconf      248     /* not implemented */
-
-#define __NR_osf_uswitch        250     /* not implemented */
-#define __NR_osf_usleep_thread  251
-#define __NR_osf_audcntl        252     /* not implemented */
-#define __NR_osf_audgen         253     /* not implemented */
-#define __NR_sysfs              254
-#define __NR_osf_subsys_info    255     /* not implemented */
-#define __NR_osf_getsysinfo     256
-#define __NR_osf_setsysinfo     257
-#define __NR_osf_afs_syscall    258     /* not implemented */
-#define __NR_osf_swapctl        259     /* not implemented */
-#define __NR_osf_memcntl        260     /* not implemented */
-#define __NR_osf_fdatasync      261     /* not implemented */
-
-/*
- * Ignore legacy syscalls that we don't use.
- */
-#define __IGNORE_alarm
-#define __IGNORE_creat
-#define __IGNORE_getegid
-#define __IGNORE_geteuid
-#define __IGNORE_getgid
-#define __IGNORE_getpid
-#define __IGNORE_getppid
-#define __IGNORE_getuid
-#define __IGNORE_pause
-#define __IGNORE_time
-#define __IGNORE_utime
-
-/*
- * Linux-specific system calls begin at 300
- */
-#define __NR_bdflush            300
-#define __NR_sethae             301
-#define __NR_mount              302
-#define __NR_old_adjtimex       303
-#define __NR_swapoff            304
-#define __NR_getdents           305
-#define __NR_create_module      306
-#define __NR_init_module        307
-#define __NR_delete_module      308
-#define __NR_get_kernel_syms    309
-#define __NR_syslog             310
-#define __NR_reboot             311
-#define __NR_clone              312
-#define __NR_uselib             313
-#define __NR_mlock              314
-#define __NR_munlock            315
-#define __NR_mlockall           316
-#define __NR_munlockall         317
-#define __NR_sysinfo            318
-#define __NR__sysctl            319
-/* 320 was sys_idle.  */
-#define __NR_oldumount          321
-#define __NR_swapon             322
-#define __NR_times              323
-#define __NR_personality        324
-#define __NR_setfsuid           325
-#define __NR_setfsgid           326
-#define __NR_ustat              327
-#define __NR_statfs             328
-#define __NR_fstatfs            329
-#define __NR_sched_setparam             330
-#define __NR_sched_getparam             331
-#define __NR_sched_setscheduler         332
-#define __NR_sched_getscheduler         333
-#define __NR_sched_yield                334
-#define __NR_sched_get_priority_max     335
-#define __NR_sched_get_priority_min     336
-#define __NR_sched_rr_get_interval      337
-#define __NR_afs_syscall                338
-#define __NR_uname                      339
-#define __NR_nanosleep                  340
-#define __NR_mremap                     341
-#define __NR_nfsservctl                 342
-#define __NR_setresuid                  343
-#define __NR_getresuid                  344
-#define __NR_pciconfig_read             345
-#define __NR_pciconfig_write            346
-#define __NR_query_module               347
-#define __NR_prctl                      348
-#define __NR_pread64                    349
-#define __NR_pwrite64                   350
-#define __NR_rt_sigreturn               351
-#define __NR_rt_sigaction               352
-#define __NR_rt_sigprocmask             353
-#define __NR_rt_sigpending              354
-#define __NR_rt_sigtimedwait            355
-#define __NR_rt_sigqueueinfo            356
-#define __NR_rt_sigsuspend              357
-#define __NR_select                     358
-#define __NR_gettimeofday               359
-#define __NR_settimeofday               360
-#define __NR_getitimer                  361
-#define __NR_setitimer                  362
-#define __NR_utimes                     363
-#define __NR_getrusage                  364
-#define __NR_wait4                      365
-#define __NR_adjtimex                   366
-#define __NR_getcwd                     367
-#define __NR_capget                     368
-#define __NR_capset                     369
-#define __NR_sendfile                   370
-#define __NR_setresgid                  371
-#define __NR_getresgid                  372
-#define __NR_dipc                       373
-#define __NR_pivot_root                 374
-#define __NR_mincore                    375
-#define __NR_pciconfig_iobase           376
-#define __NR_getdents64                 377
-#define __NR_gettid                     378
-#define __NR_readahead                  379
-/* 380 is unused */
-#define __NR_tkill                      381
-#define __NR_setxattr                   382
-#define __NR_lsetxattr                  383
-#define __NR_fsetxattr                  384
-#define __NR_getxattr                   385
-#define __NR_lgetxattr                  386
-#define __NR_fgetxattr                  387
-#define __NR_listxattr                  388
-#define __NR_llistxattr                 389
-#define __NR_flistxattr                 390
-#define __NR_removexattr                391
-#define __NR_lremovexattr               392
-#define __NR_fremovexattr               393
-#define __NR_futex                      394
-#define __NR_sched_setaffinity          395     
-#define __NR_sched_getaffinity          396
-#define __NR_tuxcall                    397
-#define __NR_io_setup                   398
-#define __NR_io_destroy                 399
-#define __NR_io_getevents               400
-#define __NR_io_submit                  401
-#define __NR_io_cancel                  402
-#define __NR_exit_group                 405
-#define __NR_lookup_dcookie             406
-#define __NR_epoll_create               407
-#define __NR_epoll_ctl                  408
-#define __NR_epoll_wait                 409
-/* Feb 2007: These three sys_epoll defines shouldn't be here but culling
- * them would break userspace apps ... we'll kill them off in 2010 :) */
-#define __NR_sys_epoll_create           __NR_epoll_create
-#define __NR_sys_epoll_ctl              __NR_epoll_ctl
-#define __NR_sys_epoll_wait             __NR_epoll_wait
-#define __NR_remap_file_pages           410
-#define __NR_set_tid_address            411
-#define __NR_restart_syscall            412
-#define __NR_fadvise64                  413
-#define __NR_timer_create               414
-#define __NR_timer_settime              415
-#define __NR_timer_gettime              416
-#define __NR_timer_getoverrun           417
-#define __NR_timer_delete               418
-#define __NR_clock_settime              419
-#define __NR_clock_gettime              420
-#define __NR_clock_getres               421
-#define __NR_clock_nanosleep            422
-#define __NR_semtimedop                 423
-#define __NR_tgkill                     424
-#define __NR_stat64                     425
-#define __NR_lstat64                    426
-#define __NR_fstat64                    427
-#define __NR_vserver                    428
-#define __NR_mbind                      429
-#define __NR_get_mempolicy              430
-#define __NR_set_mempolicy              431
-#define __NR_mq_open                    432
-#define __NR_mq_unlink                  433
-#define __NR_mq_timedsend               434
-#define __NR_mq_timedreceive            435
-#define __NR_mq_notify                  436
-#define __NR_mq_getsetattr              437
-#define __NR_waitid                     438
-#define __NR_add_key                    439
-#define __NR_request_key                440
-#define __NR_keyctl                     441
-#define __NR_ioprio_set                 442
-#define __NR_ioprio_get                 443
-#define __NR_inotify_init               444
-#define __NR_inotify_add_watch          445
-#define __NR_inotify_rm_watch           446
-#define __NR_fdatasync                  447
-#define __NR_kexec_load                 448
-#define __NR_migrate_pages              449
-#define __NR_openat                     450
-#define __NR_mkdirat                    451
-#define __NR_mknodat                    452
-#define __NR_fchownat                   453
-#define __NR_futimesat                  454
-#define __NR_fstatat64                  455
-#define __NR_unlinkat                   456
-#define __NR_renameat                   457
-#define __NR_linkat                     458
-#define __NR_symlinkat                  459
-#define __NR_readlinkat                 460
-#define __NR_fchmodat                   461
-#define __NR_faccessat                  462
-#define __NR_pselect6                   463
-#define __NR_ppoll                      464
-#define __NR_unshare                    465
-#define __NR_set_robust_list            466
-#define __NR_get_robust_list            467
-#define __NR_splice                     468
-#define __NR_sync_file_range            469
-#define __NR_tee                        470
-#define __NR_vmsplice                   471
-#define __NR_move_pages                 472
-#define __NR_getcpu                     473
-#define __NR_epoll_pwait                474
-#define __NR_utimensat                  475
-#define __NR_signalfd                   476
-#define __NR_timerfd                    477
-#define __NR_eventfd                    478
-
-#ifdef __KERNEL__
-
-#define NR_SYSCALLS                     479
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-
-/* "Conditional" syscalls.  What we want is
-
-        __attribute__((weak,alias("sys_ni_syscall")))
-
-   but that raises the problem of what type to give the symbol.  If we use
-   a prototype, it'll conflict with the definition given in this file and
-   others.  If we use __typeof, we discover that not all symbols actually
-   have declarations.  If we use no prototype, then we get warnings from
-   -Wstrict-prototypes.  Ho hum.  */
-
-#define cond_syscall(x)  asm(".weak\t" #x "\n" #x " = sys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _ALPHA_UNISTD_H */
diff --git a/include/asm-alpha/user.h b/include/asm-alpha/user.h
deleted file mode 100644
index a4eb6a4ca8d1..000000000000
--- a/include/asm-alpha/user.h
+++ /dev/null
@@ -1,53 +0,0 @@
-#ifndef _ALPHA_USER_H
-#define _ALPHA_USER_H
-
-#include <linux/sched.h>
-#include <linux/ptrace.h>
-
-#include <asm/page.h>
-#include <asm/reg.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd, NOT the osf-core).  The file contents
- * are as follows:
- *
- *  upage: 1 page consisting of a user struct that tells gdb
- *      what is present in the file.  Directly after this is a
- *      copy of the task_struct, which is currently not used by gdb,
- *      but it may come in handy at some point.  All of the registers
- *      are stored as part of the upage.  The upage should always be
- *      only one page long.
- *  data: The data segment follows next.  We use current->end_text to
- *      current->brk to pick up all of the user variables, plus any memory
- *      that may have been sbrk'ed.  No attempt is made to determine if a
- *      page is demand-zero or if a page is totally unused, we just cover
- *      the entire range.  All of the addresses are rounded in such a way
- *      that an integral number of pages is written.
- *  stack: We need the stack information in order to get a meaningful
- *      backtrace.  We need to write the data from usp to
- *      current->start_stack, so we round each of these in order to be able
- *      to write an integer number of pages.
- */
-struct user {
-        unsigned long   regs[EF_SIZE/8+32];     /* integer and fp regs */
-        size_t          u_tsize;                /* text size (pages) */
-        size_t          u_dsize;                /* data size (pages) */
-        size_t          u_ssize;                /* stack size (pages) */
-        unsigned long   start_code;             /* text starting address */
-        unsigned long   start_data;             /* data starting address */
-        unsigned long   start_stack;            /* stack starting address */
-        long int        signal;                 /* signal causing core dump */
-        unsigned long   u_ar0;                  /* help gdb find registers */
-        unsigned long   magic;                  /* identifies a core file */
-        char            u_comm[32];             /* user command name */
-};
-
-#define NBPG                    PAGE_SIZE
-#define UPAGES                  1
-#define HOST_TEXT_START_ADDR    (u.start_code)
-#define HOST_DATA_START_ADDR    (u.start_data)
-#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* _ALPHA_USER_H */
diff --git a/include/asm-alpha/vga.h b/include/asm-alpha/vga.h
deleted file mode 100644
index c00106bac521..000000000000
--- a/include/asm-alpha/vga.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- *      Access to VGA videoram
- *
- *      (c) 1998 Martin Mares <mj@ucw.cz>
- */
-
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
-
-#include <asm/io.h>
-
-#define VT_BUF_HAVE_RW
-#define VT_BUF_HAVE_MEMSETW
-#define VT_BUF_HAVE_MEMCPYW
-
-static inline void scr_writew(u16 val, volatile u16 *addr)
-{
-        if (__is_ioaddr(addr))
-                __raw_writew(val, (volatile u16 __iomem *) addr);
-        else
-                *addr = val;
-}
-
-static inline u16 scr_readw(volatile const u16 *addr)
-{
-        if (__is_ioaddr(addr))
-                return __raw_readw((volatile const u16 __iomem *) addr);
-        else
-                return *addr;
-}
-
-static inline void scr_memsetw(u16 *s, u16 c, unsigned int count)
-{
-        if (__is_ioaddr(s))
-                memsetw_io((u16 __iomem *) s, c, count);
-        else
-                memsetw(s, c, count);
-}
-
-/* Do not trust that the usage will be correct; analyze the arguments.  */
-extern void scr_memcpyw(u16 *d, const u16 *s, unsigned int count);
-
-/* ??? These are currently only used for downloading character sets.  As
-   such, they don't need memory barriers.  Is this all they are intended
-   to be used for?  */
-#define vga_readb(a)    readb((u8 __iomem *)(a))
-#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
-
-#ifdef CONFIG_VGA_HOSE
-#include <linux/ioport.h>
-#include <linux/pci.h>
-
-extern struct pci_controller *pci_vga_hose;
-
-# define __is_port_vga(a)       \
-        (((a) >= 0x3b0) && ((a) < 0x3e0) && \
-         ((a) != 0x3b3) && ((a) != 0x3d3))
-
-# define __is_mem_vga(a) \
-        (((a) >= 0xa0000) && ((a) <= 0xc0000))
-
-# define FIXUP_IOADDR_VGA(a) do {                       \
-        if (pci_vga_hose && __is_port_vga(a))     \
-                (a) += pci_vga_hose->io_space->start;     \
- } while(0)
-
-# define FIXUP_MEMADDR_VGA(a) do {                       \
-        if (pci_vga_hose && __is_mem_vga(a))     \
-                (a) += pci_vga_hose->mem_space->start; \
- } while(0)
-
-#else /* CONFIG_VGA_HOSE */
-# define pci_vga_hose 0
-# define __is_port_vga(a) 0
-# define __is_mem_vga(a) 0
-# define FIXUP_IOADDR_VGA(a)
-# define FIXUP_MEMADDR_VGA(a)
-#endif /* CONFIG_VGA_HOSE */
-
-#define VGA_MAP_MEM(x,s)        ((unsigned long) ioremap(x, s))
-
-#endif
diff --git a/include/asm-alpha/xor.h b/include/asm-alpha/xor.h
deleted file mode 100644
index 5ee1c2bc0499..000000000000
--- a/include/asm-alpha/xor.h
+++ /dev/null
@@ -1,855 +0,0 @@
-/*
- * include/asm-alpha/xor.h
- *
- * Optimized RAID-5 checksumming functions for alpha EV5 and EV6
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * You should have received a copy of the GNU General Public License
- * (for example /usr/src/linux/COPYING); if not, write to the Free
- * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-extern void xor_alpha_2(unsigned long, unsigned long *, unsigned long *);
-extern void xor_alpha_3(unsigned long, unsigned long *, unsigned long *,
-                        unsigned long *);
-extern void xor_alpha_4(unsigned long, unsigned long *, unsigned long *,
-                        unsigned long *, unsigned long *);
-extern void xor_alpha_5(unsigned long, unsigned long *, unsigned long *,
-                        unsigned long *, unsigned long *, unsigned long *);
-
-extern void xor_alpha_prefetch_2(unsigned long, unsigned long *,
-                                 unsigned long *);
-extern void xor_alpha_prefetch_3(unsigned long, unsigned long *,
-                                 unsigned long *, unsigned long *);
-extern void xor_alpha_prefetch_4(unsigned long, unsigned long *,
-                                 unsigned long *, unsigned long *,
-                                 unsigned long *);
-extern void xor_alpha_prefetch_5(unsigned long, unsigned long *,
-                                 unsigned long *, unsigned long *,
-                                 unsigned long *, unsigned long *);
-
-asm("                                                           \n\
-        .text                                                   \n\
-        .align 3                                                \n\
-        .ent xor_alpha_2                                        \n\
-xor_alpha_2:                                                    \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-        .align 4                                                \n\
-2:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,8($17)                                           \n\
-        ldq $3,8($18)                                           \n\
-                                                                \n\
-        ldq $4,16($17)                                          \n\
-        ldq $5,16($18)                                          \n\
-        ldq $6,24($17)                                          \n\
-        ldq $7,24($18)                                          \n\
-                                                                \n\
-        ldq $19,32($17)                                         \n\
-        ldq $20,32($18)                                         \n\
-        ldq $21,40($17)                                         \n\
-        ldq $22,40($18)                                         \n\
-                                                                \n\
-        ldq $23,48($17)                                         \n\
-        ldq $24,48($18)                                         \n\
-        ldq $25,56($17)                                         \n\
-        xor $0,$1,$0            # 7 cycles from $1 load         \n\
-                                                                \n\
-        ldq $27,56($18)                                         \n\
-        xor $2,$3,$2                                            \n\
-        stq $0,0($17)                                           \n\
-        xor $4,$5,$4                                            \n\
-                                                                \n\
-        stq $2,8($17)                                           \n\
-        xor $6,$7,$6                                            \n\
-        stq $4,16($17)                                          \n\
-        xor $19,$20,$19                                         \n\
-                                                                \n\
-        stq $6,24($17)                                          \n\
-        xor $21,$22,$21                                         \n\
-        stq $19,32($17)                                         \n\
-        xor $23,$24,$23                                         \n\
-                                                                \n\
-        stq $21,40($17)                                         \n\
-        xor $25,$27,$25                                         \n\
-        stq $23,48($17)                                         \n\
-        subq $16,1,$16                                          \n\
-                                                                \n\
-        stq $25,56($17)                                         \n\
-        addq $17,64,$17                                         \n\
-        addq $18,64,$18                                         \n\
-        bgt $16,2b                                              \n\
-                                                                \n\
-        ret                                                     \n\
-        .end xor_alpha_2                                        \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_3                                        \n\
-xor_alpha_3:                                                    \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-        .align 4                                                \n\
-3:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,0($19)                                           \n\
-        ldq $3,8($17)                                           \n\
-                                                                \n\
-        ldq $4,8($18)                                           \n\
-        ldq $6,16($17)                                          \n\
-        ldq $7,16($18)                                          \n\
-        ldq $21,24($17)                                         \n\
-                                                                \n\
-        ldq $22,24($18)                                         \n\
-        ldq $24,32($17)                                         \n\
-        ldq $25,32($18)                                         \n\
-        ldq $5,8($19)                                           \n\
-                                                                \n\
-        ldq $20,16($19)                                         \n\
-        ldq $23,24($19)                                         \n\
-        ldq $27,32($19)                                         \n\
-        nop                                                     \n\
-                                                                \n\
-        xor $0,$1,$1            # 8 cycles from $0 load         \n\
-        xor $3,$4,$4            # 6 cycles from $4 load         \n\
-        xor $6,$7,$7            # 6 cycles from $7 load         \n\
-        xor $21,$22,$22         # 5 cycles from $22 load        \n\
-                                                                \n\
-        xor $1,$2,$2            # 9 cycles from $2 load         \n\
-        xor $24,$25,$25         # 5 cycles from $25 load        \n\
-        stq $2,0($17)                                           \n\
-        xor $4,$5,$5            # 6 cycles from $5 load         \n\
-                                                                \n\
-        stq $5,8($17)                                           \n\
-        xor $7,$20,$20          # 7 cycles from $20 load        \n\
-        stq $20,16($17)                                         \n\
-        xor $22,$23,$23         # 7 cycles from $23 load        \n\
-                                                                \n\
-        stq $23,24($17)                                         \n\
-        xor $25,$27,$27         # 7 cycles from $27 load        \n\
-        stq $27,32($17)                                         \n\
-        nop                                                     \n\
-                                                                \n\
-        ldq $0,40($17)                                          \n\
-        ldq $1,40($18)                                          \n\
-        ldq $3,48($17)                                          \n\
-        ldq $4,48($18)                                          \n\
-                                                                \n\
-        ldq $6,56($17)                                          \n\
-        ldq $7,56($18)                                          \n\
-        ldq $2,40($19)                                          \n\
-        ldq $5,48($19)                                          \n\
-                                                                \n\
-        ldq $20,56($19)                                         \n\
-        xor $0,$1,$1            # 4 cycles from $1 load         \n\
-        xor $3,$4,$4            # 5 cycles from $4 load         \n\
-        xor $6,$7,$7            # 5 cycles from $7 load         \n\
-                                                                \n\
-        xor $1,$2,$2            # 4 cycles from $2 load         \n\
-        xor $4,$5,$5            # 5 cycles from $5 load         \n\
-        stq $2,40($17)                                          \n\
-        xor $7,$20,$20          # 4 cycles from $20 load        \n\
-                                                                \n\
-        stq $5,48($17)                                          \n\
-        subq $16,1,$16                                          \n\
-        stq $20,56($17)                                         \n\
-        addq $19,64,$19                                         \n\
-                                                                \n\
-        addq $18,64,$18                                         \n\
-        addq $17,64,$17                                         \n\
-        bgt $16,3b                                              \n\
-        ret                                                     \n\
-        .end xor_alpha_3                                        \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_4                                        \n\
-xor_alpha_4:                                                    \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-        .align 4                                                \n\
-4:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,0($19)                                           \n\
-        ldq $3,0($20)                                           \n\
-                                                                \n\
-        ldq $4,8($17)                                           \n\
-        ldq $5,8($18)                                           \n\
-        ldq $6,8($19)                                           \n\
-        ldq $7,8($20)                                           \n\
-                                                                \n\
-        ldq $21,16($17)                                         \n\
-        ldq $22,16($18)                                         \n\
-        ldq $23,16($19)                                         \n\
-        ldq $24,16($20)                                         \n\
-                                                                \n\
-        ldq $25,24($17)                                         \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-        ldq $27,24($18)                                         \n\
-        xor $2,$3,$3            # 6 cycles from $3 load         \n\
-                                                                \n\
-        ldq $0,24($19)                                          \n\
-        xor $1,$3,$3                                            \n\
-        ldq $1,24($20)                                          \n\
-        xor $4,$5,$5            # 7 cycles from $5 load         \n\
-                                                                \n\
-        stq $3,0($17)                                           \n\
-        xor $6,$7,$7                                            \n\
-        xor $21,$22,$22         # 7 cycles from $22 load        \n\
-        xor $5,$7,$7                                            \n\
-                                                                \n\
-        stq $7,8($17)                                           \n\
-        xor $23,$24,$24         # 7 cycles from $24 load        \n\
-        ldq $2,32($17)                                          \n\
-        xor $22,$24,$24                                         \n\
-                                                                \n\
-        ldq $3,32($18)                                          \n\
-        ldq $4,32($19)                                          \n\
-        ldq $5,32($20)                                          \n\
-        xor $25,$27,$27         # 8 cycles from $27 load        \n\
-                                                                \n\
-        ldq $6,40($17)                                          \n\
-        ldq $7,40($18)                                          \n\
-        ldq $21,40($19)                                         \n\
-        ldq $22,40($20)                                         \n\
-                                                                \n\
-        stq $24,16($17)                                         \n\
-        xor $0,$1,$1            # 9 cycles from $1 load         \n\
-        xor $2,$3,$3            # 5 cycles from $3 load         \n\
-        xor $27,$1,$1                                           \n\
-                                                                \n\
-        stq $1,24($17)                                          \n\
-        xor $4,$5,$5            # 5 cycles from $5 load         \n\
-        ldq $23,48($17)                                         \n\
-        ldq $24,48($18)                                         \n\
-                                                                \n\
-        ldq $25,48($19)                                         \n\
-        xor $3,$5,$5                                            \n\
-        ldq $27,48($20)                                         \n\
-        ldq $0,56($17)                                          \n\
-                                                                \n\
-        ldq $1,56($18)                                          \n\
-        ldq $2,56($19)                                          \n\
-        xor $6,$7,$7            # 8 cycles from $6 load         \n\
-        ldq $3,56($20)                                          \n\
-                                                                \n\
-        stq $5,32($17)                                          \n\
-        xor $21,$22,$22         # 8 cycles from $22 load        \n\
-        xor $7,$22,$22                                          \n\
-        xor $23,$24,$24         # 5 cycles from $24 load        \n\
-                                                                \n\
-        stq $22,40($17)                                         \n\
-        xor $25,$27,$27         # 5 cycles from $27 load        \n\
-        xor $24,$27,$27                                         \n\
-        xor $0,$1,$1            # 5 cycles from $1 load         \n\
-                                                                \n\
-        stq $27,48($17)                                         \n\
-        xor $2,$3,$3            # 4 cycles from $3 load         \n\
-        xor $1,$3,$3                                            \n\
-        subq $16,1,$16                                          \n\
-                                                                \n\
-        stq $3,56($17)                                          \n\
-        addq $20,64,$20                                         \n\
-        addq $19,64,$19                                         \n\
-        addq $18,64,$18                                         \n\
-                                                                \n\
-        addq $17,64,$17                                         \n\
-        bgt $16,4b                                              \n\
-        ret                                                     \n\
-        .end xor_alpha_4                                        \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_5                                        \n\
-xor_alpha_5:                                                    \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-        .align 4                                                \n\
-5:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,0($19)                                           \n\
-        ldq $3,0($20)                                           \n\
-                                                                \n\
-        ldq $4,0($21)                                           \n\
-        ldq $5,8($17)                                           \n\
-        ldq $6,8($18)                                           \n\
-        ldq $7,8($19)                                           \n\
-                                                                \n\
-        ldq $22,8($20)                                          \n\
-        ldq $23,8($21)                                          \n\
-        ldq $24,16($17)                                         \n\
-        ldq $25,16($18)                                         \n\
-                                                                \n\
-        ldq $27,16($19)                                         \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-        ldq $28,16($20)                                         \n\
-        xor $2,$3,$3            # 6 cycles from $3 load         \n\
-                                                                \n\
-        ldq $0,16($21)                                          \n\
-        xor $1,$3,$3                                            \n\
-        ldq $1,24($17)                                          \n\
-        xor $3,$4,$4            # 7 cycles from $4 load         \n\
-                                                                \n\
-        stq $4,0($17)                                           \n\
-        xor $5,$6,$6            # 7 cycles from $6 load         \n\
-        xor $7,$22,$22          # 7 cycles from $22 load        \n\
-        xor $6,$23,$23          # 7 cycles from $23 load        \n\
-                                                                \n\
-        ldq $2,24($18)                                          \n\
-        xor $22,$23,$23                                         \n\
-        ldq $3,24($19)                                          \n\
-        xor $24,$25,$25         # 8 cycles from $25 load        \n\
-                                                                \n\
-        stq $23,8($17)                                          \n\
-        xor $25,$27,$27         # 8 cycles from $27 load        \n\
-        ldq $4,24($20)                                          \n\
-        xor $28,$0,$0           # 7 cycles from $0 load         \n\
-                                                                \n\
-        ldq $5,24($21)                                          \n\
-        xor $27,$0,$0                                           \n\
-        ldq $6,32($17)                                          \n\
-        ldq $7,32($18)                                          \n\
-                                                                \n\
-        stq $0,16($17)                                          \n\
-        xor $1,$2,$2            # 6 cycles from $2 load         \n\
-        ldq $22,32($19)                                         \n\
-        xor $3,$4,$4            # 4 cycles from $4 load         \n\
-                                                                \n\
-        ldq $23,32($20)                                         \n\
-        xor $2,$4,$4                                            \n\
-        ldq $24,32($21)                                         \n\
-        ldq $25,40($17)                                         \n\
-                                                                \n\
-        ldq $27,40($18)                                         \n\
-        ldq $28,40($19)                                         \n\
-        ldq $0,40($20)                                          \n\
-        xor $4,$5,$5            # 7 cycles from $5 load         \n\
-                                                                \n\
-        stq $5,24($17)                                          \n\
-        xor $6,$7,$7            # 7 cycles from $7 load         \n\
-        ldq $1,40($21)                                          \n\
-        ldq $2,48($17)                                          \n\
-                                                                \n\
-        ldq $3,48($18)                                          \n\
-        xor $7,$22,$22          # 7 cycles from $22 load        \n\
-        ldq $4,48($19)                                          \n\
-        xor $23,$24,$24         # 6 cycles from $24 load        \n\
-                                                                \n\
-        ldq $5,48($20)                                          \n\
-        xor $22,$24,$24                                         \n\
-        ldq $6,48($21)                                          \n\
-        xor $25,$27,$27         # 7 cycles from $27 load        \n\
-                                                                \n\
-        stq $24,32($17)                                         \n\
-        xor $27,$28,$28         # 8 cycles from $28 load        \n\
-        ldq $7,56($17)                                          \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-                                                                \n\
-        ldq $22,56($18)                                         \n\
-        ldq $23,56($19)                                         \n\
-        ldq $24,56($20)                                         \n\
-        ldq $25,56($21)                                         \n\
-                                                                \n\
-        xor $28,$1,$1                                           \n\
-        xor $2,$3,$3            # 9 cycles from $3 load         \n\
-        xor $3,$4,$4            # 9 cycles from $4 load         \n\
-        xor $5,$6,$6            # 8 cycles from $6 load         \n\
-                                                                \n\
-        stq $1,40($17)                                          \n\
-        xor $4,$6,$6                                            \n\
-        xor $7,$22,$22          # 7 cycles from $22 load        \n\
-        xor $23,$24,$24         # 6 cycles from $24 load        \n\
-                                                                \n\
-        stq $6,48($17)                                          \n\
-        xor $22,$24,$24                                         \n\
-        subq $16,1,$16                                          \n\
-        xor $24,$25,$25         # 8 cycles from $25 load        \n\
-                                                                \n\
-        stq $25,56($17)                                         \n\
-        addq $21,64,$21                                         \n\
-        addq $20,64,$20                                         \n\
-        addq $19,64,$19                                         \n\
-                                                                \n\
-        addq $18,64,$18                                         \n\
-        addq $17,64,$17                                         \n\
-        bgt $16,5b                                              \n\
-        ret                                                     \n\
-        .end xor_alpha_5                                        \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_prefetch_2                               \n\
-xor_alpha_prefetch_2:                                           \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-                                                                \n\
-        ldq $31, 0($17)                                         \n\
-        ldq $31, 0($18)                                         \n\
-                                                                \n\
-        ldq $31, 64($17)                                        \n\
-        ldq $31, 64($18)                                        \n\
-                                                                \n\
-        ldq $31, 128($17)                                       \n\
-        ldq $31, 128($18)                                       \n\
-                                                                \n\
-        ldq $31, 192($17)                                       \n\
-        ldq $31, 192($18)                                       \n\
-        .align 4                                                \n\
-2:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,8($17)                                           \n\
-        ldq $3,8($18)                                           \n\
-                                                                \n\
-        ldq $4,16($17)                                          \n\
-        ldq $5,16($18)                                          \n\
-        ldq $6,24($17)                                          \n\
-        ldq $7,24($18)                                          \n\
-                                                                \n\
-        ldq $19,32($17)                                         \n\
-        ldq $20,32($18)                                         \n\
-        ldq $21,40($17)                                         \n\
-        ldq $22,40($18)                                         \n\
-                                                                \n\
-        ldq $23,48($17)                                         \n\
-        ldq $24,48($18)                                         \n\
-        ldq $25,56($17)                                         \n\
-        ldq $27,56($18)                                         \n\
-                                                                \n\
-        ldq $31,256($17)                                        \n\
-        xor $0,$1,$0            # 8 cycles from $1 load         \n\
-        ldq $31,256($18)                                        \n\
-        xor $2,$3,$2                                            \n\
-                                                                \n\
-        stq $0,0($17)                                           \n\
-        xor $4,$5,$4                                            \n\
-        stq $2,8($17)                                           \n\
-        xor $6,$7,$6                                            \n\
-                                                                \n\
-        stq $4,16($17)                                          \n\
-        xor $19,$20,$19                                         \n\
-        stq $6,24($17)                                          \n\
-        xor $21,$22,$21                                         \n\
-                                                                \n\
-        stq $19,32($17)                                         \n\
-        xor $23,$24,$23                                         \n\
-        stq $21,40($17)                                         \n\
-        xor $25,$27,$25                                         \n\
-                                                                \n\
-        stq $23,48($17)                                         \n\
-        subq $16,1,$16                                          \n\
-        stq $25,56($17)                                         \n\
-        addq $17,64,$17                                         \n\
-                                                                \n\
-        addq $18,64,$18                                         \n\
-        bgt $16,2b                                              \n\
-        ret                                                     \n\
-        .end xor_alpha_prefetch_2                               \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_prefetch_3                               \n\
-xor_alpha_prefetch_3:                                           \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-                                                                \n\
-        ldq $31, 0($17)                                         \n\
-        ldq $31, 0($18)                                         \n\
-        ldq $31, 0($19)                                         \n\
-                                                                \n\
-        ldq $31, 64($17)                                        \n\
-        ldq $31, 64($18)                                        \n\
-        ldq $31, 64($19)                                        \n\
-                                                                \n\
-        ldq $31, 128($17)                                       \n\
-        ldq $31, 128($18)                                       \n\
-        ldq $31, 128($19)                                       \n\
-                                                                \n\
-        ldq $31, 192($17)                                       \n\
-        ldq $31, 192($18)                                       \n\
-        ldq $31, 192($19)                                       \n\
-        .align 4                                                \n\
-3:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,0($19)                                           \n\
-        ldq $3,8($17)                                           \n\
-                                                                \n\
-        ldq $4,8($18)                                           \n\
-        ldq $6,16($17)                                          \n\
-        ldq $7,16($18)                                          \n\
-        ldq $21,24($17)                                         \n\
-                                                                \n\
-        ldq $22,24($18)                                         \n\
-        ldq $24,32($17)                                         \n\
-        ldq $25,32($18)                                         \n\
-        ldq $5,8($19)                                           \n\
-                                                                \n\
-        ldq $20,16($19)                                         \n\
-        ldq $23,24($19)                                         \n\
-        ldq $27,32($19)                                         \n\
-        nop                                                     \n\
-                                                                \n\
-        xor $0,$1,$1            # 8 cycles from $0 load         \n\
-        xor $3,$4,$4            # 7 cycles from $4 load         \n\
-        xor $6,$7,$7            # 6 cycles from $7 load         \n\
-        xor $21,$22,$22         # 5 cycles from $22 load        \n\
-                                                                \n\
-        xor $1,$2,$2            # 9 cycles from $2 load         \n\
-        xor $24,$25,$25         # 5 cycles from $25 load        \n\
-        stq $2,0($17)                                           \n\
-        xor $4,$5,$5            # 6 cycles from $5 load         \n\
-                                                                \n\
-        stq $5,8($17)                                           \n\
-        xor $7,$20,$20          # 7 cycles from $20 load        \n\
-        stq $20,16($17)                                         \n\
-        xor $22,$23,$23         # 7 cycles from $23 load        \n\
-                                                                \n\
-        stq $23,24($17)                                         \n\
-        xor $25,$27,$27         # 7 cycles from $27 load        \n\
-        stq $27,32($17)                                         \n\
-        nop                                                     \n\
-                                                                \n\
-        ldq $0,40($17)                                          \n\
-        ldq $1,40($18)                                          \n\
-        ldq $3,48($17)                                          \n\
-        ldq $4,48($18)                                          \n\
-                                                                \n\
-        ldq $6,56($17)                                          \n\
-        ldq $7,56($18)                                          \n\
-        ldq $2,40($19)                                          \n\
-        ldq $5,48($19)                                          \n\
-                                                                \n\
-        ldq $20,56($19)                                         \n\
-        ldq $31,256($17)                                        \n\
-        ldq $31,256($18)                                        \n\
-        ldq $31,256($19)                                        \n\
-                                                                \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-        xor $3,$4,$4            # 5 cycles from $4 load         \n\
-        xor $6,$7,$7            # 5 cycles from $7 load         \n\
-        xor $1,$2,$2            # 4 cycles from $2 load         \n\
-                                                                \n\
-        xor $4,$5,$5            # 5 cycles from $5 load         \n\
-        xor $7,$20,$20          # 4 cycles from $20 load        \n\
-        stq $2,40($17)                                          \n\
-        subq $16,1,$16                                          \n\
-                                                                \n\
-        stq $5,48($17)                                          \n\
-        addq $19,64,$19                                         \n\
-        stq $20,56($17)                                         \n\
-        addq $18,64,$18                                         \n\
-                                                                \n\
-        addq $17,64,$17                                         \n\
-        bgt $16,3b                                              \n\
-        ret                                                     \n\
-        .end xor_alpha_prefetch_3                               \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_prefetch_4                               \n\
-xor_alpha_prefetch_4:                                           \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-                                                                \n\
-        ldq $31, 0($17)                                         \n\
-        ldq $31, 0($18)                                         \n\
-        ldq $31, 0($19)                                         \n\
-        ldq $31, 0($20)                                         \n\
-                                                                \n\
-        ldq $31, 64($17)                                        \n\
-        ldq $31, 64($18)                                        \n\
-        ldq $31, 64($19)                                        \n\
-        ldq $31, 64($20)                                        \n\
-                                                                \n\
-        ldq $31, 128($17)                                       \n\
-        ldq $31, 128($18)                                       \n\
-        ldq $31, 128($19)                                       \n\
-        ldq $31, 128($20)                                       \n\
-                                                                \n\
-        ldq $31, 192($17)                                       \n\
-        ldq $31, 192($18)                                       \n\
-        ldq $31, 192($19)                                       \n\
-        ldq $31, 192($20)                                       \n\
-        .align 4                                                \n\
-4:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,0($19)                                           \n\
-        ldq $3,0($20)                                           \n\
-                                                                \n\
-        ldq $4,8($17)                                           \n\
-        ldq $5,8($18)                                           \n\
-        ldq $6,8($19)                                           \n\
-        ldq $7,8($20)                                           \n\
-                                                                \n\
-        ldq $21,16($17)                                         \n\
-        ldq $22,16($18)                                         \n\
-        ldq $23,16($19)                                         \n\
-        ldq $24,16($20)                                         \n\
-                                                                \n\
-        ldq $25,24($17)                                         \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-        ldq $27,24($18)                                         \n\
-        xor $2,$3,$3            # 6 cycles from $3 load         \n\
-                                                                \n\
-        ldq $0,24($19)                                          \n\
-        xor $1,$3,$3                                            \n\
-        ldq $1,24($20)                                          \n\
-        xor $4,$5,$5            # 7 cycles from $5 load         \n\
-                                                                \n\
-        stq $3,0($17)                                           \n\
-        xor $6,$7,$7                                            \n\
-        xor $21,$22,$22         # 7 cycles from $22 load        \n\
-        xor $5,$7,$7                                            \n\
-                                                                \n\
-        stq $7,8($17)                                           \n\
-        xor $23,$24,$24         # 7 cycles from $24 load        \n\
-        ldq $2,32($17)                                          \n\
-        xor $22,$24,$24                                         \n\
-                                                                \n\
-        ldq $3,32($18)                                          \n\
-        ldq $4,32($19)                                          \n\
-        ldq $5,32($20)                                          \n\
-        xor $25,$27,$27         # 8 cycles from $27 load        \n\
-                                                                \n\
-        ldq $6,40($17)                                          \n\
-        ldq $7,40($18)                                          \n\
-        ldq $21,40($19)                                         \n\
-        ldq $22,40($20)                                         \n\
-                                                                \n\
-        stq $24,16($17)                                         \n\
-        xor $0,$1,$1            # 9 cycles from $1 load         \n\
-        xor $2,$3,$3            # 5 cycles from $3 load         \n\
-        xor $27,$1,$1                                           \n\
-                                                                \n\
-        stq $1,24($17)                                          \n\
-        xor $4,$5,$5            # 5 cycles from $5 load         \n\
-        ldq $23,48($17)                                         \n\
-        xor $3,$5,$5                                            \n\
-                                                                \n\
-        ldq $24,48($18)                                         \n\
-        ldq $25,48($19)                                         \n\
-        ldq $27,48($20)                                         \n\
-        ldq $0,56($17)                                          \n\
-                                                                \n\
-        ldq $1,56($18)                                          \n\
-        ldq $2,56($19)                                          \n\
-        ldq $3,56($20)                                          \n\
-        xor $6,$7,$7            # 8 cycles from $6 load         \n\
-                                                                \n\
-        ldq $31,256($17)                                        \n\
-        xor $21,$22,$22         # 8 cycles from $22 load        \n\
-        ldq $31,256($18)                                        \n\
-        xor $7,$22,$22                                          \n\
-                                                                \n\
-        ldq $31,256($19)                                        \n\
-        xor $23,$24,$24         # 6 cycles from $24 load        \n\
-        ldq $31,256($20)                                        \n\
-        xor $25,$27,$27         # 6 cycles from $27 load        \n\
-                                                                \n\
-        stq $5,32($17)                                          \n\
-        xor $24,$27,$27                                         \n\
-        xor $0,$1,$1            # 7 cycles from $1 load         \n\
-        xor $2,$3,$3            # 6 cycles from $3 load         \n\
-                                                                \n\
-        stq $22,40($17)                                         \n\
-        xor $1,$3,$3                                            \n\
-        stq $27,48($17)                                         \n\
-        subq $16,1,$16                                          \n\
-                                                                \n\
-        stq $3,56($17)                                          \n\
-        addq $20,64,$20                                         \n\
-        addq $19,64,$19                                         \n\
-        addq $18,64,$18                                         \n\
-                                                                \n\
-        addq $17,64,$17                                         \n\
-        bgt $16,4b                                              \n\
-        ret                                                     \n\
-        .end xor_alpha_prefetch_4                               \n\
-                                                                \n\
-        .align 3                                                \n\
-        .ent xor_alpha_prefetch_5                               \n\
-xor_alpha_prefetch_5:                                           \n\
-        .prologue 0                                             \n\
-        srl $16, 6, $16                                         \n\
-                                                                \n\
-        ldq $31, 0($17)                                         \n\
-        ldq $31, 0($18)                                         \n\
-        ldq $31, 0($19)                                         \n\
-        ldq $31, 0($20)                                         \n\
-        ldq $31, 0($21)                                         \n\
-                                                                \n\
-        ldq $31, 64($17)                                        \n\
-        ldq $31, 64($18)                                        \n\
-        ldq $31, 64($19)                                        \n\
-        ldq $31, 64($20)                                        \n\
-        ldq $31, 64($21)                                        \n\
-                                                                \n\
-        ldq $31, 128($17)                                       \n\
-        ldq $31, 128($18)                                       \n\
-        ldq $31, 128($19)                                       \n\
-        ldq $31, 128($20)                                       \n\
-        ldq $31, 128($21)                                       \n\
-                                                                \n\
-        ldq $31, 192($17)                                       \n\
-        ldq $31, 192($18)                                       \n\
-        ldq $31, 192($19)                                       \n\
-        ldq $31, 192($20)                                       \n\
-        ldq $31, 192($21)                                       \n\
-        .align 4                                                \n\
-5:                                                              \n\
-        ldq $0,0($17)                                           \n\
-        ldq $1,0($18)                                           \n\
-        ldq $2,0($19)                                           \n\
-        ldq $3,0($20)                                           \n\
-                                                                \n\
-        ldq $4,0($21)                                           \n\
-        ldq $5,8($17)                                           \n\
-        ldq $6,8($18)                                           \n\
-        ldq $7,8($19)                                           \n\
-                                                                \n\
-        ldq $22,8($20)                                          \n\
-        ldq $23,8($21)                                          \n\
-        ldq $24,16($17)                                         \n\
-        ldq $25,16($18)                                         \n\
-                                                                \n\
-        ldq $27,16($19)                                         \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-        ldq $28,16($20)                                         \n\
-        xor $2,$3,$3            # 6 cycles from $3 load         \n\
-                                                                \n\
-        ldq $0,16($21)                                          \n\
-        xor $1,$3,$3                                            \n\
-        ldq $1,24($17)                                          \n\
-        xor $3,$4,$4            # 7 cycles from $4 load         \n\
-                                                                \n\
-        stq $4,0($17)                                           \n\
-        xor $5,$6,$6            # 7 cycles from $6 load         \n\
-        xor $7,$22,$22          # 7 cycles from $22 load        \n\
-        xor $6,$23,$23          # 7 cycles from $23 load        \n\
-                                                                \n\
-        ldq $2,24($18)                                          \n\
-        xor $22,$23,$23                                         \n\
-        ldq $3,24($19)                                          \n\
-        xor $24,$25,$25         # 8 cycles from $25 load        \n\
-                                                                \n\
-        stq $23,8($17)                                          \n\
-        xor $25,$27,$27         # 8 cycles from $27 load        \n\
-        ldq $4,24($20)                                          \n\
-        xor $28,$0,$0           # 7 cycles from $0 load         \n\
-                                                                \n\
-        ldq $5,24($21)                                          \n\
-        xor $27,$0,$0                                           \n\
-        ldq $6,32($17)                                          \n\
-        ldq $7,32($18)                                          \n\
-                                                                \n\
-        stq $0,16($17)                                          \n\
-        xor $1,$2,$2            # 6 cycles from $2 load         \n\
-        ldq $22,32($19)                                         \n\
-        xor $3,$4,$4            # 4 cycles from $4 load         \n\
-                                                                \n\
-        ldq $23,32($20)                                         \n\
-        xor $2,$4,$4                                            \n\
-        ldq $24,32($21)                                         \n\
-        ldq $25,40($17)                                         \n\
-                                                                \n\
-        ldq $27,40($18)                                         \n\
-        ldq $28,40($19)                                         \n\
-        ldq $0,40($20)                                          \n\
-        xor $4,$5,$5            # 7 cycles from $5 load         \n\
-                                                                \n\
-        stq $5,24($17)                                          \n\
-        xor $6,$7,$7            # 7 cycles from $7 load         \n\
-        ldq $1,40($21)                                          \n\
-        ldq $2,48($17)                                          \n\
-                                                                \n\
-        ldq $3,48($18)                                          \n\
-        xor $7,$22,$22          # 7 cycles from $22 load        \n\
-        ldq $4,48($19)                                          \n\
-        xor $23,$24,$24         # 6 cycles from $24 load        \n\
-                                                                \n\
-        ldq $5,48($20)                                          \n\
-        xor $22,$24,$24                                         \n\
-        ldq $6,48($21)                                          \n\
-        xor $25,$27,$27         # 7 cycles from $27 load        \n\
-                                                                \n\
-        stq $24,32($17)                                         \n\
-        xor $27,$28,$28         # 8 cycles from $28 load        \n\
-        ldq $7,56($17)                                          \n\
-        xor $0,$1,$1            # 6 cycles from $1 load         \n\
-                                                                \n\
-        ldq $22,56($18)                                         \n\
-        ldq $23,56($19)                                         \n\
-        ldq $24,56($20)                                         \n\
-        ldq $25,56($21)                                         \n\
-                                                                \n\
-        ldq $31,256($17)                                        \n\
-        xor $28,$1,$1                                           \n\
-        ldq $31,256($18)                                        \n\
-        xor $2,$3,$3            # 9 cycles from $3 load         \n\
-                                                                \n\
-        ldq $31,256($19)                                        \n\
-        xor $3,$4,$4            # 9 cycles from $4 load         \n\
-        ldq $31,256($20)                                        \n\
-        xor $5,$6,$6            # 8 cycles from $6 load         \n\
-                                                                \n\
-        stq $1,40($17)                                          \n\
-        xor $4,$6,$6                                            \n\
-        xor $7,$22,$22          # 7 cycles from $22 load        \n\
-        xor $23,$24,$24         # 6 cycles from $24 load        \n\
-                                                                \n\
-        stq $6,48($17)                                          \n\
-        xor $22,$24,$24                                         \n\
-        ldq $31,256($21)                                        \n\
-        xor $24,$25,$25         # 8 cycles from $25 load        \n\
-                                                                \n\
-        stq $25,56($17)                                         \n\
-        subq $16,1,$16                                          \n\
-        addq $21,64,$21                                         \n\
-        addq $20,64,$20                                         \n\
-                                                                \n\
-        addq $19,64,$19                                         \n\
-        addq $18,64,$18                                         \n\
-        addq $17,64,$17                                         \n\
-        bgt $16,5b                                              \n\
-                                                                \n\
-        ret                                                     \n\
-        .end xor_alpha_prefetch_5                               \n\
-");
-
-static struct xor_block_template xor_block_alpha = {
-        .name   = "alpha",
-        .do_2   = xor_alpha_2,
-        .do_3   = xor_alpha_3,
-        .do_4   = xor_alpha_4,
-        .do_5   = xor_alpha_5,
-};
-
-static struct xor_block_template xor_block_alpha_prefetch = {
-        .name   = "alpha prefetch",
-        .do_2   = xor_alpha_prefetch_2,
-        .do_3   = xor_alpha_prefetch_3,
-        .do_4   = xor_alpha_prefetch_4,
-        .do_5   = xor_alpha_prefetch_5,
-};
-
-/* For grins, also test the generic routines.  */
-#include <asm-generic/xor.h>
-
-#undef XOR_TRY_TEMPLATES
-#define XOR_TRY_TEMPLATES                               \
-        do {                                            \
-                xor_speed(&xor_block_8regs);            \
-                xor_speed(&xor_block_32regs);           \
-                xor_speed(&xor_block_alpha);            \
-                xor_speed(&xor_block_alpha_prefetch);   \
-        } while (0)
-
-/* Force the use of alpha_prefetch if EV6, as it is significantly
-   faster in the cold cache case.  */
-#define XOR_SELECT_TEMPLATE(FASTEST) \
-        (implver() == IMPLVER_EV6 ? &xor_block_alpha_prefetch : FASTEST)
diff --git a/include/asm-arm/plat-orion/cache-feroceon-l2.h b/include/asm-arm/plat-orion/cache-feroceon-l2.h
deleted file mode 100644
index ba4e016d3ec0..000000000000
--- a/include/asm-arm/plat-orion/cache-feroceon-l2.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * include/asm-arm/plat-orion/cache-feroceon-l2.h
- *
- * Copyright (C) 2008 Marvell Semiconductor
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-extern void __init feroceon_l2_init(int l2_wt_override);
diff --git a/include/asm-arm/plat-orion/ehci-orion.h b/include/asm-arm/plat-orion/ehci-orion.h
deleted file mode 100644
index 785705651e24..000000000000
--- a/include/asm-arm/plat-orion/ehci-orion.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * include/asm-arm/plat-orion/ehci-orion.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_PLAT_ORION_EHCI_ORION_H
-#define __ASM_PLAT_ORION_EHCI_ORION_H
-
-#include <linux/mbus.h>
-
-struct orion_ehci_data {
-        struct mbus_dram_target_info    *dram;
-};
-
-
-#endif
diff --git a/include/asm-arm/plat-orion/irq.h b/include/asm-arm/plat-orion/irq.h
deleted file mode 100644
index 94aeed919d5b..000000000000
--- a/include/asm-arm/plat-orion/irq.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * include/asm-arm/plat-orion/irq.h
- *
- * Marvell Orion SoC IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_PLAT_ORION_IRQ_H
-#define __ASM_PLAT_ORION_IRQ_H
-
-void orion_irq_init(unsigned int irq_start, void __iomem *maskaddr);
-
-
-#endif
diff --git a/include/asm-arm/plat-orion/mv_xor.h b/include/asm-arm/plat-orion/mv_xor.h
deleted file mode 100644
index c349e8ff5cc0..000000000000
--- a/include/asm-arm/plat-orion/mv_xor.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Marvell XOR platform device data definition file.
- */
-
-#ifndef __ASM_PLAT_ORION_MV_XOR_H
-#define __ASM_PLAT_ORION_MV_XOR_H
-
-#include <linux/dmaengine.h>
-#include <linux/mbus.h>
-
-#define MV_XOR_SHARED_NAME      "mv_xor_shared"
-#define MV_XOR_NAME             "mv_xor"
-
-struct mbus_dram_target_info;
-
-struct mv_xor_platform_shared_data {
-        struct mbus_dram_target_info    *dram;
-};
-
-struct mv_xor_platform_data {
-        struct platform_device          *shared;
-        int                             hw_id;
-        dma_cap_mask_t                  cap_mask;
-        size_t                          pool_size;
-};
-
-
-#endif
diff --git a/include/asm-arm/plat-orion/orion_nand.h b/include/asm-arm/plat-orion/orion_nand.h
deleted file mode 100644
index ad4ce94c1998..000000000000
--- a/include/asm-arm/plat-orion/orion_nand.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * include/asm-arm/plat-orion/orion_nand.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_PLAT_ORION_ORION_NAND_H
-#define __ASM_PLAT_ORION_ORION_NAND_H
-
-/*
- * Device bus NAND private data
- */
-struct orion_nand_data {
-        struct mtd_partition *parts;
-        u32 nr_parts;
-        u8 ale;         /* address line number connected to ALE */
-        u8 cle;         /* address line number connected to CLE */
-        u8 width;       /* buswidth */
-        u8 chip_delay;
-};
-
-
-#endif
diff --git a/include/asm-arm/plat-orion/pcie.h b/include/asm-arm/plat-orion/pcie.h
deleted file mode 100644
index e61b7bd97af5..000000000000
--- a/include/asm-arm/plat-orion/pcie.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * include/asm-arm/plat-orion/pcie.h
- *
- * Marvell Orion SoC PCIe handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_PLAT_ORION_PCIE_H
-#define __ASM_PLAT_ORION_PCIE_H
-
-u32 orion_pcie_dev_id(void __iomem *base);
-u32 orion_pcie_rev(void __iomem *base);
-int orion_pcie_link_up(void __iomem *base);
-int orion_pcie_x4_mode(void __iomem *base);
-int orion_pcie_get_local_bus_nr(void __iomem *base);
-void orion_pcie_set_local_bus_nr(void __iomem *base, int nr);
-void orion_pcie_setup(void __iomem *base,
-                      struct mbus_dram_target_info *dram);
-int orion_pcie_rd_conf(void __iomem *base, struct pci_bus *bus,
-                       u32 devfn, int where, int size, u32 *val);
-int orion_pcie_rd_conf_tlp(void __iomem *base, struct pci_bus *bus,
-                           u32 devfn, int where, int size, u32 *val);
-int orion_pcie_rd_conf_wa(void __iomem *wa_base, struct pci_bus *bus,
-                          u32 devfn, int where, int size, u32 *val);
-int orion_pcie_wr_conf(void __iomem *base, struct pci_bus *bus,
-                       u32 devfn, int where, int size, u32 val);
-
-
-#endif
diff --git a/include/asm-arm/plat-orion/time.h b/include/asm-arm/plat-orion/time.h
deleted file mode 100644
index 0e85cc8f44d9..000000000000
--- a/include/asm-arm/plat-orion/time.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * include/asm-arm/plat-orion/time.h
- *
- * Marvell Orion SoC time handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_PLAT_ORION_TIME_H
-#define __ASM_PLAT_ORION_TIME_H
-
-void orion_time_init(unsigned int irq, unsigned int tclk);
-
-
-#endif
diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index 09f0b5503f5b..b2caa4bca270 100644
--- a/include/asm-arm/plat-s3c/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
@@ -11,7 +11,7 @@
 */
 
 #ifndef __ASM_ARM_REGS_NAND
-#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
+#define __ASM_ARM_REGS_NAND
 
 
 #define S3C2410_NFREG(x) (x)
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index b4366ea39677..cc0eedd53e38 100644
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -12,7 +12,7 @@
 
 
 #ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
+#define __ASM_ARCH_REGS_TIMER_H
 
 #define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
 #define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
diff --git a/include/asm-arm/plat-s3c/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
index 1229f076c0a0..4938492470f7 100644
--- a/include/asm-arm/plat-s3c/regs-watchdog.h
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -12,7 +12,7 @@
 
 
 #ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
+#define __ASM_ARCH_REGS_WATCHDOG_H
 
 #define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
 
diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/include/asm-arm/plat-s3c24xx/s3c2410.h
index 36de0b835873..3cd1ec677b3f 100644
--- a/include/asm-arm/plat-s3c24xx/s3c2410.h
+++ b/include/asm-arm/plat-s3c24xx/s3c2410.h
@@ -21,11 +21,11 @@ extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
 extern void s3c2410_init_clocks(int xtal);
 
-extern  int s3c2410_baseclk_add(void);
-
 #else
 #define s3c2410_init_clocks NULL
 #define s3c2410_init_uarts NULL
 #define s3c2410_map_io NULL
 #define s3c2410_init NULL
 #endif
+
+extern int s3c2410_baseclk_add(void);
diff --git a/include/asm-blackfin/.gitignore b/include/asm-blackfin/.gitignore
deleted file mode 100644
index 7858564a4466..000000000000
--- a/include/asm-blackfin/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-+mach
diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild
deleted file mode 100644
index 71f8fe783258..000000000000
--- a/include/asm-blackfin/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += fixed_code.h
diff --git a/include/asm-blackfin/a.out.h b/include/asm-blackfin/a.out.h
deleted file mode 100644
index 6c3d652ebd33..000000000000
--- a/include/asm-blackfin/a.out.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __BFIN_A_OUT_H__
-#define __BFIN_A_OUT_H__
-
-struct exec {
-        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
-        unsigned a_text;        /* length of text, in bytes */
-        unsigned a_data;        /* length of data, in bytes */
-        unsigned a_bss;         /* length of uninitialized data area for file, in bytes */
-        unsigned a_syms;        /* length of symbol table data in file, in bytes */
-        unsigned a_entry;       /* start address */
-        unsigned a_trsize;      /* length of relocation info for text, in bytes */
-        unsigned a_drsize;      /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif                          /* __BFIN_A_OUT_H__ */
diff --git a/include/asm-blackfin/atomic.h b/include/asm-blackfin/atomic.h
deleted file mode 100644
index 7cf508718605..000000000000
--- a/include/asm-blackfin/atomic.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __ARCH_BLACKFIN_ATOMIC__
-#define __ARCH_BLACKFIN_ATOMIC__
-
-#include <asm/system.h> /* local_irq_XXX() */
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- *
- * Generally we do not concern about SMP BFIN systems, so we don't have
- * to deal with that.
- *
- * Tony Kou (tonyko@lineo.ca)   Lineo Inc.   2001
- */
-
-typedef struct {
-        int counter;
-} atomic_t;
-#define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v)          ((v)->counter)
-#define atomic_set(v, i)        (((v)->counter) = i)
-
-static __inline__ void atomic_add(int i, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter += i;
-        local_irq_restore(flags);
-}
-
-static __inline__ void atomic_sub(int i, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter -= i;
-        local_irq_restore(flags);
-
-}
-
-static inline int atomic_add_return(int i, atomic_t * v)
-{
-        int __temp = 0;
-        long flags;
-
-        local_irq_save(flags);
-        v->counter += i;
-        __temp = v->counter;
-        local_irq_restore(flags);
-
-
-        return __temp;
-}
-
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-static inline int atomic_sub_return(int i, atomic_t * v)
-{
-        int __temp = 0;
-        long flags;
-
-        local_irq_save(flags);
-        v->counter -= i;
-        __temp = v->counter;
-        local_irq_restore(flags);
-
-        return __temp;
-}
-
-static __inline__ void atomic_inc(volatile atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter++;
-        local_irq_restore(flags);
-}
-
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-static __inline__ void atomic_dec(volatile atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter--;
-        local_irq_restore(flags);
-}
-
-static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter &= ~mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter |= mask;
-        local_irq_restore(flags);
-}
-
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec()    barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc()    barrier()
-#define smp_mb__after_atomic_inc() barrier()
-
-#define atomic_dec_return(v) atomic_sub_return(1,(v))
-#define atomic_inc_return(v) atomic_add_return(1,(v))
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
-#include <asm-generic/atomic.h>
-
-#endif                          /* __ARCH_BLACKFIN_ATOMIC __ */
diff --git a/include/asm-blackfin/auxvec.h b/include/asm-blackfin/auxvec.h
deleted file mode 100644
index 215506cd87b7..000000000000
--- a/include/asm-blackfin/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASMBFIN_AUXVEC_H
-#define __ASMBFIN_AUXVEC_H
-
-#endif
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
deleted file mode 100644
index 320aa5e167e9..000000000000
--- a/include/asm-blackfin/bfin-global.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * File:         include/asm-blackfin/bfin-global.h
- * Based on:
- * Author: *
- * Created:
- * Description:  Global extern defines for blackfin
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _BFIN_GLOBAL_H_
-#define _BFIN_GLOBAL_H_
-
-#ifndef __ASSEMBLY__
-
-#include <asm-generic/sections.h>
-#include <asm/ptrace.h>
-#include <asm/user.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_DMA_UNCACHED_4M)
-# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_2M)
-# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_1M)
-# define DMA_UNCACHED_REGION (1024 * 1024)
-#else
-# define DMA_UNCACHED_REGION (0)
-#endif
-
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
-extern unsigned long sclk_to_usecs(unsigned long sclk);
-extern unsigned long usecs_to_sclk(unsigned long usecs);
-
-extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(struct pt_regs *regs);
-extern void dump_bfin_trace_buffer(void);
-
-extern int init_arch_irq(void);
-extern void bfin_reset(void);
-extern void _cplb_hdr(void);
-/* Blackfin cache functions */
-extern void bfin_icache_init(void);
-extern void bfin_dcache_init(void);
-extern int read_iloc(void);
-extern int bfin_console_init(void);
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern void init_exception_vectors(void);
-extern void init_dma(void);
-extern void program_IAR(void);
-extern void evt14_softirq(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-extern asmlinkage void finish_atomic_sections (struct pt_regs *regs);
-extern char fixed_code_start;
-extern char fixed_code_end;
-extern int atomic_xchg32(void);
-extern int atomic_cas32(void);
-extern int atomic_add32(void);
-extern int atomic_sub32(void);
-extern int atomic_ior32(void);
-extern int atomic_and32(void);
-extern int atomic_xor32(void);
-extern void safe_user_instruction(void);
-extern void sigreturn_stub(void);
-
-extern void *l1_data_A_sram_alloc(size_t);
-extern void *l1_data_B_sram_alloc(size_t);
-extern void *l1_inst_sram_alloc(size_t);
-extern void *l1_data_sram_alloc(size_t);
-extern void *l1_data_sram_zalloc(size_t);
-extern void *l2_sram_alloc(size_t);
-extern void *l2_sram_zalloc(size_t);
-extern int l1_data_A_sram_free(const void*);
-extern int l1_data_B_sram_free(const void*);
-extern int l1_inst_sram_free(const void*);
-extern int l1_data_sram_free(const void*);
-extern int l2_sram_free(const void *);
-extern int sram_free(const void*);
-
-#define L1_INST_SRAM            0x00000001
-#define L1_DATA_A_SRAM          0x00000002
-#define L1_DATA_B_SRAM          0x00000004
-#define L1_DATA_SRAM            0x00000006
-#define L2_SRAM                 0x00000008
-extern void *sram_alloc_with_lsl(size_t, unsigned long);
-extern int sram_free_with_lsl(const void*);
-
-extern const char bfin_board_name[];
-extern unsigned long wall_jiffies;
-
-extern unsigned long bfin_sic_iwr[];
-extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-extern struct file_operations dpmc_fops;
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
-        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[],
-        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
-        _ebss_l2[], _l2_lma_start[];
-
-#ifdef CONFIG_MTD_UCLINUX
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
-#endif
-
-#endif
-
-#endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
deleted file mode 100644
index 9fa19158e38d..000000000000
--- a/include/asm-blackfin/bfin5xx_spi.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/************************************************************
-
-* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
-*
-* FILE bfin5xx_spi.h
-* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
-*
-*
-* DATE OF CREATION: March. 10th 2006
-*
-* SYNOPSIS:
-*
-* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
-**************************************************************
-
-* MODIFICATION HISTORY:
-* March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
-
-************************************************************/
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#define SPI_READ              0
-#define SPI_WRITE             1
-
-#define SPI_CTRL_OFF            0x0
-#define SPI_FLAG_OFF            0x4
-#define SPI_STAT_OFF            0x8
-#define SPI_TXBUFF_OFF          0xc
-#define SPI_RXBUFF_OFF          0x10
-#define SPI_BAUD_OFF            0x14
-#define SPI_SHAW_OFF            0x18
-
-
-#define BIT_CTL_ENABLE      0x4000
-#define BIT_CTL_OPENDRAIN   0x2000
-#define BIT_CTL_MASTER      0x1000
-#define BIT_CTL_POLAR       0x0800
-#define BIT_CTL_PHASE       0x0400
-#define BIT_CTL_BITORDER    0x0200
-#define BIT_CTL_WORDSIZE    0x0100
-#define BIT_CTL_MISOENABLE  0x0020
-#define BIT_CTL_RXMOD       0x0000
-#define BIT_CTL_TXMOD       0x0001
-#define BIT_CTL_TIMOD_DMA_TX 0x0003
-#define BIT_CTL_TIMOD_DMA_RX 0x0002
-#define BIT_CTL_SENDOPT     0x0004
-#define BIT_CTL_TIMOD       0x0003
-
-#define BIT_STAT_SPIF       0x0001
-#define BIT_STAT_MODF       0x0002
-#define BIT_STAT_TXE        0x0004
-#define BIT_STAT_TXS        0x0008
-#define BIT_STAT_RBSY       0x0010
-#define BIT_STAT_RXS        0x0020
-#define BIT_STAT_TXCOL      0x0040
-#define BIT_STAT_CLR        0xFFFF
-
-#define BIT_STU_SENDOVER    0x0001
-#define BIT_STU_RECVFULL    0x0020
-
-#define CFG_SPI_ENABLE      1
-#define CFG_SPI_DISABLE     0
-
-#define CFG_SPI_OUTENABLE   1
-#define CFG_SPI_OUTDISABLE  0
-
-#define CFG_SPI_ACTLOW      1
-#define CFG_SPI_ACTHIGH     0
-
-#define CFG_SPI_PHASESTART  1
-#define CFG_SPI_PHASEMID    0
-
-#define CFG_SPI_MASTER      1
-#define CFG_SPI_SLAVE       0
-
-#define CFG_SPI_SENELAST    0
-#define CFG_SPI_SENDZERO    1
-
-#define CFG_SPI_RCVFLUSH    1
-#define CFG_SPI_RCVDISCARD  0
-
-#define CFG_SPI_LSBFIRST    1
-#define CFG_SPI_MSBFIRST    0
-
-#define CFG_SPI_WORDSIZE16  1
-#define CFG_SPI_WORDSIZE8   0
-
-#define CFG_SPI_MISOENABLE   1
-#define CFG_SPI_MISODISABLE  0
-
-#define CFG_SPI_READ      0x00
-#define CFG_SPI_WRITE     0x01
-#define CFG_SPI_DMAREAD   0x02
-#define CFG_SPI_DMAWRITE  0x03
-
-#define CFG_SPI_CSCLEARALL  0
-#define CFG_SPI_CHIPSEL1    1
-#define CFG_SPI_CHIPSEL2    2
-#define CFG_SPI_CHIPSEL3    3
-#define CFG_SPI_CHIPSEL4    4
-#define CFG_SPI_CHIPSEL5    5
-#define CFG_SPI_CHIPSEL6    6
-#define CFG_SPI_CHIPSEL7    7
-
-#define CFG_SPI_CS1VALUE    1
-#define CFG_SPI_CS2VALUE    2
-#define CFG_SPI_CS3VALUE    3
-#define CFG_SPI_CS4VALUE    4
-#define CFG_SPI_CS5VALUE    5
-#define CFG_SPI_CS6VALUE    6
-#define CFG_SPI_CS7VALUE    7
-
-#define CMD_SPI_SET_BAUDRATE  2
-#define CMD_SPI_GET_SYSTEMCLOCK   25
-#define CMD_SPI_SET_WRITECONTINUOUS     26
-
-/* device.platform_data for SSP controller devices */
-struct bfin5xx_spi_master {
-        u16 num_chipselect;
-        u8 enable_dma;
-        u16 pin_req[4];
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct bfin5xx_spi_chip {
-        u16 ctl_reg;
-        u8 enable_dma;
-        u8 bits_per_word;
-        u8 cs_change_per_word;
-        u16 cs_chg_udelay; /* Some devices require 16-bit delays */
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/include/asm-blackfin/bfin_simple_timer.h b/include/asm-blackfin/bfin_simple_timer.h
deleted file mode 100644
index fccbb595464a..000000000000
--- a/include/asm-blackfin/bfin_simple_timer.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _bfin_simple_timer_h_
-#define _bfin_simple_timer_h_
-
-#include <linux/ioctl.h>
-
-#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
-
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  2)
-#define BFIN_SIMPLE_TIMER_START      _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
-#define BFIN_SIMPLE_TIMER_STOP       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
-#define BFIN_SIMPLE_TIMER_READ       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
-
-#endif
diff --git a/include/asm-blackfin/bfin_sport.h b/include/asm-blackfin/bfin_sport.h
deleted file mode 100644
index c76ed8def302..000000000000
--- a/include/asm-blackfin/bfin_sport.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * File:         include/asm-blackfin/bfin_sport.h
- * Based on:
- * Author:       Roy Huang (roy.huang@analog.com)
- *
- * Created:      Thu Aug. 24 2006
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __BFIN_SPORT_H__
-#define __BFIN_SPORT_H__
-
-#define SPORT_MAJOR     237
-#define SPORT_NR_DEVS   2
-
-/* Sport mode: it can be set to TDM, i2s or others */
-#define NORM_MODE       0x0
-#define TDM_MODE        0x1
-#define I2S_MODE        0x2
-
-/* Data format, normal, a-law or u-law */
-#define NORM_FORMAT     0x0
-#define ALAW_FORMAT     0x2
-#define ULAW_FORMAT     0x3
-struct sport_register;
-
-/* Function driver which use sport must initialize the structure */
-struct sport_config {
-        /*TDM (multichannels), I2S or other mode */
-        unsigned int mode:3;
-
-        /* if TDM mode is selected, channels must be set */
-        int channels;           /* Must be in 8 units */
-        unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
-
-        /* I2S mode */
-        unsigned int right_first:1;     /* Right stereo channel first */
-
-        /* In mormal mode, the following item need to be set */
-        unsigned int lsb_first:1;       /* order of transmit or receive data */
-        unsigned int fsync:1;   /* Frame sync required */
-        unsigned int data_indep:1;      /* data independent frame sync generated */
-        unsigned int act_low:1; /* Active low TFS */
-        unsigned int late_fsync:1;      /* Late frame sync */
-        unsigned int tckfe:1;
-        unsigned int sec_en:1;  /* Secondary side enabled */
-
-        /* Choose clock source */
-        unsigned int int_clk:1; /* Internal or external clock */
-
-        /* If external clock is used, the following fields are ignored */
-        int serial_clk;
-        int fsync_clk;
-
-        unsigned int data_format:2;     /*Normal, u-law or a-law */
-
-        int word_len;           /* How length of the word in bits, 3-32 bits */
-        int dma_enabled;
-};
-
-struct sport_register {
-        unsigned short tcr1;
-        unsigned short reserved0;
-        unsigned short tcr2;
-        unsigned short reserved1;
-        unsigned short tclkdiv;
-        unsigned short reserved2;
-        unsigned short tfsdiv;
-        unsigned short reserved3;
-        unsigned long tx;
-        unsigned long reserved_l0;
-        unsigned long rx;
-        unsigned long reserved_l1;
-        unsigned short rcr1;
-        unsigned short reserved4;
-        unsigned short rcr2;
-        unsigned short reserved5;
-        unsigned short rclkdiv;
-        unsigned short reserved6;
-        unsigned short rfsdiv;
-        unsigned short reserved7;
-        unsigned short stat;
-        unsigned short reserved8;
-        unsigned short chnl;
-        unsigned short reserved9;
-        unsigned short mcmc1;
-        unsigned short reserved10;
-        unsigned short mcmc2;
-        unsigned short reserved11;
-        unsigned long mtcs0;
-        unsigned long mtcs1;
-        unsigned long mtcs2;
-        unsigned long mtcs3;
-        unsigned long mrcs0;
-        unsigned long mrcs1;
-        unsigned long mrcs2;
-        unsigned long mrcs3;
-};
-
-#define SPORT_IOC_MAGIC         'P'
-#define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
-
-/* Test purpose */
-#define ENABLE_AD73311          _IOWR('P', 0x02, int)
-
-struct sport_dev {
-        struct cdev cdev;       /* Char device structure */
-
-        int sport_num;
-
-        int dma_rx_chan;
-        int dma_tx_chan;
-
-        int rx_irq;
-        unsigned char *rx_buf;  /* Buffer store the received data */
-        int rx_len;             /* How many bytes will be received */
-        int rx_received;        /* How many bytes has been received */
-
-        int tx_irq;
-        const unsigned char *tx_buf;
-        int tx_len;
-        int tx_sent;
-
-        int sport_err_irq;
-
-        struct mutex mutex;     /* mutual exclusion semaphore */
-        struct task_struct *task;
-
-        wait_queue_head_t waitq;
-        int     wait_con;
-        struct sport_register *regs;
-        struct sport_config config;
-};
-
-#define SPORT_TCR1      0
-#define SPORT_TCR2      1
-#define SPORT_TCLKDIV   2
-#define SPORT_TFSDIV    3
-#define SPORT_RCR1      8
-#define SPORT_RCR2      9
-#define SPORT_RCLKDIV   10
-#define SPORT_RFSDIV    11
-#define SPORT_CHANNEL   13
-#define SPORT_MCMC1     14
-#define SPORT_MCMC2     15
-#define SPORT_MTCS0     16
-#define SPORT_MTCS1     17
-#define SPORT_MTCS2     18
-#define SPORT_MTCS3     19
-#define SPORT_MRCS0     20
-#define SPORT_MRCS1     21
-#define SPORT_MRCS2     22
-#define SPORT_MRCS3     23
-
-#endif                          /*__BFIN_SPORT_H__*/
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
deleted file mode 100644
index b39a175c79c1..000000000000
--- a/include/asm-blackfin/bitops.h
+++ /dev/null
@@ -1,218 +0,0 @@
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>      /* swab32 */
-#include <asm/system.h>         /* save_flags */
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffz.h>
-
-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        *a |= mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        *a |= mask;
-}
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
-
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-        unsigned long flags;
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        *a &= ~mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        *a &= ~mask;
-}
-
-static __inline__ void change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, flags;
-        unsigned long *ADDR = (unsigned long *)addr;
-
-        ADDR += nr >> 5;
-        mask = 1 << (nr & 31);
-        local_irq_save(flags);
-        *ADDR ^= mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask;
-        unsigned long *ADDR = (unsigned long *)addr;
-
-        ADDR += nr >> 5;
-        mask = 1 << (nr & 31);
-        *ADDR ^= mask;
-}
-
-static __inline__ int test_and_set_bit(int nr, void *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        retval = (mask & *a) != 0;
-        *a |= mask;
-        local_irq_restore(flags);
-
-        return retval;
-}
-
-static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        retval = (mask & *a) != 0;
-        *a |= mask;
-        return retval;
-}
-
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        retval = (mask & *a) != 0;
-        *a &= ~mask;
-        local_irq_restore(flags);
-
-        return retval;
-}
-
-static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        retval = (mask & *a) != 0;
-        *a &= ~mask;
-        return retval;
-}
-
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        retval = (mask & *a) != 0;
-        *a ^= mask;
-        local_irq_restore(flags);
-        return retval;
-}
-
-static __inline__ int __test_and_change_bit(int nr,
-                                            volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        retval = (mask & *a) != 0;
-        *a ^= mask;
-        return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const void *addr)
-{
-        return ((1UL << (nr & 31)) &
-                (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, const void *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        return ((mask & *a) != 0);
-}
-
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-#include <asm-generic/bitops/minix.h>
-
-#endif                          /* __KERNEL__ */
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif                          /* _BLACKFIN_BITOPS_H */
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
deleted file mode 100644
index 984b74f0a2ec..000000000000
--- a/include/asm-blackfin/blackfin.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-#include <asm/mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
-        int _tmp;
-        if (ANOMALY_05000312)
-                __asm__ __volatile__(
-                        "cli %0;"
-                        "nop;"
-                        "nop;"
-                        "ssync;"
-                        "sti %0;"
-                        : "=d" (_tmp)
-                );
-        else if (ANOMALY_05000244)
-                __asm__ __volatile__(
-                        "nop;"
-                        "nop;"
-                        "nop;"
-                        "ssync;"
-                );
-        else
-                __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
-        int _tmp;
-        if (ANOMALY_05000312)
-                __asm__ __volatile__(
-                        "cli %0;"
-                        "nop;"
-                        "nop;"
-                        "csync;"
-                        "sti %0;"
-                        : "=d" (_tmp)
-                );
-        else if (ANOMALY_05000244)
-                __asm__ __volatile__(
-                        "nop;"
-                        "nop;"
-                        "nop;"
-                        "csync;"
-                );
-        else
-                __asm__ __volatile__("csync;");
-}
-
-#else  /* __ASSEMBLY__ */
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-
-#elif ANOMALY_05000244
-#define SSYNC(scratch) nop; nop; nop; SSYNC;
-#define CSYNC(scratch) nop; nop; nop; CSYNC;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/mach/blackfin.h>
-#include <asm/bfin-global.h>
-
-#endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h
deleted file mode 100644
index 6d3e11b1fc57..000000000000
--- a/include/asm-blackfin/bug.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _BLACKFIN_BUG_H
-#define _BLACKFIN_BUG_H
-
-#ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
-
-#define BUG() do { \
-        dump_bfin_trace_buffer(); \
-        printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
-        panic("BUG!"); \
-} while (0)
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-blackfin/bugs.h b/include/asm-blackfin/bugs.h
deleted file mode 100644
index 9093c9c1fb81..000000000000
--- a/include/asm-blackfin/bugs.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  include/asm-blackfin/bugs.h
- *
- *  Copyright (C) 1994  Linus Torvalds
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *      void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
deleted file mode 100644
index 6a673d42da18..000000000000
--- a/include/asm-blackfin/byteorder.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef _BLACKFIN_BYTEORDER_H
-#define _BLACKFIN_BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u32 ___arch__swahb32(__u32 xx)
-{
-        __u32 tmp;
-        __asm__("%1 = %0 >> 8 (V);\n\t"
-                "%0 = %0 << 8 (V);\n\t"
-                "%0 = %0 | %1;\n\t"
-                : "+d"(xx), "=&d"(tmp));
-        return xx;
-}
-
-static __inline__ __attribute_const__ __u32 ___arch__swahw32(__u32 xx)
-{
-        __u32 rv;
-        __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
-        return rv;
-}
-
-#define __arch__swahb32(x) ___arch__swahb32(x)
-#define __arch__swahw32(x) ___arch__swahw32(x)
-#define __arch__swab32(x) ___arch__swahb32(___arch__swahw32(x))
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 xx)
-{
-        __u32 xw = xx;
-        __asm__("%0 <<= 8;\n    %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
-        return (__u16)xw;
-}
-
-#define __arch__swab16(x) ___arch__swab16(x)
-
-#endif
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/little_endian.h>
-
-#endif                          /* _BLACKFIN_BYTEORDER_H */
diff --git a/include/asm-blackfin/cache.h b/include/asm-blackfin/cache.h
deleted file mode 100644
index 023d72133b5a..000000000000
--- a/include/asm-blackfin/cache.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * include/asm-blackfin/cache.h
- */
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT  5
-#define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned                             \
-          __attribute__((__aligned__(L1_CACHE_BYTES),   \
-                __section__(".data_l1.cacheline_aligned")))
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX      5
-
-#endif
diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h
deleted file mode 100644
index d81a77545a04..000000000000
--- a/include/asm-blackfin/cacheflush.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * File:         include/asm-blackfin/cacheflush.h
- * Based on:     include/asm-m68knommu/cacheflush.h
- * Author:       LG Soft India
- *               Copyright (C) 2004 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  Blackfin low-level cache routines adapted from the i386
- *               and PPC versions by Greg Ungerer (gerg@snapgear.com)
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BLACKFIN_CACHEFLUSH_H
-#define _BLACKFIN_CACHEFLUSH_H
-
-#include <asm/cplb.h>
-
-extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
-extern void blackfin_icache_flush_range(unsigned int, unsigned int);
-extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
-extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
-extern void blackfin_dflush_page(void *);
-
-#define flush_dcache_mmap_lock(mapping)         do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
-#define flush_cache_mm(mm)                      do { } while (0)
-#define flush_cache_range(vma, start, end)      do { } while (0)
-#define flush_cache_page(vma, vmaddr)           do { } while (0)
-#define flush_cache_vmap(start, end)            do { } while (0)
-#define flush_cache_vunmap(start, end)          do { } while (0)
-
-static inline void flush_icache_range(unsigned start, unsigned end)
-{
-#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
-
-# if defined(CONFIG_BFIN_WT)
-        blackfin_icache_flush_range((start), (end));
-# else
-        blackfin_icache_dcache_flush_range((start), (end));
-# endif
-
-#else
-
-# if defined(CONFIG_BFIN_ICACHE)
-        blackfin_icache_flush_range((start), (end));
-# endif
-# if defined(CONFIG_BFIN_DCACHE)
-        blackfin_dcache_flush_range((start), (end));
-# endif
-
-#endif
-}
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
-     flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
-
-#if defined(CONFIG_BFIN_DCACHE)
-# define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
-#else
-# define invalidate_dcache_range(start,end)     do { } while (0)
-#endif
-#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
-# define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
-# define flush_dcache_page(page)                        blackfin_dflush_page(page_address(page))
-#else
-# define flush_dcache_range(start,end)          do { } while (0)
-# define flush_dcache_page(page)                        do { } while (0)
-#endif
-
-#endif                          /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/include/asm-blackfin/checksum.h b/include/asm-blackfin/checksum.h
deleted file mode 100644
index 6f6af2b8e9e0..000000000000
--- a/include/asm-blackfin/checksum.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef _BFIN_CHECKSUM_H
-#define _BFIN_CHECKSUM_H
-
-/*
- * MODIFIED FOR BFIN April 30, 2001 akbar.hussain@lineo.com
- *
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy(const void *src, void *dst,
-                               int len, __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-                                          int len, __wsum sum, int *csum_err);
-
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy((src), (dst), (len), (sum))
-
-__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
-
-/*
- *      Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-        while (sum >> 16)
-                sum = (sum & 0xffff) + (sum >> 16);
-        return ((~(sum << 16)) >> 16);
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
-                   unsigned short proto, __wsum sum)
-{
-
-        __asm__ ("%0 = %0 + %1;\n\t"
-                 "CC = AC0;\n\t"
-                 "if !CC jump 4;\n\t"
-                 "%0 = %0 + %4;\n\t"
-                 "%0 = %0 + %2;\n\t"
-                 "CC = AC0;\n\t"
-                 "if !CC jump 4;\n\t"
-                 "%0 = %0 + %4;\n\t"
-                 "%0 = %0 + %3;\n\t"
-                 "CC = AC0;\n\t"
-                 "if !CC jump 4;\n\t"
-                 "%0 = %0 + %4;\n\t"
-                 "NOP;\n\t"
-                 : "=d" (sum)
-                 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
-
-        return (sum);
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#endif                          /* _BFIN_CHECKSUM_H */
diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h
deleted file mode 100644
index 75c67b99d607..000000000000
--- a/include/asm-blackfin/cplb-mpu.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplbinit.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#ifndef __ASM_BFIN_CPLB_MPU_H
-#define __ASM_BFIN_CPLB_MPU_H
-
-struct cplb_entry {
-        unsigned long data, addr;
-};
-
-struct mem_region {
-        unsigned long start, end;
-        unsigned long dcplb_data;
-        unsigned long icplb_data;
-};
-
-extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_mask_dcplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
-extern int nr_cplb_flush;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask;
-
-extern void flush_switched_cplbs(void);
-extern void set_mask_dcplbs(unsigned long *);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
deleted file mode 100644
index 5b0da9a69b67..000000000000
--- a/include/asm-blackfin/cplb.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplb.h
- * Based on:     include/asm-blackfin/mach-bf537/bf537.h
- * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
- *
- * Created:      2000
- * Description:  Common CPLB definitions for CPLB init
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <asm/blackfin.h>
-#include <asm/mach/anomaly.h>
-
-#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
-
-#if ANOMALY_05000158
-#define ANOMALY_05000158_WORKAROUND             0x200
-#else
-#define ANOMALY_05000158_WORKAROUND             0x0
-#endif
-
-#define CPLB_COMMON     (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#ifdef CONFIG_BFIN_WB         /*Write Back Policy */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
-#else                           /*Write Through */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
-#endif
-
-#define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
-#define L2_MEMORY        (CPLB_COMMON)
-#define SDRAM_DNON_CHBL  (CPLB_COMMON)
-#define SDRAM_EBIU       (CPLB_COMMON)
-#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-
-#define SIZE_1K 0x00000400      /* 1K */
-#define SIZE_4K 0x00001000      /* 4K */
-#define SIZE_1M 0x00100000      /* 1M */
-#define SIZE_4M 0x00400000      /* 4M */
-
-#ifdef CONFIG_MPU
-#define MAX_CPLBS 16
-#else
-#define MAX_CPLBS (16 * 2)
-#endif
-
-#define ASYNC_MEMORY_CPLB_COVERAGE      ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
-                                 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
-
-#define CPLB_ENABLE_ICACHE_P    0
-#define CPLB_ENABLE_DCACHE_P    1
-#define CPLB_ENABLE_DCACHE2_P   2
-#define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P    4
-#define CPLB_ENABLE_DCPLBS_P    5
-
-#define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
-                                CPLB_ENABLE_ICPLBS | \
-                                CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED           0x0000
-#define CPLB_NO_UNLOCKED        0x0001
-#define CPLB_NO_ADDR_MATCH      0x0002
-#define CPLB_PROT_VIOL          0x0003
-#define CPLB_UNKNOWN_ERR        0x0004
-
-#define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
-
-#endif                          /* _CPLB_H */
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
deleted file mode 100644
index 0eb1c1b685a7..000000000000
--- a/include/asm-blackfin/cplbinit.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplbinit.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __ASM_CPLBINIT_H__
-#define __ASM_CPLBINIT_H__
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-
-#ifdef CONFIG_MPU
-
-#include <asm/cplb-mpu.h>
-
-#else
-
-#define INITIAL_T 0x1
-#define SWITCH_T  0x2
-#define I_CPLB    0x4
-#define D_CPLB    0x8
-
-#define IN_KERNEL 1
-
-enum
-{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
-
-struct cplb_desc {
-        u32 start; /* start address */
-        u32 end; /* end address */
-        u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
-        u16 attr;/* attributes */
-        u16 i_conf;/* I-CPLB DATA */
-        u16 d_conf;/* D-CPLB DATA */
-        u16 valid;/* valid */
-        const s8 name[30];/* name */
-};
-
-struct cplb_tab {
-  u_long *tab;
-        u16 pos;
-        u16 size;
-};
-
-extern u_long icplb_table[];
-extern u_long dcplb_table[];
-
-/* Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
-
-extern u_long ipdt_table[];
-extern u_long dpdt_table[];
-#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[];
-extern u_long dpdt_swapcount_table[];
-#endif
-
-#endif /* CONFIG_MPU */
-
-extern unsigned long reserved_mem_dcache_on;
-extern unsigned long reserved_mem_icache_on;
-
-extern void generate_cpl_tables(void);
-
-#endif
diff --git a/include/asm-blackfin/cpumask.h b/include/asm-blackfin/cpumask.h
deleted file mode 100644
index b20a8e9012cb..000000000000
--- a/include/asm-blackfin/cpumask.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_BLACKFIN_CPUMASK_H
-#define _ASM_BLACKFIN_CPUMASK_H
-
-#include <asm-generic/cpumask.h>
-
-#endif                          /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/include/asm-blackfin/cputime.h b/include/asm-blackfin/cputime.h
deleted file mode 100644
index 2b19705f9885..000000000000
--- a/include/asm-blackfin/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BLACKFIN_CPUTIME_H
-#define __BLACKFIN_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif                          /* __BLACKFIN_CPUTIME_H */
diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
deleted file mode 100644
index 31918d29122c..000000000000
--- a/include/asm-blackfin/current.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _BLACKFIN_CURRENT_H
-#define _BLACKFIN_CURRENT_H
-/*
- *      current.h
- *      (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
- *
- *      rather than dedicate a register (as the m68k source does), we
- *      just keep a global,  we should probably just change it all to be
- *      current and lose _current_task.
- */
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct *get_current(void) __attribute__ ((__const__));
-static inline struct task_struct *get_current(void)
-{
-        return (current_thread_info()->task);
-}
-
-#define current (get_current())
-
-#endif                          /* _BLACKFIN_CURRENT_H */
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
deleted file mode 100644
index 473a8113277f..000000000000
--- a/include/asm-blackfin/delay.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * delay.h - delay functions
- *
- * Copyright (c) 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_DELAY_H__
-#define __ASM_DELAY_H__
-
-#include <asm/mach/anomaly.h>
-
-static inline void __delay(unsigned long loops)
-{
-        if (ANOMALY_05000312) {
-                /* Interrupted loads to loop registers -> bad */
-                unsigned long tmp;
-                __asm__ __volatile__(
-                        "[--SP] = LC0;"
-                        "[--SP] = LT0;"
-                        "[--SP] = LB0;"
-                        "LSETUP (1f,1f) LC0 = %1;"
-                        "1: NOP;"
-                        /* We take advantage of the fact that LC0 is 0 at
-                         * the end of the loop.  Otherwise we'd need some
-                         * NOPs after the CLI here.
-                         */
-                        "CLI %0;"
-                        "LB0 = [SP++];"
-                        "LT0 = [SP++];"
-                        "LC0 = [SP++];"
-                        "STI %0;"
-                        : "=d" (tmp)
-                        : "a" (loops)
-                );
-        } else
-                __asm__ __volatile__ (
-                        "LSETUP(1f, 1f) LC0 = %0;"
-                        "1: NOP;"
-                        :
-                        : "a" (loops)
-                        : "LT0", "LB0", "LC0"
-                );
-}
-
-#include <linux/param.h>        /* needed for HZ */
-
-/*
- * Use only for very small delays ( < 1 msec).  Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays.  This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-static inline void udelay(unsigned long usecs)
-{
-        extern unsigned long loops_per_jiffy;
-        __delay(usecs * loops_per_jiffy / (1000000 / HZ));
-}
-
-#endif
diff --git a/include/asm-blackfin/device.h b/include/asm-blackfin/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-blackfin/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-blackfin/div64.h b/include/asm-blackfin/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-blackfin/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
deleted file mode 100644
index 1a13c2fc3667..000000000000
--- a/include/asm-blackfin/dma-mapping.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _BLACKFIN_DMA_MAPPING_H
-#define _BLACKFIN_DMA_MAPPING_H
-
-#include <asm/scatterlist.h>
-
-void dma_alloc_init(unsigned long start, unsigned long end);
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, gfp_t gfp);
-void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
-                       dma_addr_t dma_handle);
-
-/*
- * Now for the API extensions over the pci_ one
- */
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-#define dma_mapping_error
-
-/*
- * Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single is performed.
- */
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-                                 enum dma_data_direction direction);
-
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page,
-             unsigned long offset, size_t size,
-             enum dma_data_direction dir)
-{
-        return dma_map_single(dev, page_address(page) + offset, size, dir);
-}
-
-/*
- * Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                          enum dma_data_direction direction);
-
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
-               enum dma_data_direction dir)
-{
-        dma_unmap_single(dev, dma_addr, size, dir);
-}
-
-/*
- * Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction direction);
-
-/*
- * Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                      int nhwentries, enum dma_data_direction direction);
-
-#endif                          /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
deleted file mode 100644
index 3cd4b522aa3f..000000000000
--- a/include/asm-blackfin/dma.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * File:         include/asm-blackfin/simple_bf533_dma.h
- * Based on:     none - original work
- * Author:       LG Soft India
- *               Copyright (C) 2004-2005 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  This file contains the major Data structures and constants
- *               used for DMA Implementation in BF533
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <asm/io.h>
-#include <linux/slab.h>
-#include <asm/irq.h>
-#include <asm/signal.h>
-
-#include <linux/kernel.h>
-#include <asm/mach/dma.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <asm/blackfin.h>
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/*****************************************************************************
-*        Generic DMA  Declarations
-*
-****************************************************************************/
-enum dma_chan_status {
-        DMA_CHANNEL_FREE,
-        DMA_CHANNEL_REQUESTED,
-        DMA_CHANNEL_ENABLED,
-};
-
-/*-------------------------
- * config reg bits value
- *-------------------------*/
-#define DATA_SIZE_8             0
-#define DATA_SIZE_16            1
-#define DATA_SIZE_32            2
-
-#define DMA_FLOW_STOP           0
-#define DMA_FLOW_AUTO           1
-#define DMA_FLOW_ARRAY          4
-#define DMA_FLOW_SMALL          6
-#define DMA_FLOW_LARGE          7
-
-#define DIMENSION_LINEAR    0
-#define DIMENSION_2D           1
-
-#define DIR_READ     0
-#define DIR_WRITE    1
-
-#define INTR_DISABLE   0
-#define INTR_ON_BUF    2
-#define INTR_ON_ROW    3
-
-#define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART        1
-
-struct dmasg {
-        unsigned long next_desc_addr;
-        unsigned long start_addr;
-        unsigned short cfg;
-        unsigned short x_count;
-        short x_modify;
-        unsigned short y_count;
-        short y_modify;
-} __attribute__((packed));
-
-struct dma_register {
-        unsigned long next_desc_ptr;    /* DMA Next Descriptor Pointer register */
-        unsigned long start_addr;       /* DMA Start address  register */
-
-        unsigned short cfg;     /* DMA Configuration register */
-        unsigned short dummy1;  /* DMA Configuration register */
-
-        unsigned long reserved;
-
-        unsigned short x_count; /* DMA x_count register */
-        unsigned short dummy2;
-
-        short x_modify; /* DMA x_modify register */
-        unsigned short dummy3;
-
-        unsigned short y_count; /* DMA y_count register */
-        unsigned short dummy4;
-
-        short y_modify; /* DMA y_modify register */
-        unsigned short dummy5;
-
-        unsigned long curr_desc_ptr;    /* DMA Current Descriptor Pointer
-                                           register */
-        unsigned long curr_addr_ptr;    /* DMA Current Address Pointer
-                                                   register */
-        unsigned short irq_status;      /* DMA irq status register */
-        unsigned short dummy6;
-
-        unsigned short peripheral_map;  /* DMA peripheral map register */
-        unsigned short dummy7;
-
-        unsigned short curr_x_count;    /* DMA Current x-count register */
-        unsigned short dummy8;
-
-        unsigned long reserved2;
-
-        unsigned short curr_y_count;    /* DMA Current y-count register */
-        unsigned short dummy9;
-
-        unsigned long reserved3;
-
-};
-
-typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
-
-struct dma_channel {
-        struct mutex dmalock;
-        char *device_id;
-        enum dma_chan_status chan_status;
-        struct dma_register *regs;
-        struct dmasg *sg;               /* large mode descriptor */
-        unsigned int ctrl_num;  /* controller number */
-        dma_interrupt_t irq_callback;
-        void *data;
-        unsigned int dma_enable_flag;
-        unsigned int loopback_flag;
-#ifdef CONFIG_PM
-        unsigned short saved_peripheral_map;
-#endif
-};
-
-#ifdef CONFIG_PM
-int blackfin_dma_suspend(void);
-void blackfin_dma_resume(void);
-#endif
-
-/*******************************************************************************
-*       DMA API's
-*******************************************************************************/
-/* functions to set register mode */
-void set_dma_start_addr(unsigned int channel, unsigned long addr);
-void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
-void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr);
-void set_dma_x_count(unsigned int channel, unsigned short x_count);
-void set_dma_x_modify(unsigned int channel, short x_modify);
-void set_dma_y_count(unsigned int channel, unsigned short y_count);
-void set_dma_y_modify(unsigned int channel, short y_modify);
-void set_dma_config(unsigned int channel, unsigned short config);
-unsigned short set_bfin_dma_config(char direction, char flow_mode,
-                                   char intr_mode, char dma_mode, char width,
-                                   char syncmode);
-void set_dma_curr_addr(unsigned int channel, unsigned long addr);
-
-/* get curr status for polling */
-unsigned short get_dma_curr_irqstat(unsigned int channel);
-unsigned short get_dma_curr_xcount(unsigned int channel);
-unsigned short get_dma_curr_ycount(unsigned int channel);
-unsigned long get_dma_next_desc_ptr(unsigned int channel);
-unsigned long get_dma_curr_desc_ptr(unsigned int channel);
-unsigned long get_dma_curr_addr(unsigned int channel);
-
-/* set large DMA mode descriptor */
-void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
-
-/* check if current channel is in use */
-int dma_channel_active(unsigned int channel);
-
-/* common functions must be called in any mode */
-void free_dma(unsigned int channel);
-int dma_channel_active(unsigned int channel); /* check if a channel is in use */
-void disable_dma(unsigned int channel);
-void enable_dma(unsigned int channel);
-int request_dma(unsigned int channel, char *device_id);
-int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
-                     void *data);
-void dma_disable_irq(unsigned int channel);
-void dma_enable_irq(unsigned int channel);
-void clear_dma_irqstat(unsigned int channel);
-void *dma_memcpy(void *dest, const void *src, size_t count);
-void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
-
-#endif
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
deleted file mode 100644
index de28e6e018b3..000000000000
--- a/include/asm-blackfin/dpmc.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * include/asm-blackfin/dpmc.h -  Miscellaneous IOCTL commands for Dynamic Power
- *                              Management Controller Driver.
- * Copyright (C) 2004-2008 Analog Device Inc.
- *
- */
-#ifndef _BLACKFIN_DPMC_H_
-#define _BLACKFIN_DPMC_H_
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void deep_sleep(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void do_hibernate(int wakeup);
-void set_dram_srfs(void);
-void unset_dram_srfs(void);
-
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
-
-struct bfin_dpmc_platform_data {
-        const unsigned int *tuple_tab;
-        unsigned short tabsize;
-        unsigned short vr_settling_time; /* in us */
-};
-
-#else
-
-#define PM_PUSH(x) \
-        R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
-        [--SP] =  R0;\
-
-#define PM_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
-
-#define PM_SYS_PUSH(x) \
-        R0 = [P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-
-#define PM_SYS_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - PLL_CTL)] = R0;\
-
-#define PM_SYS_PUSH16(x) \
-        R0 = w[P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-
-#define PM_SYS_POP16(x) \
-        R0 = [SP++];\
-        w[P0 + (x - PLL_CTL)] = R0;\
-
-#endif
-#endif  /* __KERNEL__ */
-
-#endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/early_printk.h b/include/asm-blackfin/early_printk.h
deleted file mode 100644
index 110f1c1f845c..000000000000
--- a/include/asm-blackfin/early_printk.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * File:         include/asm-blackfin/early_printk.h
- * Author:       Robin Getz <rgetz@blackfin.uclinux.org
- *
- * Created:      14Aug2007
- * Description:  function prototpyes for early printk
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifdef CONFIG_EARLY_PRINTK
-extern int setup_early_printk(char *);
-#else
-#define setup_early_printk(fmt) do { } while (0)
-#endif /* CONFIG_EARLY_PRINTK */
diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h
deleted file mode 100644
index 67a03a8a353e..000000000000
--- a/include/asm-blackfin/elf.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Changes made by  LG Soft Oct 2004*/
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field.  */
-#define EF_BFIN_PIC             0x00000001      /* -fpic */
-#define EF_BFIN_FDPIC           0x00000002      /* -mfdpic */
-#define EF_BFIN_CODE_IN_L1      0x00000010      /* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1      0x00000020      /* --data-in-l1 */
-#define EF_BFIN_CODE_IN_L2      0x00000040      /* --code-in-l2 */
-#define EF_BFIN_DATA_IN_L2      0x00000080      /* --data-in-l2 */
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_bfinfp_struct elf_fpregset_t;
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h   */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r)       _r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr)     \
-do {                                                                                    \
-        _regs->r7       = 0;                                            \
-        _regs->p0       = _exec_map_addr;                               \
-        _regs->p1       = _interp_map_addr;                             \
-        _regs->p2       = _dynamic_addr;                                \
-} while(0)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_FDPIC_CORE_EFLAGS   EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE       4096
-
-#define R_unused0       0       /* relocation type 0 is not defined */
-#define R_pcrel5m2      1       /*LSETUP part a */
-#define R_unused1       2       /* relocation type 2 is not defined */
-#define R_pcrel10       3       /* type 3, if cc jump <target>  */
-#define R_pcrel12_jump  4       /* type 4, jump <target> */
-#define R_rimm16        5       /* type 0x5, rN = <target> */
-#define R_luimm16       6       /* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_huimm16       7       /* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_pcrel12_jump_s 8      /* # 0x8 jump.s <target> */
-#define R_pcrel24_jump_x 9      /* # 0x9 jump.x <target> */
-#define R_pcrel24       10      /* # 0xa call <target> , not expandable */
-#define R_unusedb       11      /* # 0xb not generated */
-#define R_unusedc       12      /* # 0xc  not used */
-#define R_pcrel24_jump_l 13     /*0xd jump.l <target> */
-#define R_pcrel24_call_x 14     /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_var_eq_symb    15     /* 0xf, linker should treat it same as 0x12 */
-#define R_byte_data      16     /* 0x10, .byte var = symbol */
-#define R_byte2_data     17     /* 0x11, .byte2 var = symbol */
-#define R_byte4_data     18     /* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_pcrel11        19     /* 0x13, lsetup part b */
-#define R_unused14      20      /* 0x14, undefined */
-#define R_unused15       21     /* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_push           0xE0
-#define R_const          0xE1
-#define R_add            0xE2
-#define R_sub            0xE3
-#define R_mult           0xE4
-#define R_div            0xE5
-#define R_mod            0xE6
-#define R_lshift         0xE7
-#define R_rshift         0xE8
-#define R_and            0xE9
-#define R_or             0xEA
-#define R_xor            0xEB
-#define R_land           0xEC
-#define R_lor            0xED
-#define R_len            0xEE
-#define R_neg            0xEF
-#define R_comp           0xF0
-#define R_page           0xF1
-#define R_hwpage         0xF2
-#define R_addr           0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)        \
-        memcpy((char *) &pr_reg, (char *)regs,  \
-               sizeof(struct pt_regs));
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  */
-
-#define ELF_HWCAP       (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM  (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-
-#endif
diff --git a/include/asm-blackfin/emergency-restart.h b/include/asm-blackfin/emergency-restart.h
deleted file mode 100644
index 27f6c785d103..000000000000
--- a/include/asm-blackfin/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif                          /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
deleted file mode 100644
index c4f721e0d00d..000000000000
--- a/include/asm-blackfin/entry.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __BFIN_ENTRY_H
-#define __BFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-
-#define LFLUSH_I_AND_D  0x00000808
-#define LSIGTRAP        5
-
-/* process bits for task_struct.flags */
-#define PF_TRACESYS_OFF 3
-#define PF_TRACESYS_BIT 5
-#define PF_PTRACED_OFF  3
-#define PF_PTRACED_BIT  4
-#define PF_DTRACE_OFF   1
-#define PF_DTRACE_BIT   5
-
-/*
- * NOTE!  The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/* This one is used for exceptions, emulation, and NMI.  It doesn't push
-   RETI and doesn't do cli.  */
-#define SAVE_ALL_SYS            save_context_no_interrupts
-/* This is used for all normal interrupts.  It saves a minimum of registers
-   to the stack, loads the IRQ number, and jumps to common code.  */
-#define INTERRUPT_ENTRY(N)                                              \
-    [--sp] = SYSCFG;                                                    \
-                                                                        \
-    [--sp] = P0;        /*orig_p0*/                                     \
-    [--sp] = R0;        /*orig_r0*/                                     \
-    [--sp] = (R7:0,P5:0);                                               \
-    R0 = (N);                                                           \
-    jump __common_int_entry;
-
-/* For timer interrupts, we need to save IPEND, since the user_mode
-           macro accesses it to determine where to account time.  */
-#define TIMER_INTERRUPT_ENTRY(N)                                        \
-    [--sp] = SYSCFG;                                                    \
-                                                                        \
-    [--sp] = P0;        /*orig_p0*/                                     \
-    [--sp] = R0;        /*orig_r0*/                                     \
-    [--sp] = (R7:0,P5:0);                                               \
-    p0.l = lo(IPEND);                                                   \
-    p0.h = hi(IPEND);                                                   \
-    r1 = [p0];                                                          \
-    R0 = (N);                                                           \
-    jump __common_int_entry;
-
-/* This one pushes RETI without using CLI.  Interrupts are enabled.  */
-#define SAVE_CONTEXT_SYSCALL    save_context_syscall
-#define SAVE_CONTEXT            save_context_with_interrupts
-
-#define RESTORE_ALL_SYS         restore_context_no_interrupts
-#define RESTORE_CONTEXT         restore_context_with_interrupts
-
-#endif                          /* __ASSEMBLY__ */
-#endif                          /* __BFIN_ENTRY_H */
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
deleted file mode 100644
index 164e4f39bb57..000000000000
--- a/include/asm-blackfin/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_ERRNO_H
-#define _BFIN_ERRNO_H
-
-#include<asm-generic/errno.h>
-
-#endif                          /* _BFIN_ERRNO_H */
diff --git a/include/asm-blackfin/fb.h b/include/asm-blackfin/fb.h
deleted file mode 100644
index c7df38030992..000000000000
--- a/include/asm-blackfin/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-        return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-blackfin/fcntl.h b/include/asm-blackfin/fcntl.h
deleted file mode 100644
index 9c4037127857..000000000000
--- a/include/asm-blackfin/fcntl.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _BFIN_FCNTL_H
-#define _BFIN_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_DIRECTORY      040000 /* must be a directory */
-#define O_NOFOLLOW      0100000 /* don't follow links */
-#define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE     0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif
diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h
deleted file mode 100644
index 37db66c7030d..000000000000
--- a/include/asm-blackfin/fixed_code.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/* This file defines the fixed addresses where userspace programs can find
-   atomic code sequences.  */
-
-#define FIXED_CODE_START        0x400
-
-#define SIGRETURN_STUB          0x400
-
-#define ATOMIC_SEQS_START       0x410
-
-#define ATOMIC_XCHG32           0x410
-#define ATOMIC_CAS32            0x420
-#define ATOMIC_ADD32            0x430
-#define ATOMIC_SUB32            0x440
-#define ATOMIC_IOR32            0x450
-#define ATOMIC_AND32            0x460
-#define ATOMIC_XOR32            0x470
-
-#define ATOMIC_SEQS_END         0x480
-
-#define SAFE_USER_INSTRUCTION   0x480
-
-#define FIXED_CODE_END          0x490
diff --git a/include/asm-blackfin/flat.h b/include/asm-blackfin/flat.h
deleted file mode 100644
index e70074e05f4e..000000000000
--- a/include/asm-blackfin/flat.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * include/asm-blackfin/flat.h -- uClinux flat-format executables
- *
- * Copyright (C) 2003,
- *
- */
-
-#ifndef __BLACKFIN_FLAT_H__
-#define __BLACKFIN_FLAT_H__
-
-#include <asm/unaligned.h>
-
-#define flat_stack_align(sp)    /* nothing needed */
-#define flat_argvp_envp_on_stack()              0
-#define flat_old_ram_flag(flags)                (flags)
-
-extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr,
-                                        unsigned long relval,
-                                        unsigned long flags,
-                                        unsigned long *persistent);
-
-extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
-                                unsigned long relval);
-
-/* The amount by which a relocation can exceed the program image limits
-   without being regarded as an error.  */
-
-#define flat_reloc_valid(reloc, size)   ((reloc) <= (size))
-
-#define flat_get_addr_from_rp(rp, relval, flags, persistent)    \
-        bfin_get_addr_from_rp(rp, relval, flags, persistent)
-#define flat_put_addr_at_rp(rp, val, relval)    \
-        bfin_put_addr_at_rp(rp, val, relval)
-
-/* Convert a relocation entry into an address.  */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
-        return relval & 0x03ffffff; /* Mask out top 6 bits */
-}
-
-static inline int flat_set_persistent(unsigned long relval,
-                                      unsigned long *persistent)
-{
-        int type = (relval >> 26) & 7;
-        if (type == 3) {
-                *persistent = relval << 16;
-                return 1;
-        }
-        return 0;
-}
-
-static inline int flat_addr_absolute(unsigned long relval)
-{
-        return (relval & (1 << 29)) != 0;
-}
-
-#endif                          /* __BLACKFIN_FLAT_H__ */
diff --git a/include/asm-blackfin/futex.h b/include/asm-blackfin/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/include/asm-blackfin/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
deleted file mode 100644
index 168f1251eb4d..000000000000
--- a/include/asm-blackfin/gpio.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * File:         arch/blackfin/kernel/bfin_gpio.h
- * Based on:
- * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2008 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-/*
-*  Number     BF537/6/4    BF561    BF533/2/1
-*             BF527/5/2
-*
-*  GPIO_0       PF0         PF0        PF0
-*  GPIO_1       PF1         PF1        PF1
-*  GPIO_2       PF2         PF2        PF2
-*  GPIO_3       PF3         PF3        PF3
-*  GPIO_4       PF4         PF4        PF4
-*  GPIO_5       PF5         PF5        PF5
-*  GPIO_6       PF6         PF6        PF6
-*  GPIO_7       PF7         PF7        PF7
-*  GPIO_8       PF8         PF8        PF8
-*  GPIO_9       PF9         PF9        PF9
-*  GPIO_10      PF10        PF10       PF10
-*  GPIO_11      PF11        PF11       PF11
-*  GPIO_12      PF12        PF12       PF12
-*  GPIO_13      PF13        PF13       PF13
-*  GPIO_14      PF14        PF14       PF14
-*  GPIO_15      PF15        PF15       PF15
-*  GPIO_16      PG0         PF16
-*  GPIO_17      PG1         PF17
-*  GPIO_18      PG2         PF18
-*  GPIO_19      PG3         PF19
-*  GPIO_20      PG4         PF20
-*  GPIO_21      PG5         PF21
-*  GPIO_22      PG6         PF22
-*  GPIO_23      PG7         PF23
-*  GPIO_24      PG8         PF24
-*  GPIO_25      PG9         PF25
-*  GPIO_26      PG10        PF26
-*  GPIO_27      PG11        PF27
-*  GPIO_28      PG12        PF28
-*  GPIO_29      PG13        PF29
-*  GPIO_30      PG14        PF30
-*  GPIO_31      PG15        PF31
-*  GPIO_32      PH0         PF32
-*  GPIO_33      PH1         PF33
-*  GPIO_34      PH2         PF34
-*  GPIO_35      PH3         PF35
-*  GPIO_36      PH4         PF36
-*  GPIO_37      PH5         PF37
-*  GPIO_38      PH6         PF38
-*  GPIO_39      PH7         PF39
-*  GPIO_40      PH8         PF40
-*  GPIO_41      PH9         PF41
-*  GPIO_42      PH10        PF42
-*  GPIO_43      PH11        PF43
-*  GPIO_44      PH12        PF44
-*  GPIO_45      PH13        PF45
-*  GPIO_46      PH14        PF46
-*  GPIO_47      PH15        PF47
-*/
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x)  (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-
-#define GPIO_0  0
-#define GPIO_1  1
-#define GPIO_2  2
-#define GPIO_3  3
-#define GPIO_4  4
-#define GPIO_5  5
-#define GPIO_6  6
-#define GPIO_7  7
-#define GPIO_8  8
-#define GPIO_9  9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
-
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-
-#ifdef BF533_FAMILY
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-
-#endif
-
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PG0        16
-#define GPIO_PG1        17
-#define GPIO_PG2        18
-#define GPIO_PG3        19
-#define GPIO_PG4        20
-#define GPIO_PG5        21
-#define GPIO_PG6        22
-#define GPIO_PG7        23
-#define GPIO_PG8        24
-#define GPIO_PG9        25
-#define GPIO_PG10       26
-#define GPIO_PG11       27
-#define GPIO_PG12       28
-#define GPIO_PG13       29
-#define GPIO_PG14       30
-#define GPIO_PG15       31
-#define GPIO_PH0        32
-#define GPIO_PH1        33
-#define GPIO_PH2        34
-#define GPIO_PH3        35
-#define GPIO_PH4        36
-#define GPIO_PH5        37
-#define GPIO_PH6        38
-#define GPIO_PH7        39
-#define GPIO_PH8        40
-#define GPIO_PH9        41
-#define GPIO_PH10       42
-#define GPIO_PH11       43
-#define GPIO_PH12       44
-#define GPIO_PH13       45
-#define GPIO_PH14       46
-#define GPIO_PH15       47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif
-
-#ifdef BF548_FAMILY
-#include <asm-blackfin/mach-bf548/gpio.h>
-#endif
-
-#ifdef BF561_FAMILY
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PF16       16
-#define GPIO_PF17       17
-#define GPIO_PF18       18
-#define GPIO_PF19       19
-#define GPIO_PF20       20
-#define GPIO_PF21       21
-#define GPIO_PF22       22
-#define GPIO_PF23       23
-#define GPIO_PF24       24
-#define GPIO_PF25       25
-#define GPIO_PF26       26
-#define GPIO_PF27       27
-#define GPIO_PF28       28
-#define GPIO_PF29       29
-#define GPIO_PF30       30
-#define GPIO_PF31       31
-#define GPIO_PF32       32
-#define GPIO_PF33       33
-#define GPIO_PF34       34
-#define GPIO_PF35       35
-#define GPIO_PF36       36
-#define GPIO_PF37       37
-#define GPIO_PF38       38
-#define GPIO_PF39       39
-#define GPIO_PF40       40
-#define GPIO_PF41       41
-#define GPIO_PF42       42
-#define GPIO_PF43       43
-#define GPIO_PF44       44
-#define GPIO_PF45       45
-#define GPIO_PF46       46
-#define GPIO_PF47       47
-
-#define PORT_FIO0 GPIO_0
-#define PORT_FIO1 GPIO_16
-#define PORT_FIO2 GPIO_32
-#endif
-
-#ifndef __ASSEMBLY__
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-*              to Blackfin processor General Purpose
-*              Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-#ifndef BF548_FAMILY
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
-        unsigned short data;
-        unsigned short dummy1;
-        unsigned short data_clear;
-        unsigned short dummy2;
-        unsigned short data_set;
-        unsigned short dummy3;
-        unsigned short toggle;
-        unsigned short dummy4;
-        unsigned short maska;
-        unsigned short dummy5;
-        unsigned short maska_clear;
-        unsigned short dummy6;
-        unsigned short maska_set;
-        unsigned short dummy7;
-        unsigned short maska_toggle;
-        unsigned short dummy8;
-        unsigned short maskb;
-        unsigned short dummy9;
-        unsigned short maskb_clear;
-        unsigned short dummy10;
-        unsigned short maskb_set;
-        unsigned short dummy11;
-        unsigned short maskb_toggle;
-        unsigned short dummy12;
-        unsigned short dir;
-        unsigned short dummy13;
-        unsigned short polar;
-        unsigned short dummy14;
-        unsigned short edge;
-        unsigned short dummy15;
-        unsigned short both;
-        unsigned short dummy16;
-        unsigned short inen;
-};
-#endif
-
-#ifdef CONFIG_PM
-
-unsigned int bfin_pm_standby_setup(void);
-void bfin_pm_standby_restore(void);
-
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-
-#ifndef CONFIG_BF54x
-#define PM_WAKE_RISING  0x1
-#define PM_WAKE_FALLING 0x2
-#define PM_WAKE_HIGH    0x4
-#define PM_WAKE_LOW     0x8
-#define PM_WAKE_BOTH_EDGES      (PM_WAKE_RISING | PM_WAKE_FALLING)
-#define PM_WAKE_IGNORE  0xF0
-
-int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
-void gpio_pm_wakeup_free(unsigned gpio);
-
-struct gpio_port_s {
-        unsigned short data;
-        unsigned short maska;
-        unsigned short maskb;
-        unsigned short dir;
-        unsigned short polar;
-        unsigned short edge;
-        unsigned short both;
-        unsigned short inen;
-
-        unsigned short fer;
-        unsigned short reserved;
-        unsigned short mux;
-};
-#endif /*CONFIG_BF54x*/
-#endif /*CONFIG_PM*/
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int gpio_request(unsigned, const char *);
-void gpio_free(unsigned);
-
-void gpio_set_value(unsigned gpio, int arg);
-int gpio_get_value(unsigned gpio);
-
-#ifndef BF548_FAMILY
-#define gpio_set_value(gpio, value)     set_gpio_data(gpio, value)
-#endif
-
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-#include <asm/irq.h>
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return (gpio + GPIO_IRQ_BASE);
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return (irq - GPIO_IRQ_BASE);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
deleted file mode 100644
index 0520d2aac8f3..000000000000
--- a/include/asm-blackfin/gptimers.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _BLACKFIN_TIMERS_H_
-#define _BLACKFIN_TIMERS_H_
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * BF537/BF527: 8 timers:
- */
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG      TIMER_ENABLE
-#endif
-/*
- * BF54x: 11 timers (BF542: 8 timers):
- */
-#if defined(BF548_FAMILY)
-# ifdef CONFIG_BF542
-#  define MAX_BLACKFIN_GPTIMERS 8
-# else
-#  define MAX_BLACKFIN_GPTIMERS 11
-#  define TIMER8_GROUP_REG      TIMER_ENABLE1
-# endif
-# define TIMER0_GROUP_REG       TIMER_ENABLE0
-#endif
-/*
- * BF561: 12 timers:
- */
-#if defined(CONFIG_BF561)
-# define MAX_BLACKFIN_GPTIMERS 12
-# define TIMER0_GROUP_REG      TMRS8_ENABLE
-# define TIMER8_GROUP_REG      TMRS4_ENABLE
-#endif
-/*
- * All others: 3 timers:
- */
-#if !defined(MAX_BLACKFIN_GPTIMERS)
-# define MAX_BLACKFIN_GPTIMERS 3
-# define TIMER0_GROUP_REG      TIMER_ENABLE
-#endif
-
-#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
-#define BFIN_TIMER_OCTET(x) ((x) >> 3)
-
-/* used in masks for timer_enable() and timer_disable() */
-#define TIMER0bit  0x0001  /*  0001b */
-#define TIMER1bit  0x0002  /*  0010b */
-#define TIMER2bit  0x0004  /*  0100b */
-#define TIMER3bit  0x0008
-#define TIMER4bit  0x0010
-#define TIMER5bit  0x0020
-#define TIMER6bit  0x0040
-#define TIMER7bit  0x0080
-#define TIMER8bit  0x0100
-#define TIMER9bit  0x0200
-#define TIMER10bit 0x0400
-#define TIMER11bit 0x0800
-
-#define TIMER0_id   0
-#define TIMER1_id   1
-#define TIMER2_id   2
-#define TIMER3_id   3
-#define TIMER4_id   4
-#define TIMER5_id   5
-#define TIMER6_id   6
-#define TIMER7_id   7
-#define TIMER8_id   8
-#define TIMER9_id   9
-#define TIMER10_id 10
-#define TIMER11_id 11
-
-/* associated timers for ppi framesync: */
-
-#if defined(CONFIG_BF561)
-# define FS0_1_TIMER_ID   TIMER8_id
-# define FS0_2_TIMER_ID   TIMER9_id
-# define FS1_1_TIMER_ID   TIMER10_id
-# define FS1_2_TIMER_ID   TIMER11_id
-# define FS0_1_TIMER_BIT  TIMER8bit
-# define FS0_2_TIMER_BIT  TIMER9bit
-# define FS1_1_TIMER_BIT  TIMER10bit
-# define FS1_2_TIMER_BIT  TIMER11bit
-# undef FS1_TIMER_ID
-# undef FS2_TIMER_ID
-# undef FS1_TIMER_BIT
-# undef FS2_TIMER_BIT
-#else
-# define FS1_TIMER_ID  TIMER0_id
-# define FS2_TIMER_ID  TIMER1_id
-# define FS1_TIMER_BIT TIMER0bit
-# define FS2_TIMER_BIT TIMER1bit
-#endif
-
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_ERR           0xC000
-#define TIMER_ERR_OVFL      0x4000
-#define TIMER_ERR_PROG_PER  0x8000
-#define TIMER_ERR_PROG_PW   0xC000
-#define TIMER_EMU_RUN       0x0200
-#define TIMER_TOGGLE_HI     0x0100
-#define TIMER_CLK_SEL       0x0080
-#define TIMER_OUT_DIS       0x0040
-#define TIMER_TIN_SEL       0x0020
-#define TIMER_IRQ_ENA       0x0010
-#define TIMER_PERIOD_CNT    0x0008
-#define TIMER_PULSE_HI      0x0004
-#define TIMER_MODE          0x0003
-#define TIMER_MODE_PWM      0x0001
-#define TIMER_MODE_WDTH     0x0002
-#define TIMER_MODE_EXT_CLK  0x0003
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0  0x0001
-#define TIMER_STATUS_TIMIL1  0x0002
-#define TIMER_STATUS_TIMIL2  0x0004
-#define TIMER_STATUS_TIMIL3  0x00000008
-#define TIMER_STATUS_TIMIL4  0x00010000
-#define TIMER_STATUS_TIMIL5  0x00020000
-#define TIMER_STATUS_TIMIL6  0x00040000
-#define TIMER_STATUS_TIMIL7  0x00080000
-#define TIMER_STATUS_TIMIL8  0x0001
-#define TIMER_STATUS_TIMIL9  0x0002
-#define TIMER_STATUS_TIMIL10 0x0004
-#define TIMER_STATUS_TIMIL11 0x0008
-
-#define TIMER_STATUS_TOVF0   0x0010     /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1   0x0020
-#define TIMER_STATUS_TOVF2   0x0040
-#define TIMER_STATUS_TOVF3   0x00000080
-#define TIMER_STATUS_TOVF4   0x00100000
-#define TIMER_STATUS_TOVF5   0x00200000
-#define TIMER_STATUS_TOVF6   0x00400000
-#define TIMER_STATUS_TOVF7   0x00800000
-#define TIMER_STATUS_TOVF8   0x0010
-#define TIMER_STATUS_TOVF9   0x0020
-#define TIMER_STATUS_TOVF10  0x0040
-#define TIMER_STATUS_TOVF11  0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0  0x1000
-#define TIMER_STATUS_TRUN1  0x2000
-#define TIMER_STATUS_TRUN2  0x4000
-#define TIMER_STATUS_TRUN3  0x00008000
-#define TIMER_STATUS_TRUN4  0x10000000
-#define TIMER_STATUS_TRUN5  0x20000000
-#define TIMER_STATUS_TRUN6  0x40000000
-#define TIMER_STATUS_TRUN7  0x80000000
-#define TIMER_STATUS_TRUN   0xF000F000
-#define TIMER_STATUS_TRUN8  0x1000
-#define TIMER_STATUS_TRUN9  0x2000
-#define TIMER_STATUS_TRUN10 0x4000
-#define TIMER_STATUS_TRUN11 0x8000
-
-/* The actual gptimer API */
-
-void     set_gptimer_pwidth    (int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth    (int timer_id);
-void     set_gptimer_period    (int timer_id, uint32_t period);
-uint32_t get_gptimer_period    (int timer_id);
-uint32_t get_gptimer_count     (int timer_id);
-uint16_t get_gptimer_intr      (int timer_id);
-void     clear_gptimer_intr    (int timer_id);
-uint16_t get_gptimer_over      (int timer_id);
-void     clear_gptimer_over    (int timer_id);
-void     set_gptimer_config    (int timer_id, uint16_t config);
-uint16_t get_gptimer_config    (int timer_id);
-void     set_gptimer_pulse_hi  (int timer_id);
-void     clear_gptimer_pulse_hi(int timer_id);
-void     enable_gptimers       (uint16_t mask);
-void     disable_gptimers      (uint16_t mask);
-uint16_t get_enabled_gptimers  (void);
-uint32_t get_gptimer_status    (int group);
-void     set_gptimer_status    (int group, uint32_t value);
-
-#endif
diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h
deleted file mode 100644
index b6b19f1b9dab..000000000000
--- a/include/asm-blackfin/hardirq.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef __BFIN_HARDIRQ_H
-#define __BFIN_HARDIRQ_H
-
-#include <linux/cache.h>
-#include <linux/threads.h>
-#include <asm/irq.h>
-
-typedef struct {
-        unsigned int __softirq_pending;
-        unsigned int __syscall_count;
-        struct task_struct *__ksoftirqd_task;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-/*
- * We put the hardirq and softirq counter into the preemption
- * counter. The bitmask has the following meaning:
- *
- * - bits 0-7 are the preemption count (max preemption depth: 256)
- * - bits 8-15 are the softirq count (max # of softirqs: 256)
- * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
- *
- * - ( bit 26 is the PREEMPT_ACTIVE flag. )
- *
- * PREEMPT_MASK: 0x000000ff
- * HARDIRQ_MASK: 0x0000ff00
- * SOFTIRQ_MASK: 0x00ff0000
- */
-
-#if NR_IRQS > 256
-#define HARDIRQ_BITS    9
-#else
-#define HARDIRQ_BITS    8
-#endif
-
-#ifdef NR_IRQS
-# if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-# endif
-#endif
-
-#define __ARCH_IRQ_EXIT_IRQS_DISABLED   1
-
-#endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
deleted file mode 100644
index 5b51eaec012c..000000000000
--- a/include/asm-blackfin/hw_irq.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_BFIN_HW_IRQ_H
-#define __ASM_BFIN_HW_IRQ_H
-
-/* Dummy include. */
-
-#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
deleted file mode 100644
index cbbf7ffdbbff..000000000000
--- a/include/asm-blackfin/io.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef _BFIN_IO_H
-#define _BFIN_IO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-#include <linux/compiler.h>
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = b [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
-
-        return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = w [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
-
-        return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = [%2];\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
-        return val;
-}
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
-
-#define inb(addr)    readb(addr)
-#define inw(addr)    readw(addr)
-#define inl(addr)    readl(addr)
-#define outb(x,addr) ((void) writeb(x,addr))
-#define outw(x,addr) ((void) writew(x,addr))
-#define outl(x,addr) ((void) writel(x,addr))
-
-#define inb_p(addr)    inb(addr)
-#define inw_p(addr)    inw(addr)
-#define inl_p(addr)    inl(addr)
-#define outb_p(x,addr) outb(x,addr)
-#define outw_p(x,addr) outw(x,addr)
-#define outl_p(x,addr) outl(x,addr)
-
-#define ioread8_rep(a,d,c)      insb(a,d,c)
-#define ioread16_rep(a,d,c)     insw(a,d,c)
-#define ioread32_rep(a,d,c)     insl(a,d,c)
-#define iowrite8_rep(a,s,c)     outsb(a,s,c)
-#define iowrite16_rep(a,s,c)    outsw(a,s,c)
-#define iowrite32_rep(a,s,c)    outsl(a,s,c)
-
-#define ioread8(X)                      readb(X)
-#define ioread16(X)                     readw(X)
-#define ioread32(X)                     readl(X)
-#define iowrite8(val,X)                 writeb(val,X)
-#define iowrite16(val,X)                writew(val,X)
-#define iowrite32(val,X)                writel(val,X)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_NOCACHE_SER               1
-
-#ifndef __ASSEMBLY__
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-
-extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
-extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
-extern void dma_outsl(unsigned long port, const void *addr, unsigned short count);
-
-extern void dma_insb(unsigned long port, void *addr, unsigned short count);
-extern void dma_insw(unsigned long port, void *addr, unsigned short count);
-extern void dma_insl(unsigned long port, void *addr, unsigned short count);
-
-/*
- * Map some physical address range into the kernel address space.
- */
-static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
-                                int cacheflag)
-{
-        return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-static inline void iounmap(void *addr)
-{
-}
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-static inline void __iounmap(void *addr, unsigned long size)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-static inline void kernel_set_cachemode(void *addr, unsigned long size,
-                                        int cmode)
-{
-}
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void __iomem *ioremap_nocache(unsigned long physaddr,
-                                            unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-
-extern void blkfin_inv_cache_all(void);
-
-#endif
-
-#define ioport_map(port, nr)            ((void __iomem*)(port))
-#define ioport_unmap(addr)
-
-/* Pages to physical address... */
-#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BFIN_IO_H */
diff --git a/include/asm-blackfin/ioctl.h b/include/asm-blackfin/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/include/asm-blackfin/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/include/asm-blackfin/ioctls.h b/include/asm-blackfin/ioctls.h
deleted file mode 100644
index 895e3173165d..000000000000
--- a/include/asm-blackfin/ioctls.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef __ARCH_BFIN_IOCTLS_H__
-#define __ARCH_BFIN_IOCTLS_H__
-
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS          0x5401
-#define TCSETS          0x5402
-#define TCSETSW         0x5403
-#define TCSETSF         0x5404
-#define TCGETA          0x5405
-#define TCSETA          0x5406
-#define TCSETAW         0x5407
-#define TCSETAF         0x5408
-#define TCSBRK          0x5409
-#define TCXONC          0x540A
-#define TCFLSH          0x540B
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-#define TIOCGPGRP       0x540F
-#define TIOCSPGRP       0x5410
-#define TIOCOUTQ        0x5411
-#define TIOCSTI         0x5412
-#define TIOCGWINSZ      0x5413
-#define TIOCSWINSZ      0x5414
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define FIONREAD        0x541B
-#define TIOCINQ         FIONREAD
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-#define FIONBIO         0x5421
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCTTYGSTRUCT  0x5426  /* For debugging only */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TCGETS2         _IOR('T', 0x2A, struct termios2)
-#define TCSETS2         _IOW('T', 0x2B, struct termios2)
-#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
-#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
-/* Get Pty Number (of pty-mux device) */
-#define TIOCGPTN        _IOR('T', 0x30, unsigned int)
-#define TIOCSPTLCK      _IOW('T', 0x31, int)    /* Lock/unlock Pty */
-
-#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
-#define FIOCLEX         0x5451
-#define FIOASYNC        0x5452
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458  /* For debugging only */
-#define TIOCSERGETLSR   0x5459  /* Get line status register */
-#define TIOCSERGETMULTI 0x545A  /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B  /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-
-#define FIOQSIZE        0x545E
-
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
-
-#endif                          /* __ARCH_BFIN_IOCTLS_H__ */
diff --git a/include/asm-blackfin/ipcbuf.h b/include/asm-blackfin/ipcbuf.h
deleted file mode 100644
index 8f0899cdf4d2..000000000000
--- a/include/asm-blackfin/ipcbuf.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Changes origined from m68k version.    Lineo Inc.  May 2001   */
-
-#ifndef __BFIN_IPCBUF_H__
-#define __BFIN_IPCBUF_H__
-
-/*
- * The user_ipc_perm structure for m68k architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-
-struct ipc64_perm {
-        __kernel_key_t key;
-        __kernel_uid32_t uid;
-        __kernel_gid32_t gid;
-        __kernel_uid32_t cuid;
-        __kernel_gid32_t cgid;
-        __kernel_mode_t mode;
-        unsigned short __pad1;
-        unsigned short seq;
-        unsigned short __pad2;
-        unsigned long __unused1;
-        unsigned long __unused2;
-};
-
-#endif                          /* __BFIN_IPCBUF_H__ */
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
deleted file mode 100644
index 86b67834354d..000000000000
--- a/include/asm-blackfin/irq.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- *
- * Changed by HuTao Apr18, 2003
- *
- * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
- * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
- * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
- *
- * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
- * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
- * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
- */
-
-#ifndef _BFIN_IRQ_H_
-#define _BFIN_IRQ_H_
-
-#include <asm/mach/irq.h>
-#include <asm/ptrace.h>
-
-/*******************************************************************************
- *****   INTRODUCTION ***********
- *   On the Blackfin, the interrupt structure allows remmapping of the hardware
- *   levels.
- * - I'm going to assume that the H/W level is going to stay at the default
- *   settings. If someone wants to go through and abstart this out, feel free
- *   to mod the interrupt numbering scheme.
- * - I'm abstracting the interrupts so that uClinux does not know anything
- *   about the H/W levels. If you want to change the H/W AND keep the abstracted
- *   levels that uClinux sees, you should be able to do most of it here.
- * - I've left the "abstract" numbering sparce in case someone wants to pull the
- *   interrupts apart (just the TX/RX for the various devices)
- *******************************************************************************/
-
-/* SYS_IRQS and NR_IRQS are defined in <asm/mach-bf5xx/irq.h>*/
-
-/*
- * Machine specific interrupt sources.
- *
- * Adding an interrupt service routine for a source with this bit
- * set indicates a special machine specific interrupt source.
- * The machine specific files define these sources.
- *
- * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
- * introduce unnecessary overhead.
- *
- * All interrupt handling is actually machine specific so it is better
- * to use function pointers, as used by the Sparc port, and select the
- * interrupt handling functions when initializing the kernel. This way
- * we save some unnecessary overhead at run-time.
- *                                                      01/11/97 - Jes
- */
-
-extern void ack_bad_irq(unsigned int irq);
-
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
-/* count of spurious interrupts */
-/* extern volatile unsigned int num_spurious; */
-
-#ifndef NO_IRQ
-#define NO_IRQ ((unsigned int)(-1))
-#endif
-
-#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
-
-#endif                          /* _BFIN_IRQ_H_ */
diff --git a/include/asm-blackfin/irq_handler.h b/include/asm-blackfin/irq_handler.h
deleted file mode 100644
index 139b5208f9d8..000000000000
--- a/include/asm-blackfin/irq_handler.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _IRQ_HANDLER_H
-#define _IRQ_HANDLER_H
-
-#include <linux/types.h>
-#include <linux/linkage.h>
-
-/* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-asmlinkage void init_exception_buff(void);
-asmlinkage void trap_c(struct pt_regs *fp);
-asmlinkage void ex_replaceable(void);
-asmlinkage void early_trap(void);
-
-extern void *ex_table[];
-extern void return_from_exception(void);
-
-extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
-extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
-
-#endif
diff --git a/include/asm-blackfin/irq_regs.h b/include/asm-blackfin/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-blackfin/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-blackfin/kdebug.h b/include/asm-blackfin/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-blackfin/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h
deleted file mode 100644
index 0f73847fd6bc..000000000000
--- a/include/asm-blackfin/kgdb.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * File:         include/asm-blackfin/kgdb.h
- * Based on:
- * Author:       Sonic Zhang
- *
- * Created:
- * Description:
- *
- * Rev:          $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
- *
- * Modified:
- *               Copyright 2005-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-#include <linux/ptrace.h>
-
-/* gdb locks */
-#define KGDB_MAX_NO_CPUS 8
-
-/************************************************************************/
-/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
-/* at least NUMREGBYTES*2 are needed for register packets */
-/* Longer buffer is needed to list all threads */
-#define BUFMAX 2048
-
-/*
- *  Note that this register image is different from
- *  the register image that Linux produces at interrupt time.
- *  
- *  Linux's register image is defined by struct pt_regs in ptrace.h.
- */
-enum regnames {
-  /* Core Registers */
-  BFIN_R0 = 0,
-  BFIN_R1,
-  BFIN_R2,
-  BFIN_R3,
-  BFIN_R4,
-  BFIN_R5,
-  BFIN_R6,
-  BFIN_R7,
-  BFIN_P0,
-  BFIN_P1,
-  BFIN_P2,
-  BFIN_P3,
-  BFIN_P4,
-  BFIN_P5,
-  BFIN_SP,
-  BFIN_FP,
-  BFIN_I0,
-  BFIN_I1,
-  BFIN_I2,
-  BFIN_I3,
-  BFIN_M0,
-  BFIN_M1,
-  BFIN_M2,
-  BFIN_M3,
-  BFIN_B0,
-  BFIN_B1,
-  BFIN_B2,
-  BFIN_B3,
-  BFIN_L0,
-  BFIN_L1,
-  BFIN_L2,
-  BFIN_L3,
-  BFIN_A0_DOT_X,
-  BFIN_A0_DOT_W,
-  BFIN_A1_DOT_X,
-  BFIN_A1_DOT_W,
-  BFIN_ASTAT,
-  BFIN_RETS,
-  BFIN_LC0,
-  BFIN_LT0,
-  BFIN_LB0,
-  BFIN_LC1,
-  BFIN_LT1,
-  BFIN_LB1,
-  BFIN_CYCLES,
-  BFIN_CYCLES2,
-  BFIN_USP,
-  BFIN_SEQSTAT,
-  BFIN_SYSCFG,
-  BFIN_RETI,
-  BFIN_RETX,
-  BFIN_RETN,
-  BFIN_RETE,
-  
-  /* Pseudo Registers */
-  BFIN_PC,
-  BFIN_CC,
-  BFIN_EXTRA1,          /* Address of .text section.  */
-  BFIN_EXTRA2,          /* Address of .data section.  */
-  BFIN_EXTRA3,          /* Address of .bss section.  */
-  BFIN_FDPIC_EXEC, 
-  BFIN_FDPIC_INTERP,
-
-  /* MMRs */
-  BFIN_IPEND,
-
-  /* LAST ENTRY SHOULD NOT BE CHANGED.  */
-  BFIN_NUM_REGS         /* The number of all registers.  */
-};
-
-/* Number of bytes of registers.  */
-#define NUMREGBYTES BFIN_NUM_REGS*4
-
-#define BREAKPOINT() asm("   EXCPT 2;");
-#define BREAK_INSTR_SIZE       2
-#define HW_BREAKPOINT_NUM               6
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR           0x1
-#define WPIREN01        0x2
-#define WPIRINV01       0x4
-#define WPIAEN0         0x8
-#define WPIAEN1         0x10
-#define WPICNTEN0       0x20
-#define WPICNTEN1       0x40
-#define EMUSW0          0x80
-#define EMUSW1          0x100
-#define WPIREN23        0x200
-#define WPIRINV23       0x400
-#define WPIAEN2         0x800
-#define WPIAEN3         0x1000
-#define WPICNTEN2       0x2000
-#define WPICNTEN3       0x4000
-#define EMUSW2          0x8000
-#define EMUSW3          0x10000
-#define WPIREN45        0x20000
-#define WPIRINV45       0x40000
-#define WPIAEN4         0x80000
-#define WPIAEN5         0x100000
-#define WPICNTEN4       0x200000
-#define WPICNTEN5       0x400000
-#define EMUSW4          0x800000
-#define EMUSW5          0x1000000
-#define WPAND           0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01        0x1
-#define WPDRINV01       0x2
-#define WPDAEN0         0x4
-#define WPDAEN1         0x8
-#define WPDCNTEN0       0x10
-#define WPDCNTEN1       0x20
-#define WPDSRC0         0xc0
-#define WPDACC0         0x300
-#define WPDSRC1         0xc00
-#define WPDACC1         0x3000
-
-/* Watchpoint status register bits mask */
-#define STATIA0         0x1
-#define STATIA1         0x2
-#define STATIA2         0x4
-#define STATIA3         0x8
-#define STATIA4         0x10
-#define STATIA5         0x20
-#define STATDA0         0x40
-#define STATDA1         0x80
-
-extern void kgdb_print(const char *fmt, ...);
-extern void init_kgdb_uart(void);
-
-#endif
diff --git a/include/asm-blackfin/kmap_types.h b/include/asm-blackfin/kmap_types.h
deleted file mode 100644
index e215f7104974..000000000000
--- a/include/asm-blackfin/kmap_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
-
-#endif
diff --git a/include/asm-blackfin/l1layout.h b/include/asm-blackfin/l1layout.h
deleted file mode 100644
index c13ded777828..000000000000
--- a/include/asm-blackfin/l1layout.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * l1layout.h
- * Defines a layout of L1 scratchpad memory that userspace can rely on.
- */
-
-#ifndef _L1LAYOUT_H_
-#define _L1LAYOUT_H_
-
-#include <asm/blackfin.h>
-
-#ifndef __ASSEMBLY__
-
-/* Data that is "mapped" into the process VM at the start of the L1 scratch
-   memory, so that each process can access it at a fixed address.  Used for
-   stack checking.  */
-struct l1_scratch_task_info
-{
-        /* Points to the start of the stack.  */
-        void *stack_start;
-        /* Not updated by the kernel; a user process can modify this to
-           keep track of the lowest address of the stack pointer during its
-           runtime.  */
-        void *lowest_sp;
-};
-
-/* A pointer to the structure in memory.  */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
-
-#endif
-
-#endif
diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
deleted file mode 100644
index 5a822bb790f7..000000000000
--- a/include/asm-blackfin/linkage.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/include/asm-blackfin/local.h b/include/asm-blackfin/local.h
deleted file mode 100644
index 75afffbc6421..000000000000
--- a/include/asm-blackfin/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BLACKFIN_LOCAL_H
-#define __BLACKFIN_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif                          /* __BLACKFIN_LOCAL_H */
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
deleted file mode 100644
index b7b166f4f064..000000000000
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf527/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* New Feature: EMAC TX DMA Word Alignment */
-#define ANOMALY_05000285 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (1)
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (1)
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* New Feature: Higher Default CCLK Rate */
-#define ANOMALY_05000368 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (1)
-/* USB Full-speed Mode not Fully Tested */
-#define ANOMALY_05000381 (1)
-/* New Feature: Boot from OTP Memory */
-#define ANOMALY_05000385 (1)
-/* New Feature: bfrom_SysControl() Routine */
-#define ANOMALY_05000386 (1)
-/* New Feature: Programmable Preboot Settings */
-#define ANOMALY_05000387 (1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (1)
-/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (1)
-/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (1)
-/* New Feature: Log Buffer Functionality */
-#define ANOMALY_05000394 (1)
-/* New Feature: Hook Routine Functionality */
-#define ANOMALY_05000395 (1)
-/* New Feature: Header Indirect Bit */
-#define ANOMALY_05000396 (1)
-/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
-#define ANOMALY_05000397 (1)
-/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
-#define ANOMALY_05000398 (1)
-/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
-#define ANOMALY_05000399 (1)
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf527/bf527.h b/include/asm-blackfin/mach-bf527/bf527.h
deleted file mode 100644
index 056eb4b9cd25..000000000000
--- a/include/asm-blackfin/mach-bf527/bf527.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/bf527.h
- * Based on:    include/asm-blackfin/mach-bf537/bf537.h
- * Author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define SUPPORTED_REVID 2
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR    0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF527_H__  */
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
deleted file mode 100644
index 2526b6ed6faa..000000000000
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port port;
-        unsigned int old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int tx_done;
-        int tx_count;
-        struct circ_buf rx_dma_buf;
-        struct timer_list rx_dma_timer;
-        int rx_dma_nrows;
-        unsigned int tx_dma_channel;
-        unsigned int rx_dma_channel;
-        struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list cts_timer;
-        int cts_pin;
-        int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long uart_base_addr;
-        int uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int uart_tx_dma_channel;
-        unsigned int uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int uart_cts_pin;
-        int uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-         0xFFC00400,
-         IRQ_UART0_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART0_TX,
-         CH_UART0_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-         CONFIG_UART0_CTS_PIN,
-         CONFIG_UART0_RTS_PIN,
-#endif
-         },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-         0xFFC02000,
-         IRQ_UART1_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART1_TX,
-         CH_UART1_RX,
-#endif
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-         CONFIG_UART1_CTS_PIN,
-         CONFIG_UART1_RTS_PIN,
-#endif
-         },
-#endif
-};
-
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
-#define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h
deleted file mode 100644
index cfd8ad4f1f2c..000000000000
--- a/include/asm-blackfin/mach-bf527/bfin_sir.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
deleted file mode 100644
index 297821e2d79a..000000000000
--- a/include/asm-blackfin/mach-bf527/blackfin.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF527_FAMILY
-
-#include "bf527.h"
-#include "mem_map.h"
-#include "defBF522.h"
-#include "anomaly.h"
-
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "defBF527.h"
-#endif
-
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "defBF525.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF522.h"
-
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "cdefBF527.h"
-#endif
-
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "cdefBF525.h"
-#endif
-#endif
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-/* DPMC*/
-#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
-#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
-#define STOPCK_OFF STOPCK
-
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf527/cdefBF522.h b/include/asm-blackfin/mach-bf527/cdefBF522.h
deleted file mode 100644
index 52c06494b886..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF522.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefbf522.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* include all Core registers and bit definitions */
-#include "defBF522.h"
-
-/* include core specific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-#endif /* _CDEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF525.h b/include/asm-blackfin/mach-bf527/cdefBF525.h
deleted file mode 100644
index 2cc67e4b4d86..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF525.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefbf525.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* include all Core registers and bit definitions */
-#include "defBF525.h"
-
-/* include core specific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF527.h b/include/asm-blackfin/mach-bf527/cdefBF527.h
deleted file mode 100644
index 5bd1a8601743..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF527.h
+++ /dev/null
@@ -1,626 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefbf527.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* include all Core registers and bit definitions */
-#include "defBF527.h"
-
-/* include core specific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
-
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE()                 bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)             bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()                 bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)             bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()                 bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)             bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()                 bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)             bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()                 bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)             bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()                 bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)             bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()                 bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)             bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()                    bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)                bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()                  bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)              bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()                  bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)              bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()               bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)           bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()            bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val)        bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()            bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val)        bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()            bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val)        bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()            bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val)        bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()             bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val)         bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()             bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val)         bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()            bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val)        bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()            bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val)        bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL()                 bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)             bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()                 bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)             bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()                bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)            bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()                bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)            bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()                bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)            bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()                bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)            bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()                bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)            bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()                bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)            bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL()                bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)            bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()              bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val)          bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()              bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val)          bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()              bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val)          bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()              bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val)          bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK()                 bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)             bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()                bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)            bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()              bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val)          bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()              bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val)          bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()             bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val)         bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()             bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val)         bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()              bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val)          bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()              bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val)          bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()             bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val)         bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()             bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val)         bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()               bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)           bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()             bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val)         bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()             bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val)         bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()              bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val)          bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()             bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val)         bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()             bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val)         bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()              bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val)          bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()              bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val)          bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()               bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)           bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()              bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val)          bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()              bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val)          bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()              bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val)          bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()             bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val)         bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()             bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val)         bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK()                 bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)             bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()               bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)           bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()             bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val)         bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()              bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val)          bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()              bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val)          bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()             bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val)         bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()             bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val)         bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()             bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val)         bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()             bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val)         bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()             bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val)         bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()              bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val)          bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()              bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val)          bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()             bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val)         bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()             bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val)         bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()             bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val)         bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()             bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val)         bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()               bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)           bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()              bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val)          bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()              bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val)          bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()              bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val)          bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()             bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val)         bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()             bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val)         bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
deleted file mode 100644
index 9dbdbec8ea1b..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ /dev/null
@@ -1,1204 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefBF52x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <asm/system.h>
-#include <asm/blackfin.h>
-
-#include "defBF52x_base.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* ==== begin from cdefBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                       bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX32)
-#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX32, val)
-#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX32)
-#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX32, val)
-#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX16)
-#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX16, val)
-#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX16)
-#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX16, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX32)
-#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX32, val)
-#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX32)
-#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX32, val)
-#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX16)
-#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX16, val)
-#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX16)
-#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX16, val)
-#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
-#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
-#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
-#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
-
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()                 bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)             bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()                     bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)                 bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()                  bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)              bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()                  bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)              bfin_write32(OTP_TIMING, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()                   bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)               bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()                   bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)               bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()                   bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)               bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()                   bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)               bfin_write32(OTP_DATA3, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF522.h b/include/asm-blackfin/mach-bf527/defBF522.h
deleted file mode 100644
index 9671d8f2c5ef..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF522.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF522.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-#endif /* _DEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF525.h b/include/asm-blackfin/mach-bf527/defBF525.h
deleted file mode 100644
index 6a375a084acc..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF525.h
+++ /dev/null
@@ -1,713 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF525.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
deleted file mode 100644
index f1a70db70cb8..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF527.h
+++ /dev/null
@@ -1,1090 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF527.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE                 0x00000001     /* Receiver Enable                                    */
-#define ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define RAF                0x00001000     /* Receive-All Mode                                   */
-#define TE                 0x00010000     /* Transmitter Enable                                 */
-#define DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define DC                 0x00080000     /* Deferral Check                                     */
-#define BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define BOLMT_10           0x00000000     /*            10-bit range                            */
-#define BOLMT_8            0x00100000     /*            8-bit range                             */
-#define BOLMT_4            0x00200000     /*            4-bit range                             */
-#define BOLMT_1            0x00300000     /*            1-bit range                             */
-#define DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define LB                 0x08000000     /* Internal Loopback Enable                           */
-#define DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define REGAD              0x000007C0     /* STA Register Address                               */
-#define PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#define SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define FLCE               0x00000002     /* Flow Control Enable                                */
-#define PCF                0x00000004     /* Pass Control Frames                                */
-#define BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
-#define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC              0x00000001    /* Reset All Counters                                     */
-#define CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
deleted file mode 100644
index fc69cf93f149..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ /dev/null
@@ -1,2014 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF52x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF52X_H
-#define _DEF_BF52X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID        0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
-
-#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
-#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
-#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-
-/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */   
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
-#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
-#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
-#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)               /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
-
-#if 0
-#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */ 
-#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */ 
-#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */ 
-#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
-#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
-
-#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
-#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
-#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
-#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */ 
-#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
-#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
-#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
-#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
-
-#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
-#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
-#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
-#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
-#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
-#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
-#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
-#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
-#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
-#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
-
-#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
-#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
-#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
-#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
-#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
-#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
-#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
-#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
-#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
-#endif
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */ 
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define TMR_DIS WDDIS
-#define TRO WDRO
-#define ICTL_P0 0x01
- #define ICTL_P1 0x02
-#define TRO_P 0x0F
-
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks                                                                         */
-#define RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
-#define RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
-#define RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
-#define RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
-
-/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
-#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-
-/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                         */
-#define STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
-#define ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
-#define SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
-#define MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
-#define HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
-#define DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
-#define DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
-#define WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
-#define WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
-
-/* RTC_FAST / RTC_PREN Mask                                                                                             */
-#define PREN                            0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#define STB                     0x04                            /* Stop Bits                    */
-#define PEN                     0x08                            /* Parity Enable                */
-#define EPS                     0x10                            /* Even Parity Select   */
-#define STP                     0x20                            /* Stick Parity                 */
-#define SB                      0x40                            /* Set Break                    */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04            /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01            /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02            /* UART_THR empty                               */
-#define IIR_RX_READY    0x04            /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */ 
-#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01            /* Enable UARTx Clocks                          */
-#define IREN            0x02            /* Enable IrDA Mode                                     */
-#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
-#define FPE                     0x10            /* Force Parity Error On Transmit       */
-#define FFE                     0x20            /* Force Framing Error On Transmit      */
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks                                                                                                                                        */
-#define TIMOD           0x0003          /* Transfer Initiate Mode                                                       */
-#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                      0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
-#define GM                      0x0008          /* Get More (When RDBR Full, Overwrite/Discard*)        */
-#define PSSE            0x0010          /* Slave-Select Input Enable                                            */
-#define EMISO           0x0020          /* Enable MISO As Output                                                        */
-#define SIZE            0x0100          /* Size of Words (16/8* Bits)                                           */
-#define LSBF            0x0200          /* LSB First                                                                            */
-#define CPHA            0x0400          /* Clock Phase                                                                          */
-#define CPOL            0x0800          /* Clock Polarity                                                                       */
-#define MSTR            0x1000          /* Master/Slave*                                                                        */
-#define WOM                     0x2000          /* Write Open Drain Master                                                      */
-#define SPE                     0x4000          /* SPI Enable                                                                           */
-
-/* SPI_FLG Masks                                                                                                                                        */
-#define FLS1            0x0002          /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
-#define FLS2            0x0004          /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
-#define FLS3            0x0008          /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
-#define FLS4            0x0010          /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
-#define FLS5            0x0020          /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
-#define FLS6            0x0040          /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
-#define FLS7            0x0080          /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
-#define FLG1            0xFDFF          /* Activates SPI_FLOUT1                                                         */
-#define FLG2            0xFBFF          /* Activates SPI_FLOUT2                                                         */
-#define FLG3            0xF7FF          /* Activates SPI_FLOUT3                                                         */
-#define FLG4            0xEFFF          /* Activates SPI_FLOUT4                                                         */
-#define FLG5            0xDFFF          /* Activates SPI_FLOUT5                                                         */
-#define FLG6            0xBFFF          /* Activates SPI_FLOUT6                                                         */
-#define FLG7            0x7FFF          /* Activates SPI_FLOUT7                                                         */
-
-/* SPI_STAT Masks                                                                                                                                                               */
-#define SPIF            0x0001          /* SPI Finished (Single-Word Transfer Complete)                                 */
-#define MODF            0x0002          /* Mode Fault Error (Another Device Tried To Become Master)             */
-#define TXE                     0x0004          /* Transmission Error (Data Sent With No New Data In TDBR)              */
-#define TXS                     0x0008          /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
-#define RBSY            0x0010          /* Receive Error (Data Received With RDBR Full)                                 */
-#define RXS                     0x0020          /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
-#define TXCOL           0x0040          /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001          /* Transmit Enable                                                              */
-#define ITCLK           0x0002          /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010          /* Transmit Bit Order                                                   */
-#define ITFS            0x0200          /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400          /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800          /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000          /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000          /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100          /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200          /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001          /* Receive Enable                                                               */
-#define IRCLK           0x0002          /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010          /* Receive Bit Order                                                    */
-#define IRFS            0x0200          /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400          /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000          /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000          /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100          /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200          /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400          /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001          /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002          /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004          /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008          /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010          /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020          /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040          /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)      ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004          /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008          /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010          /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080          /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
-#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
-#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
-#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001          /* DMA Channel Enable                                                   */
-#define WNR                             0x0002          /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000          /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004          /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008          /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010          /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020          /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040          /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080          /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100          /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200          /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300          /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400          /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500          /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600          /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700          /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800          /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900          /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000          /* Stop Mode                                                                    */
-#define DMAFLOW_AUTO            0x1000          /* Autobuffer Mode                                                              */
-#define DMAFLOW_ARRAY           0x4000          /* Descriptor Array Mode                                                */
-#define DMAFLOW_SMALL           0x6000          /* Small Model Descriptor List Mode                             */
-#define DMAFLOW_LARGE           0x7000          /* Large Model Descriptor List Mode                             */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002          /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
-#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
-#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
-#define DLENGTH                 0x3800          /* PPI Data Length  */
-#define POLC                    0x4000          /* PPI Clock Polarity                           */
-#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400          /* Field Indicator                                      */
-#define FT_ERR                  0x0800          /* Frame Track Error                            */
-#define OVR                             0x1000          /* FIFO Overflow Error                          */
-#define UNDR                    0x2000          /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTRL Masks                                                                                                                 */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTRL Masks                                                                                                        */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010                  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000 
-#define _BOOTROM_FINAL_INIT 0xEF000002 
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
-#define                  HOST_CNTR_nHOST_EN  0x0
-#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
-#define                 HOST_CNTR_nHOST_END  0x0
-#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
-#define                HOST_CNTR_nDATA_SIZE  0x0
-#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
-#define                 HOST_CNTR_nHOST_RST  0x0
-#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
-#define                 HOST_CNTR_nHRDY_OVR  0x0
-#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
-#define                 HOST_CNTR_nINT_MODE  0x0
-#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
-#define                   HOST_CNTR_ nBT_EN  0x0
-#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
-#define                      HOST_CNTR_nEHW  0x0
-#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
-#define                      HOST_CNTR_nEHR  0x0
-#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
-#define                      HOST_CNTR_nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                     HOST_STAT_READY  0x1        /* DMA Ready */
-#define                    HOST_STAT_nREADY  0x0
-#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
-#define                 HOST_STAT_nFIFOFULL  0x0
-#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
-#define                HOST_STAT_nFIFOEMPTY  0x0
-#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
-#define                 HOST_STAT_nCOMPLETE  0x0
-#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
-#define                     HOST_STAT_nHSHK  0x0
-#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
-#define                  HOST_STAT_nTIMEOUT  0x0
-#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
-#define                     HOST_STAT_nHIRQ  0x0
-#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               HOST_STAT_nALLOW_CNFG  0x0
-#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
-#define                  HOST_STAT_nDMA_DIR  0x0
-#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
-#define                      HOST_STAT_nBTE  0x0
-#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              HOST_STAT_nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0       
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0       
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0       
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0       
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0       
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0       
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0       
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0       
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0       
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0       
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0       
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0       
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0       
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0       
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0       
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0       
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0       
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0       
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0       
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0       
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0       
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0       
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0       
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0       
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0       
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0       
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0       
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0       
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0       
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0       
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                     nFIEN  0x0       
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                 nFTESTDEC  0x0       
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                  nFWRTEST  0x0       
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                    nFRDEN  0x0       
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-#define                    nFWREN  0x0       
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    nFCOMP  0x0       
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                   nFERROR  0x0       
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                 nMMRGLOAD  0x0       
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                 nMMRGLOCK  0x0       
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-#define                   nFPGMEN  0x0       
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0       
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0       
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0       
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0       
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0       
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0       
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0       
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0       
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0       
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0       
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0       
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0       
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0       
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   nNWIDTH  0x0       
-#define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0       
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0       
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0       
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0       
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0       
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0       
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0       
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0       
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0       
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0       
-#define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0       
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0       
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0       
-#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define             nMASK_WBEMPTY  0x0       
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0       
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0       
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0       
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0       
-#define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0       
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-
-#endif /* _DEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
deleted file mode 100644
index 49dd693223e8..000000000000
--- a/include/asm-blackfin/mach-bf527/dma.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/dma.h
- * based on:    include/asm-blackfin/mach-bf537/dma.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * created:
- * description:
- *      system DMA map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 16
-
-#define CH_PPI                  0       /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX              1       /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP          1       /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX              2       /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX            3       /* SPORT0 receive */
-#define CH_SPORT0_TX            4       /* SPORT0 transmit */
-#define CH_SPORT1_RX            5       /* SPORT1 receive */
-#define CH_SPORT1_TX            6       /* SPORT1 transmit */
-#define CH_SPI                  7       /* SPI transmit/receive */
-#define CH_UART0_RX             8       /* UART0 receive */
-#define CH_UART0_TX             9       /* UART0 transmit */
-#define CH_UART1_RX             10      /* UART1 receive */
-#define CH_UART1_TX             11      /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST     12      /* TX */
-#define CH_MEM_STREAM0_SRC      13      /* RX */
-#define CH_MEM_STREAM1_DEST     14      /* TX */
-#define CH_MEM_STREAM1_SRC      15      /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC                  CH_PPI  /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC                  CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
deleted file mode 100644
index 4e2b3f2020e5..000000000000
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/irq.h
- * based on:    include/asm-blackfin/mach-bf537/irq.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-/*
- * Interrupt source definitions
-        Event Source    Core Event Name
-        Core        Emulation               **
-        Events         (highest priority)  EMU         0
-        Reset                   RST         1
-        NMI                     NMI         2
-        Exception               EVX         3
-        Reserved                --          4
-        Hardware Error          IVHW        5
-        Core Timer              IVTMR       6 *
-
-        .....
-
-         Software Interrupt 1    IVG14       31
-         Software Interrupt 2    --
-         (lowest priority)  IVG15       32 *
-*/
-
-#define NR_PERI_INTS    (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
-
-#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK           BFIN_IRQ(2)     /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK           BFIN_IRQ(3)     /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR           BFIN_IRQ(4)     /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR           BFIN_IRQ(5)     /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR           BFIN_IRQ(6)     /* PPI Error */
-#define IRQ_MAC_ERROR           BFIN_IRQ(7)     /* MAC Status */
-#define IRQ_SPORT0_ERROR        BFIN_IRQ(8)     /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR        BFIN_IRQ(9)     /* SPORT1 Status */
-#define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
-#define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
-#define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
-#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
-#define IRQ_SPI                 BFIN_IRQ(21)    /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
-#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
-#define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC                 BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
-#define IRQ_TMR0                BFIN_IRQ(32)    /* Timer 0 */
-#define IRQ_TMR1                BFIN_IRQ(33)    /* Timer 1 */
-#define IRQ_TMR2                BFIN_IRQ(34)    /* Timer 2 */
-#define IRQ_TMR3                BFIN_IRQ(35)    /* Timer 3 */
-#define IRQ_TMR4                BFIN_IRQ(36)    /* Timer 4 */
-#define IRQ_TMR5                BFIN_IRQ(37)    /* Timer 5 */
-#define IRQ_TMR6                BFIN_IRQ(38)    /* Timer 6 */
-#define IRQ_TMR7                BFIN_IRQ(39)    /* Timer 7 */
-#define IRQ_PORTG_INTA          BFIN_IRQ(40)    /* Port G Interrupt A */
-#define IRQ_PORTG_INTB          BFIN_IRQ(41)    /* Port G Interrupt B */
-#define IRQ_MEM_DMA0            BFIN_IRQ(42)    /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1            BFIN_IRQ(43)    /* MDMA Stream 1 */
-#define IRQ_WATCH               BFIN_IRQ(44)    /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA          BFIN_IRQ(45)    /* Port F Interrupt A */
-#define IRQ_PORTF_INTB          BFIN_IRQ(46)    /* Port F Interrupt B */
-#define IRQ_SPI_ERROR           BFIN_IRQ(47)    /* SPI Status */
-#define IRQ_NFC_ERROR           BFIN_IRQ(48)    /* NAND Error */
-#define IRQ_HDMA_ERROR          BFIN_IRQ(49)    /* HDMA Error */
-#define IRQ_HDMA                BFIN_IRQ(50)    /* HDMA (TFI) */
-#define IRQ_USB_EINT            BFIN_IRQ(51)    /* USB_EINT Interrupt */
-#define IRQ_USB_INT0            BFIN_IRQ(52)    /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1            BFIN_IRQ(53)    /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2            BFIN_IRQ(54)    /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA             BFIN_IRQ(55)    /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
-
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define IRQ_PG0         87
-#define IRQ_PG1         88
-#define IRQ_PG2         89
-#define IRQ_PG3         90
-#define IRQ_PG4         91
-#define IRQ_PG5         92
-#define IRQ_PG6         93
-#define IRQ_PG7         94
-#define IRQ_PG8         95
-#define IRQ_PG9         96
-#define IRQ_PG10        97
-#define IRQ_PG11        98
-#define IRQ_PG12        99
-#define IRQ_PG13        100
-#define IRQ_PG14        101
-#define IRQ_PG15        102
-
-#define IRQ_PH0         103
-#define IRQ_PH1         104
-#define IRQ_PH2         105
-#define IRQ_PH3         106
-#define IRQ_PH4         107
-#define IRQ_PH5         108
-#define IRQ_PH6         109
-#define IRQ_PH7         110
-#define IRQ_PH8         111
-#define IRQ_PH9         112
-#define IRQ_PH10        113
-#define IRQ_PH11        114
-#define IRQ_PH12        115
-#define IRQ_PH13        116
-#define IRQ_PH14        117
-#define IRQ_PH15        118
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define NR_IRQS     (IRQ_PH15+1)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS      0
-#define IRQ_DMA0_ERROR_POS      4
-#define IRQ_DMAR0_BLK_POS       8
-#define IRQ_DMAR1_BLK_POS       12
-#define IRQ_DMAR0_OVR_POS       16
-#define IRQ_DMAR1_OVR_POS       20
-#define IRQ_PPI_ERROR_POS       24
-#define IRQ_MAC_ERROR_POS       28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS    0
-#define IRQ_SPORT1_ERROR_POS    4
-#define IRQ_UART0_ERROR_POS     16
-#define IRQ_UART1_ERROR_POS     20
-#define IRQ_RTC_POS             24
-#define IRQ_PPI_POS             28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS       0
-#define IRQ_SPORT0_TX_POS       4
-#define IRQ_SPORT1_RX_POS       8
-#define IRQ_SPORT1_TX_POS       12
-#define IRQ_TWI_POS             16
-#define IRQ_SPI_POS             20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS        0
-#define IRQ_UART1_TX_POS        4
-#define IRQ_OPTSEC_POS          8
-#define IRQ_CNT_POS             12
-#define IRQ_MAC_RX_POS          16
-#define IRQ_PORTH_INTA_POS      20
-#define IRQ_MAC_TX_POS          24
-#define IRQ_PORTH_INTB_POS      28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TMR0_POS            0
-#define IRQ_TMR1_POS            4
-#define IRQ_TMR2_POS            8
-#define IRQ_TMR3_POS            12
-#define IRQ_TMR4_POS            16
-#define IRQ_TMR5_POS            20
-#define IRQ_TMR6_POS            24
-#define IRQ_TMR7_POS            28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS      0
-#define IRQ_PORTG_INTB_POS      4
-#define IRQ_MEM_DMA0_POS        8
-#define IRQ_MEM_DMA1_POS        12
-#define IRQ_WATCH_POS           16
-#define IRQ_PORTF_INTA_POS      20
-#define IRQ_PORTF_INTB_POS      24
-#define IRQ_SPI_ERROR_POS       28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS       0
-#define IRQ_HDMA_ERROR_POS      4
-#define IRQ_HDMA_POS            8
-#define IRQ_USB_EINT_POS        12
-#define IRQ_USB_INT0_POS        16
-#define IRQ_USB_INT1_POS        20
-#define IRQ_USB_INT2_POS        24
-#define IRQ_USB_DMA_POS         28
-
-#endif                          /* _BF527_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf527/mem_init.h b/include/asm-blackfin/mach-bf527/mem_init.h
deleted file mode 100644
index cbe03f4a5698..000000000000
--- a/include/asm-blackfin/mach-bf527/mem_init.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
deleted file mode 100644
index 193082deaa4e..000000000000
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf527/mem_map.h
- * based on:    include/asm-blackfin/mach-bf537/mem_map.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * created:
- * description:
- *      Memory MAP Common header file for blackfin BF527/5/2 of processors.
- * rev:
- *
- * modified:
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MEM_MAP_527_H_
-#define _MEM_MAP_527_H_
-
-#define COREMMR_BASE           0xFFE00000       /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000       /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x20300000      /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK2_BASE        0x20200000      /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK1_BASE        0x20100000      /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK0_BASE        0x20000000      /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif                          /*CONFIG_BFIN_DCACHE */
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
deleted file mode 100644
index ae4d205bfcf5..000000000000
--- a/include/asm-blackfin/mach-bf527/portmux.h
+++ /dev/null
@@ -1,207 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_HWAIT         (P_DONTCARE)
-
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7               (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC           (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD       (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE       (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1       (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2       (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5       (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6       (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7       (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE       (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE       (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE       (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB       (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE      (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1       (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2       (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5       (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6       (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7       (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8       (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9       (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10      (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11      (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12      (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13      (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14      (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO          (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL      (P_DONTCARE)
-#define P_TWI0_SDA      (P_DONTCARE)
-#define P_PPI0_FS1      (P_DONTCARE)
-#define P_TMR0          (P_DONTCARE)
-#define P_TMRCLK        (P_DONTCARE)
-#define P_PPI0_CLK      (P_DONTCARE)
-
-#define P_MII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxD2, \
-        P_MII0_ETxD3, \
-        P_MII0_ETxEN, \
-        P_MII0_TxCLK, \
-        P_MII0_PHYINT, \
-        P_MII0_COL, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxD2, \
-        P_MII0_ERxD3, \
-        P_MII0_ERxDV, \
-        P_MII0_ERxCLK, \
-        P_MII0_ERxER, \
-        P_MII0_CRS, \
-        P_MDC, \
-        P_MDIO, 0}
-
-#define P_RMII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxEN, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxER, \
-        P_RMII0_REF_CLK, \
-        P_RMII0_MDINT, \
-        P_RMII0_CRS_DV, \
-        P_MDC, \
-        P_MDIO, 0}
-
-#endif                          /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
deleted file mode 100644
index 8f7ea112fd3a..000000000000
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf533/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning Serial Ports on with External Frame Syncs */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses When Stalled by Preceding Memory Read */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent Spurious Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (1)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (1)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (1)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (1)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (1)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-
-
-/* These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* Reserved bits in SYSCFG register not set at power on */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous exception when enabling cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL is not set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* The source MDMA descriptor may stop with a DMA Error */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT transmit data is not gated by external frame sync in certain conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* SDRAM auto-refresh and subsequent Power Ups */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB page miss can result in lost write-through cache data writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI resets the PPI configuration registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* PPI TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000323 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
deleted file mode 100644
index 12a416931991..000000000000
--- a/include/asm-blackfin/mach-bf533/bf533.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/bf533.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF533_H__
-#define __MACH_BF533_H__
-
-#define SUPPORTED_REVID 2
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR            0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_BIT                   0x0FFFFFFF
-#define UART_ERROR_BIT                  0xF0FFFFFF
-#define SPORT1_ERROR_BIT                0xFF0FFFFF
-#define SPI_ERROR_BIT                   0xFFF0FFFF
-#define SPORT0_ERROR_BIT                0xFFFF0FFF
-#define PPI_ERROR_BIT                   0xFFFFF0FF
-#define DMA_ERROR_BIT                   0xFFFFFF0F
-#define PLLWAKE_ERROR_BIT               0xFFFFFFFF
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_BIT                 0x0FFFFFFF
-#define DMA6_UARTRX_BIT                 0xF0FFFFFF
-#define DMA5_SPI_BIT                    0xFF0FFFFF
-#define DMA4_SPORT1TX_BIT               0xFFF0FFFF
-#define DMA3_SPORT1RX_BIT               0xFFFF0FFF
-#define DMA2_SPORT0TX_BIT               0xFFFFF0FF
-#define DMA1_SPORT0RX_BIT               0xFFFFFF0F
-#define DMA0_PPI_BIT                    0xFFFFFFFF
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_BIT                     0x0FFFFFFF
-#define MEMDMA1_BIT                     0xF0FFFFFF
-#define MEMDMA0_BIT                     0xFF0FFFFF
-#define PFB_BIT                         0xFFF0FFFF
-#define PFA_BIT                         0xFFFF0FFF
-#define TIMER2_BIT                      0xFFFFF0FF
-#define TIMER1_BIT                      0xFFFFFF0F
-#define TIMER0_BIT                      0xFFFFFFFF
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF533
-#define CPU "BF533"
-#define CPUID 0x027a5000
-#endif
-#ifdef CONFIG_BF532
-#define CPU "BF532"
-#define CPUID 0x0275A000
-#endif
-#ifdef CONFIG_BF531
-#define CPU "BF531"
-#define CPUID 0x027a5000
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF533_H__  */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
deleted file mode 100644
index ebf592b59aab..000000000000
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-# define CONFIG_SERIAL_BFIN_CTSRTS
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000230
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART_TX,
-        CH_UART_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        }
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-int nr_ports = BFIN_UART_NR_PORTS;
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/include/asm-blackfin/mach-bf533/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        CH_UART_RX,
-        CH_UART_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
deleted file mode 100644
index d80971b4e3aa..000000000000
--- a/include/asm-blackfin/mach-bf533/blackfin.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF533_FAMILY
-
-#include "bf533.h"
-#include "mem_map.h"
-#include "defBF532.h"
-#include "anomaly.h"
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF532.h"
-#endif
-
-#define BFIN_UART_NR_PORTS      1
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-#endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
deleted file mode 100644
index 154655452d4c..000000000000
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ /dev/null
@@ -1,767 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/cdefBF532.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-#include <asm/blackfin.h>
-
-/*include all Core registers and bit definitions*/
-#include "defBF532.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-#include <asm/system.h>
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define bfin_read_SWRST()                    bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
-#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
-#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
-
-/* DMA Traffic controls */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_MASKA_C()              bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val)          bfin_write16(FIO_MASKA_C,val)
-#define bfin_read_FIO_MASKA_S()              bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val)          bfin_write16(FIO_MASKA_S,val)
-#define bfin_read_FIO_MASKB_C()              bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val)          bfin_write16(FIO_MASKB_C,val)
-#define bfin_read_FIO_MASKB_S()              bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val)          bfin_write16(FIO_MASKB_S,val)
-#define bfin_read_FIO_POLAR()                bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val)            bfin_write16(FIO_POLAR,val)
-#define bfin_read_FIO_EDGE()                 bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val)             bfin_write16(FIO_EDGE,val)
-#define bfin_read_FIO_BOTH()                 bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val)             bfin_write16(FIO_BOTH,val)
-#define bfin_read_FIO_INEN()                 bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val)             bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_MASKA_D()              bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val)          bfin_write16(FIO_MASKA_D,val)
-#define bfin_read_FIO_MASKA_T()              bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val)          bfin_write16(FIO_MASKA_T,val)
-#define bfin_read_FIO_MASKB_D()              bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val)          bfin_write16(FIO_MASKB_D,val)
-#define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
-
-
-#if ANOMALY_05000311
-#define BFIN_WRITE_FIO_FLAG(name) \
-static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
-{\
-        unsigned long flags;\
-        local_irq_save(flags);\
-        bfin_write16(FIO_FLAG_ ## name,val);\
-        bfin_read_CHIPID();\
-        local_irq_restore(flags);\
-}
-BFIN_WRITE_FIO_FLAG(D)
-BFIN_WRITE_FIO_FLAG(C)
-BFIN_WRITE_FIO_FLAG(S)
-BFIN_WRITE_FIO_FLAG(T)
-
-#define BFIN_READ_FIO_FLAG(name) \
-static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
-{\
-        unsigned long flags;\
-        unsigned short ret;\
-        local_irq_save(flags);\
-        ret = bfin_read16(FIO_FLAG_ ## name);\
-        bfin_read_CHIPID();\
-        local_irq_restore(flags);\
-        return ret;\
-}
-BFIN_READ_FIO_FLAG(D)
-BFIN_READ_FIO_FLAG(C)
-BFIN_READ_FIO_FLAG(S)
-BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D,val)
-#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C,val)
-#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S,val)
-#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T,val)
-#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
-#endif
-
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)      bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()      bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)  bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG()              bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)          bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()       bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR()          bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT()             bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)         bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT()             bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)         bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY()            bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)        bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY()            bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)        bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR()       bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR()           bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT()        bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)    bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT()        bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)    bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS()          bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)      bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()      bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)  bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG()              bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)          bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()       bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR()          bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT()             bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)         bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT()             bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)         bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY()            bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)        bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY()            bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)        bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR()       bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR()           bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT()        bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)    bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT()        bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)    bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS()          bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)      bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()      bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)  bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG()           bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)       bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()    bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR()       bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT()          bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)      bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT()          bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)      bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY()         bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)     bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY()         bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)     bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()    bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR()        bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()     bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()     bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()       bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)   bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()   bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG()           bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)       bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()    bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR()       bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT()          bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)      bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT()          bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)      bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY()         bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)     bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY()         bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)     bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()    bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR()        bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()     bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()     bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()       bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)   bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()   bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG()           bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)       bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()    bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR()       bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT()          bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)      bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT()          bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)      bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY()         bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)     bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY()         bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)     bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()    bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR()        bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()     bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()     bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()       bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)   bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()   bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG()           bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)       bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()    bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR()       bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT()          bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)      bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT()          bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)      bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY()         bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)     bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY()         bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)     bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()    bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR()        bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()     bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()     bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()       bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)   bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()   bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
-#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)
-
-/* UART Controller */
-#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
-/*
-#define UART_MSR
-*/
-#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
-
-/* SPI Controller */
-#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
-
-/* TIMER 0, 1, 2 Registers */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE()             bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)         bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE()            bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)        bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS()             bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)         bfin_write16(TIMER_STATUS,val)
-
-/* SPORT0 Controller */
-#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller */
-#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
-
-/* Parallel Peripheral Interface (PPI) */
-#define bfin_read_PPI_CONTROL()              bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)          bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS()               bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)           bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS()              bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY()                bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)            bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT()                bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)            bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
-
-#endif                          /* _CDEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
deleted file mode 100644
index 0ab4dd7494cf..000000000000
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ /dev/null
@@ -1,1266 +0,0 @@
-/************************************************************************
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@analog.com
- *
- ************************************************************************/
-/*
- * File:         include/asm-blackfin/mach-bf533/defBF532.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/* include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
-#define PLL_DIV                  0xFFC00004     /* PLL Divide Register (16-bit) */
-#define VR_CTL                   0xFFC00008     /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
-#define CHIPID                 0xFFC00014       /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
-#define SYSCR                   0xFFC00104  /* System Configuration registe */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2 */
-#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register */
-#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART_*.
- */
-#define BFIN_UART_THR                   0xFFC00400      /* Transmit Holding register */
-#define BFIN_UART_RBR                   0xFFC00400      /* Receive Buffer register */
-#define BFIN_UART_DLL                   0xFFC00400      /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER                   0xFFC00404      /* Interrupt Enable Register */
-#define BFIN_UART_DLH                   0xFFC00404      /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR                   0xFFC00408      /* Interrupt Identification Register */
-#define BFIN_UART_LCR                   0xFFC0040C      /* Line Control Register */
-#define BFIN_UART_MCR                   0xFFC00410      /* Modem Control Register */
-#define BFIN_UART_LSR                   0xFFC00414      /* Line Status Register */
-#if 0
-#define BFIN_UART_MSR                   0xFFC00418      /* Modem Status Register (UNUSED in ADSP-BF532) */
-#endif
-#define BFIN_UART_SCR                   0xFFC0041C      /* SCR Scratch Register */
-#define BFIN_UART_GCTL                  0xFFC00424      /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-
-#define TIMER0_CONFIG                   0xFFC00600      /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                  0xFFC00604      /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                   0xFFC00608      /* Timer 0 Period Register */
-#define TIMER0_WIDTH                    0xFFC0060C      /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
-#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
-#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
-#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
-
-#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
-#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
-#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
-#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
-
-#define TIMER_ENABLE                    0xFFC00640      /* Timer Enable Register */
-#define TIMER_DISABLE                   0xFFC00644      /* Timer Disable Register */
-#define TIMER_STATUS                    0xFFC00648      /* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-
-#define FIO_FLAG_D                      0xFFC00700      /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C                      0xFFC00704      /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S                      0xFFC00708      /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T                      0xFFC0070C      /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D                     0xFFC00710      /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C                     0xFFC00714      /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S                     0xFFC00718      /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T                     0xFFC0071C      /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D                     0xFFC00720      /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C                     0xFFC00724      /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S                     0xFFC00728      /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T                     0xFFC0072C      /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR                         0xFFC00730      /* Peripheral Flag Direction Register */
-#define FIO_POLAR                       0xFFC00734      /* Flag Source Polarity Register */
-#define FIO_EDGE                        0xFFC00738      /* Flag Source Sensitivity Register */
-#define FIO_BOTH                        0xFFC0073C      /* Flag Set on BOTH Edges Register */
-#define FIO_INEN                                        0xFFC00740      /* Flag Input Enable Register  */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit  */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                    0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                    0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register */
-
-/* DMA Traffic controls */
-#define DMA_TC_PER 0xFFC00B0C   /* Traffic Control Periods Register */
-#define DMA_TC_CNT 0xFFC00B10   /* Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
-#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG             0xFFC00C08      /* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR      0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR         0xFFC00C04      /* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT            0xFFC00C10      /* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT            0xFFC00C18      /* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY           0xFFC00C14      /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY           0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR      0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR          0xFFC00C24      /* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT       0xFFC00C30      /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT       0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS         0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP     0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG             0xFFC00C48      /* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR      0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR         0xFFC00C44      /* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT            0xFFC00C50      /* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT            0xFFC00C58      /* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY           0xFFC00C54      /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY           0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR      0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR          0xFFC00C64      /* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT       0xFFC00C70      /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT       0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS         0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP     0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG             0xFFC00C88      /* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR      0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR         0xFFC00C84      /* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT            0xFFC00C90      /* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT            0xFFC00C98      /* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY           0xFFC00C94      /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY           0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR      0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR          0xFFC00CA4      /* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT       0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT       0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS         0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP     0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR      0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR         0xFFC00CC4      /* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT            0xFFC00CD0      /* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT            0xFFC00CD8      /* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY           0xFFC00CD4      /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY           0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR      0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR          0xFFC00CE4      /* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT       0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT       0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS         0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP     0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG             0xFFC00D08      /* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR      0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR         0xFFC00D04      /* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT            0xFFC00D10      /* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT            0xFFC00D18      /* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY           0xFFC00D14      /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY           0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR      0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR          0xFFC00D24      /* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT       0xFFC00D30      /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT       0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS         0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP     0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG             0xFFC00D48      /* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR      0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR         0xFFC00D44      /* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT            0xFFC00D50      /* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT            0xFFC00D58      /* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY           0xFFC00D54      /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY           0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR      0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR          0xFFC00D64      /* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT       0xFFC00D70      /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT       0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS         0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP     0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG             0xFFC00D88      /* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR      0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR         0xFFC00D84      /* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT            0xFFC00D90      /* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT            0xFFC00D98      /* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY           0xFFC00D94      /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY           0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR      0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR          0xFFC00DA4      /* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT       0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT       0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS         0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP     0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR      0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR         0xFFC00DC4      /* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT            0xFFC00DD0      /* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT            0xFFC00DD8      /* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY           0xFFC00DD4      /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY           0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR      0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR          0xFFC00DE4      /* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT       0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT       0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS         0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP     0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG          0xFFC00E88      /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00E80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR      0xFFC00E84      /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT         0xFFC00E90      /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT         0xFFC00E98      /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY        0xFFC00E94      /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY        0xFFC00E9C      /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00EA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR       0xFFC00EA4      /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00EB0      /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00EB8      /* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS      0xFFC00EA8      /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00EAC      /* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG          0xFFC00EC8      /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00EC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR      0xFFC00EC4      /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT         0xFFC00ED0      /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT         0xFFC00ED8      /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY        0xFFC00ED4      /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY        0xFFC00EDC      /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00EE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR       0xFFC00EE4      /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00EF0      /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00EF8      /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS      0xFFC00EE8      /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00EEC      /* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG          0xFFC00E08      /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00E00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR      0xFFC00E04      /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT         0xFFC00E10      /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT         0xFFC00E18      /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY        0xFFC00E14      /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY        0xFFC00E1C      /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00E20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR       0xFFC00E24      /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00E30      /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00E38      /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS      0xFFC00E28      /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00E2C      /* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG          0xFFC00E48      /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00E40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR      0xFFC00E44      /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT         0xFFC00E50      /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT         0xFFC00E58      /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY        0xFFC00E54      /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY        0xFFC00E5C      /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00E60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR       0xFFC00E64      /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00E70      /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00E78      /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS      0xFFC00E68      /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00E6C      /* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2                  0x0001  /* Pass CLKIN/2 to PLL */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
-#define STOPCK_OFF                      0x0008  /* Core clock off */
-#define STOPCK                          0x0008  /* Core Clock Off                                                                       */
-#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
-#if !defined(__ADSPBF538__)
-/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
-# define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS                          0x0100  /* Bypass the PLL */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks */
-#define SSEL                            0x000F  /* System Select                                                */
-#define CSEL                            0x0030  /* Core Select                                                  */
-
-#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
-
-#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Mask */
-#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-    /* SIC_IAR0 Masks */
-
-#define P0_IVG(x)    ((x)-7)    /* Peripheral #0 assigned IVG #x  */
-#define P1_IVG(x)    ((x)-7) << 0x4     /* Peripheral #1 assigned IVG #x  */
-#define P2_IVG(x)    ((x)-7) << 0x8     /* Peripheral #2 assigned IVG #x  */
-#define P3_IVG(x)    ((x)-7) << 0xC     /* Peripheral #3 assigned IVG #x  */
-#define P4_IVG(x)    ((x)-7) << 0x10    /* Peripheral #4 assigned IVG #x  */
-#define P5_IVG(x)    ((x)-7) << 0x14    /* Peripheral #5 assigned IVG #x  */
-#define P6_IVG(x)    ((x)-7) << 0x18    /* Peripheral #6 assigned IVG #x  */
-#define P7_IVG(x)    ((x)-7) << 0x1C    /* Peripheral #7 assigned IVG #x  */
-
-/* SIC_IAR1 Masks */
-
-#define P8_IVG(x)     ((x)-7)   /* Peripheral #8 assigned IVG #x  */
-#define P9_IVG(x)     ((x)-7) << 0x4    /* Peripheral #9 assigned IVG #x  */
-#define P10_IVG(x)    ((x)-7) << 0x8    /* Peripheral #10 assigned IVG #x  */
-#define P11_IVG(x)    ((x)-7) << 0xC    /* Peripheral #11 assigned IVG #x  */
-#define P12_IVG(x)    ((x)-7) << 0x10   /* Peripheral #12 assigned IVG #x  */
-#define P13_IVG(x)    ((x)-7) << 0x14   /* Peripheral #13 assigned IVG #x  */
-#define P14_IVG(x)    ((x)-7) << 0x18   /* Peripheral #14 assigned IVG #x  */
-#define P15_IVG(x)    ((x)-7) << 0x1C   /* Peripheral #15 assigned IVG #x  */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x)    ((x)-7)   /* Peripheral #16 assigned IVG #x  */
-#define P17_IVG(x)    ((x)-7) << 0x4    /* Peripheral #17 assigned IVG #x  */
-#define P18_IVG(x)    ((x)-7) << 0x8    /* Peripheral #18 assigned IVG #x  */
-#define P19_IVG(x)    ((x)-7) << 0xC    /* Peripheral #19 assigned IVG #x  */
-#define P20_IVG(x)    ((x)-7) << 0x10   /* Peripheral #20 assigned IVG #x  */
-#define P21_IVG(x)    ((x)-7) << 0x14   /* Peripheral #21 assigned IVG #x  */
-#define P22_IVG(x)    ((x)-7) << 0x18   /* Peripheral #22 assigned IVG #x  */
-#define P23_IVG(x)    ((x)-7) << 0x1C   /* Peripheral #23 assigned IVG #x  */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
-#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001         /* TX enable  */
-#define ITCLK    0x0002         /* Internal TX Clock Select  */
-#define TDTYPE   0x000C         /* TX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT   0x0010         /* TX Bit Order */
-#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400         /* TX Frame Sync Required Select  */
-#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000         /* Low TX Frame Sync Select  */
-#define LATFS    0x2000         /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
-    defined(__ADSPBF533__)
-# define SLEN       0x001F      /*TX Word Length  */
-#else
-# define SLEN(x)                ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#endif
-#define TXSE        0x0100      /*TX Secondary Enable */
-#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400      /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001         /* RX enable  */
-#define IRCLK    0x0002         /* Internal RX Clock Select  */
-#define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* no companding                                                        */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT   0x0010         /* RX Bit Order */
-#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400         /* RX Frame Sync Required Select  */
-#define LRFS     0x1000         /* Low RX Frame Sync Select  */
-#define LARFS    0x2000         /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE        0x0100      /*RX Secondary Enable */
-#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400      /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001  /*RX FIFO Not Empty Status */
-#define RUVF            0x0002  /*RX Underflow Status */
-#define ROVF            0x0004  /*RX Overflow Status */
-#define TXF             0x0008  /*TX FIFO Full Status */
-#define TUVF            0x0010  /*TX Underflow Status */
-#define TOVF            0x0020  /*TX Overflow Status */
-#define TXHRE           0x0040  /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
-#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SET_SP_WOFF(x)  ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits                                                */
-#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-
-/*  PPI_CONTROL Masks         */
-#define PORT_EN              0x00000001 /* PPI Port Enable  */
-#define PORT_DIR             0x00000002 /* PPI Port Direction       */
-#define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
-#define PORT_CFG             0x00000030 /* PPI Port Configuration */
-#define FLD_SEL              0x00000040 /* PPI Active Field Select */
-#define PACK_EN              0x00000080 /* PPI Packing Mode */
-#define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH              0x00003800 /* PPI Data Length  */
-#define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
-#define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#define POL                  0x0000C000 /* PPI Signal Polarities       */
-#define POLC            0x4000          /* PPI Clock Polarity                           */
-#define POLS            0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                          */
-#define FLD                  0x00000400 /* Field Indicator   */
-#define FT_ERR               0x00000800 /* Frame Track Error */
-#define OVR                  0x00001000 /* FIFO Overflow Error */
-#define UNDR                 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET              0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
-
-/* **********  DMA CONTROLLER MASKS  *********************8 */
-
-/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN           0x00000001      /* Channel Enable */
-#define WNR             0x00000002      /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
-#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
-#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
-#define DMA2D           0x00000010      /* 2D/1D* Mode */
-#define RESTART         0x00000020      /* Restart */
-#define DI_SEL          0x00000040      /* Data Interrupt Select */
-#define DI_EN           0x00000080      /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE          0x00000900      /* Next Descriptor Size */
-#define DMAFLOW         0x00007000      /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P                 0       /* Channel Enable */
-#define WNR_P                   1       /* Channel Direction (W/R*) */
-#define DMA2D_P                 4       /* 2D/1D* Mode */
-#define RESTART_P               5       /* Restart */
-#define DI_SEL_P                6       /* Data Interrupt Select */
-#define DI_EN_P                 7       /* Data Interrupt Enable */
-
-/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE                0x00000001      /* DMA Done Indicator */
-#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
-#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
-#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
-
-#define DMA_DONE_P              0       /* DMA Done Indicator */
-#define DMA_ERR_P               1       /* DMA Error Indicator */
-#define DFETCH_P                2       /* Descriptor Fetch Indicator */
-#define DMA_RUN_P               3       /* DMA Running Indicator */
-
-/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE               0x00000040  /* DMA Channel Type Indicator */
-#define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
-#define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
-#define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
-#define PMAP                0x00007000  /* DMA Peripheral Map Field */
-
-#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX           0x1000  /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX           0x2000  /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX           0x3000  /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX           0x4000  /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI                0x5000  /* PMAP SPI DMA */
-#define PMAP_UARTRX             0x6000  /* PMAP UART Receive DMA */
-#define PMAP_UARTTX             0x7000  /* PMAP UART Transmit DMA */
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0  0x0001
-#define TIMEN1  0x0002
-#define TIMEN2  0x0004
-
-#define TIMEN0_P        0x00
-#define TIMEN1_P        0x01
-#define TIMEN2_P        0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-
-#define TIMDIS0_P       0x00
-#define TIMDIS1_P       0x01
-#define TIMDIS2_P       0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0          0x0001
-#define TIMIL1          0x0002
-#define TIMIL2          0x0004
-#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow             */
-#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow             */
-#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow             */
-#define TRUN0           0x1000
-#define TRUN1           0x2000
-#define TRUN2           0x4000
-
-#define TIMIL0_P        0x00
-#define TIMIL1_P        0x01
-#define TIMIL2_P        0x02
-#define TOVF_ERR0_P             0x04
-#define TOVF_ERR1_P             0x05
-#define TOVF_ERR2_P             0x06
-#define TRUN0_P         0x0C
-#define TRUN1_P         0x0D
-#define TRUN2_P         0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0               TOVF_ERR0
-#define TOVL_ERR1               TOVF_ERR1
-#define TOVL_ERR2               TOVF_ERR2
-#define TOVL_ERR0_P             TOVF_ERR0_P
-#define TOVL_ERR1_P             TOVF_ERR1_P
-#define TOVL_ERR2_P             TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT         0x0001
-#define WDTH_CAP        0x0002
-#define EXT_CLK         0x0003
-#define PULSE_HI        0x0004
-#define PERIOD_CNT      0x0008
-#define IRQ_ENA         0x0010
-#define TIN_SEL         0x0020
-#define OUT_DIS         0x0040
-#define CLK_SEL         0x0080
-#define TOGGLE_HI       0x0100
-#define EMU_RUN         0x0200
-#define ERR_TYP(x)      ((x & 0x03) << 14)
-
-#define TMODE_P0                0x00
-#define TMODE_P1                0x01
-#define PULSE_HI_P              0x02
-#define PERIOD_CNT_P            0x03
-#define IRQ_ENA_P               0x04
-#define TIN_SEL_P               0x05
-#define OUT_DIS_P               0x06
-#define CLK_SEL_P               0x07
-#define TOGGLE_HI_P             0x08
-#define EMU_RUN_P               0x09
-#define ERR_TYP_P0              0x0E
-#define ERR_TYP_P1              0x0F
-
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-
-/* SPI_CTL Masks */
-#define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
-#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
-#define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
-#define SIZE                   0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR                   0x00001000       /* Configures SPI as master (=1) or slave (=0) */
-#define WOM                    0x00002000       /* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE                    0x00004000       /* SPI module enable (=1), disable (=0) */
-
-/* SPI_FLG Masks */
-#define FLS1                   0x00000002       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2                   0x00000004       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3                   0x00000008       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4                   0x00000010       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5                   0x00000020       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6                   0x00000040       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7                   0x00000080       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1                   0x00000200       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2                   0x00000400       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3                   0x00000800       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4                   0x00001000       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5                   0x00002000       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6                   0x00004000       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7                   0x00008000       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P                 0x00000001       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P                 0x00000002       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P                 0x00000003       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P                 0x00000004       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P                 0x00000005       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P                 0x00000006       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P                 0x00000007       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P                 0x00000009       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P                 0x0000000A       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P                 0x0000000B       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P                 0x0000000C       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P                 0x0000000D       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P                 0x0000000E       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P                 0x0000000F       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF                   0x00000001       /* Set (=1) when SPI single-word transfer complete */
-#define MODF                   0x00000002       /* Set (=1) in a master device when some other device tries to become master */
-#define TXE                    0x00000004       /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS                    0x00000008       /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY                   0x00000010       /* Set (=1) when data is received with RDBR full */
-#define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
-
-/* SPIx_FLG Masks                                                                                                                                       */
-#define FLG1E   0xFDFF          /* Activates SPI_FLOUT1                                                         */
-#define FLG2E   0xFBFF          /* Activates SPI_FLOUT2                                                         */
-#define FLG3E   0xF7FF          /* Activates SPI_FLOUT3                                                         */
-#define FLG4E   0xEFFF          /* Activates SPI_FLOUT4                                                         */
-#define FLG5E   0xDFFF          /* Activates SPI_FLOUT5                                                         */
-#define FLG6E   0xBFFF          /* Activates SPI_FLOUT6                                                         */
-#define FLG7E   0x7FFF          /* Activates SPI_FLOUT7                                                         */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN                  0x00000001      /* Enable CLKOUT */
-#define AMBEN_NONE              0x00000000      /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x00000002      /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1             0x00000004      /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2          0x00000006      /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL               0x00000008      /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P                0x00000000      /* Enable CLKOUT */
-#define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-
-/* SDGCTL Masks */
-#define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
-#define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
-#define PFE                     0x00000010      /* Enable SDRAM prefetch */
-#define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
-#define PUPSD                   0x00200000      /*Power-up start delay */
-#define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
-#define EBUFE                   0x02000000      /* Enable external buffering timing */
-#define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
-#define EMREN                   0x10000000      /* Extended mode register enable */
-#define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
-#define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE                     0x00000001      /* Enable SDRAM external bank */
-#define EBSZ_16                 0x00000000      /* SDRAM external bank size = 16MB */
-#define EBSZ_32                 0x00000002      /* SDRAM external bank size = 32MB */
-#define EBSZ_64                 0x00000004      /* SDRAM external bank size = 64MB */
-#define EBSZ_128                        0x00000006      /* SDRAM external bank size = 128MB */
-#define EBCAW_8                 0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9                 0x00000010      /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10                        0x00000020      /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11                        0x00000030      /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI                    0x00000001      /* SDRAM controller is idle  */
-#define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
-#define SDPUA                   0x00000004      /* SDRAM power up active  */
-#define SDRS                    0x00000008      /* SDRAM is in reset state */
-#define SDEASE                0x00000010        /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT                  0x00000020      /* Bus granted */
-
-
-#endif                          /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
deleted file mode 100644
index bd9d5e94307d..000000000000
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*****************************************************************************
-*
-*        BF-533/2/1 Specific Declarations
-*
-****************************************************************************/
-/*
- * File:         include/asm-blackfin/mach-bf533/dma.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 12
-
-#define CH_PPI          0
-#define CH_SPORT0_RX    1
-#define CH_SPORT0_TX    2
-#define CH_SPORT1_RX    3
-#define CH_SPORT1_TX    4
-#define CH_SPI          5
-#define CH_UART_RX      6
-#define CH_UART_TX      7
-#define CH_MEM_STREAM0_DEST     8        /* TX */
-#define CH_MEM_STREAM0_SRC      9        /* RX */
-#define CH_MEM_STREAM1_DEST     10       /* TX */
-#define CH_MEM_STREAM1_SRC      11       /* RX */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
deleted file mode 100644
index 5aa38e5da6b7..000000000000
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/defBF532.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BF533_IRQ_H_
-#define _BF533_IRQ_H_
-
-/*
- * Interrupt source definitions
-             Event Source    Core Event Name
-Core        Emulation               **
- Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-            PLL Wakeup Interrupt    IVG7        7
-            DMA Error (generic)     IVG7        8
-            PPI Error Interrupt     IVG7        9
-            SPORT0 Error Interrupt  IVG7        10
-            SPORT1 Error Interrupt  IVG7        11
-            SPI Error Interrupt     IVG7        12
-            UART Error Interrupt    IVG7        13
-            RTC Interrupt           IVG8        14
-            DMA0 Interrupt (PPI)    IVG8        15
-            DMA1 (SPORT0 RX)        IVG9        16
-            DMA2 (SPORT0 TX)        IVG9        17
-            DMA3 (SPORT1 RX)        IVG9        18
-            DMA4 (SPORT1 TX)        IVG9        19
-            DMA5 (PPI)              IVG10       20
-            DMA6 (UART RX)          IVG10       21
-            DMA7 (UART TX)          IVG10       22
-            Timer0                  IVG11       23
-            Timer1                  IVG11       24
-            Timer2                  IVG11       25
-            PF Interrupt A          IVG12       26
-            PF Interrupt B          IVG12       27
-            DMA8/9 Interrupt        IVG13       28
-            DMA10/11 Interrupt      IVG13       29
-            Watchdog Timer          IVG13       30
-
-            Softirq                 IVG14       31
-            System Call    --
-                 (lowest priority)  IVG15       32 *
- */
-#define SYS_IRQS        31
-#define NR_PERI_INTS    24
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /*Emulation */
-#define IRQ_RST                 1       /*reset */
-#define IRQ_NMI                 2       /*Non Maskable */
-#define IRQ_EVX                 3       /*Exception */
-#define IRQ_UNUSED              4       /*- unused interrupt*/
-#define IRQ_HWERR               5       /*Hardware Error */
-#define IRQ_CORETMR             6       /*Core timer */
-
-#define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR           8       /*DMA Error (general) */
-#define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
-#define IRQ_UART_ERROR          13      /*UART Error Interrupt */
-#define IRQ_RTC                 14      /*RTC Interrupt */
-#define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
-#define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
-#define IRQ_TMR0                23      /*Timer 0 */
-#define IRQ_TMR1                24      /*Timer 1 */
-#define IRQ_TMR2                25      /*Timer 2 */
-#define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
-#define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
-#define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH               30      /*Watch Dog Timer */
-
-#define IRQ_PF0                 33
-#define IRQ_PF1                 34
-#define IRQ_PF2                 35
-#define IRQ_PF3                 36
-#define IRQ_PF4                 37
-#define IRQ_PF5                 38
-#define IRQ_PF6                 39
-#define IRQ_PF7                 40
-#define IRQ_PF8                 41
-#define IRQ_PF9                 42
-#define IRQ_PF10                43
-#define IRQ_PF11                44
-#define IRQ_PF12                45
-#define IRQ_PF13                46
-#define IRQ_PF14                47
-#define IRQ_PF15                48
-
-#define GPIO_IRQ_BASE           IRQ_PF0
-
-#define NR_IRQS         (IRQ_PF15+1)
-
-#define IVG7                    7
-#define IVG8                    8
-#define IVG9                    9
-#define IVG10                   10
-#define IVG11                   11
-#define IVG12                   12
-#define IVG13                   13
-#define IVG14                   14
-#define IVG15                   15
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_POS                   28
-#define UART_ERROR_POS                  24
-#define SPORT1_ERROR_POS                20
-#define SPI_ERROR_POS                   16
-#define SPORT0_ERROR_POS                12
-#define PPI_ERROR_POS                   8
-#define DMA_ERROR_POS                   4
-#define PLLWAKE_ERROR_POS               0
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_POS                 28
-#define DMA6_UARTRX_POS                 24
-#define DMA5_SPI_POS                    20
-#define DMA4_SPORT1TX_POS               16
-#define DMA3_SPORT1RX_POS               12
-#define DMA2_SPORT0TX_POS               8
-#define DMA1_SPORT0RX_POS               4
-#define DMA0_PPI_POS                    0
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_POS                     28
-#define MEMDMA1_POS                     24
-#define MEMDMA0_POS                     20
-#define PFB_POS                         16
-#define PFA_POS                         12
-#define TIMER2_POS                      8
-#define TIMER1_POS                      4
-#define TIMER0_POS                      0
-
-#endif                          /* _BF533_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
deleted file mode 100644
index 995c06b2b1ef..000000000000
--- a/include/asm-blackfin/mach-bf533/mem_init.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
-     CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 8955223) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
deleted file mode 100644
index bd30b6f3be00..000000000000
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/mem_map.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MEM_MAP_533_H_
-#define _MEM_MAP_533_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF533 processors */
-
-#ifdef CONFIG_BF533
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH      (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH      0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF532 processors */
-
-#ifdef CONFIG_BF532
-#define L1_CODE_START       0xFFA08000
-#define L1_DATA_A_START     0xFF804000
-#define L1_DATA_B_START     0xFF904000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH      (0xC000 - 0x4000)
-#else
-#define L1_CODE_LENGTH      0xC000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x4000
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF531 processors */
-
-#ifdef CONFIG_BF531
-#define L1_CODE_START       0xFFA08000
-#define L1_DATA_A_START     0xFF804000
-#define L1_DATA_B_START     0xFF904000
-#define L1_CODE_LENGTH      0x4000
-#define L1_DATA_B_LENGTH      0x0000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB  | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB  | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif
-
-#endif
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
deleted file mode 100644
index 685a2651dcda..000000000000
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK      (P_DONTCARE)
-#define P_PPI0_FS1      (P_DONTCARE)
-#define P_PPI0_FS2      (P_DONTCARE)
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0       (P_DONTCARE)
-#define P_PPI0_D1       (P_DONTCARE)
-#define P_PPI0_D2       (P_DONTCARE)
-#define P_PPI0_D3       (P_DONTCARE)
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK  (P_DONTCARE)
-#define P_SPORT1_RSCLK  (P_DONTCARE)
-#define P_SPORT0_TSCLK  (P_DONTCARE)
-#define P_SPORT0_RSCLK  (P_DONTCARE)
-#define P_UART0_RX      (P_DONTCARE)
-#define P_UART0_TX      (P_DONTCARE)
-#define P_SPORT1_DRSEC  (P_DONTCARE)
-#define P_SPORT1_RFS    (P_DONTCARE)
-#define P_SPORT1_DTPRI  (P_DONTCARE)
-#define P_SPORT1_DTSEC  (P_DONTCARE)
-#define P_SPORT1_TFS    (P_DONTCARE)
-#define P_SPORT1_DRPRI  (P_DONTCARE)
-#define P_SPORT0_DRSEC  (P_DONTCARE)
-#define P_SPORT0_RFS    (P_DONTCARE)
-#define P_SPORT0_DTPRI  (P_DONTCARE)
-#define P_SPORT0_DTSEC  (P_DONTCARE)
-#define P_SPORT0_TFS    (P_DONTCARE)
-#define P_SPORT0_DRPRI  (P_DONTCARE)
-
-#define P_SPI0_MOSI     (P_DONTCARE)
-#define P_SPI0_MISO     (P_DONTCARE)
-#define P_SPI0_SCK      (P_DONTCARE)
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
-
-#define P_TMR2          (P_DONTCARE)
-#define P_TMR1          (P_DONTCARE)
-#define P_TMR0          (P_DONTCARE)
-#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF1))
-
-
-
-
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
deleted file mode 100644
index 8460ab9c324f..000000000000
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf537/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H cannot be used to access 16-bit System MMR registers */
-#define ANOMALY_05000122 (1)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
-#define ANOMALY_05000180 (1)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* Spurious Hardware Error from an access in the shadow of a conditional branch */
-#define ANOMALY_05000245 (1)
-/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
-#define ANOMALY_05000247 (1)
-/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC Tx DMA error after an early frame abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum external clock speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO input latched on wrong MDC edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR register may be corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR register may be corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores to data cache may be lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware loop corrupted when taking an ICPLB exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain data cache write through modes fail for VDDint <=0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM memory may be lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA running may cause DMA system instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master boot mode does not work well with Atmel Data flash devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error Exception when ISR context is not restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA corruption with 32-bit data and traffic control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs may receive bad data if FIFOs fill up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory to memory DMA source/destination descriptors must be in same memory space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False hardware errors caused by fetches at the boundary of reserved memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI is level sensitive on first transfer */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode: collisions occur in Full Duplex mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* New Feature: UART Remains Enabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
deleted file mode 100644
index cfe2a221112e..000000000000
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/bf537.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF537_H__
-#define __MACH_BF537_H__
-
-#define SUPPORTED_REVID 2
-
-/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
-
-#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE)        /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORTx_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD)    /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)   /* EMAC_SYSTAT */
-#define UART_ERR_MASK_STAT1 (0x4)       /* UARTx_IIR */
-#define UART_ERR_MASK_STAT0 (0x2)       /* UARTx_IIR */
-#define CAN_ERR_MASK  (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)        /* CAN_GIF */
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR    0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF537
-#define CPU "BF537"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF536
-#define CPU "BF536"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF534
-#define CPU "BF534"
-#define CPUID 0x027c6000
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF537_H__  */
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
deleted file mode 100644
index 1bf56ffa22f9..000000000000
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver header files
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int     uart_cts_pin;
-        int     uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-        CONFIG_UART1_CTS_PIN,
-        CONFIG_UART1_RTS_PIN,
-#endif
-        },
-#endif
-};
-
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
-#define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
deleted file mode 100644
index cfd8ad4f1f2c..000000000000
--- a/include/asm-blackfin/mach-bf537/bfin_sir.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
deleted file mode 100644
index cffc786b2a2b..000000000000
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF537_FAMILY
-
-#include "bf537.h"
-#include "mem_map.h"
-#include "defBF534.h"
-#include "anomaly.h"
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "defBF537.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF534.h"
-
-/* UART 0*/
-#define bfin_read_UART_THR() bfin_read_UART0_THR()
-#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
-#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
-#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
-#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
-#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
-#define bfin_read_UART_IER() bfin_read_UART0_IER()
-#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
-#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
-#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
-#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
-#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
-#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
-#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
-#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
-#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
-#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
-#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
-#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
-#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
-#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
-#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "cdefBF537.h"
-#endif
-#endif
-
-/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-/* DMA Channnel */
-#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
-#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
-#define CH_UART_RX CH_UART0_RX
-#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
-#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
-#define CH_UART_TX CH_UART0_TX
-
-/* System Interrupt Controller */
-#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
-#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
-#define IRQ_UART_RX IRQ_UART0_RX
-#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
-#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
-#define IRQ_UART_TX IRQ_UART0_TX
-#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
-#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
-#define IRQ_UART_ERROR IRQ_UART0_ERROR
-
-/* MMR Registers*/
-#define bfin_read_UART_THR() bfin_read_UART0_THR()
-#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
-#define BFIN_UART_THR UART0_THR
-#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
-#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
-#define BFIN_UART_RBR UART0_RBR
-#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
-#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
-#define BFIN_UART_DLL UART0_DLL
-#define bfin_read_UART_IER() bfin_read_UART0_IER()
-#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
-#define BFIN_UART_IER UART0_IER
-#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
-#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
-#define BFIN_UART_DLH UART0_DLH
-#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
-#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
-#define BFIN_UART_IIR UART0_IIR
-#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
-#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
-#define BFIN_UART_LCR UART0_LCR
-#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
-#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
-#define BFIN_UART_MCR UART0_MCR
-#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
-#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
-#define BFIN_UART_LSR UART0_LSR
-#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
-#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
-#define BFIN_UART_SCR  UART0_SCR
-#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
-#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
-#define BFIN_UART_GCTL UART0_GCTL
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-/* DPMC*/
-#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
-#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
-#define STOPCK_OFF STOPCK
-
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
deleted file mode 100644
index 82de526f8097..000000000000
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ /dev/null
@@ -1,1819 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/cdefbf534.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-#include <asm/blackfin.h>
-
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF534.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-#include <asm/system.h>
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                    bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
-#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT()                bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)            bfin_write32(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)            bfin_write16(UART0_THR,val)
-#define bfin_read_UART0_RBR()                bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)            bfin_write16(UART0_RBR,val)
-#define bfin_read_UART0_DLL()                bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)            bfin_write16(UART0_DLL,val)
-#define bfin_read_UART0_IER()                bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)            bfin_write16(UART0_IER,val)
-#define bfin_read_UART0_DLH()                bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)            bfin_write16(UART0_DLH,val)
-#define bfin_read_UART0_IIR()                bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)            bfin_write16(UART0_IIR,val)
-#define bfin_read_UART0_LCR()                bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)            bfin_write16(UART0_LCR,val)
-#define bfin_read_UART0_MCR()                bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)            bfin_write16(UART0_MCR,val)
-#define bfin_read_UART0_LSR()                bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)            bfin_write16(UART0_LSR,val)
-#define bfin_read_UART0_MSR()                bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)            bfin_write16(UART0_MSR,val)
-#define bfin_read_UART0_SCR()                bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)            bfin_write16(UART0_SCR,val)
-#define bfin_read_UART0_GCTL()               bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)           bfin_write16(UART0_GCTL,val)
-
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
-
-#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
-
-#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
-
-#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
-
-#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE()             bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)         bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE()            bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)        bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS()             bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)         bfin_write32(TIMER_STATUS,val)
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                  bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)              bfin_write16(PORTFIO,val)
-#define bfin_read_PORTFIO_CLEAR()            bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)        bfin_write16(PORTFIO_CLEAR,val)
-#define bfin_read_PORTFIO_SET()              bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)          bfin_write16(PORTFIO_SET,val)
-#define bfin_read_PORTFIO_TOGGLE()           bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)       bfin_write16(PORTFIO_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKA()            bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)        bfin_write16(PORTFIO_MASKA,val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()      bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)  bfin_write16(PORTFIO_MASKA_CLEAR,val)
-#define bfin_read_PORTFIO_MASKA_SET()        bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)    bfin_write16(PORTFIO_MASKA_SET,val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()     bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKB()            bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)        bfin_write16(PORTFIO_MASKB,val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()      bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)  bfin_write16(PORTFIO_MASKB_CLEAR,val)
-#define bfin_read_PORTFIO_MASKB_SET()        bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)    bfin_write16(PORTFIO_MASKB_SET,val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()     bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTFIO_DIR()              bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)          bfin_write16(PORTFIO_DIR,val)
-#define bfin_read_PORTFIO_POLAR()            bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)        bfin_write16(PORTFIO_POLAR,val)
-#define bfin_read_PORTFIO_EDGE()             bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)         bfin_write16(PORTFIO_EDGE,val)
-#define bfin_read_PORTFIO_BOTH()             bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)         bfin_write16(PORTFIO_BOTH,val)
-#define bfin_read_PORTFIO_INEN()             bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)         bfin_write16(PORTFIO_INEN,val)
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
-#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)      bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()      bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)  bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG()              bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)          bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()       bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR()          bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT()             bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)         bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT()             bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)         bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY()            bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)        bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY()            bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)        bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR()       bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR()           bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT()        bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)    bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT()        bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)    bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS()          bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)      bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()      bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)  bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG()              bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)          bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()       bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR()          bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT()             bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)         bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT()             bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)         bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY()            bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)        bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY()            bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)        bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR()       bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR()           bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT()        bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)    bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT()        bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)    bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS()          bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)      bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()      bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)  bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA8_CONFIG()              bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)          bfin_write16(DMA8_CONFIG,val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()       bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)   bfin_write32(DMA8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA8_START_ADDR()          bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)      bfin_write32(DMA8_START_ADDR,val)
-#define bfin_read_DMA8_X_COUNT()             bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)         bfin_write16(DMA8_X_COUNT,val)
-#define bfin_read_DMA8_Y_COUNT()             bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)         bfin_write16(DMA8_Y_COUNT,val)
-#define bfin_read_DMA8_X_MODIFY()            bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)        bfin_write16(DMA8_X_MODIFY,val)
-#define bfin_read_DMA8_Y_MODIFY()            bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)        bfin_write16(DMA8_Y_MODIFY,val)
-#define bfin_read_DMA8_CURR_DESC_PTR()       bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)   bfin_write32(DMA8_CURR_DESC_PTR,val)
-#define bfin_read_DMA8_CURR_ADDR()           bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)       bfin_write32(DMA8_CURR_ADDR,val)
-#define bfin_read_DMA8_CURR_X_COUNT()        bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)    bfin_write16(DMA8_CURR_X_COUNT,val)
-#define bfin_read_DMA8_CURR_Y_COUNT()        bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)    bfin_write16(DMA8_CURR_Y_COUNT,val)
-#define bfin_read_DMA8_IRQ_STATUS()          bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)      bfin_write16(DMA8_IRQ_STATUS,val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()      bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)  bfin_write16(DMA8_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA9_CONFIG()              bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)          bfin_write16(DMA9_CONFIG,val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()       bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)   bfin_write32(DMA9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA9_START_ADDR()          bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)      bfin_write32(DMA9_START_ADDR,val)
-#define bfin_read_DMA9_X_COUNT()             bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)         bfin_write16(DMA9_X_COUNT,val)
-#define bfin_read_DMA9_Y_COUNT()             bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)         bfin_write16(DMA9_Y_COUNT,val)
-#define bfin_read_DMA9_X_MODIFY()            bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)        bfin_write16(DMA9_X_MODIFY,val)
-#define bfin_read_DMA9_Y_MODIFY()            bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)        bfin_write16(DMA9_Y_MODIFY,val)
-#define bfin_read_DMA9_CURR_DESC_PTR()       bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)   bfin_write32(DMA9_CURR_DESC_PTR,val)
-#define bfin_read_DMA9_CURR_ADDR()           bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)       bfin_write32(DMA9_CURR_ADDR,val)
-#define bfin_read_DMA9_CURR_X_COUNT()        bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)    bfin_write16(DMA9_CURR_X_COUNT,val)
-#define bfin_read_DMA9_CURR_Y_COUNT()        bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)    bfin_write16(DMA9_CURR_Y_COUNT,val)
-#define bfin_read_DMA9_IRQ_STATUS()          bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)      bfin_write16(DMA9_IRQ_STATUS,val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()      bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)  bfin_write16(DMA9_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA10_CONFIG()             bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)         bfin_write16(DMA10_CONFIG,val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()      bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)  bfin_write32(DMA10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA10_START_ADDR()         bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)     bfin_write32(DMA10_START_ADDR,val)
-#define bfin_read_DMA10_X_COUNT()            bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)        bfin_write16(DMA10_X_COUNT,val)
-#define bfin_read_DMA10_Y_COUNT()            bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)        bfin_write16(DMA10_Y_COUNT,val)
-#define bfin_read_DMA10_X_MODIFY()           bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)       bfin_write16(DMA10_X_MODIFY,val)
-#define bfin_read_DMA10_Y_MODIFY()           bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)       bfin_write16(DMA10_Y_MODIFY,val)
-#define bfin_read_DMA10_CURR_DESC_PTR()      bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)  bfin_write32(DMA10_CURR_DESC_PTR,val)
-#define bfin_read_DMA10_CURR_ADDR()          bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)      bfin_write32(DMA10_CURR_ADDR,val)
-#define bfin_read_DMA10_CURR_X_COUNT()       bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)   bfin_write16(DMA10_CURR_X_COUNT,val)
-#define bfin_read_DMA10_CURR_Y_COUNT()       bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)   bfin_write16(DMA10_CURR_Y_COUNT,val)
-#define bfin_read_DMA10_IRQ_STATUS()         bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)     bfin_write16(DMA10_IRQ_STATUS,val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()     bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA11_CONFIG()             bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)         bfin_write16(DMA11_CONFIG,val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()      bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)  bfin_write32(DMA11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA11_START_ADDR()         bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)     bfin_write32(DMA11_START_ADDR,val)
-#define bfin_read_DMA11_X_COUNT()            bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)        bfin_write16(DMA11_X_COUNT,val)
-#define bfin_read_DMA11_Y_COUNT()            bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)        bfin_write16(DMA11_Y_COUNT,val)
-#define bfin_read_DMA11_X_MODIFY()           bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)       bfin_write16(DMA11_X_MODIFY,val)
-#define bfin_read_DMA11_Y_MODIFY()           bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)       bfin_write16(DMA11_Y_MODIFY,val)
-#define bfin_read_DMA11_CURR_DESC_PTR()      bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)  bfin_write32(DMA11_CURR_DESC_PTR,val)
-#define bfin_read_DMA11_CURR_ADDR()          bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)      bfin_write32(DMA11_CURR_ADDR,val)
-#define bfin_read_DMA11_CURR_X_COUNT()       bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)   bfin_write16(DMA11_CURR_X_COUNT,val)
-#define bfin_read_DMA11_CURR_Y_COUNT()       bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)   bfin_write16(DMA11_CURR_Y_COUNT,val)
-#define bfin_read_DMA11_IRQ_STATUS()         bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)     bfin_write16(DMA11_IRQ_STATUS,val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()     bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG()           bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)       bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()    bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR()       bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT()          bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)      bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT()          bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)      bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY()         bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)     bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY()         bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)     bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()    bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR()        bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()     bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()     bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()       bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)   bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()   bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG()           bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)       bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()    bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR()       bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT()          bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)      bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT()          bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)      bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY()         bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)     bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY()         bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)     bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()    bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR()        bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()     bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()     bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()       bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)   bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()   bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG()           bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)       bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()    bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR()       bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT()          bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)      bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT()          bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)      bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY()         bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)     bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY()         bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)     bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()    bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR()        bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()     bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()     bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()       bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)   bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()   bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG()           bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)       bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()    bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR()       bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT()          bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)      bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT()          bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)      bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY()         bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)     bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY()         bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)     bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()    bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR()        bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()     bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()     bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()       bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)   bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()   bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()              bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)          bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS()               bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)           bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS()              bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY()                bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)            bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT()                bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)            bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                  bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)              bfin_write16(PORTGIO,val)
-#define bfin_read_PORTGIO_CLEAR()            bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)        bfin_write16(PORTGIO_CLEAR,val)
-#define bfin_read_PORTGIO_SET()              bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)          bfin_write16(PORTGIO_SET,val)
-#define bfin_read_PORTGIO_TOGGLE()           bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)       bfin_write16(PORTGIO_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKA()            bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)        bfin_write16(PORTGIO_MASKA,val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()      bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)  bfin_write16(PORTGIO_MASKA_CLEAR,val)
-#define bfin_read_PORTGIO_MASKA_SET()        bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)    bfin_write16(PORTGIO_MASKA_SET,val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()     bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKB()            bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)        bfin_write16(PORTGIO_MASKB,val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()      bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)  bfin_write16(PORTGIO_MASKB_CLEAR,val)
-#define bfin_read_PORTGIO_MASKB_SET()        bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)    bfin_write16(PORTGIO_MASKB_SET,val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()     bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTGIO_DIR()              bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)          bfin_write16(PORTGIO_DIR,val)
-#define bfin_read_PORTGIO_POLAR()            bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)        bfin_write16(PORTGIO_POLAR,val)
-#define bfin_read_PORTGIO_EDGE()             bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)         bfin_write16(PORTGIO_EDGE,val)
-#define bfin_read_PORTGIO_BOTH()             bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)         bfin_write16(PORTGIO_BOTH,val)
-#define bfin_read_PORTGIO_INEN()             bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)         bfin_write16(PORTGIO_INEN,val)
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                  bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)              bfin_write16(PORTHIO,val)
-#define bfin_read_PORTHIO_CLEAR()            bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)        bfin_write16(PORTHIO_CLEAR,val)
-#define bfin_read_PORTHIO_SET()              bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)          bfin_write16(PORTHIO_SET,val)
-#define bfin_read_PORTHIO_TOGGLE()           bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)       bfin_write16(PORTHIO_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKA()            bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)        bfin_write16(PORTHIO_MASKA,val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()      bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)  bfin_write16(PORTHIO_MASKA_CLEAR,val)
-#define bfin_read_PORTHIO_MASKA_SET()        bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)    bfin_write16(PORTHIO_MASKA_SET,val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()     bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKB()            bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)        bfin_write16(PORTHIO_MASKB,val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()      bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)  bfin_write16(PORTHIO_MASKB_CLEAR,val)
-#define bfin_read_PORTHIO_MASKB_SET()        bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)    bfin_write16(PORTHIO_MASKB_SET,val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()     bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTHIO_DIR()              bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)          bfin_write16(PORTHIO_DIR,val)
-#define bfin_read_PORTHIO_POLAR()            bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)        bfin_write16(PORTHIO_POLAR,val)
-#define bfin_read_PORTHIO_EDGE()             bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)         bfin_write16(PORTHIO_EDGE,val)
-#define bfin_read_PORTHIO_BOTH()             bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)         bfin_write16(PORTHIO_BOTH,val)
-#define bfin_read_PORTHIO_INEN()             bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)         bfin_write16(PORTHIO_INEN,val)
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)            bfin_write16(UART1_THR,val)
-#define bfin_read_UART1_RBR()                bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)            bfin_write16(UART1_RBR,val)
-#define bfin_read_UART1_DLL()                bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)            bfin_write16(UART1_DLL,val)
-#define bfin_read_UART1_IER()                bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)            bfin_write16(UART1_IER,val)
-#define bfin_read_UART1_DLH()                bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)            bfin_write16(UART1_DLH,val)
-#define bfin_read_UART1_IIR()                bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)            bfin_write16(UART1_IIR,val)
-#define bfin_read_UART1_LCR()                bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)            bfin_write16(UART1_LCR,val)
-#define bfin_read_UART1_MCR()                bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)            bfin_write16(UART1_MCR,val)
-#define bfin_read_UART1_LSR()                bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)            bfin_write16(UART1_LSR,val)
-#define bfin_read_UART1_MSR()                bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)            bfin_write16(UART1_MSR,val)
-#define bfin_read_UART1_SCR()                bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)            bfin_write16(UART1_SCR,val)
-#define bfin_read_UART1_GCTL()               bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)           bfin_write16(UART1_GCTL,val)
-
-/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                               */
-/* For Mailboxes 0-15 */
-#define bfin_read_CAN_MC1()                  bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val)              bfin_write16(CAN_MC1,val)
-#define bfin_read_CAN_MD1()                  bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val)              bfin_write16(CAN_MD1,val)
-#define bfin_read_CAN_TRS1()                 bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val)             bfin_write16(CAN_TRS1,val)
-#define bfin_read_CAN_TRR1()                 bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val)             bfin_write16(CAN_TRR1,val)
-#define bfin_read_CAN_TA1()                  bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val)              bfin_write16(CAN_TA1,val)
-#define bfin_read_CAN_AA1()                  bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val)              bfin_write16(CAN_AA1,val)
-#define bfin_read_CAN_RMP1()                 bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val)             bfin_write16(CAN_RMP1,val)
-#define bfin_read_CAN_RML1()                 bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val)             bfin_write16(CAN_RML1,val)
-#define bfin_read_CAN_MBTIF1()               bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val)           bfin_write16(CAN_MBTIF1,val)
-#define bfin_read_CAN_MBRIF1()               bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val)           bfin_write16(CAN_MBRIF1,val)
-#define bfin_read_CAN_MBIM1()                bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val)            bfin_write16(CAN_MBIM1,val)
-#define bfin_read_CAN_RFH1()                 bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val)             bfin_write16(CAN_RFH1,val)
-#define bfin_read_CAN_OPSS1()                bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val)            bfin_write16(CAN_OPSS1,val)
-
-/* For Mailboxes 16-31 */
-#define bfin_read_CAN_MC2()                  bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val)              bfin_write16(CAN_MC2,val)
-#define bfin_read_CAN_MD2()                  bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val)              bfin_write16(CAN_MD2,val)
-#define bfin_read_CAN_TRS2()                 bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val)             bfin_write16(CAN_TRS2,val)
-#define bfin_read_CAN_TRR2()                 bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val)             bfin_write16(CAN_TRR2,val)
-#define bfin_read_CAN_TA2()                  bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val)              bfin_write16(CAN_TA2,val)
-#define bfin_read_CAN_AA2()                  bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val)              bfin_write16(CAN_AA2,val)
-#define bfin_read_CAN_RMP2()                 bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val)             bfin_write16(CAN_RMP2,val)
-#define bfin_read_CAN_RML2()                 bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val)             bfin_write16(CAN_RML2,val)
-#define bfin_read_CAN_MBTIF2()               bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val)           bfin_write16(CAN_MBTIF2,val)
-#define bfin_read_CAN_MBRIF2()               bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val)           bfin_write16(CAN_MBRIF2,val)
-#define bfin_read_CAN_MBIM2()                bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val)            bfin_write16(CAN_MBIM2,val)
-#define bfin_read_CAN_RFH2()                 bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val)             bfin_write16(CAN_RFH2,val)
-#define bfin_read_CAN_OPSS2()                bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val)            bfin_write16(CAN_OPSS2,val)
-
-#define bfin_read_CAN_CLOCK()                bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val)            bfin_write16(CAN_CLOCK,val)
-#define bfin_read_CAN_TIMING()               bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val)           bfin_write16(CAN_TIMING,val)
-#define bfin_read_CAN_DEBUG()                bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val)            bfin_write16(CAN_DEBUG,val)
-#define bfin_read_CAN_STATUS()               bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val)           bfin_write16(CAN_STATUS,val)
-#define bfin_read_CAN_CEC()                  bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val)              bfin_write16(CAN_CEC,val)
-#define bfin_read_CAN_GIS()                  bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val)              bfin_write16(CAN_GIS,val)
-#define bfin_read_CAN_GIM()                  bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val)              bfin_write16(CAN_GIM,val)
-#define bfin_read_CAN_GIF()                  bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val)              bfin_write16(CAN_GIF,val)
-#define bfin_read_CAN_CONTROL()              bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val)          bfin_write16(CAN_CONTROL,val)
-#define bfin_read_CAN_INTR()                 bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val)             bfin_write16(CAN_INTR,val)
-#define bfin_read_CAN_SFCMVER()              bfin_read16(CAN_SFCMVER)
-#define bfin_write_CAN_SFCMVER(val)          bfin_write16(CAN_SFCMVER,val)
-#define bfin_read_CAN_MBTD()                 bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val)             bfin_write16(CAN_MBTD,val)
-#define bfin_read_CAN_EWR()                  bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val)              bfin_write16(CAN_EWR,val)
-#define bfin_read_CAN_ESR()                  bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val)              bfin_write16(CAN_ESR,val)
-#define bfin_read_CAN_UCREG()                bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val)            bfin_write16(CAN_UCREG,val)
-#define bfin_read_CAN_UCCNT()                bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val)            bfin_write16(CAN_UCCNT,val)
-#define bfin_read_CAN_UCRC()                 bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val)             bfin_write16(CAN_UCRC,val)
-#define bfin_read_CAN_UCCNF()                bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val)            bfin_write16(CAN_UCCNF,val)
-
-/* Mailbox Acceptance Masks */
-#define bfin_read_CAN_AM00L()                bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val)            bfin_write16(CAN_AM00L,val)
-#define bfin_read_CAN_AM00H()                bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val)            bfin_write16(CAN_AM00H,val)
-#define bfin_read_CAN_AM01L()                bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val)            bfin_write16(CAN_AM01L,val)
-#define bfin_read_CAN_AM01H()                bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val)            bfin_write16(CAN_AM01H,val)
-#define bfin_read_CAN_AM02L()                bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val)            bfin_write16(CAN_AM02L,val)
-#define bfin_read_CAN_AM02H()                bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val)            bfin_write16(CAN_AM02H,val)
-#define bfin_read_CAN_AM03L()                bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val)            bfin_write16(CAN_AM03L,val)
-#define bfin_read_CAN_AM03H()                bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val)            bfin_write16(CAN_AM03H,val)
-#define bfin_read_CAN_AM04L()                bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val)            bfin_write16(CAN_AM04L,val)
-#define bfin_read_CAN_AM04H()                bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val)            bfin_write16(CAN_AM04H,val)
-#define bfin_read_CAN_AM05L()                bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val)            bfin_write16(CAN_AM05L,val)
-#define bfin_read_CAN_AM05H()                bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val)            bfin_write16(CAN_AM05H,val)
-#define bfin_read_CAN_AM06L()                bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val)            bfin_write16(CAN_AM06L,val)
-#define bfin_read_CAN_AM06H()                bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val)            bfin_write16(CAN_AM06H,val)
-#define bfin_read_CAN_AM07L()                bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val)            bfin_write16(CAN_AM07L,val)
-#define bfin_read_CAN_AM07H()                bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val)            bfin_write16(CAN_AM07H,val)
-#define bfin_read_CAN_AM08L()                bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val)            bfin_write16(CAN_AM08L,val)
-#define bfin_read_CAN_AM08H()                bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val)            bfin_write16(CAN_AM08H,val)
-#define bfin_read_CAN_AM09L()                bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val)            bfin_write16(CAN_AM09L,val)
-#define bfin_read_CAN_AM09H()                bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val)            bfin_write16(CAN_AM09H,val)
-#define bfin_read_CAN_AM10L()                bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val)            bfin_write16(CAN_AM10L,val)
-#define bfin_read_CAN_AM10H()                bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val)            bfin_write16(CAN_AM10H,val)
-#define bfin_read_CAN_AM11L()                bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val)            bfin_write16(CAN_AM11L,val)
-#define bfin_read_CAN_AM11H()                bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val)            bfin_write16(CAN_AM11H,val)
-#define bfin_read_CAN_AM12L()                bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val)            bfin_write16(CAN_AM12L,val)
-#define bfin_read_CAN_AM12H()                bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val)            bfin_write16(CAN_AM12H,val)
-#define bfin_read_CAN_AM13L()                bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val)            bfin_write16(CAN_AM13L,val)
-#define bfin_read_CAN_AM13H()                bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val)            bfin_write16(CAN_AM13H,val)
-#define bfin_read_CAN_AM14L()                bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val)            bfin_write16(CAN_AM14L,val)
-#define bfin_read_CAN_AM14H()                bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val)            bfin_write16(CAN_AM14H,val)
-#define bfin_read_CAN_AM15L()                bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val)            bfin_write16(CAN_AM15L,val)
-#define bfin_read_CAN_AM15H()                bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val)            bfin_write16(CAN_AM15H,val)
-
-#define bfin_read_CAN_AM16L()                bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val)            bfin_write16(CAN_AM16L,val)
-#define bfin_read_CAN_AM16H()                bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val)            bfin_write16(CAN_AM16H,val)
-#define bfin_read_CAN_AM17L()                bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val)            bfin_write16(CAN_AM17L,val)
-#define bfin_read_CAN_AM17H()                bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val)            bfin_write16(CAN_AM17H,val)
-#define bfin_read_CAN_AM18L()                bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val)            bfin_write16(CAN_AM18L,val)
-#define bfin_read_CAN_AM18H()                bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val)            bfin_write16(CAN_AM18H,val)
-#define bfin_read_CAN_AM19L()                bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val)            bfin_write16(CAN_AM19L,val)
-#define bfin_read_CAN_AM19H()                bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val)            bfin_write16(CAN_AM19H,val)
-#define bfin_read_CAN_AM20L()                bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val)            bfin_write16(CAN_AM20L,val)
-#define bfin_read_CAN_AM20H()                bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val)            bfin_write16(CAN_AM20H,val)
-#define bfin_read_CAN_AM21L()                bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val)            bfin_write16(CAN_AM21L,val)
-#define bfin_read_CAN_AM21H()                bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val)            bfin_write16(CAN_AM21H,val)
-#define bfin_read_CAN_AM22L()                bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val)            bfin_write16(CAN_AM22L,val)
-#define bfin_read_CAN_AM22H()                bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val)            bfin_write16(CAN_AM22H,val)
-#define bfin_read_CAN_AM23L()                bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val)            bfin_write16(CAN_AM23L,val)
-#define bfin_read_CAN_AM23H()                bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val)            bfin_write16(CAN_AM23H,val)
-#define bfin_read_CAN_AM24L()                bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val)            bfin_write16(CAN_AM24L,val)
-#define bfin_read_CAN_AM24H()                bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val)            bfin_write16(CAN_AM24H,val)
-#define bfin_read_CAN_AM25L()                bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val)            bfin_write16(CAN_AM25L,val)
-#define bfin_read_CAN_AM25H()                bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val)            bfin_write16(CAN_AM25H,val)
-#define bfin_read_CAN_AM26L()                bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val)            bfin_write16(CAN_AM26L,val)
-#define bfin_read_CAN_AM26H()                bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val)            bfin_write16(CAN_AM26H,val)
-#define bfin_read_CAN_AM27L()                bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val)            bfin_write16(CAN_AM27L,val)
-#define bfin_read_CAN_AM27H()                bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val)            bfin_write16(CAN_AM27H,val)
-#define bfin_read_CAN_AM28L()                bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val)            bfin_write16(CAN_AM28L,val)
-#define bfin_read_CAN_AM28H()                bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val)            bfin_write16(CAN_AM28H,val)
-#define bfin_read_CAN_AM29L()                bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val)            bfin_write16(CAN_AM29L,val)
-#define bfin_read_CAN_AM29H()                bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val)            bfin_write16(CAN_AM29H,val)
-#define bfin_read_CAN_AM30L()                bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val)            bfin_write16(CAN_AM30L,val)
-#define bfin_read_CAN_AM30H()                bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val)            bfin_write16(CAN_AM30H,val)
-#define bfin_read_CAN_AM31L()                bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val)            bfin_write16(CAN_AM31L,val)
-#define bfin_read_CAN_AM31H()                bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val)            bfin_write16(CAN_AM31H,val)
-
-/* CAN Acceptance Mask Area Macros      */
-#define bfin_read_CAN_AM_L(x)()              bfin_read16(CAN_AM_L(x))
-#define bfin_write_CAN_AM_L(x)(val)          bfin_write16(CAN_AM_L(x),val)
-#define bfin_read_CAN_AM_H(x)()              bfin_read16(CAN_AM_H(x))
-#define bfin_write_CAN_AM_H(x)(val)          bfin_write16(CAN_AM_H(x),val)
-
-/* Mailbox Registers */
-#define bfin_read_CAN_MB00_ID1()             bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val)         bfin_write16(CAN_MB00_ID1,val)
-#define bfin_read_CAN_MB00_ID0()             bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val)         bfin_write16(CAN_MB00_ID0,val)
-#define bfin_read_CAN_MB00_TIMESTAMP()       bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val)   bfin_write16(CAN_MB00_TIMESTAMP,val)
-#define bfin_read_CAN_MB00_LENGTH()          bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val)      bfin_write16(CAN_MB00_LENGTH,val)
-#define bfin_read_CAN_MB00_DATA3()           bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val)       bfin_write16(CAN_MB00_DATA3,val)
-#define bfin_read_CAN_MB00_DATA2()           bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val)       bfin_write16(CAN_MB00_DATA2,val)
-#define bfin_read_CAN_MB00_DATA1()           bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val)       bfin_write16(CAN_MB00_DATA1,val)
-#define bfin_read_CAN_MB00_DATA0()           bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val)       bfin_write16(CAN_MB00_DATA0,val)
-
-#define bfin_read_CAN_MB01_ID1()             bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val)         bfin_write16(CAN_MB01_ID1,val)
-#define bfin_read_CAN_MB01_ID0()             bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val)         bfin_write16(CAN_MB01_ID0,val)
-#define bfin_read_CAN_MB01_TIMESTAMP()       bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val)   bfin_write16(CAN_MB01_TIMESTAMP,val)
-#define bfin_read_CAN_MB01_LENGTH()          bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val)      bfin_write16(CAN_MB01_LENGTH,val)
-#define bfin_read_CAN_MB01_DATA3()           bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val)       bfin_write16(CAN_MB01_DATA3,val)
-#define bfin_read_CAN_MB01_DATA2()           bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val)       bfin_write16(CAN_MB01_DATA2,val)
-#define bfin_read_CAN_MB01_DATA1()           bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val)       bfin_write16(CAN_MB01_DATA1,val)
-#define bfin_read_CAN_MB01_DATA0()           bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val)       bfin_write16(CAN_MB01_DATA0,val)
-
-#define bfin_read_CAN_MB02_ID1()             bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val)         bfin_write16(CAN_MB02_ID1,val)
-#define bfin_read_CAN_MB02_ID0()             bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val)         bfin_write16(CAN_MB02_ID0,val)
-#define bfin_read_CAN_MB02_TIMESTAMP()       bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val)   bfin_write16(CAN_MB02_TIMESTAMP,val)
-#define bfin_read_CAN_MB02_LENGTH()          bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val)      bfin_write16(CAN_MB02_LENGTH,val)
-#define bfin_read_CAN_MB02_DATA3()           bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val)       bfin_write16(CAN_MB02_DATA3,val)
-#define bfin_read_CAN_MB02_DATA2()           bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val)       bfin_write16(CAN_MB02_DATA2,val)
-#define bfin_read_CAN_MB02_DATA1()           bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val)       bfin_write16(CAN_MB02_DATA1,val)
-#define bfin_read_CAN_MB02_DATA0()           bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val)       bfin_write16(CAN_MB02_DATA0,val)
-
-#define bfin_read_CAN_MB03_ID1()             bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val)         bfin_write16(CAN_MB03_ID1,val)
-#define bfin_read_CAN_MB03_ID0()             bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val)         bfin_write16(CAN_MB03_ID0,val)
-#define bfin_read_CAN_MB03_TIMESTAMP()       bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val)   bfin_write16(CAN_MB03_TIMESTAMP,val)
-#define bfin_read_CAN_MB03_LENGTH()          bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val)      bfin_write16(CAN_MB03_LENGTH,val)
-#define bfin_read_CAN_MB03_DATA3()           bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val)       bfin_write16(CAN_MB03_DATA3,val)
-#define bfin_read_CAN_MB03_DATA2()           bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val)       bfin_write16(CAN_MB03_DATA2,val)
-#define bfin_read_CAN_MB03_DATA1()           bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val)       bfin_write16(CAN_MB03_DATA1,val)
-#define bfin_read_CAN_MB03_DATA0()           bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val)       bfin_write16(CAN_MB03_DATA0,val)
-
-#define bfin_read_CAN_MB04_ID1()             bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val)         bfin_write16(CAN_MB04_ID1,val)
-#define bfin_read_CAN_MB04_ID0()             bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val)         bfin_write16(CAN_MB04_ID0,val)
-#define bfin_read_CAN_MB04_TIMESTAMP()       bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val)   bfin_write16(CAN_MB04_TIMESTAMP,val)
-#define bfin_read_CAN_MB04_LENGTH()          bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val)      bfin_write16(CAN_MB04_LENGTH,val)
-#define bfin_read_CAN_MB04_DATA3()           bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val)       bfin_write16(CAN_MB04_DATA3,val)
-#define bfin_read_CAN_MB04_DATA2()           bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val)       bfin_write16(CAN_MB04_DATA2,val)
-#define bfin_read_CAN_MB04_DATA1()           bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val)       bfin_write16(CAN_MB04_DATA1,val)
-#define bfin_read_CAN_MB04_DATA0()           bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val)       bfin_write16(CAN_MB04_DATA0,val)
-
-#define bfin_read_CAN_MB05_ID1()             bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val)         bfin_write16(CAN_MB05_ID1,val)
-#define bfin_read_CAN_MB05_ID0()             bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val)         bfin_write16(CAN_MB05_ID0,val)
-#define bfin_read_CAN_MB05_TIMESTAMP()       bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val)   bfin_write16(CAN_MB05_TIMESTAMP,val)
-#define bfin_read_CAN_MB05_LENGTH()          bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val)      bfin_write16(CAN_MB05_LENGTH,val)
-#define bfin_read_CAN_MB05_DATA3()           bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val)       bfin_write16(CAN_MB05_DATA3,val)
-#define bfin_read_CAN_MB05_DATA2()           bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val)       bfin_write16(CAN_MB05_DATA2,val)
-#define bfin_read_CAN_MB05_DATA1()           bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val)       bfin_write16(CAN_MB05_DATA1,val)
-#define bfin_read_CAN_MB05_DATA0()           bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val)       bfin_write16(CAN_MB05_DATA0,val)
-
-#define bfin_read_CAN_MB06_ID1()             bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val)         bfin_write16(CAN_MB06_ID1,val)
-#define bfin_read_CAN_MB06_ID0()             bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val)         bfin_write16(CAN_MB06_ID0,val)
-#define bfin_read_CAN_MB06_TIMESTAMP()       bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val)   bfin_write16(CAN_MB06_TIMESTAMP,val)
-#define bfin_read_CAN_MB06_LENGTH()          bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val)      bfin_write16(CAN_MB06_LENGTH,val)
-#define bfin_read_CAN_MB06_DATA3()           bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val)       bfin_write16(CAN_MB06_DATA3,val)
-#define bfin_read_CAN_MB06_DATA2()           bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val)       bfin_write16(CAN_MB06_DATA2,val)
-#define bfin_read_CAN_MB06_DATA1()           bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val)       bfin_write16(CAN_MB06_DATA1,val)
-#define bfin_read_CAN_MB06_DATA0()           bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val)       bfin_write16(CAN_MB06_DATA0,val)
-
-#define bfin_read_CAN_MB07_ID1()             bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val)         bfin_write16(CAN_MB07_ID1,val)
-#define bfin_read_CAN_MB07_ID0()             bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val)         bfin_write16(CAN_MB07_ID0,val)
-#define bfin_read_CAN_MB07_TIMESTAMP()       bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val)   bfin_write16(CAN_MB07_TIMESTAMP,val)
-#define bfin_read_CAN_MB07_LENGTH()          bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val)      bfin_write16(CAN_MB07_LENGTH,val)
-#define bfin_read_CAN_MB07_DATA3()           bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val)       bfin_write16(CAN_MB07_DATA3,val)
-#define bfin_read_CAN_MB07_DATA2()           bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val)       bfin_write16(CAN_MB07_DATA2,val)
-#define bfin_read_CAN_MB07_DATA1()           bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val)       bfin_write16(CAN_MB07_DATA1,val)
-#define bfin_read_CAN_MB07_DATA0()           bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val)       bfin_write16(CAN_MB07_DATA0,val)
-
-#define bfin_read_CAN_MB08_ID1()             bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val)         bfin_write16(CAN_MB08_ID1,val)
-#define bfin_read_CAN_MB08_ID0()             bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val)         bfin_write16(CAN_MB08_ID0,val)
-#define bfin_read_CAN_MB08_TIMESTAMP()       bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val)   bfin_write16(CAN_MB08_TIMESTAMP,val)
-#define bfin_read_CAN_MB08_LENGTH()          bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val)      bfin_write16(CAN_MB08_LENGTH,val)
-#define bfin_read_CAN_MB08_DATA3()           bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val)       bfin_write16(CAN_MB08_DATA3,val)
-#define bfin_read_CAN_MB08_DATA2()           bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val)       bfin_write16(CAN_MB08_DATA2,val)
-#define bfin_read_CAN_MB08_DATA1()           bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val)       bfin_write16(CAN_MB08_DATA1,val)
-#define bfin_read_CAN_MB08_DATA0()           bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val)       bfin_write16(CAN_MB08_DATA0,val)
-
-#define bfin_read_CAN_MB09_ID1()             bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val)         bfin_write16(CAN_MB09_ID1,val)
-#define bfin_read_CAN_MB09_ID0()             bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val)         bfin_write16(CAN_MB09_ID0,val)
-#define bfin_read_CAN_MB09_TIMESTAMP()       bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val)   bfin_write16(CAN_MB09_TIMESTAMP,val)
-#define bfin_read_CAN_MB09_LENGTH()          bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val)      bfin_write16(CAN_MB09_LENGTH,val)
-#define bfin_read_CAN_MB09_DATA3()           bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val)       bfin_write16(CAN_MB09_DATA3,val)
-#define bfin_read_CAN_MB09_DATA2()           bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val)       bfin_write16(CAN_MB09_DATA2,val)
-#define bfin_read_CAN_MB09_DATA1()           bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val)       bfin_write16(CAN_MB09_DATA1,val)
-#define bfin_read_CAN_MB09_DATA0()           bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val)       bfin_write16(CAN_MB09_DATA0,val)
-
-#define bfin_read_CAN_MB10_ID1()             bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val)         bfin_write16(CAN_MB10_ID1,val)
-#define bfin_read_CAN_MB10_ID0()             bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val)         bfin_write16(CAN_MB10_ID0,val)
-#define bfin_read_CAN_MB10_TIMESTAMP()       bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val)   bfin_write16(CAN_MB10_TIMESTAMP,val)
-#define bfin_read_CAN_MB10_LENGTH()          bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val)      bfin_write16(CAN_MB10_LENGTH,val)
-#define bfin_read_CAN_MB10_DATA3()           bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val)       bfin_write16(CAN_MB10_DATA3,val)
-#define bfin_read_CAN_MB10_DATA2()           bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val)       bfin_write16(CAN_MB10_DATA2,val)
-#define bfin_read_CAN_MB10_DATA1()           bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val)       bfin_write16(CAN_MB10_DATA1,val)
-#define bfin_read_CAN_MB10_DATA0()           bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val)       bfin_write16(CAN_MB10_DATA0,val)
-
-#define bfin_read_CAN_MB11_ID1()             bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val)         bfin_write16(CAN_MB11_ID1,val)
-#define bfin_read_CAN_MB11_ID0()             bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val)         bfin_write16(CAN_MB11_ID0,val)
-#define bfin_read_CAN_MB11_TIMESTAMP()       bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val)   bfin_write16(CAN_MB11_TIMESTAMP,val)
-#define bfin_read_CAN_MB11_LENGTH()          bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val)      bfin_write16(CAN_MB11_LENGTH,val)
-#define bfin_read_CAN_MB11_DATA3()           bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val)       bfin_write16(CAN_MB11_DATA3,val)
-#define bfin_read_CAN_MB11_DATA2()           bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val)       bfin_write16(CAN_MB11_DATA2,val)
-#define bfin_read_CAN_MB11_DATA1()           bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val)       bfin_write16(CAN_MB11_DATA1,val)
-#define bfin_read_CAN_MB11_DATA0()           bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val)       bfin_write16(CAN_MB11_DATA0,val)
-
-#define bfin_read_CAN_MB12_ID1()             bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val)         bfin_write16(CAN_MB12_ID1,val)
-#define bfin_read_CAN_MB12_ID0()             bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val)         bfin_write16(CAN_MB12_ID0,val)
-#define bfin_read_CAN_MB12_TIMESTAMP()       bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val)   bfin_write16(CAN_MB12_TIMESTAMP,val)
-#define bfin_read_CAN_MB12_LENGTH()          bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val)      bfin_write16(CAN_MB12_LENGTH,val)
-#define bfin_read_CAN_MB12_DATA3()           bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val)       bfin_write16(CAN_MB12_DATA3,val)
-#define bfin_read_CAN_MB12_DATA2()           bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val)       bfin_write16(CAN_MB12_DATA2,val)
-#define bfin_read_CAN_MB12_DATA1()           bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val)       bfin_write16(CAN_MB12_DATA1,val)
-#define bfin_read_CAN_MB12_DATA0()           bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val)       bfin_write16(CAN_MB12_DATA0,val)
-
-#define bfin_read_CAN_MB13_ID1()             bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val)         bfin_write16(CAN_MB13_ID1,val)
-#define bfin_read_CAN_MB13_ID0()             bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val)         bfin_write16(CAN_MB13_ID0,val)
-#define bfin_read_CAN_MB13_TIMESTAMP()       bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val)   bfin_write16(CAN_MB13_TIMESTAMP,val)
-#define bfin_read_CAN_MB13_LENGTH()          bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val)      bfin_write16(CAN_MB13_LENGTH,val)
-#define bfin_read_CAN_MB13_DATA3()           bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val)       bfin_write16(CAN_MB13_DATA3,val)
-#define bfin_read_CAN_MB13_DATA2()           bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val)       bfin_write16(CAN_MB13_DATA2,val)
-#define bfin_read_CAN_MB13_DATA1()           bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val)       bfin_write16(CAN_MB13_DATA1,val)
-#define bfin_read_CAN_MB13_DATA0()           bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val)       bfin_write16(CAN_MB13_DATA0,val)
-
-#define bfin_read_CAN_MB14_ID1()             bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val)         bfin_write16(CAN_MB14_ID1,val)
-#define bfin_read_CAN_MB14_ID0()             bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val)         bfin_write16(CAN_MB14_ID0,val)
-#define bfin_read_CAN_MB14_TIMESTAMP()       bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val)   bfin_write16(CAN_MB14_TIMESTAMP,val)
-#define bfin_read_CAN_MB14_LENGTH()          bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val)      bfin_write16(CAN_MB14_LENGTH,val)
-#define bfin_read_CAN_MB14_DATA3()           bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val)       bfin_write16(CAN_MB14_DATA3,val)
-#define bfin_read_CAN_MB14_DATA2()           bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val)       bfin_write16(CAN_MB14_DATA2,val)
-#define bfin_read_CAN_MB14_DATA1()           bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val)       bfin_write16(CAN_MB14_DATA1,val)
-#define bfin_read_CAN_MB14_DATA0()           bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val)       bfin_write16(CAN_MB14_DATA0,val)
-
-#define bfin_read_CAN_MB15_ID1()             bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val)         bfin_write16(CAN_MB15_ID1,val)
-#define bfin_read_CAN_MB15_ID0()             bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val)         bfin_write16(CAN_MB15_ID0,val)
-#define bfin_read_CAN_MB15_TIMESTAMP()       bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val)   bfin_write16(CAN_MB15_TIMESTAMP,val)
-#define bfin_read_CAN_MB15_LENGTH()          bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val)      bfin_write16(CAN_MB15_LENGTH,val)
-#define bfin_read_CAN_MB15_DATA3()           bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val)       bfin_write16(CAN_MB15_DATA3,val)
-#define bfin_read_CAN_MB15_DATA2()           bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val)       bfin_write16(CAN_MB15_DATA2,val)
-#define bfin_read_CAN_MB15_DATA1()           bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val)       bfin_write16(CAN_MB15_DATA1,val)
-#define bfin_read_CAN_MB15_DATA0()           bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val)       bfin_write16(CAN_MB15_DATA0,val)
-
-#define bfin_read_CAN_MB16_ID1()             bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val)         bfin_write16(CAN_MB16_ID1,val)
-#define bfin_read_CAN_MB16_ID0()             bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val)         bfin_write16(CAN_MB16_ID0,val)
-#define bfin_read_CAN_MB16_TIMESTAMP()       bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val)   bfin_write16(CAN_MB16_TIMESTAMP,val)
-#define bfin_read_CAN_MB16_LENGTH()          bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val)      bfin_write16(CAN_MB16_LENGTH,val)
-#define bfin_read_CAN_MB16_DATA3()           bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val)       bfin_write16(CAN_MB16_DATA3,val)
-#define bfin_read_CAN_MB16_DATA2()           bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val)       bfin_write16(CAN_MB16_DATA2,val)
-#define bfin_read_CAN_MB16_DATA1()           bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val)       bfin_write16(CAN_MB16_DATA1,val)
-#define bfin_read_CAN_MB16_DATA0()           bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val)       bfin_write16(CAN_MB16_DATA0,val)
-
-#define bfin_read_CAN_MB17_ID1()             bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val)         bfin_write16(CAN_MB17_ID1,val)
-#define bfin_read_CAN_MB17_ID0()             bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val)         bfin_write16(CAN_MB17_ID0,val)
-#define bfin_read_CAN_MB17_TIMESTAMP()       bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val)   bfin_write16(CAN_MB17_TIMESTAMP,val)
-#define bfin_read_CAN_MB17_LENGTH()          bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val)      bfin_write16(CAN_MB17_LENGTH,val)
-#define bfin_read_CAN_MB17_DATA3()           bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val)       bfin_write16(CAN_MB17_DATA3,val)
-#define bfin_read_CAN_MB17_DATA2()           bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val)       bfin_write16(CAN_MB17_DATA2,val)
-#define bfin_read_CAN_MB17_DATA1()           bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val)       bfin_write16(CAN_MB17_DATA1,val)
-#define bfin_read_CAN_MB17_DATA0()           bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val)       bfin_write16(CAN_MB17_DATA0,val)
-
-#define bfin_read_CAN_MB18_ID1()             bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val)         bfin_write16(CAN_MB18_ID1,val)
-#define bfin_read_CAN_MB18_ID0()             bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val)         bfin_write16(CAN_MB18_ID0,val)
-#define bfin_read_CAN_MB18_TIMESTAMP()       bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val)   bfin_write16(CAN_MB18_TIMESTAMP,val)
-#define bfin_read_CAN_MB18_LENGTH()          bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val)      bfin_write16(CAN_MB18_LENGTH,val)
-#define bfin_read_CAN_MB18_DATA3()           bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val)       bfin_write16(CAN_MB18_DATA3,val)
-#define bfin_read_CAN_MB18_DATA2()           bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val)       bfin_write16(CAN_MB18_DATA2,val)
-#define bfin_read_CAN_MB18_DATA1()           bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val)       bfin_write16(CAN_MB18_DATA1,val)
-#define bfin_read_CAN_MB18_DATA0()           bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val)       bfin_write16(CAN_MB18_DATA0,val)
-
-#define bfin_read_CAN_MB19_ID1()             bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val)         bfin_write16(CAN_MB19_ID1,val)
-#define bfin_read_CAN_MB19_ID0()             bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val)         bfin_write16(CAN_MB19_ID0,val)
-#define bfin_read_CAN_MB19_TIMESTAMP()       bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val)   bfin_write16(CAN_MB19_TIMESTAMP,val)
-#define bfin_read_CAN_MB19_LENGTH()          bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val)      bfin_write16(CAN_MB19_LENGTH,val)
-#define bfin_read_CAN_MB19_DATA3()           bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val)       bfin_write16(CAN_MB19_DATA3,val)
-#define bfin_read_CAN_MB19_DATA2()           bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val)       bfin_write16(CAN_MB19_DATA2,val)
-#define bfin_read_CAN_MB19_DATA1()           bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val)       bfin_write16(CAN_MB19_DATA1,val)
-#define bfin_read_CAN_MB19_DATA0()           bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val)       bfin_write16(CAN_MB19_DATA0,val)
-
-#define bfin_read_CAN_MB20_ID1()             bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val)         bfin_write16(CAN_MB20_ID1,val)
-#define bfin_read_CAN_MB20_ID0()             bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val)         bfin_write16(CAN_MB20_ID0,val)
-#define bfin_read_CAN_MB20_TIMESTAMP()       bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val)   bfin_write16(CAN_MB20_TIMESTAMP,val)
-#define bfin_read_CAN_MB20_LENGTH()          bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val)      bfin_write16(CAN_MB20_LENGTH,val)
-#define bfin_read_CAN_MB20_DATA3()           bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val)       bfin_write16(CAN_MB20_DATA3,val)
-#define bfin_read_CAN_MB20_DATA2()           bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val)       bfin_write16(CAN_MB20_DATA2,val)
-#define bfin_read_CAN_MB20_DATA1()           bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val)       bfin_write16(CAN_MB20_DATA1,val)
-#define bfin_read_CAN_MB20_DATA0()           bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val)       bfin_write16(CAN_MB20_DATA0,val)
-
-#define bfin_read_CAN_MB21_ID1()             bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val)         bfin_write16(CAN_MB21_ID1,val)
-#define bfin_read_CAN_MB21_ID0()             bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val)         bfin_write16(CAN_MB21_ID0,val)
-#define bfin_read_CAN_MB21_TIMESTAMP()       bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val)   bfin_write16(CAN_MB21_TIMESTAMP,val)
-#define bfin_read_CAN_MB21_LENGTH()          bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val)      bfin_write16(CAN_MB21_LENGTH,val)
-#define bfin_read_CAN_MB21_DATA3()           bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val)       bfin_write16(CAN_MB21_DATA3,val)
-#define bfin_read_CAN_MB21_DATA2()           bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val)       bfin_write16(CAN_MB21_DATA2,val)
-#define bfin_read_CAN_MB21_DATA1()           bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val)       bfin_write16(CAN_MB21_DATA1,val)
-#define bfin_read_CAN_MB21_DATA0()           bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val)       bfin_write16(CAN_MB21_DATA0,val)
-
-#define bfin_read_CAN_MB22_ID1()             bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val)         bfin_write16(CAN_MB22_ID1,val)
-#define bfin_read_CAN_MB22_ID0()             bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val)         bfin_write16(CAN_MB22_ID0,val)
-#define bfin_read_CAN_MB22_TIMESTAMP()       bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val)   bfin_write16(CAN_MB22_TIMESTAMP,val)
-#define bfin_read_CAN_MB22_LENGTH()          bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val)      bfin_write16(CAN_MB22_LENGTH,val)
-#define bfin_read_CAN_MB22_DATA3()           bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val)       bfin_write16(CAN_MB22_DATA3,val)
-#define bfin_read_CAN_MB22_DATA2()           bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val)       bfin_write16(CAN_MB22_DATA2,val)
-#define bfin_read_CAN_MB22_DATA1()           bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val)       bfin_write16(CAN_MB22_DATA1,val)
-#define bfin_read_CAN_MB22_DATA0()           bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val)       bfin_write16(CAN_MB22_DATA0,val)
-
-#define bfin_read_CAN_MB23_ID1()             bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val)         bfin_write16(CAN_MB23_ID1,val)
-#define bfin_read_CAN_MB23_ID0()             bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val)         bfin_write16(CAN_MB23_ID0,val)
-#define bfin_read_CAN_MB23_TIMESTAMP()       bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val)   bfin_write16(CAN_MB23_TIMESTAMP,val)
-#define bfin_read_CAN_MB23_LENGTH()          bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val)      bfin_write16(CAN_MB23_LENGTH,val)
-#define bfin_read_CAN_MB23_DATA3()           bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val)       bfin_write16(CAN_MB23_DATA3,val)
-#define bfin_read_CAN_MB23_DATA2()           bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val)       bfin_write16(CAN_MB23_DATA2,val)
-#define bfin_read_CAN_MB23_DATA1()           bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val)       bfin_write16(CAN_MB23_DATA1,val)
-#define bfin_read_CAN_MB23_DATA0()           bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val)       bfin_write16(CAN_MB23_DATA0,val)
-
-#define bfin_read_CAN_MB24_ID1()             bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val)         bfin_write16(CAN_MB24_ID1,val)
-#define bfin_read_CAN_MB24_ID0()             bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val)         bfin_write16(CAN_MB24_ID0,val)
-#define bfin_read_CAN_MB24_TIMESTAMP()       bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val)   bfin_write16(CAN_MB24_TIMESTAMP,val)
-#define bfin_read_CAN_MB24_LENGTH()          bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val)      bfin_write16(CAN_MB24_LENGTH,val)
-#define bfin_read_CAN_MB24_DATA3()           bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val)       bfin_write16(CAN_MB24_DATA3,val)
-#define bfin_read_CAN_MB24_DATA2()           bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val)       bfin_write16(CAN_MB24_DATA2,val)
-#define bfin_read_CAN_MB24_DATA1()           bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val)       bfin_write16(CAN_MB24_DATA1,val)
-#define bfin_read_CAN_MB24_DATA0()           bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val)       bfin_write16(CAN_MB24_DATA0,val)
-
-#define bfin_read_CAN_MB25_ID1()             bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val)         bfin_write16(CAN_MB25_ID1,val)
-#define bfin_read_CAN_MB25_ID0()             bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val)         bfin_write16(CAN_MB25_ID0,val)
-#define bfin_read_CAN_MB25_TIMESTAMP()       bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val)   bfin_write16(CAN_MB25_TIMESTAMP,val)
-#define bfin_read_CAN_MB25_LENGTH()          bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val)      bfin_write16(CAN_MB25_LENGTH,val)
-#define bfin_read_CAN_MB25_DATA3()           bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val)       bfin_write16(CAN_MB25_DATA3,val)
-#define bfin_read_CAN_MB25_DATA2()           bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val)       bfin_write16(CAN_MB25_DATA2,val)
-#define bfin_read_CAN_MB25_DATA1()           bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val)       bfin_write16(CAN_MB25_DATA1,val)
-#define bfin_read_CAN_MB25_DATA0()           bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val)       bfin_write16(CAN_MB25_DATA0,val)
-
-#define bfin_read_CAN_MB26_ID1()             bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val)         bfin_write16(CAN_MB26_ID1,val)
-#define bfin_read_CAN_MB26_ID0()             bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val)         bfin_write16(CAN_MB26_ID0,val)
-#define bfin_read_CAN_MB26_TIMESTAMP()       bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val)   bfin_write16(CAN_MB26_TIMESTAMP,val)
-#define bfin_read_CAN_MB26_LENGTH()          bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val)      bfin_write16(CAN_MB26_LENGTH,val)
-#define bfin_read_CAN_MB26_DATA3()           bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val)       bfin_write16(CAN_MB26_DATA3,val)
-#define bfin_read_CAN_MB26_DATA2()           bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val)       bfin_write16(CAN_MB26_DATA2,val)
-#define bfin_read_CAN_MB26_DATA1()           bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val)       bfin_write16(CAN_MB26_DATA1,val)
-#define bfin_read_CAN_MB26_DATA0()           bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val)       bfin_write16(CAN_MB26_DATA0,val)
-
-#define bfin_read_CAN_MB27_ID1()             bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val)         bfin_write16(CAN_MB27_ID1,val)
-#define bfin_read_CAN_MB27_ID0()             bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val)         bfin_write16(CAN_MB27_ID0,val)
-#define bfin_read_CAN_MB27_TIMESTAMP()       bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val)   bfin_write16(CAN_MB27_TIMESTAMP,val)
-#define bfin_read_CAN_MB27_LENGTH()          bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val)      bfin_write16(CAN_MB27_LENGTH,val)
-#define bfin_read_CAN_MB27_DATA3()           bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val)       bfin_write16(CAN_MB27_DATA3,val)
-#define bfin_read_CAN_MB27_DATA2()           bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val)       bfin_write16(CAN_MB27_DATA2,val)
-#define bfin_read_CAN_MB27_DATA1()           bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val)       bfin_write16(CAN_MB27_DATA1,val)
-#define bfin_read_CAN_MB27_DATA0()           bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val)       bfin_write16(CAN_MB27_DATA0,val)
-
-#define bfin_read_CAN_MB28_ID1()             bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val)         bfin_write16(CAN_MB28_ID1,val)
-#define bfin_read_CAN_MB28_ID0()             bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val)         bfin_write16(CAN_MB28_ID0,val)
-#define bfin_read_CAN_MB28_TIMESTAMP()       bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val)   bfin_write16(CAN_MB28_TIMESTAMP,val)
-#define bfin_read_CAN_MB28_LENGTH()          bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val)      bfin_write16(CAN_MB28_LENGTH,val)
-#define bfin_read_CAN_MB28_DATA3()           bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val)       bfin_write16(CAN_MB28_DATA3,val)
-#define bfin_read_CAN_MB28_DATA2()           bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val)       bfin_write16(CAN_MB28_DATA2,val)
-#define bfin_read_CAN_MB28_DATA1()           bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val)       bfin_write16(CAN_MB28_DATA1,val)
-#define bfin_read_CAN_MB28_DATA0()           bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val)       bfin_write16(CAN_MB28_DATA0,val)
-
-#define bfin_read_CAN_MB29_ID1()             bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val)         bfin_write16(CAN_MB29_ID1,val)
-#define bfin_read_CAN_MB29_ID0()             bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val)         bfin_write16(CAN_MB29_ID0,val)
-#define bfin_read_CAN_MB29_TIMESTAMP()       bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val)   bfin_write16(CAN_MB29_TIMESTAMP,val)
-#define bfin_read_CAN_MB29_LENGTH()          bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val)      bfin_write16(CAN_MB29_LENGTH,val)
-#define bfin_read_CAN_MB29_DATA3()           bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val)       bfin_write16(CAN_MB29_DATA3,val)
-#define bfin_read_CAN_MB29_DATA2()           bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val)       bfin_write16(CAN_MB29_DATA2,val)
-#define bfin_read_CAN_MB29_DATA1()           bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val)       bfin_write16(CAN_MB29_DATA1,val)
-#define bfin_read_CAN_MB29_DATA0()           bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val)       bfin_write16(CAN_MB29_DATA0,val)
-
-#define bfin_read_CAN_MB30_ID1()             bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val)         bfin_write16(CAN_MB30_ID1,val)
-#define bfin_read_CAN_MB30_ID0()             bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val)         bfin_write16(CAN_MB30_ID0,val)
-#define bfin_read_CAN_MB30_TIMESTAMP()       bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val)   bfin_write16(CAN_MB30_TIMESTAMP,val)
-#define bfin_read_CAN_MB30_LENGTH()          bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val)      bfin_write16(CAN_MB30_LENGTH,val)
-#define bfin_read_CAN_MB30_DATA3()           bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val)       bfin_write16(CAN_MB30_DATA3,val)
-#define bfin_read_CAN_MB30_DATA2()           bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val)       bfin_write16(CAN_MB30_DATA2,val)
-#define bfin_read_CAN_MB30_DATA1()           bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val)       bfin_write16(CAN_MB30_DATA1,val)
-#define bfin_read_CAN_MB30_DATA0()           bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val)       bfin_write16(CAN_MB30_DATA0,val)
-
-#define bfin_read_CAN_MB31_ID1()             bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val)         bfin_write16(CAN_MB31_ID1,val)
-#define bfin_read_CAN_MB31_ID0()             bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val)         bfin_write16(CAN_MB31_ID0,val)
-#define bfin_read_CAN_MB31_TIMESTAMP()       bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val)   bfin_write16(CAN_MB31_TIMESTAMP,val)
-#define bfin_read_CAN_MB31_LENGTH()          bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val)      bfin_write16(CAN_MB31_LENGTH,val)
-#define bfin_read_CAN_MB31_DATA3()           bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val)       bfin_write16(CAN_MB31_DATA3,val)
-#define bfin_read_CAN_MB31_DATA2()           bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val)       bfin_write16(CAN_MB31_DATA2,val)
-#define bfin_read_CAN_MB31_DATA1()           bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val)       bfin_write16(CAN_MB31_DATA1,val)
-#define bfin_read_CAN_MB31_DATA0()           bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val)       bfin_write16(CAN_MB31_DATA0,val)
-
-/* CAN Mailbox Area Macros              */
-#define bfin_read_CAN_MB_ID1(x)()            bfin_read16(CAN_MB_ID1(x))
-#define bfin_write_CAN_MB_ID1(x)(val)        bfin_write16(CAN_MB_ID1(x),val)
-#define bfin_read_CAN_MB_ID0(x)()            bfin_read16(CAN_MB_ID0(x))
-#define bfin_write_CAN_MB_ID0(x)(val)        bfin_write16(CAN_MB_ID0(x),val)
-#define bfin_read_CAN_MB_TIMESTAMP(x)()      bfin_read16(CAN_MB_TIMESTAMP(x))
-#define bfin_write_CAN_MB_TIMESTAMP(x)(val)  bfin_write16(CAN_MB_TIMESTAMP(x),val)
-#define bfin_read_CAN_MB_LENGTH(x)()         bfin_read16(CAN_MB_LENGTH(x))
-#define bfin_write_CAN_MB_LENGTH(x)(val)     bfin_write16(CAN_MB_LENGTH(x),val)
-#define bfin_read_CAN_MB_DATA3(x)()          bfin_read16(CAN_MB_DATA3(x))
-#define bfin_write_CAN_MB_DATA3(x)(val)      bfin_write16(CAN_MB_DATA3(x),val)
-#define bfin_read_CAN_MB_DATA2(x)()          bfin_read16(CAN_MB_DATA2(x))
-#define bfin_write_CAN_MB_DATA2(x)(val)      bfin_write16(CAN_MB_DATA2(x),val)
-#define bfin_read_CAN_MB_DATA1(x)()          bfin_read16(CAN_MB_DATA1(x))
-#define bfin_write_CAN_MB_DATA1(x)(val)      bfin_write16(CAN_MB_DATA1(x),val)
-#define bfin_read_CAN_MB_DATA0(x)()          bfin_read16(CAN_MB_DATA0(x))
-#define bfin_write_CAN_MB_DATA0(x)(val)      bfin_write16(CAN_MB_DATA0(x),val)
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)            bfin_write16(PORTF_FER,val)
-#define bfin_read_PORTG_FER()                bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)            bfin_write16(PORTG_FER,val)
-#define bfin_read_PORTH_FER()                bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)            bfin_write16(PORTH_FER,val)
-#define bfin_read_PORT_MUX()                 bfin_read16(BFIN_PORT_MUX)
-#define bfin_write_PORT_MUX(val)             bfin_write16(BFIN_PORT_MUX,val)
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()           bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)       bfin_write16(HMDMA0_CONTROL,val)
-#define bfin_read_HMDMA0_ECINIT()            bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)        bfin_write16(HMDMA0_ECINIT,val)
-#define bfin_read_HMDMA0_BCINIT()            bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)        bfin_write16(HMDMA0_BCINIT,val)
-#define bfin_read_HMDMA0_ECURGENT()          bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)      bfin_write16(HMDMA0_ECURGENT,val)
-#define bfin_read_HMDMA0_ECOVERFLOW()        bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)    bfin_write16(HMDMA0_ECOVERFLOW,val)
-#define bfin_read_HMDMA0_ECOUNT()            bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)        bfin_write16(HMDMA0_ECOUNT,val)
-#define bfin_read_HMDMA0_BCOUNT()            bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)        bfin_write16(HMDMA0_BCOUNT,val)
-
-#define bfin_read_HMDMA1_CONTROL()           bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)       bfin_write16(HMDMA1_CONTROL,val)
-#define bfin_read_HMDMA1_ECINIT()            bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)        bfin_write16(HMDMA1_ECINIT,val)
-#define bfin_read_HMDMA1_BCINIT()            bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)        bfin_write16(HMDMA1_BCINIT,val)
-#define bfin_read_HMDMA1_ECURGENT()          bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)      bfin_write16(HMDMA1_ECURGENT,val)
-#define bfin_read_HMDMA1_ECOVERFLOW()        bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)    bfin_write16(HMDMA1_ECOVERFLOW,val)
-#define bfin_read_HMDMA1_ECOUNT()            bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)        bfin_write16(HMDMA1_ECOUNT,val)
-#define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)
-
-#endif                          /* _CDEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF537.h b/include/asm-blackfin/mach-bf537/cdefBF537.h
deleted file mode 100644
index b8fc949a991f..000000000000
--- a/include/asm-blackfin/mach-bf537/cdefBF537.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *      System MMR Register Map
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534                                                                 */
-#include "cdefBF534.h"
-
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF537.h"
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537              */
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                               */
-#define bfin_read_EMAC_OPMODE()              bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)          bfin_write32(EMAC_OPMODE,val)
-#define bfin_read_EMAC_ADDRLO()              bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)          bfin_write32(EMAC_ADDRLO,val)
-#define bfin_read_EMAC_ADDRHI()              bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)          bfin_write32(EMAC_ADDRHI,val)
-#define bfin_read_EMAC_HASHLO()              bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)          bfin_write32(EMAC_HASHLO,val)
-#define bfin_read_EMAC_HASHHI()              bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)          bfin_write32(EMAC_HASHHI,val)
-#define bfin_read_EMAC_STAADD()              bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)          bfin_write32(EMAC_STAADD,val)
-#define bfin_read_EMAC_STADAT()              bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)          bfin_write32(EMAC_STADAT,val)
-#define bfin_read_EMAC_FLC()                 bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)             bfin_write32(EMAC_FLC,val)
-#define bfin_read_EMAC_VLAN1()               bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)           bfin_write32(EMAC_VLAN1,val)
-#define bfin_read_EMAC_VLAN2()               bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)           bfin_write32(EMAC_VLAN2,val)
-#define bfin_read_EMAC_WKUP_CTL()            bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)        bfin_write32(EMAC_WKUP_CTL,val)
-#define bfin_read_EMAC_WKUP_FFMSK0()         bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val)     bfin_write32(EMAC_WKUP_FFMSK0,val)
-#define bfin_read_EMAC_WKUP_FFMSK1()         bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val)     bfin_write32(EMAC_WKUP_FFMSK1,val)
-#define bfin_read_EMAC_WKUP_FFMSK2()         bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val)     bfin_write32(EMAC_WKUP_FFMSK2,val)
-#define bfin_read_EMAC_WKUP_FFMSK3()         bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val)     bfin_write32(EMAC_WKUP_FFMSK3,val)
-#define bfin_read_EMAC_WKUP_FFCMD()          bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val)      bfin_write32(EMAC_WKUP_FFCMD,val)
-#define bfin_read_EMAC_WKUP_FFOFF()          bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val)      bfin_write32(EMAC_WKUP_FFOFF,val)
-#define bfin_read_EMAC_WKUP_FFCRC0()         bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val)     bfin_write32(EMAC_WKUP_FFCRC0,val)
-#define bfin_read_EMAC_WKUP_FFCRC1()         bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val)     bfin_write32(EMAC_WKUP_FFCRC1,val)
-
-#define bfin_read_EMAC_SYSCTL()              bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)          bfin_write32(EMAC_SYSCTL,val)
-#define bfin_read_EMAC_SYSTAT()              bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)          bfin_write32(EMAC_SYSTAT,val)
-#define bfin_read_EMAC_RX_STAT()             bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)         bfin_write32(EMAC_RX_STAT,val)
-#define bfin_read_EMAC_RX_STKY()             bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)         bfin_write32(EMAC_RX_STKY,val)
-#define bfin_read_EMAC_RX_IRQE()             bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)         bfin_write32(EMAC_RX_IRQE,val)
-#define bfin_read_EMAC_TX_STAT()             bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)         bfin_write32(EMAC_TX_STAT,val)
-#define bfin_read_EMAC_TX_STKY()             bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)         bfin_write32(EMAC_TX_STKY,val)
-#define bfin_read_EMAC_TX_IRQE()             bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)         bfin_write32(EMAC_TX_IRQE,val)
-
-#define bfin_read_EMAC_MMC_CTL()             bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)         bfin_write32(EMAC_MMC_CTL,val)
-#define bfin_read_EMAC_MMC_RIRQS()           bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val)       bfin_write32(EMAC_MMC_RIRQS,val)
-#define bfin_read_EMAC_MMC_RIRQE()           bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val)       bfin_write32(EMAC_MMC_RIRQE,val)
-#define bfin_read_EMAC_MMC_TIRQS()           bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val)       bfin_write32(EMAC_MMC_TIRQS,val)
-#define bfin_read_EMAC_MMC_TIRQE()           bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val)       bfin_write32(EMAC_MMC_TIRQE,val)
-
-#define bfin_read_EMAC_RXC_OK()              bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)          bfin_write32(EMAC_RXC_OK,val)
-#define bfin_read_EMAC_RXC_FCS()             bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)         bfin_write32(EMAC_RXC_FCS,val)
-#define bfin_read_EMAC_RXC_ALIGN()           bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val)       bfin_write32(EMAC_RXC_ALIGN,val)
-#define bfin_read_EMAC_RXC_OCTET()           bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val)       bfin_write32(EMAC_RXC_OCTET,val)
-#define bfin_read_EMAC_RXC_DMAOVF()          bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val)      bfin_write32(EMAC_RXC_DMAOVF,val)
-#define bfin_read_EMAC_RXC_UNICST()          bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val)      bfin_write32(EMAC_RXC_UNICST,val)
-#define bfin_read_EMAC_RXC_MULTI()           bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val)       bfin_write32(EMAC_RXC_MULTI,val)
-#define bfin_read_EMAC_RXC_BROAD()           bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val)       bfin_write32(EMAC_RXC_BROAD,val)
-#define bfin_read_EMAC_RXC_LNERRI()          bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val)      bfin_write32(EMAC_RXC_LNERRI,val)
-#define bfin_read_EMAC_RXC_LNERRO()          bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val)      bfin_write32(EMAC_RXC_LNERRO,val)
-#define bfin_read_EMAC_RXC_LONG()            bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)        bfin_write32(EMAC_RXC_LONG,val)
-#define bfin_read_EMAC_RXC_MACCTL()          bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val)      bfin_write32(EMAC_RXC_MACCTL,val)
-#define bfin_read_EMAC_RXC_OPCODE()          bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val)      bfin_write32(EMAC_RXC_OPCODE,val)
-#define bfin_read_EMAC_RXC_PAUSE()           bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val)       bfin_write32(EMAC_RXC_PAUSE,val)
-#define bfin_read_EMAC_RXC_ALLFRM()          bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val)      bfin_write32(EMAC_RXC_ALLFRM,val)
-#define bfin_read_EMAC_RXC_ALLOCT()          bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val)      bfin_write32(EMAC_RXC_ALLOCT,val)
-#define bfin_read_EMAC_RXC_TYPED()           bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val)       bfin_write32(EMAC_RXC_TYPED,val)
-#define bfin_read_EMAC_RXC_SHORT()           bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val)       bfin_write32(EMAC_RXC_SHORT,val)
-#define bfin_read_EMAC_RXC_EQ64()            bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)        bfin_write32(EMAC_RXC_EQ64,val)
-#define bfin_read_EMAC_RXC_LT128()           bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val)       bfin_write32(EMAC_RXC_LT128,val)
-#define bfin_read_EMAC_RXC_LT256()           bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val)       bfin_write32(EMAC_RXC_LT256,val)
-#define bfin_read_EMAC_RXC_LT512()           bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val)       bfin_write32(EMAC_RXC_LT512,val)
-#define bfin_read_EMAC_RXC_LT1024()          bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val)      bfin_write32(EMAC_RXC_LT1024,val)
-#define bfin_read_EMAC_RXC_GE1024()          bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val)      bfin_write32(EMAC_RXC_GE1024,val)
-
-#define bfin_read_EMAC_TXC_OK()              bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)          bfin_write32(EMAC_TXC_OK,val)
-#define bfin_read_EMAC_TXC_1COL()            bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)        bfin_write32(EMAC_TXC_1COL,val)
-#define bfin_read_EMAC_TXC_GT1COL()          bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val)      bfin_write32(EMAC_TXC_GT1COL,val)
-#define bfin_read_EMAC_TXC_OCTET()           bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val)       bfin_write32(EMAC_TXC_OCTET,val)
-#define bfin_read_EMAC_TXC_DEFER()           bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val)       bfin_write32(EMAC_TXC_DEFER,val)
-#define bfin_read_EMAC_TXC_LATECL()          bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val)      bfin_write32(EMAC_TXC_LATECL,val)
-#define bfin_read_EMAC_TXC_XS_COL()          bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val)      bfin_write32(EMAC_TXC_XS_COL,val)
-#define bfin_read_EMAC_TXC_DMAUND()          bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val)      bfin_write32(EMAC_TXC_DMAUND,val)
-#define bfin_read_EMAC_TXC_CRSERR()          bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val)      bfin_write32(EMAC_TXC_CRSERR,val)
-#define bfin_read_EMAC_TXC_UNICST()          bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val)      bfin_write32(EMAC_TXC_UNICST,val)
-#define bfin_read_EMAC_TXC_MULTI()           bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val)       bfin_write32(EMAC_TXC_MULTI,val)
-#define bfin_read_EMAC_TXC_BROAD()           bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val)       bfin_write32(EMAC_TXC_BROAD,val)
-#define bfin_read_EMAC_TXC_XS_DFR()          bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val)      bfin_write32(EMAC_TXC_XS_DFR,val)
-#define bfin_read_EMAC_TXC_MACCTL()          bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val)      bfin_write32(EMAC_TXC_MACCTL,val)
-#define bfin_read_EMAC_TXC_ALLFRM()          bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val)      bfin_write32(EMAC_TXC_ALLFRM,val)
-#define bfin_read_EMAC_TXC_ALLOCT()          bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val)      bfin_write32(EMAC_TXC_ALLOCT,val)
-#define bfin_read_EMAC_TXC_EQ64()            bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)        bfin_write32(EMAC_TXC_EQ64,val)
-#define bfin_read_EMAC_TXC_LT128()           bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val)       bfin_write32(EMAC_TXC_LT128,val)
-#define bfin_read_EMAC_TXC_LT256()           bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val)       bfin_write32(EMAC_TXC_LT256,val)
-#define bfin_read_EMAC_TXC_LT512()           bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val)       bfin_write32(EMAC_TXC_LT512,val)
-#define bfin_read_EMAC_TXC_LT1024()          bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val)      bfin_write32(EMAC_TXC_LT1024,val)
-#define bfin_read_EMAC_TXC_GE1024()          bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val)      bfin_write32(EMAC_TXC_GE1024,val)
-#define bfin_read_EMAC_TXC_ABORT()           bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val)       bfin_write32(EMAC_TXC_ABORT,val)
-
-#endif                          /* _CDEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
deleted file mode 100644
index d0d80d3152ba..000000000000
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ /dev/null
@@ -1,2527 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID                          0xFFC00014      /* Chip ID Register                                             */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
-#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
-#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register                            */
-#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register                            */
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                                               */
-/* For Mailboxes 0-15                                                                                                                                   */
-#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1                                                 */
-#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1                                              */
-#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1                                   */
-#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1                                 */
-#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1                                   */
-#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1                             */
-#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1                                */
-#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1                                   */
-#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1                */
-#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1                */
-#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1                                 */
-#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1                                  */
-#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmit reg 1  */
-
-/* For Mailboxes 16-31                                                                                                                                  */
-#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2                                                 */
-#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2                                              */
-#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2                                   */
-#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2                                 */
-#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2                                   */
-#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2                             */
-#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2                                */
-#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2                                   */
-#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2                */
-#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2                */
-#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2                                 */
-#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2                                  */
-#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmit reg 2  */
-
-/* CAN Configuration, Control, and Status Registers                                                                             */
-#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0                  */
-#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1                  */
-#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                                                               */
-#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register                                               */
-#define CAN_CEC                         0xFFC02A90      /* Error Counter Register                                               */
-#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register                             */
-#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register                               */
-#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register                               */
-#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register                                              */
-#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register                                   */
-
-#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature                    */
-#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level                                   */
-#define CAN_ESR                         0xFFC02AB4      /* Error Status Register                                                */
-#define CAN_UCREG                       0xFFC02AC0      /* Universal Counter Register/Capture Register  */
-#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter                                                    */
-#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Force Reload Register              */
-#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register             */
-
-/* Mailbox Acceptance Masks                                                                                             */
-#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask        */
-#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask       */
-#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask        */
-#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask       */
-#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask        */
-#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask       */
-#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask        */
-#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask       */
-#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask        */
-#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask       */
-#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask        */
-#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask       */
-#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask        */
-#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask       */
-#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask        */
-#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask       */
-#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask        */
-#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask       */
-#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask        */
-#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask       */
-#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask       */
-#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask      */
-#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask       */
-#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask      */
-#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask       */
-#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask      */
-#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask       */
-#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask      */
-#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask       */
-#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask      */
-#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask       */
-#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask      */
-
-#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask       */
-#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask      */
-#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask       */
-#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask      */
-#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask       */
-#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask      */
-#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask       */
-#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask      */
-#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask       */
-#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask      */
-#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask       */
-#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask      */
-#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask       */
-#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask      */
-#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask       */
-#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask      */
-#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask       */
-#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask      */
-#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask       */
-#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask      */
-#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask       */
-#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask      */
-#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask       */
-#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask      */
-#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask       */
-#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask      */
-#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask       */
-#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask      */
-#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask       */
-#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask      */
-#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask       */
-#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask      */
-
-/* CAN Acceptance Mask Macros                           */
-#define CAN_AM_L(x)             (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)             (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers                                                                                                                            */
-#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register        */
-#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register       */
-#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register       */
-#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register       */
-#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register          */
-#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register          */
-#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register            */
-#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register           */
-
-#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register        */
-#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register       */
-#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register       */
-#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register       */
-#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register          */
-#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register          */
-#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register            */
-#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register           */
-
-#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register        */
-#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register       */
-#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register       */
-#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register       */
-#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register          */
-#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register          */
-#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register            */
-#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register           */
-
-#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register        */
-#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register       */
-#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register       */
-#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register       */
-#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register          */
-#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register          */
-#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register            */
-#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register           */
-
-#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register        */
-#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register       */
-#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register       */
-#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register       */
-#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register          */
-#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register          */
-#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register            */
-#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register           */
-
-#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register        */
-#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register       */
-#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register       */
-#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register       */
-#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register          */
-#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register          */
-#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register            */
-#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register           */
-
-#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register        */
-#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register       */
-#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register       */
-#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register       */
-#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register          */
-#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register          */
-#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register            */
-#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register           */
-
-#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register        */
-#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register       */
-#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register       */
-#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register       */
-#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register          */
-#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register          */
-#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register            */
-#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register           */
-
-#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register        */
-#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register       */
-#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register       */
-#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register       */
-#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register          */
-#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register          */
-#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register            */
-#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register           */
-
-#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register        */
-#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register       */
-#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register       */
-#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register       */
-#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register          */
-#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register          */
-#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register            */
-#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register           */
-
-#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register       */
-#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register      */
-#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register      */
-#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register      */
-#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register         */
-#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register         */
-#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register           */
-#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register          */
-
-#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register       */
-#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register      */
-#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register      */
-#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register      */
-#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register         */
-#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register         */
-#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register           */
-#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register          */
-
-#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register       */
-#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register      */
-#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register      */
-#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register      */
-#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register         */
-#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register         */
-#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register           */
-#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register          */
-
-#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register       */
-#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register      */
-#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register      */
-#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register      */
-#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register         */
-#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register         */
-#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register           */
-#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register          */
-
-#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register       */
-#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register      */
-#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register      */
-#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register      */
-#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register         */
-#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register         */
-#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register           */
-#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register          */
-
-#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register       */
-#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register      */
-#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register      */
-#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register      */
-#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register         */
-#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register         */
-#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register           */
-#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register          */
-
-#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register       */
-#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register      */
-#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register      */
-#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register      */
-#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register         */
-#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register         */
-#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register           */
-#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register          */
-
-#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register       */
-#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register      */
-#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register      */
-#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register      */
-#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register         */
-#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register         */
-#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register           */
-#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register          */
-
-#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register       */
-#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register      */
-#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register      */
-#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register      */
-#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register         */
-#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register         */
-#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register           */
-#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register          */
-
-#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register       */
-#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register      */
-#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register      */
-#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register      */
-#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register         */
-#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register         */
-#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register           */
-#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register          */
-
-#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register       */
-#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register      */
-#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register      */
-#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register      */
-#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register         */
-#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register         */
-#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register           */
-#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register          */
-
-#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register       */
-#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register      */
-#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register      */
-#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register      */
-#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register         */
-#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register         */
-#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register           */
-#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register          */
-
-#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register       */
-#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register      */
-#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register      */
-#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register      */
-#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register         */
-#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register         */
-#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register           */
-#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register          */
-
-#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register       */
-#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register      */
-#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register      */
-#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register      */
-#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register         */
-#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register         */
-#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register           */
-#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register          */
-
-#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register       */
-#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register      */
-#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register      */
-#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register      */
-#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register         */
-#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register         */
-#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register           */
-#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register          */
-
-#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register       */
-#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register      */
-#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register      */
-#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register      */
-#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register         */
-#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register         */
-#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register           */
-#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register          */
-
-#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register       */
-#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register      */
-#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register      */
-#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register      */
-#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register         */
-#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register         */
-#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register           */
-#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register          */
-
-#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register       */
-#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register      */
-#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register      */
-#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register      */
-#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register         */
-#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register         */
-#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register           */
-#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register          */
-
-#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register       */
-#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register      */
-#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register      */
-#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register      */
-#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register         */
-#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register         */
-#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register           */
-#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register          */
-
-#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register       */
-#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register      */
-#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register      */
-#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register      */
-#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register         */
-#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register         */
-#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register           */
-#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register          */
-
-#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register       */
-#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register      */
-#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register      */
-#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register      */
-#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register         */
-#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register         */
-#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register           */
-#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register          */
-
-#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register       */
-#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register      */
-#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register      */
-#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register      */
-#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register         */
-#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register         */
-#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register           */
-#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register          */
-
-/* CAN Mailbox Area Macros                              */
-#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
-#define STB                     0x04    /* Stop Bits                    */
-#define PEN                     0x08    /* Parity Enable                */
-#define EPS                     0x10    /* Even Parity Select   */
-#define STP                     0x20    /* Stick Parity                 */
-#define SB                      0x40    /* Set Break                    */
-#define DLAB            0x80    /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA                0x10    /* Loopback Mode Enable         */
-#define LOOP_ENA_P      0x04
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04    /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01    /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01    /* Enable UARTx Clocks                          */
-#define IREN            0x02    /* Enable IrDA Mode                                     */
-#define TPOLC           0x04    /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08    /* IrDA RX Polarity Change                      */
-#define FPE                     0x10    /* Force Parity Error On Transmit       */
-#define FFE                     0x20    /* Force Framing Error On Transmit      */
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks                                                                                                                                        */
-#define TIMOD           0x0003  /* Transfer Initiate Mode                                                       */
-#define RDBR_CORE       0x0000  /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define TDBR_CORE       0x0001  /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA        0x0002  /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA        0x0003  /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                      0x0004  /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
-#define GM                      0x0008  /* Get More (When RDBR Full, Overwrite/Discard*)        */
-#define PSSE            0x0010  /* Slave-Select Input Enable                                            */
-#define EMISO           0x0020  /* Enable MISO As Output                                                        */
-#define SIZE            0x0100  /* Size of Words (16/8* Bits)                                           */
-#define LSBF            0x0200  /* LSB First                                                                            */
-#define CPHA            0x0400  /* Clock Phase                                                                          */
-#define CPOL            0x0800  /* Clock Polarity                                                                       */
-#define MSTR            0x1000  /* Master/Slave*                                                                        */
-#define WOM                     0x2000  /* Write Open Drain Master                                                      */
-#define SPE                     0x4000  /* SPI Enable                                                                           */
-
-/* SPI_FLG Masks                                                                                                                                        */
-#define FLS1            0x0002  /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
-#define FLS2            0x0004  /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
-#define FLS3            0x0008  /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
-#define FLS4            0x0010  /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
-#define FLS5            0x0020  /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
-#define FLS6            0x0040  /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
-#define FLS7            0x0080  /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
-#define FLG1            0xFDFF  /* Activates SPI_FLOUT1                                                         */
-#define FLG2            0xFBFF  /* Activates SPI_FLOUT2                                                         */
-#define FLG3            0xF7FF  /* Activates SPI_FLOUT3                                                         */
-#define FLG4            0xEFFF  /* Activates SPI_FLOUT4                                                         */
-#define FLG5            0xDFFF  /* Activates SPI_FLOUT5                                                         */
-#define FLG6            0xBFFF  /* Activates SPI_FLOUT6                                                         */
-#define FLG7            0x7FFF  /* Activates SPI_FLOUT7                                                         */
-
-/* SPI_STAT Masks                                                                                                                                                               */
-#define SPIF            0x0001  /* SPI Finished (Single-Word Transfer Complete)                                 */
-#define MODF            0x0002  /* Mode Fault Error (Another Device Tried To Become Master)             */
-#define TXE                     0x0004  /* Transmission Error (Data Sent With No New Data In TDBR)              */
-#define TXS                     0x0008  /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
-#define RBSY            0x0010  /* Receive Error (Data Received With RDBR Full)                                 */
-#define RXS                     0x0020  /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
-#define TXCOL           0x0040  /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001  /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002  /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004  /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008  /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010  /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020  /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040  /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080  /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0  /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1  /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2  /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3  /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4  /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5  /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6  /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7  /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001  /* Transmit Enable                                                              */
-#define ITCLK           0x0002  /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010  /* Transmit Bit Order                                                   */
-#define ITFS            0x0200  /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400  /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800  /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000  /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000  /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000  /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100  /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200  /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400  /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001  /* Receive Enable                                                               */
-#define IRCLK           0x0002  /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010  /* Receive Bit Order                                                    */
-#define IRFS            0x0200  /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400  /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000  /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000  /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000  /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100  /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200  /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400  /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001  /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002  /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004  /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008  /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010  /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020  /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040  /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)              ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010  /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000  /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000  /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000  /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000  /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000  /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000  /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000  /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000  /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000  /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000  /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000  /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000  /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000  /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000  /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000  /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000  /* Multichannel Frame Delay = 15                                */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000  /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002  /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004  /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008  /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001      /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002      /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004      /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008      /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C      /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000      /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010      /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020      /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030      /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000      /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040      /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080      /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0      /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000      /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100      /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200      /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300      /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400      /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500      /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600      /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700      /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800      /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900      /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00      /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00      /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00      /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00      /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00      /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00      /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000      /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000      /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000      /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000      /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000      /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000      /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000      /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000      /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000      /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000      /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000      /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000      /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000      /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000      /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000      /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000      /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000      /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000      /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000      /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000      /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000      /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000      /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000      /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000      /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000      /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000      /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000      /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000      /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000      /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000      /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000      /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000      /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000      /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000      /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000      /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000      /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000      /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000      /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000      /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000      /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000      /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000      /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000      /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000      /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000      /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000      /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000      /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000      /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000      /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000      /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000      /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000      /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000      /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000      /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000      /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000      /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000      /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000      /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000      /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001      /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002      /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004      /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008      /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C      /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000      /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010      /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020      /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030      /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000      /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040      /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080      /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0      /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000      /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100      /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200      /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300      /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400      /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500      /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600      /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700      /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800      /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900      /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00      /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00      /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00      /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00      /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00      /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00      /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000      /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000      /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000      /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000      /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000      /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000      /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000      /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000      /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000      /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000      /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000      /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000      /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000      /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000      /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000      /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000      /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000      /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000      /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000      /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000      /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000      /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000      /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000      /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000      /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000      /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000      /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000      /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000      /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000      /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000      /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000      /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000      /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000      /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000      /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000      /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000      /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000      /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000      /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000      /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000      /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000      /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000      /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000      /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000      /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000      /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000      /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000      /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000      /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000      /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000      /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000      /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000      /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000      /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000      /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000      /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000      /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000      /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000      /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000      /* B3 Write Access Time = 15 cycles                                 */
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001  /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000  /* SDRAM External Bank Size = 16MB                                              */
-#define EBSZ_32                 0x0002  /* SDRAM External Bank Size = 32MB                                              */
-#define EBSZ_64                 0x0004  /* SDRAM External Bank Size = 64MB                                              */
-#define EBSZ_128                0x0006  /* SDRAM External Bank Size = 128MB                                             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000  /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010  /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020  /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030  /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001  /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002  /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004  /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008  /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010  /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020  /* Bus Grant Status                                             */
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001  /* DMA Channel Enable                                                   */
-#define WNR                             0x0002  /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000  /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004  /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008  /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010  /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020  /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040  /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080  /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001  /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002  /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C  /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030  /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040  /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080  /* PPI Packing Mode                                     */
-#define DMA32                   0x0100  /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200  /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400  /* PPI Skip Even/Odd Elements           */
-#define DLENGTH         0x3800  /* PPI Data Length  */
-#define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
-#define POLC                    0x4000  /* PPI Clock Polarity                           */
-#define POLS                    0x8000  /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400  /* Field Indicator                                      */
-#define FT_ERR                  0x0800  /* Frame Track Error                            */
-#define OVR                             0x1000  /* FIFO Overflow Error                          */
-#define UNDR                    0x2000  /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000  /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000  /* Error Not Corrected Indicator        */
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
-#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTRL Masks                                                                                                                 */
-#define SEN                     0x0001  /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
-#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010  /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002  /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTRL Masks                                                                                                        */
-#define MEN                     0x0001  /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002  /* Master Address Length                                        */
-#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010  /* Issue Stop Condition                                         */
-#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000  /* Serial Data Override                                         */
-#define SCLOVR          0x8000  /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001  /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004  /* Address Not Acknowledged                                             */
-#define DNAK            0x0008  /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
-#define SDASEN          0x0040  /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001  /* Slave Transfer Initiated     */
-#define SCOMP           0x0002  /* Slave Transfer Complete      */
-#define SERR            0x0004  /* Slave Transfer Error         */
-#define SOVF            0x0008  /* Slave Overflow                       */
-#define MCOMP           0x0010  /* Master Transfer Complete     */
-#define MERR            0x0020  /* Master Transfer Error        */
-#define XMTSERV         0x0040  /* Transmit FIFO Service        */
-#define RCVSERV         0x0080  /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
-
-/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
-/* CAN_CONTROL Masks                                                                                            */
-#define SRS                     0x0001  /* Software Reset                                               */
-#define DNM                     0x0002  /* Device Net Mode                                              */
-#define ABO                     0x0004  /* Auto-Bus On Enable                                   */
-#define TXPRIO          0x0008  /* TX Priority (Priority/Mailbox*)              */
-#define WBA                     0x0010  /* Wake-Up On CAN Bus Activity Enable   */
-#define SMR                     0x0020  /* Sleep Mode Request                                   */
-#define CSR                     0x0040  /* CAN Suspend Mode Request                             */
-#define CCR                     0x0080  /* CAN Configuration Mode Request               */
-
-/* CAN_STATUS Masks                                                                                             */
-#define WT                      0x0001  /* TX Warning Flag                                      */
-#define WR                      0x0002  /* RX Warning Flag                                      */
-#define EP                      0x0004  /* Error Passive Mode                           */
-#define EBO                     0x0008  /* Error Bus Off Mode                           */
-#define SMA                     0x0020  /* Sleep Mode Acknowledge                       */
-#define CSA                     0x0040  /* Suspend Mode Acknowledge                     */
-#define CCA                     0x0080  /* Configuration Mode Acknowledge       */
-#define MBPTR           0x1F00  /* Mailbox Pointer                                      */
-#define TRM                     0x4000  /* Transmit Mode                                        */
-#define REC                     0x8000  /* Receive Mode                                         */
-
-/* CAN_CLOCK Masks                                                                      */
-#define BRP                     0x03FF  /* Bit-Rate Pre-Scaler  */
-
-/* CAN_TIMING Masks                                                                                     */
-#define TSEG1           0x000F  /* Time Segment 1                               */
-#define TSEG2           0x0070  /* Time Segment 2                               */
-#define SAM                     0x0080  /* Sampling                                             */
-#define SJW                     0x0300  /* Synchronization Jump Width   */
-
-/* CAN_DEBUG Masks                                                                                      */
-#define DEC                     0x0001  /* Disable CAN Error Counters   */
-#define DRI                     0x0002  /* Disable CAN RX Input                 */
-#define DTO                     0x0004  /* Disable CAN TX Output                */
-#define DIL                     0x0008  /* Disable CAN Internal Loop    */
-#define MAA                     0x0010  /* Mode Auto-Acknowledge Enable */
-#define MRB                     0x0020  /* Mode Read Back Enable                */
-#define CDE                     0x8000  /* CAN Debug Enable                             */
-
-/* CAN_CEC Masks                                                                                */
-#define RXECNT          0x00FF  /* Receive Error Counter        */
-#define TXECNT          0xFF00  /* Transmit Error Counter       */
-
-/* CAN_INTR Masks                                                                                       */
-#define MBRIRQ  0x0001  /* Mailbox Receive Interrupt    */
-#define MBRIF           MBRIRQ  /* legacy */
-#define MBTIRQ  0x0002  /* Mailbox Transmit Interrupt   */
-#define MBTIF           MBTIRQ  /* legacy */
-#define GIRQ            0x0004  /* Global Interrupt                             */
-#define SMACK           0x0008  /* Sleep Mode Acknowledge               */
-#define CANTX           0x0040  /* CAN TX Bus Value                             */
-#define CANRX           0x0080  /* CAN RX Bus Value                             */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks                                                                          */
-#define DFC                     0xFFFF  /* Data Filtering Code (If Enabled) (ID0)               */
-#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (ID0)   */
-#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (ID1)    */
-#define BASEID          0x1FFC  /* Base Identifier                                                              */
-#define IDE                     0x2000  /* Identifier Extension                                                 */
-#define RTR                     0x4000  /* Remote Frame Transmission Request                    */
-#define AME                     0x8000  /* Acceptance Mask Enable                                               */
-
-/* CAN_MBxx_TIMESTAMP Masks                                     */
-#define TSV                     0xFFFF  /* Timestamp    */
-
-/* CAN_MBxx_LENGTH Masks                                                */
-#define DLC                     0x000F  /* Data Length Code     */
-
-/* CAN_AMxxH and CAN_AMxxL Masks                                                                                                */
-#define DFM                     0xFFFF  /* Data Field Mask (If Enabled) (CAN_AMxxL)                     */
-#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (CAN_AMxxL)     */
-#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (CAN_AMxxH)      */
-#define BASEID          0x1FFC  /* Base Identifier                                                                      */
-#define AMIDE           0x2000  /* Acceptance Mask ID Extension Enable                          */
-#define FMD                     0x4000  /* Full Mask Data Field Enable                                          */
-#define FDF                     0x8000  /* Filter On Data Field Enable                                          */
-
-/* CAN_MC1 Masks                                                                        */
-#define MC0                     0x0001  /* Enable Mailbox 0             */
-#define MC1                     0x0002  /* Enable Mailbox 1             */
-#define MC2                     0x0004  /* Enable Mailbox 2             */
-#define MC3                     0x0008  /* Enable Mailbox 3             */
-#define MC4                     0x0010  /* Enable Mailbox 4             */
-#define MC5                     0x0020  /* Enable Mailbox 5             */
-#define MC6                     0x0040  /* Enable Mailbox 6             */
-#define MC7                     0x0080  /* Enable Mailbox 7             */
-#define MC8                     0x0100  /* Enable Mailbox 8             */
-#define MC9                     0x0200  /* Enable Mailbox 9             */
-#define MC10            0x0400  /* Enable Mailbox 10    */
-#define MC11            0x0800  /* Enable Mailbox 11    */
-#define MC12            0x1000  /* Enable Mailbox 12    */
-#define MC13            0x2000  /* Enable Mailbox 13    */
-#define MC14            0x4000  /* Enable Mailbox 14    */
-#define MC15            0x8000  /* Enable Mailbox 15    */
-
-/* CAN_MC2 Masks                                                                        */
-#define MC16            0x0001  /* Enable Mailbox 16    */
-#define MC17            0x0002  /* Enable Mailbox 17    */
-#define MC18            0x0004  /* Enable Mailbox 18    */
-#define MC19            0x0008  /* Enable Mailbox 19    */
-#define MC20            0x0010  /* Enable Mailbox 20    */
-#define MC21            0x0020  /* Enable Mailbox 21    */
-#define MC22            0x0040  /* Enable Mailbox 22    */
-#define MC23            0x0080  /* Enable Mailbox 23    */
-#define MC24            0x0100  /* Enable Mailbox 24    */
-#define MC25            0x0200  /* Enable Mailbox 25    */
-#define MC26            0x0400  /* Enable Mailbox 26    */
-#define MC27            0x0800  /* Enable Mailbox 27    */
-#define MC28            0x1000  /* Enable Mailbox 28    */
-#define MC29            0x2000  /* Enable Mailbox 29    */
-#define MC30            0x4000  /* Enable Mailbox 30    */
-#define MC31            0x8000  /* Enable Mailbox 31    */
-
-/* CAN_MD1 Masks                                                                                                */
-#define MD0                     0x0001  /* Enable Mailbox 0 For Receive         */
-#define MD1                     0x0002  /* Enable Mailbox 1 For Receive         */
-#define MD2                     0x0004  /* Enable Mailbox 2 For Receive         */
-#define MD3                     0x0008  /* Enable Mailbox 3 For Receive         */
-#define MD4                     0x0010  /* Enable Mailbox 4 For Receive         */
-#define MD5                     0x0020  /* Enable Mailbox 5 For Receive         */
-#define MD6                     0x0040  /* Enable Mailbox 6 For Receive         */
-#define MD7                     0x0080  /* Enable Mailbox 7 For Receive         */
-#define MD8                     0x0100  /* Enable Mailbox 8 For Receive         */
-#define MD9                     0x0200  /* Enable Mailbox 9 For Receive         */
-#define MD10            0x0400  /* Enable Mailbox 10 For Receive        */
-#define MD11            0x0800  /* Enable Mailbox 11 For Receive        */
-#define MD12            0x1000  /* Enable Mailbox 12 For Receive        */
-#define MD13            0x2000  /* Enable Mailbox 13 For Receive        */
-#define MD14            0x4000  /* Enable Mailbox 14 For Receive        */
-#define MD15            0x8000  /* Enable Mailbox 15 For Receive        */
-
-/* CAN_MD2 Masks                                                                                                */
-#define MD16            0x0001  /* Enable Mailbox 16 For Receive        */
-#define MD17            0x0002  /* Enable Mailbox 17 For Receive        */
-#define MD18            0x0004  /* Enable Mailbox 18 For Receive        */
-#define MD19            0x0008  /* Enable Mailbox 19 For Receive        */
-#define MD20            0x0010  /* Enable Mailbox 20 For Receive        */
-#define MD21            0x0020  /* Enable Mailbox 21 For Receive        */
-#define MD22            0x0040  /* Enable Mailbox 22 For Receive        */
-#define MD23            0x0080  /* Enable Mailbox 23 For Receive        */
-#define MD24            0x0100  /* Enable Mailbox 24 For Receive        */
-#define MD25            0x0200  /* Enable Mailbox 25 For Receive        */
-#define MD26            0x0400  /* Enable Mailbox 26 For Receive        */
-#define MD27            0x0800  /* Enable Mailbox 27 For Receive        */
-#define MD28            0x1000  /* Enable Mailbox 28 For Receive        */
-#define MD29            0x2000  /* Enable Mailbox 29 For Receive        */
-#define MD30            0x4000  /* Enable Mailbox 30 For Receive        */
-#define MD31            0x8000  /* Enable Mailbox 31 For Receive        */
-
-/* CAN_RMP1 Masks                                                                                               */
-#define RMP0            0x0001  /* RX Message Pending In Mailbox 0      */
-#define RMP1            0x0002  /* RX Message Pending In Mailbox 1      */
-#define RMP2            0x0004  /* RX Message Pending In Mailbox 2      */
-#define RMP3            0x0008  /* RX Message Pending In Mailbox 3      */
-#define RMP4            0x0010  /* RX Message Pending In Mailbox 4      */
-#define RMP5            0x0020  /* RX Message Pending In Mailbox 5      */
-#define RMP6            0x0040  /* RX Message Pending In Mailbox 6      */
-#define RMP7            0x0080  /* RX Message Pending In Mailbox 7      */
-#define RMP8            0x0100  /* RX Message Pending In Mailbox 8      */
-#define RMP9            0x0200  /* RX Message Pending In Mailbox 9      */
-#define RMP10           0x0400  /* RX Message Pending In Mailbox 10     */
-#define RMP11           0x0800  /* RX Message Pending In Mailbox 11     */
-#define RMP12           0x1000  /* RX Message Pending In Mailbox 12     */
-#define RMP13           0x2000  /* RX Message Pending In Mailbox 13     */
-#define RMP14           0x4000  /* RX Message Pending In Mailbox 14     */
-#define RMP15           0x8000  /* RX Message Pending In Mailbox 15     */
-
-/* CAN_RMP2 Masks                                                                                               */
-#define RMP16           0x0001  /* RX Message Pending In Mailbox 16     */
-#define RMP17           0x0002  /* RX Message Pending In Mailbox 17     */
-#define RMP18           0x0004  /* RX Message Pending In Mailbox 18     */
-#define RMP19           0x0008  /* RX Message Pending In Mailbox 19     */
-#define RMP20           0x0010  /* RX Message Pending In Mailbox 20     */
-#define RMP21           0x0020  /* RX Message Pending In Mailbox 21     */
-#define RMP22           0x0040  /* RX Message Pending In Mailbox 22     */
-#define RMP23           0x0080  /* RX Message Pending In Mailbox 23     */
-#define RMP24           0x0100  /* RX Message Pending In Mailbox 24     */
-#define RMP25           0x0200  /* RX Message Pending In Mailbox 25     */
-#define RMP26           0x0400  /* RX Message Pending In Mailbox 26     */
-#define RMP27           0x0800  /* RX Message Pending In Mailbox 27     */
-#define RMP28           0x1000  /* RX Message Pending In Mailbox 28     */
-#define RMP29           0x2000  /* RX Message Pending In Mailbox 29     */
-#define RMP30           0x4000  /* RX Message Pending In Mailbox 30     */
-#define RMP31           0x8000  /* RX Message Pending In Mailbox 31     */
-
-/* CAN_RML1 Masks                                                                                               */
-#define RML0            0x0001  /* RX Message Lost In Mailbox 0         */
-#define RML1            0x0002  /* RX Message Lost In Mailbox 1         */
-#define RML2            0x0004  /* RX Message Lost In Mailbox 2         */
-#define RML3            0x0008  /* RX Message Lost In Mailbox 3         */
-#define RML4            0x0010  /* RX Message Lost In Mailbox 4         */
-#define RML5            0x0020  /* RX Message Lost In Mailbox 5         */
-#define RML6            0x0040  /* RX Message Lost In Mailbox 6         */
-#define RML7            0x0080  /* RX Message Lost In Mailbox 7         */
-#define RML8            0x0100  /* RX Message Lost In Mailbox 8         */
-#define RML9            0x0200  /* RX Message Lost In Mailbox 9         */
-#define RML10           0x0400  /* RX Message Lost In Mailbox 10        */
-#define RML11           0x0800  /* RX Message Lost In Mailbox 11        */
-#define RML12           0x1000  /* RX Message Lost In Mailbox 12        */
-#define RML13           0x2000  /* RX Message Lost In Mailbox 13        */
-#define RML14           0x4000  /* RX Message Lost In Mailbox 14        */
-#define RML15           0x8000  /* RX Message Lost In Mailbox 15        */
-
-/* CAN_RML2 Masks                                                                                               */
-#define RML16           0x0001  /* RX Message Lost In Mailbox 16        */
-#define RML17           0x0002  /* RX Message Lost In Mailbox 17        */
-#define RML18           0x0004  /* RX Message Lost In Mailbox 18        */
-#define RML19           0x0008  /* RX Message Lost In Mailbox 19        */
-#define RML20           0x0010  /* RX Message Lost In Mailbox 20        */
-#define RML21           0x0020  /* RX Message Lost In Mailbox 21        */
-#define RML22           0x0040  /* RX Message Lost In Mailbox 22        */
-#define RML23           0x0080  /* RX Message Lost In Mailbox 23        */
-#define RML24           0x0100  /* RX Message Lost In Mailbox 24        */
-#define RML25           0x0200  /* RX Message Lost In Mailbox 25        */
-#define RML26           0x0400  /* RX Message Lost In Mailbox 26        */
-#define RML27           0x0800  /* RX Message Lost In Mailbox 27        */
-#define RML28           0x1000  /* RX Message Lost In Mailbox 28        */
-#define RML29           0x2000  /* RX Message Lost In Mailbox 29        */
-#define RML30           0x4000  /* RX Message Lost In Mailbox 30        */
-#define RML31           0x8000  /* RX Message Lost In Mailbox 31        */
-
-/* CAN_OPSS1 Masks                                                                                                                                                              */
-#define OPSS0           0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0       */
-#define OPSS1           0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1       */
-#define OPSS2           0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2       */
-#define OPSS3           0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3       */
-#define OPSS4           0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4       */
-#define OPSS5           0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5       */
-#define OPSS6           0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6       */
-#define OPSS7           0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7       */
-#define OPSS8           0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8       */
-#define OPSS9           0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9       */
-#define OPSS10          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10      */
-#define OPSS11          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11      */
-#define OPSS12          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12      */
-#define OPSS13          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13      */
-#define OPSS14          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14      */
-#define OPSS15          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15      */
-
-/* CAN_OPSS2 Masks                                                                                                                                                              */
-#define OPSS16          0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16      */
-#define OPSS17          0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17      */
-#define OPSS18          0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18      */
-#define OPSS19          0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19      */
-#define OPSS20          0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20      */
-#define OPSS21          0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21      */
-#define OPSS22          0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22      */
-#define OPSS23          0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23      */
-#define OPSS24          0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24      */
-#define OPSS25          0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25      */
-#define OPSS26          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26      */
-#define OPSS27          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27      */
-#define OPSS28          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28      */
-#define OPSS29          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29      */
-#define OPSS30          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30      */
-#define OPSS31          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31      */
-
-/* CAN_TRR1 Masks                                                                                                               */
-#define TRR0            0x0001  /* Deny But Don't Lock Access To Mailbox 0      */
-#define TRR1            0x0002  /* Deny But Don't Lock Access To Mailbox 1      */
-#define TRR2            0x0004  /* Deny But Don't Lock Access To Mailbox 2      */
-#define TRR3            0x0008  /* Deny But Don't Lock Access To Mailbox 3      */
-#define TRR4            0x0010  /* Deny But Don't Lock Access To Mailbox 4      */
-#define TRR5            0x0020  /* Deny But Don't Lock Access To Mailbox 5      */
-#define TRR6            0x0040  /* Deny But Don't Lock Access To Mailbox 6      */
-#define TRR7            0x0080  /* Deny But Don't Lock Access To Mailbox 7      */
-#define TRR8            0x0100  /* Deny But Don't Lock Access To Mailbox 8      */
-#define TRR9            0x0200  /* Deny But Don't Lock Access To Mailbox 9      */
-#define TRR10           0x0400  /* Deny But Don't Lock Access To Mailbox 10     */
-#define TRR11           0x0800  /* Deny But Don't Lock Access To Mailbox 11     */
-#define TRR12           0x1000  /* Deny But Don't Lock Access To Mailbox 12     */
-#define TRR13           0x2000  /* Deny But Don't Lock Access To Mailbox 13     */
-#define TRR14           0x4000  /* Deny But Don't Lock Access To Mailbox 14     */
-#define TRR15           0x8000  /* Deny But Don't Lock Access To Mailbox 15     */
-
-/* CAN_TRR2 Masks                                                                                                               */
-#define TRR16           0x0001  /* Deny But Don't Lock Access To Mailbox 16     */
-#define TRR17           0x0002  /* Deny But Don't Lock Access To Mailbox 17     */
-#define TRR18           0x0004  /* Deny But Don't Lock Access To Mailbox 18     */
-#define TRR19           0x0008  /* Deny But Don't Lock Access To Mailbox 19     */
-#define TRR20           0x0010  /* Deny But Don't Lock Access To Mailbox 20     */
-#define TRR21           0x0020  /* Deny But Don't Lock Access To Mailbox 21     */
-#define TRR22           0x0040  /* Deny But Don't Lock Access To Mailbox 22     */
-#define TRR23           0x0080  /* Deny But Don't Lock Access To Mailbox 23     */
-#define TRR24           0x0100  /* Deny But Don't Lock Access To Mailbox 24     */
-#define TRR25           0x0200  /* Deny But Don't Lock Access To Mailbox 25     */
-#define TRR26           0x0400  /* Deny But Don't Lock Access To Mailbox 26     */
-#define TRR27           0x0800  /* Deny But Don't Lock Access To Mailbox 27     */
-#define TRR28           0x1000  /* Deny But Don't Lock Access To Mailbox 28     */
-#define TRR29           0x2000  /* Deny But Don't Lock Access To Mailbox 29     */
-#define TRR30           0x4000  /* Deny But Don't Lock Access To Mailbox 30     */
-#define TRR31           0x8000  /* Deny But Don't Lock Access To Mailbox 31     */
-
-/* CAN_TRS1 Masks                                                                                                       */
-#define TRS0            0x0001  /* Remote Frame Request For Mailbox 0   */
-#define TRS1            0x0002  /* Remote Frame Request For Mailbox 1   */
-#define TRS2            0x0004  /* Remote Frame Request For Mailbox 2   */
-#define TRS3            0x0008  /* Remote Frame Request For Mailbox 3   */
-#define TRS4            0x0010  /* Remote Frame Request For Mailbox 4   */
-#define TRS5            0x0020  /* Remote Frame Request For Mailbox 5   */
-#define TRS6            0x0040  /* Remote Frame Request For Mailbox 6   */
-#define TRS7            0x0080  /* Remote Frame Request For Mailbox 7   */
-#define TRS8            0x0100  /* Remote Frame Request For Mailbox 8   */
-#define TRS9            0x0200  /* Remote Frame Request For Mailbox 9   */
-#define TRS10           0x0400  /* Remote Frame Request For Mailbox 10  */
-#define TRS11           0x0800  /* Remote Frame Request For Mailbox 11  */
-#define TRS12           0x1000  /* Remote Frame Request For Mailbox 12  */
-#define TRS13           0x2000  /* Remote Frame Request For Mailbox 13  */
-#define TRS14           0x4000  /* Remote Frame Request For Mailbox 14  */
-#define TRS15           0x8000  /* Remote Frame Request For Mailbox 15  */
-
-/* CAN_TRS2 Masks                                                                                                       */
-#define TRS16           0x0001  /* Remote Frame Request For Mailbox 16  */
-#define TRS17           0x0002  /* Remote Frame Request For Mailbox 17  */
-#define TRS18           0x0004  /* Remote Frame Request For Mailbox 18  */
-#define TRS19           0x0008  /* Remote Frame Request For Mailbox 19  */
-#define TRS20           0x0010  /* Remote Frame Request For Mailbox 20  */
-#define TRS21           0x0020  /* Remote Frame Request For Mailbox 21  */
-#define TRS22           0x0040  /* Remote Frame Request For Mailbox 22  */
-#define TRS23           0x0080  /* Remote Frame Request For Mailbox 23  */
-#define TRS24           0x0100  /* Remote Frame Request For Mailbox 24  */
-#define TRS25           0x0200  /* Remote Frame Request For Mailbox 25  */
-#define TRS26           0x0400  /* Remote Frame Request For Mailbox 26  */
-#define TRS27           0x0800  /* Remote Frame Request For Mailbox 27  */
-#define TRS28           0x1000  /* Remote Frame Request For Mailbox 28  */
-#define TRS29           0x2000  /* Remote Frame Request For Mailbox 29  */
-#define TRS30           0x4000  /* Remote Frame Request For Mailbox 30  */
-#define TRS31           0x8000  /* Remote Frame Request For Mailbox 31  */
-
-/* CAN_AA1 Masks                                                                                                */
-#define AA0                     0x0001  /* Aborted Message In Mailbox 0         */
-#define AA1                     0x0002  /* Aborted Message In Mailbox 1         */
-#define AA2                     0x0004  /* Aborted Message In Mailbox 2         */
-#define AA3                     0x0008  /* Aborted Message In Mailbox 3         */
-#define AA4                     0x0010  /* Aborted Message In Mailbox 4         */
-#define AA5                     0x0020  /* Aborted Message In Mailbox 5         */
-#define AA6                     0x0040  /* Aborted Message In Mailbox 6         */
-#define AA7                     0x0080  /* Aborted Message In Mailbox 7         */
-#define AA8                     0x0100  /* Aborted Message In Mailbox 8         */
-#define AA9                     0x0200  /* Aborted Message In Mailbox 9         */
-#define AA10            0x0400  /* Aborted Message In Mailbox 10        */
-#define AA11            0x0800  /* Aborted Message In Mailbox 11        */
-#define AA12            0x1000  /* Aborted Message In Mailbox 12        */
-#define AA13            0x2000  /* Aborted Message In Mailbox 13        */
-#define AA14            0x4000  /* Aborted Message In Mailbox 14        */
-#define AA15            0x8000  /* Aborted Message In Mailbox 15        */
-
-/* CAN_AA2 Masks                                                                                                */
-#define AA16            0x0001  /* Aborted Message In Mailbox 16        */
-#define AA17            0x0002  /* Aborted Message In Mailbox 17        */
-#define AA18            0x0004  /* Aborted Message In Mailbox 18        */
-#define AA19            0x0008  /* Aborted Message In Mailbox 19        */
-#define AA20            0x0010  /* Aborted Message In Mailbox 20        */
-#define AA21            0x0020  /* Aborted Message In Mailbox 21        */
-#define AA22            0x0040  /* Aborted Message In Mailbox 22        */
-#define AA23            0x0080  /* Aborted Message In Mailbox 23        */
-#define AA24            0x0100  /* Aborted Message In Mailbox 24        */
-#define AA25            0x0200  /* Aborted Message In Mailbox 25        */
-#define AA26            0x0400  /* Aborted Message In Mailbox 26        */
-#define AA27            0x0800  /* Aborted Message In Mailbox 27        */
-#define AA28            0x1000  /* Aborted Message In Mailbox 28        */
-#define AA29            0x2000  /* Aborted Message In Mailbox 29        */
-#define AA30            0x4000  /* Aborted Message In Mailbox 30        */
-#define AA31            0x8000  /* Aborted Message In Mailbox 31        */
-
-/* CAN_TA1 Masks                                                                                                        */
-#define TA0                     0x0001  /* Transmit Successful From Mailbox 0   */
-#define TA1                     0x0002  /* Transmit Successful From Mailbox 1   */
-#define TA2                     0x0004  /* Transmit Successful From Mailbox 2   */
-#define TA3                     0x0008  /* Transmit Successful From Mailbox 3   */
-#define TA4                     0x0010  /* Transmit Successful From Mailbox 4   */
-#define TA5                     0x0020  /* Transmit Successful From Mailbox 5   */
-#define TA6                     0x0040  /* Transmit Successful From Mailbox 6   */
-#define TA7                     0x0080  /* Transmit Successful From Mailbox 7   */
-#define TA8                     0x0100  /* Transmit Successful From Mailbox 8   */
-#define TA9                     0x0200  /* Transmit Successful From Mailbox 9   */
-#define TA10            0x0400  /* Transmit Successful From Mailbox 10  */
-#define TA11            0x0800  /* Transmit Successful From Mailbox 11  */
-#define TA12            0x1000  /* Transmit Successful From Mailbox 12  */
-#define TA13            0x2000  /* Transmit Successful From Mailbox 13  */
-#define TA14            0x4000  /* Transmit Successful From Mailbox 14  */
-#define TA15            0x8000  /* Transmit Successful From Mailbox 15  */
-
-/* CAN_TA2 Masks                                                                                                        */
-#define TA16            0x0001  /* Transmit Successful From Mailbox 16  */
-#define TA17            0x0002  /* Transmit Successful From Mailbox 17  */
-#define TA18            0x0004  /* Transmit Successful From Mailbox 18  */
-#define TA19            0x0008  /* Transmit Successful From Mailbox 19  */
-#define TA20            0x0010  /* Transmit Successful From Mailbox 20  */
-#define TA21            0x0020  /* Transmit Successful From Mailbox 21  */
-#define TA22            0x0040  /* Transmit Successful From Mailbox 22  */
-#define TA23            0x0080  /* Transmit Successful From Mailbox 23  */
-#define TA24            0x0100  /* Transmit Successful From Mailbox 24  */
-#define TA25            0x0200  /* Transmit Successful From Mailbox 25  */
-#define TA26            0x0400  /* Transmit Successful From Mailbox 26  */
-#define TA27            0x0800  /* Transmit Successful From Mailbox 27  */
-#define TA28            0x1000  /* Transmit Successful From Mailbox 28  */
-#define TA29            0x2000  /* Transmit Successful From Mailbox 29  */
-#define TA30            0x4000  /* Transmit Successful From Mailbox 30  */
-#define TA31            0x8000  /* Transmit Successful From Mailbox 31  */
-
-/* CAN_MBTD Masks                                                                                               */
-#define TDPTR           0x001F  /* Mailbox To Temporarily Disable       */
-#define TDA                     0x0040  /* Temporary Disable Acknowledge        */
-#define TDR                     0x0080  /* Temporary Disable Request            */
-
-/* CAN_RFH1 Masks                                                                                                                                               */
-#define RFH0            0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 0         */
-#define RFH1            0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 1         */
-#define RFH2            0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 2         */
-#define RFH3            0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 3         */
-#define RFH4            0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 4         */
-#define RFH5            0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 5         */
-#define RFH6            0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 6         */
-#define RFH7            0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 7         */
-#define RFH8            0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 8         */
-#define RFH9            0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 9         */
-#define RFH10           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 10        */
-#define RFH11           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 11        */
-#define RFH12           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 12        */
-#define RFH13           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 13        */
-#define RFH14           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 14        */
-#define RFH15           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 15        */
-
-/* CAN_RFH2 Masks                                                                                                                                               */
-#define RFH16           0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 16        */
-#define RFH17           0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 17        */
-#define RFH18           0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 18        */
-#define RFH19           0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 19        */
-#define RFH20           0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 20        */
-#define RFH21           0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 21        */
-#define RFH22           0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 22        */
-#define RFH23           0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 23        */
-#define RFH24           0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 24        */
-#define RFH25           0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 25        */
-#define RFH26           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 26        */
-#define RFH27           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 27        */
-#define RFH28           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 28        */
-#define RFH29           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 29        */
-#define RFH30           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 30        */
-#define RFH31           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 31        */
-
-/* CAN_MBTIF1 Masks                                                                                                     */
-#define MBTIF0          0x0001  /* TX Interrupt Active In Mailbox 0             */
-#define MBTIF1          0x0002  /* TX Interrupt Active In Mailbox 1             */
-#define MBTIF2          0x0004  /* TX Interrupt Active In Mailbox 2             */
-#define MBTIF3          0x0008  /* TX Interrupt Active In Mailbox 3             */
-#define MBTIF4          0x0010  /* TX Interrupt Active In Mailbox 4             */
-#define MBTIF5          0x0020  /* TX Interrupt Active In Mailbox 5             */
-#define MBTIF6          0x0040  /* TX Interrupt Active In Mailbox 6             */
-#define MBTIF7          0x0080  /* TX Interrupt Active In Mailbox 7             */
-#define MBTIF8          0x0100  /* TX Interrupt Active In Mailbox 8             */
-#define MBTIF9          0x0200  /* TX Interrupt Active In Mailbox 9             */
-#define MBTIF10         0x0400  /* TX Interrupt Active In Mailbox 10    */
-#define MBTIF11         0x0800  /* TX Interrupt Active In Mailbox 11    */
-#define MBTIF12         0x1000  /* TX Interrupt Active In Mailbox 12    */
-#define MBTIF13         0x2000  /* TX Interrupt Active In Mailbox 13    */
-#define MBTIF14         0x4000  /* TX Interrupt Active In Mailbox 14    */
-#define MBTIF15         0x8000  /* TX Interrupt Active In Mailbox 15    */
-
-/* CAN_MBTIF2 Masks                                                                                                     */
-#define MBTIF16         0x0001  /* TX Interrupt Active In Mailbox 16    */
-#define MBTIF17         0x0002  /* TX Interrupt Active In Mailbox 17    */
-#define MBTIF18         0x0004  /* TX Interrupt Active In Mailbox 18    */
-#define MBTIF19         0x0008  /* TX Interrupt Active In Mailbox 19    */
-#define MBTIF20         0x0010  /* TX Interrupt Active In Mailbox 20    */
-#define MBTIF21         0x0020  /* TX Interrupt Active In Mailbox 21    */
-#define MBTIF22         0x0040  /* TX Interrupt Active In Mailbox 22    */
-#define MBTIF23         0x0080  /* TX Interrupt Active In Mailbox 23    */
-#define MBTIF24         0x0100  /* TX Interrupt Active In Mailbox 24    */
-#define MBTIF25         0x0200  /* TX Interrupt Active In Mailbox 25    */
-#define MBTIF26         0x0400  /* TX Interrupt Active In Mailbox 26    */
-#define MBTIF27         0x0800  /* TX Interrupt Active In Mailbox 27    */
-#define MBTIF28         0x1000  /* TX Interrupt Active In Mailbox 28    */
-#define MBTIF29         0x2000  /* TX Interrupt Active In Mailbox 29    */
-#define MBTIF30         0x4000  /* TX Interrupt Active In Mailbox 30    */
-#define MBTIF31         0x8000  /* TX Interrupt Active In Mailbox 31    */
-
-/* CAN_MBRIF1 Masks                                                                                                     */
-#define MBRIF0          0x0001  /* RX Interrupt Active In Mailbox 0             */
-#define MBRIF1          0x0002  /* RX Interrupt Active In Mailbox 1             */
-#define MBRIF2          0x0004  /* RX Interrupt Active In Mailbox 2             */
-#define MBRIF3          0x0008  /* RX Interrupt Active In Mailbox 3             */
-#define MBRIF4          0x0010  /* RX Interrupt Active In Mailbox 4             */
-#define MBRIF5          0x0020  /* RX Interrupt Active In Mailbox 5             */
-#define MBRIF6          0x0040  /* RX Interrupt Active In Mailbox 6             */
-#define MBRIF7          0x0080  /* RX Interrupt Active In Mailbox 7             */
-#define MBRIF8          0x0100  /* RX Interrupt Active In Mailbox 8             */
-#define MBRIF9          0x0200  /* RX Interrupt Active In Mailbox 9             */
-#define MBRIF10         0x0400  /* RX Interrupt Active In Mailbox 10    */
-#define MBRIF11         0x0800  /* RX Interrupt Active In Mailbox 11    */
-#define MBRIF12         0x1000  /* RX Interrupt Active In Mailbox 12    */
-#define MBRIF13         0x2000  /* RX Interrupt Active In Mailbox 13    */
-#define MBRIF14         0x4000  /* RX Interrupt Active In Mailbox 14    */
-#define MBRIF15         0x8000  /* RX Interrupt Active In Mailbox 15    */
-
-/* CAN_MBRIF2 Masks                                                                                                     */
-#define MBRIF16         0x0001  /* RX Interrupt Active In Mailbox 16    */
-#define MBRIF17         0x0002  /* RX Interrupt Active In Mailbox 17    */
-#define MBRIF18         0x0004  /* RX Interrupt Active In Mailbox 18    */
-#define MBRIF19         0x0008  /* RX Interrupt Active In Mailbox 19    */
-#define MBRIF20         0x0010  /* RX Interrupt Active In Mailbox 20    */
-#define MBRIF21         0x0020  /* RX Interrupt Active In Mailbox 21    */
-#define MBRIF22         0x0040  /* RX Interrupt Active In Mailbox 22    */
-#define MBRIF23         0x0080  /* RX Interrupt Active In Mailbox 23    */
-#define MBRIF24         0x0100  /* RX Interrupt Active In Mailbox 24    */
-#define MBRIF25         0x0200  /* RX Interrupt Active In Mailbox 25    */
-#define MBRIF26         0x0400  /* RX Interrupt Active In Mailbox 26    */
-#define MBRIF27         0x0800  /* RX Interrupt Active In Mailbox 27    */
-#define MBRIF28         0x1000  /* RX Interrupt Active In Mailbox 28    */
-#define MBRIF29         0x2000  /* RX Interrupt Active In Mailbox 29    */
-#define MBRIF30         0x4000  /* RX Interrupt Active In Mailbox 30    */
-#define MBRIF31         0x8000  /* RX Interrupt Active In Mailbox 31    */
-
-/* CAN_MBIM1 Masks                                                                                              */
-#define MBIM0           0x0001  /* Enable Interrupt For Mailbox 0       */
-#define MBIM1           0x0002  /* Enable Interrupt For Mailbox 1       */
-#define MBIM2           0x0004  /* Enable Interrupt For Mailbox 2       */
-#define MBIM3           0x0008  /* Enable Interrupt For Mailbox 3       */
-#define MBIM4           0x0010  /* Enable Interrupt For Mailbox 4       */
-#define MBIM5           0x0020  /* Enable Interrupt For Mailbox 5       */
-#define MBIM6           0x0040  /* Enable Interrupt For Mailbox 6       */
-#define MBIM7           0x0080  /* Enable Interrupt For Mailbox 7       */
-#define MBIM8           0x0100  /* Enable Interrupt For Mailbox 8       */
-#define MBIM9           0x0200  /* Enable Interrupt For Mailbox 9       */
-#define MBIM10          0x0400  /* Enable Interrupt For Mailbox 10      */
-#define MBIM11          0x0800  /* Enable Interrupt For Mailbox 11      */
-#define MBIM12          0x1000  /* Enable Interrupt For Mailbox 12      */
-#define MBIM13          0x2000  /* Enable Interrupt For Mailbox 13      */
-#define MBIM14          0x4000  /* Enable Interrupt For Mailbox 14      */
-#define MBIM15          0x8000  /* Enable Interrupt For Mailbox 15      */
-
-/* CAN_MBIM2 Masks                                                                                              */
-#define MBIM16          0x0001  /* Enable Interrupt For Mailbox 16      */
-#define MBIM17          0x0002  /* Enable Interrupt For Mailbox 17      */
-#define MBIM18          0x0004  /* Enable Interrupt For Mailbox 18      */
-#define MBIM19          0x0008  /* Enable Interrupt For Mailbox 19      */
-#define MBIM20          0x0010  /* Enable Interrupt For Mailbox 20      */
-#define MBIM21          0x0020  /* Enable Interrupt For Mailbox 21      */
-#define MBIM22          0x0040  /* Enable Interrupt For Mailbox 22      */
-#define MBIM23          0x0080  /* Enable Interrupt For Mailbox 23      */
-#define MBIM24          0x0100  /* Enable Interrupt For Mailbox 24      */
-#define MBIM25          0x0200  /* Enable Interrupt For Mailbox 25      */
-#define MBIM26          0x0400  /* Enable Interrupt For Mailbox 26      */
-#define MBIM27          0x0800  /* Enable Interrupt For Mailbox 27      */
-#define MBIM28          0x1000  /* Enable Interrupt For Mailbox 28      */
-#define MBIM29          0x2000  /* Enable Interrupt For Mailbox 29      */
-#define MBIM30          0x4000  /* Enable Interrupt For Mailbox 30      */
-#define MBIM31          0x8000  /* Enable Interrupt For Mailbox 31      */
-
-/* CAN_GIM Masks                                                                                                                                */
-#define EWTIM           0x0001  /* Enable TX Error Count Interrupt                                      */
-#define EWRIM           0x0002  /* Enable RX Error Count Interrupt                                      */
-#define EPIM            0x0004  /* Enable Error-Passive Mode Interrupt                          */
-#define BOIM            0x0008  /* Enable Bus Off Interrupt                                                     */
-#define WUIM            0x0010  /* Enable Wake-Up Interrupt                                                     */
-#define UIAIM           0x0020  /* Enable Access To Unimplemented Address Interrupt     */
-#define AAIM            0x0040  /* Enable Abort Acknowledge Interrupt                           */
-#define RMLIM           0x0080  /* Enable RX Message Lost Interrupt                                     */
-#define UCEIM           0x0100  /* Enable Universal Counter Overflow Interrupt          */
-#define EXTIM           0x0200  /* Enable External Trigger Output Interrupt                     */
-#define ADIM            0x0400  /* Enable Access Denied Interrupt                                       */
-
-/* CAN_GIS Masks                                                                                                                        */
-#define EWTIS           0x0001  /* TX Error Count IRQ Status                                    */
-#define EWRIS           0x0002  /* RX Error Count IRQ Status                                    */
-#define EPIS            0x0004  /* Error-Passive Mode IRQ Status                                */
-#define BOIS            0x0008  /* Bus Off IRQ Status                                                   */
-#define WUIS            0x0010  /* Wake-Up IRQ Status                                                   */
-#define UIAIS           0x0020  /* Access To Unimplemented Address IRQ Status   */
-#define AAIS            0x0040  /* Abort Acknowledge IRQ Status                                 */
-#define RMLIS           0x0080  /* RX Message Lost IRQ Status                                   */
-#define UCEIS           0x0100  /* Universal Counter Overflow IRQ Status                */
-#define EXTIS           0x0200  /* External Trigger Output IRQ Status                   */
-#define ADIS            0x0400  /* Access Denied IRQ Status                                             */
-
-/* CAN_GIF Masks                                                                                                                        */
-#define EWTIF           0x0001  /* TX Error Count IRQ Flag                                              */
-#define EWRIF           0x0002  /* RX Error Count IRQ Flag                                              */
-#define EPIF            0x0004  /* Error-Passive Mode IRQ Flag                                  */
-#define BOIF            0x0008  /* Bus Off IRQ Flag                                                             */
-#define WUIF            0x0010  /* Wake-Up IRQ Flag                                                             */
-#define UIAIF           0x0020  /* Access To Unimplemented Address IRQ Flag             */
-#define AAIF            0x0040  /* Abort Acknowledge IRQ Flag                                   */
-#define RMLIF           0x0080  /* RX Message Lost IRQ Flag                                             */
-#define UCEIF           0x0100  /* Universal Counter Overflow IRQ Flag                  */
-#define EXTIF           0x0200  /* External Trigger Output IRQ Flag                             */
-#define ADIF            0x0400  /* Access Denied IRQ Flag                                               */
-
-/* CAN_UCCNF Masks                                                                                                                      */
-#define UCCNF           0x000F  /* Universal Counter Mode                                               */
-#define UC_STAMP        0x0001  /*              Timestamp Mode                                                  */
-#define UC_WDOG         0x0002  /*              Watchdog Mode                                                   */
-#define UC_AUTOTX       0x0003  /*              Auto-Transmit Mode                                              */
-#define UC_ERROR        0x0006  /*              CAN Error Frame Count                                   */
-#define UC_OVER         0x0007  /*              CAN Overload Frame Count                                */
-#define UC_LOST         0x0008  /*              Arbitration Lost During TX Count                */
-#define UC_AA           0x0009  /*              TX Abort Count                                                  */
-#define UC_TA           0x000A  /*              TX Successful Count                                             */
-#define UC_REJECT       0x000B  /*              RX Message Rejected Count                               */
-#define UC_RML          0x000C  /*              RX Message Lost Count                                   */
-#define UC_RX           0x000D  /*              Total Successful RX Messages Count              */
-#define UC_RMP          0x000E  /*              Successful RX W/Matching ID Count               */
-#define UC_ALL          0x000F  /*              Correct Message On CAN Bus Line Count   */
-#define UCRC            0x0020  /* Universal Counter Reload/Clear                               */
-#define UCCT            0x0040  /* Universal Counter CAN Trigger                                */
-#define UCE                     0x0080  /* Universal Counter Enable                                             */
-
-/* CAN_ESR Masks                                                                                */
-#define ACKE            0x0004  /* Acknowledge Error            */
-#define SER                     0x0008  /* Stuff Error                          */
-#define CRCE            0x0010  /* CRC Error                            */
-#define SA0                     0x0020  /* Stuck At Dominant Error      */
-#define BEF                     0x0040  /* Bit Error Flag                       */
-#define FER                     0x0080  /* Form Error Flag                      */
-
-/* CAN_EWR Masks                                                                                                */
-#define EWLREC          0x00FF  /* RX Error Count Limit (For EWRIS)     */
-#define EWLTEC          0xFF00  /* TX Error Count Limit (For EWTIS)     */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000 
-#define _BOOTROM_FINAL_INIT 0xEF000002 
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-#endif                          /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
deleted file mode 100644
index abde24c6d3b1..000000000000
--- a/include/asm-blackfin/mach-bf537/defBF537.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/defbf537.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all Core registers and bit definitions*/
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* Include all MMR and bit defines common to BF534 */
-#include "defBF534.h"
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                                                               */
-#define EMAC_OPMODE                     0xFFC03000      /* Operating Mode Register                                                              */
-#define EMAC_ADDRLO                     0xFFC03004      /* Address Low (32 LSBs) Register                                               */
-#define EMAC_ADDRHI                     0xFFC03008      /* Address High (16 MSBs) Register                                              */
-#define EMAC_HASHLO                     0xFFC0300C      /* Multicast Hash Table Low (Bins 31-0) Register                */
-#define EMAC_HASHHI                     0xFFC03010      /* Multicast Hash Table High (Bins 63-32) Register              */
-#define EMAC_STAADD                     0xFFC03014      /* Station Management Address Register                                  */
-#define EMAC_STADAT                     0xFFC03018      /* Station Management Data Register                                     */
-#define EMAC_FLC                        0xFFC0301C      /* Flow Control Register                                                                */
-#define EMAC_VLAN1                      0xFFC03020      /* VLAN1 Tag Register                                                                   */
-#define EMAC_VLAN2                      0xFFC03024      /* VLAN2 Tag Register                                                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C      /* Wake-Up Control/Status Register                                              */
-#define EMAC_WKUP_FFMSK0        0xFFC03030      /* Wake-Up Frame Filter 0 Byte Mask Register                    */
-#define EMAC_WKUP_FFMSK1        0xFFC03034      /* Wake-Up Frame Filter 1 Byte Mask Register                    */
-#define EMAC_WKUP_FFMSK2        0xFFC03038      /* Wake-Up Frame Filter 2 Byte Mask Register                    */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C      /* Wake-Up Frame Filter 3 Byte Mask Register                    */
-#define EMAC_WKUP_FFCMD         0xFFC03040      /* Wake-Up Frame Filter Commands Register                               */
-#define EMAC_WKUP_FFOFF         0xFFC03044      /* Wake-Up Frame Filter Offsets Register                                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048      /* Wake-Up Frame Filter 0,1 CRC-16 Register                             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C      /* Wake-Up Frame Filter 2,3 CRC-16 Register                             */
-
-#define EMAC_SYSCTL                     0xFFC03060      /* EMAC System Control Register                                                 */
-#define EMAC_SYSTAT                     0xFFC03064      /* EMAC System Status Register                                                  */
-#define EMAC_RX_STAT            0xFFC03068      /* RX Current Frame Status Register                                             */
-#define EMAC_RX_STKY            0xFFC0306C      /* RX Sticky Frame Status Register                                              */
-#define EMAC_RX_IRQE            0xFFC03070      /* RX Frame Status Interrupt Enables Register                   */
-#define EMAC_TX_STAT            0xFFC03074      /* TX Current Frame Status Register                                             */
-#define EMAC_TX_STKY            0xFFC03078      /* TX Sticky Frame Status Register                                              */
-#define EMAC_TX_IRQE            0xFFC0307C      /* TX Frame Status Interrupt Enables Register                   */
-
-#define EMAC_MMC_CTL            0xFFC03080      /* MMC Counter Control Register                                                 */
-#define EMAC_MMC_RIRQS          0xFFC03084      /* MMC RX Interrupt Status Register                                             */
-#define EMAC_MMC_RIRQE          0xFFC03088      /* MMC RX Interrupt Enables Register                                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C      /* MMC TX Interrupt Status Register                                             */
-#define EMAC_MMC_TIRQE          0xFFC03090      /* MMC TX Interrupt Enables Register                                    */
-
-#define EMAC_RXC_OK                     0xFFC03100      /* RX Frame Successful Count                                                    */
-#define EMAC_RXC_FCS            0xFFC03104      /* RX Frame FCS Failure Count                                                   */
-#define EMAC_RXC_ALIGN          0xFFC03108      /* RX Alignment Error Count                                                             */
-#define EMAC_RXC_OCTET          0xFFC0310C      /* RX Octets Successfully Received Count                                */
-#define EMAC_RXC_DMAOVF         0xFFC03110      /* Internal MAC Sublayer Error RX Frame Count                   */
-#define EMAC_RXC_UNICST         0xFFC03114      /* Unicast RX Frame Count                                                               */
-#define EMAC_RXC_MULTI          0xFFC03118      /* Multicast RX Frame Count                                                             */
-#define EMAC_RXC_BROAD          0xFFC0311C      /* Broadcast RX Frame Count                                                             */
-#define EMAC_RXC_LNERRI         0xFFC03120      /* RX Frame In Range Error Count                                                */
-#define EMAC_RXC_LNERRO         0xFFC03124      /* RX Frame Out Of Range Error Count                                    */
-#define EMAC_RXC_LONG           0xFFC03128      /* RX Frame Too Long Count                                                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C      /* MAC Control RX Frame Count                                                   */
-#define EMAC_RXC_OPCODE         0xFFC03130      /* Unsupported Op-Code RX Frame Count                                   */
-#define EMAC_RXC_PAUSE          0xFFC03134      /* MAC Control Pause RX Frame Count                                             */
-#define EMAC_RXC_ALLFRM         0xFFC03138      /* Overall RX Frame Count                                                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C      /* Overall RX Octet Count                                                               */
-#define EMAC_RXC_TYPED          0xFFC03140      /* Type/Length Consistent RX Frame Count                                */
-#define EMAC_RXC_SHORT          0xFFC03144      /* RX Frame Fragment Count - Byte Count x < 64                  */
-#define EMAC_RXC_EQ64           0xFFC03148      /* Good RX Frame Count - Byte Count x = 64                              */
-#define EMAC_RXC_LT128          0xFFC0314C      /* Good RX Frame Count - Byte Count  64 <= x < 128              */
-#define EMAC_RXC_LT256          0xFFC03150      /* Good RX Frame Count - Byte Count 128 <= x < 256              */
-#define EMAC_RXC_LT512          0xFFC03154      /* Good RX Frame Count - Byte Count 256 <= x < 512              */
-#define EMAC_RXC_LT1024         0xFFC03158      /* Good RX Frame Count - Byte Count 512 <= x < 1024             */
-#define EMAC_RXC_GE1024         0xFFC0315C      /* Good RX Frame Count - Byte Count x >= 1024                   */
-
-#define EMAC_TXC_OK                     0xFFC03180      /* TX Frame Successful Count                                                    */
-#define EMAC_TXC_1COL           0xFFC03184      /* TX Frames Successful After Single Collision Count    */
-#define EMAC_TXC_GT1COL         0xFFC03188      /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET          0xFFC0318C      /* TX Octets Successfully Received Count                                */
-#define EMAC_TXC_DEFER          0xFFC03190      /* TX Frame Delayed Due To Busy Count                                   */
-#define EMAC_TXC_LATECL         0xFFC03194      /* Late TX Collisions Count                                                             */
-#define EMAC_TXC_XS_COL         0xFFC03198      /* TX Frame Failed Due To Excessive Collisions Count    */
-#define EMAC_TXC_DMAUND         0xFFC0319C      /* Internal MAC Sublayer Error TX Frame Count                   */
-#define EMAC_TXC_CRSERR         0xFFC031A0      /* Carrier Sense Deasserted During TX Frame Count               */
-#define EMAC_TXC_UNICST         0xFFC031A4      /* Unicast TX Frame Count                                                               */
-#define EMAC_TXC_MULTI          0xFFC031A8      /* Multicast TX Frame Count                                                             */
-#define EMAC_TXC_BROAD          0xFFC031AC      /* Broadcast TX Frame Count                                                             */
-#define EMAC_TXC_XS_DFR         0xFFC031B0      /* TX Frames With Excessive Deferral Count                              */
-#define EMAC_TXC_MACCTL         0xFFC031B4      /* MAC Control TX Frame Count                                                   */
-#define EMAC_TXC_ALLFRM         0xFFC031B8      /* Overall TX Frame Count                                                               */
-#define EMAC_TXC_ALLOCT         0xFFC031BC      /* Overall TX Octet Count                                                               */
-#define EMAC_TXC_EQ64           0xFFC031C0      /* Good TX Frame Count - Byte Count x = 64                              */
-#define EMAC_TXC_LT128          0xFFC031C4      /* Good TX Frame Count - Byte Count  64 <= x < 128              */
-#define EMAC_TXC_LT256          0xFFC031C8      /* Good TX Frame Count - Byte Count 128 <= x < 256              */
-#define EMAC_TXC_LT512          0xFFC031CC      /* Good TX Frame Count - Byte Count 256 <= x < 512              */
-#define EMAC_TXC_LT1024         0xFFC031D0      /* Good TX Frame Count - Byte Count 512 <= x < 1024             */
-#define EMAC_TXC_GE1024         0xFFC031D4      /* Good TX Frame Count - Byte Count x >= 1024                   */
-#define EMAC_TXC_ABORT          0xFFC031D8      /* Total TX Frames Aborted Count                                                */
-
-/* Listing for IEEE-Supported Count Registers                                                                                                                                   */
-#define FramesReceivedOK                                EMAC_RXC_OK     /* RX Frame Successful Count                                                    */
-#define FrameCheckSequenceErrors                EMAC_RXC_FCS    /* RX Frame FCS Failure Count                                                   */
-#define AlignmentErrors                                 EMAC_RXC_ALIGN  /* RX Alignment Error Count                                                             */
-#define OctetsReceivedOK                                EMAC_RXC_OCTET  /* RX Octets Successfully Received Count                                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count                   */
-#define UnicastFramesReceivedOK                 EMAC_RXC_UNICST /* Unicast RX Frame Count                                                               */
-#define MulticastFramesReceivedOK               EMAC_RXC_MULTI  /* Multicast RX Frame Count                                                             */
-#define BroadcastFramesReceivedOK               EMAC_RXC_BROAD  /* Broadcast RX Frame Count                                                             */
-#define InRangeLengthErrors                             EMAC_RXC_LNERRI /* RX Frame In Range Error Count                                                */
-#define OutOfRangeLengthField                   EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count                                    */
-#define FrameTooLongErrors                              EMAC_RXC_LONG   /* RX Frame Too Long Count                                                              */
-#define MACControlFramesReceived                EMAC_RXC_MACCTL /* MAC Control RX Frame Count                                                   */
-#define UnsupportedOpcodesReceived              EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count                                   */
-#define PAUSEMACCtrlFramesReceived              EMAC_RXC_PAUSE  /* MAC Control Pause RX Frame Count                                             */
-#define FramesReceivedAll                               EMAC_RXC_ALLFRM /* Overall RX Frame Count                                                               */
-#define OctetsReceivedAll                               EMAC_RXC_ALLOCT /* Overall RX Octet Count                                                               */
-#define TypedFramesReceived                             EMAC_RXC_TYPED  /* Type/Length Consistent RX Frame Count                                */
-#define FramesLenLt64Received                   EMAC_RXC_SHORT  /* RX Frame Fragment Count - Byte Count x < 64                  */
-#define FramesLenEq64Received                   EMAC_RXC_EQ64   /* Good RX Frame Count - Byte Count x = 64                              */
-#define FramesLen65_127Received                 EMAC_RXC_LT128  /* Good RX Frame Count - Byte Count  64 <= x < 128              */
-#define FramesLen128_255Received                EMAC_RXC_LT256  /* Good RX Frame Count - Byte Count 128 <= x < 256              */
-#define FramesLen256_511Received                EMAC_RXC_LT512  /* Good RX Frame Count - Byte Count 256 <= x < 512              */
-#define FramesLen512_1023Received               EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024             */
-#define FramesLen1024_MaxReceived               EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024                   */
-
-#define FramesTransmittedOK                             EMAC_TXC_OK     /* TX Frame Successful Count                                                    */
-#define SingleCollisionFrames                   EMAC_TXC_1COL   /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames                 EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK                             EMAC_TXC_OCTET  /* TX Octets Successfully Received Count                                */
-#define FramesWithDeferredXmissions             EMAC_TXC_DEFER  /* TX Frame Delayed Due To Busy Count                                   */
-#define LateCollisions                                  EMAC_TXC_LATECL /* Late TX Collisions Count                                                             */
-#define FramesAbortedDueToXSColls               EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count                   */
-#define CarrierSenseErrors                              EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count               */
-#define UnicastFramesXmittedOK                  EMAC_TXC_UNICST /* Unicast TX Frame Count                                                               */
-#define MulticastFramesXmittedOK                EMAC_TXC_MULTI  /* Multicast TX Frame Count                                                             */
-#define BroadcastFramesXmittedOK                EMAC_TXC_BROAD  /* Broadcast TX Frame Count                                                             */
-#define FramesWithExcessiveDeferral             EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count                              */
-#define MACControlFramesTransmitted             EMAC_TXC_MACCTL /* MAC Control TX Frame Count                                                   */
-#define FramesTransmittedAll                    EMAC_TXC_ALLFRM /* Overall TX Frame Count                                                               */
-#define OctetsTransmittedAll                    EMAC_TXC_ALLOCT /* Overall TX Octet Count                                                               */
-#define FramesLenEq64Transmitted                EMAC_TXC_EQ64   /* Good TX Frame Count - Byte Count x = 64                              */
-#define FramesLen65_127Transmitted              EMAC_TXC_LT128  /* Good TX Frame Count - Byte Count  64 <= x < 128              */
-#define FramesLen128_255Transmitted             EMAC_TXC_LT256  /* Good TX Frame Count - Byte Count 128 <= x < 256              */
-#define FramesLen256_511Transmitted             EMAC_TXC_LT512  /* Good TX Frame Count - Byte Count 256 <= x < 512              */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024             */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024                   */
-#define TxAbortedFrames                                 EMAC_TXC_ABORT  /* Total TX Frames Aborted Count                                                */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-/* EMAC_OPMODE Masks                                                                                                                            */
-#define RE                      0x00000001      /* Receiver Enable                                                                      */
-#define ASTP            0x00000002      /* Enable Automatic Pad Stripping On RX Frames          */
-#define HU                      0x00000010      /* Hash Filter Unicast Address                                          */
-#define HM                      0x00000020      /* Hash Filter Multicast Address                                        */
-#define PAM                     0x00000040      /* Pass-All-Multicast Mode Enable                                       */
-#define PR                      0x00000080      /* Promiscuous Mode Enable                                                      */
-#define IFE                     0x00000100      /* Inverse Filtering Enable                                                     */
-#define DBF                     0x00000200      /* Disable Broadcast Frame Reception                            */
-#define PBF                     0x00000400      /* Pass Bad Frames Enable                                                       */
-#define PSF                     0x00000800      /* Pass Short Frames Enable                                                     */
-#define RAF                     0x00001000      /* Receive-All Mode                                                                     */
-#define TE                      0x00010000      /* Transmitter Enable                                                           */
-#define DTXPAD          0x00020000      /* Disable Automatic TX Padding                                         */
-#define DTXCRC          0x00040000      /* Disable Automatic TX CRC Generation                          */
-#define DC                      0x00080000      /* Deferral Check                                                                       */
-#define BOLMT           0x00300000      /* Back-Off Limit                                                                       */
-#define BOLMT_10        0x00000000      /*              10-bit range                                                            */
-#define BOLMT_8         0x00100000      /*              8-bit range                                                                     */
-#define BOLMT_4         0x00200000      /*              4-bit range                                                                     */
-#define BOLMT_1         0x00300000      /*              1-bit range                                                                     */
-#define DRTY            0x00400000      /* Disable TX Retry On Collision                                        */
-#define LCTRE           0x00800000      /* Enable TX Retry On Late Collision                            */
-#define RMII            0x01000000      /* RMII/MII* Mode                                                                       */
-#define RMII_10         0x02000000      /* Speed Select for RMII Port (10MBit/100MBit*)         */
-#define FDMODE          0x04000000      /* Duplex Mode Enable (Full/Half*)                                      */
-#define LB                      0x08000000      /* Internal Loopback Enable                                                     */
-#define DRO                     0x10000000      /* Disable Receive Own Frames (Half-Duplex Mode)        */
-
-/* EMAC_STAADD Masks                                                                                                                            */
-#define STABUSY         0x00000001      /* Initiate Station Mgt Reg Access / STA Busy Stat      */
-#define STAOP           0x00000002      /* Station Management Operation Code (Write/Read*)      */
-#define STADISPRE       0x00000004      /* Disable Preamble Generation                                          */
-#define STAIE           0x00000008      /* Station Mgt. Transfer Done Interrupt Enable          */
-#define REGAD           0x000007C0      /* STA Register Address                                                         */
-#define PHYAD           0x0000F800      /* PHY Device Address                                                           */
-
-#define SET_REGAD(x)    (((x)&0x1F)<<  6 )      /* Set STA Register Address                             */
-#define SET_PHYAD(x)    (((x)&0x1F)<< 11 )      /* Set PHY Device Address                               */
-
-/* EMAC_STADAT Mask                                                                                     */
-#define STADATA         0x0000FFFF      /* Station Management Data      */
-
-/* EMAC_FLC Masks                                                                                                                                       */
-#define FLCBUSY         0x00000001      /* Send Flow Ctrl Frame / Flow Ctrl Busy Status         */
-#define FLCE            0x00000002      /* Flow Control Enable                                                          */
-#define PCF                     0x00000004      /* Pass Control Frames                                                          */
-#define BKPRSEN         0x00000008      /* Enable Backpressure                                                          */
-#define FLCPAUSE        0xFFFF0000      /* Pause Time                                                                           */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16)     /* Set Pause Time                                               */
-
-/* EMAC_WKUP_CTL Masks                                                                                                                          */
-#define CAPWKFRM        0x00000001      /* Capture Wake-Up Frames                                                       */
-#define MPKE            0x00000002      /* Magic Packet Enable                                                          */
-#define RWKE            0x00000004      /* Remote Wake-Up Frame Enable                                          */
-#define GUWKE           0x00000008      /* Global Unicast Wake Enable                                           */
-#define MPKS            0x00000020      /* Magic Packet Received Status                                         */
-#define RWKS            0x00000F00      /* Wake-Up Frame Received Status, Filters 3:0           */
-
-/* EMAC_WKUP_FFCMD Masks                                                                                                                        */
-#define WF0_E           0x00000001      /* Enable Wake-Up Filter 0                                                      */
-#define WF0_T           0x00000008      /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define WF1_E           0x00000100      /* Enable Wake-Up Filter 1                                                      */
-#define WF1_T           0x00000800      /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define WF2_E           0x00010000      /* Enable Wake-Up Filter 2                                                      */
-#define WF2_T           0x00080000      /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define WF3_E           0x01000000      /* Enable Wake-Up Filter 3                                                      */
-#define WF3_T           0x08000000      /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks                                                                                                                        */
-#define WF0_OFF         0x000000FF      /* Wake-Up Filter 0 Pattern Offset                                      */
-#define WF1_OFF         0x0000FF00      /* Wake-Up Filter 1 Pattern Offset                                      */
-#define WF2_OFF         0x00FF0000      /* Wake-Up Filter 2 Pattern Offset                                      */
-#define WF3_OFF         0xFF000000      /* Wake-Up Filter 3 Pattern Offset                                      */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 )       /* Set Wake-Up Filter 0 Byte Offset           */
-#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 )       /* Set Wake-Up Filter 1 Byte Offset           */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 )       /* Set Wake-Up Filter 2 Byte Offset           */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 )       /* Set Wake-Up Filter 3 Byte Offset           */
-/* Set ALL Offsets                                                                                                                                      */
-#define SET_WF_OFFS(x0,x1,x2,x3)        (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks                                                                                                                       */
-#define WF0_CRC         0x0000FFFF      /* Wake-Up Filter 0 Pattern CRC                                         */
-#define WF1_CRC         0xFFFF0000      /* Wake-Up Filter 1 Pattern CRC                                         */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 )    /* Set Wake-Up Filter 0 Target CRC         */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 )    /* Set Wake-Up Filter 1 Target CRC         */
-
-/* EMAC_WKUP_FFCRC1 Masks                                                                                                                       */
-#define WF2_CRC         0x0000FFFF      /* Wake-Up Filter 2 Pattern CRC                                         */
-#define WF3_CRC         0xFFFF0000      /* Wake-Up Filter 3 Pattern CRC                                         */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 )    /* Set Wake-Up Filter 2 Target CRC         */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 )    /* Set Wake-Up Filter 3 Target CRC         */
-
-/* EMAC_SYSCTL Masks                                                                                                                            */
-#define PHYIE           0x00000001      /* PHY_INT Interrupt Enable                                                     */
-#define RXDWA           0x00000002      /* Receive Frame DMA Word Alignment (Odd/Even*)         */
-#define RXCKS           0x00000004      /* Enable RX Frame TCP/UDP Checksum Computation         */
-#define TXDWA           0x00000010      /* Transmit Frame DMA Word Alignment (Odd/Even*)        */
-#define MDCDIV          0x00003F00      /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]          */
-
-#define SET_MDCDIV(x)   (((x)&0x3F)<< 8)        /* Set MDC Clock Divisor                                */
-
-/* EMAC_SYSTAT Masks                                                                                                                    */
-#define PHYINT          0x00000001      /* PHY_INT Interrupt Status                                             */
-#define MMCINT          0x00000002      /* MMC Counter Interrupt Status                                 */
-#define RXFSINT         0x00000004      /* RX Frame-Status Interrupt Status                             */
-#define TXFSINT         0x00000008      /* TX Frame-Status Interrupt Status                             */
-#define WAKEDET         0x00000010      /* Wake-Up Detected Status                                              */
-#define RXDMAERR        0x00000020      /* RX DMA Direction Error Status                                */
-#define TXDMAERR        0x00000040      /* TX DMA Direction Error Status                                */
-#define STMDONE         0x00000080      /* Station Mgt. Transfer Done Interrupt Status  */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks                                                   */
-#define RX_FRLEN        0x000007FF      /* Frame Length In Bytes                                                */
-#define RX_COMP         0x00001000      /* RX Frame Complete                                                    */
-#define RX_OK           0x00002000      /* RX Frame Received With No Errors                             */
-#define RX_LONG         0x00004000      /* RX Frame Too Long Error                                              */
-#define RX_ALIGN        0x00008000      /* RX Frame Alignment Error                                             */
-#define RX_CRC          0x00010000      /* RX Frame CRC Error                                                   */
-#define RX_LEN          0x00020000      /* RX Frame Length Error                                                */
-#define RX_FRAG         0x00040000      /* RX Frame Fragment Error                                              */
-#define RX_ADDR         0x00080000      /* RX Frame Address Filter Failed Error                 */
-#define RX_DMAO         0x00100000      /* RX Frame DMA Overrun Error                                   */
-#define RX_PHY          0x00200000      /* RX Frame PHY Error                                                   */
-#define RX_LATE         0x00400000      /* RX Frame Late Collision Error                                */
-#define RX_RANGE        0x00800000      /* RX Frame Length Field Out of Range Error             */
-#define RX_MULTI        0x01000000      /* RX Multicast Frame Indicator                                 */
-#define RX_BROAD        0x02000000      /* RX Broadcast Frame Indicator                                 */
-#define RX_CTL          0x04000000      /* RX Control Frame Indicator                                   */
-#define RX_UCTL         0x08000000      /* Unsupported RX Control Frame Indicator               */
-#define RX_TYPE         0x10000000      /* RX Typed Frame Indicator                                             */
-#define RX_VLAN1        0x20000000      /* RX VLAN1 Frame Indicator                                             */
-#define RX_VLAN2        0x40000000      /* RX VLAN2 Frame Indicator                                             */
-#define RX_ACCEPT       0x80000000      /* RX Frame Accepted Indicator                                  */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks                                                  */
-#define TX_COMP         0x00000001      /* TX Frame Complete                                                    */
-#define TX_OK           0x00000002      /* TX Frame Sent With No Errors                                 */
-#define TX_ECOLL        0x00000004      /* TX Frame Excessive Collision Error                   */
-#define TX_LATE         0x00000008      /* TX Frame Late Collision Error                                */
-#define TX_DMAU         0x00000010      /* TX Frame DMA Underrun Error (STAT)                   */
-#define TX_MACE         0x00000010      /* Internal MAC Error Detected (STKY and IRQE)  */
-#define TX_EDEFER       0x00000020      /* TX Frame Excessive Deferral Error                    */
-#define TX_BROAD        0x00000040      /* TX Broadcast Frame Indicator                                 */
-#define TX_MULTI        0x00000080      /* TX Multicast Frame Indicator                                 */
-#define TX_CCNT         0x00000F00      /* TX Frame Collision Count                                             */
-#define TX_DEFER        0x00001000      /* TX Frame Deferred Indicator                                  */
-#define TX_CRS          0x00002000      /* TX Frame Carrier Sense Not Asserted Error    */
-#define TX_LOSS         0x00004000      /* TX Frame Carrier Lost During TX Error                */
-#define TX_RETRY        0x00008000      /* TX Frame Successful After Retry                              */
-#define TX_FRLEN        0x07FF0000      /* TX Frame Length (Bytes)                                              */
-
-/* EMAC_MMC_CTL Masks                                                                                                                   */
-#define RSTC            0x00000001      /* Reset All Counters                                                   */
-#define CROLL           0x00000002      /* Counter Roll-Over Enable                                             */
-#define CCOR            0x00000004      /* Counter Clear-On-Read Mode Enable                    */
-#define MMCE            0x00000008      /* Enable MMC Counter Operation                                 */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks                                                                                      */
-#define RX_OK_CNT               0x00000001      /* RX Frames Received With No Errors                    */
-#define RX_FCS_CNT              0x00000002      /* RX Frames W/Frame Check Sequence Errors              */
-#define RX_ALIGN_CNT    0x00000004      /* RX Frames With Alignment Errors                              */
-#define RX_OCTET_CNT    0x00000008      /* RX Octets Received OK                                                */
-#define RX_LOST_CNT             0x00000010      /* RX Frames Lost Due To Internal MAC RX Error  */
-#define RX_UNI_CNT              0x00000020      /* Unicast RX Frames Received OK                                */
-#define RX_MULTI_CNT    0x00000040      /* Multicast RX Frames Received OK                              */
-#define RX_BROAD_CNT    0x00000080      /* Broadcast RX Frames Received OK                              */
-#define RX_IRL_CNT              0x00000100      /* RX Frames With In-Range Length Errors                */
-#define RX_ORL_CNT              0x00000200      /* RX Frames With Out-Of-Range Length Errors    */
-#define RX_LONG_CNT             0x00000400      /* RX Frames With Frame Too Long Errors                 */
-#define RX_MACCTL_CNT   0x00000800      /* MAC Control RX Frames Received                               */
-#define RX_OPCODE_CTL   0x00001000      /* Unsupported Op-Code RX Frames Received               */
-#define RX_PAUSE_CNT    0x00002000      /* PAUSEMAC Control RX Frames Received                  */
-#define RX_ALLF_CNT             0x00004000      /* All RX Frames Received                                               */
-#define RX_ALLO_CNT             0x00008000      /* All RX Octets Received                                               */
-#define RX_TYPED_CNT    0x00010000      /* Typed RX Frames Received                                             */
-#define RX_SHORT_CNT    0x00020000      /* RX Frame Fragments (< 64 Bytes) Received             */
-#define RX_EQ64_CNT             0x00040000      /* 64-Byte RX Frames Received                                   */
-#define RX_LT128_CNT    0x00080000      /* 65-127-Byte RX Frames Received                               */
-#define RX_LT256_CNT    0x00100000      /* 128-255-Byte RX Frames Received                              */
-#define RX_LT512_CNT    0x00200000      /* 256-511-Byte RX Frames Received                              */
-#define RX_LT1024_CNT   0x00400000      /* 512-1023-Byte RX Frames Received                             */
-#define RX_GE1024_CNT   0x00800000      /* 1024-Max-Byte RX Frames Received                             */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks                                                                                      */
-#define TX_OK_CNT               0x00000001      /* TX Frames Sent OK                                                    */
-#define TX_SCOLL_CNT    0x00000002      /* TX Frames With Single Collisions                             */
-#define TX_MCOLL_CNT    0x00000004      /* TX Frames With Multiple Collisions                   */
-#define TX_OCTET_CNT    0x00000008      /* TX Octets Sent OK                                                    */
-#define TX_DEFER_CNT    0x00000010      /* TX Frames With Deferred Transmission                 */
-#define TX_LATE_CNT             0x00000020      /* TX Frames With Late Collisions                               */
-#define TX_ABORTC_CNT   0x00000040      /* TX Frames Aborted Due To Excess Collisions   */
-#define TX_LOST_CNT             0x00000080      /* TX Frames Lost Due To Internal MAC TX Error  */
-#define TX_CRS_CNT              0x00000100      /* TX Frames With Carrier Sense Errors                  */
-#define TX_UNI_CNT              0x00000200      /* Unicast TX Frames Sent                                               */
-#define TX_MULTI_CNT    0x00000400      /* Multicast TX Frames Sent                                             */
-#define TX_BROAD_CNT    0x00000800      /* Broadcast TX Frames Sent                                             */
-#define TX_EXDEF_CTL    0x00001000      /* TX Frames With Excessive Deferral                    */
-#define TX_MACCTL_CNT   0x00002000      /* MAC Control TX Frames Sent                                   */
-#define TX_ALLF_CNT             0x00004000      /* All TX Frames Sent                                                   */
-#define TX_ALLO_CNT             0x00008000      /* All TX Octets Sent                                                   */
-#define TX_EQ64_CNT             0x00010000      /* 64-Byte TX Frames Sent                                               */
-#define TX_LT128_CNT    0x00020000      /* 65-127-Byte TX Frames Sent                                   */
-#define TX_LT256_CNT    0x00040000      /* 128-255-Byte TX Frames Sent                                  */
-#define TX_LT512_CNT    0x00080000      /* 256-511-Byte TX Frames Sent                                  */
-#define TX_LT1024_CNT   0x00100000      /* 512-1023-Byte TX Frames Sent                                 */
-#define TX_GE1024_CNT   0x00200000      /* 1024-Max-Byte TX Frames Sent                                 */
-#define TX_ABORT_CNT    0x00400000      /* TX Frames Aborted                                                    */
-
-#endif                          /* _DEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
deleted file mode 100644
index 7a964040870a..000000000000
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/dma.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 16
-
-#define CH_PPI                      0
-#define CH_EMAC_RX                  1
-#define CH_EMAC_TX                  2
-#define CH_SPORT0_RX            3
-#define CH_SPORT0_TX            4
-#define CH_SPORT1_RX            5
-#define CH_SPORT1_TX            6
-#define CH_SPI                      7
-#define CH_UART0_RX             8
-#define CH_UART0_TX             9
-#define CH_UART1_RX             10
-#define CH_UART1_TX             11
-
-#define CH_MEM_STREAM0_DEST     12       /* TX */
-#define CH_MEM_STREAM0_SRC      13       /* RX */
-#define CH_MEM_STREAM1_DEST     14       /* TX */
-#define CH_MEM_STREAM1_SRC      15       /* RX */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
deleted file mode 100644
index 2e68a8a1e730..000000000000
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/irq.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _BF537_IRQ_H_
-#define _BF537_IRQ_H_
-
-/*
- * Interrupt source definitions
- *            Event Source    Core Event Name
- * Core       Emulation               **
- * Events         (highest priority)  EMU         0
- *            Reset                   RST         1
- *            NMI                     NMI         2
- *            Exception               EVX         3
- *            Reserved                --          4
- *            Hardware Error          IVHW        5
- *            Core Timer              IVTMR       6
- *  .....
- *
- *            Softirq                 IVG14
- *            System Call    --
- *               (lowest priority)    IVG15
- */
-
-#define SYS_IRQS        39
-#define NR_PERI_INTS    32
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU             0   /*Emulation */
-#define IRQ_RST             1   /*reset */
-#define IRQ_NMI             2   /*Non Maskable */
-#define IRQ_EVX             3   /*Exception */
-#define IRQ_UNUSED          4   /*- unused interrupt*/
-#define IRQ_HWERR           5   /*Hardware Error */
-#define IRQ_CORETMR         6   /*Core timer */
-
-#define IRQ_PLL_WAKEUP      7   /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR       8   /*DMA Error (general) */
-#define IRQ_GENERIC_ERROR   9   /*GENERIC Error Interrupt */
-#define IRQ_RTC             10  /*RTC Interrupt */
-#define IRQ_PPI             11  /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX       12  /*DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX       13  /*DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX       14  /*DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX       15  /*DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI             16  /*TWI Interrupt */
-#define IRQ_SPI             17  /*DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX        18  /*DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX        19  /*DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX        20  /*DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX        21  /*DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX          22  /*CAN Receive Interrupt */
-#define IRQ_CAN_TX          23  /*CAN Transmit Interrupt */
-#define IRQ_MAC_RX          24  /*DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX          25  /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TMR0            26  /*Timer 0 */
-#define IRQ_TMR1            27  /*Timer 1 */
-#define IRQ_TMR2            28  /*Timer 2 */
-#define IRQ_TMR3            29  /*Timer 3 */
-#define IRQ_TMR4            30  /*Timer 4 */
-#define IRQ_TMR5            31  /*Timer 5 */
-#define IRQ_TMR6            32  /*Timer 6 */
-#define IRQ_TMR7            33  /*Timer 7 */
-#define IRQ_PROG_INTA       34  /* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
-#define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1        37  /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB         38        /* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH           38  /*Watch Dog Timer */
-
-#define IRQ_PPI_ERROR       42  /*PPI Error Interrupt */
-#define IRQ_CAN_ERROR       43  /*CAN Error Interrupt */
-#define IRQ_MAC_ERROR       44  /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR    45  /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR    46  /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR       47  /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR     48  /*UART Error Interrupt */
-#define IRQ_UART1_ERROR     49  /*UART Error Interrupt */
-
-#define IRQ_PF0         50
-#define IRQ_PF1         51
-#define IRQ_PF2         52
-#define IRQ_PF3         53
-#define IRQ_PF4         54
-#define IRQ_PF5         55
-#define IRQ_PF6         56
-#define IRQ_PF7         57
-#define IRQ_PF8         58
-#define IRQ_PF9         59
-#define IRQ_PF10        60
-#define IRQ_PF11        61
-#define IRQ_PF12        62
-#define IRQ_PF13        63
-#define IRQ_PF14        64
-#define IRQ_PF15        65
-
-#define IRQ_PG0         66
-#define IRQ_PG1         67
-#define IRQ_PG2         68
-#define IRQ_PG3         69
-#define IRQ_PG4         70
-#define IRQ_PG5         71
-#define IRQ_PG6         72
-#define IRQ_PG7         73
-#define IRQ_PG8         74
-#define IRQ_PG9         75
-#define IRQ_PG10        76
-#define IRQ_PG11        77
-#define IRQ_PG12        78
-#define IRQ_PG13        79
-#define IRQ_PG14        80
-#define IRQ_PG15        81
-
-#define IRQ_PH0         82
-#define IRQ_PH1         83
-#define IRQ_PH2         84
-#define IRQ_PH3         85
-#define IRQ_PH4         86
-#define IRQ_PH5         87
-#define IRQ_PH6         88
-#define IRQ_PH7         89
-#define IRQ_PH8         90
-#define IRQ_PH9         91
-#define IRQ_PH10        92
-#define IRQ_PH11        93
-#define IRQ_PH12        94
-#define IRQ_PH13        95
-#define IRQ_PH14        96
-#define IRQ_PH15        97
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define NR_IRQS     (IRQ_PH15+1)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS*/
-#define IRQ_PLL_WAKEUP_POS  0
-#define IRQ_DMA_ERROR_POS   4
-#define IRQ_ERROR_POS       8
-#define IRQ_RTC_POS         12
-#define IRQ_PPI_POS         16
-#define IRQ_SPORT0_RX_POS   20
-#define IRQ_SPORT0_TX_POS   24
-#define IRQ_SPORT1_RX_POS   28
-
-/* IAR1 BIT FIELDS*/
-#define IRQ_SPORT1_TX_POS   0
-#define IRQ_TWI_POS         4
-#define IRQ_SPI_POS         8
-#define IRQ_UART0_RX_POS    12
-#define IRQ_UART0_TX_POS    16
-#define IRQ_UART1_RX_POS    20
-#define IRQ_UART1_TX_POS    24
-#define IRQ_CAN_RX_POS      28
-
-/* IAR2 BIT FIELDS*/
-#define IRQ_CAN_TX_POS      0
-#define IRQ_MAC_RX_POS      4
-#define IRQ_MAC_TX_POS      8
-#define IRQ_TMR0_POS        12
-#define IRQ_TMR1_POS        16
-#define IRQ_TMR2_POS        20
-#define IRQ_TMR3_POS        24
-#define IRQ_TMR4_POS        28
-
-/* IAR3 BIT FIELDS*/
-#define IRQ_TMR5_POS        0
-#define IRQ_TMR6_POS        4
-#define IRQ_TMR7_POS        8
-#define IRQ_PROG_INTA_POS   12
-#define IRQ_PORTG_INTB_POS   16
-#define IRQ_MEM_DMA0_POS    20
-#define IRQ_MEM_DMA1_POS    24
-#define IRQ_WATCH_POS       28
-
-#endif                          /* _BF537_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
deleted file mode 100644
index f67698f670ca..000000000000
--- a/include/asm-blackfin/mach-bf537/mem_init.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
deleted file mode 100644
index 5c6726d6f3b1..000000000000
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/mem_map.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
- * rev:
- *
- * modified:
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MEM_MAP_537_H_
-#define _MEM_MAP_537_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x800
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF537 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-
-#ifdef CONFIG_BF537
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif /*CONFIG_BF537*/
-
-/* Memory Map for ADSP-BF536 processors */
-
-#ifdef CONFIG_BF536
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF804000
-#define L1_DATA_B_START     0xFF904000
-
-#define L1_CODE_LENGTH      0xC000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x4000
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Memory Map for ADSP-BF534 processors */
-
-#ifdef CONFIG_BF534
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
deleted file mode 100644
index 78fee6e0f237..000000000000
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE)    /* We additionally handle PORTJ */
-
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0        (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0        (GPIO_PH15 + 1)
-#define PORT_PJ1        (GPIO_PH15 + 2)
-#define PORT_PJ2        (GPIO_PH15 + 3)
-#define PORT_PJ3        (GPIO_PH15 + 4)
-#define PORT_PJ4        (GPIO_PH15 + 5)
-#define PORT_PJ5        (GPIO_PH15 + 6)
-#define PORT_PJ6        (GPIO_PH15 + 7)
-#define PORT_PJ7        (GPIO_PH15 + 8)
-#define PORT_PJ8        (GPIO_PH15 + 9)
-#define PORT_PJ9        (GPIO_PH15 + 10)
-#define PORT_PJ10       (GPIO_PH15 + 11)
-#define PORT_PJ11       (GPIO_PH15 + 12)
-
-#define P_MDC           (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO          (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL      (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA      (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX       (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX       (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxD2, \
-        P_MII0_ETxD3, \
-        P_MII0_ETxEN, \
-        P_MII0_TxCLK, \
-        P_MII0_PHYINT, \
-        P_MII0_COL, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxD2, \
-        P_MII0_ERxD3, \
-        P_MII0_ERxDV, \
-        P_MII0_ERxCLK, \
-        P_MII0_ERxER, \
-        P_MII0_CRS, \
-        P_MDC, \
-        P_MDIO, 0}
-
-
-#define P_RMII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxEN, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxER, \
-        P_RMII0_REF_CLK, \
-        P_RMII0_MDINT, \
-        P_RMII0_CRS_DV, \
-        P_MDC, \
-        P_MDIO, 0}
-#endif                                  /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
deleted file mode 100644
index 3ad59655881a..000000000000
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf548/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2007 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Error Exception when ISR context is not restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Mode Is Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Intialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Mobile DDR Operation Not Functional */
-#define ANOMALY_05000377 (1)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
deleted file mode 100644
index e748588e8930..000000000000
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/bf548.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  System MMR register and memory map for ADSP-BF548
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF548_H__
-#define __MACH_BF548_H__
-
-#define SUPPORTED_REVID 0
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR    0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF542)
-# define CPU   "BF542"
-# define CPUID 0x027c8000
-#elif defined(CONFIG_BF544)
-# define CPU "BF544"
-# define CPUID 0x027c8000
-#elif defined(CONFIG_BF547)
-# define CPU "BF547"
-#elif defined(CONFIG_BF548)
-# define CPU "BF548"
-# define CPUID 0x027c6000
-#elif defined(CONFIG_BF549)
-# define CPU "BF549"
-#else
-# define CPU "UNKNOWN"
-# define CPUID 0x0
-#endif
-
-#endif  /* __MACH_BF48_H__  */
diff --git a/include/asm-blackfin/mach-bf548/bf54x-lq043.h b/include/asm-blackfin/mach-bf548/bf54x-lq043.h
deleted file mode 100644
index 9c7ca62a45eb..000000000000
--- a/include/asm-blackfin/mach-bf548/bf54x-lq043.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef BF54X_LQ043_H
-#define BF54X_LQ043_H
-
-struct bfin_bf54xfb_val {
-        unsigned int    defval;
-        unsigned int    min;
-        unsigned int    max;
-};
-
-struct bfin_bf54xfb_mach_info {
-        unsigned char   fixed_syncs;    /* do not update sync/border */
-
-        /* LCD types */
-        int             type;
-
-        /* Screen size */
-        int             width;
-        int             height;
-
-        /* Screen info */
-        struct bfin_bf54xfb_val xres;
-        struct bfin_bf54xfb_val yres;
-        struct bfin_bf54xfb_val bpp;
-
-        /* GPIOs */
-        unsigned short          disp;
-
-};
-
-#endif /* BF54X_LQ043_H */
diff --git a/include/asm-blackfin/mach-bf548/bf54x_keys.h b/include/asm-blackfin/mach-bf548/bf54x_keys.h
deleted file mode 100644
index 1fb4ec77cc25..000000000000
--- a/include/asm-blackfin/mach-bf548/bf54x_keys.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _BFIN_KPAD_H
-#define _BFIN_KPAD_H
-
-struct bfin_kpad_platform_data {
-        int rows;
-        int cols;
-        const unsigned int *keymap;
-        unsigned short keymapsize;
-        unsigned short repeat;
-        u32 debounce_time;      /* in ns */
-        u32 coldrive_time;      /* in ns */
-        u32 keyup_test_interval; /* in ms */
-};
-
-#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
deleted file mode 100644
index 5e29446a8e03..000000000000
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-#define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
-#define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
-#define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-#define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
-
-#define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
-#define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
-
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
-#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int     uart_cts_pin;
-        int     uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART2_TX,
-        CH_UART2_RX,
-#endif
-#ifdef CONFIG_BFIN_UART2_CTSRTS
-        CONFIG_UART2_CTS_PIN,
-        CONFIG_UART2_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-        {
-        0xFFC03100,
-        IRQ_UART3_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART3_TX,
-        CH_UART3_RX,
-#endif
-        },
-#endif
-};
-
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
-#define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-        peripheral_request(P_UART1_RTS, DRIVER_NAME);
-        peripheral_request(P_UART1_CTS, DRIVER_NAME);
-#endif
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        peripheral_request(P_UART2_TX, DRIVER_NAME);
-        peripheral_request(P_UART2_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART3
-        peripheral_request(P_UART3_TX, DRIVER_NAME);
-        peripheral_request(P_UART3_RX, DRIVER_NAME);
-
-#ifdef CONFIG_BFIN_UART3_CTSRTS
-        peripheral_request(P_UART3_RTS, DRIVER_NAME);
-        peripheral_request(P_UART3_CTS, DRIVER_NAME);
-#endif
-#endif
-        SSYNC();
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
deleted file mode 100644
index c41f9cf00268..000000000000
--- a/include/asm-blackfin/mach-bf548/bfin_sir.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER_SET)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_LSR(port)    bfin_read16((port)->membase + OFFSET_LSR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_SET_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER_SET), v)
-#define SIR_UART_CLEAR_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LSR(port, v)  bfin_write16(((port)->membase + OFFSET_LSR), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_CLEAR_LSR(port)  bfin_write16(((port)->membase + OFFSET_LSR), -1)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-        CH_UART2_RX,
-        CH_UART2_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR3
-        {
-        0xFFC03100,
-        IRQ_UART3_RX,
-        CH_UART3_RX,
-        CH_UART3_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR2
-        ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR3
-        ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
deleted file mode 100644
index d6ee74ac0460..000000000000
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF548_FAMILY
-
-#include "bf548.h"
-#include "mem_map.h"
-#include "anomaly.h"
-
-#ifdef CONFIG_BF542
-#include "defBF542.h"
-#endif
-
-#ifdef CONFIG_BF544
-#include "defBF544.h"
-#endif
-
-#ifdef CONFIG_BF547
-#include "defBF547.h"
-#endif
-
-#ifdef CONFIG_BF548
-#include "defBF548.h"
-#endif
-
-#ifdef CONFIG_BF549
-#include "defBF549.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#ifdef CONFIG_BF542
-#include "cdefBF542.h"
-#endif
-#ifdef CONFIG_BF544
-#include "cdefBF544.h"
-#endif
-#ifdef CONFIG_BF547
-#include "cdefBF547.h"
-#endif
-#ifdef CONFIG_BF548
-#include "cdefBF548.h"
-#endif
-#ifdef CONFIG_BF549
-#include "cdefBF549.h"
-#endif
-
-/* UART 1*/
-#define bfin_read_UART_THR()            bfin_read_UART1_THR()
-#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
-#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
-#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
-#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
-#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
-#define bfin_read_UART_IER()            bfin_read_UART1_IER()
-#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
-#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
-#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
-#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
-#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
-#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
-#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
-#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
-#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
-#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
-#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
-#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
-#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
-#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
-#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-
-#endif
-
-/* MAP used DEFINES from BF533 to BF54x - so we don't need to change 
- * them in the driver, kernel, etc. */
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-/* UART 0*/
-
-/* DMA Channnel */
-#define bfin_read_CH_UART_RX()          bfin_read_CH_UART1_RX()
-#define bfin_write_CH_UART_RX(val)      bfin_write_CH_UART1_RX(val)
-#define bfin_read_CH_UART_TX()          bfin_read_CH_UART1_TX()
-#define bfin_write_CH_UART_TX(val)      bfin_write_CH_UART1_TX(val)
-#define CH_UART_RX                      CH_UART1_RX
-#define CH_UART_TX                      CH_UART1_TX
-
-/* System Interrupt Controller */
-#define bfin_read_IRQ_UART_RX()         bfin_read_IRQ_UART1_RX()
-#define bfin_write_IRQ_UART_RX(val)     bfin_write_IRQ_UART1_RX(val)
-#define bfin_read_IRQ_UART_TX()         bfin_read_IRQ_UART1_TX()
-#define bfin_write_IRQ_UART_TX(val)     bfin_write_IRQ_UART1_TX(val)
-#define bfin_read_IRQ_UART_ERROR()      bfin_read_IRQ_UART1_ERROR()
-#define bfin_write_IRQ_UART_ERROR(val)  bfin_write_IRQ_UART1_ERROR(val)
-#define IRQ_UART_RX                     IRQ_UART1_RX
-#define IRQ_UART_TX                     IRQ_UART1_TX
-#define IRQ_UART_ERROR                  IRQ_UART1_ERROR
-
-/* MMR Registers*/
-#define bfin_read_UART_THR()            bfin_read_UART1_THR()
-#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
-#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
-#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
-#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
-#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
-#define bfin_read_UART_IER()            bfin_read_UART1_IER()
-#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
-#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
-#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
-#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
-#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
-#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
-#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
-#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
-#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
-#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
-#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
-#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
-#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
-#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
-#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-
-#define BFIN_UART_THR                   UART1_THR
-#define BFIN_UART_RBR                   UART1_RBR
-#define BFIN_UART_DLL                   UART1_DLL
-#define BFIN_UART_IER                   UART1_IER
-#define BFIN_UART_DLH                   UART1_DLH
-#define BFIN_UART_IIR                   UART1_IIR
-#define BFIN_UART_LCR                   UART1_LCR
-#define BFIN_UART_MCR                   UART1_MCR
-#define BFIN_UART_LSR                   UART1_LSR
-#define BFIN_UART_SCR                   UART1_SCR
-#define BFIN_UART_GCTL                  UART1_GCTL
-
-#define BFIN_UART_NR_PORTS      4
-
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_GCTL             0x08    /* Global Control Register              */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
-#define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
-#define OFFSET_THR              0x28    /* Transmit Holding register            */
-#define OFFSET_RBR              0x2C    /* Receive Buffer register              */
-
-/* PLL_DIV Masks */
-#define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
-#define CCLK_DIV2 CSEL_DIV2     /* CCLK = VCO / 2 */
-#define CCLK_DIV4 CSEL_DIV4     /* CCLK = VCO / 4 */
-#define CCLK_DIV8 CSEL_DIV8     /* CCLK = VCO / 8 */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
deleted file mode 100644
index 60b9f77576f1..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF542.h
+++ /dev/null
@@ -1,590 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF542.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include all Core registers and bit definitions */
-#include "defBF542.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()                    bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)                bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()               bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)           bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()                   bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)               bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()                 bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)             bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()                   bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)               bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()               bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)           bfin_write16(KPAD_SOFTEVAL, val)
-
-#endif /* _CDEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
deleted file mode 100644
index ea9b4ab496f3..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF544.h
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF544.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include all Core registers and bit definitions */
-#include "defBF544.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h
deleted file mode 100644
index ba716277c00d..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF547.h
+++ /dev/null
@@ -1,832 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF547.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include all Core registers and bit definitions */
-#include "defBF548.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()       bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()      bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)  bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()       bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()        bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)    bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()       bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()      bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)  bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()       bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()        bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)    bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()      bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)  bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()     bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()      bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)  bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()       bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()       bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)   bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()      bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)  bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()       bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)   bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()         bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)     bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()         bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)     bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()      bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)  bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()       bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()           bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)       bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()           bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)       bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()         bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)     bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()         bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)     bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()      bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)  bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()       bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()         bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)     bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()         bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)     bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()        bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)    bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()        bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)    bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()        bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)    bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()        bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)    bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()        bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)    bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()        bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)    bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()        bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)    bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()        bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)    bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()        bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)    bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()        bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)    bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()        bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)    bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()        bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)    bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()        bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)    bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()        bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)    bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()        bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)    bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()         bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)     bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()          bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)      bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()        bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)    bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()       bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)   bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()      bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)  bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()     bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()      bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)  bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()     bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()          bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)      bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()           bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)       bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()           bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)       bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()          bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)      bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()           bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)       bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()           bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)       bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()           bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)       bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()           bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)       bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()           bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)       bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()       bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)   bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()     bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()           bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)       bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2  Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()            bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)        bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()           bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)       bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()           bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)       bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()          bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)      bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()         bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)     bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()          bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)      bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()       bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)   bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()      bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)  bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()          bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)      bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()      bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)  bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()         bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)     bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()        bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)    bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()        bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)    bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()        bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)    bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()        bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)    bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()        bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)    bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()        bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)    bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()        bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)    bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()        bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)    bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()        bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)    bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()           bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)       bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()         bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)     bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()         bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)     bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()         bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)     bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
deleted file mode 100644
index ae971ebff6a0..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF548.h
+++ /dev/null
@@ -1,1577 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF548.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include all Core registers and bit definitions */
-#include "defBF548.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()       bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()      bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)  bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()       bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()        bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)    bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()       bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()      bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)  bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()       bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()        bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)    bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()      bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)  bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()     bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()      bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)  bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()       bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()       bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)   bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()      bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)  bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()       bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)   bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()         bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)     bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()         bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)     bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()      bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)  bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()       bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()           bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)       bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()           bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)       bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()         bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)     bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()         bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)     bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()      bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)  bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()       bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()         bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)     bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()         bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)     bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()        bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)    bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()        bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)    bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()        bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)    bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()        bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)    bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()        bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)    bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()        bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)    bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()        bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)    bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()        bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)    bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()        bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)    bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()        bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)    bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()        bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)    bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()        bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)    bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()        bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)    bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()        bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)    bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()        bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)    bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()         bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)     bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()          bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)      bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()        bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)    bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()       bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)   bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()      bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)  bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()     bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()      bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)  bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()     bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()          bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)      bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()           bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)       bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()           bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)       bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()          bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)      bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()           bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)       bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()           bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)       bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()           bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)       bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()           bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)       bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()           bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)       bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()       bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)   bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()     bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()           bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)       bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2  Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()            bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)        bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()           bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)       bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()           bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)       bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()          bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)      bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()         bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)     bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()          bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)      bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()       bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)   bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()      bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)  bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()          bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)      bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()      bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)  bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()         bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)     bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()        bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)    bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()        bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)    bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()        bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)    bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()        bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)    bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()        bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)    bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()        bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)    bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()        bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)    bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()        bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)    bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()        bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)    bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()           bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)       bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()         bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)     bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()         bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)     bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()         bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)     bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
deleted file mode 100644
index 92d07d961999..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF549.h
+++ /dev/null
@@ -1,1863 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf549/cdefBF549.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include all Core registers and bit definitions */
-#include "defBF549.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()                   bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)               bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()                   bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)               bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()                  bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)              bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()                   bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)               bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()                   bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)               bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()                   bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)               bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()                   bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)               bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()                   bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)               bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()               bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)           bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()             bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val)         bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()                   bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)               bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
-
-/* MXVR Registers */
-
-#define bfin_read_MXVR_CONFIG()                 bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val)             bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0()                bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val)            bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1()                bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val)            bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0()             bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val)         bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1()             bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val)         bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0()               bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val)           bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1()               bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val)           bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION()               bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val)           bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION()           bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val)       bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY()                  bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val)              bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY()              bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val)          bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR()                  bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val)              bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR()                  bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val)              bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR()                  bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val)              bfin_write32(MXVR_AADDR, val)
-
-/* MXVR Allocation Table Registers */
-
-#define bfin_read_MXVR_ALLOC_0()                bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val)            bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1()                bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val)            bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2()                bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val)            bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3()                bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val)            bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4()                bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val)            bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5()                bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val)            bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6()                bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val)            bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7()                bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val)            bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8()                bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val)            bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9()                bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val)            bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10()               bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val)           bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11()               bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val)           bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12()               bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val)           bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13()               bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val)           bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14()               bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val)           bfin_write32(MXVR_ALLOC_14, val)
-
-/* MXVR Channel Assign Registers */
-
-#define bfin_read_MXVR_SYNC_LCHAN_0()           bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val)       bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1()           bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val)       bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2()           bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val)       bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3()           bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val)       bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4()           bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val)       bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5()           bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val)       bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6()           bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val)       bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7()           bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val)       bfin_write32(MXVR_SYNC_LCHAN_7, val)
-
-/* MXVR DMA0 Registers */
-
-#define bfin_read_MXVR_DMA0_CONFIG()            bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val)        bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR()        bfin_read32(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val)    bfin_write32(MXVR_DMA0_START_ADDR)
-#define bfin_read_MXVR_DMA0_COUNT()             bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val)         bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR()         bfin_read32(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val)     bfin_write32(MXVR_DMA0_CURR_ADDR)
-#define bfin_read_MXVR_DMA0_CURR_COUNT()        bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val)    bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-
-/* MXVR DMA1 Registers */
-
-#define bfin_read_MXVR_DMA1_CONFIG()            bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val)        bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR()        bfin_read32(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val)    bfin_write32(MXVR_DMA1_START_ADDR)
-#define bfin_read_MXVR_DMA1_COUNT()             bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val)         bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR()         bfin_read32(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val)     bfin_write32(MXVR_DMA1_CURR_ADDR)
-#define bfin_read_MXVR_DMA1_CURR_COUNT()        bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val)    bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-
-/* MXVR DMA2 Registers */
-
-#define bfin_read_MXVR_DMA2_CONFIG()            bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val)        bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR()        bfin_read32(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val)    bfin_write32(MXVR_DMA2_START_ADDR)
-#define bfin_read_MXVR_DMA2_COUNT()             bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val)         bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR()         bfin_read32(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val)     bfin_write32(MXVR_DMA2_CURR_ADDR)
-#define bfin_read_MXVR_DMA2_CURR_COUNT()        bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val)    bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-
-/* MXVR DMA3 Registers */
-
-#define bfin_read_MXVR_DMA3_CONFIG()            bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val)        bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR()        bfin_read32(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val)    bfin_write32(MXVR_DMA3_START_ADDR)
-#define bfin_read_MXVR_DMA3_COUNT()             bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val)         bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR()         bfin_read32(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val)     bfin_write32(MXVR_DMA3_CURR_ADDR)
-#define bfin_read_MXVR_DMA3_CURR_COUNT()        bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val)    bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-
-/* MXVR DMA4 Registers */
-
-#define bfin_read_MXVR_DMA4_CONFIG()            bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val)        bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR()        bfin_read32(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val)    bfin_write32(MXVR_DMA4_START_ADDR)
-#define bfin_read_MXVR_DMA4_COUNT()             bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val)         bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR()         bfin_read32(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val)     bfin_write32(MXVR_DMA4_CURR_ADDR)
-#define bfin_read_MXVR_DMA4_CURR_COUNT()        bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val)    bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-
-/* MXVR DMA5 Registers */
-
-#define bfin_read_MXVR_DMA5_CONFIG()            bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val)        bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR()        bfin_read32(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val)    bfin_write32(MXVR_DMA5_START_ADDR)
-#define bfin_read_MXVR_DMA5_COUNT()             bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val)         bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR()         bfin_read32(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val)     bfin_write32(MXVR_DMA5_CURR_ADDR)
-#define bfin_read_MXVR_DMA5_CURR_COUNT()        bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val)    bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-
-/* MXVR DMA6 Registers */
-
-#define bfin_read_MXVR_DMA6_CONFIG()            bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val)        bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR()        bfin_read32(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val)    bfin_write32(MXVR_DMA6_START_ADDR)
-#define bfin_read_MXVR_DMA6_COUNT()             bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val)         bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR()         bfin_read32(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val)     bfin_write32(MXVR_DMA6_CURR_ADDR)
-#define bfin_read_MXVR_DMA6_CURR_COUNT()        bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val)    bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-
-/* MXVR DMA7 Registers */
-
-#define bfin_read_MXVR_DMA7_CONFIG()            bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val)        bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR()        bfin_read32(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val)    bfin_write32(MXVR_DMA7_START_ADDR)
-#define bfin_read_MXVR_DMA7_COUNT()             bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val)         bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR()         bfin_read32(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val)     bfin_write32(MXVR_DMA7_CURR_ADDR)
-#define bfin_read_MXVR_DMA7_CURR_COUNT()        bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val)    bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-
-/* MXVR Asynch Packet Registers */
-
-#define bfin_read_MXVR_AP_CTL()                 bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val)             bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR()        bfin_read32(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val)    bfin_write32(MXVR_APRB_START_ADDR)
-#define bfin_read_MXVR_APRB_CURR_ADDR()         bfin_read32(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val)     bfin_write32(MXVR_APRB_CURR_ADDR)
-#define bfin_read_MXVR_APTB_START_ADDR()        bfin_read32(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val)    bfin_write32(MXVR_APTB_START_ADDR)
-#define bfin_read_MXVR_APTB_CURR_ADDR()         bfin_read32(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val)     bfin_write32(MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define bfin_read_MXVR_CM_CTL()                 bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val)             bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR()        bfin_read32(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val)    bfin_write32(MXVR_CMRB_START_ADDR)
-#define bfin_read_MXVR_CMRB_CURR_ADDR()         bfin_read32(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val)     bfin_write32(MXVR_CMRB_CURR_ADDR)
-#define bfin_read_MXVR_CMTB_START_ADDR()        bfin_read32(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val)    bfin_write32(MXVR_CMTB_START_ADDR)
-#define bfin_read_MXVR_CMTB_CURR_ADDR()         bfin_read32(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val)     bfin_write32(MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define bfin_read_MXVR_RRDB_START_ADDR()        bfin_read32(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val)    bfin_write32(MXVR_RRDB_START_ADDR)
-#define bfin_read_MXVR_RRDB_CURR_ADDR()         bfin_read32(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val)     bfin_write32(MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define bfin_read_MXVR_PAT_DATA_0()             bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val)         bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0()               bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val)           bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1()             bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val)         bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1()               bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val)           bfin_write32(MXVR_PAT_EN_1, val)
-
-/* MXVR Frame Counter Registers */
-
-#define bfin_read_MXVR_FRAME_CNT_0()            bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val)        bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1()            bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val)        bfin_write16(MXVR_FRAME_CNT_1, val)
-
-/* MXVR Routing Table Registers */
-
-#define bfin_read_MXVR_ROUTING_0()              bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val)          bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1()              bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val)          bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2()              bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val)          bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3()              bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val)          bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4()              bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val)          bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5()              bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val)          bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6()              bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val)          bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7()              bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val)          bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8()              bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val)          bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9()              bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val)          bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10()             bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val)         bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11()             bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val)         bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12()             bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val)         bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13()             bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val)         bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14()             bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val)         bfin_write32(MXVR_ROUTING_14, val)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define bfin_read_MXVR_BLOCK_CNT()              bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val)          bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL()                bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val)            bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL()             bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val)         bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL()              bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val)          bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL()                bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val)            bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT()               bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val)           bfin_write16(MXVR_SCLK_CNT, val)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)                bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
deleted file mode 100644
index 57ac8cb9b1f6..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ /dev/null
@@ -1,2750 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF54x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-#include <asm/blackfin.h>
-
-#include "defBF54x_base.h"
-#include <asm/system.h>
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define bfin_read_PLL_CTL()             bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()             bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)         bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()              bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()            bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)        bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()         bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)     bfin_write16(PLL_LOCKCNT, val)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID()              bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)          bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-#define bfin_read_SWRST()               bfin_read16(SWRST)
-#define bfin_write_SWRST(val)           bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()               bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)           bfin_write16(SYSCR, val)
-
-/* SIC Registers */
-
-#define bfin_read_SIC_IMASK0()          bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)      bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()          bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)      bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()          bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)      bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_IMASK(x)          bfin_read32(SIC_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val)    bfin_write32((SIC_IMASK0 + (x << 2)), val)
-
-#define bfin_read_SIC_ISR0()            bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)        bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()            bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)        bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()            bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)        bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_ISR(x)            bfin_read32(SIC_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val)      bfin_write32((SIC_ISR0 + (x << 2)), val)
-
-#define bfin_read_SIC_IWR0()            bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)        bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()            bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)        bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()            bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)        bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()            bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)        bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()            bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)        bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()            bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)        bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()            bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)        bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()            bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)        bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()            bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)        bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()            bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)        bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()            bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)        bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()            bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)        bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()            bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)        bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()           bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)       bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()           bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)       bfin_write32(SIC_IAR11, val)
-
-/* Watchdog Timer Registers */
-
-#define bfin_read_WDOG_CTL()            bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)        bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()            bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)        bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()           bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)       bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-#define bfin_read_RTC_STAT()            bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)        bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()            bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)        bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()           bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)       bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()           bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)       bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()           bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)       bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()            bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)        bfin_write16(RTC_PREN, val)
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_DLL()           bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)       bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()           bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)       bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()          bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)      bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()           bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)       bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()           bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)       bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()           bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)       bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()           bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)       bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()           bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)       bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()       bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)   bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()     bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()           bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)       bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()           bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)       bfin_write16(UART0_RBR, val)
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL()            bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)        bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()            bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)        bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()           bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)       bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()           bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)       bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()           bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)       bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()           bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)       bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()         bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)     bfin_write16(SPI0_SHADOW, val)
-
-/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPORT1 Registers */
-
-#define bfin_read_SPORT1_TCR1()         bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)     bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()         bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)     bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()      bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)  bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()       bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)   bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()           bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)       bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()           bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)       bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()         bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)     bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()         bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)     bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()      bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)  bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()       bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)   bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()         bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)     bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()         bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)     bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()        bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)    bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()        bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)    bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()        bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)    bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()        bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)    bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()        bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)    bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()        bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)    bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()        bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)    bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()        bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)    bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()        bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)    bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()        bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)    bfin_write32(SPORT1_MRCS3, val)
-
-/* Asynchronous Memory Control Registers */
-
-#define bfin_read_EBIU_AMGCTL()         bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)     bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()        bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)    bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()        bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)    bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()         bfin_read16(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)     bfin_write16(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()        bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)    bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()           bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)       bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()           bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)       bfin_write16(EBIU_FCTL, val)
-
-/* DDR Memory Control Registers */
-
-#define bfin_read_EBIU_DDRCTL0()        bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)    bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()        bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)    bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()        bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)    bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()        bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)    bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()         bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)     bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()         bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)     bfin_write32(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()         bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)     bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()         bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)     bfin_write16(EBIU_RSTCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-#define bfin_read_EBIU_DDRBRC0()        bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)    bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()        bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)    bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()        bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)    bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()        bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)    bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()        bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)    bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()        bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)    bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()        bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)    bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()        bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)    bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()        bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)    bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()        bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)    bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()        bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)    bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()        bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)    bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()        bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)    bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()        bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)    bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()        bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)    bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()        bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)    bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()        bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)    bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()        bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)    bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()        bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)    bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()         bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)     bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()         bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)     bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()         bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)     bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()         bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)     bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()        bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)    bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()        bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)    bfin_write32(EBIU_DDRMCCL, val)
-
-/* DMAC0 Registers */
-
-#define bfin_read_DMAC0_TCPER()         bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)     bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()         bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)     bfin_write16(DMAC0_TCCNT, val)
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-
-/* MDMA Stream 0 Registers */
-
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers */
-
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-
-/* EPPI1 Registers */
-
-#define bfin_read_EPPI1_STATUS()                bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)            bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()                bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)            bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()                bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)            bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()                bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)            bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()                bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)            bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()                 bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)             bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()                  bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)              bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()                bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)            bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()               bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)           bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()              bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val)          bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()             bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val)         bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()              bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val)          bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()             bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val)         bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()                  bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)              bfin_write32(EPPI1_CLIP, val)
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET()              bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val)          bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()            bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val)        bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST()               bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val)           bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN()                bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)            bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()              bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val)          bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()            bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val)        bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()            bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val)        bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR()          bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val)      bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()              bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val)          bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()                 bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)             bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET()              bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val)          bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()            bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val)        bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST()               bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val)           bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN()                bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)            bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()              bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val)          bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()            bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val)        bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()            bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val)        bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR()          bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val)      bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()              bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val)          bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()                 bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)             bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET()              bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val)          bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()            bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val)        bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST()               bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val)           bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN()                bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)            bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()              bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val)          bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()            bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val)        bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()            bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val)        bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR()          bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val)      bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()              bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val)          bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()                 bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)             bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET()              bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val)          bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()            bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val)        bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST()               bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val)           bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN()                bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)            bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()              bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val)          bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()            bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val)        bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()            bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val)        bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR()          bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val)      bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()              bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val)          bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()                 bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)             bfin_write32(PINT3_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER()           bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)       bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()               bfin_read16(PORTA)
-#define bfin_write_PORTA(val)           bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()           bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)       bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()         bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)     bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()       bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)   bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()     bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()          bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)      bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()           bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)       bfin_write32(PORTA_MUX, val)
-
-/* Port B Registers */
-
-#define bfin_read_PORTB_FER()           bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)       bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()               bfin_read16(PORTB)
-#define bfin_write_PORTB(val)           bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()           bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)       bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()         bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)     bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()       bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)   bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()     bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()          bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)      bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()           bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)       bfin_write32(PORTB_MUX, val)
-
-/* Port C Registers */
-
-#define bfin_read_PORTC_FER()           bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)       bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()               bfin_read16(PORTC)
-#define bfin_write_PORTC(val)           bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()           bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)       bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()         bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)     bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()       bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)   bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()     bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()          bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)      bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()           bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)       bfin_write32(PORTC_MUX, val)
-
-/* Port D Registers */
-
-#define bfin_read_PORTD_FER()           bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)       bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()               bfin_read16(PORTD)
-#define bfin_write_PORTD(val)           bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()           bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)       bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()         bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)     bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()       bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)   bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()     bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()          bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)      bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()           bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)       bfin_write32(PORTD_MUX, val)
-
-/* Port E Registers */
-
-#define bfin_read_PORTE_FER()           bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)       bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()               bfin_read16(PORTE)
-#define bfin_write_PORTE(val)           bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()           bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)       bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()         bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)     bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()       bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)   bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()     bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()          bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)      bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()           bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)       bfin_write32(PORTE_MUX, val)
-
-/* Port F Registers */
-
-#define bfin_read_PORTF_FER()           bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)       bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()               bfin_read16(PORTF)
-#define bfin_write_PORTF(val)           bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()           bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)       bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()         bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)     bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()       bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)   bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()     bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()          bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)      bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()           bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)       bfin_write32(PORTF_MUX, val)
-
-/* Port G Registers */
-
-#define bfin_read_PORTG_FER()           bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)       bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()               bfin_read16(PORTG)
-#define bfin_write_PORTG(val)           bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()           bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)       bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()         bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)     bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()       bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)   bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()     bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()          bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)      bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()           bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)       bfin_write32(PORTG_MUX, val)
-
-/* Port H Registers */
-
-#define bfin_read_PORTH_FER()           bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)       bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()               bfin_read16(PORTH)
-#define bfin_write_PORTH(val)           bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()           bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)       bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()         bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)     bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()       bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)   bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()     bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()          bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)      bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()           bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)       bfin_write32(PORTH_MUX, val)
-
-/* Port I Registers */
-
-#define bfin_read_PORTI_FER()           bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)       bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()               bfin_read16(PORTI)
-#define bfin_write_PORTI(val)           bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()           bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)       bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()         bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)     bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()       bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)   bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()     bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()          bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)      bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()           bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)       bfin_write32(PORTI_MUX, val)
-
-/* Port J Registers */
-
-#define bfin_read_PORTJ_FER()           bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)       bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()               bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)           bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()           bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)       bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()         bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)     bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()       bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)   bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()     bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()          bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)      bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()           bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)       bfin_write32(PORTJ_MUX, val)
-
-/* PWM Timer Registers */
-
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-/* Timer Groubfin_read_() of 8 */
-
-#define bfin_read_TIMER_ENABLE0()               bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)           bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()              bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val)          bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()               bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)           bfin_write32(TIMER_STATUS0, val)
-
-/* DMAC1 Registers */
-
-#define bfin_read_DMAC1_TCPER()                 bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)             bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()                 bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)             bfin_write16(DMAC1_TCCNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR()         bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val)     bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()            bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val)        bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()                bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)            bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()               bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)           bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()              bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val)          bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()               bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)           bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()              bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val)          bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR()         bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val)     bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()             bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val)         bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()            bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val)        bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP()        bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val)    bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT()          bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val)      bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT()          bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val)      bfin_write16(DMA12_CURR_Y_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR()         bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val)     bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()            bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val)        bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()                bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)            bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()               bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)           bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()              bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val)          bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()               bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)           bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()              bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val)          bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR()         bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val)     bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()             bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val)         bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()            bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val)        bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP()        bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val)    bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT()          bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val)      bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT()          bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val)      bfin_write16(DMA13_CURR_Y_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR()         bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val)     bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()            bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val)        bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()                bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)            bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()               bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)           bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()              bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val)          bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()               bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)           bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()              bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val)          bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR()         bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val)     bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()             bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val)         bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()            bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val)        bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP()        bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val)    bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT()          bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val)      bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT()          bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val)      bfin_write16(DMA14_CURR_Y_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR()         bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val)     bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()            bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val)        bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()                bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)            bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()               bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)           bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()              bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val)          bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()               bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)           bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()              bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val)          bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR()         bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val)     bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()             bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val)         bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()            bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val)        bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP()        bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val)    bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT()          bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val)      bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT()          bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val)      bfin_write16(DMA15_CURR_Y_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR()         bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val)     bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()            bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val)        bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()                bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)            bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()               bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)           bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()              bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val)          bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()               bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)           bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()              bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val)          bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR()         bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val)     bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()             bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val)         bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()            bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val)        bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP()        bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val)    bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT()          bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val)      bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT()          bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val)      bfin_write16(DMA16_CURR_Y_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR()         bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val)     bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()            bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val)        bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()                bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)            bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()               bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)           bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()              bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val)          bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()               bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)           bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()              bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val)          bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR()         bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val)     bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()             bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val)         bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()            bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val)        bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP()        bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val)    bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT()          bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val)      bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT()          bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val)      bfin_write16(DMA17_CURR_Y_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR()         bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val)     bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()            bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val)        bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()                bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)            bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()               bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)           bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()              bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val)          bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()               bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)           bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()              bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val)          bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR()         bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val)     bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()             bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val)         bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()            bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val)        bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP()        bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val)    bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT()          bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val)      bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT()          bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val)      bfin_write16(DMA18_CURR_Y_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR()         bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val)     bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()            bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val)        bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()                bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)            bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()               bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)           bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()              bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val)          bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()               bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)           bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()              bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val)          bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR()         bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val)     bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()             bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val)         bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()            bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val)        bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP()        bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val)    bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT()          bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val)      bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT()          bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val)      bfin_write16(DMA19_CURR_Y_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR()         bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val)     bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()            bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val)        bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()                bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)            bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()               bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)           bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()              bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val)          bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()               bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)           bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()              bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val)          bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR()         bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val)     bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()             bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val)         bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()            bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val)        bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP()        bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val)    bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT()          bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val)      bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT()          bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val)      bfin_write16(DMA20_CURR_Y_COUNT, val)
-
-/* DMA Channel 21 Registers */
-
-#define bfin_read_DMA21_NEXT_DESC_PTR()         bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val)     bfin_write32(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()            bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val)        bfin_write32(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()                bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)            bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()               bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)           bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()              bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val)          bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()               bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)           bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()              bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val)          bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR()         bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val)     bfin_write32(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()             bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val)         bfin_write32(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()            bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val)        bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP()        bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val)    bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT()          bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val)      bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT()          bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val)      bfin_write16(DMA21_CURR_Y_COUNT, val)
-
-/* DMA Channel 22 Registers */
-
-#define bfin_read_DMA22_NEXT_DESC_PTR()         bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val)     bfin_write32(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()            bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val)        bfin_write32(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()                bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)            bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()               bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)           bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()              bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val)          bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()               bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)           bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()              bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val)          bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR()         bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val)     bfin_write32(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()             bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val)         bfin_write32(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()            bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val)        bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP()        bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val)    bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT()          bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val)      bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT()          bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val)      bfin_write16(DMA22_CURR_Y_COUNT, val)
-
-/* DMA Channel 23 Registers */
-
-#define bfin_read_DMA23_NEXT_DESC_PTR()                 bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val)             bfin_write32(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()                    bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val)                bfin_write32(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()                        bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)                    bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()                       bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)                   bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()                      bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val)                  bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()                       bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)                   bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()                      bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val)                  bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR()                 bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val)             bfin_write32(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()                     bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val)                 bfin_write32(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()                    bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val)                bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP()                bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val)            bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT()                  bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val)              bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT()                  bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val)              bfin_write16(DMA23_CURR_Y_COUNT, val)
-
-/* MDMA Stream 2 Registers */
-
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR()               bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val)           bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR()                  bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val)              bfin_write32(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()                      bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val)                  bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()                     bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val)                 bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()                    bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val)                bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()                     bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val)                 bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()                    bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val)                bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR()               bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val)           bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()                   bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val)               bfin_write32(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS()                  bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val)              bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP()              bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val)          bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT()                bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val)            bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT()                bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val)            bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR()               bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val)           bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR()                  bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val)              bfin_write32(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()                      bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val)                  bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()                     bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val)                 bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()                    bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val)                bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()                     bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val)                 bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()                    bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val)                bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR()               bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val)           bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()                   bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val)               bfin_write32(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS()                  bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val)              bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP()              bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val)          bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT()                bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val)            bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT()                bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val)            bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers */
-
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR()               bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val)           bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR()                  bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val)              bfin_write32(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()                      bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val)                  bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()                     bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val)                 bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()                    bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val)                bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()                     bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val)                 bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()                    bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val)                bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR()               bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val)           bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()                   bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val)               bfin_write32(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS()                  bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val)              bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP()              bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val)          bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT()                bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val)            bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT()                bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val)            bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR()               bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val)           bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR()                  bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val)              bfin_write32(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()                      bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val)                  bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()                     bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val)                 bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()                    bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val)                bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()                     bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val)                 bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()                    bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val)                bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR()               bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val)           bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()                   bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val)               bfin_write32(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS()                  bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val)              bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP()              bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val)          bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT()                bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val)            bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT()                bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val)            bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()               bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)           bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()             bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val)         bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL()                    bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)                bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()                    bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)                bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()                   bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)               bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()                   bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)               bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()                   bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)               bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()                   bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)               bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()                 bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)             bfin_write16(SPI1_SHADOW, val)
-
-/* SPORT2 Registers */
-
-#define bfin_read_SPORT2_TCR1()                 bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)             bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()                 bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)             bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()              bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val)          bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()               bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)           bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX()                   bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val)               bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX()                   bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)               bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1()                 bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)             bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()                 bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)             bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()              bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val)          bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()               bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)           bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT()                 bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)             bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL()                 bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)             bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1()                bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)            bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()                bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)            bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0()                bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)            bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()                bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)            bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()                bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)            bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()                bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)            bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0()                bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)            bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()                bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)            bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()                bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)            bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()                bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)            bfin_write32(SPORT2_MRCS3, val)
-
-/* SPORT3 Registers */
-
-#define bfin_read_SPORT3_TCR1()                 bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)             bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()                 bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)             bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()              bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val)          bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()               bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)           bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX()                   bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val)               bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX()                   bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)               bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1()                 bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)             bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()                 bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)             bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()              bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val)          bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()               bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)           bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT()                 bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)             bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL()                 bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)             bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1()                bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)            bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()                bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)            bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0()                bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)            bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()                bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)            bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()                bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)            bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()                bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)            bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0()                bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)            bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()                bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)            bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()                bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)            bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()                bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)            bfin_write32(SPORT3_MRCS3, val)
-
-/* EPPI2 Registers */
-
-#define bfin_read_EPPI2_STATUS()                bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)            bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()                bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)            bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()                bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)            bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()                bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)            bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()                bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)            bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()                 bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)             bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()                  bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)              bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()                bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)            bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()               bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)           bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()              bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val)          bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()             bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val)         bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()              bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val)          bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()             bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val)         bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()                  bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)              bfin_write32(EPPI2_CLIP, val)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1()            bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)        bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()            bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)        bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()           bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)       bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()           bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)       bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()            bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)        bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()            bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)        bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()           bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)       bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()           bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)       bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()         bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)     bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()         bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)     bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()          bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)      bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()           bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)       bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()          bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)      bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2()            bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)        bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()            bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)        bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()           bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)       bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()           bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)       bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()            bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)        bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()            bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)        bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()           bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)       bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()           bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)       bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()         bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)     bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()         bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)     bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()          bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)      bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()           bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)       bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()          bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)      bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK()          bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)      bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()         bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)     bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()          bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)      bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()         bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)     bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()            bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)        bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()            bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)        bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()            bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)        bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()            bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)        bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()        bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)    bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()           bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)       bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()           bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)       bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()            bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)        bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()            bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)        bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()          bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)      bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()           bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)       bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()          bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)      bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L()          bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)      bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()          bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)      bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()          bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)      bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()          bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)      bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()          bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)      bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()          bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)      bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()          bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)      bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()          bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)      bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()          bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)      bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()          bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)      bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()          bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)      bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()          bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)      bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()          bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)      bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()          bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)      bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()          bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)      bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()          bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)      bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()          bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)      bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()          bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)      bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()          bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)      bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()          bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)      bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()          bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)      bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()          bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)      bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()          bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)      bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()          bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)      bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()          bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)      bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()          bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)      bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()          bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)      bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()          bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)      bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()          bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)      bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()          bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)      bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()          bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)      bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()          bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)      bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L()          bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)      bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()          bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)      bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()          bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)      bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()          bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)      bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()          bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)      bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()          bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)      bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()          bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)      bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()          bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)      bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()          bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)      bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()          bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)      bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()          bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)      bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()          bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)      bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()          bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)      bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()          bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)      bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()          bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)      bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()          bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)      bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()          bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)      bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()          bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)      bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()          bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)      bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()          bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)      bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()          bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)      bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()          bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)      bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()          bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)      bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()          bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)      bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()          bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)      bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()          bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)      bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()          bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)      bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()          bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)      bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()          bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)      bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()          bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)      bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()          bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)      bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()          bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)      bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0()             bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val)         bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()             bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val)         bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()             bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val)         bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()             bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val)         bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()            bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val)        bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP()         bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val)     bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()               bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)           bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()               bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)           bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()             bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val)         bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()             bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val)         bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()             bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val)         bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()             bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val)         bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()            bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val)        bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP()         bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val)     bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()               bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)           bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()               bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)           bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()             bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val)         bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()             bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val)         bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()             bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val)         bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()             bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val)         bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()            bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val)        bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP()         bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val)     bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()               bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)           bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()               bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)           bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()             bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val)         bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()             bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val)         bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()             bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val)         bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()             bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val)         bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()            bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val)        bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP()         bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val)     bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()               bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)           bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()               bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)           bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()             bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val)         bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()             bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val)         bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()             bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val)         bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()             bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val)         bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()            bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val)        bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP()         bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val)     bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()               bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)           bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()               bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)           bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()             bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val)         bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()             bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val)         bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()             bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val)         bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()             bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val)         bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()            bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val)        bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP()         bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val)     bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()               bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)           bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()               bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)           bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()             bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val)         bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()             bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val)         bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()             bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val)         bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()             bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val)         bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()            bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val)        bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP()         bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val)     bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()               bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)           bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()               bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)           bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()             bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val)         bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()             bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val)         bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()             bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val)         bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()             bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val)         bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()            bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val)        bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP()         bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val)     bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()               bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)           bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()               bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)           bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()             bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val)         bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()             bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val)         bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()             bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val)         bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()             bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val)         bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()            bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val)        bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP()         bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val)     bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()               bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)           bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()               bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)           bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()             bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val)         bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()             bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val)         bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()             bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val)         bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()             bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val)         bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()            bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val)        bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP()         bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val)     bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()               bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)           bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()               bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)           bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()             bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val)         bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()             bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val)         bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()             bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val)         bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()             bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val)         bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()            bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val)        bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP()         bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val)     bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()               bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)           bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()               bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)           bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()             bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val)         bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()             bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val)         bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()             bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val)         bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()             bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val)         bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()            bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val)        bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP()         bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val)     bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()               bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)           bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()               bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)           bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()             bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val)         bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()             bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val)         bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()             bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val)         bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()             bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val)         bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()            bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val)        bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP()         bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val)     bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()               bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)           bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()               bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)           bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()             bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val)         bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()             bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val)         bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()             bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val)         bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()             bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val)         bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()            bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val)        bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP()         bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val)     bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()               bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)           bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()               bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)           bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()             bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val)         bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()             bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val)         bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()             bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val)         bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()             bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val)         bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()            bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val)        bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP()         bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val)     bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()               bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)           bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()               bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)           bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()             bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val)         bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()             bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val)         bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()             bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val)         bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()             bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val)         bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()            bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val)        bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP()         bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val)     bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()               bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)           bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()               bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)           bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0()             bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val)         bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()             bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val)         bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()             bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val)         bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()             bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val)         bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()            bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val)        bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP()         bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val)     bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()               bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)           bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()               bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)           bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()             bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val)         bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()             bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val)         bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()             bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val)         bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()             bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val)         bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()            bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val)        bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP()         bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val)     bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()               bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)           bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()               bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)           bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()             bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val)         bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()             bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val)         bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()             bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val)         bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()             bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val)         bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()            bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val)        bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP()         bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val)     bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()               bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)           bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()               bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)           bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()             bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val)         bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()             bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val)         bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()             bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val)         bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()             bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val)         bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()            bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val)        bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP()         bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val)     bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()               bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)           bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()               bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)           bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()             bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val)         bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()             bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val)         bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()             bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val)         bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()             bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val)         bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()            bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val)        bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP()         bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val)     bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()               bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)           bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()               bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)           bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()             bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val)         bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()             bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val)         bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()             bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val)         bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()             bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val)         bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()            bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val)        bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP()         bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val)     bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()               bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)           bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()               bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)           bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()             bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val)         bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()             bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val)         bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()             bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val)         bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()             bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val)         bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()            bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val)        bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP()         bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val)     bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()               bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)           bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()               bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)           bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()             bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val)         bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()             bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val)         bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()             bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val)         bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()             bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val)         bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()            bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val)        bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP()         bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val)     bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()               bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)           bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()               bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)           bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()             bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val)         bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()             bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val)         bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()             bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val)         bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()             bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val)         bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()            bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val)        bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP()         bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val)     bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()               bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)           bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()               bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)           bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()             bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val)         bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()             bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val)         bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()             bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val)         bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()             bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val)         bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()            bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val)        bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP()         bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val)     bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()               bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)           bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()               bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)           bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()             bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val)         bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()             bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val)         bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()             bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val)         bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()             bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val)         bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()            bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val)        bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP()         bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val)     bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()               bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)           bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()               bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)           bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()             bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val)         bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()             bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val)         bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()             bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val)         bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()             bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val)         bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()            bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val)        bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP()         bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val)     bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()               bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)           bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()               bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)           bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()             bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val)         bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()             bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val)         bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()             bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val)         bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()             bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val)         bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()            bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val)        bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP()         bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val)     bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()               bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)           bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()               bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)           bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()             bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val)         bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()             bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val)         bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()             bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val)         bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()             bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val)         bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()            bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val)        bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP()         bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val)     bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()               bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)           bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()               bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)           bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()             bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val)         bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()             bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val)         bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()             bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val)         bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()             bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val)         bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()            bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val)        bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP()         bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val)     bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()               bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)           bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()               bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)           bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()             bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val)         bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()             bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val)         bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()             bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val)         bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()             bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val)         bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()            bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val)        bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP()         bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val)     bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()               bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)           bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()               bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)           bfin_write16(CAN0_MB31_ID1, val)
-
-/* UART3 Registers */
-
-#define bfin_read_UART3_DLL()           bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)       bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()           bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)       bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()          bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)      bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()           bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)       bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()           bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)       bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()           bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)       bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()           bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)       bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()           bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)       bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()       bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)   bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()     bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()           bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)       bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()           bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)       bfin_write16(UART3_RBR, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()             bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)         bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()            bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)        bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()         bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)     bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()         bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)     bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()            bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)        bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()            bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)        bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()            bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)        bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()            bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)        bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()           bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)       bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()             bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)         bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()           bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)       bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()            bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)        bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()            bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)        bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()             bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)         bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()         bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)     bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()         bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)     bfin_write16(NFC_DATA_RD, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()          bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)      bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()           bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)       bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()          bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)      bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()         bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)     bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()        bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)    bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()         bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)     bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()             bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)         bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()             bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)         bfin_write32(CNT_MIN, val)
-
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()         bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)     bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()             bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)         bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()          bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)      bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()          bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)      bfin_write32(OTP_TIMING, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()       bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)   bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()      bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)  bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()       bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)   bfin_write16(SECURE_STATUS, val)
-
-/* DMA Peribfin_read_()heral Mux Register */
-
-#define bfin_read_DMAC1_PERIMUX()       bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)   bfin_write16(DMAC1_PERIMUX, val)
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()           bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)       bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()           bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)       bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()           bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)       bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()           bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)       bfin_write32(OTP_DATA3, val)
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
-
-/* legacy definitions */
-#define bfin_read_EBIU_AMCBCTL0         bfin_read_EBIU_AMBCTL0
-#define bfin_write_EBIU_AMCBCTL0        bfin_write_EBIU_AMBCTL0
-#define bfin_read_EBIU_AMCBCTL1         bfin_read_EBIU_AMBCTL1
-#define bfin_write_EBIU_AMCBCTL1        bfin_write_EBIU_AMBCTL1
-#define bfin_read_PINT0_IRQ             bfin_read_PINT0_REQUEST
-#define bfin_write_PINT0_IRQ            bfin_write_PINT0_REQUEST
-#define bfin_read_PINT1_IRQ             bfin_read_PINT1_REQUEST
-#define bfin_write_PINT1_IRQ            bfin_write_PINT1_REQUEST
-#define bfin_read_PINT2_IRQ             bfin_read_PINT2_REQUEST
-#define bfin_write_PINT2_IRQ            bfin_write_PINT2_REQUEST
-#define bfin_read_PINT3_IRQ             bfin_read_PINT3_REQUEST
-#define bfin_write_PINT3_IRQ            bfin_write_PINT3_REQUEST
-
-#endif /* _CDEF_BF54X_H */
-
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
deleted file mode 100644
index a7c809f29ede..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ /dev/null
@@ -1,925 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF542.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
deleted file mode 100644
index b8b9870e2697..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ /dev/null
@@ -1,707 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF544.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                  COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                   TIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-#endif /* _DEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF547.h b/include/asm-blackfin/mach-bf548/defBF547.h
deleted file mode 100644
index 3a3a18ebb10e..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF547.h
+++ /dev/null
@@ -1,1244 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF547.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
deleted file mode 100644
index 1d7c96edb038..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ /dev/null
@@ -1,1627 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF548.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
deleted file mode 100644
index fcb72b41e007..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ /dev/null
@@ -1,2737 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF549.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* MXVR Registers */
-
-#define                      MXVR_CONFIG  0xffc02700   /* MXVR Configuration Register */
-#define                     MXVR_STATE_0  0xffc02708   /* MXVR State Register 0 */
-#define                     MXVR_STATE_1  0xffc0270c   /* MXVR State Register 1 */
-#define                  MXVR_INT_STAT_0  0xffc02710   /* MXVR Interrupt Status Register 0 */
-#define                  MXVR_INT_STAT_1  0xffc02714   /* MXVR Interrupt Status Register 1 */
-#define                    MXVR_INT_EN_0  0xffc02718   /* MXVR Interrupt Enable Register 0 */
-#define                    MXVR_INT_EN_1  0xffc0271c   /* MXVR Interrupt Enable Register 1 */
-#define                    MXVR_POSITION  0xffc02720   /* MXVR Node Position Register */
-#define                MXVR_MAX_POSITION  0xffc02724   /* MXVR Maximum Node Position Register */
-#define                       MXVR_DELAY  0xffc02728   /* MXVR Node Frame Delay Register */
-#define                   MXVR_MAX_DELAY  0xffc0272c   /* MXVR Maximum Node Frame Delay Register */
-#define                       MXVR_LADDR  0xffc02730   /* MXVR Logical Address Register */
-#define                       MXVR_GADDR  0xffc02734   /* MXVR Group Address Register */
-#define                       MXVR_AADDR  0xffc02738   /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define                     MXVR_ALLOC_0  0xffc0273c   /* MXVR Allocation Table Register 0 */
-#define                     MXVR_ALLOC_1  0xffc02740   /* MXVR Allocation Table Register 1 */
-#define                     MXVR_ALLOC_2  0xffc02744   /* MXVR Allocation Table Register 2 */
-#define                     MXVR_ALLOC_3  0xffc02748   /* MXVR Allocation Table Register 3 */
-#define                     MXVR_ALLOC_4  0xffc0274c   /* MXVR Allocation Table Register 4 */
-#define                     MXVR_ALLOC_5  0xffc02750   /* MXVR Allocation Table Register 5 */
-#define                     MXVR_ALLOC_6  0xffc02754   /* MXVR Allocation Table Register 6 */
-#define                     MXVR_ALLOC_7  0xffc02758   /* MXVR Allocation Table Register 7 */
-#define                     MXVR_ALLOC_8  0xffc0275c   /* MXVR Allocation Table Register 8 */
-#define                     MXVR_ALLOC_9  0xffc02760   /* MXVR Allocation Table Register 9 */
-#define                    MXVR_ALLOC_10  0xffc02764   /* MXVR Allocation Table Register 10 */
-#define                    MXVR_ALLOC_11  0xffc02768   /* MXVR Allocation Table Register 11 */
-#define                    MXVR_ALLOC_12  0xffc0276c   /* MXVR Allocation Table Register 12 */
-#define                    MXVR_ALLOC_13  0xffc02770   /* MXVR Allocation Table Register 13 */
-#define                    MXVR_ALLOC_14  0xffc02774   /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define                MXVR_SYNC_LCHAN_0  0xffc02778   /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define                MXVR_SYNC_LCHAN_1  0xffc0277c   /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define                MXVR_SYNC_LCHAN_2  0xffc02780   /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define                MXVR_SYNC_LCHAN_3  0xffc02784   /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define                MXVR_SYNC_LCHAN_4  0xffc02788   /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define                MXVR_SYNC_LCHAN_5  0xffc0278c   /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define                MXVR_SYNC_LCHAN_6  0xffc02790   /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define                MXVR_SYNC_LCHAN_7  0xffc02794   /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define                 MXVR_DMA0_CONFIG  0xffc02798   /* MXVR Sync Data DMA0 Config Register */
-#define             MXVR_DMA0_START_ADDR  0xffc0279c   /* MXVR Sync Data DMA0 Start Address */
-#define                  MXVR_DMA0_COUNT  0xffc027a0   /* MXVR Sync Data DMA0 Loop Count Register */
-#define              MXVR_DMA0_CURR_ADDR  0xffc027a4   /* MXVR Sync Data DMA0 Current Address */
-#define             MXVR_DMA0_CURR_COUNT  0xffc027a8   /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define                 MXVR_DMA1_CONFIG  0xffc027ac   /* MXVR Sync Data DMA1 Config Register */
-#define             MXVR_DMA1_START_ADDR  0xffc027b0   /* MXVR Sync Data DMA1 Start Address */
-#define                  MXVR_DMA1_COUNT  0xffc027b4   /* MXVR Sync Data DMA1 Loop Count Register */
-#define              MXVR_DMA1_CURR_ADDR  0xffc027b8   /* MXVR Sync Data DMA1 Current Address */
-#define             MXVR_DMA1_CURR_COUNT  0xffc027bc   /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define                 MXVR_DMA2_CONFIG  0xffc027c0   /* MXVR Sync Data DMA2 Config Register */
-#define             MXVR_DMA2_START_ADDR  0xffc027c4   /* MXVR Sync Data DMA2 Start Address */
-#define                  MXVR_DMA2_COUNT  0xffc027c8   /* MXVR Sync Data DMA2 Loop Count Register */
-#define              MXVR_DMA2_CURR_ADDR  0xffc027cc   /* MXVR Sync Data DMA2 Current Address */
-#define             MXVR_DMA2_CURR_COUNT  0xffc027d0   /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define                 MXVR_DMA3_CONFIG  0xffc027d4   /* MXVR Sync Data DMA3 Config Register */
-#define             MXVR_DMA3_START_ADDR  0xffc027d8   /* MXVR Sync Data DMA3 Start Address */
-#define                  MXVR_DMA3_COUNT  0xffc027dc   /* MXVR Sync Data DMA3 Loop Count Register */
-#define              MXVR_DMA3_CURR_ADDR  0xffc027e0   /* MXVR Sync Data DMA3 Current Address */
-#define             MXVR_DMA3_CURR_COUNT  0xffc027e4   /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define                 MXVR_DMA4_CONFIG  0xffc027e8   /* MXVR Sync Data DMA4 Config Register */
-#define             MXVR_DMA4_START_ADDR  0xffc027ec   /* MXVR Sync Data DMA4 Start Address */
-#define                  MXVR_DMA4_COUNT  0xffc027f0   /* MXVR Sync Data DMA4 Loop Count Register */
-#define              MXVR_DMA4_CURR_ADDR  0xffc027f4   /* MXVR Sync Data DMA4 Current Address */
-#define             MXVR_DMA4_CURR_COUNT  0xffc027f8   /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define                 MXVR_DMA5_CONFIG  0xffc027fc   /* MXVR Sync Data DMA5 Config Register */
-#define             MXVR_DMA5_START_ADDR  0xffc02800   /* MXVR Sync Data DMA5 Start Address */
-#define                  MXVR_DMA5_COUNT  0xffc02804   /* MXVR Sync Data DMA5 Loop Count Register */
-#define              MXVR_DMA5_CURR_ADDR  0xffc02808   /* MXVR Sync Data DMA5 Current Address */
-#define             MXVR_DMA5_CURR_COUNT  0xffc0280c   /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define                 MXVR_DMA6_CONFIG  0xffc02810   /* MXVR Sync Data DMA6 Config Register */
-#define             MXVR_DMA6_START_ADDR  0xffc02814   /* MXVR Sync Data DMA6 Start Address */
-#define                  MXVR_DMA6_COUNT  0xffc02818   /* MXVR Sync Data DMA6 Loop Count Register */
-#define              MXVR_DMA6_CURR_ADDR  0xffc0281c   /* MXVR Sync Data DMA6 Current Address */
-#define             MXVR_DMA6_CURR_COUNT  0xffc02820   /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define                 MXVR_DMA7_CONFIG  0xffc02824   /* MXVR Sync Data DMA7 Config Register */
-#define             MXVR_DMA7_START_ADDR  0xffc02828   /* MXVR Sync Data DMA7 Start Address */
-#define                  MXVR_DMA7_COUNT  0xffc0282c   /* MXVR Sync Data DMA7 Loop Count Register */
-#define              MXVR_DMA7_CURR_ADDR  0xffc02830   /* MXVR Sync Data DMA7 Current Address */
-#define             MXVR_DMA7_CURR_COUNT  0xffc02834   /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define                      MXVR_AP_CTL  0xffc02838   /* MXVR Async Packet Control Register */
-#define             MXVR_APRB_START_ADDR  0xffc0283c   /* MXVR Async Packet RX Buffer Start Addr Register */
-#define              MXVR_APRB_CURR_ADDR  0xffc02840   /* MXVR Async Packet RX Buffer Current Addr Register */
-#define             MXVR_APTB_START_ADDR  0xffc02844   /* MXVR Async Packet TX Buffer Start Addr Register */
-#define              MXVR_APTB_CURR_ADDR  0xffc02848   /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define                      MXVR_CM_CTL  0xffc0284c   /* MXVR Control Message Control Register */
-#define             MXVR_CMRB_START_ADDR  0xffc02850   /* MXVR Control Message RX Buffer Start Addr Register */
-#define              MXVR_CMRB_CURR_ADDR  0xffc02854   /* MXVR Control Message RX Buffer Current Address */
-#define             MXVR_CMTB_START_ADDR  0xffc02858   /* MXVR Control Message TX Buffer Start Addr Register */
-#define              MXVR_CMTB_CURR_ADDR  0xffc0285c   /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define             MXVR_RRDB_START_ADDR  0xffc02860   /* MXVR Remote Read Buffer Start Addr Register */
-#define              MXVR_RRDB_CURR_ADDR  0xffc02864   /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define                  MXVR_PAT_DATA_0  0xffc02868   /* MXVR Pattern Data Register 0 */
-#define                    MXVR_PAT_EN_0  0xffc0286c   /* MXVR Pattern Enable Register 0 */
-#define                  MXVR_PAT_DATA_1  0xffc02870   /* MXVR Pattern Data Register 1 */
-#define                    MXVR_PAT_EN_1  0xffc02874   /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define                 MXVR_FRAME_CNT_0  0xffc02878   /* MXVR Frame Counter 0 */
-#define                 MXVR_FRAME_CNT_1  0xffc0287c   /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define                   MXVR_ROUTING_0  0xffc02880   /* MXVR Routing Table Register 0 */
-#define                   MXVR_ROUTING_1  0xffc02884   /* MXVR Routing Table Register 1 */
-#define                   MXVR_ROUTING_2  0xffc02888   /* MXVR Routing Table Register 2 */
-#define                   MXVR_ROUTING_3  0xffc0288c   /* MXVR Routing Table Register 3 */
-#define                   MXVR_ROUTING_4  0xffc02890   /* MXVR Routing Table Register 4 */
-#define                   MXVR_ROUTING_5  0xffc02894   /* MXVR Routing Table Register 5 */
-#define                   MXVR_ROUTING_6  0xffc02898   /* MXVR Routing Table Register 6 */
-#define                   MXVR_ROUTING_7  0xffc0289c   /* MXVR Routing Table Register 7 */
-#define                   MXVR_ROUTING_8  0xffc028a0   /* MXVR Routing Table Register 8 */
-#define                   MXVR_ROUTING_9  0xffc028a4   /* MXVR Routing Table Register 9 */
-#define                  MXVR_ROUTING_10  0xffc028a8   /* MXVR Routing Table Register 10 */
-#define                  MXVR_ROUTING_11  0xffc028ac   /* MXVR Routing Table Register 11 */
-#define                  MXVR_ROUTING_12  0xffc028b0   /* MXVR Routing Table Register 12 */
-#define                  MXVR_ROUTING_13  0xffc028b4   /* MXVR Routing Table Register 13 */
-#define                  MXVR_ROUTING_14  0xffc028b8   /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define                   MXVR_BLOCK_CNT  0xffc028c0   /* MXVR Block Counter */
-#define                     MXVR_CLK_CTL  0xffc028d0   /* MXVR Clock Control Register */
-#define                  MXVR_CDRPLL_CTL  0xffc028d4   /* MXVR Clock/Data Recovery PLL Control Register */
-#define                   MXVR_FMPLL_CTL  0xffc028d8   /* MXVR Frequency Multiply PLL Control Register */
-#define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
-#define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                   TIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for MXVR_CONFIG */
-
-#define                    MXVREN  0x1        /* MXVR Enable */
-#define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
-#define                    ACTIVE  0x4        /* Active Mode */
-#define                    SDELAY  0x8        /* Synchronous Data Delay */
-#define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
-#define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
-#define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
-#define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
-#define                   EPARITY  0x100      /* Even Parity Select */
-#define                       MSB  0x1e00     /* Master Synchronous Boundary */
-#define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
-#define                    WAKEUP  0x4000     /* Wake-Up */
-#define                     LMECH  0x8000     /* Lock Mechanism Select */
-
-/* Bit masks for MXVR_STATE_0 */
-
-#define                      NACT  0x1        /* Network Activity */
-#define                    SBLOCK  0x2        /* Super Block Lock */
-#define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
-#define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
-#define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
-#define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
-#define                      APTX  0x400      /* Asynchronous Packet Transmitting */
-#define                      APRX  0x800      /* Receiving Asynchronous Packet */
-#define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
-#define                     CMARB  0x2000     /* Control Message Arbitrating */
-#define                      CMTX  0x4000     /* Control Message Transmitting */
-#define                      CMRX  0x8000     /* Receiving Control Message */
-#define                    MRXONB  0x10000    /* MRXONB Pin State */
-#define                     RGSIP  0x20000    /* Remote Get Source In Progress */
-#define                     DALIP  0x40000    /* Resource Deallocate In Progress */
-#define                      ALIP  0x80000    /* Resource Allocate In Progress */
-#define                     RRDIP  0x100000   /* Remote Read In Progress */
-#define                     RWRIP  0x200000   /* Remote Write In Progress */
-#define                     FLOCK  0x400000   /* Frame Lock */
-#define                     BLOCK  0x800000   /* Block Lock */
-#define                       RSB  0xf000000  /* Received Synchronous Boundary */
-#define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
-
-/* Bit masks for MXVR_STATE_1 */
-
-#define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
-#define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
-#define                    APCONT  0x100      /* Asynchronous Packet Continuation */
-#define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
-#define                DMAACTIVE0  0x10000    /* DMA0 Active */
-#define                DMAACTIVE1  0x20000    /* DMA1 Active */
-#define                DMAACTIVE2  0x40000    /* DMA2 Active */
-#define                DMAACTIVE3  0x80000    /* DMA3 Active */
-#define                DMAACTIVE4  0x100000   /* DMA4 Active */
-#define                DMAACTIVE5  0x200000   /* DMA5 Active */
-#define                DMAACTIVE6  0x400000   /* DMA6 Active */
-#define                DMAACTIVE7  0x800000   /* DMA7 Active */
-#define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
-#define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
-#define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
-#define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
-#define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
-#define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
-#define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
-#define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
-
-/* Bit masks for MXVR_INT_STAT_0 */
-
-#define                      NI2A  0x1        /* Network Inactive to Active */
-#define                      NA2I  0x2        /* Network Active to Inactive */
-#define                     SBU2L  0x4        /* Super Block Unlock to Lock */
-#define                     SBL2U  0x8        /* Super Block Lock to Unlock */
-#define                       PRU  0x10       /* Position Register Updated */
-#define                      MPRU  0x20       /* Maximum Position Register Updated */
-#define                       DRU  0x40       /* Delay Register Updated */
-#define                      MDRU  0x80       /* Maximum Delay Register Updated */
-#define                       SBU  0x100      /* Synchronous Boundary Updated */
-#define                       ATU  0x200      /* Allocation Table Updated */
-#define                      FCZ0  0x400      /* Frame Counter 0 Zero */
-#define                      FCZ1  0x800      /* Frame Counter 1 Zero */
-#define                      PERR  0x1000     /* Parity Error */
-#define                      MH2L  0x2000     /* MRXONB High to Low */
-#define                      ML2H  0x4000     /* MRXONB Low to High */
-#define                       WUP  0x8000     /* Wake-Up Preamble Received */
-#define                      FU2L  0x10000    /* Frame Unlock to Lock */
-#define                      FL2U  0x20000    /* Frame Lock to Unlock */
-#define                      BU2L  0x40000    /* Block Unlock to Lock */
-#define                      BL2U  0x80000    /* Block Lock to Unlock */
-#define                     OBERR  0x100000   /* DMA Out of Bounds Error */
-#define                       PFL  0x200000   /* PLL Frequency Locked */
-#define                       SCZ  0x400000   /* System Clock Counter Zero */
-#define                      FERR  0x800000   /* FIFO Error */
-#define                       CMR  0x1000000  /* Control Message Received */
-#define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
-#define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
-#define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
-#define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
-#define                       BCZ  0x20000000 /* Block Counter Zero */
-#define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
-#define                      DERR  0x80000000 /* DMA Error */
-
-/* Bit masks for MXVR_INT_STAT_1 */
-
-#define                    HDONE0  0x1        /* DMA0 Half Done */
-#define                     DONE0  0x2        /* DMA0 Done */
-#define                       APR  0x4        /* Asynchronous Packet Received */
-#define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
-#define                    HDONE1  0x10       /* DMA1 Half Done */
-#define                     DONE1  0x20       /* DMA1 Done */
-#define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define                    HDONE2  0x100      /* DMA2 Half Done */
-#define                     DONE2  0x200      /* DMA2 Done */
-#define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
-#define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
-#define                    HDONE3  0x1000     /* DMA3 Half Done */
-#define                     DONE3  0x2000     /* DMA3 Done */
-#define                    HDONE4  0x10000    /* DMA4 Half Done */
-#define                     DONE4  0x20000    /* DMA4 Done */
-#define                    HDONE5  0x100000   /* DMA5 Half Done */
-#define                     DONE5  0x200000   /* DMA5 Done */
-#define                    HDONE6  0x1000000  /* DMA6 Half Done */
-#define                     DONE6  0x2000000  /* DMA6 Done */
-#define                    HDONE7  0x10000000 /* DMA7 Half Done */
-#define                     DONE7  0x20000000 /* DMA7 Done */
-
-/* Bit masks for MXVR_INT_EN_0 */
-
-#define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
-#define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
-#define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
-#define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
-#define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
-#define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
-#define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
-#define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
-#define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
-#define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
-#define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
-#define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
-#define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
-#define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
-#define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
-#define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
-#define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
-#define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
-#define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
-#define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
-#define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
-#define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
-#define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
-#define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
-#define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
-#define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
-#define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
-
-/* Bit masks for MXVR_INT_EN_1 */
-
-#define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
-#define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
-#define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
-#define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
-#define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
-#define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
-#define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
-#define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
-#define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
-#define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
-#define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
-#define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
-#define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
-#define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
-#define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
-#define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
-
-/* Bit masks for MXVR_POSITION */
-
-#define                  POSITION  0x3f       /* Node Position */
-#define                    PVALID  0x8000     /* Node Position Valid */
-
-/* Bit masks for MXVR_MAX_POSITION */
-
-#define                 MPOSITION  0x3f       /* Maximum Node Position */
-#define                   MPVALID  0x8000     /* Maximum Node Position Valid */
-
-/* Bit masks for MXVR_DELAY */
-
-#define                     DELAY  0x3f       /* Node Frame Delay */
-#define                    DVALID  0x8000     /* Node Frame Delay Valid */
-
-/* Bit masks for MXVR_MAX_DELAY */
-
-#define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
-#define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
-
-/* Bit masks for MXVR_LADDR */
-
-#define                     LADDR  0xffff     /* Logical Address */
-#define                    LVALID  0x80000000 /* Logical Address Valid */
-
-/* Bit masks for MXVR_GADDR */
-
-#define                    GADDRL  0xff       /* Group Address Lower Byte */
-#define                    GVALID  0x8000     /* Group Address Valid */
-
-/* Bit masks for MXVR_AADDR */
-
-#define                     AADDR  0xffff     /* Alternate Address */
-#define                    AVALID  0x80000000 /* Alternate Address Valid */
-
-/* Bit masks for MXVR_ALLOC_0 */
-
-#define                       CL0  0x7f       /* Channel 0 Connection Label */
-#define                      CIU0  0x80       /* Channel 0 In Use */
-#define                       CL1  0x7f00     /* Channel 0 Connection Label */
-#define                      CIU1  0x8000     /* Channel 0 In Use */
-#define                       CL2  0x7f0000   /* Channel 0 Connection Label */
-#define                      CIU2  0x800000   /* Channel 0 In Use */
-#define                       CL3  0x7f000000 /* Channel 0 Connection Label */
-#define                      CIU3  0x80000000 /* Channel 0 In Use */
-
-/* Bit masks for MXVR_ALLOC_1 */
-
-#define                       CL4  0x7f       /* Channel 4 Connection Label */
-#define                      CIU4  0x80       /* Channel 4 In Use */
-#define                       CL5  0x7f00     /* Channel 5 Connection Label */
-#define                      CIU5  0x8000     /* Channel 5 In Use */
-#define                       CL6  0x7f0000   /* Channel 6 Connection Label */
-#define                      CIU6  0x800000   /* Channel 6 In Use */
-#define                       CL7  0x7f000000 /* Channel 7 Connection Label */
-#define                      CIU7  0x80000000 /* Channel 7 In Use */
-
-/* Bit masks for MXVR_ALLOC_2 */
-
-#define                       CL8  0x7f       /* Channel 8 Connection Label */
-#define                      CIU8  0x80       /* Channel 8 In Use */
-#define                       CL9  0x7f00     /* Channel 9 Connection Label */
-#define                      CIU9  0x8000     /* Channel 9 In Use */
-#define                      CL10  0x7f0000   /* Channel 10 Connection Label */
-#define                     CIU10  0x800000   /* Channel 10 In Use */
-#define                      CL11  0x7f000000 /* Channel 11 Connection Label */
-#define                     CIU11  0x80000000 /* Channel 11 In Use */
-
-/* Bit masks for MXVR_ALLOC_3 */
-
-#define                      CL12  0x7f       /* Channel 12 Connection Label */
-#define                     CIU12  0x80       /* Channel 12 In Use */
-#define                      CL13  0x7f00     /* Channel 13 Connection Label */
-#define                     CIU13  0x8000     /* Channel 13 In Use */
-#define                      CL14  0x7f0000   /* Channel 14 Connection Label */
-#define                     CIU14  0x800000   /* Channel 14 In Use */
-#define                      CL15  0x7f000000 /* Channel 15 Connection Label */
-#define                     CIU15  0x80000000 /* Channel 15 In Use */
-
-/* Bit masks for MXVR_ALLOC_4 */
-
-#define                      CL16  0x7f       /* Channel 16 Connection Label */
-#define                     CIU16  0x80       /* Channel 16 In Use */
-#define                      CL17  0x7f00     /* Channel 17 Connection Label */
-#define                     CIU17  0x8000     /* Channel 17 In Use */
-#define                      CL18  0x7f0000   /* Channel 18 Connection Label */
-#define                     CIU18  0x800000   /* Channel 18 In Use */
-#define                      CL19  0x7f000000 /* Channel 19 Connection Label */
-#define                     CIU19  0x80000000 /* Channel 19 In Use */
-
-/* Bit masks for MXVR_ALLOC_5 */
-
-#define                      CL20  0x7f       /* Channel 20 Connection Label */
-#define                     CIU20  0x80       /* Channel 20 In Use */
-#define                      CL21  0x7f00     /* Channel 21 Connection Label */
-#define                     CIU21  0x8000     /* Channel 21 In Use */
-#define                      CL22  0x7f0000   /* Channel 22 Connection Label */
-#define                     CIU22  0x800000   /* Channel 22 In Use */
-#define                      CL23  0x7f000000 /* Channel 23 Connection Label */
-#define                     CIU23  0x80000000 /* Channel 23 In Use */
-
-/* Bit masks for MXVR_ALLOC_6 */
-
-#define                      CL24  0x7f       /* Channel 24 Connection Label */
-#define                     CIU24  0x80       /* Channel 24 In Use */
-#define                      CL25  0x7f00     /* Channel 25 Connection Label */
-#define                     CIU25  0x8000     /* Channel 25 In Use */
-#define                      CL26  0x7f0000   /* Channel 26 Connection Label */
-#define                     CIU26  0x800000   /* Channel 26 In Use */
-#define                      CL27  0x7f000000 /* Channel 27 Connection Label */
-#define                     CIU27  0x80000000 /* Channel 27 In Use */
-
-/* Bit masks for MXVR_ALLOC_7 */
-
-#define                      CL28  0x7f       /* Channel 28 Connection Label */
-#define                     CIU28  0x80       /* Channel 28 In Use */
-#define                      CL29  0x7f00     /* Channel 29 Connection Label */
-#define                     CIU29  0x8000     /* Channel 29 In Use */
-#define                      CL30  0x7f0000   /* Channel 30 Connection Label */
-#define                     CIU30  0x800000   /* Channel 30 In Use */
-#define                      CL31  0x7f000000 /* Channel 31 Connection Label */
-#define                     CIU31  0x80000000 /* Channel 31 In Use */
-
-/* Bit masks for MXVR_ALLOC_8 */
-
-#define                      CL32  0x7f       /* Channel 32 Connection Label */
-#define                     CIU32  0x80       /* Channel 32 In Use */
-#define                      CL33  0x7f00     /* Channel 33 Connection Label */
-#define                     CIU33  0x8000     /* Channel 33 In Use */
-#define                      CL34  0x7f0000   /* Channel 34 Connection Label */
-#define                     CIU34  0x800000   /* Channel 34 In Use */
-#define                      CL35  0x7f000000 /* Channel 35 Connection Label */
-#define                     CIU35  0x80000000 /* Channel 35 In Use */
-
-/* Bit masks for MXVR_ALLOC_9 */
-
-#define                      CL36  0x7f       /* Channel 36 Connection Label */
-#define                     CIU36  0x80       /* Channel 36 In Use */
-#define                      CL37  0x7f00     /* Channel 37 Connection Label */
-#define                     CIU37  0x8000     /* Channel 37 In Use */
-#define                      CL38  0x7f0000   /* Channel 38 Connection Label */
-#define                     CIU38  0x800000   /* Channel 38 In Use */
-#define                      CL39  0x7f000000 /* Channel 39 Connection Label */
-#define                     CIU39  0x80000000 /* Channel 39 In Use */
-
-/* Bit masks for MXVR_ALLOC_10 */
-
-#define                      CL40  0x7f       /* Channel 40 Connection Label */
-#define                     CIU40  0x80       /* Channel 40 In Use */
-#define                      CL41  0x7f00     /* Channel 41 Connection Label */
-#define                     CIU41  0x8000     /* Channel 41 In Use */
-#define                      CL42  0x7f0000   /* Channel 42 Connection Label */
-#define                     CIU42  0x800000   /* Channel 42 In Use */
-#define                      CL43  0x7f000000 /* Channel 43 Connection Label */
-#define                     CIU43  0x80000000 /* Channel 43 In Use */
-
-/* Bit masks for MXVR_ALLOC_11 */
-
-#define                      CL44  0x7f       /* Channel 44 Connection Label */
-#define                     CIU44  0x80       /* Channel 44 In Use */
-#define                      CL45  0x7f00     /* Channel 45 Connection Label */
-#define                     CIU45  0x8000     /* Channel 45 In Use */
-#define                      CL46  0x7f0000   /* Channel 46 Connection Label */
-#define                     CIU46  0x800000   /* Channel 46 In Use */
-#define                      CL47  0x7f000000 /* Channel 47 Connection Label */
-#define                     CIU47  0x80000000 /* Channel 47 In Use */
-
-/* Bit masks for MXVR_ALLOC_12 */
-
-#define                      CL48  0x7f       /* Channel 48 Connection Label */
-#define                     CIU48  0x80       /* Channel 48 In Use */
-#define                      CL49  0x7f00     /* Channel 49 Connection Label */
-#define                     CIU49  0x8000     /* Channel 49 In Use */
-#define                      CL50  0x7f0000   /* Channel 50 Connection Label */
-#define                     CIU50  0x800000   /* Channel 50 In Use */
-#define                      CL51  0x7f000000 /* Channel 51 Connection Label */
-#define                     CIU51  0x80000000 /* Channel 51 In Use */
-
-/* Bit masks for MXVR_ALLOC_13 */
-
-#define                      CL52  0x7f       /* Channel 52 Connection Label */
-#define                     CIU52  0x80       /* Channel 52 In Use */
-#define                      CL53  0x7f00     /* Channel 53 Connection Label */
-#define                     CIU53  0x8000     /* Channel 53 In Use */
-#define                      CL54  0x7f0000   /* Channel 54 Connection Label */
-#define                     CIU54  0x800000   /* Channel 54 In Use */
-#define                      CL55  0x7f000000 /* Channel 55 Connection Label */
-#define                     CIU55  0x80000000 /* Channel 55 In Use */
-
-/* Bit masks for MXVR_ALLOC_14 */
-
-#define                      CL56  0x7f       /* Channel 56 Connection Label */
-#define                     CIU56  0x80       /* Channel 56 In Use */
-#define                      CL57  0x7f00     /* Channel 57 Connection Label */
-#define                     CIU57  0x8000     /* Channel 57 In Use */
-#define                      CL58  0x7f0000   /* Channel 58 Connection Label */
-#define                     CIU58  0x800000   /* Channel 58 In Use */
-#define                      CL59  0x7f000000 /* Channel 59 Connection Label */
-#define                     CIU59  0x80000000 /* Channel 59 In Use */
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-/* Bit masks for MXVR_DMAx_CONFIG */
-
-#define                    MDMAEN  0x1        /* DMA Channel Enable */
-#define                     DMADD  0x2        /* DMA Channel Direction */
-#define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
-#define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
-#define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
-#define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
-#define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
-#define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
-#define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
-#define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
-#define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
-
-/* Bit masks for MXVR_AP_CTL */
-
-#define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
-#define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
-#define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
-#define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
-#define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
-
-/* Bit masks for MXVR_APRB_START_ADDR */
-
-#define      MXVR_APRB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
-
-/* Bit masks for MXVR_APRB_CURR_ADDR */
-
-#define       MXVR_APRB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
-
-/* Bit masks for MXVR_APTB_START_ADDR */
-
-#define       MXVR_APTB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_APTB_CURR_ADDR */
-
-#define        MXVR_APTB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_CM_CTL */
-
-#define                   STARTCM  0x1        /* Start Control Message Transmission */
-#define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
-#define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
-#define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
-#define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
-#define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
-#define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
-#define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
-#define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
-#define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
-#define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
-#define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
-#define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
-#define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
-#define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
-
-/* Bit masks for MXVR_CMRB_START_ADDR */
-
-#define      MXVR_CMRB_START_ADDR_MASK  0x1fffffe  /* Control Message Receive Buffer Start Address */
-
-/* Bit masks for MXVR_CMRB_CURR_ADDR */
-
-#define       MXVR_CMRB_CURR_ADDR_MASK  0xffffffff /* Control Message Receive Buffer Current Address */
-
-/* Bit masks for MXVR_CMTB_START_ADDR */
-
-#define      MXVR_CMTB_START_ADDR_MASK  0x1fffffe  /* Control Message Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_CMTB_CURR_ADDR */
-
-#define       MXVR_CMTB_CURR_ADDR_MASK  0xffffffff /* Control Message Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_RRDB_START_ADDR */
-
-#define      MXVR_RRDB_START_ADDR_MASK  0x1fffffe  /* Remote Read Buffer Start Address */
-
-/* Bit masks for MXVR_RRDB_CURR_ADDR */
-
-#define       MXVR_RRDB_CURR_ADDR_MASK  0xffffffff /* Remote Read Buffer Current Address */
-
-/* Bit masks for MXVR_PAT_DATAx */
-
-#define              MATCH_DATA_0  0xff       /* Pattern Match Data Byte 0 */
-#define              MATCH_DATA_1  0xff00     /* Pattern Match Data Byte 1 */
-#define              MATCH_DATA_2  0xff0000   /* Pattern Match Data Byte 2 */
-#define              MATCH_DATA_3  0xff000000 /* Pattern Match Data Byte 3 */
-
-/* Bit masks for MXVR_PAT_EN_0 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-
-/* Bit masks for MXVR_PAT_EN_1 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-
-/* Bit masks for MXVR_FRAME_CNT_0 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_FRAME_CNT_1 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_ROUTING_0 */
-
-#define                    TX_CH0  0x3f       /* Transmit Channel 0 */
-#define                  MUTE_CH0  0x80       /* Mute Channel 0 */
-#define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
-#define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
-#define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
-#define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
-#define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
-#define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
-
-/* Bit masks for MXVR_ROUTING_1 */
-
-#define                    TX_CH4  0x3f       /* Transmit Channel 4 */
-#define                  MUTE_CH4  0x80       /* Mute Channel 4 */
-#define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
-#define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
-#define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
-#define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
-#define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
-#define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
-
-/* Bit masks for MXVR_ROUTING_2 */
-
-#define                    TX_CH8  0x3f       /* Transmit Channel 8 */
-#define                  MUTE_CH8  0x80       /* Mute Channel 8 */
-#define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
-#define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
-#define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
-#define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
-#define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
-#define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
-
-/* Bit masks for MXVR_ROUTING_3 */
-
-#define                   TX_CH12  0x3f       /* Transmit Channel 12 */
-#define                 MUTE_CH12  0x80       /* Mute Channel 12 */
-#define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
-#define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
-#define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
-#define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
-#define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
-#define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
-
-/* Bit masks for MXVR_ROUTING_4 */
-
-#define                   TX_CH16  0x3f       /* Transmit Channel 16 */
-#define                 MUTE_CH16  0x80       /* Mute Channel 16 */
-#define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
-#define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
-#define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
-#define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
-#define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
-#define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
-
-/* Bit masks for MXVR_ROUTING_5 */
-
-#define                   TX_CH20  0x3f       /* Transmit Channel 20 */
-#define                 MUTE_CH20  0x80       /* Mute Channel 20 */
-#define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
-#define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
-#define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
-#define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
-#define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
-#define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
-
-/* Bit masks for MXVR_ROUTING_6 */
-
-#define                   TX_CH24  0x3f       /* Transmit Channel 24 */
-#define                 MUTE_CH24  0x80       /* Mute Channel 24 */
-#define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
-#define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
-#define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
-#define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
-#define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
-#define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
-
-/* Bit masks for MXVR_ROUTING_7 */
-
-#define                   TX_CH28  0x3f       /* Transmit Channel 28 */
-#define                 MUTE_CH28  0x80       /* Mute Channel 28 */
-#define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
-#define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
-#define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
-#define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
-#define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
-#define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
-
-/* Bit masks for MXVR_ROUTING_8 */
-
-#define                   TX_CH32  0x3f       /* Transmit Channel 32 */
-#define                 MUTE_CH32  0x80       /* Mute Channel 32 */
-#define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
-#define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
-#define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
-#define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
-#define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
-#define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
-
-/* Bit masks for MXVR_ROUTING_9 */
-
-#define                   TX_CH36  0x3f       /* Transmit Channel 36 */
-#define                 MUTE_CH36  0x80       /* Mute Channel 36 */
-#define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
-#define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
-#define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
-#define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
-#define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
-#define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
-
-/* Bit masks for MXVR_ROUTING_10 */
-
-#define                   TX_CH40  0x3f       /* Transmit Channel 40 */
-#define                 MUTE_CH40  0x80       /* Mute Channel 40 */
-#define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
-#define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
-#define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
-#define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
-#define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
-#define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
-
-/* Bit masks for MXVR_ROUTING_11 */
-
-#define                   TX_CH44  0x3f       /* Transmit Channel 44 */
-#define                 MUTE_CH44  0x80       /* Mute Channel 44 */
-#define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
-#define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
-#define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
-#define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
-#define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
-#define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
-
-/* Bit masks for MXVR_ROUTING_12 */
-
-#define                   TX_CH48  0x3f       /* Transmit Channel 48 */
-#define                 MUTE_CH48  0x80       /* Mute Channel 48 */
-#define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
-#define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
-#define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
-#define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
-#define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
-#define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
-
-/* Bit masks for MXVR_ROUTING_13 */
-
-#define                   TX_CH52  0x3f       /* Transmit Channel 52 */
-#define                 MUTE_CH52  0x80       /* Mute Channel 52 */
-#define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
-#define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
-#define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
-#define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
-#define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
-#define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
-
-/* Bit masks for MXVR_ROUTING_14 */
-
-#define                   TX_CH56  0x3f       /* Transmit Channel 56 */
-#define                 MUTE_CH56  0x80       /* Mute Channel 56 */
-#define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
-#define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
-#define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
-#define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
-#define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
-#define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
-
-/* Bit masks for MXVR_BLOCK_CNT */
-
-#define                      BCNT  0xffff     /* Block Count */
-
-/* Bit masks for MXVR_CLK_CTL */
-
-#define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
-#define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
-#define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
-#define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
-#define                   MMCLKEN  0x100      /* Master Clock Enable */
-#define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
-#define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
-#define                   MBCLKEN  0x10000    /* Bit Clock Enable */
-#define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
-#define                     INVRX  0x800000   /* Invert Receive Data */
-#define                     MFSEN  0x1000000  /* Frame Sync Enable */
-#define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
-#define                    MFSSEL  0x60000000 /* Frame Sync Select */
-#define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
-
-/* Bit masks for MXVR_CDRPLL_CTL */
-
-#define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
-#define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
-#define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
-#define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
-#define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
-#define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
-#define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
-#define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
-#define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_FMPLL_CTL */
-
-#define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
-#define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
-#define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
-#define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
-#define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
-#define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_PIN_CTL */
-
-#define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
-#define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
-#define                     MFSOE  0x10       /* MFS Output Enable */
-#define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
-#define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
-
-/* Bit masks for MXVR_SCLK_CNT */
-
-#define                      SCNT  0xffff     /* System Clock Count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* ************************ */
-/*   MXVR Address Offsets   */
-/* ************************ */
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-/* **************** */
-/*   MXVR Macros    */
-/* **************** */
-
-/* MXVR_CONFIG Macros */
-
-#define SET_MSB(x)       ( ( (x) & 0xF  ) << 9)
-
-/* MXVR_INT_STAT_1 Macros */
-
-#define DONEX(x)         (0x00000002 << (4 * (x)))
-#define HDONEX(x)        (0x00000001 << (4 * (x)))
-
-/* MXVR_INT_EN_1 Macros */
-
-#define DONEENX(x)       (0x00000002 << (4 * (x)))
-#define HDONEENX(x)      (0x00000001 << (4 * (x)))
-
-/* MXVR_CDRPLL_CTL Macros */
-
-#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
-
-/* MXVR_FMPLL_CTL Macros */
-
-#define SET_CDRCPSEL(x)  ( ( (x) & 0xFF ) << 24)
-#define SET_FMCPSEL(x)   ( ( (x) & 0xFF ) << 24)
-
-#endif /* _DEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
deleted file mode 100644
index e022e896cb18..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ /dev/null
@@ -1,3956 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF54x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define                          PLL_CTL  0xffc00000   /* PLL Control Register */
-#define                          PLL_DIV  0xffc00004   /* PLL Divisor Register */
-#define                           VR_CTL  0xffc00008   /* Voltage Regulator Control Register */
-#define                         PLL_STAT  0xffc0000c   /* PLL Status Register */
-#define                      PLL_LOCKCNT  0xffc00010   /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define                           CHIPID  0xffc00014
-/* CHIPID Masks */
-#define                   CHIPID_VERSION  0xF0000000
-#define                    CHIPID_FAMILY  0x0FFFF000
-#define               CHIPID_MANUFACTURE  0x00000FFE
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define                            SWRST  0xffc00100   /* Software Reset Register */
-#define                            SYSCR  0xffc00104   /* System Configuration register */
-
-/* SIC Registers */
-
-#define                       SIC_IMASK0  0xffc0010c   /* System Interrupt Mask Register 0 */
-#define                       SIC_IMASK1  0xffc00110   /* System Interrupt Mask Register 1 */
-#define                       SIC_IMASK2  0xffc00114   /* System Interrupt Mask Register 2 */
-#define                         SIC_ISR0  0xffc00118   /* System Interrupt Status Register 0 */
-#define                         SIC_ISR1  0xffc0011c   /* System Interrupt Status Register 1 */
-#define                         SIC_ISR2  0xffc00120   /* System Interrupt Status Register 2 */
-#define                         SIC_IWR0  0xffc00124   /* System Interrupt Wakeup Register 0 */
-#define                         SIC_IWR1  0xffc00128   /* System Interrupt Wakeup Register 1 */
-#define                         SIC_IWR2  0xffc0012c   /* System Interrupt Wakeup Register 2 */
-#define                         SIC_IAR0  0xffc00130   /* System Interrupt Assignment Register 0 */
-#define                         SIC_IAR1  0xffc00134   /* System Interrupt Assignment Register 1 */
-#define                         SIC_IAR2  0xffc00138   /* System Interrupt Assignment Register 2 */
-#define                         SIC_IAR3  0xffc0013c   /* System Interrupt Assignment Register 3 */
-#define                         SIC_IAR4  0xffc00140   /* System Interrupt Assignment Register 4 */
-#define                         SIC_IAR5  0xffc00144   /* System Interrupt Assignment Register 5 */
-#define                         SIC_IAR6  0xffc00148   /* System Interrupt Assignment Register 6 */
-#define                         SIC_IAR7  0xffc0014c   /* System Interrupt Assignment Register 7 */
-#define                         SIC_IAR8  0xffc00150   /* System Interrupt Assignment Register 8 */
-#define                         SIC_IAR9  0xffc00154   /* System Interrupt Assignment Register 9 */
-#define                        SIC_IAR10  0xffc00158   /* System Interrupt Assignment Register 10 */
-#define                        SIC_IAR11  0xffc0015c   /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define                         WDOG_CTL  0xffc00200   /* Watchdog Control Register */
-#define                         WDOG_CNT  0xffc00204   /* Watchdog Count Register */
-#define                        WDOG_STAT  0xffc00208   /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define                         RTC_STAT  0xffc00300   /* RTC Status Register */
-#define                         RTC_ICTL  0xffc00304   /* RTC Interrupt Control Register */
-#define                        RTC_ISTAT  0xffc00308   /* RTC Interrupt Status Register */
-#define                        RTC_SWCNT  0xffc0030c   /* RTC Stopwatch Count Register */
-#define                        RTC_ALARM  0xffc00310   /* RTC Alarm Register */
-#define                         RTC_PREN  0xffc00314   /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define                        UART0_DLL  0xffc00400   /* Divisor Latch Low Byte */
-#define                        UART0_DLH  0xffc00404   /* Divisor Latch High Byte */
-#define                       UART0_GCTL  0xffc00408   /* Global Control Register */
-#define                        UART0_LCR  0xffc0040c   /* Line Control Register */
-#define                        UART0_MCR  0xffc00410   /* Modem Control Register */
-#define                        UART0_LSR  0xffc00414   /* Line Status Register */
-#define                        UART0_MSR  0xffc00418   /* Modem Status Register */
-#define                        UART0_SCR  0xffc0041c   /* Scratch Register */
-#define                    UART0_IER_SET  0xffc00420   /* Interrupt Enable Register Set */
-#define                  UART0_IER_CLEAR  0xffc00424   /* Interrupt Enable Register Clear */
-#define                        UART0_THR  0xffc00428   /* Transmit Hold Register */
-#define                        UART0_RBR  0xffc0042c   /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define                     SPI0_REGBASE  0xffc00500
-#define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
-#define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
-#define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
-#define                        SPI0_TDBR  0xffc0050c   /* SPI0 Transmit Data Buffer Register */
-#define                        SPI0_RDBR  0xffc00510   /* SPI0 Receive Data Buffer Register */
-#define                        SPI0_BAUD  0xffc00514   /* SPI0 Baud Rate Register */
-#define                      SPI0_SHADOW  0xffc00518   /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define                     TWI0_REGBASE  0xffc00700
-#define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
-#define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
-#define                  TWI0_SLAVE_CTRL  0xffc00708   /* TWI Slave Mode Control Register */
-#define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
-#define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
-#define                 TWI0_MASTER_CTRL  0xffc00714   /* TWI Master Mode Control Register */
-#define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
-#define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
-#define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
-#define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
-#define                   TWI0_FIFO_CTRL  0xffc00728   /* TWI FIFO Control Register */
-#define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
-#define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI0_RCV_DATA8  0xffc00788   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI0_RCV_DATA16  0xffc0078c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define                      SPORT1_TCR1  0xffc00900   /* SPORT1 Transmit Configuration 1 Register */
-#define                      SPORT1_TCR2  0xffc00904   /* SPORT1 Transmit Configuration 2 Register */
-#define                   SPORT1_TCLKDIV  0xffc00908   /* SPORT1 Transmit Serial Clock Divider Register */
-#define                    SPORT1_TFSDIV  0xffc0090c   /* SPORT1 Transmit Frame Sync Divider Register */
-#define                        SPORT1_TX  0xffc00910   /* SPORT1 Transmit Data Register */
-#define                        SPORT1_RX  0xffc00918   /* SPORT1 Receive Data Register */
-#define                      SPORT1_RCR1  0xffc00920   /* SPORT1 Receive Configuration 1 Register */
-#define                      SPORT1_RCR2  0xffc00924   /* SPORT1 Receive Configuration 2 Register */
-#define                   SPORT1_RCLKDIV  0xffc00928   /* SPORT1 Receive Serial Clock Divider Register */
-#define                    SPORT1_RFSDIV  0xffc0092c   /* SPORT1 Receive Frame Sync Divider Register */
-#define                      SPORT1_STAT  0xffc00930   /* SPORT1 Status Register */
-#define                      SPORT1_CHNL  0xffc00934   /* SPORT1 Current Channel Register */
-#define                     SPORT1_MCMC1  0xffc00938   /* SPORT1 Multi channel Configuration Register 1 */
-#define                     SPORT1_MCMC2  0xffc0093c   /* SPORT1 Multi channel Configuration Register 2 */
-#define                     SPORT1_MTCS0  0xffc00940   /* SPORT1 Multi channel Transmit Select Register 0 */
-#define                     SPORT1_MTCS1  0xffc00944   /* SPORT1 Multi channel Transmit Select Register 1 */
-#define                     SPORT1_MTCS2  0xffc00948   /* SPORT1 Multi channel Transmit Select Register 2 */
-#define                     SPORT1_MTCS3  0xffc0094c   /* SPORT1 Multi channel Transmit Select Register 3 */
-#define                     SPORT1_MRCS0  0xffc00950   /* SPORT1 Multi channel Receive Select Register 0 */
-#define                     SPORT1_MRCS1  0xffc00954   /* SPORT1 Multi channel Receive Select Register 1 */
-#define                     SPORT1_MRCS2  0xffc00958   /* SPORT1 Multi channel Receive Select Register 2 */
-#define                     SPORT1_MRCS3  0xffc0095c   /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define                      EBIU_AMGCTL  0xffc00a00   /* Asynchronous Memory Global Control Register */
-#define                    EBIU_AMBCTL0   0xffc00a04   /* Asynchronous Memory Bank Control Register */
-#define                    EBIU_AMBCTL1   0xffc00a08   /* Asynchronous Memory Bank Control Register */
-#define                      EBIU_MBSCTL  0xffc00a0c   /* Asynchronous Memory Bank Select Control Register */
-#define                     EBIU_ARBSTAT  0xffc00a10   /* Asynchronous Memory Arbiter Status Register */
-#define                        EBIU_MODE  0xffc00a14   /* Asynchronous Mode Control Register */
-#define                        EBIU_FCTL  0xffc00a18   /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define                     EBIU_DDRCTL0  0xffc00a20   /* DDR Memory Control 0 Register */
-#define                     EBIU_DDRCTL1  0xffc00a24   /* DDR Memory Control 1 Register */
-#define                     EBIU_DDRCTL2  0xffc00a28   /* DDR Memory Control 2 Register */
-#define                     EBIU_DDRCTL3  0xffc00a2c   /* DDR Memory Control 3 Register */
-#define                      EBIU_DDRQUE  0xffc00a30   /* DDR Queue Configuration Register */
-#define                      EBIU_ERRADD  0xffc00a34   /* DDR Error Address Register */
-#define                      EBIU_ERRMST  0xffc00a38   /* DDR Error Master Register */
-#define                      EBIU_RSTCTL  0xffc00a3c   /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define                     EBIU_DDRBRC0  0xffc00a60   /* DDR Bank0 Read Count Register */
-#define                     EBIU_DDRBRC1  0xffc00a64   /* DDR Bank1 Read Count Register */
-#define                     EBIU_DDRBRC2  0xffc00a68   /* DDR Bank2 Read Count Register */
-#define                     EBIU_DDRBRC3  0xffc00a6c   /* DDR Bank3 Read Count Register */
-#define                     EBIU_DDRBRC4  0xffc00a70   /* DDR Bank4 Read Count Register */
-#define                     EBIU_DDRBRC5  0xffc00a74   /* DDR Bank5 Read Count Register */
-#define                     EBIU_DDRBRC6  0xffc00a78   /* DDR Bank6 Read Count Register */
-#define                     EBIU_DDRBRC7  0xffc00a7c   /* DDR Bank7 Read Count Register */
-#define                     EBIU_DDRBWC0  0xffc00a80   /* DDR Bank0 Write Count Register */
-#define                     EBIU_DDRBWC1  0xffc00a84   /* DDR Bank1 Write Count Register */
-#define                     EBIU_DDRBWC2  0xffc00a88   /* DDR Bank2 Write Count Register */
-#define                     EBIU_DDRBWC3  0xffc00a8c   /* DDR Bank3 Write Count Register */
-#define                     EBIU_DDRBWC4  0xffc00a90   /* DDR Bank4 Write Count Register */
-#define                     EBIU_DDRBWC5  0xffc00a94   /* DDR Bank5 Write Count Register */
-#define                     EBIU_DDRBWC6  0xffc00a98   /* DDR Bank6 Write Count Register */
-#define                     EBIU_DDRBWC7  0xffc00a9c   /* DDR Bank7 Write Count Register */
-#define                     EBIU_DDRACCT  0xffc00aa0   /* DDR Activation Count Register */
-#define                     EBIU_DDRTACT  0xffc00aa8   /* DDR Turn Around Count Register */
-#define                     EBIU_DDRARCT  0xffc00aac   /* DDR Auto-refresh Count Register */
-#define                      EBIU_DDRGC0  0xffc00ab0   /* DDR Grant Count 0 Register */
-#define                      EBIU_DDRGC1  0xffc00ab4   /* DDR Grant Count 1 Register */
-#define                      EBIU_DDRGC2  0xffc00ab8   /* DDR Grant Count 2 Register */
-#define                      EBIU_DDRGC3  0xffc00abc   /* DDR Grant Count 3 Register */
-#define                     EBIU_DDRMCEN  0xffc00ac0   /* DDR Metrics Counter Enable Register */
-#define                     EBIU_DDRMCCL  0xffc00ac4   /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define                      DMAC0_TCPER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
-#define                      DMAC0_TCCNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define               DMA0_NEXT_DESC_PTR  0xffc00c00   /* DMA Channel 0 Next Descriptor Pointer Register */
-#define                  DMA0_START_ADDR  0xffc00c04   /* DMA Channel 0 Start Address Register */
-#define                      DMA0_CONFIG  0xffc00c08   /* DMA Channel 0 Configuration Register */
-#define                     DMA0_X_COUNT  0xffc00c10   /* DMA Channel 0 X Count Register */
-#define                    DMA0_X_MODIFY  0xffc00c14   /* DMA Channel 0 X Modify Register */
-#define                     DMA0_Y_COUNT  0xffc00c18   /* DMA Channel 0 Y Count Register */
-#define                    DMA0_Y_MODIFY  0xffc00c1c   /* DMA Channel 0 Y Modify Register */
-#define               DMA0_CURR_DESC_PTR  0xffc00c20   /* DMA Channel 0 Current Descriptor Pointer Register */
-#define                   DMA0_CURR_ADDR  0xffc00c24   /* DMA Channel 0 Current Address Register */
-#define                  DMA0_IRQ_STATUS  0xffc00c28   /* DMA Channel 0 Interrupt/Status Register */
-#define              DMA0_PERIPHERAL_MAP  0xffc00c2c   /* DMA Channel 0 Peripheral Map Register */
-#define                DMA0_CURR_X_COUNT  0xffc00c30   /* DMA Channel 0 Current X Count Register */
-#define                DMA0_CURR_Y_COUNT  0xffc00c38   /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define               DMA1_NEXT_DESC_PTR  0xffc00c40   /* DMA Channel 1 Next Descriptor Pointer Register */
-#define                  DMA1_START_ADDR  0xffc00c44   /* DMA Channel 1 Start Address Register */
-#define                      DMA1_CONFIG  0xffc00c48   /* DMA Channel 1 Configuration Register */
-#define                     DMA1_X_COUNT  0xffc00c50   /* DMA Channel 1 X Count Register */
-#define                    DMA1_X_MODIFY  0xffc00c54   /* DMA Channel 1 X Modify Register */
-#define                     DMA1_Y_COUNT  0xffc00c58   /* DMA Channel 1 Y Count Register */
-#define                    DMA1_Y_MODIFY  0xffc00c5c   /* DMA Channel 1 Y Modify Register */
-#define               DMA1_CURR_DESC_PTR  0xffc00c60   /* DMA Channel 1 Current Descriptor Pointer Register */
-#define                   DMA1_CURR_ADDR  0xffc00c64   /* DMA Channel 1 Current Address Register */
-#define                  DMA1_IRQ_STATUS  0xffc00c68   /* DMA Channel 1 Interrupt/Status Register */
-#define              DMA1_PERIPHERAL_MAP  0xffc00c6c   /* DMA Channel 1 Peripheral Map Register */
-#define                DMA1_CURR_X_COUNT  0xffc00c70   /* DMA Channel 1 Current X Count Register */
-#define                DMA1_CURR_Y_COUNT  0xffc00c78   /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define               DMA2_NEXT_DESC_PTR  0xffc00c80   /* DMA Channel 2 Next Descriptor Pointer Register */
-#define                  DMA2_START_ADDR  0xffc00c84   /* DMA Channel 2 Start Address Register */
-#define                      DMA2_CONFIG  0xffc00c88   /* DMA Channel 2 Configuration Register */
-#define                     DMA2_X_COUNT  0xffc00c90   /* DMA Channel 2 X Count Register */
-#define                    DMA2_X_MODIFY  0xffc00c94   /* DMA Channel 2 X Modify Register */
-#define                     DMA2_Y_COUNT  0xffc00c98   /* DMA Channel 2 Y Count Register */
-#define                    DMA2_Y_MODIFY  0xffc00c9c   /* DMA Channel 2 Y Modify Register */
-#define               DMA2_CURR_DESC_PTR  0xffc00ca0   /* DMA Channel 2 Current Descriptor Pointer Register */
-#define                   DMA2_CURR_ADDR  0xffc00ca4   /* DMA Channel 2 Current Address Register */
-#define                  DMA2_IRQ_STATUS  0xffc00ca8   /* DMA Channel 2 Interrupt/Status Register */
-#define              DMA2_PERIPHERAL_MAP  0xffc00cac   /* DMA Channel 2 Peripheral Map Register */
-#define                DMA2_CURR_X_COUNT  0xffc00cb0   /* DMA Channel 2 Current X Count Register */
-#define                DMA2_CURR_Y_COUNT  0xffc00cb8   /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define               DMA3_NEXT_DESC_PTR  0xffc00cc0   /* DMA Channel 3 Next Descriptor Pointer Register */
-#define                  DMA3_START_ADDR  0xffc00cc4   /* DMA Channel 3 Start Address Register */
-#define                      DMA3_CONFIG  0xffc00cc8   /* DMA Channel 3 Configuration Register */
-#define                     DMA3_X_COUNT  0xffc00cd0   /* DMA Channel 3 X Count Register */
-#define                    DMA3_X_MODIFY  0xffc00cd4   /* DMA Channel 3 X Modify Register */
-#define                     DMA3_Y_COUNT  0xffc00cd8   /* DMA Channel 3 Y Count Register */
-#define                    DMA3_Y_MODIFY  0xffc00cdc   /* DMA Channel 3 Y Modify Register */
-#define               DMA3_CURR_DESC_PTR  0xffc00ce0   /* DMA Channel 3 Current Descriptor Pointer Register */
-#define                   DMA3_CURR_ADDR  0xffc00ce4   /* DMA Channel 3 Current Address Register */
-#define                  DMA3_IRQ_STATUS  0xffc00ce8   /* DMA Channel 3 Interrupt/Status Register */
-#define              DMA3_PERIPHERAL_MAP  0xffc00cec   /* DMA Channel 3 Peripheral Map Register */
-#define                DMA3_CURR_X_COUNT  0xffc00cf0   /* DMA Channel 3 Current X Count Register */
-#define                DMA3_CURR_Y_COUNT  0xffc00cf8   /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define               DMA4_NEXT_DESC_PTR  0xffc00d00   /* DMA Channel 4 Next Descriptor Pointer Register */
-#define                  DMA4_START_ADDR  0xffc00d04   /* DMA Channel 4 Start Address Register */
-#define                      DMA4_CONFIG  0xffc00d08   /* DMA Channel 4 Configuration Register */
-#define                     DMA4_X_COUNT  0xffc00d10   /* DMA Channel 4 X Count Register */
-#define                    DMA4_X_MODIFY  0xffc00d14   /* DMA Channel 4 X Modify Register */
-#define                     DMA4_Y_COUNT  0xffc00d18   /* DMA Channel 4 Y Count Register */
-#define                    DMA4_Y_MODIFY  0xffc00d1c   /* DMA Channel 4 Y Modify Register */
-#define               DMA4_CURR_DESC_PTR  0xffc00d20   /* DMA Channel 4 Current Descriptor Pointer Register */
-#define                   DMA4_CURR_ADDR  0xffc00d24   /* DMA Channel 4 Current Address Register */
-#define                  DMA4_IRQ_STATUS  0xffc00d28   /* DMA Channel 4 Interrupt/Status Register */
-#define              DMA4_PERIPHERAL_MAP  0xffc00d2c   /* DMA Channel 4 Peripheral Map Register */
-#define                DMA4_CURR_X_COUNT  0xffc00d30   /* DMA Channel 4 Current X Count Register */
-#define                DMA4_CURR_Y_COUNT  0xffc00d38   /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define               DMA5_NEXT_DESC_PTR  0xffc00d40   /* DMA Channel 5 Next Descriptor Pointer Register */
-#define                  DMA5_START_ADDR  0xffc00d44   /* DMA Channel 5 Start Address Register */
-#define                      DMA5_CONFIG  0xffc00d48   /* DMA Channel 5 Configuration Register */
-#define                     DMA5_X_COUNT  0xffc00d50   /* DMA Channel 5 X Count Register */
-#define                    DMA5_X_MODIFY  0xffc00d54   /* DMA Channel 5 X Modify Register */
-#define                     DMA5_Y_COUNT  0xffc00d58   /* DMA Channel 5 Y Count Register */
-#define                    DMA5_Y_MODIFY  0xffc00d5c   /* DMA Channel 5 Y Modify Register */
-#define               DMA5_CURR_DESC_PTR  0xffc00d60   /* DMA Channel 5 Current Descriptor Pointer Register */
-#define                   DMA5_CURR_ADDR  0xffc00d64   /* DMA Channel 5 Current Address Register */
-#define                  DMA5_IRQ_STATUS  0xffc00d68   /* DMA Channel 5 Interrupt/Status Register */
-#define              DMA5_PERIPHERAL_MAP  0xffc00d6c   /* DMA Channel 5 Peripheral Map Register */
-#define                DMA5_CURR_X_COUNT  0xffc00d70   /* DMA Channel 5 Current X Count Register */
-#define                DMA5_CURR_Y_COUNT  0xffc00d78   /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define               DMA6_NEXT_DESC_PTR  0xffc00d80   /* DMA Channel 6 Next Descriptor Pointer Register */
-#define                  DMA6_START_ADDR  0xffc00d84   /* DMA Channel 6 Start Address Register */
-#define                      DMA6_CONFIG  0xffc00d88   /* DMA Channel 6 Configuration Register */
-#define                     DMA6_X_COUNT  0xffc00d90   /* DMA Channel 6 X Count Register */
-#define                    DMA6_X_MODIFY  0xffc00d94   /* DMA Channel 6 X Modify Register */
-#define                     DMA6_Y_COUNT  0xffc00d98   /* DMA Channel 6 Y Count Register */
-#define                    DMA6_Y_MODIFY  0xffc00d9c   /* DMA Channel 6 Y Modify Register */
-#define               DMA6_CURR_DESC_PTR  0xffc00da0   /* DMA Channel 6 Current Descriptor Pointer Register */
-#define                   DMA6_CURR_ADDR  0xffc00da4   /* DMA Channel 6 Current Address Register */
-#define                  DMA6_IRQ_STATUS  0xffc00da8   /* DMA Channel 6 Interrupt/Status Register */
-#define              DMA6_PERIPHERAL_MAP  0xffc00dac   /* DMA Channel 6 Peripheral Map Register */
-#define                DMA6_CURR_X_COUNT  0xffc00db0   /* DMA Channel 6 Current X Count Register */
-#define                DMA6_CURR_Y_COUNT  0xffc00db8   /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define               DMA7_NEXT_DESC_PTR  0xffc00dc0   /* DMA Channel 7 Next Descriptor Pointer Register */
-#define                  DMA7_START_ADDR  0xffc00dc4   /* DMA Channel 7 Start Address Register */
-#define                      DMA7_CONFIG  0xffc00dc8   /* DMA Channel 7 Configuration Register */
-#define                     DMA7_X_COUNT  0xffc00dd0   /* DMA Channel 7 X Count Register */
-#define                    DMA7_X_MODIFY  0xffc00dd4   /* DMA Channel 7 X Modify Register */
-#define                     DMA7_Y_COUNT  0xffc00dd8   /* DMA Channel 7 Y Count Register */
-#define                    DMA7_Y_MODIFY  0xffc00ddc   /* DMA Channel 7 Y Modify Register */
-#define               DMA7_CURR_DESC_PTR  0xffc00de0   /* DMA Channel 7 Current Descriptor Pointer Register */
-#define                   DMA7_CURR_ADDR  0xffc00de4   /* DMA Channel 7 Current Address Register */
-#define                  DMA7_IRQ_STATUS  0xffc00de8   /* DMA Channel 7 Interrupt/Status Register */
-#define              DMA7_PERIPHERAL_MAP  0xffc00dec   /* DMA Channel 7 Peripheral Map Register */
-#define                DMA7_CURR_X_COUNT  0xffc00df0   /* DMA Channel 7 Current X Count Register */
-#define                DMA7_CURR_Y_COUNT  0xffc00df8   /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define               DMA8_NEXT_DESC_PTR  0xffc00e00   /* DMA Channel 8 Next Descriptor Pointer Register */
-#define                  DMA8_START_ADDR  0xffc00e04   /* DMA Channel 8 Start Address Register */
-#define                      DMA8_CONFIG  0xffc00e08   /* DMA Channel 8 Configuration Register */
-#define                     DMA8_X_COUNT  0xffc00e10   /* DMA Channel 8 X Count Register */
-#define                    DMA8_X_MODIFY  0xffc00e14   /* DMA Channel 8 X Modify Register */
-#define                     DMA8_Y_COUNT  0xffc00e18   /* DMA Channel 8 Y Count Register */
-#define                    DMA8_Y_MODIFY  0xffc00e1c   /* DMA Channel 8 Y Modify Register */
-#define               DMA8_CURR_DESC_PTR  0xffc00e20   /* DMA Channel 8 Current Descriptor Pointer Register */
-#define                   DMA8_CURR_ADDR  0xffc00e24   /* DMA Channel 8 Current Address Register */
-#define                  DMA8_IRQ_STATUS  0xffc00e28   /* DMA Channel 8 Interrupt/Status Register */
-#define              DMA8_PERIPHERAL_MAP  0xffc00e2c   /* DMA Channel 8 Peripheral Map Register */
-#define                DMA8_CURR_X_COUNT  0xffc00e30   /* DMA Channel 8 Current X Count Register */
-#define                DMA8_CURR_Y_COUNT  0xffc00e38   /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define               DMA9_NEXT_DESC_PTR  0xffc00e40   /* DMA Channel 9 Next Descriptor Pointer Register */
-#define                  DMA9_START_ADDR  0xffc00e44   /* DMA Channel 9 Start Address Register */
-#define                      DMA9_CONFIG  0xffc00e48   /* DMA Channel 9 Configuration Register */
-#define                     DMA9_X_COUNT  0xffc00e50   /* DMA Channel 9 X Count Register */
-#define                    DMA9_X_MODIFY  0xffc00e54   /* DMA Channel 9 X Modify Register */
-#define                     DMA9_Y_COUNT  0xffc00e58   /* DMA Channel 9 Y Count Register */
-#define                    DMA9_Y_MODIFY  0xffc00e5c   /* DMA Channel 9 Y Modify Register */
-#define               DMA9_CURR_DESC_PTR  0xffc00e60   /* DMA Channel 9 Current Descriptor Pointer Register */
-#define                   DMA9_CURR_ADDR  0xffc00e64   /* DMA Channel 9 Current Address Register */
-#define                  DMA9_IRQ_STATUS  0xffc00e68   /* DMA Channel 9 Interrupt/Status Register */
-#define              DMA9_PERIPHERAL_MAP  0xffc00e6c   /* DMA Channel 9 Peripheral Map Register */
-#define                DMA9_CURR_X_COUNT  0xffc00e70   /* DMA Channel 9 Current X Count Register */
-#define                DMA9_CURR_Y_COUNT  0xffc00e78   /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define              DMA10_NEXT_DESC_PTR  0xffc00e80   /* DMA Channel 10 Next Descriptor Pointer Register */
-#define                 DMA10_START_ADDR  0xffc00e84   /* DMA Channel 10 Start Address Register */
-#define                     DMA10_CONFIG  0xffc00e88   /* DMA Channel 10 Configuration Register */
-#define                    DMA10_X_COUNT  0xffc00e90   /* DMA Channel 10 X Count Register */
-#define                   DMA10_X_MODIFY  0xffc00e94   /* DMA Channel 10 X Modify Register */
-#define                    DMA10_Y_COUNT  0xffc00e98   /* DMA Channel 10 Y Count Register */
-#define                   DMA10_Y_MODIFY  0xffc00e9c   /* DMA Channel 10 Y Modify Register */
-#define              DMA10_CURR_DESC_PTR  0xffc00ea0   /* DMA Channel 10 Current Descriptor Pointer Register */
-#define                  DMA10_CURR_ADDR  0xffc00ea4   /* DMA Channel 10 Current Address Register */
-#define                 DMA10_IRQ_STATUS  0xffc00ea8   /* DMA Channel 10 Interrupt/Status Register */
-#define             DMA10_PERIPHERAL_MAP  0xffc00eac   /* DMA Channel 10 Peripheral Map Register */
-#define               DMA10_CURR_X_COUNT  0xffc00eb0   /* DMA Channel 10 Current X Count Register */
-#define               DMA10_CURR_Y_COUNT  0xffc00eb8   /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define              DMA11_NEXT_DESC_PTR  0xffc00ec0   /* DMA Channel 11 Next Descriptor Pointer Register */
-#define                 DMA11_START_ADDR  0xffc00ec4   /* DMA Channel 11 Start Address Register */
-#define                     DMA11_CONFIG  0xffc00ec8   /* DMA Channel 11 Configuration Register */
-#define                    DMA11_X_COUNT  0xffc00ed0   /* DMA Channel 11 X Count Register */
-#define                   DMA11_X_MODIFY  0xffc00ed4   /* DMA Channel 11 X Modify Register */
-#define                    DMA11_Y_COUNT  0xffc00ed8   /* DMA Channel 11 Y Count Register */
-#define                   DMA11_Y_MODIFY  0xffc00edc   /* DMA Channel 11 Y Modify Register */
-#define              DMA11_CURR_DESC_PTR  0xffc00ee0   /* DMA Channel 11 Current Descriptor Pointer Register */
-#define                  DMA11_CURR_ADDR  0xffc00ee4   /* DMA Channel 11 Current Address Register */
-#define                 DMA11_IRQ_STATUS  0xffc00ee8   /* DMA Channel 11 Interrupt/Status Register */
-#define             DMA11_PERIPHERAL_MAP  0xffc00eec   /* DMA Channel 11 Peripheral Map Register */
-#define               DMA11_CURR_X_COUNT  0xffc00ef0   /* DMA Channel 11 Current X Count Register */
-#define               DMA11_CURR_Y_COUNT  0xffc00ef8   /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define            MDMA_D0_NEXT_DESC_PTR  0xffc00f00   /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define               MDMA_D0_START_ADDR  0xffc00f04   /* Memory DMA Stream 0 Destination Start Address Register */
-#define                   MDMA_D0_CONFIG  0xffc00f08   /* Memory DMA Stream 0 Destination Configuration Register */
-#define                  MDMA_D0_X_COUNT  0xffc00f10   /* Memory DMA Stream 0 Destination X Count Register */
-#define                 MDMA_D0_X_MODIFY  0xffc00f14   /* Memory DMA Stream 0 Destination X Modify Register */
-#define                  MDMA_D0_Y_COUNT  0xffc00f18   /* Memory DMA Stream 0 Destination Y Count Register */
-#define                 MDMA_D0_Y_MODIFY  0xffc00f1c   /* Memory DMA Stream 0 Destination Y Modify Register */
-#define            MDMA_D0_CURR_DESC_PTR  0xffc00f20   /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define                MDMA_D0_CURR_ADDR  0xffc00f24   /* Memory DMA Stream 0 Destination Current Address Register */
-#define               MDMA_D0_IRQ_STATUS  0xffc00f28   /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define           MDMA_D0_PERIPHERAL_MAP  0xffc00f2c   /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define             MDMA_D0_CURR_X_COUNT  0xffc00f30   /* Memory DMA Stream 0 Destination Current X Count Register */
-#define             MDMA_D0_CURR_Y_COUNT  0xffc00f38   /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define            MDMA_S0_NEXT_DESC_PTR  0xffc00f40   /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define               MDMA_S0_START_ADDR  0xffc00f44   /* Memory DMA Stream 0 Source Start Address Register */
-#define                   MDMA_S0_CONFIG  0xffc00f48   /* Memory DMA Stream 0 Source Configuration Register */
-#define                  MDMA_S0_X_COUNT  0xffc00f50   /* Memory DMA Stream 0 Source X Count Register */
-#define                 MDMA_S0_X_MODIFY  0xffc00f54   /* Memory DMA Stream 0 Source X Modify Register */
-#define                  MDMA_S0_Y_COUNT  0xffc00f58   /* Memory DMA Stream 0 Source Y Count Register */
-#define                 MDMA_S0_Y_MODIFY  0xffc00f5c   /* Memory DMA Stream 0 Source Y Modify Register */
-#define            MDMA_S0_CURR_DESC_PTR  0xffc00f60   /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define                MDMA_S0_CURR_ADDR  0xffc00f64   /* Memory DMA Stream 0 Source Current Address Register */
-#define               MDMA_S0_IRQ_STATUS  0xffc00f68   /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define           MDMA_S0_PERIPHERAL_MAP  0xffc00f6c   /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define             MDMA_S0_CURR_X_COUNT  0xffc00f70   /* Memory DMA Stream 0 Source Current X Count Register */
-#define             MDMA_S0_CURR_Y_COUNT  0xffc00f78   /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define            MDMA_D1_NEXT_DESC_PTR  0xffc00f80   /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define               MDMA_D1_START_ADDR  0xffc00f84   /* Memory DMA Stream 1 Destination Start Address Register */
-#define                   MDMA_D1_CONFIG  0xffc00f88   /* Memory DMA Stream 1 Destination Configuration Register */
-#define                  MDMA_D1_X_COUNT  0xffc00f90   /* Memory DMA Stream 1 Destination X Count Register */
-#define                 MDMA_D1_X_MODIFY  0xffc00f94   /* Memory DMA Stream 1 Destination X Modify Register */
-#define                  MDMA_D1_Y_COUNT  0xffc00f98   /* Memory DMA Stream 1 Destination Y Count Register */
-#define                 MDMA_D1_Y_MODIFY  0xffc00f9c   /* Memory DMA Stream 1 Destination Y Modify Register */
-#define            MDMA_D1_CURR_DESC_PTR  0xffc00fa0   /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define                MDMA_D1_CURR_ADDR  0xffc00fa4   /* Memory DMA Stream 1 Destination Current Address Register */
-#define               MDMA_D1_IRQ_STATUS  0xffc00fa8   /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define           MDMA_D1_PERIPHERAL_MAP  0xffc00fac   /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define             MDMA_D1_CURR_X_COUNT  0xffc00fb0   /* Memory DMA Stream 1 Destination Current X Count Register */
-#define             MDMA_D1_CURR_Y_COUNT  0xffc00fb8   /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define            MDMA_S1_NEXT_DESC_PTR  0xffc00fc0   /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define               MDMA_S1_START_ADDR  0xffc00fc4   /* Memory DMA Stream 1 Source Start Address Register */
-#define                   MDMA_S1_CONFIG  0xffc00fc8   /* Memory DMA Stream 1 Source Configuration Register */
-#define                  MDMA_S1_X_COUNT  0xffc00fd0   /* Memory DMA Stream 1 Source X Count Register */
-#define                 MDMA_S1_X_MODIFY  0xffc00fd4   /* Memory DMA Stream 1 Source X Modify Register */
-#define                  MDMA_S1_Y_COUNT  0xffc00fd8   /* Memory DMA Stream 1 Source Y Count Register */
-#define                 MDMA_S1_Y_MODIFY  0xffc00fdc   /* Memory DMA Stream 1 Source Y Modify Register */
-#define            MDMA_S1_CURR_DESC_PTR  0xffc00fe0   /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define                MDMA_S1_CURR_ADDR  0xffc00fe4   /* Memory DMA Stream 1 Source Current Address Register */
-#define               MDMA_S1_IRQ_STATUS  0xffc00fe8   /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define           MDMA_S1_PERIPHERAL_MAP  0xffc00fec   /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define             MDMA_S1_CURR_X_COUNT  0xffc00ff0   /* Memory DMA Stream 1 Source Current X Count Register */
-#define             MDMA_S1_CURR_Y_COUNT  0xffc00ff8   /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
-#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
-#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
-#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
-#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
-#define                        UART3_LSR  0xffc03114   /* Line Status Register */
-#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
-#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
-#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
-#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
-#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
-#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define                     EPPI1_STATUS  0xffc01300   /* EPPI1 Status Register */
-#define                     EPPI1_HCOUNT  0xffc01304   /* EPPI1 Horizontal Transfer Count Register */
-#define                     EPPI1_HDELAY  0xffc01308   /* EPPI1 Horizontal Delay Count Register */
-#define                     EPPI1_VCOUNT  0xffc0130c   /* EPPI1 Vertical Transfer Count Register */
-#define                     EPPI1_VDELAY  0xffc01310   /* EPPI1 Vertical Delay Count Register */
-#define                      EPPI1_FRAME  0xffc01314   /* EPPI1 Lines per Frame Register */
-#define                       EPPI1_LINE  0xffc01318   /* EPPI1 Samples per Line Register */
-#define                     EPPI1_CLKDIV  0xffc0131c   /* EPPI1 Clock Divide Register */
-#define                    EPPI1_CONTROL  0xffc01320   /* EPPI1 Control Register */
-#define                   EPPI1_FS1W_HBL  0xffc01324   /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI1_FS1P_AVPL  0xffc01328   /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define                   EPPI1_FS2W_LVB  0xffc0132c   /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define                  EPPI1_FS2P_LAVF  0xffc01330   /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define                       EPPI1_CLIP  0xffc01334   /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define                   PINT0_MASK_SET  0xffc01400   /* Pin Interrupt 0 Mask Set Register */
-#define                 PINT0_MASK_CLEAR  0xffc01404   /* Pin Interrupt 0 Mask Clear Register */
-#define                    PINT0_REQUEST  0xffc01408   /* Pin Interrupt 0 Interrupt Request Register */
-#define                     PINT0_ASSIGN  0xffc0140c   /* Pin Interrupt 0 Port Assign Register */
-#define                   PINT0_EDGE_SET  0xffc01410   /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define                 PINT0_EDGE_CLEAR  0xffc01414   /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define                 PINT0_INVERT_SET  0xffc01418   /* Pin Interrupt 0 Inversion Set Register */
-#define               PINT0_INVERT_CLEAR  0xffc0141c   /* Pin Interrupt 0 Inversion Clear Register */
-#define                   PINT0_PINSTATE  0xffc01420   /* Pin Interrupt 0 Pin Status Register */
-#define                      PINT0_LATCH  0xffc01424   /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define                   PINT1_MASK_SET  0xffc01430   /* Pin Interrupt 1 Mask Set Register */
-#define                 PINT1_MASK_CLEAR  0xffc01434   /* Pin Interrupt 1 Mask Clear Register */
-#define                    PINT1_REQUEST  0xffc01438   /* Pin Interrupt 1 Interrupt Request Register */
-#define                     PINT1_ASSIGN  0xffc0143c   /* Pin Interrupt 1 Port Assign Register */
-#define                   PINT1_EDGE_SET  0xffc01440   /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define                 PINT1_EDGE_CLEAR  0xffc01444   /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define                 PINT1_INVERT_SET  0xffc01448   /* Pin Interrupt 1 Inversion Set Register */
-#define               PINT1_INVERT_CLEAR  0xffc0144c   /* Pin Interrupt 1 Inversion Clear Register */
-#define                   PINT1_PINSTATE  0xffc01450   /* Pin Interrupt 1 Pin Status Register */
-#define                      PINT1_LATCH  0xffc01454   /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define                   PINT2_MASK_SET  0xffc01460   /* Pin Interrupt 2 Mask Set Register */
-#define                 PINT2_MASK_CLEAR  0xffc01464   /* Pin Interrupt 2 Mask Clear Register */
-#define                    PINT2_REQUEST  0xffc01468   /* Pin Interrupt 2 Interrupt Request Register */
-#define                     PINT2_ASSIGN  0xffc0146c   /* Pin Interrupt 2 Port Assign Register */
-#define                   PINT2_EDGE_SET  0xffc01470   /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define                 PINT2_EDGE_CLEAR  0xffc01474   /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define                 PINT2_INVERT_SET  0xffc01478   /* Pin Interrupt 2 Inversion Set Register */
-#define               PINT2_INVERT_CLEAR  0xffc0147c   /* Pin Interrupt 2 Inversion Clear Register */
-#define                   PINT2_PINSTATE  0xffc01480   /* Pin Interrupt 2 Pin Status Register */
-#define                      PINT2_LATCH  0xffc01484   /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define                   PINT3_MASK_SET  0xffc01490   /* Pin Interrupt 3 Mask Set Register */
-#define                 PINT3_MASK_CLEAR  0xffc01494   /* Pin Interrupt 3 Mask Clear Register */
-#define                    PINT3_REQUEST  0xffc01498   /* Pin Interrupt 3 Interrupt Request Register */
-#define                     PINT3_ASSIGN  0xffc0149c   /* Pin Interrupt 3 Port Assign Register */
-#define                   PINT3_EDGE_SET  0xffc014a0   /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define                 PINT3_EDGE_CLEAR  0xffc014a4   /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define                 PINT3_INVERT_SET  0xffc014a8   /* Pin Interrupt 3 Inversion Set Register */
-#define               PINT3_INVERT_CLEAR  0xffc014ac   /* Pin Interrupt 3 Inversion Clear Register */
-#define                   PINT3_PINSTATE  0xffc014b0   /* Pin Interrupt 3 Pin Status Register */
-#define                      PINT3_LATCH  0xffc014b4   /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define                        PORTA_FER  0xffc014c0   /* Function Enable Register */
-#define                            PORTA  0xffc014c4   /* GPIO Data Register */
-#define                        PORTA_SET  0xffc014c8   /* GPIO Data Set Register */
-#define                      PORTA_CLEAR  0xffc014cc   /* GPIO Data Clear Register */
-#define                    PORTA_DIR_SET  0xffc014d0   /* GPIO Direction Set Register */
-#define                  PORTA_DIR_CLEAR  0xffc014d4   /* GPIO Direction Clear Register */
-#define                       PORTA_INEN  0xffc014d8   /* GPIO Input Enable Register */
-#define                        PORTA_MUX  0xffc014dc   /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define                        PORTB_FER  0xffc014e0   /* Function Enable Register */
-#define                            PORTB  0xffc014e4   /* GPIO Data Register */
-#define                        PORTB_SET  0xffc014e8   /* GPIO Data Set Register */
-#define                      PORTB_CLEAR  0xffc014ec   /* GPIO Data Clear Register */
-#define                    PORTB_DIR_SET  0xffc014f0   /* GPIO Direction Set Register */
-#define                  PORTB_DIR_CLEAR  0xffc014f4   /* GPIO Direction Clear Register */
-#define                       PORTB_INEN  0xffc014f8   /* GPIO Input Enable Register */
-#define                        PORTB_MUX  0xffc014fc   /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define                        PORTC_FER  0xffc01500   /* Function Enable Register */
-#define                            PORTC  0xffc01504   /* GPIO Data Register */
-#define                        PORTC_SET  0xffc01508   /* GPIO Data Set Register */
-#define                      PORTC_CLEAR  0xffc0150c   /* GPIO Data Clear Register */
-#define                    PORTC_DIR_SET  0xffc01510   /* GPIO Direction Set Register */
-#define                  PORTC_DIR_CLEAR  0xffc01514   /* GPIO Direction Clear Register */
-#define                       PORTC_INEN  0xffc01518   /* GPIO Input Enable Register */
-#define                        PORTC_MUX  0xffc0151c   /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define                        PORTD_FER  0xffc01520   /* Function Enable Register */
-#define                            PORTD  0xffc01524   /* GPIO Data Register */
-#define                        PORTD_SET  0xffc01528   /* GPIO Data Set Register */
-#define                      PORTD_CLEAR  0xffc0152c   /* GPIO Data Clear Register */
-#define                    PORTD_DIR_SET  0xffc01530   /* GPIO Direction Set Register */
-#define                  PORTD_DIR_CLEAR  0xffc01534   /* GPIO Direction Clear Register */
-#define                       PORTD_INEN  0xffc01538   /* GPIO Input Enable Register */
-#define                        PORTD_MUX  0xffc0153c   /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define                        PORTE_FER  0xffc01540   /* Function Enable Register */
-#define                            PORTE  0xffc01544   /* GPIO Data Register */
-#define                        PORTE_SET  0xffc01548   /* GPIO Data Set Register */
-#define                      PORTE_CLEAR  0xffc0154c   /* GPIO Data Clear Register */
-#define                    PORTE_DIR_SET  0xffc01550   /* GPIO Direction Set Register */
-#define                  PORTE_DIR_CLEAR  0xffc01554   /* GPIO Direction Clear Register */
-#define                       PORTE_INEN  0xffc01558   /* GPIO Input Enable Register */
-#define                        PORTE_MUX  0xffc0155c   /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define                        PORTF_FER  0xffc01560   /* Function Enable Register */
-#define                            PORTF  0xffc01564   /* GPIO Data Register */
-#define                        PORTF_SET  0xffc01568   /* GPIO Data Set Register */
-#define                      PORTF_CLEAR  0xffc0156c   /* GPIO Data Clear Register */
-#define                    PORTF_DIR_SET  0xffc01570   /* GPIO Direction Set Register */
-#define                  PORTF_DIR_CLEAR  0xffc01574   /* GPIO Direction Clear Register */
-#define                       PORTF_INEN  0xffc01578   /* GPIO Input Enable Register */
-#define                        PORTF_MUX  0xffc0157c   /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define                        PORTG_FER  0xffc01580   /* Function Enable Register */
-#define                            PORTG  0xffc01584   /* GPIO Data Register */
-#define                        PORTG_SET  0xffc01588   /* GPIO Data Set Register */
-#define                      PORTG_CLEAR  0xffc0158c   /* GPIO Data Clear Register */
-#define                    PORTG_DIR_SET  0xffc01590   /* GPIO Direction Set Register */
-#define                  PORTG_DIR_CLEAR  0xffc01594   /* GPIO Direction Clear Register */
-#define                       PORTG_INEN  0xffc01598   /* GPIO Input Enable Register */
-#define                        PORTG_MUX  0xffc0159c   /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define                        PORTH_FER  0xffc015a0   /* Function Enable Register */
-#define                            PORTH  0xffc015a4   /* GPIO Data Register */
-#define                        PORTH_SET  0xffc015a8   /* GPIO Data Set Register */
-#define                      PORTH_CLEAR  0xffc015ac   /* GPIO Data Clear Register */
-#define                    PORTH_DIR_SET  0xffc015b0   /* GPIO Direction Set Register */
-#define                  PORTH_DIR_CLEAR  0xffc015b4   /* GPIO Direction Clear Register */
-#define                       PORTH_INEN  0xffc015b8   /* GPIO Input Enable Register */
-#define                        PORTH_MUX  0xffc015bc   /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define                        PORTI_FER  0xffc015c0   /* Function Enable Register */
-#define                            PORTI  0xffc015c4   /* GPIO Data Register */
-#define                        PORTI_SET  0xffc015c8   /* GPIO Data Set Register */
-#define                      PORTI_CLEAR  0xffc015cc   /* GPIO Data Clear Register */
-#define                    PORTI_DIR_SET  0xffc015d0   /* GPIO Direction Set Register */
-#define                  PORTI_DIR_CLEAR  0xffc015d4   /* GPIO Direction Clear Register */
-#define                       PORTI_INEN  0xffc015d8   /* GPIO Input Enable Register */
-#define                        PORTI_MUX  0xffc015dc   /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define                        PORTJ_FER  0xffc015e0   /* Function Enable Register */
-#define                            PORTJ  0xffc015e4   /* GPIO Data Register */
-#define                        PORTJ_SET  0xffc015e8   /* GPIO Data Set Register */
-#define                      PORTJ_CLEAR  0xffc015ec   /* GPIO Data Clear Register */
-#define                    PORTJ_DIR_SET  0xffc015f0   /* GPIO Direction Set Register */
-#define                  PORTJ_DIR_CLEAR  0xffc015f4   /* GPIO Direction Clear Register */
-#define                       PORTJ_INEN  0xffc015f8   /* GPIO Input Enable Register */
-#define                        PORTJ_MUX  0xffc015fc   /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define                    TIMER0_CONFIG  0xffc01600   /* Timer 0 Configuration Register */
-#define                   TIMER0_COUNTER  0xffc01604   /* Timer 0 Counter Register */
-#define                    TIMER0_PERIOD  0xffc01608   /* Timer 0 Period Register */
-#define                     TIMER0_WIDTH  0xffc0160c   /* Timer 0 Width Register */
-#define                    TIMER1_CONFIG  0xffc01610   /* Timer 1 Configuration Register */
-#define                   TIMER1_COUNTER  0xffc01614   /* Timer 1 Counter Register */
-#define                    TIMER1_PERIOD  0xffc01618   /* Timer 1 Period Register */
-#define                     TIMER1_WIDTH  0xffc0161c   /* Timer 1 Width Register */
-#define                    TIMER2_CONFIG  0xffc01620   /* Timer 2 Configuration Register */
-#define                   TIMER2_COUNTER  0xffc01624   /* Timer 2 Counter Register */
-#define                    TIMER2_PERIOD  0xffc01628   /* Timer 2 Period Register */
-#define                     TIMER2_WIDTH  0xffc0162c   /* Timer 2 Width Register */
-#define                    TIMER3_CONFIG  0xffc01630   /* Timer 3 Configuration Register */
-#define                   TIMER3_COUNTER  0xffc01634   /* Timer 3 Counter Register */
-#define                    TIMER3_PERIOD  0xffc01638   /* Timer 3 Period Register */
-#define                     TIMER3_WIDTH  0xffc0163c   /* Timer 3 Width Register */
-#define                    TIMER4_CONFIG  0xffc01640   /* Timer 4 Configuration Register */
-#define                   TIMER4_COUNTER  0xffc01644   /* Timer 4 Counter Register */
-#define                    TIMER4_PERIOD  0xffc01648   /* Timer 4 Period Register */
-#define                     TIMER4_WIDTH  0xffc0164c   /* Timer 4 Width Register */
-#define                    TIMER5_CONFIG  0xffc01650   /* Timer 5 Configuration Register */
-#define                   TIMER5_COUNTER  0xffc01654   /* Timer 5 Counter Register */
-#define                    TIMER5_PERIOD  0xffc01658   /* Timer 5 Period Register */
-#define                     TIMER5_WIDTH  0xffc0165c   /* Timer 5 Width Register */
-#define                    TIMER6_CONFIG  0xffc01660   /* Timer 6 Configuration Register */
-#define                   TIMER6_COUNTER  0xffc01664   /* Timer 6 Counter Register */
-#define                    TIMER6_PERIOD  0xffc01668   /* Timer 6 Period Register */
-#define                     TIMER6_WIDTH  0xffc0166c   /* Timer 6 Width Register */
-#define                    TIMER7_CONFIG  0xffc01670   /* Timer 7 Configuration Register */
-#define                   TIMER7_COUNTER  0xffc01674   /* Timer 7 Counter Register */
-#define                    TIMER7_PERIOD  0xffc01678   /* Timer 7 Period Register */
-#define                     TIMER7_WIDTH  0xffc0167c   /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define                    TIMER_ENABLE0  0xffc01680   /* Timer Group of 8 Enable Register */
-#define                   TIMER_DISABLE0  0xffc01684   /* Timer Group of 8 Disable Register */
-#define                    TIMER_STATUS0  0xffc01688   /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define                      DMAC1_TCPER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
-#define                      DMAC1_TCCNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define              DMA12_NEXT_DESC_PTR  0xffc01c00   /* DMA Channel 12 Next Descriptor Pointer Register */
-#define                 DMA12_START_ADDR  0xffc01c04   /* DMA Channel 12 Start Address Register */
-#define                     DMA12_CONFIG  0xffc01c08   /* DMA Channel 12 Configuration Register */
-#define                    DMA12_X_COUNT  0xffc01c10   /* DMA Channel 12 X Count Register */
-#define                   DMA12_X_MODIFY  0xffc01c14   /* DMA Channel 12 X Modify Register */
-#define                    DMA12_Y_COUNT  0xffc01c18   /* DMA Channel 12 Y Count Register */
-#define                   DMA12_Y_MODIFY  0xffc01c1c   /* DMA Channel 12 Y Modify Register */
-#define              DMA12_CURR_DESC_PTR  0xffc01c20   /* DMA Channel 12 Current Descriptor Pointer Register */
-#define                  DMA12_CURR_ADDR  0xffc01c24   /* DMA Channel 12 Current Address Register */
-#define                 DMA12_IRQ_STATUS  0xffc01c28   /* DMA Channel 12 Interrupt/Status Register */
-#define             DMA12_PERIPHERAL_MAP  0xffc01c2c   /* DMA Channel 12 Peripheral Map Register */
-#define               DMA12_CURR_X_COUNT  0xffc01c30   /* DMA Channel 12 Current X Count Register */
-#define               DMA12_CURR_Y_COUNT  0xffc01c38   /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define              DMA13_NEXT_DESC_PTR  0xffc01c40   /* DMA Channel 13 Next Descriptor Pointer Register */
-#define                 DMA13_START_ADDR  0xffc01c44   /* DMA Channel 13 Start Address Register */
-#define                     DMA13_CONFIG  0xffc01c48   /* DMA Channel 13 Configuration Register */
-#define                    DMA13_X_COUNT  0xffc01c50   /* DMA Channel 13 X Count Register */
-#define                   DMA13_X_MODIFY  0xffc01c54   /* DMA Channel 13 X Modify Register */
-#define                    DMA13_Y_COUNT  0xffc01c58   /* DMA Channel 13 Y Count Register */
-#define                   DMA13_Y_MODIFY  0xffc01c5c   /* DMA Channel 13 Y Modify Register */
-#define              DMA13_CURR_DESC_PTR  0xffc01c60   /* DMA Channel 13 Current Descriptor Pointer Register */
-#define                  DMA13_CURR_ADDR  0xffc01c64   /* DMA Channel 13 Current Address Register */
-#define                 DMA13_IRQ_STATUS  0xffc01c68   /* DMA Channel 13 Interrupt/Status Register */
-#define             DMA13_PERIPHERAL_MAP  0xffc01c6c   /* DMA Channel 13 Peripheral Map Register */
-#define               DMA13_CURR_X_COUNT  0xffc01c70   /* DMA Channel 13 Current X Count Register */
-#define               DMA13_CURR_Y_COUNT  0xffc01c78   /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define              DMA14_NEXT_DESC_PTR  0xffc01c80   /* DMA Channel 14 Next Descriptor Pointer Register */
-#define                 DMA14_START_ADDR  0xffc01c84   /* DMA Channel 14 Start Address Register */
-#define                     DMA14_CONFIG  0xffc01c88   /* DMA Channel 14 Configuration Register */
-#define                    DMA14_X_COUNT  0xffc01c90   /* DMA Channel 14 X Count Register */
-#define                   DMA14_X_MODIFY  0xffc01c94   /* DMA Channel 14 X Modify Register */
-#define                    DMA14_Y_COUNT  0xffc01c98   /* DMA Channel 14 Y Count Register */
-#define                   DMA14_Y_MODIFY  0xffc01c9c   /* DMA Channel 14 Y Modify Register */
-#define              DMA14_CURR_DESC_PTR  0xffc01ca0   /* DMA Channel 14 Current Descriptor Pointer Register */
-#define                  DMA14_CURR_ADDR  0xffc01ca4   /* DMA Channel 14 Current Address Register */
-#define                 DMA14_IRQ_STATUS  0xffc01ca8   /* DMA Channel 14 Interrupt/Status Register */
-#define             DMA14_PERIPHERAL_MAP  0xffc01cac   /* DMA Channel 14 Peripheral Map Register */
-#define               DMA14_CURR_X_COUNT  0xffc01cb0   /* DMA Channel 14 Current X Count Register */
-#define               DMA14_CURR_Y_COUNT  0xffc01cb8   /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define              DMA15_NEXT_DESC_PTR  0xffc01cc0   /* DMA Channel 15 Next Descriptor Pointer Register */
-#define                 DMA15_START_ADDR  0xffc01cc4   /* DMA Channel 15 Start Address Register */
-#define                     DMA15_CONFIG  0xffc01cc8   /* DMA Channel 15 Configuration Register */
-#define                    DMA15_X_COUNT  0xffc01cd0   /* DMA Channel 15 X Count Register */
-#define                   DMA15_X_MODIFY  0xffc01cd4   /* DMA Channel 15 X Modify Register */
-#define                    DMA15_Y_COUNT  0xffc01cd8   /* DMA Channel 15 Y Count Register */
-#define                   DMA15_Y_MODIFY  0xffc01cdc   /* DMA Channel 15 Y Modify Register */
-#define              DMA15_CURR_DESC_PTR  0xffc01ce0   /* DMA Channel 15 Current Descriptor Pointer Register */
-#define                  DMA15_CURR_ADDR  0xffc01ce4   /* DMA Channel 15 Current Address Register */
-#define                 DMA15_IRQ_STATUS  0xffc01ce8   /* DMA Channel 15 Interrupt/Status Register */
-#define             DMA15_PERIPHERAL_MAP  0xffc01cec   /* DMA Channel 15 Peripheral Map Register */
-#define               DMA15_CURR_X_COUNT  0xffc01cf0   /* DMA Channel 15 Current X Count Register */
-#define               DMA15_CURR_Y_COUNT  0xffc01cf8   /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define              DMA16_NEXT_DESC_PTR  0xffc01d00   /* DMA Channel 16 Next Descriptor Pointer Register */
-#define                 DMA16_START_ADDR  0xffc01d04   /* DMA Channel 16 Start Address Register */
-#define                     DMA16_CONFIG  0xffc01d08   /* DMA Channel 16 Configuration Register */
-#define                    DMA16_X_COUNT  0xffc01d10   /* DMA Channel 16 X Count Register */
-#define                   DMA16_X_MODIFY  0xffc01d14   /* DMA Channel 16 X Modify Register */
-#define                    DMA16_Y_COUNT  0xffc01d18   /* DMA Channel 16 Y Count Register */
-#define                   DMA16_Y_MODIFY  0xffc01d1c   /* DMA Channel 16 Y Modify Register */
-#define              DMA16_CURR_DESC_PTR  0xffc01d20   /* DMA Channel 16 Current Descriptor Pointer Register */
-#define                  DMA16_CURR_ADDR  0xffc01d24   /* DMA Channel 16 Current Address Register */
-#define                 DMA16_IRQ_STATUS  0xffc01d28   /* DMA Channel 16 Interrupt/Status Register */
-#define             DMA16_PERIPHERAL_MAP  0xffc01d2c   /* DMA Channel 16 Peripheral Map Register */
-#define               DMA16_CURR_X_COUNT  0xffc01d30   /* DMA Channel 16 Current X Count Register */
-#define               DMA16_CURR_Y_COUNT  0xffc01d38   /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define              DMA17_NEXT_DESC_PTR  0xffc01d40   /* DMA Channel 17 Next Descriptor Pointer Register */
-#define                 DMA17_START_ADDR  0xffc01d44   /* DMA Channel 17 Start Address Register */
-#define                     DMA17_CONFIG  0xffc01d48   /* DMA Channel 17 Configuration Register */
-#define                    DMA17_X_COUNT  0xffc01d50   /* DMA Channel 17 X Count Register */
-#define                   DMA17_X_MODIFY  0xffc01d54   /* DMA Channel 17 X Modify Register */
-#define                    DMA17_Y_COUNT  0xffc01d58   /* DMA Channel 17 Y Count Register */
-#define                   DMA17_Y_MODIFY  0xffc01d5c   /* DMA Channel 17 Y Modify Register */
-#define              DMA17_CURR_DESC_PTR  0xffc01d60   /* DMA Channel 17 Current Descriptor Pointer Register */
-#define                  DMA17_CURR_ADDR  0xffc01d64   /* DMA Channel 17 Current Address Register */
-#define                 DMA17_IRQ_STATUS  0xffc01d68   /* DMA Channel 17 Interrupt/Status Register */
-#define             DMA17_PERIPHERAL_MAP  0xffc01d6c   /* DMA Channel 17 Peripheral Map Register */
-#define               DMA17_CURR_X_COUNT  0xffc01d70   /* DMA Channel 17 Current X Count Register */
-#define               DMA17_CURR_Y_COUNT  0xffc01d78   /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define              DMA18_NEXT_DESC_PTR  0xffc01d80   /* DMA Channel 18 Next Descriptor Pointer Register */
-#define                 DMA18_START_ADDR  0xffc01d84   /* DMA Channel 18 Start Address Register */
-#define                     DMA18_CONFIG  0xffc01d88   /* DMA Channel 18 Configuration Register */
-#define                    DMA18_X_COUNT  0xffc01d90   /* DMA Channel 18 X Count Register */
-#define                   DMA18_X_MODIFY  0xffc01d94   /* DMA Channel 18 X Modify Register */
-#define                    DMA18_Y_COUNT  0xffc01d98   /* DMA Channel 18 Y Count Register */
-#define                   DMA18_Y_MODIFY  0xffc01d9c   /* DMA Channel 18 Y Modify Register */
-#define              DMA18_CURR_DESC_PTR  0xffc01da0   /* DMA Channel 18 Current Descriptor Pointer Register */
-#define                  DMA18_CURR_ADDR  0xffc01da4   /* DMA Channel 18 Current Address Register */
-#define                 DMA18_IRQ_STATUS  0xffc01da8   /* DMA Channel 18 Interrupt/Status Register */
-#define             DMA18_PERIPHERAL_MAP  0xffc01dac   /* DMA Channel 18 Peripheral Map Register */
-#define               DMA18_CURR_X_COUNT  0xffc01db0   /* DMA Channel 18 Current X Count Register */
-#define               DMA18_CURR_Y_COUNT  0xffc01db8   /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define              DMA19_NEXT_DESC_PTR  0xffc01dc0   /* DMA Channel 19 Next Descriptor Pointer Register */
-#define                 DMA19_START_ADDR  0xffc01dc4   /* DMA Channel 19 Start Address Register */
-#define                     DMA19_CONFIG  0xffc01dc8   /* DMA Channel 19 Configuration Register */
-#define                    DMA19_X_COUNT  0xffc01dd0   /* DMA Channel 19 X Count Register */
-#define                   DMA19_X_MODIFY  0xffc01dd4   /* DMA Channel 19 X Modify Register */
-#define                    DMA19_Y_COUNT  0xffc01dd8   /* DMA Channel 19 Y Count Register */
-#define                   DMA19_Y_MODIFY  0xffc01ddc   /* DMA Channel 19 Y Modify Register */
-#define              DMA19_CURR_DESC_PTR  0xffc01de0   /* DMA Channel 19 Current Descriptor Pointer Register */
-#define                  DMA19_CURR_ADDR  0xffc01de4   /* DMA Channel 19 Current Address Register */
-#define                 DMA19_IRQ_STATUS  0xffc01de8   /* DMA Channel 19 Interrupt/Status Register */
-#define             DMA19_PERIPHERAL_MAP  0xffc01dec   /* DMA Channel 19 Peripheral Map Register */
-#define               DMA19_CURR_X_COUNT  0xffc01df0   /* DMA Channel 19 Current X Count Register */
-#define               DMA19_CURR_Y_COUNT  0xffc01df8   /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define              DMA20_NEXT_DESC_PTR  0xffc01e00   /* DMA Channel 20 Next Descriptor Pointer Register */
-#define                 DMA20_START_ADDR  0xffc01e04   /* DMA Channel 20 Start Address Register */
-#define                     DMA20_CONFIG  0xffc01e08   /* DMA Channel 20 Configuration Register */
-#define                    DMA20_X_COUNT  0xffc01e10   /* DMA Channel 20 X Count Register */
-#define                   DMA20_X_MODIFY  0xffc01e14   /* DMA Channel 20 X Modify Register */
-#define                    DMA20_Y_COUNT  0xffc01e18   /* DMA Channel 20 Y Count Register */
-#define                   DMA20_Y_MODIFY  0xffc01e1c   /* DMA Channel 20 Y Modify Register */
-#define              DMA20_CURR_DESC_PTR  0xffc01e20   /* DMA Channel 20 Current Descriptor Pointer Register */
-#define                  DMA20_CURR_ADDR  0xffc01e24   /* DMA Channel 20 Current Address Register */
-#define                 DMA20_IRQ_STATUS  0xffc01e28   /* DMA Channel 20 Interrupt/Status Register */
-#define             DMA20_PERIPHERAL_MAP  0xffc01e2c   /* DMA Channel 20 Peripheral Map Register */
-#define               DMA20_CURR_X_COUNT  0xffc01e30   /* DMA Channel 20 Current X Count Register */
-#define               DMA20_CURR_Y_COUNT  0xffc01e38   /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define              DMA21_NEXT_DESC_PTR  0xffc01e40   /* DMA Channel 21 Next Descriptor Pointer Register */
-#define                 DMA21_START_ADDR  0xffc01e44   /* DMA Channel 21 Start Address Register */
-#define                     DMA21_CONFIG  0xffc01e48   /* DMA Channel 21 Configuration Register */
-#define                    DMA21_X_COUNT  0xffc01e50   /* DMA Channel 21 X Count Register */
-#define                   DMA21_X_MODIFY  0xffc01e54   /* DMA Channel 21 X Modify Register */
-#define                    DMA21_Y_COUNT  0xffc01e58   /* DMA Channel 21 Y Count Register */
-#define                   DMA21_Y_MODIFY  0xffc01e5c   /* DMA Channel 21 Y Modify Register */
-#define              DMA21_CURR_DESC_PTR  0xffc01e60   /* DMA Channel 21 Current Descriptor Pointer Register */
-#define                  DMA21_CURR_ADDR  0xffc01e64   /* DMA Channel 21 Current Address Register */
-#define                 DMA21_IRQ_STATUS  0xffc01e68   /* DMA Channel 21 Interrupt/Status Register */
-#define             DMA21_PERIPHERAL_MAP  0xffc01e6c   /* DMA Channel 21 Peripheral Map Register */
-#define               DMA21_CURR_X_COUNT  0xffc01e70   /* DMA Channel 21 Current X Count Register */
-#define               DMA21_CURR_Y_COUNT  0xffc01e78   /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define              DMA22_NEXT_DESC_PTR  0xffc01e80   /* DMA Channel 22 Next Descriptor Pointer Register */
-#define                 DMA22_START_ADDR  0xffc01e84   /* DMA Channel 22 Start Address Register */
-#define                     DMA22_CONFIG  0xffc01e88   /* DMA Channel 22 Configuration Register */
-#define                    DMA22_X_COUNT  0xffc01e90   /* DMA Channel 22 X Count Register */
-#define                   DMA22_X_MODIFY  0xffc01e94   /* DMA Channel 22 X Modify Register */
-#define                    DMA22_Y_COUNT  0xffc01e98   /* DMA Channel 22 Y Count Register */
-#define                   DMA22_Y_MODIFY  0xffc01e9c   /* DMA Channel 22 Y Modify Register */
-#define              DMA22_CURR_DESC_PTR  0xffc01ea0   /* DMA Channel 22 Current Descriptor Pointer Register */
-#define                  DMA22_CURR_ADDR  0xffc01ea4   /* DMA Channel 22 Current Address Register */
-#define                 DMA22_IRQ_STATUS  0xffc01ea8   /* DMA Channel 22 Interrupt/Status Register */
-#define             DMA22_PERIPHERAL_MAP  0xffc01eac   /* DMA Channel 22 Peripheral Map Register */
-#define               DMA22_CURR_X_COUNT  0xffc01eb0   /* DMA Channel 22 Current X Count Register */
-#define               DMA22_CURR_Y_COUNT  0xffc01eb8   /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define              DMA23_NEXT_DESC_PTR  0xffc01ec0   /* DMA Channel 23 Next Descriptor Pointer Register */
-#define                 DMA23_START_ADDR  0xffc01ec4   /* DMA Channel 23 Start Address Register */
-#define                     DMA23_CONFIG  0xffc01ec8   /* DMA Channel 23 Configuration Register */
-#define                    DMA23_X_COUNT  0xffc01ed0   /* DMA Channel 23 X Count Register */
-#define                   DMA23_X_MODIFY  0xffc01ed4   /* DMA Channel 23 X Modify Register */
-#define                    DMA23_Y_COUNT  0xffc01ed8   /* DMA Channel 23 Y Count Register */
-#define                   DMA23_Y_MODIFY  0xffc01edc   /* DMA Channel 23 Y Modify Register */
-#define              DMA23_CURR_DESC_PTR  0xffc01ee0   /* DMA Channel 23 Current Descriptor Pointer Register */
-#define                  DMA23_CURR_ADDR  0xffc01ee4   /* DMA Channel 23 Current Address Register */
-#define                 DMA23_IRQ_STATUS  0xffc01ee8   /* DMA Channel 23 Interrupt/Status Register */
-#define             DMA23_PERIPHERAL_MAP  0xffc01eec   /* DMA Channel 23 Peripheral Map Register */
-#define               DMA23_CURR_X_COUNT  0xffc01ef0   /* DMA Channel 23 Current X Count Register */
-#define               DMA23_CURR_Y_COUNT  0xffc01ef8   /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define            MDMA_D2_NEXT_DESC_PTR  0xffc01f00   /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define               MDMA_D2_START_ADDR  0xffc01f04   /* Memory DMA Stream 2 Destination Start Address Register */
-#define                   MDMA_D2_CONFIG  0xffc01f08   /* Memory DMA Stream 2 Destination Configuration Register */
-#define                  MDMA_D2_X_COUNT  0xffc01f10   /* Memory DMA Stream 2 Destination X Count Register */
-#define                 MDMA_D2_X_MODIFY  0xffc01f14   /* Memory DMA Stream 2 Destination X Modify Register */
-#define                  MDMA_D2_Y_COUNT  0xffc01f18   /* Memory DMA Stream 2 Destination Y Count Register */
-#define                 MDMA_D2_Y_MODIFY  0xffc01f1c   /* Memory DMA Stream 2 Destination Y Modify Register */
-#define            MDMA_D2_CURR_DESC_PTR  0xffc01f20   /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define                MDMA_D2_CURR_ADDR  0xffc01f24   /* Memory DMA Stream 2 Destination Current Address Register */
-#define               MDMA_D2_IRQ_STATUS  0xffc01f28   /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define           MDMA_D2_PERIPHERAL_MAP  0xffc01f2c   /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define             MDMA_D2_CURR_X_COUNT  0xffc01f30   /* Memory DMA Stream 2 Destination Current X Count Register */
-#define             MDMA_D2_CURR_Y_COUNT  0xffc01f38   /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define            MDMA_S2_NEXT_DESC_PTR  0xffc01f40   /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define               MDMA_S2_START_ADDR  0xffc01f44   /* Memory DMA Stream 2 Source Start Address Register */
-#define                   MDMA_S2_CONFIG  0xffc01f48   /* Memory DMA Stream 2 Source Configuration Register */
-#define                  MDMA_S2_X_COUNT  0xffc01f50   /* Memory DMA Stream 2 Source X Count Register */
-#define                 MDMA_S2_X_MODIFY  0xffc01f54   /* Memory DMA Stream 2 Source X Modify Register */
-#define                  MDMA_S2_Y_COUNT  0xffc01f58   /* Memory DMA Stream 2 Source Y Count Register */
-#define                 MDMA_S2_Y_MODIFY  0xffc01f5c   /* Memory DMA Stream 2 Source Y Modify Register */
-#define            MDMA_S2_CURR_DESC_PTR  0xffc01f60   /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define                MDMA_S2_CURR_ADDR  0xffc01f64   /* Memory DMA Stream 2 Source Current Address Register */
-#define               MDMA_S2_IRQ_STATUS  0xffc01f68   /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define           MDMA_S2_PERIPHERAL_MAP  0xffc01f6c   /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define             MDMA_S2_CURR_X_COUNT  0xffc01f70   /* Memory DMA Stream 2 Source Current X Count Register */
-#define             MDMA_S2_CURR_Y_COUNT  0xffc01f78   /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define            MDMA_D3_NEXT_DESC_PTR  0xffc01f80   /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define               MDMA_D3_START_ADDR  0xffc01f84   /* Memory DMA Stream 3 Destination Start Address Register */
-#define                   MDMA_D3_CONFIG  0xffc01f88   /* Memory DMA Stream 3 Destination Configuration Register */
-#define                  MDMA_D3_X_COUNT  0xffc01f90   /* Memory DMA Stream 3 Destination X Count Register */
-#define                 MDMA_D3_X_MODIFY  0xffc01f94   /* Memory DMA Stream 3 Destination X Modify Register */
-#define                  MDMA_D3_Y_COUNT  0xffc01f98   /* Memory DMA Stream 3 Destination Y Count Register */
-#define                 MDMA_D3_Y_MODIFY  0xffc01f9c   /* Memory DMA Stream 3 Destination Y Modify Register */
-#define            MDMA_D3_CURR_DESC_PTR  0xffc01fa0   /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define                MDMA_D3_CURR_ADDR  0xffc01fa4   /* Memory DMA Stream 3 Destination Current Address Register */
-#define               MDMA_D3_IRQ_STATUS  0xffc01fa8   /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define           MDMA_D3_PERIPHERAL_MAP  0xffc01fac   /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define             MDMA_D3_CURR_X_COUNT  0xffc01fb0   /* Memory DMA Stream 3 Destination Current X Count Register */
-#define             MDMA_D3_CURR_Y_COUNT  0xffc01fb8   /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define            MDMA_S3_NEXT_DESC_PTR  0xffc01fc0   /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define               MDMA_S3_START_ADDR  0xffc01fc4   /* Memory DMA Stream 3 Source Start Address Register */
-#define                   MDMA_S3_CONFIG  0xffc01fc8   /* Memory DMA Stream 3 Source Configuration Register */
-#define                  MDMA_S3_X_COUNT  0xffc01fd0   /* Memory DMA Stream 3 Source X Count Register */
-#define                 MDMA_S3_X_MODIFY  0xffc01fd4   /* Memory DMA Stream 3 Source X Modify Register */
-#define                  MDMA_S3_Y_COUNT  0xffc01fd8   /* Memory DMA Stream 3 Source Y Count Register */
-#define                 MDMA_S3_Y_MODIFY  0xffc01fdc   /* Memory DMA Stream 3 Source Y Modify Register */
-#define            MDMA_S3_CURR_DESC_PTR  0xffc01fe0   /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define                MDMA_S3_CURR_ADDR  0xffc01fe4   /* Memory DMA Stream 3 Source Current Address Register */
-#define               MDMA_S3_IRQ_STATUS  0xffc01fe8   /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define           MDMA_S3_PERIPHERAL_MAP  0xffc01fec   /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define             MDMA_S3_CURR_X_COUNT  0xffc01ff0   /* Memory DMA Stream 3 Source Current X Count Register */
-#define             MDMA_S3_CURR_Y_COUNT  0xffc01ff8   /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define                        UART1_DLL  0xffc02000   /* Divisor Latch Low Byte */
-#define                        UART1_DLH  0xffc02004   /* Divisor Latch High Byte */
-#define                       UART1_GCTL  0xffc02008   /* Global Control Register */
-#define                        UART1_LCR  0xffc0200c   /* Line Control Register */
-#define                        UART1_MCR  0xffc02010   /* Modem Control Register */
-#define                        UART1_LSR  0xffc02014   /* Line Status Register */
-#define                        UART1_MSR  0xffc02018   /* Modem Status Register */
-#define                        UART1_SCR  0xffc0201c   /* Scratch Register */
-#define                    UART1_IER_SET  0xffc02020   /* Interrupt Enable Register Set */
-#define                  UART1_IER_CLEAR  0xffc02024   /* Interrupt Enable Register Clear */
-#define                        UART1_THR  0xffc02028   /* Transmit Hold Register */
-#define                        UART1_RBR  0xffc0202c   /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define                     SPI1_REGBASE  0xffc02300
-#define                         SPI1_CTL  0xffc02300   /* SPI1 Control Register */
-#define                         SPI1_FLG  0xffc02304   /* SPI1 Flag Register */
-#define                        SPI1_STAT  0xffc02308   /* SPI1 Status Register */
-#define                        SPI1_TDBR  0xffc0230c   /* SPI1 Transmit Data Buffer Register */
-#define                        SPI1_RDBR  0xffc02310   /* SPI1 Receive Data Buffer Register */
-#define                        SPI1_BAUD  0xffc02314   /* SPI1 Baud Rate Register */
-#define                      SPI1_SHADOW  0xffc02318   /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define                      SPORT2_TCR1  0xffc02500   /* SPORT2 Transmit Configuration 1 Register */
-#define                      SPORT2_TCR2  0xffc02504   /* SPORT2 Transmit Configuration 2 Register */
-#define                   SPORT2_TCLKDIV  0xffc02508   /* SPORT2 Transmit Serial Clock Divider Register */
-#define                    SPORT2_TFSDIV  0xffc0250c   /* SPORT2 Transmit Frame Sync Divider Register */
-#define                        SPORT2_TX  0xffc02510   /* SPORT2 Transmit Data Register */
-#define                        SPORT2_RX  0xffc02518   /* SPORT2 Receive Data Register */
-#define                      SPORT2_RCR1  0xffc02520   /* SPORT2 Receive Configuration 1 Register */
-#define                      SPORT2_RCR2  0xffc02524   /* SPORT2 Receive Configuration 2 Register */
-#define                   SPORT2_RCLKDIV  0xffc02528   /* SPORT2 Receive Serial Clock Divider Register */
-#define                    SPORT2_RFSDIV  0xffc0252c   /* SPORT2 Receive Frame Sync Divider Register */
-#define                      SPORT2_STAT  0xffc02530   /* SPORT2 Status Register */
-#define                      SPORT2_CHNL  0xffc02534   /* SPORT2 Current Channel Register */
-#define                     SPORT2_MCMC1  0xffc02538   /* SPORT2 Multi channel Configuration Register 1 */
-#define                     SPORT2_MCMC2  0xffc0253c   /* SPORT2 Multi channel Configuration Register 2 */
-#define                     SPORT2_MTCS0  0xffc02540   /* SPORT2 Multi channel Transmit Select Register 0 */
-#define                     SPORT2_MTCS1  0xffc02544   /* SPORT2 Multi channel Transmit Select Register 1 */
-#define                     SPORT2_MTCS2  0xffc02548   /* SPORT2 Multi channel Transmit Select Register 2 */
-#define                     SPORT2_MTCS3  0xffc0254c   /* SPORT2 Multi channel Transmit Select Register 3 */
-#define                     SPORT2_MRCS0  0xffc02550   /* SPORT2 Multi channel Receive Select Register 0 */
-#define                     SPORT2_MRCS1  0xffc02554   /* SPORT2 Multi channel Receive Select Register 1 */
-#define                     SPORT2_MRCS2  0xffc02558   /* SPORT2 Multi channel Receive Select Register 2 */
-#define                     SPORT2_MRCS3  0xffc0255c   /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define                      SPORT3_TCR1  0xffc02600   /* SPORT3 Transmit Configuration 1 Register */
-#define                      SPORT3_TCR2  0xffc02604   /* SPORT3 Transmit Configuration 2 Register */
-#define                   SPORT3_TCLKDIV  0xffc02608   /* SPORT3 Transmit Serial Clock Divider Register */
-#define                    SPORT3_TFSDIV  0xffc0260c   /* SPORT3 Transmit Frame Sync Divider Register */
-#define                        SPORT3_TX  0xffc02610   /* SPORT3 Transmit Data Register */
-#define                        SPORT3_RX  0xffc02618   /* SPORT3 Receive Data Register */
-#define                      SPORT3_RCR1  0xffc02620   /* SPORT3 Receive Configuration 1 Register */
-#define                      SPORT3_RCR2  0xffc02624   /* SPORT3 Receive Configuration 2 Register */
-#define                   SPORT3_RCLKDIV  0xffc02628   /* SPORT3 Receive Serial Clock Divider Register */
-#define                    SPORT3_RFSDIV  0xffc0262c   /* SPORT3 Receive Frame Sync Divider Register */
-#define                      SPORT3_STAT  0xffc02630   /* SPORT3 Status Register */
-#define                      SPORT3_CHNL  0xffc02634   /* SPORT3 Current Channel Register */
-#define                     SPORT3_MCMC1  0xffc02638   /* SPORT3 Multi channel Configuration Register 1 */
-#define                     SPORT3_MCMC2  0xffc0263c   /* SPORT3 Multi channel Configuration Register 2 */
-#define                     SPORT3_MTCS0  0xffc02640   /* SPORT3 Multi channel Transmit Select Register 0 */
-#define                     SPORT3_MTCS1  0xffc02644   /* SPORT3 Multi channel Transmit Select Register 1 */
-#define                     SPORT3_MTCS2  0xffc02648   /* SPORT3 Multi channel Transmit Select Register 2 */
-#define                     SPORT3_MTCS3  0xffc0264c   /* SPORT3 Multi channel Transmit Select Register 3 */
-#define                     SPORT3_MRCS0  0xffc02650   /* SPORT3 Multi channel Receive Select Register 0 */
-#define                     SPORT3_MRCS1  0xffc02654   /* SPORT3 Multi channel Receive Select Register 1 */
-#define                     SPORT3_MRCS2  0xffc02658   /* SPORT3 Multi channel Receive Select Register 2 */
-#define                     SPORT3_MRCS3  0xffc0265c   /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define                     EPPI2_STATUS  0xffc02900   /* EPPI2 Status Register */
-#define                     EPPI2_HCOUNT  0xffc02904   /* EPPI2 Horizontal Transfer Count Register */
-#define                     EPPI2_HDELAY  0xffc02908   /* EPPI2 Horizontal Delay Count Register */
-#define                     EPPI2_VCOUNT  0xffc0290c   /* EPPI2 Vertical Transfer Count Register */
-#define                     EPPI2_VDELAY  0xffc02910   /* EPPI2 Vertical Delay Count Register */
-#define                      EPPI2_FRAME  0xffc02914   /* EPPI2 Lines per Frame Register */
-#define                       EPPI2_LINE  0xffc02918   /* EPPI2 Samples per Line Register */
-#define                     EPPI2_CLKDIV  0xffc0291c   /* EPPI2 Clock Divide Register */
-#define                    EPPI2_CONTROL  0xffc02920   /* EPPI2 Control Register */
-#define                   EPPI2_FS1W_HBL  0xffc02924   /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI2_FS1P_AVPL  0xffc02928   /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define                   EPPI2_FS2W_LVB  0xffc0292c   /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define                  EPPI2_FS2P_LAVF  0xffc02930   /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define                       EPPI2_CLIP  0xffc02934   /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define                         CAN0_MC1  0xffc02a00   /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define                         CAN0_MD1  0xffc02a04   /* CAN Controller 0 Mailbox Direction Register 1 */
-#define                        CAN0_TRS1  0xffc02a08   /* CAN Controller 0 Transmit Request Set Register 1 */
-#define                        CAN0_TRR1  0xffc02a0c   /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define                         CAN0_TA1  0xffc02a10   /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define                         CAN0_AA1  0xffc02a14   /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define                        CAN0_RMP1  0xffc02a18   /* CAN Controller 0 Receive Message Pending Register 1 */
-#define                        CAN0_RML1  0xffc02a1c   /* CAN Controller 0 Receive Message Lost Register 1 */
-#define                      CAN0_MBTIF1  0xffc02a20   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN0_MBRIF1  0xffc02a24   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN0_MBIM1  0xffc02a28   /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define                        CAN0_RFH1  0xffc02a2c   /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define                       CAN0_OPSS1  0xffc02a30   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define                         CAN0_MC2  0xffc02a40   /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define                         CAN0_MD2  0xffc02a44   /* CAN Controller 0 Mailbox Direction Register 2 */
-#define                        CAN0_TRS2  0xffc02a48   /* CAN Controller 0 Transmit Request Set Register 2 */
-#define                        CAN0_TRR2  0xffc02a4c   /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define                         CAN0_TA2  0xffc02a50   /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define                         CAN0_AA2  0xffc02a54   /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define                        CAN0_RMP2  0xffc02a58   /* CAN Controller 0 Receive Message Pending Register 2 */
-#define                        CAN0_RML2  0xffc02a5c   /* CAN Controller 0 Receive Message Lost Register 2 */
-#define                      CAN0_MBTIF2  0xffc02a60   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN0_MBRIF2  0xffc02a64   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN0_MBIM2  0xffc02a68   /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define                        CAN0_RFH2  0xffc02a6c   /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define                       CAN0_OPSS2  0xffc02a70   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define                       CAN0_CLOCK  0xffc02a80   /* CAN Controller 0 Clock Register */
-#define                      CAN0_TIMING  0xffc02a84   /* CAN Controller 0 Timing Register */
-#define                       CAN0_DEBUG  0xffc02a88   /* CAN Controller 0 Debug Register */
-#define                      CAN0_STATUS  0xffc02a8c   /* CAN Controller 0 Global Status Register */
-#define                         CAN0_CEC  0xffc02a90   /* CAN Controller 0 Error Counter Register */
-#define                         CAN0_GIS  0xffc02a94   /* CAN Controller 0 Global Interrupt Status Register */
-#define                         CAN0_GIM  0xffc02a98   /* CAN Controller 0 Global Interrupt Mask Register */
-#define                         CAN0_GIF  0xffc02a9c   /* CAN Controller 0 Global Interrupt Flag Register */
-#define                     CAN0_CONTROL  0xffc02aa0   /* CAN Controller 0 Master Control Register */
-#define                        CAN0_INTR  0xffc02aa4   /* CAN Controller 0 Interrupt Pending Register */
-#define                        CAN0_MBTD  0xffc02aac   /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define                         CAN0_EWR  0xffc02ab0   /* CAN Controller 0 Programmable Warning Level Register */
-#define                         CAN0_ESR  0xffc02ab4   /* CAN Controller 0 Error Status Register */
-#define                       CAN0_UCCNT  0xffc02ac4   /* CAN Controller 0 Universal Counter Register */
-#define                        CAN0_UCRC  0xffc02ac8   /* CAN Controller 0 Universal Counter Force Reload Register */
-#define                       CAN0_UCCNF  0xffc02acc   /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       CAN0_AM00L  0xffc02b00   /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN0_AM00H  0xffc02b04   /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN0_AM01L  0xffc02b08   /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN0_AM01H  0xffc02b0c   /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN0_AM02L  0xffc02b10   /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN0_AM02H  0xffc02b14   /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN0_AM03L  0xffc02b18   /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN0_AM03H  0xffc02b1c   /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN0_AM04L  0xffc02b20   /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN0_AM04H  0xffc02b24   /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN0_AM05L  0xffc02b28   /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN0_AM05H  0xffc02b2c   /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN0_AM06L  0xffc02b30   /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN0_AM06H  0xffc02b34   /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN0_AM07L  0xffc02b38   /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN0_AM07H  0xffc02b3c   /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN0_AM08L  0xffc02b40   /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN0_AM08H  0xffc02b44   /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN0_AM09L  0xffc02b48   /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN0_AM09H  0xffc02b4c   /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN0_AM10L  0xffc02b50   /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN0_AM10H  0xffc02b54   /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN0_AM11L  0xffc02b58   /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN0_AM11H  0xffc02b5c   /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN0_AM12L  0xffc02b60   /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN0_AM12H  0xffc02b64   /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN0_AM13L  0xffc02b68   /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN0_AM13H  0xffc02b6c   /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN0_AM14L  0xffc02b70   /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN0_AM14H  0xffc02b74   /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN0_AM15L  0xffc02b78   /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN0_AM15H  0xffc02b7c   /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       CAN0_AM16L  0xffc02b80   /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN0_AM16H  0xffc02b84   /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN0_AM17L  0xffc02b88   /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN0_AM17H  0xffc02b8c   /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN0_AM18L  0xffc02b90   /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN0_AM18H  0xffc02b94   /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN0_AM19L  0xffc02b98   /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN0_AM19H  0xffc02b9c   /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN0_AM20L  0xffc02ba0   /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN0_AM20H  0xffc02ba4   /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN0_AM21L  0xffc02ba8   /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN0_AM21H  0xffc02bac   /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN0_AM22L  0xffc02bb0   /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN0_AM22H  0xffc02bb4   /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN0_AM23L  0xffc02bb8   /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN0_AM23H  0xffc02bbc   /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN0_AM24L  0xffc02bc0   /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN0_AM24H  0xffc02bc4   /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN0_AM25L  0xffc02bc8   /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN0_AM25H  0xffc02bcc   /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN0_AM26L  0xffc02bd0   /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN0_AM26H  0xffc02bd4   /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN0_AM27L  0xffc02bd8   /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN0_AM27H  0xffc02bdc   /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN0_AM28L  0xffc02be0   /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN0_AM28H  0xffc02be4   /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN0_AM29L  0xffc02be8   /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN0_AM29H  0xffc02bec   /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN0_AM30L  0xffc02bf0   /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN0_AM30H  0xffc02bf4   /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN0_AM31L  0xffc02bf8   /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN0_AM31H  0xffc02bfc   /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  CAN0_MB00_DATA0  0xffc02c00   /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define                  CAN0_MB00_DATA1  0xffc02c04   /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define                  CAN0_MB00_DATA2  0xffc02c08   /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define                  CAN0_MB00_DATA3  0xffc02c0c   /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define                 CAN0_MB00_LENGTH  0xffc02c10   /* CAN Controller 0 Mailbox 0 Length Register */
-#define              CAN0_MB00_TIMESTAMP  0xffc02c14   /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define                    CAN0_MB00_ID0  0xffc02c18   /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define                    CAN0_MB00_ID1  0xffc02c1c   /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define                  CAN0_MB01_DATA0  0xffc02c20   /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define                  CAN0_MB01_DATA1  0xffc02c24   /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define                  CAN0_MB01_DATA2  0xffc02c28   /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define                  CAN0_MB01_DATA3  0xffc02c2c   /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define                 CAN0_MB01_LENGTH  0xffc02c30   /* CAN Controller 0 Mailbox 1 Length Register */
-#define              CAN0_MB01_TIMESTAMP  0xffc02c34   /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define                    CAN0_MB01_ID0  0xffc02c38   /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define                    CAN0_MB01_ID1  0xffc02c3c   /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define                  CAN0_MB02_DATA0  0xffc02c40   /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define                  CAN0_MB02_DATA1  0xffc02c44   /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define                  CAN0_MB02_DATA2  0xffc02c48   /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define                  CAN0_MB02_DATA3  0xffc02c4c   /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define                 CAN0_MB02_LENGTH  0xffc02c50   /* CAN Controller 0 Mailbox 2 Length Register */
-#define              CAN0_MB02_TIMESTAMP  0xffc02c54   /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define                    CAN0_MB02_ID0  0xffc02c58   /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define                    CAN0_MB02_ID1  0xffc02c5c   /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define                  CAN0_MB03_DATA0  0xffc02c60   /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define                  CAN0_MB03_DATA1  0xffc02c64   /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define                  CAN0_MB03_DATA2  0xffc02c68   /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define                  CAN0_MB03_DATA3  0xffc02c6c   /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define                 CAN0_MB03_LENGTH  0xffc02c70   /* CAN Controller 0 Mailbox 3 Length Register */
-#define              CAN0_MB03_TIMESTAMP  0xffc02c74   /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define                    CAN0_MB03_ID0  0xffc02c78   /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define                    CAN0_MB03_ID1  0xffc02c7c   /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define                  CAN0_MB04_DATA0  0xffc02c80   /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define                  CAN0_MB04_DATA1  0xffc02c84   /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define                  CAN0_MB04_DATA2  0xffc02c88   /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define                  CAN0_MB04_DATA3  0xffc02c8c   /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define                 CAN0_MB04_LENGTH  0xffc02c90   /* CAN Controller 0 Mailbox 4 Length Register */
-#define              CAN0_MB04_TIMESTAMP  0xffc02c94   /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define                    CAN0_MB04_ID0  0xffc02c98   /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define                    CAN0_MB04_ID1  0xffc02c9c   /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define                  CAN0_MB05_DATA0  0xffc02ca0   /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define                  CAN0_MB05_DATA1  0xffc02ca4   /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define                  CAN0_MB05_DATA2  0xffc02ca8   /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define                  CAN0_MB05_DATA3  0xffc02cac   /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define                 CAN0_MB05_LENGTH  0xffc02cb0   /* CAN Controller 0 Mailbox 5 Length Register */
-#define              CAN0_MB05_TIMESTAMP  0xffc02cb4   /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define                    CAN0_MB05_ID0  0xffc02cb8   /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define                    CAN0_MB05_ID1  0xffc02cbc   /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define                  CAN0_MB06_DATA0  0xffc02cc0   /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define                  CAN0_MB06_DATA1  0xffc02cc4   /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define                  CAN0_MB06_DATA2  0xffc02cc8   /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define                  CAN0_MB06_DATA3  0xffc02ccc   /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define                 CAN0_MB06_LENGTH  0xffc02cd0   /* CAN Controller 0 Mailbox 6 Length Register */
-#define              CAN0_MB06_TIMESTAMP  0xffc02cd4   /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define                    CAN0_MB06_ID0  0xffc02cd8   /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define                    CAN0_MB06_ID1  0xffc02cdc   /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define                  CAN0_MB07_DATA0  0xffc02ce0   /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define                  CAN0_MB07_DATA1  0xffc02ce4   /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define                  CAN0_MB07_DATA2  0xffc02ce8   /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define                  CAN0_MB07_DATA3  0xffc02cec   /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define                 CAN0_MB07_LENGTH  0xffc02cf0   /* CAN Controller 0 Mailbox 7 Length Register */
-#define              CAN0_MB07_TIMESTAMP  0xffc02cf4   /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define                    CAN0_MB07_ID0  0xffc02cf8   /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define                    CAN0_MB07_ID1  0xffc02cfc   /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define                  CAN0_MB08_DATA0  0xffc02d00   /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define                  CAN0_MB08_DATA1  0xffc02d04   /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define                  CAN0_MB08_DATA2  0xffc02d08   /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define                  CAN0_MB08_DATA3  0xffc02d0c   /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define                 CAN0_MB08_LENGTH  0xffc02d10   /* CAN Controller 0 Mailbox 8 Length Register */
-#define              CAN0_MB08_TIMESTAMP  0xffc02d14   /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define                    CAN0_MB08_ID0  0xffc02d18   /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define                    CAN0_MB08_ID1  0xffc02d1c   /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define                  CAN0_MB09_DATA0  0xffc02d20   /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define                  CAN0_MB09_DATA1  0xffc02d24   /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define                  CAN0_MB09_DATA2  0xffc02d28   /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define                  CAN0_MB09_DATA3  0xffc02d2c   /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define                 CAN0_MB09_LENGTH  0xffc02d30   /* CAN Controller 0 Mailbox 9 Length Register */
-#define              CAN0_MB09_TIMESTAMP  0xffc02d34   /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define                    CAN0_MB09_ID0  0xffc02d38   /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define                    CAN0_MB09_ID1  0xffc02d3c   /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define                  CAN0_MB10_DATA0  0xffc02d40   /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define                  CAN0_MB10_DATA1  0xffc02d44   /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define                  CAN0_MB10_DATA2  0xffc02d48   /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define                  CAN0_MB10_DATA3  0xffc02d4c   /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define                 CAN0_MB10_LENGTH  0xffc02d50   /* CAN Controller 0 Mailbox 10 Length Register */
-#define              CAN0_MB10_TIMESTAMP  0xffc02d54   /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define                    CAN0_MB10_ID0  0xffc02d58   /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define                    CAN0_MB10_ID1  0xffc02d5c   /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define                  CAN0_MB11_DATA0  0xffc02d60   /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define                  CAN0_MB11_DATA1  0xffc02d64   /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define                  CAN0_MB11_DATA2  0xffc02d68   /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define                  CAN0_MB11_DATA3  0xffc02d6c   /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define                 CAN0_MB11_LENGTH  0xffc02d70   /* CAN Controller 0 Mailbox 11 Length Register */
-#define              CAN0_MB11_TIMESTAMP  0xffc02d74   /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define                    CAN0_MB11_ID0  0xffc02d78   /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define                    CAN0_MB11_ID1  0xffc02d7c   /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define                  CAN0_MB12_DATA0  0xffc02d80   /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define                  CAN0_MB12_DATA1  0xffc02d84   /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define                  CAN0_MB12_DATA2  0xffc02d88   /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define                  CAN0_MB12_DATA3  0xffc02d8c   /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define                 CAN0_MB12_LENGTH  0xffc02d90   /* CAN Controller 0 Mailbox 12 Length Register */
-#define              CAN0_MB12_TIMESTAMP  0xffc02d94   /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define                    CAN0_MB12_ID0  0xffc02d98   /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define                    CAN0_MB12_ID1  0xffc02d9c   /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define                  CAN0_MB13_DATA0  0xffc02da0   /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define                  CAN0_MB13_DATA1  0xffc02da4   /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define                  CAN0_MB13_DATA2  0xffc02da8   /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define                  CAN0_MB13_DATA3  0xffc02dac   /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define                 CAN0_MB13_LENGTH  0xffc02db0   /* CAN Controller 0 Mailbox 13 Length Register */
-#define              CAN0_MB13_TIMESTAMP  0xffc02db4   /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define                    CAN0_MB13_ID0  0xffc02db8   /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define                    CAN0_MB13_ID1  0xffc02dbc   /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define                  CAN0_MB14_DATA0  0xffc02dc0   /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define                  CAN0_MB14_DATA1  0xffc02dc4   /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define                  CAN0_MB14_DATA2  0xffc02dc8   /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define                  CAN0_MB14_DATA3  0xffc02dcc   /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define                 CAN0_MB14_LENGTH  0xffc02dd0   /* CAN Controller 0 Mailbox 14 Length Register */
-#define              CAN0_MB14_TIMESTAMP  0xffc02dd4   /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define                    CAN0_MB14_ID0  0xffc02dd8   /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define                    CAN0_MB14_ID1  0xffc02ddc   /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define                  CAN0_MB15_DATA0  0xffc02de0   /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define                  CAN0_MB15_DATA1  0xffc02de4   /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define                  CAN0_MB15_DATA2  0xffc02de8   /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define                  CAN0_MB15_DATA3  0xffc02dec   /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define                 CAN0_MB15_LENGTH  0xffc02df0   /* CAN Controller 0 Mailbox 15 Length Register */
-#define              CAN0_MB15_TIMESTAMP  0xffc02df4   /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define                    CAN0_MB15_ID0  0xffc02df8   /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define                    CAN0_MB15_ID1  0xffc02dfc   /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  CAN0_MB16_DATA0  0xffc02e00   /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define                  CAN0_MB16_DATA1  0xffc02e04   /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define                  CAN0_MB16_DATA2  0xffc02e08   /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define                  CAN0_MB16_DATA3  0xffc02e0c   /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define                 CAN0_MB16_LENGTH  0xffc02e10   /* CAN Controller 0 Mailbox 16 Length Register */
-#define              CAN0_MB16_TIMESTAMP  0xffc02e14   /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define                    CAN0_MB16_ID0  0xffc02e18   /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define                    CAN0_MB16_ID1  0xffc02e1c   /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define                  CAN0_MB17_DATA0  0xffc02e20   /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define                  CAN0_MB17_DATA1  0xffc02e24   /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define                  CAN0_MB17_DATA2  0xffc02e28   /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define                  CAN0_MB17_DATA3  0xffc02e2c   /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define                 CAN0_MB17_LENGTH  0xffc02e30   /* CAN Controller 0 Mailbox 17 Length Register */
-#define              CAN0_MB17_TIMESTAMP  0xffc02e34   /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define                    CAN0_MB17_ID0  0xffc02e38   /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define                    CAN0_MB17_ID1  0xffc02e3c   /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define                  CAN0_MB18_DATA0  0xffc02e40   /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define                  CAN0_MB18_DATA1  0xffc02e44   /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define                  CAN0_MB18_DATA2  0xffc02e48   /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define                  CAN0_MB18_DATA3  0xffc02e4c   /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define                 CAN0_MB18_LENGTH  0xffc02e50   /* CAN Controller 0 Mailbox 18 Length Register */
-#define              CAN0_MB18_TIMESTAMP  0xffc02e54   /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define                    CAN0_MB18_ID0  0xffc02e58   /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define                    CAN0_MB18_ID1  0xffc02e5c   /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define                  CAN0_MB19_DATA0  0xffc02e60   /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define                  CAN0_MB19_DATA1  0xffc02e64   /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define                  CAN0_MB19_DATA2  0xffc02e68   /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define                  CAN0_MB19_DATA3  0xffc02e6c   /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define                 CAN0_MB19_LENGTH  0xffc02e70   /* CAN Controller 0 Mailbox 19 Length Register */
-#define              CAN0_MB19_TIMESTAMP  0xffc02e74   /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define                    CAN0_MB19_ID0  0xffc02e78   /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define                    CAN0_MB19_ID1  0xffc02e7c   /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define                  CAN0_MB20_DATA0  0xffc02e80   /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define                  CAN0_MB20_DATA1  0xffc02e84   /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define                  CAN0_MB20_DATA2  0xffc02e88   /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define                  CAN0_MB20_DATA3  0xffc02e8c   /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define                 CAN0_MB20_LENGTH  0xffc02e90   /* CAN Controller 0 Mailbox 20 Length Register */
-#define              CAN0_MB20_TIMESTAMP  0xffc02e94   /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define                    CAN0_MB20_ID0  0xffc02e98   /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define                    CAN0_MB20_ID1  0xffc02e9c   /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define                  CAN0_MB21_DATA0  0xffc02ea0   /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define                  CAN0_MB21_DATA1  0xffc02ea4   /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define                  CAN0_MB21_DATA2  0xffc02ea8   /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define                  CAN0_MB21_DATA3  0xffc02eac   /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define                 CAN0_MB21_LENGTH  0xffc02eb0   /* CAN Controller 0 Mailbox 21 Length Register */
-#define              CAN0_MB21_TIMESTAMP  0xffc02eb4   /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define                    CAN0_MB21_ID0  0xffc02eb8   /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define                    CAN0_MB21_ID1  0xffc02ebc   /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define                  CAN0_MB22_DATA0  0xffc02ec0   /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define                  CAN0_MB22_DATA1  0xffc02ec4   /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define                  CAN0_MB22_DATA2  0xffc02ec8   /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define                  CAN0_MB22_DATA3  0xffc02ecc   /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define                 CAN0_MB22_LENGTH  0xffc02ed0   /* CAN Controller 0 Mailbox 22 Length Register */
-#define              CAN0_MB22_TIMESTAMP  0xffc02ed4   /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define                    CAN0_MB22_ID0  0xffc02ed8   /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define                    CAN0_MB22_ID1  0xffc02edc   /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define                  CAN0_MB23_DATA0  0xffc02ee0   /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define                  CAN0_MB23_DATA1  0xffc02ee4   /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define                  CAN0_MB23_DATA2  0xffc02ee8   /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define                  CAN0_MB23_DATA3  0xffc02eec   /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define                 CAN0_MB23_LENGTH  0xffc02ef0   /* CAN Controller 0 Mailbox 23 Length Register */
-#define              CAN0_MB23_TIMESTAMP  0xffc02ef4   /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define                    CAN0_MB23_ID0  0xffc02ef8   /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define                    CAN0_MB23_ID1  0xffc02efc   /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define                  CAN0_MB24_DATA0  0xffc02f00   /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define                  CAN0_MB24_DATA1  0xffc02f04   /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define                  CAN0_MB24_DATA2  0xffc02f08   /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define                  CAN0_MB24_DATA3  0xffc02f0c   /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define                 CAN0_MB24_LENGTH  0xffc02f10   /* CAN Controller 0 Mailbox 24 Length Register */
-#define              CAN0_MB24_TIMESTAMP  0xffc02f14   /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define                    CAN0_MB24_ID0  0xffc02f18   /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define                    CAN0_MB24_ID1  0xffc02f1c   /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define                  CAN0_MB25_DATA0  0xffc02f20   /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define                  CAN0_MB25_DATA1  0xffc02f24   /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define                  CAN0_MB25_DATA2  0xffc02f28   /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define                  CAN0_MB25_DATA3  0xffc02f2c   /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define                 CAN0_MB25_LENGTH  0xffc02f30   /* CAN Controller 0 Mailbox 25 Length Register */
-#define              CAN0_MB25_TIMESTAMP  0xffc02f34   /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define                    CAN0_MB25_ID0  0xffc02f38   /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define                    CAN0_MB25_ID1  0xffc02f3c   /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define                  CAN0_MB26_DATA0  0xffc02f40   /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define                  CAN0_MB26_DATA1  0xffc02f44   /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define                  CAN0_MB26_DATA2  0xffc02f48   /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define                  CAN0_MB26_DATA3  0xffc02f4c   /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define                 CAN0_MB26_LENGTH  0xffc02f50   /* CAN Controller 0 Mailbox 26 Length Register */
-#define              CAN0_MB26_TIMESTAMP  0xffc02f54   /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define                    CAN0_MB26_ID0  0xffc02f58   /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define                    CAN0_MB26_ID1  0xffc02f5c   /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define                  CAN0_MB27_DATA0  0xffc02f60   /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define                  CAN0_MB27_DATA1  0xffc02f64   /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define                  CAN0_MB27_DATA2  0xffc02f68   /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define                  CAN0_MB27_DATA3  0xffc02f6c   /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define                 CAN0_MB27_LENGTH  0xffc02f70   /* CAN Controller 0 Mailbox 27 Length Register */
-#define              CAN0_MB27_TIMESTAMP  0xffc02f74   /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define                    CAN0_MB27_ID0  0xffc02f78   /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define                    CAN0_MB27_ID1  0xffc02f7c   /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define                  CAN0_MB28_DATA0  0xffc02f80   /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define                  CAN0_MB28_DATA1  0xffc02f84   /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define                  CAN0_MB28_DATA2  0xffc02f88   /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define                  CAN0_MB28_DATA3  0xffc02f8c   /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define                 CAN0_MB28_LENGTH  0xffc02f90   /* CAN Controller 0 Mailbox 28 Length Register */
-#define              CAN0_MB28_TIMESTAMP  0xffc02f94   /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define                    CAN0_MB28_ID0  0xffc02f98   /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define                    CAN0_MB28_ID1  0xffc02f9c   /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define                  CAN0_MB29_DATA0  0xffc02fa0   /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define                  CAN0_MB29_DATA1  0xffc02fa4   /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define                  CAN0_MB29_DATA2  0xffc02fa8   /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define                  CAN0_MB29_DATA3  0xffc02fac   /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define                 CAN0_MB29_LENGTH  0xffc02fb0   /* CAN Controller 0 Mailbox 29 Length Register */
-#define              CAN0_MB29_TIMESTAMP  0xffc02fb4   /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define                    CAN0_MB29_ID0  0xffc02fb8   /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define                    CAN0_MB29_ID1  0xffc02fbc   /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define                  CAN0_MB30_DATA0  0xffc02fc0   /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define                  CAN0_MB30_DATA1  0xffc02fc4   /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define                  CAN0_MB30_DATA2  0xffc02fc8   /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define                  CAN0_MB30_DATA3  0xffc02fcc   /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define                 CAN0_MB30_LENGTH  0xffc02fd0   /* CAN Controller 0 Mailbox 30 Length Register */
-#define              CAN0_MB30_TIMESTAMP  0xffc02fd4   /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define                    CAN0_MB30_ID0  0xffc02fd8   /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define                    CAN0_MB30_ID1  0xffc02fdc   /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define                  CAN0_MB31_DATA0  0xffc02fe0   /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define                  CAN0_MB31_DATA1  0xffc02fe4   /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define                  CAN0_MB31_DATA2  0xffc02fe8   /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define                  CAN0_MB31_DATA3  0xffc02fec   /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define                 CAN0_MB31_LENGTH  0xffc02ff0   /* CAN Controller 0 Mailbox 31 Length Register */
-#define              CAN0_MB31_TIMESTAMP  0xffc02ff4   /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define                    CAN0_MB31_ID0  0xffc02ff8   /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define                    CAN0_MB31_ID1  0xffc02ffc   /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
-#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
-#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
-#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
-#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
-#define                        UART3_LSR  0xffc03114   /* Line Status Register */
-#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
-#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
-#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
-#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
-#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
-#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03b00   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03b04   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03b08   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc03b0c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03b10   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03b14   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03b18   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc03b1c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03b20   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03b24   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03b28   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc03b2c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03b40   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03b44   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03b48   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc03b4c   /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc04200   /* Configuration Register */
-#define                        CNT_IMASK  0xffc04204   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc04208   /* Status Register */
-#define                      CNT_COMMAND  0xffc0420c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc04210   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc04214   /* Counter Register */
-#define                          CNT_MAX  0xffc04218   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0421c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc04300   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc04304   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc04308   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0430c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc04320   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc04324   /* Secure Control */
-#define                    SECURE_STATUS  0xffc04328   /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define                    DMAC1_PERIMUX  0xffc04340   /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc04380   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc04384   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc04388   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0438c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
-#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
-
-/* Bit masks for SIC_IAR0 */
-
-#define            PLL_WAKEUP  0x1        /* PLL Wakeup */
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define              DMA0_ERR  0x2        /* DMA Controller 0 Error */
-#define             EPPI0_ERR  0x4        /* EPPI0 Error */
-#define            SPORT0_ERR  0x8        /* SPORT0 Error */
-#define            SPORT1_ERR  0x10       /* SPORT1 Error */
-#define              SPI0_ERR  0x20       /* SPI0 Error */
-#define             UART0_ERR  0x40       /* UART0 Error */
-#define                   RTC  0x80       /* Real-Time Clock */
-#define                 DMA12  0x100      /* DMA Channel 12 */
-#define                  DMA0  0x200      /* DMA Channel 0 */
-#define                  DMA1  0x400      /* DMA Channel 1 */
-#define                  DMA2  0x800      /* DMA Channel 2 */
-#define                  DMA3  0x1000     /* DMA Channel 3 */
-#define                  DMA4  0x2000     /* DMA Channel 4 */
-#define                  DMA6  0x4000     /* DMA Channel 6 */
-#define                  DMA7  0x8000     /* DMA Channel 7 */
-#define                 PINT0  0x80000    /* Pin Interrupt 0 */
-#define                 PINT1  0x100000   /* Pin Interrupt 1 */
-#define                 MDMA0  0x200000   /* Memory DMA Stream 0 */
-#define                 MDMA1  0x400000   /* Memory DMA Stream 1 */
-#define                  WDOG  0x800000   /* Watchdog Timer */
-#define              DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
-#define            SPORT2_ERR  0x2000000  /* SPORT2 Error */
-#define            SPORT3_ERR  0x4000000  /* SPORT3 Error */
-#define               MXVR_SD  0x8000000  /* MXVR Synchronous Data */
-#define              SPI1_ERR  0x10000000 /* SPI1 Error */
-#define              SPI2_ERR  0x20000000 /* SPI2 Error */
-#define             UART1_ERR  0x40000000 /* UART1 Error */
-#define             UART2_ERR  0x80000000 /* UART2 Error */
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define              CAN0_ERR  0x1        /* CAN0 Error */
-#define                 DMA18  0x2        /* DMA Channel 18 */
-#define                 DMA19  0x4        /* DMA Channel 19 */
-#define                 DMA20  0x8        /* DMA Channel 20 */
-#define                 DMA21  0x10       /* DMA Channel 21 */
-#define                 DMA13  0x20       /* DMA Channel 13 */
-#define                 DMA14  0x40       /* DMA Channel 14 */
-#define                  DMA5  0x80       /* DMA Channel 5 */
-#define                 DMA23  0x100      /* DMA Channel 23 */
-#define                  DMA8  0x200      /* DMA Channel 8 */
-#define                  DMA9  0x400      /* DMA Channel 9 */
-#define                 DMA10  0x800      /* DMA Channel 10 */
-#define                 DMA11  0x1000     /* DMA Channel 11 */
-#define                  TWI0  0x2000     /* TWI0 */
-#define                  TWI1  0x4000     /* TWI1 */
-#define               CAN0_RX  0x8000     /* CAN0 Receive */
-#define               CAN0_TX  0x10000    /* CAN0 Transmit */
-#define                 MDMA2  0x20000    /* Memory DMA Stream 0 */
-#define                 MDMA3  0x40000    /* Memory DMA Stream 1 */
-#define             MXVR_STAT  0x80000    /* MXVR Status */
-#define               MXVR_CM  0x100000   /* MXVR Control Message */
-#define               MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
-#define             EPPI1_ERR  0x400000   /* EPPI1 Error */
-#define             EPPI2_ERR  0x800000   /* EPPI2 Error */
-#define             UART3_ERR  0x1000000  /* UART3 Error */
-#define              HOST_ERR  0x2000000  /* Host DMA Port Error */
-#define               USB_ERR  0x4000000  /* USB Error */
-#define              PIXC_ERR  0x8000000  /* Pixel Compositor Error */
-#define               NFC_ERR  0x10000000 /* Nand Flash Controller Error */
-#define             ATAPI_ERR  0x20000000 /* ATAPI Error */
-#define              CAN1_ERR  0x40000000 /* CAN1 Error */
-#define             DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
-#define             DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
-#define                 DMAR0  0x80000000 /* DMAR0 Block */
-#define                 DMAR1  0x80000000 /* DMAR1 Block */
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define                 DMA15  0x1        /* DMA Channel 15 */
-#define                 DMA16  0x2        /* DMA Channel 16 */
-#define                 DMA17  0x4        /* DMA Channel 17 */
-#define                 DMA22  0x8        /* DMA Channel 22 */
-#define                   CNT  0x10       /* Counter */
-#define                   KEY  0x20       /* Keypad */
-#define               CAN1_RX  0x40       /* CAN1 Receive */
-#define               CAN1_TX  0x80       /* CAN1 Transmit */
-#define             SDH_INT_MASK0  0x100      /* SDH Mask 0 */
-#define             SDH_INT_MASK1  0x200      /* SDH Mask 1 */
-#define              USB_EINT  0x400      /* USB Exception */
-#define              USB_INT0  0x800      /* USB Interrupt 0 */
-#define              USB_INT1  0x1000     /* USB Interrupt 1 */
-#define              USB_INT2  0x2000     /* USB Interrupt 2 */
-#define            USB_DMAINT  0x4000     /* USB DMA */
-#define                OTPSEC  0x8000     /* OTP Access Complete */
-#define                TIMER0  0x400000   /* Timer 0 */
-#define                TIMER1  0x800000   /* Timer 1 */
-#define                TIMER2  0x1000000  /* Timer 2 */
-#define                TIMER3  0x2000000  /* Timer 3 */
-#define                TIMER4  0x4000000  /* Timer 4 */
-#define                TIMER5  0x8000000  /* Timer 5 */
-#define                TIMER6  0x10000000 /* Timer 6 */
-#define                TIMER7  0x20000000 /* Timer 7 */
-#define                 PINT2  0x40000000 /* Pin Interrupt 2 */
-#define                 PINT3  0x80000000 /* Pin Interrupt 3 */
-
-/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
-
-#define                     DMAEN  0x1        /* DMA Channel Enable */
-#define                       WNR  0x2        /* DMA Direction */
-#define                  WDSIZE_8  0x0        /* Transfer Word Size = 8 */
-#define                 WDSIZE_16  0x4        /* Transfer Word Size = 16 */
-#define                 WDSIZE_32  0x8        /* Transfer Word Size = 32 */
-#define                     DMA2D  0x10       /* DMA Mode */
-#define                   RESTART  0x20       /* Work Unit Transitions */
-#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
-#define                     DI_EN  0x80       /* Data Interrupt Enable */
-
-#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
-#define                  NDSIZE_0 0x0000      /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define                  NDSIZE_1 0x0100      /* Next Descriptor Size = 1 */
-#define                  NDSIZE_2 0x0200      /* Next Descriptor Size = 2 */
-#define                  NDSIZE_3 0x0300      /* Next Descriptor Size = 3 */
-#define                  NDSIZE_4 0x0400      /* Next Descriptor Size = 4 */
-#define                  NDSIZE_5 0x0500      /* Next Descriptor Size = 5 */
-#define                  NDSIZE_6 0x0600      /* Next Descriptor Size = 6 */
-#define                  NDSIZE_7 0x0700      /* Next Descriptor Size = 7 */
-#define                  NDSIZE_8 0x0800      /* Next Descriptor Size = 8 */
-#define                  NDSIZE_9 0x0900      /* Next Descriptor Size = 9 */
-
-#define                   DMAFLOW  0xf000     /* Next Operation */
-#define              DMAFLOW_STOP  0x0000     /* Stop Mode */
-#define              DMAFLOW_AUTO  0x1000     /* Autobuffer Mode */
-#define             DMAFLOW_ARRAY  0x4000     /* Descriptor Array Mode */
-#define             DMAFLOW_SMALL  0x6000     /* Small Model Descriptor List Mode */
-#define             DMAFLOW_LARGE  0x7000     /* Large Model Descriptor List Mode */
-
-/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
-#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
-#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
-#define                   DMA_RUN  0x8        /* DMA Channel Running */
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                     CTYPE  0x40       /* DMA Channel Type */
-#define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TCPER */
-
-#define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
-#define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
-#define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
-#define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TCCNT */
-
-#define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
-#define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
-#define         DAB_TRAFFIC_COUNT  0x700      /* DAB Traffic Control Count */
-#define    MDMA_ROUND_ROBIN_COUNT  0xf800     /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define                   PMUXSDH  0x1        /* Peripheral Select for DMA22 channel */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define                   B0RDYEN  0x1        /* Bank 0 ARDY Enable */
-#define                  B0RDYPOL  0x2        /* Bank 0 ARDY Polarity */
-#define                      B0TT  0xc        /* Bank 0 transition time */
-#define                      B0ST  0x30       /* Bank 0 Setup time */
-#define                      B0HT  0xc0       /* Bank 0 Hold time */
-#define                     B0RAT  0xf00      /* Bank 0 Read access time */
-#define                     B0WAT  0xf000     /* Bank 0 write access time */
-#define                   B1RDYEN  0x10000    /* Bank 1 ARDY Enable */
-#define                  B1RDYPOL  0x20000    /* Bank 1 ARDY Polarity */
-#define                      B1TT  0xc0000    /* Bank 1 transition time */
-#define                      B1ST  0x300000   /* Bank 1 Setup time */
-#define                      B1HT  0xc00000   /* Bank 1 Hold time */
-#define                     B1RAT  0xf000000  /* Bank 1 Read access time */
-#define                     B1WAT  0xf0000000 /* Bank 1 write access time */
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define                   B2RDYEN  0x1        /* Bank 2 ARDY Enable */
-#define                  B2RDYPOL  0x2        /* Bank 2 ARDY Polarity */
-#define                      B2TT  0xc        /* Bank 2 transition time */
-#define                      B2ST  0x30       /* Bank 2 Setup time */
-#define                      B2HT  0xc0       /* Bank 2 Hold time */
-#define                     B2RAT  0xf00      /* Bank 2 Read access time */
-#define                     B2WAT  0xf000     /* Bank 2 write access time */
-#define                   B3RDYEN  0x10000    /* Bank 3 ARDY Enable */
-#define                  B3RDYPOL  0x20000    /* Bank 3 ARDY Polarity */
-#define                      B3TT  0xc0000    /* Bank 3 transition time */
-#define                      B3ST  0x300000   /* Bank 3 Setup time */
-#define                      B3HT  0xc00000   /* Bank 3 Hold time */
-#define                     B3RAT  0xf000000  /* Bank 3 Read access time */
-#define                     B3WAT  0xf0000000 /* Bank 3 write access time */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define                  AMSB0CTL  0x3        /* Async Memory Bank 0 select */
-#define                  AMSB1CTL  0xc        /* Async Memory Bank 1 select */
-#define                  AMSB2CTL  0x30       /* Async Memory Bank 2 select */
-#define                  AMSB3CTL  0xc0       /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define                    B0MODE  0x3        /* Async Memory Bank 0 Access Mode */
-#define                    B1MODE  0xc        /* Async Memory Bank 1 Access Mode */
-#define                    B2MODE  0x30       /* Async Memory Bank 2 Access Mode */
-#define                    B3MODE  0xc0       /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define               TESTSETLOCK  0x1        /* Test set lock */
-#define                      BCLK  0x6        /* Burst clock frequency */
-#define                      PGWS  0x38       /* Page wait states */
-#define                      PGSZ  0x40       /* Page size */
-#define                      RDDL  0x380      /* Read data delay */
-
-/* Bit masks for EBIU_ARBSTAT */
-
-#define                   ARBSTAT  0x1        /* Arbitration status */
-#define                    BGSTAT  0x2        /* Bus grant status */
-
-/* Bit masks for EBIU_DDRCTL0 */
-
-#define                     TREFI  0x3fff     /* Refresh Interval */
-#define                      TRFC  0x3c000    /* Auto-refresh command period */
-#define                       TRP  0x3c0000   /* Pre charge-to-active command period */
-#define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
-#define                       TRC  0x3c000000 /* Active-to-active time */
-#define DDR_TRAS(x)             ((x<<22)&TRAS)  /* DDR tRAS = (1~15) cycles */
-#define DDR_TRP(x)              ((x<<18)&TRP)   /* DDR tRP = (1~15) cycles */
-#define DDR_TRC(x)              ((x<<26)&TRC)   /* DDR tRC = (1~15) cycles */
-#define DDR_TRFC(x)             ((x<<14)&TRFC)  /* DDR tRFC = (1~15) cycles */
-#define DDR_TREFI(x)            (x&TREFI)       /* DDR tRFC = (1~15) cycles */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define                      TRCD  0xf        /* Active-to-Read/write delay */
-#define                      TMRD  0xf0       /* Mode register set to active */
-#define                       TWR  0x300      /* Write Recovery time */
-#define               DDRDATWIDTH  0x3000     /* DDR data width */
-#define                  EXTBANKS  0xc000     /* External banks */
-#define               DDRDEVWIDTH  0x30000    /* DDR device width */
-#define                DDRDEVSIZE  0xc0000    /* DDR device size */
-#define                      TWTR  0xf0000000 /* Write-to-read delay */
-#define DDR_TWTR(x)             ((x<<28)&TWTR)  /* DDR tWTR = (1~15) cycles */
-#define DDR_TMRD(x)             ((x<<4)&TMRD)   /* DDR tMRD = (1~15) cycles */
-#define DDR_TWR(x)              ((x<<8)&TWR)    /* DDR tWR = (1~15) cycles */
-#define DDR_TRCD(x)             (x&TRCD)        /* DDR tRCD = (1~15) cycles */
-#define DDR_DATWIDTH            0x2000          /* DDR data width */
-#define EXTBANK_1               0               /* 1 external bank */
-#define EXTBANK_2               0x4000          /* 2 external banks */
-#define DEVSZ_64                0x40000         /* DDR External Bank Size = 64MB */
-#define DEVSZ_128               0x80000         /* DDR External Bank Size = 128MB */
-#define DEVSZ_256               0xc0000         /* DDR External Bank Size = 256MB */
-#define DEVSZ_512               0               /* DDR External Bank Size = 512MB */
-#define DEVWD_4                 0               /* DDR Device Width = 4 Bits    */
-#define DEVWD_8                 0x10000         /* DDR Device Width = 8 Bits    */
-#define DEVWD_16                0x20000         /* DDR Device Width = 16 Bits    */
-
-/* Bit masks for EBIU_DDRCTL2 */
-
-#define               BURSTLENGTH  0x7        /* Burst length */
-#define                CASLATENCY  0x70       /* CAS latency */
-#define                  DLLRESET  0x100      /* DLL Reset */
-#define                      REGE  0x1000     /* Register mode enable */
-#define CL_1_5                  0x50            /* DDR CAS Latency = 1.5 cycles */
-#define CL_2                    0x20            /* DDR CAS Latency = 2 cycles */
-#define CL_2_5                  0x60            /* DDR CAS Latency = 2.5 cycles */
-#define CL_3                    0x30            /* DDR CAS Latency = 3 cycles */
-
-/* Bit masks for EBIU_DDRCTL3 */
-
-#define                      PASR  0x7        /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-
-#define                DEB1_PFLEN  0x3        /* Pre fetch length for DEB1 accesses */
-#define                DEB2_PFLEN  0xc        /* Pre fetch length for DEB2 accesses */
-#define                DEB3_PFLEN  0x30       /* Pre fetch length for DEB3 accesses */
-#define          DEB_ARB_PRIORITY  0x700      /* Arbitration between DEB busses */
-#define               DEB1_URGENT  0x1000     /* DEB1 Urgent */
-#define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
-#define               DEB3_URGENT  0x4000     /* DEB3 Urgent */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define                DEB1_ERROR  0x1        /* DEB1 Error */
-#define                DEB2_ERROR  0x2        /* DEB2 Error */
-#define                DEB3_ERROR  0x4        /* DEB3 Error */
-#define                CORE_ERROR  0x8        /* Core error */
-#define                DEB_MERROR  0x10       /* DEB1 Error (2nd) */
-#define               DEB2_MERROR  0x20       /* DEB2 Error (2nd) */
-#define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
-#define               CORE_MERROR  0x80       /* Core Error (2nd) */
-
-/* Bit masks for EBIU_ERRADD */
-
-#define             ERROR_ADDRESS  0xffffffff /* Error Address */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define                 DDRSRESET  0x1        /* DDR soft reset */
-#define               PFTCHSRESET  0x4        /* DDR prefetch reset */
-#define                     SRREQ  0x8        /* Self-refresh request */
-#define                     SRACK  0x10       /* Self-refresh acknowledge */
-#define                MDDRENABLE  0x20       /* Mobile DDR enable */
-
-/* Bit masks for EBIU_DDRBRC0 */
-
-#define                      BRC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC1 */
-
-#define                      BRC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC2 */
-
-#define                      BRC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC3 */
-
-#define                      BRC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC4 */
-
-#define                      BRC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC5 */
-
-#define                      BRC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC6 */
-
-#define                      BRC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC7 */
-
-#define                      BRC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC0 */
-
-#define                      BWC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC1 */
-
-#define                      BWC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC2 */
-
-#define                      BWC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC3 */
-
-#define                      BWC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC4 */
-
-#define                      BWC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC5 */
-
-#define                      BWC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC6 */
-
-#define                      BWC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC7 */
-
-#define                      BWC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRACCT */
-
-#define                      ACCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRTACT */
-
-#define                      TECT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRARCT */
-
-#define                      ARCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC0 */
-
-#define                       GC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC1 */
-
-#define                       GC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC2 */
-
-#define                       GC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC3 */
-
-#define                       GC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define                B0WCENABLE  0x1        /* Bank 0 write count enable */
-#define                B1WCENABLE  0x2        /* Bank 1 write count enable */
-#define                B2WCENABLE  0x4        /* Bank 2 write count enable */
-#define                B3WCENABLE  0x8        /* Bank 3 write count enable */
-#define                B4WCENABLE  0x10       /* Bank 4 write count enable */
-#define                B5WCENABLE  0x20       /* Bank 5 write count enable */
-#define                B6WCENABLE  0x40       /* Bank 6 write count enable */
-#define                B7WCENABLE  0x80       /* Bank 7 write count enable */
-#define                B0RCENABLE  0x100      /* Bank 0 read count enable */
-#define                B1RCENABLE  0x200      /* Bank 1 read count enable */
-#define                B2RCENABLE  0x400      /* Bank 2 read count enable */
-#define                B3RCENABLE  0x800      /* Bank 3 read count enable */
-#define                B4RCENABLE  0x1000     /* Bank 4 read count enable */
-#define                B5RCENABLE  0x2000     /* Bank 5 read count enable */
-#define                B6RCENABLE  0x4000     /* Bank 6 read count enable */
-#define                B7RCENABLE  0x8000     /* Bank 7 read count enable */
-#define             ROWACTCENABLE  0x10000    /* DDR Row activate count enable */
-#define                RWTCENABLE  0x20000    /* DDR R/W Turn around count enable */
-#define                 ARCENABLE  0x40000    /* DDR Auto-refresh count enable */
-#define                 GC0ENABLE  0x100000   /* DDR Grant count 0 enable */
-#define                 GC1ENABLE  0x200000   /* DDR Grant count 1 enable */
-#define                 GC2ENABLE  0x400000   /* DDR Grant count 2 enable */
-#define                 GC3ENABLE  0x800000   /* DDR Grant count 3 enable */
-#define                 GCCONTROL  0x3000000  /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define                 CB0WCOUNT  0x1        /* Clear write count 0 */
-#define                 CB1WCOUNT  0x2        /* Clear write count 1 */
-#define                 CB2WCOUNT  0x4        /* Clear write count 2 */
-#define                 CB3WCOUNT  0x8        /* Clear write count 3 */
-#define                 CB4WCOUNT  0x10       /* Clear write count 4 */
-#define                 CB5WCOUNT  0x20       /* Clear write count 5 */
-#define                 CB6WCOUNT  0x40       /* Clear write count 6 */
-#define                 CB7WCOUNT  0x80       /* Clear write count 7 */
-#define                  CBRCOUNT  0x100      /* Clear read count 0 */
-#define                 CB1RCOUNT  0x200      /* Clear read count 1 */
-#define                 CB2RCOUNT  0x400      /* Clear read count 2 */
-#define                 CB3RCOUNT  0x800      /* Clear read count 3 */
-#define                 CB4RCOUNT  0x1000     /* Clear read count 4 */
-#define                 CB5RCOUNT  0x2000     /* Clear read count 5 */
-#define                 CB6RCOUNT  0x4000     /* Clear read count 6 */
-#define                 CB7RCOUNT  0x8000     /* Clear read count 7 */
-#define                  CRACOUNT  0x10000    /* Clear row activation count */
-#define                CRWTACOUNT  0x20000    /* Clear R/W turn-around count */
-#define                  CARCOUNT  0x40000    /* Clear auto-refresh count */
-#define                  CG0COUNT  0x100000   /* Clear grant count 0 */
-#define                  CG1COUNT  0x200000   /* Clear grant count 1 */
-#define                  CG2COUNT  0x400000   /* Clear grant count 2 */
-#define                  CG3COUNT  0x800000   /* Clear grant count 3 */
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define                       Px0  0x1        /* GPIO 0 */
-#define                       Px1  0x2        /* GPIO 1 */
-#define                       Px2  0x4        /* GPIO 2 */
-#define                       Px3  0x8        /* GPIO 3 */
-#define                       Px4  0x10       /* GPIO 4 */
-#define                       Px5  0x20       /* GPIO 5 */
-#define                       Px6  0x40       /* GPIO 6 */
-#define                       Px7  0x80       /* GPIO 7 */
-#define                       Px8  0x100      /* GPIO 8 */
-#define                       Px9  0x200      /* GPIO 9 */
-#define                      Px10  0x400      /* GPIO 10 */
-#define                      Px11  0x800      /* GPIO 11 */
-#define                      Px12  0x1000     /* GPIO 12 */
-#define                      Px13  0x2000     /* GPIO 13 */
-#define                      Px14  0x4000     /* GPIO 14 */
-#define                      Px15  0x8000     /* GPIO 15 */
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define                      PxM0  0x3        /* GPIO Mux 0 */
-#define                      PxM1  0xc        /* GPIO Mux 1 */
-#define                      PxM2  0x30       /* GPIO Mux 2 */
-#define                      PxM3  0xc0       /* GPIO Mux 3 */
-#define                      PxM4  0x300      /* GPIO Mux 4 */
-#define                      PxM5  0xc00      /* GPIO Mux 5 */
-#define                      PxM6  0x3000     /* GPIO Mux 6 */
-#define                      PxM7  0xc000     /* GPIO Mux 7 */
-#define                      PxM8  0x30000    /* GPIO Mux 8 */
-#define                      PxM9  0xc0000    /* GPIO Mux 9 */
-#define                     PxM10  0x300000   /* GPIO Mux 10 */
-#define                     PxM11  0xc00000   /* GPIO Mux 11 */
-#define                     PxM12  0x3000000  /* GPIO Mux 12 */
-#define                     PxM13  0xc000000  /* GPIO Mux 13 */
-#define                     PxM14  0x30000000 /* GPIO Mux 14 */
-#define                     PxM15  0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define                       IB0  0x1        /* Interrupt Bit 0 */
-#define                       IB1  0x2        /* Interrupt Bit 1 */
-#define                       IB2  0x4        /* Interrupt Bit 2 */
-#define                       IB3  0x8        /* Interrupt Bit 3 */
-#define                       IB4  0x10       /* Interrupt Bit 4 */
-#define                       IB5  0x20       /* Interrupt Bit 5 */
-#define                       IB6  0x40       /* Interrupt Bit 6 */
-#define                       IB7  0x80       /* Interrupt Bit 7 */
-#define                       IB8  0x100      /* Interrupt Bit 8 */
-#define                       IB9  0x200      /* Interrupt Bit 9 */
-#define                      IB10  0x400      /* Interrupt Bit 10 */
-#define                      IB11  0x800      /* Interrupt Bit 11 */
-#define                      IB12  0x1000     /* Interrupt Bit 12 */
-#define                      IB13  0x2000     /* Interrupt Bit 13 */
-#define                      IB14  0x4000     /* Interrupt Bit 14 */
-#define                      IB15  0x8000     /* Interrupt Bit 15 */
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define                     TMODE  0x3        /* Timer Mode */
-#define                  PULSE_HI  0x4        /* Pulse Polarity */
-#define                PERIOD_CNT  0x8        /* Period Count */
-#define                   IRQ_ENA  0x10       /* Interrupt Request Enable */
-#define                   TIN_SEL  0x20       /* Timer Input Select */
-#define                   OUT_DIS  0x40       /* Output Pad Disable */
-#define                   CLK_SEL  0x80       /* Timer Clock Select */
-#define                 TOGGLE_HI  0x100      /* Toggle Mode */
-#define                   EMU_RUN  0x200      /* Emulation Behavior Select */
-#define                   ERR_TYP  0xc000     /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define                    TIMEN0  0x1        /* Timer 0 Enable */
-#define                    TIMEN1  0x2        /* Timer 1 Enable */
-#define                    TIMEN2  0x4        /* Timer 2 Enable */
-#define                    TIMEN3  0x8        /* Timer 3 Enable */
-#define                    TIMEN4  0x10       /* Timer 4 Enable */
-#define                    TIMEN5  0x20       /* Timer 5 Enable */
-#define                    TIMEN6  0x40       /* Timer 6 Enable */
-#define                    TIMEN7  0x80       /* Timer 7 Enable */
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define                   TIMDIS0  0x1        /* Timer 0 Disable */
-#define                   TIMDIS1  0x2        /* Timer 1 Disable */
-#define                   TIMDIS2  0x4        /* Timer 2 Disable */
-#define                   TIMDIS3  0x8        /* Timer 3 Disable */
-#define                   TIMDIS4  0x10       /* Timer 4 Disable */
-#define                   TIMDIS5  0x20       /* Timer 5 Disable */
-#define                   TIMDIS6  0x40       /* Timer 6 Disable */
-#define                   TIMDIS7  0x80       /* Timer 7 Disable */
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define                    TIMIL0  0x1        /* Timer 0 Interrupt */
-#define                    TIMIL1  0x2        /* Timer 1 Interrupt */
-#define                    TIMIL2  0x4        /* Timer 2 Interrupt */
-#define                    TIMIL3  0x8        /* Timer 3 Interrupt */
-#define                 TOVF_ERR0  0x10       /* Timer 0 Counter Overflow */
-#define                 TOVF_ERR1  0x20       /* Timer 1 Counter Overflow */
-#define                 TOVF_ERR2  0x40       /* Timer 2 Counter Overflow */
-#define                 TOVF_ERR3  0x80       /* Timer 3 Counter Overflow */
-#define                     TRUN0  0x1000     /* Timer 0 Slave Enable Status */
-#define                     TRUN1  0x2000     /* Timer 1 Slave Enable Status */
-#define                     TRUN2  0x4000     /* Timer 2 Slave Enable Status */
-#define                     TRUN3  0x8000     /* Timer 3 Slave Enable Status */
-#define                    TIMIL4  0x10000    /* Timer 4 Interrupt */
-#define                    TIMIL5  0x20000    /* Timer 5 Interrupt */
-#define                    TIMIL6  0x40000    /* Timer 6 Interrupt */
-#define                    TIMIL7  0x80000    /* Timer 7 Interrupt */
-#define                 TOVF_ERR4  0x100000   /* Timer 4 Counter Overflow */
-#define                 TOVF_ERR5  0x200000   /* Timer 5 Counter Overflow */
-#define                 TOVF_ERR6  0x400000   /* Timer 6 Counter Overflow */
-#define                 TOVF_ERR7  0x800000   /* Timer 7 Counter Overflow */
-#define                     TRUN4  0x10000000 /* Timer 4 Slave Enable Status */
-#define                     TRUN5  0x20000000 /* Timer 5 Slave Enable Status */
-#define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
-#define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Bit masks for WDOG_CTL */
-
-#define                      WDEV  0x6        /* Watchdog Event */
-#define                      WDEN  0xff0      /* Watchdog Enable */
-#define                      WDRO  0x8000     /* Watchdog Rolled Over */
-
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* Bit masks for RTC_STAT */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define               DAY_COUNTER  0xfffe0000 /* Day Counter */
-
-/* Bit masks for RTC_ICTL */
-
-#define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
-#define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
-#define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
-#define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
-#define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
-#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
-#define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
-#define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
-
-/* Bit masks for RTC_ISTAT */
-
-#define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
-#define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
-#define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
-#define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
-#define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
-#define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
-#define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
-#define     WRITE_PENDING__STATUS  0x4000     /* Write Pending  Status */
-#define            WRITE_COMPLETE  0x8000     /* Write Complete */
-
-/* Bit masks for RTC_SWCNT */
-
-#define           STOPWATCH_COUNT  0xffff     /* Stopwatch Count */
-
-/* Bit masks for RTC_ALARM */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define                       DAY  0xfffe0000 /* Day */
-
-/* Bit masks for RTC_PREN */
-
-#define                      PREN  0x1        /* Prescaler Enable */
-
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                   SECURE3  0x8        /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-/* Bit masks for PLL_DIV */
-
-#define                      CSEL  0x30       /* Core Select */
-#define                      SSEL  0xf        /* System Select */
-#define                 CSEL_DIV1       0x0000  /* CCLK = VCO / 1 */
-#define                 CSEL_DIV2       0x0010  /* CCLK = VCO / 2 */
-#define                 CSEL_DIV4       0x0020  /* CCLK = VCO / 4 */
-#define                 CSEL_DIV8       0x0030  /* CCLK = VCO / 8 */
-
-/* Bit masks for PLL_CTL */
-
-#define                      MSEL  0x7e00     /* Multiplier Select */
-#define                    BYPASS  0x100      /* PLL Bypass Enable */
-#define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
-#define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
-#define                      PDWN  0x20       /* Power Down */
-#define                    STOPCK  0x8        /* Stop Clock */
-#define                   PLL_OFF  0x2        /* Disable PLL */
-#define                        DF  0x1        /* Divide Frequency */
-
-/* SWRST Masks */
-#define              SYSTEM_RESET 0x0007       /* Initiates A System Software Reset */
-#define              DOUBLE_FAULT 0x0008       /* Core Double Fault Causes Reset */
-#define              RESET_DOUBLE 0x2000       /* SW Reset Generated By Core Double-Fault */
-#define                RESET_WDOG 0x4000       /* SW Reset Generated By Watchdog Timer */
-#define            RESET_SOFTWARE 0x8000       /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* Bit masks for PLL_STAT */
-
-#define                PLL_LOCKED  0x20       /* PLL Locked Status */
-#define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
-#define                   FULL_ON  0x2        /* Full-On Mode */
-#define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
-#define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
-#define                     CANWS  0x800      /* CAN Wake-Up Status */
-#define                     USBWS  0x2000     /* USB Wake-Up Status */
-#define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
-#define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
-#define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
-
-/* Bit masks for VR_CTL */
-
-#define                      FREQ  0x3        /* Regulator Switching Frequency */
-#define                      GAIN  0xc        /* Voltage Output Level Gain */
-#define                      VLEV  0xf0       /* Internal Voltage Level */
-#define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
-#define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
-#define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
-#define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
-#define                     USBWE  0x800      /* USB Wake-Up Enable */
-#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
-#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
-
-#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
-
-#define GAIN_5                  0x0000  /* GAIN = 5*/
-#define GAIN_10                 0x0004  /* GAIN = 1*/
-#define GAIN_20                 0x0008  /* GAIN = 2*/
-#define GAIN_50                 0x000C  /* GAIN = 5*/
-
-#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   PG_SIZE  0x200      /* Page Size */
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   WR_DONE  0x10       /* Page Write Done */
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define               PG_WR_START  0x2        /* Page Write Start */
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-/* Bit masks for CAN0_CONTROL */
-
-#define                       SRS  0x1        /* Software Reset */
-#define                       DNM  0x2        /* DeviceNet Mode */
-#define                       ABO  0x4        /* Auto Bus On */
-#define                       WBA  0x10       /* Wakeup On CAN Bus Activity */
-#define                       SMR  0x20       /* Sleep Mode Request */
-#define                       CSR  0x40       /* CAN Suspend Mode Request */
-#define                       CCR  0x80       /* CAN Configuration Mode Request */
-
-/* Bit masks for CAN0_STATUS */
-
-#define                        WT  0x1        /* CAN Transmit Warning Flag */
-#define                        WR  0x2        /* CAN Receive Warning Flag */
-#define                        EP  0x4        /* CAN Error Passive Mode */
-#define                       EBO  0x8        /* CAN Error Bus Off Mode */
-#define                       CSA  0x40       /* CAN Suspend Mode Acknowledge */
-#define                       CCA  0x80       /* CAN Configuration Mode Acknowledge */
-#define                     MBPTR  0x1f00     /* Mailbox Pointer */
-#define                       TRM  0x4000     /* Transmit Mode Status */
-#define                       REC  0x8000     /* Receive Mode Status */
-
-/* Bit masks for CAN0_DEBUG */
-
-#define                       DEC  0x1        /* Disable Transmit/Receive Error Counters */
-#define                       DRI  0x2        /* Disable CANRX Input Pin */
-#define                       DTO  0x4        /* Disable CANTX Output Pin */
-#define                       DIL  0x8        /* Disable Internal Loop */
-#define                       MAA  0x10       /* Mode Auto-Acknowledge */
-#define                       MRB  0x20       /* Mode Read Back */
-#define                       CDE  0x8000     /* CAN Debug Mode Enable */
-
-/* Bit masks for CAN0_CLOCK */
-
-#define                       BRP  0x3ff      /* CAN Bit Rate Prescaler */
-
-/* Bit masks for CAN0_TIMING */
-
-#define                       SJW  0x300      /* Synchronization Jump Width */
-#define                       SAM  0x80       /* Sampling */
-#define                     TSEG2  0x70       /* Time Segment 2 */
-#define                     TSEG1  0xf        /* Time Segment 1 */
-
-/* Bit masks for CAN0_INTR */
-
-#define                     CANRX  0x80       /* Serial Input From Transceiver */
-#define                     CANTX  0x40       /* Serial Output To Transceiver */
-#define                     SMACK  0x8        /* Sleep Mode Acknowledge */
-#define                      GIRQ  0x4        /* Global Interrupt Request Status */
-#define                    MBTIRQ  0x2        /* Mailbox Transmit Interrupt Request */
-#define                    MBRIRQ  0x1        /* Mailbox Receive Interrupt Request */
-
-/* Bit masks for CAN0_GIM */
-
-#define                     EWTIM  0x1        /* Error Warning Transmit Interrupt Mask */
-#define                     EWRIM  0x2        /* Error Warning Receive Interrupt Mask */
-#define                      EPIM  0x4        /* Error Passive Interrupt Mask */
-#define                      BOIM  0x8        /* Bus Off Interrupt Mask */
-#define                      WUIM  0x10       /* Wakeup Interrupt Mask */
-#define                     UIAIM  0x20       /* Unimplemented Address Interrupt Mask */
-#define                      AAIM  0x40       /* Abort Acknowledge Interrupt Mask */
-#define                     RMLIM  0x80       /* Receive Message Lost Interrupt Mask */
-#define                     UCEIM  0x100      /* Universal Counter Exceeded Interrupt Mask */
-#define                      ADIM  0x400      /* Access Denied Interrupt Mask */
-
-/* Bit masks for CAN0_GIS */
-
-#define                     EWTIS  0x1        /* Error Warning Transmit Interrupt Status */
-#define                     EWRIS  0x2        /* Error Warning Receive Interrupt Status */
-#define                      EPIS  0x4        /* Error Passive Interrupt Status */
-#define                      BOIS  0x8        /* Bus Off Interrupt Status */
-#define                      WUIS  0x10       /* Wakeup Interrupt Status */
-#define                     UIAIS  0x20       /* Unimplemented Address Interrupt Status */
-#define                      AAIS  0x40       /* Abort Acknowledge Interrupt Status */
-#define                     RMLIS  0x80       /* Receive Message Lost Interrupt Status */
-#define                     UCEIS  0x100      /* Universal Counter Exceeded Interrupt Status */
-#define                      ADIS  0x400      /* Access Denied Interrupt Status */
-
-/* Bit masks for CAN0_GIF */
-
-#define                     EWTIF  0x1        /* Error Warning Transmit Interrupt Flag */
-#define                     EWRIF  0x2        /* Error Warning Receive Interrupt Flag */
-#define                      EPIF  0x4        /* Error Passive Interrupt Flag */
-#define                      BOIF  0x8        /* Bus Off Interrupt Flag */
-#define                      WUIF  0x10       /* Wakeup Interrupt Flag */
-#define                     UIAIF  0x20       /* Unimplemented Address Interrupt Flag */
-#define                      AAIF  0x40       /* Abort Acknowledge Interrupt Flag */
-#define                     RMLIF  0x80       /* Receive Message Lost Interrupt Flag */
-#define                     UCEIF  0x100      /* Universal Counter Exceeded Interrupt Flag */
-#define                      ADIF  0x400      /* Access Denied Interrupt Flag */
-
-/* Bit masks for CAN0_MBTD */
-
-#define                       TDR  0x80       /* Temporary Disable Request */
-#define                       TDA  0x40       /* Temporary Disable Acknowledge */
-#define                     TDPTR  0x1f       /* Temporary Disable Pointer */
-
-/* Bit masks for CAN0_UCCNF */
-
-#define                     UCCNF  0xf        /* Universal Counter Configuration */
-#define                      UCRC  0x20       /* Universal Counter Reload/Clear */
-#define                      UCCT  0x40       /* Universal Counter CAN Trigger */
-#define                       UCE  0x80       /* Universal Counter Enable */
-
-/* Bit masks for CAN0_UCCNT */
-
-#define                     UCCNT  0xffff     /* Universal Counter Count Value */
-
-/* Bit masks for CAN0_UCRC */
-
-#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */
-
-/* Bit masks for CAN0_CEC */
-
-#define                    RXECNT  0xff       /* Receive Error Counter */
-#define                    TXECNT  0xff00     /* Transmit Error Counter */
-
-/* Bit masks for CAN0_ESR */
-
-#define                       FER  0x80       /* Form Error */
-#define                       BEF  0x40       /* Bit Error Flag */
-#define                       SA0  0x20       /* Stuck At Dominant */
-#define                      CRCE  0x10       /* CRC Error */
-#define                       SER  0x8        /* Stuff Bit Error */
-#define                      ACKE  0x4        /* Acknowledge Error */
-
-/* Bit masks for CAN0_EWR */
-
-#define                    EWLTEC  0xff00     /* Transmit Error Warning Limit */
-#define                    EWLREC  0xff       /* Receive Error Warning Limit */
-
-/* Bit masks for CAN0_AMxx_H */
-
-#define                       FDF  0x8000     /* Filter On Data Field */
-#define                       FMD  0x4000     /* Full Mask Data */
-#define                     AMIDE  0x2000     /* Acceptance Mask Identifier Extension */
-#define                    BASEID  0x1ffc     /* Base Identifier */
-#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_AMxx_L */
-
-#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
-#define                       DFM  0xffff     /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_ID1 */
-
-#define                       AME  0x8000     /* Acceptance Mask Enable */
-#define                       RTR  0x4000     /* Remote Transmission Request */
-#define                       IDE  0x2000     /* Identifier Extension */
-#define                    BASEID  0x1ffc     /* Base Identifier */
-#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_MBxx_ID0 */
-
-#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
-#define                       DFM  0xffff     /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_TIMESTAMP */
-
-#define                       TSV  0xffff     /* Time Stamp Value */
-
-/* Bit masks for CAN0_MBxx_LENGTH */
-
-#define                       DLC  0xf        /* Data Length Code */
-
-/* Bit masks for CAN0_MBxx_DATA3 */
-
-#define                 CAN_BYTE0  0xff00     /* Data Field Byte 0 */
-#define                 CAN_BYTE1  0xff       /* Data Field Byte 1 */
-
-/* Bit masks for CAN0_MBxx_DATA2 */
-
-#define                 CAN_BYTE2  0xff00     /* Data Field Byte 2 */
-#define                 CAN_BYTE3  0xff       /* Data Field Byte 3 */
-
-/* Bit masks for CAN0_MBxx_DATA1 */
-
-#define                 CAN_BYTE4  0xff00     /* Data Field Byte 4 */
-#define                 CAN_BYTE5  0xff       /* Data Field Byte 5 */
-
-/* Bit masks for CAN0_MBxx_DATA0 */
-
-#define                 CAN_BYTE6  0xff00     /* Data Field Byte 6 */
-#define                 CAN_BYTE7  0xff       /* Data Field Byte 7 */
-
-/* Bit masks for CAN0_MC1 */
-
-#define                       MC0  0x1        /* Mailbox 0 Enable */
-#define                       MC1  0x2        /* Mailbox 1 Enable */
-#define                       MC2  0x4        /* Mailbox 2 Enable */
-#define                       MC3  0x8        /* Mailbox 3 Enable */
-#define                       MC4  0x10       /* Mailbox 4 Enable */
-#define                       MC5  0x20       /* Mailbox 5 Enable */
-#define                       MC6  0x40       /* Mailbox 6 Enable */
-#define                       MC7  0x80       /* Mailbox 7 Enable */
-#define                       MC8  0x100      /* Mailbox 8 Enable */
-#define                       MC9  0x200      /* Mailbox 9 Enable */
-#define                      MC10  0x400      /* Mailbox 10 Enable */
-#define                      MC11  0x800      /* Mailbox 11 Enable */
-#define                      MC12  0x1000     /* Mailbox 12 Enable */
-#define                      MC13  0x2000     /* Mailbox 13 Enable */
-#define                      MC14  0x4000     /* Mailbox 14 Enable */
-#define                      MC15  0x8000     /* Mailbox 15 Enable */
-
-/* Bit masks for CAN0_MC2 */
-
-#define                      MC16  0x1        /* Mailbox 16 Enable */
-#define                      MC17  0x2        /* Mailbox 17 Enable */
-#define                      MC18  0x4        /* Mailbox 18 Enable */
-#define                      MC19  0x8        /* Mailbox 19 Enable */
-#define                      MC20  0x10       /* Mailbox 20 Enable */
-#define                      MC21  0x20       /* Mailbox 21 Enable */
-#define                      MC22  0x40       /* Mailbox 22 Enable */
-#define                      MC23  0x80       /* Mailbox 23 Enable */
-#define                      MC24  0x100      /* Mailbox 24 Enable */
-#define                      MC25  0x200      /* Mailbox 25 Enable */
-#define                      MC26  0x400      /* Mailbox 26 Enable */
-#define                      MC27  0x800      /* Mailbox 27 Enable */
-#define                      MC28  0x1000     /* Mailbox 28 Enable */
-#define                      MC29  0x2000     /* Mailbox 29 Enable */
-#define                      MC30  0x4000     /* Mailbox 30 Enable */
-#define                      MC31  0x8000     /* Mailbox 31 Enable */
-
-/* Bit masks for CAN0_MD1 */
-
-#define                       MD0  0x1        /* Mailbox 0 Receive Enable */
-#define                       MD1  0x2        /* Mailbox 1 Receive Enable */
-#define                       MD2  0x4        /* Mailbox 2 Receive Enable */
-#define                       MD3  0x8        /* Mailbox 3 Receive Enable */
-#define                       MD4  0x10       /* Mailbox 4 Receive Enable */
-#define                       MD5  0x20       /* Mailbox 5 Receive Enable */
-#define                       MD6  0x40       /* Mailbox 6 Receive Enable */
-#define                       MD7  0x80       /* Mailbox 7 Receive Enable */
-#define                       MD8  0x100      /* Mailbox 8 Receive Enable */
-#define                       MD9  0x200      /* Mailbox 9 Receive Enable */
-#define                      MD10  0x400      /* Mailbox 10 Receive Enable */
-#define                      MD11  0x800      /* Mailbox 11 Receive Enable */
-#define                      MD12  0x1000     /* Mailbox 12 Receive Enable */
-#define                      MD13  0x2000     /* Mailbox 13 Receive Enable */
-#define                      MD14  0x4000     /* Mailbox 14 Receive Enable */
-#define                      MD15  0x8000     /* Mailbox 15 Receive Enable */
-
-/* Bit masks for CAN0_MD2 */
-
-#define                      MD16  0x1        /* Mailbox 16 Receive Enable */
-#define                      MD17  0x2        /* Mailbox 17 Receive Enable */
-#define                      MD18  0x4        /* Mailbox 18 Receive Enable */
-#define                      MD19  0x8        /* Mailbox 19 Receive Enable */
-#define                      MD20  0x10       /* Mailbox 20 Receive Enable */
-#define                      MD21  0x20       /* Mailbox 21 Receive Enable */
-#define                      MD22  0x40       /* Mailbox 22 Receive Enable */
-#define                      MD23  0x80       /* Mailbox 23 Receive Enable */
-#define                      MD24  0x100      /* Mailbox 24 Receive Enable */
-#define                      MD25  0x200      /* Mailbox 25 Receive Enable */
-#define                      MD26  0x400      /* Mailbox 26 Receive Enable */
-#define                      MD27  0x800      /* Mailbox 27 Receive Enable */
-#define                      MD28  0x1000     /* Mailbox 28 Receive Enable */
-#define                      MD29  0x2000     /* Mailbox 29 Receive Enable */
-#define                      MD30  0x4000     /* Mailbox 30 Receive Enable */
-#define                      MD31  0x8000     /* Mailbox 31 Receive Enable */
-
-/* Bit masks for CAN0_RMP1 */
-
-#define                      RMP0  0x1        /* Mailbox 0 Receive Message Pending */
-#define                      RMP1  0x2        /* Mailbox 1 Receive Message Pending */
-#define                      RMP2  0x4        /* Mailbox 2 Receive Message Pending */
-#define                      RMP3  0x8        /* Mailbox 3 Receive Message Pending */
-#define                      RMP4  0x10       /* Mailbox 4 Receive Message Pending */
-#define                      RMP5  0x20       /* Mailbox 5 Receive Message Pending */
-#define                      RMP6  0x40       /* Mailbox 6 Receive Message Pending */
-#define                      RMP7  0x80       /* Mailbox 7 Receive Message Pending */
-#define                      RMP8  0x100      /* Mailbox 8 Receive Message Pending */
-#define                      RMP9  0x200      /* Mailbox 9 Receive Message Pending */
-#define                     RMP10  0x400      /* Mailbox 10 Receive Message Pending */
-#define                     RMP11  0x800      /* Mailbox 11 Receive Message Pending */
-#define                     RMP12  0x1000     /* Mailbox 12 Receive Message Pending */
-#define                     RMP13  0x2000     /* Mailbox 13 Receive Message Pending */
-#define                     RMP14  0x4000     /* Mailbox 14 Receive Message Pending */
-#define                     RMP15  0x8000     /* Mailbox 15 Receive Message Pending */
-
-/* Bit masks for CAN0_RMP2 */
-
-#define                     RMP16  0x1        /* Mailbox 16 Receive Message Pending */
-#define                     RMP17  0x2        /* Mailbox 17 Receive Message Pending */
-#define                     RMP18  0x4        /* Mailbox 18 Receive Message Pending */
-#define                     RMP19  0x8        /* Mailbox 19 Receive Message Pending */
-#define                     RMP20  0x10       /* Mailbox 20 Receive Message Pending */
-#define                     RMP21  0x20       /* Mailbox 21 Receive Message Pending */
-#define                     RMP22  0x40       /* Mailbox 22 Receive Message Pending */
-#define                     RMP23  0x80       /* Mailbox 23 Receive Message Pending */
-#define                     RMP24  0x100      /* Mailbox 24 Receive Message Pending */
-#define                     RMP25  0x200      /* Mailbox 25 Receive Message Pending */
-#define                     RMP26  0x400      /* Mailbox 26 Receive Message Pending */
-#define                     RMP27  0x800      /* Mailbox 27 Receive Message Pending */
-#define                     RMP28  0x1000     /* Mailbox 28 Receive Message Pending */
-#define                     RMP29  0x2000     /* Mailbox 29 Receive Message Pending */
-#define                     RMP30  0x4000     /* Mailbox 30 Receive Message Pending */
-#define                     RMP31  0x8000     /* Mailbox 31 Receive Message Pending */
-
-/* Bit masks for CAN0_RML1 */
-
-#define                      RML0  0x1        /* Mailbox 0 Receive Message Lost */
-#define                      RML1  0x2        /* Mailbox 1 Receive Message Lost */
-#define                      RML2  0x4        /* Mailbox 2 Receive Message Lost */
-#define                      RML3  0x8        /* Mailbox 3 Receive Message Lost */
-#define                      RML4  0x10       /* Mailbox 4 Receive Message Lost */
-#define                      RML5  0x20       /* Mailbox 5 Receive Message Lost */
-#define                      RML6  0x40       /* Mailbox 6 Receive Message Lost */
-#define                      RML7  0x80       /* Mailbox 7 Receive Message Lost */
-#define                      RML8  0x100      /* Mailbox 8 Receive Message Lost */
-#define                      RML9  0x200      /* Mailbox 9 Receive Message Lost */
-#define                     RML10  0x400      /* Mailbox 10 Receive Message Lost */
-#define                     RML11  0x800      /* Mailbox 11 Receive Message Lost */
-#define                     RML12  0x1000     /* Mailbox 12 Receive Message Lost */
-#define                     RML13  0x2000     /* Mailbox 13 Receive Message Lost */
-#define                     RML14  0x4000     /* Mailbox 14 Receive Message Lost */
-#define                     RML15  0x8000     /* Mailbox 15 Receive Message Lost */
-
-/* Bit masks for CAN0_RML2 */
-
-#define                     RML16  0x1        /* Mailbox 16 Receive Message Lost */
-#define                     RML17  0x2        /* Mailbox 17 Receive Message Lost */
-#define                     RML18  0x4        /* Mailbox 18 Receive Message Lost */
-#define                     RML19  0x8        /* Mailbox 19 Receive Message Lost */
-#define                     RML20  0x10       /* Mailbox 20 Receive Message Lost */
-#define                     RML21  0x20       /* Mailbox 21 Receive Message Lost */
-#define                     RML22  0x40       /* Mailbox 22 Receive Message Lost */
-#define                     RML23  0x80       /* Mailbox 23 Receive Message Lost */
-#define                     RML24  0x100      /* Mailbox 24 Receive Message Lost */
-#define                     RML25  0x200      /* Mailbox 25 Receive Message Lost */
-#define                     RML26  0x400      /* Mailbox 26 Receive Message Lost */
-#define                     RML27  0x800      /* Mailbox 27 Receive Message Lost */
-#define                     RML28  0x1000     /* Mailbox 28 Receive Message Lost */
-#define                     RML29  0x2000     /* Mailbox 29 Receive Message Lost */
-#define                     RML30  0x4000     /* Mailbox 30 Receive Message Lost */
-#define                     RML31  0x8000     /* Mailbox 31 Receive Message Lost */
-
-/* Bit masks for CAN0_OPSS1 */
-
-#define                     OPSS0  0x1        /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS1  0x2        /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS2  0x4        /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS3  0x8        /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS4  0x10       /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS5  0x20       /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS6  0x40       /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS7  0x80       /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS8  0x100      /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS9  0x200      /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS10  0x400      /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS11  0x800      /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS12  0x1000     /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS13  0x2000     /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS14  0x4000     /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS15  0x8000     /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
-
-/* Bit masks for CAN0_OPSS2 */
-
-#define                    OPSS16  0x1        /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS17  0x2        /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS18  0x4        /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS19  0x8        /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS20  0x10       /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS21  0x20       /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS22  0x40       /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS23  0x80       /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS24  0x100      /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS25  0x200      /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS26  0x400      /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS27  0x800      /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS28  0x1000     /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS29  0x2000     /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS30  0x4000     /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS31  0x8000     /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
-
-/* Bit masks for CAN0_TRS1 */
-
-#define                      TRS0  0x1        /* Mailbox 0 Transmit Request Set */
-#define                      TRS1  0x2        /* Mailbox 1 Transmit Request Set */
-#define                      TRS2  0x4        /* Mailbox 2 Transmit Request Set */
-#define                      TRS3  0x8        /* Mailbox 3 Transmit Request Set */
-#define                      TRS4  0x10       /* Mailbox 4 Transmit Request Set */
-#define                      TRS5  0x20       /* Mailbox 5 Transmit Request Set */
-#define                      TRS6  0x40       /* Mailbox 6 Transmit Request Set */
-#define                      TRS7  0x80       /* Mailbox 7 Transmit Request Set */
-#define                      TRS8  0x100      /* Mailbox 8 Transmit Request Set */
-#define                      TRS9  0x200      /* Mailbox 9 Transmit Request Set */
-#define                     TRS10  0x400      /* Mailbox 10 Transmit Request Set */
-#define                     TRS11  0x800      /* Mailbox 11 Transmit Request Set */
-#define                     TRS12  0x1000     /* Mailbox 12 Transmit Request Set */
-#define                     TRS13  0x2000     /* Mailbox 13 Transmit Request Set */
-#define                     TRS14  0x4000     /* Mailbox 14 Transmit Request Set */
-#define                     TRS15  0x8000     /* Mailbox 15 Transmit Request Set */
-
-/* Bit masks for CAN0_TRS2 */
-
-#define                     TRS16  0x1        /* Mailbox 16 Transmit Request Set */
-#define                     TRS17  0x2        /* Mailbox 17 Transmit Request Set */
-#define                     TRS18  0x4        /* Mailbox 18 Transmit Request Set */
-#define                     TRS19  0x8        /* Mailbox 19 Transmit Request Set */
-#define                     TRS20  0x10       /* Mailbox 20 Transmit Request Set */
-#define                     TRS21  0x20       /* Mailbox 21 Transmit Request Set */
-#define                     TRS22  0x40       /* Mailbox 22 Transmit Request Set */
-#define                     TRS23  0x80       /* Mailbox 23 Transmit Request Set */
-#define                     TRS24  0x100      /* Mailbox 24 Transmit Request Set */
-#define                     TRS25  0x200      /* Mailbox 25 Transmit Request Set */
-#define                     TRS26  0x400      /* Mailbox 26 Transmit Request Set */
-#define                     TRS27  0x800      /* Mailbox 27 Transmit Request Set */
-#define                     TRS28  0x1000     /* Mailbox 28 Transmit Request Set */
-#define                     TRS29  0x2000     /* Mailbox 29 Transmit Request Set */
-#define                     TRS30  0x4000     /* Mailbox 30 Transmit Request Set */
-#define                     TRS31  0x8000     /* Mailbox 31 Transmit Request Set */
-
-/* Bit masks for CAN0_TRR1 */
-
-#define                      TRR0  0x1        /* Mailbox 0 Transmit Request Reset */
-#define                      TRR1  0x2        /* Mailbox 1 Transmit Request Reset */
-#define                      TRR2  0x4        /* Mailbox 2 Transmit Request Reset */
-#define                      TRR3  0x8        /* Mailbox 3 Transmit Request Reset */
-#define                      TRR4  0x10       /* Mailbox 4 Transmit Request Reset */
-#define                      TRR5  0x20       /* Mailbox 5 Transmit Request Reset */
-#define                      TRR6  0x40       /* Mailbox 6 Transmit Request Reset */
-#define                      TRR7  0x80       /* Mailbox 7 Transmit Request Reset */
-#define                      TRR8  0x100      /* Mailbox 8 Transmit Request Reset */
-#define                      TRR9  0x200      /* Mailbox 9 Transmit Request Reset */
-#define                     TRR10  0x400      /* Mailbox 10 Transmit Request Reset */
-#define                     TRR11  0x800      /* Mailbox 11 Transmit Request Reset */
-#define                     TRR12  0x1000     /* Mailbox 12 Transmit Request Reset */
-#define                     TRR13  0x2000     /* Mailbox 13 Transmit Request Reset */
-#define                     TRR14  0x4000     /* Mailbox 14 Transmit Request Reset */
-#define                     TRR15  0x8000     /* Mailbox 15 Transmit Request Reset */
-
-/* Bit masks for CAN0_TRR2 */
-
-#define                     TRR16  0x1        /* Mailbox 16 Transmit Request Reset */
-#define                     TRR17  0x2        /* Mailbox 17 Transmit Request Reset */
-#define                     TRR18  0x4        /* Mailbox 18 Transmit Request Reset */
-#define                     TRR19  0x8        /* Mailbox 19 Transmit Request Reset */
-#define                     TRR20  0x10       /* Mailbox 20 Transmit Request Reset */
-#define                     TRR21  0x20       /* Mailbox 21 Transmit Request Reset */
-#define                     TRR22  0x40       /* Mailbox 22 Transmit Request Reset */
-#define                     TRR23  0x80       /* Mailbox 23 Transmit Request Reset */
-#define                     TRR24  0x100      /* Mailbox 24 Transmit Request Reset */
-#define                     TRR25  0x200      /* Mailbox 25 Transmit Request Reset */
-#define                     TRR26  0x400      /* Mailbox 26 Transmit Request Reset */
-#define                     TRR27  0x800      /* Mailbox 27 Transmit Request Reset */
-#define                     TRR28  0x1000     /* Mailbox 28 Transmit Request Reset */
-#define                     TRR29  0x2000     /* Mailbox 29 Transmit Request Reset */
-#define                     TRR30  0x4000     /* Mailbox 30 Transmit Request Reset */
-#define                     TRR31  0x8000     /* Mailbox 31 Transmit Request Reset */
-
-/* Bit masks for CAN0_AA1 */
-
-#define                       AA0  0x1        /* Mailbox 0 Abort Acknowledge */
-#define                       AA1  0x2        /* Mailbox 1 Abort Acknowledge */
-#define                       AA2  0x4        /* Mailbox 2 Abort Acknowledge */
-#define                       AA3  0x8        /* Mailbox 3 Abort Acknowledge */
-#define                       AA4  0x10       /* Mailbox 4 Abort Acknowledge */
-#define                       AA5  0x20       /* Mailbox 5 Abort Acknowledge */
-#define                       AA6  0x40       /* Mailbox 6 Abort Acknowledge */
-#define                       AA7  0x80       /* Mailbox 7 Abort Acknowledge */
-#define                       AA8  0x100      /* Mailbox 8 Abort Acknowledge */
-#define                       AA9  0x200      /* Mailbox 9 Abort Acknowledge */
-#define                      AA10  0x400      /* Mailbox 10 Abort Acknowledge */
-#define                      AA11  0x800      /* Mailbox 11 Abort Acknowledge */
-#define                      AA12  0x1000     /* Mailbox 12 Abort Acknowledge */
-#define                      AA13  0x2000     /* Mailbox 13 Abort Acknowledge */
-#define                      AA14  0x4000     /* Mailbox 14 Abort Acknowledge */
-#define                      AA15  0x8000     /* Mailbox 15 Abort Acknowledge */
-
-/* Bit masks for CAN0_AA2 */
-
-#define                      AA16  0x1        /* Mailbox 16 Abort Acknowledge */
-#define                      AA17  0x2        /* Mailbox 17 Abort Acknowledge */
-#define                      AA18  0x4        /* Mailbox 18 Abort Acknowledge */
-#define                      AA19  0x8        /* Mailbox 19 Abort Acknowledge */
-#define                      AA20  0x10       /* Mailbox 20 Abort Acknowledge */
-#define                      AA21  0x20       /* Mailbox 21 Abort Acknowledge */
-#define                      AA22  0x40       /* Mailbox 22 Abort Acknowledge */
-#define                      AA23  0x80       /* Mailbox 23 Abort Acknowledge */
-#define                      AA24  0x100      /* Mailbox 24 Abort Acknowledge */
-#define                      AA25  0x200      /* Mailbox 25 Abort Acknowledge */
-#define                      AA26  0x400      /* Mailbox 26 Abort Acknowledge */
-#define                      AA27  0x800      /* Mailbox 27 Abort Acknowledge */
-#define                      AA28  0x1000     /* Mailbox 28 Abort Acknowledge */
-#define                      AA29  0x2000     /* Mailbox 29 Abort Acknowledge */
-#define                      AA30  0x4000     /* Mailbox 30 Abort Acknowledge */
-#define                      AA31  0x8000     /* Mailbox 31 Abort Acknowledge */
-
-/* Bit masks for CAN0_TA1 */
-
-#define                       TA0  0x1        /* Mailbox 0 Transmit Acknowledge */
-#define                       TA1  0x2        /* Mailbox 1 Transmit Acknowledge */
-#define                       TA2  0x4        /* Mailbox 2 Transmit Acknowledge */
-#define                       TA3  0x8        /* Mailbox 3 Transmit Acknowledge */
-#define                       TA4  0x10       /* Mailbox 4 Transmit Acknowledge */
-#define                       TA5  0x20       /* Mailbox 5 Transmit Acknowledge */
-#define                       TA6  0x40       /* Mailbox 6 Transmit Acknowledge */
-#define                       TA7  0x80       /* Mailbox 7 Transmit Acknowledge */
-#define                       TA8  0x100      /* Mailbox 8 Transmit Acknowledge */
-#define                       TA9  0x200      /* Mailbox 9 Transmit Acknowledge */
-#define                      TA10  0x400      /* Mailbox 10 Transmit Acknowledge */
-#define                      TA11  0x800      /* Mailbox 11 Transmit Acknowledge */
-#define                      TA12  0x1000     /* Mailbox 12 Transmit Acknowledge */
-#define                      TA13  0x2000     /* Mailbox 13 Transmit Acknowledge */
-#define                      TA14  0x4000     /* Mailbox 14 Transmit Acknowledge */
-#define                      TA15  0x8000     /* Mailbox 15 Transmit Acknowledge */
-
-/* Bit masks for CAN0_TA2 */
-
-#define                      TA16  0x1        /* Mailbox 16 Transmit Acknowledge */
-#define                      TA17  0x2        /* Mailbox 17 Transmit Acknowledge */
-#define                      TA18  0x4        /* Mailbox 18 Transmit Acknowledge */
-#define                      TA19  0x8        /* Mailbox 19 Transmit Acknowledge */
-#define                      TA20  0x10       /* Mailbox 20 Transmit Acknowledge */
-#define                      TA21  0x20       /* Mailbox 21 Transmit Acknowledge */
-#define                      TA22  0x40       /* Mailbox 22 Transmit Acknowledge */
-#define                      TA23  0x80       /* Mailbox 23 Transmit Acknowledge */
-#define                      TA24  0x100      /* Mailbox 24 Transmit Acknowledge */
-#define                      TA25  0x200      /* Mailbox 25 Transmit Acknowledge */
-#define                      TA26  0x400      /* Mailbox 26 Transmit Acknowledge */
-#define                      TA27  0x800      /* Mailbox 27 Transmit Acknowledge */
-#define                      TA28  0x1000     /* Mailbox 28 Transmit Acknowledge */
-#define                      TA29  0x2000     /* Mailbox 29 Transmit Acknowledge */
-#define                      TA30  0x4000     /* Mailbox 30 Transmit Acknowledge */
-#define                      TA31  0x8000     /* Mailbox 31 Transmit Acknowledge */
-
-/* Bit masks for CAN0_RFH1 */
-
-#define                      RFH0  0x1        /* Mailbox 0 Remote Frame Handling Enable */
-#define                      RFH1  0x2        /* Mailbox 1 Remote Frame Handling Enable */
-#define                      RFH2  0x4        /* Mailbox 2 Remote Frame Handling Enable */
-#define                      RFH3  0x8        /* Mailbox 3 Remote Frame Handling Enable */
-#define                      RFH4  0x10       /* Mailbox 4 Remote Frame Handling Enable */
-#define                      RFH5  0x20       /* Mailbox 5 Remote Frame Handling Enable */
-#define                      RFH6  0x40       /* Mailbox 6 Remote Frame Handling Enable */
-#define                      RFH7  0x80       /* Mailbox 7 Remote Frame Handling Enable */
-#define                      RFH8  0x100      /* Mailbox 8 Remote Frame Handling Enable */
-#define                      RFH9  0x200      /* Mailbox 9 Remote Frame Handling Enable */
-#define                     RFH10  0x400      /* Mailbox 10 Remote Frame Handling Enable */
-#define                     RFH11  0x800      /* Mailbox 11 Remote Frame Handling Enable */
-#define                     RFH12  0x1000     /* Mailbox 12 Remote Frame Handling Enable */
-#define                     RFH13  0x2000     /* Mailbox 13 Remote Frame Handling Enable */
-#define                     RFH14  0x4000     /* Mailbox 14 Remote Frame Handling Enable */
-#define                     RFH15  0x8000     /* Mailbox 15 Remote Frame Handling Enable */
-
-/* Bit masks for CAN0_RFH2 */
-
-#define                     RFH16  0x1        /* Mailbox 16 Remote Frame Handling Enable */
-#define                     RFH17  0x2        /* Mailbox 17 Remote Frame Handling Enable */
-#define                     RFH18  0x4        /* Mailbox 18 Remote Frame Handling Enable */
-#define                     RFH19  0x8        /* Mailbox 19 Remote Frame Handling Enable */
-#define                     RFH20  0x10       /* Mailbox 20 Remote Frame Handling Enable */
-#define                     RFH21  0x20       /* Mailbox 21 Remote Frame Handling Enable */
-#define                     RFH22  0x40       /* Mailbox 22 Remote Frame Handling Enable */
-#define                     RFH23  0x80       /* Mailbox 23 Remote Frame Handling Enable */
-#define                     RFH24  0x100      /* Mailbox 24 Remote Frame Handling Enable */
-#define                     RFH25  0x200      /* Mailbox 25 Remote Frame Handling Enable */
-#define                     RFH26  0x400      /* Mailbox 26 Remote Frame Handling Enable */
-#define                     RFH27  0x800      /* Mailbox 27 Remote Frame Handling Enable */
-#define                     RFH28  0x1000     /* Mailbox 28 Remote Frame Handling Enable */
-#define                     RFH29  0x2000     /* Mailbox 29 Remote Frame Handling Enable */
-#define                     RFH30  0x4000     /* Mailbox 30 Remote Frame Handling Enable */
-#define                     RFH31  0x8000     /* Mailbox 31 Remote Frame Handling Enable */
-
-/* Bit masks for CAN0_MBIM1 */
-
-#define                     MBIM0  0x1        /* Mailbox 0 Mailbox Interrupt Mask */
-#define                     MBIM1  0x2        /* Mailbox 1 Mailbox Interrupt Mask */
-#define                     MBIM2  0x4        /* Mailbox 2 Mailbox Interrupt Mask */
-#define                     MBIM3  0x8        /* Mailbox 3 Mailbox Interrupt Mask */
-#define                     MBIM4  0x10       /* Mailbox 4 Mailbox Interrupt Mask */
-#define                     MBIM5  0x20       /* Mailbox 5 Mailbox Interrupt Mask */
-#define                     MBIM6  0x40       /* Mailbox 6 Mailbox Interrupt Mask */
-#define                     MBIM7  0x80       /* Mailbox 7 Mailbox Interrupt Mask */
-#define                     MBIM8  0x100      /* Mailbox 8 Mailbox Interrupt Mask */
-#define                     MBIM9  0x200      /* Mailbox 9 Mailbox Interrupt Mask */
-#define                    MBIM10  0x400      /* Mailbox 10 Mailbox Interrupt Mask */
-#define                    MBIM11  0x800      /* Mailbox 11 Mailbox Interrupt Mask */
-#define                    MBIM12  0x1000     /* Mailbox 12 Mailbox Interrupt Mask */
-#define                    MBIM13  0x2000     /* Mailbox 13 Mailbox Interrupt Mask */
-#define                    MBIM14  0x4000     /* Mailbox 14 Mailbox Interrupt Mask */
-#define                    MBIM15  0x8000     /* Mailbox 15 Mailbox Interrupt Mask */
-
-/* Bit masks for CAN0_MBIM2 */
-
-#define                    MBIM16  0x1        /* Mailbox 16 Mailbox Interrupt Mask */
-#define                    MBIM17  0x2        /* Mailbox 17 Mailbox Interrupt Mask */
-#define                    MBIM18  0x4        /* Mailbox 18 Mailbox Interrupt Mask */
-#define                    MBIM19  0x8        /* Mailbox 19 Mailbox Interrupt Mask */
-#define                    MBIM20  0x10       /* Mailbox 20 Mailbox Interrupt Mask */
-#define                    MBIM21  0x20       /* Mailbox 21 Mailbox Interrupt Mask */
-#define                    MBIM22  0x40       /* Mailbox 22 Mailbox Interrupt Mask */
-#define                    MBIM23  0x80       /* Mailbox 23 Mailbox Interrupt Mask */
-#define                    MBIM24  0x100      /* Mailbox 24 Mailbox Interrupt Mask */
-#define                    MBIM25  0x200      /* Mailbox 25 Mailbox Interrupt Mask */
-#define                    MBIM26  0x400      /* Mailbox 26 Mailbox Interrupt Mask */
-#define                    MBIM27  0x800      /* Mailbox 27 Mailbox Interrupt Mask */
-#define                    MBIM28  0x1000     /* Mailbox 28 Mailbox Interrupt Mask */
-#define                    MBIM29  0x2000     /* Mailbox 29 Mailbox Interrupt Mask */
-#define                    MBIM30  0x4000     /* Mailbox 30 Mailbox Interrupt Mask */
-#define                    MBIM31  0x8000     /* Mailbox 31 Mailbox Interrupt Mask */
-
-/* Bit masks for CAN0_MBTIF1 */
-
-#define                    MBTIF0  0x1        /* Mailbox 0 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF1  0x2        /* Mailbox 1 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF2  0x4        /* Mailbox 2 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF3  0x8        /* Mailbox 3 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF4  0x10       /* Mailbox 4 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF5  0x20       /* Mailbox 5 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF6  0x40       /* Mailbox 6 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF7  0x80       /* Mailbox 7 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF8  0x100      /* Mailbox 8 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF9  0x200      /* Mailbox 9 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF10  0x400      /* Mailbox 10 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF11  0x800      /* Mailbox 11 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF12  0x1000     /* Mailbox 12 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF13  0x2000     /* Mailbox 13 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF14  0x4000     /* Mailbox 14 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF15  0x8000     /* Mailbox 15 Mailbox Transmit Interrupt Flag */
-
-/* Bit masks for CAN0_MBTIF2 */
-
-#define                   MBTIF16  0x1        /* Mailbox 16 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF17  0x2        /* Mailbox 17 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF18  0x4        /* Mailbox 18 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF19  0x8        /* Mailbox 19 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF20  0x10       /* Mailbox 20 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF21  0x20       /* Mailbox 21 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF22  0x40       /* Mailbox 22 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF23  0x80       /* Mailbox 23 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF24  0x100      /* Mailbox 24 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF25  0x200      /* Mailbox 25 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF26  0x400      /* Mailbox 26 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF27  0x800      /* Mailbox 27 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF28  0x1000     /* Mailbox 28 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF29  0x2000     /* Mailbox 29 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF30  0x4000     /* Mailbox 30 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF31  0x8000     /* Mailbox 31 Mailbox Transmit Interrupt Flag */
-
-/* Bit masks for CAN0_MBRIF1 */
-
-#define                    MBRIF0  0x1        /* Mailbox 0 Mailbox Receive Interrupt Flag */
-#define                    MBRIF1  0x2        /* Mailbox 1 Mailbox Receive Interrupt Flag */
-#define                    MBRIF2  0x4        /* Mailbox 2 Mailbox Receive Interrupt Flag */
-#define                    MBRIF3  0x8        /* Mailbox 3 Mailbox Receive Interrupt Flag */
-#define                    MBRIF4  0x10       /* Mailbox 4 Mailbox Receive Interrupt Flag */
-#define                    MBRIF5  0x20       /* Mailbox 5 Mailbox Receive Interrupt Flag */
-#define                    MBRIF6  0x40       /* Mailbox 6 Mailbox Receive Interrupt Flag */
-#define                    MBRIF7  0x80       /* Mailbox 7 Mailbox Receive Interrupt Flag */
-#define                    MBRIF8  0x100      /* Mailbox 8 Mailbox Receive Interrupt Flag */
-#define                    MBRIF9  0x200      /* Mailbox 9 Mailbox Receive Interrupt Flag */
-#define                   MBRIF10  0x400      /* Mailbox 10 Mailbox Receive Interrupt Flag */
-#define                   MBRIF11  0x800      /* Mailbox 11 Mailbox Receive Interrupt Flag */
-#define                   MBRIF12  0x1000     /* Mailbox 12 Mailbox Receive Interrupt Flag */
-#define                   MBRIF13  0x2000     /* Mailbox 13 Mailbox Receive Interrupt Flag */
-#define                   MBRIF14  0x4000     /* Mailbox 14 Mailbox Receive Interrupt Flag */
-#define                   MBRIF15  0x8000     /* Mailbox 15 Mailbox Receive Interrupt Flag */
-
-/* Bit masks for CAN0_MBRIF2 */
-
-#define                   MBRIF16  0x1        /* Mailbox 16 Mailbox Receive Interrupt Flag */
-#define                   MBRIF17  0x2        /* Mailbox 17 Mailbox Receive Interrupt Flag */
-#define                   MBRIF18  0x4        /* Mailbox 18 Mailbox Receive Interrupt Flag */
-#define                   MBRIF19  0x8        /* Mailbox 19 Mailbox Receive Interrupt Flag */
-#define                   MBRIF20  0x10       /* Mailbox 20 Mailbox Receive Interrupt Flag */
-#define                   MBRIF21  0x20       /* Mailbox 21 Mailbox Receive Interrupt Flag */
-#define                   MBRIF22  0x40       /* Mailbox 22 Mailbox Receive Interrupt Flag */
-#define                   MBRIF23  0x80       /* Mailbox 23 Mailbox Receive Interrupt Flag */
-#define                   MBRIF24  0x100      /* Mailbox 24 Mailbox Receive Interrupt Flag */
-#define                   MBRIF25  0x200      /* Mailbox 25 Mailbox Receive Interrupt Flag */
-#define                   MBRIF26  0x400      /* Mailbox 26 Mailbox Receive Interrupt Flag */
-#define                   MBRIF27  0x800      /* Mailbox 27 Mailbox Receive Interrupt Flag */
-#define                   MBRIF28  0x1000     /* Mailbox 28 Mailbox Receive Interrupt Flag */
-#define                   MBRIF29  0x2000     /* Mailbox 29 Mailbox Receive Interrupt Flag */
-#define                   MBRIF30  0x4000     /* Mailbox 30 Mailbox Receive Interrupt Flag */
-#define                   MBRIF31  0x8000     /* Mailbox 31 Mailbox Receive Interrupt Flag */
-
-/* Bit masks for EPPIx_STATUS */
-
-#define                 CFIFO_ERR  0x1        /* Chroma FIFO Error */
-#define                 YFIFO_ERR  0x2        /* Luma FIFO Error */
-#define                 LTERR_OVR  0x4        /* Line Track Overflow */
-#define                LTERR_UNDR  0x8        /* Line Track Underflow */
-#define                 FTERR_OVR  0x10       /* Frame Track Overflow */
-#define                FTERR_UNDR  0x20       /* Frame Track Underflow */
-#define                  ERR_NCOR  0x40       /* Preamble Error Not Corrected */
-#define                   DMA1URQ  0x80       /* DMA1 Urgent Request */
-#define                   DMA0URQ  0x100      /* DMA0 Urgent Request */
-#define                   ERR_DET  0x4000     /* Preamble Error Detected */
-#define                       FLD  0x8000     /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define                   EPPI_EN  0x1        /* Enable */
-#define                  EPPI_DIR  0x2        /* Direction */
-#define                  XFR_TYPE  0xc        /* Operating Mode */
-#define                    FS_CFG  0x30       /* Frame Sync Configuration */
-#define                   FLD_SEL  0x40       /* Field Select/Trigger */
-#define                  ITU_TYPE  0x80       /* ITU Interlaced or Progressive */
-#define                  BLANKGEN  0x100      /* ITU Output Mode with Internal Blanking Generation */
-#define                   ICLKGEN  0x200      /* Internal Clock Generation */
-#define                    IFSGEN  0x400      /* Internal Frame Sync Generation */
-#define                      POLC  0x1800     /* Frame Sync and Data Driving/Sampling Edges */
-#define                      POLS  0x6000     /* Frame Sync Polarity */
-#define                   DLENGTH  0x38000    /* Data Length */
-#define                   SKIP_EN  0x40000    /* Skip Enable */
-#define                   SKIP_EO  0x80000    /* Skip Even or Odd */
-#define                    PACKEN  0x100000   /* Packing/Unpacking Enable */
-#define                    SWAPEN  0x200000   /* Swap Enable */
-#define                  SIGN_EXT  0x400000   /* Sign Extension or Zero-filled / Data Split Format */
-#define             SPLT_EVEN_ODD  0x800000   /* Split Even and Odd Data Samples */
-#define               SUBSPLT_ODD  0x1000000  /* Sub-split Odd Samples */
-#define                    DMACFG  0x2000000  /* One or Two DMA Channels Mode */
-#define                RGB_FMT_EN  0x4000000  /* RGB Formatting Enable */
-#define                  FIFO_RWM  0x18000000 /* FIFO Regular Watermarks */
-#define                  FIFO_UWM  0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8          (0 << 15) /* 000 - 8 bits */
-#define DLEN_10         (1 << 15) /* 001 - 10 bits */
-#define DLEN_12         (2 << 15) /* 010 - 12 bits */
-#define DLEN_14         (3 << 15) /* 011 - 14 bits */
-#define DLEN_16         (4 << 15) /* 100 - 16 bits */
-#define DLEN_18         (5 << 15) /* 101 - 18 bits */
-#define DLEN_24         (6 << 15) /* 110 - 24 bits */
-
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define                   F1VB_BD  0xff       /* Vertical Blanking before Field 1 Active Data */
-#define                   F1VB_AD  0xff00     /* Vertical Blanking after Field 1 Active Data */
-#define                   F2VB_BD  0xff0000   /* Vertical Blanking before Field 2 Active Data */
-#define                   F2VB_AD  0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define                    F1_ACT  0xffff     /* Number of Lines of Active Data in Field 1 */
-#define                    F2_ACT  0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define                   LOW_ODD  0xff       /* Lower Limit for Odd Bytes (Chroma) */
-#define                  HIGH_ODD  0xff00     /* Upper Limit for Odd Bytes (Chroma) */
-#define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
-#define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-/* Bit masks for SPIx_BAUD */
-
-#define                  SPI_BAUD  0xffff     /* Baud Rate */
-
-/* Bit masks for SPIx_CTL */
-
-#define                       SPE  0x4000     /* SPI Enable */
-#define                       WOM  0x2000     /* Write Open Drain Master */
-#define                      MSTR  0x1000     /* Master Mode */
-#define                      CPOL  0x800      /* Clock Polarity */
-#define                      CPHA  0x400      /* Clock Phase */
-#define                      LSBF  0x200      /* LSB First */
-#define                      SIZE  0x100      /* Size of Words */
-#define                     EMISO  0x20       /* Enable MISO Output */
-#define                      PSSE  0x10       /* Slave-Select Enable */
-#define                        GM  0x8        /* Get More Data */
-#define                        SZ  0x4        /* Send Zero */
-#define                     TIMOD  0x3        /* Transfer Initiation Mode */
-
-/* Bit masks for SPIx_FLG */
-
-#define                      FLS1  0x2        /* Slave Select Enable 1 */
-#define                      FLS2  0x4        /* Slave Select Enable 2 */
-#define                      FLS3  0x8        /* Slave Select Enable 3 */
-#define                      FLG1  0x200      /* Slave Select Value 1 */
-#define                      FLG2  0x400      /* Slave Select Value 2 */
-#define                      FLG3  0x800      /* Slave Select Value 3 */
-
-/* Bit masks for SPIx_STAT */
-
-#define                     TXCOL  0x40       /* Transmit Collision Error */
-#define                       RXS  0x20       /* RDBR Data Buffer Status */
-#define                      RBSY  0x10       /* Receive Error */
-#define                       TXS  0x8        /* TDBR Data Buffer Status */
-#define                       TXE  0x4        /* Transmission Error */
-#define                      MODF  0x2        /* Mode Fault Error */
-#define                      SPIF  0x1        /* SPI Finished */
-
-/* Bit masks for SPIx_TDBR */
-
-#define                      TDBR  0xffff     /* Transmit Data Buffer */
-
-/* Bit masks for SPIx_RDBR */
-
-#define                      RDBR  0xffff     /* Receive Data Buffer */
-
-/* Bit masks for SPIx_SHADOW */
-
-#define                    SHADOW  0xffff     /* RDBR Shadow */
-
-/* ************************************************ */
-/* The TWI bit masks fields are from the ADSP-BF538 */
-/* and they have not been verified as the final     */
-/* ones for the Moab processors ... bz 1/19/2007    */
-/* ************************************************ */
-
-/* Bit masks for TWIx_CONTROL */
-
-#define                  PRESCALE  0x7f       /* Prescale Value */
-#define                   TWI_ENA  0x80       /* TWI Enable */
-#define                      SCCB  0x200      /* Serial Camera Control Bus */
-
-/* Bit maskes for TWIx_CLKDIV */
-
-#define                    CLKLOW  0xff       /* Clock Low */
-#define                     CLKHI  0xff00     /* Clock High */
-
-/* Bit maskes for TWIx_SLAVE_CTL */
-
-#define                       SEN  0x1        /* Slave Enable */
-#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
-#define                       NAK  0x8        /* Not Acknowledge */
-#define                       GEN  0x10       /* General Call Enable */
-
-/* Bit maskes for TWIx_SLAVE_ADDR */
-
-#define                     SADDR  0x7f       /* Slave Mode Address */
-
-/* Bit maskes for TWIx_SLAVE_STAT */
-
-#define                      SDIR  0x1        /* Slave Transfer Direction */
-#define                     GCALL  0x2        /* General Call */
-
-/* Bit maskes for TWIx_MASTER_CTL */
-
-#define                       MEN  0x1        /* Master Mode Enable */
-#define                      MDIR  0x4        /* Master Transfer Direction */
-#define                      FAST  0x8        /* Fast Mode */
-#define                      STOP  0x10       /* Issue Stop Condition */
-#define                    RSTART  0x20       /* Repeat Start */
-#define                      DCNT  0x3fc0     /* Data Transfer Count */
-#define                    SDAOVR  0x4000     /* Serial Data Override */
-#define                    SCLOVR  0x8000     /* Serial Clock Override */
-
-/* Bit maskes for TWIx_MASTER_ADDR */
-
-#define                     MADDR  0x7f       /* Master Mode Address */
-
-/* Bit maskes for TWIx_MASTER_STAT */
-
-#define                     MPROG  0x1        /* Master Transfer in Progress */
-#define                   LOSTARB  0x2        /* Lost Arbitration */
-#define                      ANAK  0x4        /* Address Not Acknowledged */
-#define                      DNAK  0x8        /* Data Not Acknowledged */
-#define                  BUFRDERR  0x10       /* Buffer Read Error */
-#define                  BUFWRERR  0x20       /* Buffer Write Error */
-#define                    SDASEN  0x40       /* Serial Data Sense */
-#define                    SCLSEN  0x80       /* Serial Clock Sense */
-#define                   BUSBUSY  0x100      /* Bus Busy */
-
-/* Bit maskes for TWIx_FIFO_CTL */
-
-#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
-#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
-#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
-#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
-
-/* Bit maskes for TWIx_FIFO_STAT */
-
-#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
-#define                   RCVSTAT  0xc        /* Receive FIFO Status */
-
-/* Bit maskes for TWIx_INT_MASK */
-
-#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
-#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
-#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
-#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
-#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
-#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
-#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
-#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
-
-/* Bit maskes for TWIx_INT_STAT */
-
-#define                     SINIT  0x1        /* Slave Transfer Initiated */
-#define                     SCOMP  0x2        /* Slave Transfer Complete */
-#define                      SERR  0x4        /* Slave Transfer Error */
-#define                      SOVF  0x8        /* Slave Overflow */
-#define                     MCOMP  0x10       /* Master Transfer Complete */
-#define                      MERR  0x20       /* Master Transfer Error */
-#define                   XMTSERV  0x40       /* Transmit FIFO Service */
-#define                   RCVSERV  0x80       /* Receive FIFO Service */
-
-/* Bit maskes for TWIx_XMT_DATA8 */
-
-#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_XMT_DATA16 */
-
-#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA8 */
-
-#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA16 */
-
-#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
-
-/* Bit masks for SPORTx_TCR1 */
-
-#define                     TCKFE  0x4000     /* Clock Falling Edge Select */
-#define                     LATFS  0x2000     /* Late Transmit Frame Sync */
-#define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
-#define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
-#define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
-#define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
-#define                    TLSBIT  0x10       /* Transmit Bit Order */
-#define                    TDTYPE  0xc        /* Data Formatting Type Select */
-#define                     ITCLK  0x2        /* Internal Transmit Clock Select */
-#define                     TSPEN  0x1        /* Transmit Enable */
-
-/* Bit masks for SPORTx_TCR2 */
-
-#define                     TRFST  0x400      /* Left/Right Order */
-#define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
-#define                      TXSE  0x100      /* TxSEC Enable */
-#define                    SLEN_T  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_RCR1 */
-
-#define                     RCKFE  0x4000     /* Clock Falling Edge Select */
-#define                     LARFS  0x2000     /* Late Receive Frame Sync */
-#define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
-#define                      RFSR  0x400      /* Receive Frame Sync Required Select */
-#define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
-#define                    RLSBIT  0x10       /* Receive Bit Order */
-#define                    RDTYPE  0xc        /* Data Formatting Type Select */
-#define                     IRCLK  0x2        /* Internal Receive Clock Select */
-#define                     RSPEN  0x1        /* Receive Enable */
-
-/* Bit masks for SPORTx_RCR2 */
-
-#define                     RRFST  0x400      /* Left/Right Order */
-#define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
-#define                      RXSE  0x100      /* RxSEC Enable */
-#define                    SLEN_R  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_STAT */
-
-#define                     TXHRE  0x40       /* Transmit Hold Register Empty */
-#define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
-#define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
-#define                       TXF  0x8        /* Transmit FIFO Full Status */
-#define                      ROVF  0x4        /* Sticky Receive Overflow Status */
-#define                      RUVF  0x2        /* Sticky Receive Underflow Status */
-#define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
-
-/* Bit masks for SPORTx_MCMC1 */
-
-#define                  SP_WSIZE  0xf000     /* Window Size */
-#define                   SP_WOFF  0x3ff      /* Windows Offset */
-
-/* Bit masks for SPORTx_MCMC2 */
-
-#define                       MFD  0xf000     /* Multi channel Frame Delay */
-#define                      FSDR  0x80       /* Frame Sync to Data Relationship */
-#define                  MCMEN  0x10       /* Multi channel Frame Mode Enable */
-#define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
-#define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
-#define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
-
-/* Bit masks for SPORTx_CHNL */
-
-#define                  CUR_CHNL  0x3ff      /* Current Channel Indicator */
-
-/* Bit masks for UARTx_LCR */
-
-#if 0
-/* conflicts with legacy one in last section */
-#define                       WLS  0x3        /* Word Length Select */
-#endif
-#define                       STB  0x4        /* Stop Bits */
-#define                       PEN  0x8        /* Parity Enable */
-#define                       EPS  0x10       /* Even Parity Select */
-#define                       STP  0x20       /* Sticky Parity */
-#define                        SB  0x40       /* Set Break */
-
-/* Bit masks for UARTx_MCR */
-
-#define                      XOFF  0x1        /* Transmitter Off */
-#define                      MRTS  0x2        /* Manual Request To Send */
-#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                      ARTS  0x40       /* Automatic Request To Send */
-#define                      ACTS  0x80       /* Automatic Clear To Send */
-
-/* Bit masks for UARTx_LSR */
-
-#define                        DR  0x1        /* Data Ready */
-#define                        OE  0x2        /* Overrun Error */
-#define                        PE  0x4        /* Parity Error */
-#define                        FE  0x8        /* Framing Error */
-#define                        BI  0x10       /* Break Interrupt */
-#define                      THRE  0x20       /* THR Empty */
-#define                      TEMT  0x40       /* Transmitter Empty */
-#define                       TFI  0x80       /* Transmission Finished Indicator */
-
-/* Bit masks for UARTx_MSR */
-
-#define                      SCTS  0x1        /* Sticky CTS */
-#define                       CTS  0x10       /* Clear To Send */
-#define                      RFCS  0x20       /* Receive FIFO Count Status */
-
-/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
-
-#define                   ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                   ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                    ELSI  0x4        /* Enable Receive Status Interrupt */
-#define                   EDSSI  0x8        /* Enable Modem Status Interrupt */
-#define                  EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                    ETFI  0x20       /* Enable Transmission Finished Interrupt */
-#define                   ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
-
-/* Bit masks for UARTx_GCTL */
-
-#define                      UCEN  0x1        /* UART Enable */
-#define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                       FPE  0x10       /* Force Parity Error */
-#define                       FFE  0x20       /* Force Framing Error */
-#define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* BCODE bit field options (SYSCFG register) */
-
-#define BCODE_WAKEUP    0x0000  /* boot according to wake-up condition */
-#define BCODE_FULLBOOT  0x0010  /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020  /* always perform quick boot */
-#define BCODE_NOBOOT    0x0030  /* always perform full boot */
-
-/* CNT_COMMAND bit field options */
-
-#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
-#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
-#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
-
-#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
-#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
-#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
-
-#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
-#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
-#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
-
-/* CNT_CONFIG bit field options */
-
-#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
-#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
-#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
-#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
-#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
-
-#define BNDMODE_COMP     0x0000  /* boundary compare mode */
-#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
-#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
-#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT  0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK  0x0003
-
-/* UARTx_LCR bit field options */
-
-#define WLS_5   0x0000    /* 5 data bits */
-#define WLS_6   0x0001    /* 6 data bits */
-#define WLS_7   0x0002    /* 7 data bits */
-#define WLS_8   0x0003    /* 8 data bits */
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* PORT A Bit Definitions for the registers
-PORTA, PORTA_SET, PORTA_CLEAR,
-PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
-PORTA_FER registers
-*/
-
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* PORT B Bit Definitions for the registers
-PORTB, PORTB_SET, PORTB_CLEAR,
-PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
-PORTB_FER registers
-*/
-
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-
-
-/* PORT C Bit Definitions for the registers
-PORTC, PORTC_SET, PORTC_CLEAR,
-PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
-PORTC_FER registers
-*/
-
-
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-
-
-/* PORT D Bit Definitions for the registers
-PORTD, PORTD_SET, PORTD_CLEAR,
-PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
-PORTD_FER registers
-*/
-
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* PORT E Bit Definitions for the registers
-PORTE, PORTE_SET, PORTE_CLEAR,
-PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
-PORTE_FER registers
-*/
-
-
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* PORT F Bit Definitions for the registers
-PORTF, PORTF_SET, PORTF_CLEAR,
-PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
-PORTF_FER registers
-*/
-
-
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* PORT G Bit Definitions for the registers
-PORTG, PORTG_SET, PORTG_CLEAR,
-PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
-PORTG_FER registers
-*/
-
-
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* PORT H Bit Definitions for the registers
-PORTH, PORTH_SET, PORTH_CLEAR,
-PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
-PORTH_FER registers
-*/
-
-
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-
-
-/* PORT I Bit Definitions for the registers
-PORTI, PORTI_SET, PORTI_CLEAR,
-PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
-PORTI_FER registers
-*/
-
-
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* PORT J Bit Definitions for the registers
-PORTJ, PORTJ_SET, PORTJ_CLEAR,
-PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
-PORTJ_FER registers
-*/
-
-
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
-    ((((b15)&3) << 30) | \
-     (((b14)&3) << 28) | \
-     (((b13)&3) << 26) | \
-     (((b12)&3) << 24) | \
-     (((b11)&3) << 22) | \
-     (((b10)&3) << 20) | \
-     (((b9) &3) << 18) | \
-     (((b8) &3) << 16) | \
-     (((b7) &3) << 14) | \
-     (((b6) &3) << 12) | \
-     (((b5) &3) << 10) | \
-     (((b4) &3) << 8)  | \
-     (((b3) &3) << 6)  | \
-     (((b2) &3) << 4)  | \
-     (((b1) &3) << 2)  | \
-     (((b0) &3)))
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF     /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00     /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000     /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000     /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-
-/* for legacy compatibility */
-
-#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
-#define W1LMAX_MAX W1LMAX_MIN
-#define EBIU_AMCBCTL0 EBIU_AMBCTL0
-#define EBIU_AMCBCTL1 EBIU_AMBCTL1
-#define PINT0_IRQ PINT0_REQUEST
-#define PINT1_IRQ PINT1_REQUEST
-#define PINT2_IRQ PINT2_REQUEST
-#define PINT3_IRQ PINT3_REQUEST
-
-#endif /* _DEF_BF54X_H */
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
deleted file mode 100644
index 36a2ef7e7849..000000000000
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf548/dma.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_RX            0
-#define CH_SPORT0_TX            1
-#define CH_SPORT1_RX            2
-#define CH_SPORT1_TX            3
-#define CH_SPI0                 4
-#define CH_SPI1                 5
-#define CH_UART0_RX             6
-#define CH_UART0_TX             7
-#define CH_UART1_RX             8
-#define CH_UART1_TX             9
-#define CH_ATAPI_RX             10
-#define CH_ATAPI_TX             11
-#define CH_EPPI0                12
-#define CH_EPPI1                13
-#define CH_EPPI2                14
-#define CH_PIXC_IMAGE           15
-#define CH_PIXC_OVERLAY         16
-#define CH_PIXC_OUTPUT          17
-#define CH_SPORT2_RX            18
-#define CH_UART2_RX             18
-#define CH_SPORT2_TX            19
-#define CH_UART2_TX             19
-#define CH_SPORT3_RX            20
-#define CH_UART3_RX             20
-#define CH_SPORT3_TX            21
-#define CH_UART3_TX             21
-#define CH_SDH                  22
-#define CH_NFC                  22
-#define CH_SPI2                 23
-
-#define CH_MEM_STREAM0_DEST     24
-#define CH_MEM_STREAM0_SRC      25
-#define CH_MEM_STREAM1_DEST     26
-#define CH_MEM_STREAM1_SRC      27
-#define CH_MEM_STREAM2_DEST     28
-#define CH_MEM_STREAM2_SRC      29
-#define CH_MEM_STREAM3_DEST     30
-#define CH_MEM_STREAM3_SRC      31
-
-#define MAX_BLACKFIN_DMA_CHANNEL 32
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
deleted file mode 100644
index bba82dc75f16..000000000000
--- a/include/asm-blackfin/mach-bf548/gpio.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/gpio.h
- * Based on:
- * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-
-
-#define GPIO_PA0        0
-#define GPIO_PA1        1
-#define GPIO_PA2        2
-#define GPIO_PA3        3
-#define GPIO_PA4        4
-#define GPIO_PA5        5
-#define GPIO_PA6        6
-#define GPIO_PA7        7
-#define GPIO_PA8        8
-#define GPIO_PA9        9
-#define GPIO_PA10       10
-#define GPIO_PA11       11
-#define GPIO_PA12       12
-#define GPIO_PA13       13
-#define GPIO_PA14       14
-#define GPIO_PA15       15
-#define GPIO_PB0        16
-#define GPIO_PB1        17
-#define GPIO_PB2        18
-#define GPIO_PB3        19
-#define GPIO_PB4        20
-#define GPIO_PB5        21
-#define GPIO_PB6        22
-#define GPIO_PB7        23
-#define GPIO_PB8        24
-#define GPIO_PB9        25
-#define GPIO_PB10       26
-#define GPIO_PB11       27
-#define GPIO_PB12       28
-#define GPIO_PB13       29
-#define GPIO_PB14       30
-#define GPIO_PB15       31      /* N/A */
-#define GPIO_PC0        32
-#define GPIO_PC1        33
-#define GPIO_PC2        34
-#define GPIO_PC3        35
-#define GPIO_PC4        36
-#define GPIO_PC5        37
-#define GPIO_PC6        38
-#define GPIO_PC7        39
-#define GPIO_PC8        40
-#define GPIO_PC9        41
-#define GPIO_PC10       42
-#define GPIO_PC11       43
-#define GPIO_PC12       44
-#define GPIO_PC13       45
-#define GPIO_PC14       46      /* N/A */
-#define GPIO_PC15       47      /* N/A */
-#define GPIO_PD0        48
-#define GPIO_PD1        49
-#define GPIO_PD2        50
-#define GPIO_PD3        51
-#define GPIO_PD4        52
-#define GPIO_PD5        53
-#define GPIO_PD6        54
-#define GPIO_PD7        55
-#define GPIO_PD8        56
-#define GPIO_PD9        57
-#define GPIO_PD10       58
-#define GPIO_PD11       59
-#define GPIO_PD12       60
-#define GPIO_PD13       61
-#define GPIO_PD14       62
-#define GPIO_PD15       63
-#define GPIO_PE0        64
-#define GPIO_PE1        65
-#define GPIO_PE2        66
-#define GPIO_PE3        67
-#define GPIO_PE4        68
-#define GPIO_PE5        69
-#define GPIO_PE6        70
-#define GPIO_PE7        71
-#define GPIO_PE8        72
-#define GPIO_PE9        73
-#define GPIO_PE10       74
-#define GPIO_PE11       75
-#define GPIO_PE12       76
-#define GPIO_PE13       77
-#define GPIO_PE14       78
-#define GPIO_PE15       79
-#define GPIO_PF0        80
-#define GPIO_PF1        81
-#define GPIO_PF2        82
-#define GPIO_PF3        83
-#define GPIO_PF4        84
-#define GPIO_PF5        85
-#define GPIO_PF6        86
-#define GPIO_PF7        87
-#define GPIO_PF8        88
-#define GPIO_PF9        89
-#define GPIO_PF10       90
-#define GPIO_PF11       91
-#define GPIO_PF12       92
-#define GPIO_PF13       93
-#define GPIO_PF14       94
-#define GPIO_PF15       95
-#define GPIO_PG0        96
-#define GPIO_PG1        97
-#define GPIO_PG2        98
-#define GPIO_PG3        99
-#define GPIO_PG4        100
-#define GPIO_PG5        101
-#define GPIO_PG6        102
-#define GPIO_PG7        103
-#define GPIO_PG8        104
-#define GPIO_PG9        105
-#define GPIO_PG10       106
-#define GPIO_PG11       107
-#define GPIO_PG12       108
-#define GPIO_PG13       109
-#define GPIO_PG14       110
-#define GPIO_PG15       111
-#define GPIO_PH0        112
-#define GPIO_PH1        113
-#define GPIO_PH2        114
-#define GPIO_PH3        115
-#define GPIO_PH4        116
-#define GPIO_PH5        117
-#define GPIO_PH6        118
-#define GPIO_PH7        119
-#define GPIO_PH8        120
-#define GPIO_PH9        121
-#define GPIO_PH10       122
-#define GPIO_PH11       123
-#define GPIO_PH12       124
-#define GPIO_PH13       125
-#define GPIO_PH14       126     /* N/A */
-#define GPIO_PH15       127     /* N/A */
-#define GPIO_PI0        128
-#define GPIO_PI1        129
-#define GPIO_PI2        130
-#define GPIO_PI3        131
-#define GPIO_PI4        132
-#define GPIO_PI5        133
-#define GPIO_PI6        134
-#define GPIO_PI7        135
-#define GPIO_PI8        136
-#define GPIO_PI9        137
-#define GPIO_PI10       138
-#define GPIO_PI11       139
-#define GPIO_PI12       140
-#define GPIO_PI13       141
-#define GPIO_PI14       142
-#define GPIO_PI15       143
-#define GPIO_PJ0        144
-#define GPIO_PJ1        145
-#define GPIO_PJ2        146
-#define GPIO_PJ3        147
-#define GPIO_PJ4        148
-#define GPIO_PJ5        149
-#define GPIO_PJ6        150
-#define GPIO_PJ7        151
-#define GPIO_PJ8        152
-#define GPIO_PJ9        153
-#define GPIO_PJ10       154
-#define GPIO_PJ11       155
-#define GPIO_PJ12       156
-#define GPIO_PJ13       157
-#define GPIO_PJ14       158     /* N/A */
-#define GPIO_PJ15       159     /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-struct gpio_port_t {
-        unsigned short port_fer;
-        unsigned short dummy1;
-        unsigned short port_data;
-        unsigned short dummy2;
-        unsigned short port_set;
-        unsigned short dummy3;
-        unsigned short port_clear;
-        unsigned short dummy4;
-        unsigned short port_dir_set;
-        unsigned short dummy5;
-        unsigned short port_dir_clear;
-        unsigned short dummy6;
-        unsigned short port_inen;
-        unsigned short dummy7;
-        unsigned int port_mux;
-};
-
-struct gpio_port_s {
-        unsigned short fer;
-        unsigned short data;
-        unsigned short dir;
-        unsigned short inen;
-        unsigned int mux;
-};
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
deleted file mode 100644
index ad380d1f5872..000000000000
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf548/irq.h
- * based on:    include/asm-blackfin/mach-bf537/irq.h
- * author:      Roy Huang (roy.huang@analog.com)
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _BF548_IRQ_H_
-#define _BF548_IRQ_H_
-
-/*
- * Interrupt source definitions
-            Event Source    Core Event Name
-Core        Emulation               **
-Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-
-.....
-
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
-                 (lowest priority)  IVG15       32 *
- */
-
-#define NR_PERI_INTS    (32 * 3)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt*/
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
-
-#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERROR         BFIN_IRQ(1)     /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERROR         BFIN_IRQ(2)     /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERROR          BFIN_IRQ(5)     /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC                 BFIN_IRQ(7)     /* RTC Interrupt */
-#define IRQ_EPPI0               BFIN_IRQ(8)     /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0                BFIN_IRQ(13)    /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX            BFIN_IRQ(14)    /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX            BFIN_IRQ(15)    /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8              BFIN_IRQ(16)    /* TIMER 8 Interrupt */
-#define IRQ_TIMER9              BFIN_IRQ(17)    /* TIMER 9 Interrupt */
-#define IRQ_TIMER10             BFIN_IRQ(18)    /* TIMER 10 Interrupt */
-#define IRQ_PINT0               BFIN_IRQ(19)    /* PINT0 Interrupt */
-#define IRQ_PINT1               BFIN_IRQ(20)    /* PINT1 Interrupt */
-#define IRQ_MDMAS0              BFIN_IRQ(21)    /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1              BFIN_IRQ(22)    /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCH               BFIN_IRQ(23)    /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERROR         BFIN_IRQ(24)    /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERROR        BFIN_IRQ(25)    /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERROR        BFIN_IRQ(26)    /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA           BFIN_IRQ(27)    /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERROR          BFIN_IRQ(28)    /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERROR          BFIN_IRQ(29)    /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERROR         BFIN_IRQ(30)    /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERROR         BFIN_IRQ(31)    /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERROR          BFIN_IRQ(32)    /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX           BFIN_IRQ(33)    /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_UART2_RX            BFIN_IRQ(33)    /* UART2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX           BFIN_IRQ(34)    /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_UART2_TX            BFIN_IRQ(34)    /* UART2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX           BFIN_IRQ(35)    /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_UART3_RX            BFIN_IRQ(35)    /* UART3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX           BFIN_IRQ(36)    /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_UART3_TX            BFIN_IRQ(36)    /* UART3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1               BFIN_IRQ(37)    /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2               BFIN_IRQ(38)    /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1                BFIN_IRQ(39)    /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2                BFIN_IRQ(40)    /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX            BFIN_IRQ(41)    /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX            BFIN_IRQ(42)    /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX            BFIN_IRQ(43)    /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX            BFIN_IRQ(44)    /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0                BFIN_IRQ(45)    /* TWI0 Interrupt */
-#define IRQ_TWI1                BFIN_IRQ(46)    /* TWI1 Interrupt */
-#define IRQ_CAN0_RX             BFIN_IRQ(47)    /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX             BFIN_IRQ(48)    /* CAN0 Transmit Interrupt */
-#define IRQ_MDMAS2              BFIN_IRQ(49)    /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS3              BFIN_IRQ(50)    /* MDMA Stream 3 Interrupt */
-#define IRQ_MXVR_ERROR          BFIN_IRQ(51)    /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_MSG            BFIN_IRQ(52)    /* MXVR Message Interrupt */
-#define IRQ_MXVR_PKT            BFIN_IRQ(53)    /* MXVR Packet Interrupt */
-#define IRQ_EPP1_ERROR          BFIN_IRQ(54)    /* EPPI1 Error Interrupt */
-#define IRQ_EPP2_ERROR          BFIN_IRQ(55)    /* EPPI2 Error Interrupt */
-#define IRQ_UART3_ERROR         BFIN_IRQ(56)    /* UART3 Status (Error) Interrupt */
-#define IRQ_HOST_ERROR          BFIN_IRQ(57)    /* HOST Status (Error) Interrupt */
-#define IRQ_PIXC_ERROR          BFIN_IRQ(59)    /* PIXC Status (Error) Interrupt */
-#define IRQ_NFC_ERROR           BFIN_IRQ(60)    /* NFC Error Interrupt */
-#define IRQ_ATAPI_ERROR         BFIN_IRQ(61)    /* ATAPI Error Interrupt */
-#define IRQ_CAN1_ERROR          BFIN_IRQ(62)    /* CAN1 Status (Error) Interrupt */
-#define IRQ_HS_DMA_ERROR        BFIN_IRQ(63)    /* Handshake DMA Status Interrupt */
-#define IRQ_PIXC_IN0            BFIN_IRQ(64)    /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN1            BFIN_IRQ(65)    /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_OUT            BFIN_IRQ(66)    /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_SDH                 BFIN_IRQ(67)    /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(68)    /* CNT Interrupt */
-#define IRQ_KEY                 BFIN_IRQ(69)    /* KEY Interrupt */
-#define IRQ_CAN1_RX             BFIN_IRQ(70)    /* CAN1 RX Interrupt */
-#define IRQ_CAN1_TX             BFIN_IRQ(71)    /* CAN1 TX Interrupt */
-#define IRQ_SDH_MASK0           BFIN_IRQ(72)    /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK1           BFIN_IRQ(73)    /* SDH Mask 1 Interrupt */
-#define IRQ_USB_INT0            BFIN_IRQ(75)    /* USB INT0 Interrupt */
-#define IRQ_USB_INT1            BFIN_IRQ(76)    /* USB INT1 Interrupt */
-#define IRQ_USB_INT2            BFIN_IRQ(77)    /* USB INT2 Interrupt */
-#define IRQ_USB_DMA             BFIN_IRQ(78)    /* USB DMA Interrupt */
-#define IRQ_OPTSEC              BFIN_IRQ(79)    /* OTPSEC Interrupt */
-#define IRQ_TIMER0              BFIN_IRQ(86)    /* Timer 0 Interrupt */
-#define IRQ_TIMER1              BFIN_IRQ(87)    /* Timer 1 Interrupt */
-#define IRQ_TIMER2              BFIN_IRQ(88)    /* Timer 2 Interrupt */
-#define IRQ_TIMER3              BFIN_IRQ(89)    /* Timer 3 Interrupt */
-#define IRQ_TIMER4              BFIN_IRQ(90)    /* Timer 4 Interrupt */
-#define IRQ_TIMER5              BFIN_IRQ(91)    /* Timer 5 Interrupt */
-#define IRQ_TIMER6              BFIN_IRQ(92)    /* Timer 6 Interrupt */
-#define IRQ_TIMER7              BFIN_IRQ(93)    /* Timer 7 Interrupt */
-#define IRQ_PINT2               BFIN_IRQ(94)    /* PINT2 Interrupt */
-#define IRQ_PINT3               BFIN_IRQ(95)    /* PINT3 Interrupt */
-
-#define SYS_IRQS                IRQ_PINT3
-
-#define BFIN_PA_IRQ(x)          ((x) + SYS_IRQS + 1)
-#define IRQ_PA0                 BFIN_PA_IRQ(0)
-#define IRQ_PA1                 BFIN_PA_IRQ(1)
-#define IRQ_PA2                 BFIN_PA_IRQ(2)
-#define IRQ_PA3                 BFIN_PA_IRQ(3)
-#define IRQ_PA4                 BFIN_PA_IRQ(4)
-#define IRQ_PA5                 BFIN_PA_IRQ(5)
-#define IRQ_PA6                 BFIN_PA_IRQ(6)
-#define IRQ_PA7                 BFIN_PA_IRQ(7)
-#define IRQ_PA8                 BFIN_PA_IRQ(8)
-#define IRQ_PA9                 BFIN_PA_IRQ(9)
-#define IRQ_PA10                BFIN_PA_IRQ(10)
-#define IRQ_PA11                BFIN_PA_IRQ(11)
-#define IRQ_PA12                BFIN_PA_IRQ(12)
-#define IRQ_PA13                BFIN_PA_IRQ(13)
-#define IRQ_PA14                BFIN_PA_IRQ(14)
-#define IRQ_PA15                BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x)          ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0                 BFIN_PB_IRQ(0)
-#define IRQ_PB1                 BFIN_PB_IRQ(1)
-#define IRQ_PB2                 BFIN_PB_IRQ(2)
-#define IRQ_PB3                 BFIN_PB_IRQ(3)
-#define IRQ_PB4                 BFIN_PB_IRQ(4)
-#define IRQ_PB5                 BFIN_PB_IRQ(5)
-#define IRQ_PB6                 BFIN_PB_IRQ(6)
-#define IRQ_PB7                 BFIN_PB_IRQ(7)
-#define IRQ_PB8                 BFIN_PB_IRQ(8)
-#define IRQ_PB9                 BFIN_PB_IRQ(9)
-#define IRQ_PB10                BFIN_PB_IRQ(10)
-#define IRQ_PB11                BFIN_PB_IRQ(11)
-#define IRQ_PB12                BFIN_PB_IRQ(12)
-#define IRQ_PB13                BFIN_PB_IRQ(13)
-#define IRQ_PB14                BFIN_PB_IRQ(14)
-#define IRQ_PB15                BFIN_PB_IRQ(15)         /* N/A */
-
-#define BFIN_PC_IRQ(x)          ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0                 BFIN_PC_IRQ(0)
-#define IRQ_PC1                 BFIN_PC_IRQ(1)
-#define IRQ_PC2                 BFIN_PC_IRQ(2)
-#define IRQ_PC3                 BFIN_PC_IRQ(3)
-#define IRQ_PC4                 BFIN_PC_IRQ(4)
-#define IRQ_PC5                 BFIN_PC_IRQ(5)
-#define IRQ_PC6                 BFIN_PC_IRQ(6)
-#define IRQ_PC7                 BFIN_PC_IRQ(7)
-#define IRQ_PC8                 BFIN_PC_IRQ(8)
-#define IRQ_PC9                 BFIN_PC_IRQ(9)
-#define IRQ_PC10                BFIN_PC_IRQ(10)
-#define IRQ_PC11                BFIN_PC_IRQ(11)
-#define IRQ_PC12                BFIN_PC_IRQ(12)
-#define IRQ_PC13                BFIN_PC_IRQ(13)
-#define IRQ_PC14                BFIN_PC_IRQ(14)         /* N/A */
-#define IRQ_PC15                BFIN_PC_IRQ(15)         /* N/A */
-
-#define BFIN_PD_IRQ(x)          ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0                 BFIN_PD_IRQ(0)
-#define IRQ_PD1                 BFIN_PD_IRQ(1)
-#define IRQ_PD2                 BFIN_PD_IRQ(2)
-#define IRQ_PD3                 BFIN_PD_IRQ(3)
-#define IRQ_PD4                 BFIN_PD_IRQ(4)
-#define IRQ_PD5                 BFIN_PD_IRQ(5)
-#define IRQ_PD6                 BFIN_PD_IRQ(6)
-#define IRQ_PD7                 BFIN_PD_IRQ(7)
-#define IRQ_PD8                 BFIN_PD_IRQ(8)
-#define IRQ_PD9                 BFIN_PD_IRQ(9)
-#define IRQ_PD10                BFIN_PD_IRQ(10)
-#define IRQ_PD11                BFIN_PD_IRQ(11)
-#define IRQ_PD12                BFIN_PD_IRQ(12)
-#define IRQ_PD13                BFIN_PD_IRQ(13)
-#define IRQ_PD14                BFIN_PD_IRQ(14)
-#define IRQ_PD15                BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x)          ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0                 BFIN_PE_IRQ(0)
-#define IRQ_PE1                 BFIN_PE_IRQ(1)
-#define IRQ_PE2                 BFIN_PE_IRQ(2)
-#define IRQ_PE3                 BFIN_PE_IRQ(3)
-#define IRQ_PE4                 BFIN_PE_IRQ(4)
-#define IRQ_PE5                 BFIN_PE_IRQ(5)
-#define IRQ_PE6                 BFIN_PE_IRQ(6)
-#define IRQ_PE7                 BFIN_PE_IRQ(7)
-#define IRQ_PE8                 BFIN_PE_IRQ(8)
-#define IRQ_PE9                 BFIN_PE_IRQ(9)
-#define IRQ_PE10                BFIN_PE_IRQ(10)
-#define IRQ_PE11                BFIN_PE_IRQ(11)
-#define IRQ_PE12                BFIN_PE_IRQ(12)
-#define IRQ_PE13                BFIN_PE_IRQ(13)
-#define IRQ_PE14                BFIN_PE_IRQ(14)
-#define IRQ_PE15                BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x)          ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0                 BFIN_PF_IRQ(0)
-#define IRQ_PF1                 BFIN_PF_IRQ(1)
-#define IRQ_PF2                 BFIN_PF_IRQ(2)
-#define IRQ_PF3                 BFIN_PF_IRQ(3)
-#define IRQ_PF4                 BFIN_PF_IRQ(4)
-#define IRQ_PF5                 BFIN_PF_IRQ(5)
-#define IRQ_PF6                 BFIN_PF_IRQ(6)
-#define IRQ_PF7                 BFIN_PF_IRQ(7)
-#define IRQ_PF8                 BFIN_PF_IRQ(8)
-#define IRQ_PF9                 BFIN_PF_IRQ(9)
-#define IRQ_PF10                BFIN_PF_IRQ(10)
-#define IRQ_PF11                BFIN_PF_IRQ(11)
-#define IRQ_PF12                BFIN_PF_IRQ(12)
-#define IRQ_PF13                BFIN_PF_IRQ(13)
-#define IRQ_PF14                BFIN_PF_IRQ(14)
-#define IRQ_PF15                BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x)          ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0                 BFIN_PG_IRQ(0)
-#define IRQ_PG1                 BFIN_PG_IRQ(1)
-#define IRQ_PG2                 BFIN_PG_IRQ(2)
-#define IRQ_PG3                 BFIN_PG_IRQ(3)
-#define IRQ_PG4                 BFIN_PG_IRQ(4)
-#define IRQ_PG5                 BFIN_PG_IRQ(5)
-#define IRQ_PG6                 BFIN_PG_IRQ(6)
-#define IRQ_PG7                 BFIN_PG_IRQ(7)
-#define IRQ_PG8                 BFIN_PG_IRQ(8)
-#define IRQ_PG9                 BFIN_PG_IRQ(9)
-#define IRQ_PG10                BFIN_PG_IRQ(10)
-#define IRQ_PG11                BFIN_PG_IRQ(11)
-#define IRQ_PG12                BFIN_PG_IRQ(12)
-#define IRQ_PG13                BFIN_PG_IRQ(13)
-#define IRQ_PG14                BFIN_PG_IRQ(14)
-#define IRQ_PG15                BFIN_PG_IRQ(15)
-
-#define BFIN_PH_IRQ(x)          ((x) + IRQ_PG15 + 1)
-#define IRQ_PH0                 BFIN_PH_IRQ(0)
-#define IRQ_PH1                 BFIN_PH_IRQ(1)
-#define IRQ_PH2                 BFIN_PH_IRQ(2)
-#define IRQ_PH3                 BFIN_PH_IRQ(3)
-#define IRQ_PH4                 BFIN_PH_IRQ(4)
-#define IRQ_PH5                 BFIN_PH_IRQ(5)
-#define IRQ_PH6                 BFIN_PH_IRQ(6)
-#define IRQ_PH7                 BFIN_PH_IRQ(7)
-#define IRQ_PH8                 BFIN_PH_IRQ(8)
-#define IRQ_PH9                 BFIN_PH_IRQ(9)
-#define IRQ_PH10                BFIN_PH_IRQ(10)
-#define IRQ_PH11                BFIN_PH_IRQ(11)
-#define IRQ_PH12                BFIN_PH_IRQ(12)
-#define IRQ_PH13                BFIN_PH_IRQ(13)
-#define IRQ_PH14                BFIN_PH_IRQ(14)         /* N/A */
-#define IRQ_PH15                BFIN_PH_IRQ(15)         /* N/A */
-
-#define BFIN_PI_IRQ(x)          ((x) + IRQ_PH15 + 1)
-#define IRQ_PI0                 BFIN_PI_IRQ(0)
-#define IRQ_PI1                 BFIN_PI_IRQ(1)
-#define IRQ_PI2                 BFIN_PI_IRQ(2)
-#define IRQ_PI3                 BFIN_PI_IRQ(3)
-#define IRQ_PI4                 BFIN_PI_IRQ(4)
-#define IRQ_PI5                 BFIN_PI_IRQ(5)
-#define IRQ_PI6                 BFIN_PI_IRQ(6)
-#define IRQ_PI7                 BFIN_PI_IRQ(7)
-#define IRQ_PI8                 BFIN_PI_IRQ(8)
-#define IRQ_PI9                 BFIN_PI_IRQ(9)
-#define IRQ_PI10                BFIN_PI_IRQ(10)
-#define IRQ_PI11                BFIN_PI_IRQ(11)
-#define IRQ_PI12                BFIN_PI_IRQ(12)
-#define IRQ_PI13                BFIN_PI_IRQ(13)
-#define IRQ_PI14                BFIN_PI_IRQ(14)
-#define IRQ_PI15                BFIN_PI_IRQ(15)
-
-#define BFIN_PJ_IRQ(x)          ((x) + IRQ_PI15 + 1)
-#define IRQ_PJ0                 BFIN_PJ_IRQ(0)
-#define IRQ_PJ1                 BFIN_PJ_IRQ(1)
-#define IRQ_PJ2                 BFIN_PJ_IRQ(2)
-#define IRQ_PJ3                 BFIN_PJ_IRQ(3)
-#define IRQ_PJ4                 BFIN_PJ_IRQ(4)
-#define IRQ_PJ5                 BFIN_PJ_IRQ(5)
-#define IRQ_PJ6                 BFIN_PJ_IRQ(6)
-#define IRQ_PJ7                 BFIN_PJ_IRQ(7)
-#define IRQ_PJ8                 BFIN_PJ_IRQ(8)
-#define IRQ_PJ9                 BFIN_PJ_IRQ(9)
-#define IRQ_PJ10                BFIN_PJ_IRQ(10)
-#define IRQ_PJ11                BFIN_PJ_IRQ(11)
-#define IRQ_PJ12                BFIN_PJ_IRQ(12)
-#define IRQ_PJ13                BFIN_PJ_IRQ(13)
-#define IRQ_PJ14                BFIN_PJ_IRQ(14)         /* N/A */
-#define IRQ_PJ15                BFIN_PJ_IRQ(15)         /* N/A */
-
-#define GPIO_IRQ_BASE   IRQ_PA0
-
-#define NR_IRQS     (IRQ_PJ15+1)
-
-/* For compatibility reasons with existing code */
-
-#define IRQ_DMAC0_ERR           IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR           IRQ_EPPI0_ERROR
-#define IRQ_SPORT0_ERR          IRQ_SPORT0_ERROR
-#define IRQ_SPORT1_ERR          IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR            IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR           IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR           IRQ_DMAC1_ERROR
-#define IRQ_SPORT2_ERR          IRQ_SPORT2_ERROR
-#define IRQ_SPORT3_ERR          IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR            IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR            IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR           IRQ_UART1_ERROR
-#define IRQ_UART2_ERR           IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR            IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR            IRQ_MXVR_ERROR
-#define IRQ_EPP1_ERR            IRQ_EPP1_ERROR
-#define IRQ_EPP2_ERR            IRQ_EPP2_ERROR
-#define IRQ_UART3_ERR           IRQ_UART3_ERROR
-#define IRQ_HOST_ERR            IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR            IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR             IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR           IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR            IRQ_CAN1_ERROR
-#define IRQ_HS_DMA_ERR          IRQ_HS_DMA_ERROR
-
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS      0
-#define IRQ_DMAC0_ERR_POS       4
-#define IRQ_EPPI0_ERR_POS       8
-#define IRQ_SPORT0_ERR_POS      12
-#define IRQ_SPORT1_ERR_POS      16
-#define IRQ_SPI0_ERR_POS        20
-#define IRQ_UART0_ERR_POS       24
-#define IRQ_RTC_POS             28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_EPPI0_POS           0
-#define IRQ_SPORT0_RX_POS       4
-#define IRQ_SPORT0_TX_POS       8
-#define IRQ_SPORT1_RX_POS       12
-#define IRQ_SPORT1_TX_POS       16
-#define IRQ_SPI0_POS            20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER8_POS          0
-#define IRQ_TIMER9_POS          4
-#define IRQ_TIMER10_POS         8
-#define IRQ_PINT0_POS           12
-#define IRQ_PINT1_POS           16
-#define IRQ_MDMAS0_POS          20
-#define IRQ_MDMAS1_POS          24
-#define IRQ_WATCH_POS           28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMAC1_ERR_POS       0
-#define IRQ_SPORT2_ERR_POS      4
-#define IRQ_SPORT3_ERR_POS      8
-#define IRQ_MXVR_DATA_POS       12
-#define IRQ_SPI1_ERR_POS        16
-#define IRQ_SPI2_ERR_POS        20
-#define IRQ_UART1_ERR_POS       24
-#define IRQ_UART2_ERR_POS       28
-
-/* IAR4 BIT FILEDS */
-#define IRQ_CAN0_ERR_POS        0
-#define IRQ_SPORT2_RX_POS       4
-#define IRQ_UART2_RX_POS        4
-#define IRQ_SPORT2_TX_POS       8
-#define IRQ_UART2_TX_POS        8
-#define IRQ_SPORT3_RX_POS       12
-#define IRQ_UART3_RX_POS        12
-#define IRQ_SPORT3_TX_POS       16
-#define IRQ_UART3_TX_POS        16
-#define IRQ_EPPI1_POS           20
-#define IRQ_EPPI2_POS           24
-#define IRQ_SPI1_POS            28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS            0
-#define IRQ_UART1_RX_POS        4
-#define IRQ_UART1_TX_POS        8
-#define IRQ_ATAPI_RX_POS        12
-#define IRQ_ATAPI_TX_POS        16
-#define IRQ_TWI0_POS            20
-#define IRQ_TWI1_POS            24
-#define IRQ_CAN0_RX_POS         28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN0_TX_POS         0
-#define IRQ_MDMAS2_POS          4
-#define IRQ_MDMAS3_POS          8
-#define IRQ_MXVR_ERR_POS        12
-#define IRQ_MXVR_MSG_POS        16
-#define IRQ_MXVR_PKT_POS        20
-#define IRQ_EPPI1_ERR_POS       24
-#define IRQ_EPPI2_ERR_POS       28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_UART3_ERR_POS       0
-#define IRQ_HOST_ERR_POS        4
-#define IRQ_PIXC_ERR_POS        12
-#define IRQ_NFC_ERR_POS         16
-#define IRQ_ATAPI_ERR_POS       20
-#define IRQ_CAN1_ERR_POS        24
-#define IRQ_HS_DMA_ERR_POS      28
-
-/* IAR8 BIT FIELDS */
-#define IRQ_PIXC_IN0_POS        0
-#define IRQ_PIXC_IN1_POS        4
-#define IRQ_PIXC_OUT_POS        8
-#define IRQ_SDH_POS             12
-#define IRQ_CNT_POS             16
-#define IRQ_KEY_POS             20
-#define IRQ_CAN1_RX_POS         24
-#define IRQ_CAN1_TX_POS         28
-
-/* IAR9 BIT FIELDS */
-#define IRQ_SDH_MASK0_POS       0
-#define IRQ_SDH_MASK1_POS       4
-#define IRQ_USB_INT0_POS        12
-#define IRQ_USB_INT1_POS        16
-#define IRQ_USB_INT2_POS        20
-#define IRQ_USB_DMA_POS         24
-#define IRQ_OTPSEC_POS          28
-
-/* IAR10 BIT FIELDS */
-#define IRQ_TIMER0_POS          24
-#define IRQ_TIMER1_POS          28
-
-/* IAR11 BIT FIELDS */
-#define IRQ_TIMER2_POS          0
-#define IRQ_TIMER3_POS          4
-#define IRQ_TIMER4_POS          8
-#define IRQ_TIMER5_POS          12
-#define IRQ_TIMER6_POS          16
-#define IRQ_TIMER7_POS          20
-#define IRQ_PINT2_POS           24
-#define IRQ_PINT3_POS           28
-
-#endif /* _BF548_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
deleted file mode 100644
index ab0b863eee66..000000000000
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x)   (1000*1000*1000/x)
-
-#if (CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR        DDR_TWTR(1)
-#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR        DDR_TWTR(2)
-#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRCD        DDR_TRCD(3)
-#define DDR_tWTR        DDR_TWTR(2)
-#define DDR_tWR         DDR_TWR(2)
-#define DDR_tMRD        DDR_TMRD(2)
-#define DDR_tRP         DDR_TRP(3)
-#define DDR_tRAS        DDR_TRAS(7)
-#define DDR_tRC         DDR_TRC(10)
-#define DDR_tRFC        DDR_TRFC(12)
-#define DDR_tREFI       DDR_TREFI(1288)
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define        DDR_CL          CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-
-#define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
-                        | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2     DDR_CL
-
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
deleted file mode 100644
index f99f47bc3a07..000000000000
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf548/mem_map.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
- * rev:
- *
- * modified:
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MEM_MAP_548_H_
-#define _MEM_MAP_548_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x1000
-
-/* L1 Instruction ROM */
-
-#define L1_ROM_START            0xFFA14000
-#define L1_ROM_LENGTH           0x10000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#if !defined(CONFIG_BF542)
-# define L2_START          0xFEB00000
-# if defined(CONFIG_BF544)
-#  define L2_LENGTH        0x10000
-# else
-#  define L2_LENGTH        0x20000
-# endif
-#endif
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
deleted file mode 100644
index 8177a567dcdb..000000000000
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ /dev/null
@@ -1,286 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_SPORT2_TFS    (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK  (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS    (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC  (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI  (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK  (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS    (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK  (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS    (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC  (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI  (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK  (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5  (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6  (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7  (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL      (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA      (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS     (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS     (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX      (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX      (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX      (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX      (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS       (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1    (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2    (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3    (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK      (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI     (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO     (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0  (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1  (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2  (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3  (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK        (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD        (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2       (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3       (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4       (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5       (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6       (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7       (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10      (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11      (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14      (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15      (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2       (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5       (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6       (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7       (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2       (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5       (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6       (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7       (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18      (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19      (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20      (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21      (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0      (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1      (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3      (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1      (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2      (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS     (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS     (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK      (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1      (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2      (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL      (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA      (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6      (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6      (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5      (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5      (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4      (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4      (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_ATAPI_D0A     (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_ATAPI_D1A     (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_ATAPI_D2A     (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_ATAPI_D3A     (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_ATAPI_D4A     (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_ATAPI_D5A     (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_ATAPI_D6A     (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_ATAPI_D7A     (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_ATAPI_D8A     (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_ATAPI_D9A     (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_ATAPI_D10A    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_ATAPI_D11A    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_ATAPI_D12A    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_ATAPI_D13A    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_ATAPI_D14A    (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_ATAPI_D15A    (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16      (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17      (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2    (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3    (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX       (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX       (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX       (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX       (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_ATAPI_A0A     (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-#define P_ATAPI_A1A     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_ATAPI_A2A     (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_HOST_CE       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB        (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET   (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR     (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK      (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX   (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB        (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8  (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9  (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK       (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT     (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE       (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB       (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR    (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW    (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0     (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1     (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK   (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ   (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ   (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY   (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR        (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG        (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH       (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0       (P_DONTCARE)
-#define P_NAND_D1       (P_DONTCARE)
-#define P_NAND_D2       (P_DONTCARE)
-#define P_NAND_D3       (P_DONTCARE)
-#define P_NAND_D4       (P_DONTCARE)
-#define P_NAND_D5       (P_DONTCARE)
-#define P_NAND_D6       (P_DONTCARE)
-#define P_NAND_D7       (P_DONTCARE)
-#define P_NAND_WE       (P_DONTCARE)
-#define P_NAND_RE       (P_DONTCARE)
-#define P_NAND_CLE      (P_DONTCARE)
-#define P_NAND_ALE      (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
deleted file mode 100644
index 5c5d7d7d695f..000000000000
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf561/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Testset instructions restricted to 32-bit aligned memory locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Erroneous exception when enabling cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Signbits instruction not functional under certain conditions */
-#define ANOMALY_05000127 (1)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* IMDMA S1/D1 channel may stall */
-#define ANOMALY_05000149 (1)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT transmit data is not gated by external frame sync in certain conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning Serial Ports on with External Frame Syncs */
-#define ANOMALY_05000167 (1)
-/* SDRAM auto-refresh and subsequent Power Ups */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB page miss can result in lost write-through cache data writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM code modifies SICA_IWRx wakeup registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI resets the PPI configuration registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* IMDMA does not operate to full speed for 600MHz and higher devices */
-#define ANOMALY_05000182 (1)
-/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* PPI TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI not functional at core voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses When Stalled by Preceding Memory Read */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific sequence that can cause DMA error or DMA stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT data transmit lines are incorrectly driven in multichannel mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET operation forces stall on the other core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA destination IRQ status must be read prior to using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA may corrupt data under certain conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data cache write back to external synchronous memory may be lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* A read will receive incorrect data under certain conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted After SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
deleted file mode 100644
index 3ef9e5f36136..000000000000
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/bf561.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF561_H__
-#define __MACH_BF561_H__
-
-#define SUPPORTED_REVID         0x3
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR            0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************
- * Blackfin Cache setup
- */
-
-
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS */
-#define PLL_WAKEUP_BIT          0xFFFFFFFF
-#define DMA1_ERROR_BIT          0xFFFFFF0F
-#define DMA2_ERROR_BIT          0xFFFFF0FF
-#define IMDMA_ERROR_BIT         0xFFFF0FFF
-#define PPI1_ERROR_BIT          0xFFF0FFFF
-#define PPI2_ERROR_BIT          0xFF0FFFFF
-#define SPORT0_ERROR_BIT        0xF0FFFFFF
-#define SPORT1_ERROR_BIT        0x0FFFFFFF
-/* IAR1 BIT FIELDS */
-#define SPI_ERROR_BIT           0xFFFFFFFF
-#define UART_ERROR_BIT          0xFFFFFF0F
-#define RESERVED_ERROR_BIT      0xFFFFF0FF
-#define DMA1_0_BIT              0xFFFF0FFF
-#define DMA1_1_BIT              0xFFF0FFFF
-#define DMA1_2_BIT              0xFF0FFFFF
-#define DMA1_3_BIT              0xF0FFFFFF
-#define DMA1_4_BIT              0x0FFFFFFF
-/* IAR2 BIT FIELDS */
-#define DMA1_5_BIT              0xFFFFFFFF
-#define DMA1_6_BIT              0xFFFFFF0F
-#define DMA1_7_BIT              0xFFFFF0FF
-#define DMA1_8_BIT              0xFFFF0FFF
-#define DMA1_9_BIT              0xFFF0FFFF
-#define DMA1_10_BIT             0xFF0FFFFF
-#define DMA1_11_BIT             0xF0FFFFFF
-#define DMA2_0_BIT              0x0FFFFFFF
-/* IAR3 BIT FIELDS */
-#define DMA2_1_BIT              0xFFFFFFFF
-#define DMA2_2_BIT              0xFFFFFF0F
-#define DMA2_3_BIT              0xFFFFF0FF
-#define DMA2_4_BIT              0xFFFF0FFF
-#define DMA2_5_BIT              0xFFF0FFFF
-#define DMA2_6_BIT              0xFF0FFFFF
-#define DMA2_7_BIT              0xF0FFFFFF
-#define DMA2_8_BIT              0x0FFFFFFF
-/* IAR4 BIT FIELDS */
-#define DMA2_9_BIT              0xFFFFFFFF
-#define DMA2_10_BIT             0xFFFFFF0F
-#define DMA2_11_BIT             0xFFFFF0FF
-#define TIMER0_BIT              0xFFFF0FFF
-#define TIMER1_BIT              0xFFF0FFFF
-#define TIMER2_BIT              0xFF0FFFFF
-#define TIMER3_BIT              0xF0FFFFFF
-#define TIMER4_BIT              0x0FFFFFFF
-/* IAR5 BIT FIELDS */
-#define TIMER5_BIT              0xFFFFFFFF
-#define TIMER6_BIT              0xFFFFFF0F
-#define TIMER7_BIT              0xFFFFF0FF
-#define TIMER8_BIT              0xFFFF0FFF
-#define TIMER9_BIT              0xFFF0FFFF
-#define TIMER10_BIT             0xFF0FFFFF
-#define TIMER11_BIT             0xF0FFFFFF
-#define PROG0_INTA_BIT          0x0FFFFFFF
-/* IAR6 BIT FIELDS */
-#define PROG0_INTB_BIT          0xFFFFFFFF
-#define PROG1_INTA_BIT          0xFFFFFF0F
-#define PROG1_INTB_BIT          0xFFFFF0FF
-#define PROG2_INTA_BIT          0xFFFF0FFF
-#define PROG2_INTB_BIT          0xFFF0FFFF
-#define DMA1_WRRD0_BIT          0xFF0FFFFF
-#define DMA1_WRRD1_BIT          0xF0FFFFFF
-#define DMA2_WRRD0_BIT          0x0FFFFFFF
-/* IAR7 BIT FIELDS */
-#define DMA2_WRRD1_BIT          0xFFFFFFFF
-#define IMDMA_WRRD0_BIT         0xFFFFFF0F
-#define IMDMA_WRRD1_BIT         0xFFFFF0FF
-#define WATCH_BIT               0xFFFF0FFF
-#define RESERVED_1_BIT          0xFFF0FFFF
-#define RESERVED_2_BIT          0xFF0FFFFF
-#define SUPPLE_0_BIT            0xF0FFFFFF
-#define SUPPLE_1_BIT            0x0FFFFFFF
-
-/* Miscellaneous Values */
-
-/****************************** EBIU Settings ********************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#if defined(CONFIG_C_AMBEN_ALL)
-#define V_AMBEN AMBEN_ALL
-#elif defined(CONFIG_C_AMBEN)
-#define V_AMBEN 0x0
-#elif defined(CONFIG_C_AMBEN_B0)
-#define V_AMBEN AMBEN_B0
-#elif defined(CONFIG_C_AMBEN_B0_B1)
-#define V_AMBEN AMBEN_B0_B1
-#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#ifdef CONFIG_C_B0PEN
-#define V_B0PEN 0x10
-#else
-#define V_B0PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B1PEN
-#define V_B1PEN 0x20
-#else
-#define V_B1PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B2PEN
-#define V_B2PEN 0x40
-#else
-#define V_B2PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B3PEN
-#define V_B3PEN 0x80
-#else
-#define V_B3PEN 0x00
-#endif
-
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-
-#ifdef CONFIG_BF561
-#define CPU "BF561"
-#define CPUID 0x027bb000
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF561_H__  */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
deleted file mode 100644
index 8aa02780e642..000000000000
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-# define CONFIG_SERIAL_BFIN_CTSRTS
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000230
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART_TX,
-        CH_UART_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        }
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-int nr_ports = BFIN_UART_NR_PORTS;
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/include/asm-blackfin/mach-bf561/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        CH_UART_RX,
-        CH_UART_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
deleted file mode 100644
index 0ea8666e6764..000000000000
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF561_FAMILY
-
-#include "bf561.h"
-#include "mem_map.h"
-#include "defBF561.h"
-#include "anomaly.h"
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF561.h"
-#endif
-
-#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
-#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
-#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
-
-#define SIC_IWR0 SICA_IWR0
-#define SIC_IWR1 SICA_IWR1
-#define SIC_IAR0 SICA_IAR0
-#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
-#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
-#define bfin_write_SIC_IWR0   bfin_write_SICA_IWR0
-#define bfin_write_SIC_IWR1   bfin_write_SICA_IWR1
-
-#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
-#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
-#define bfin_read_SIC_IWR0   bfin_read_SICA_IWR0
-#define bfin_read_SIC_IWR1   bfin_read_SICA_IWR1
-#define bfin_read_SIC_ISR0   bfin_read_SICA_ISR0
-#define bfin_read_SIC_ISR1   bfin_read_SICA_ISR1
-
-#define bfin_read_SIC_IMASK(x)          bfin_read32(SICA_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val)    bfin_write32((SICA_IMASK0 + (x << 2)), val)
-#define bfin_read_SIC_ISR(x)            bfin_read32(SICA_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val)      bfin_write32((SICA_ISR0 + (x << 2)), val)
-
-#define BFIN_UART_NR_PORTS      1
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-#endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
deleted file mode 100644
index b07ffccd66dd..000000000000
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ /dev/null
@@ -1,1579 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/cdefBF561.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-#include <asm/blackfin.h>
-
-/* include all Core registers and bit definitions */
-#include "defBF561.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-#include <asm/system.h>
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define bfin_read_SWRST()                    bfin_read_SICA_SWRST()
-#define bfin_write_SWRST(val)                bfin_write_SICA_SWRST(val)
-#define bfin_read_SYSCR()                    bfin_read_SICA_SYSCR()
-#define bfin_write_SYSCR(val)                bfin_write_SICA_SYSCR(val)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define bfin_read_SICA_SWRST()               bfin_read16(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val)           bfin_write16(SICA_SWRST,val)
-#define bfin_read_SICA_SYSCR()               bfin_read16(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val)           bfin_write16(SICA_SYSCR,val)
-#define bfin_read_SICA_RVECT()               bfin_read16(SICA_RVECT)
-#define bfin_write_SICA_RVECT(val)           bfin_write16(SICA_RVECT,val)
-#define bfin_read_SICA_IMASK()               bfin_read32(SICA_IMASK)
-#define bfin_write_SICA_IMASK(val)           bfin_write32(SICA_IMASK,val)
-#define bfin_read_SICA_IMASK0()              bfin_read32(SICA_IMASK0)
-#define bfin_write_SICA_IMASK0(val)          bfin_write32(SICA_IMASK0,val)
-#define bfin_read_SICA_IMASK1()              bfin_read32(SICA_IMASK1)
-#define bfin_write_SICA_IMASK1(val)          bfin_write32(SICA_IMASK1,val)
-#define bfin_read_SICA_IAR0()                bfin_read32(SICA_IAR0)
-#define bfin_write_SICA_IAR0(val)            bfin_write32(SICA_IAR0,val)
-#define bfin_read_SICA_IAR1()                bfin_read32(SICA_IAR1)
-#define bfin_write_SICA_IAR1(val)            bfin_write32(SICA_IAR1,val)
-#define bfin_read_SICA_IAR2()                bfin_read32(SICA_IAR2)
-#define bfin_write_SICA_IAR2(val)            bfin_write32(SICA_IAR2,val)
-#define bfin_read_SICA_IAR3()                bfin_read32(SICA_IAR3)
-#define bfin_write_SICA_IAR3(val)            bfin_write32(SICA_IAR3,val)
-#define bfin_read_SICA_IAR4()                bfin_read32(SICA_IAR4)
-#define bfin_write_SICA_IAR4(val)            bfin_write32(SICA_IAR4,val)
-#define bfin_read_SICA_IAR5()                bfin_read32(SICA_IAR5)
-#define bfin_write_SICA_IAR5(val)            bfin_write32(SICA_IAR5,val)
-#define bfin_read_SICA_IAR6()                bfin_read32(SICA_IAR6)
-#define bfin_write_SICA_IAR6(val)            bfin_write32(SICA_IAR6,val)
-#define bfin_read_SICA_IAR7()                bfin_read32(SICA_IAR7)
-#define bfin_write_SICA_IAR7(val)            bfin_write32(SICA_IAR7,val)
-#define bfin_read_SICA_ISR0()                bfin_read32(SICA_ISR0)
-#define bfin_write_SICA_ISR0(val)            bfin_write32(SICA_ISR0,val)
-#define bfin_read_SICA_ISR1()                bfin_read32(SICA_ISR1)
-#define bfin_write_SICA_ISR1(val)            bfin_write32(SICA_ISR1,val)
-#define bfin_read_SICA_IWR0()                bfin_read32(SICA_IWR0)
-#define bfin_write_SICA_IWR0(val)            bfin_write32(SICA_IWR0,val)
-#define bfin_read_SICA_IWR1()                bfin_read32(SICA_IWR1)
-#define bfin_write_SICA_IWR1(val)            bfin_write32(SICA_IWR1,val)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define bfin_read_SICB_SWRST()               bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val)           bfin_write16(SICB_SWRST,val)
-#define bfin_read_SICB_SYSCR()               bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val)           bfin_write16(SICB_SYSCR,val)
-#define bfin_read_SICB_RVECT()               bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val)           bfin_write16(SICB_RVECT,val)
-#define bfin_read_SICB_IMASK0()              bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val)          bfin_write32(SICB_IMASK0,val)
-#define bfin_read_SICB_IMASK1()              bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val)          bfin_write32(SICB_IMASK1,val)
-#define bfin_read_SICB_IAR0()                bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val)            bfin_write32(SICB_IAR0,val)
-#define bfin_read_SICB_IAR1()                bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val)            bfin_write32(SICB_IAR1,val)
-#define bfin_read_SICB_IAR2()                bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val)            bfin_write32(SICB_IAR2,val)
-#define bfin_read_SICB_IAR3()                bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val)            bfin_write32(SICB_IAR3,val)
-#define bfin_read_SICB_IAR4()                bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val)            bfin_write32(SICB_IAR4,val)
-#define bfin_read_SICB_IAR5()                bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val)            bfin_write32(SICB_IAR5,val)
-#define bfin_read_SICB_IAR6()                bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val)            bfin_write32(SICB_IAR6,val)
-#define bfin_read_SICB_IAR7()                bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val)            bfin_write32(SICB_IAR7,val)
-#define bfin_read_SICB_ISR0()                bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val)            bfin_write32(SICB_ISR0,val)
-#define bfin_read_SICB_ISR1()                bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val)            bfin_write32(SICB_ISR1,val)
-#define bfin_read_SICB_IWR0()                bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val)            bfin_write32(SICB_IWR0,val)
-#define bfin_read_SICB_IWR1()                bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val)            bfin_write32(SICB_IWR1,val)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define bfin_read_WDOGA_CTL()                bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val)            bfin_write16(WDOGA_CTL,val)
-#define bfin_read_WDOGA_CNT()                bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val)            bfin_write32(WDOGA_CNT,val)
-#define bfin_read_WDOGA_STAT()               bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val)           bfin_write32(WDOGA_STAT,val)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define bfin_read_WDOGB_CTL()                bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val)            bfin_write16(WDOGB_CTL,val)
-#define bfin_read_WDOGB_CNT()                bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val)            bfin_write32(WDOGB_CNT,val)
-#define bfin_read_WDOGB_STAT()               bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val)           bfin_write32(WDOGB_STAT,val)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
-#define bfin_read_UART_MSR()                 bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val)             bfin_write16(UART_MSR,val)
-#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
-#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
-#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
-#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
-#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
-#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define bfin_read_TMRS8_ENABLE()             bfin_read16(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val)         bfin_write16(TMRS8_ENABLE,val)
-#define bfin_read_TMRS8_DISABLE()            bfin_read16(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val)        bfin_write16(TMRS8_DISABLE,val)
-#define bfin_read_TMRS8_STATUS()             bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val)         bfin_write32(TMRS8_STATUS,val)
-#define bfin_read_TIMER8_CONFIG()            bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)        bfin_write16(TIMER8_CONFIG,val)
-#define bfin_read_TIMER8_COUNTER()           bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)       bfin_write32(TIMER8_COUNTER,val)
-#define bfin_read_TIMER8_PERIOD()            bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)        bfin_write32(TIMER8_PERIOD,val)
-#define bfin_read_TIMER8_WIDTH()             bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)         bfin_write32(TIMER8_WIDTH,val)
-#define bfin_read_TIMER9_CONFIG()            bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)        bfin_write16(TIMER9_CONFIG,val)
-#define bfin_read_TIMER9_COUNTER()           bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)       bfin_write32(TIMER9_COUNTER,val)
-#define bfin_read_TIMER9_PERIOD()            bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)        bfin_write32(TIMER9_PERIOD,val)
-#define bfin_read_TIMER9_WIDTH()             bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)         bfin_write32(TIMER9_WIDTH,val)
-#define bfin_read_TIMER10_CONFIG()           bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)       bfin_write16(TIMER10_CONFIG,val)
-#define bfin_read_TIMER10_COUNTER()          bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)      bfin_write32(TIMER10_COUNTER,val)
-#define bfin_read_TIMER10_PERIOD()           bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)       bfin_write32(TIMER10_PERIOD,val)
-#define bfin_read_TIMER10_WIDTH()            bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)        bfin_write32(TIMER10_WIDTH,val)
-#define bfin_read_TIMER11_CONFIG()           bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val)       bfin_write16(TIMER11_CONFIG,val)
-#define bfin_read_TIMER11_COUNTER()          bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val)      bfin_write32(TIMER11_COUNTER,val)
-#define bfin_read_TIMER11_PERIOD()           bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val)       bfin_write32(TIMER11_PERIOD,val)
-#define bfin_read_TIMER11_WIDTH()            bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val)        bfin_write32(TIMER11_WIDTH,val)
-#define bfin_read_TMRS4_ENABLE()             bfin_read16(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val)         bfin_write16(TMRS4_ENABLE,val)
-#define bfin_read_TMRS4_DISABLE()            bfin_read16(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val)        bfin_write16(TMRS4_DISABLE,val)
-#define bfin_read_TMRS4_STATUS()             bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val)         bfin_write32(TMRS4_STATUS,val)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define bfin_read_FIO0_FLAG_D()              bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val)          bfin_write16(FIO0_FLAG_D,val)
-#define bfin_read_FIO0_FLAG_C()              bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val)          bfin_write16(FIO0_FLAG_C,val)
-#define bfin_read_FIO0_FLAG_S()              bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val)          bfin_write16(FIO0_FLAG_S,val)
-#define bfin_read_FIO0_FLAG_T()              bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val)          bfin_write16(FIO0_FLAG_T,val)
-#define bfin_read_FIO0_MASKA_D()             bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val)         bfin_write16(FIO0_MASKA_D,val)
-#define bfin_read_FIO0_MASKA_C()             bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val)         bfin_write16(FIO0_MASKA_C,val)
-#define bfin_read_FIO0_MASKA_S()             bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val)         bfin_write16(FIO0_MASKA_S,val)
-#define bfin_read_FIO0_MASKA_T()             bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val)         bfin_write16(FIO0_MASKA_T,val)
-#define bfin_read_FIO0_MASKB_D()             bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val)         bfin_write16(FIO0_MASKB_D,val)
-#define bfin_read_FIO0_MASKB_C()             bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val)         bfin_write16(FIO0_MASKB_C,val)
-#define bfin_read_FIO0_MASKB_S()             bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val)         bfin_write16(FIO0_MASKB_S,val)
-#define bfin_read_FIO0_MASKB_T()             bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val)         bfin_write16(FIO0_MASKB_T,val)
-#define bfin_read_FIO0_DIR()                 bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val)             bfin_write16(FIO0_DIR,val)
-#define bfin_read_FIO0_POLAR()               bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val)           bfin_write16(FIO0_POLAR,val)
-#define bfin_read_FIO0_EDGE()                bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val)            bfin_write16(FIO0_EDGE,val)
-#define bfin_read_FIO0_BOTH()                bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val)            bfin_write16(FIO0_BOTH,val)
-#define bfin_read_FIO0_INEN()                bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val)            bfin_write16(FIO0_INEN,val)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define bfin_read_FIO1_FLAG_D()              bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val)          bfin_write16(FIO1_FLAG_D,val)
-#define bfin_read_FIO1_FLAG_C()              bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val)          bfin_write16(FIO1_FLAG_C,val)
-#define bfin_read_FIO1_FLAG_S()              bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val)          bfin_write16(FIO1_FLAG_S,val)
-#define bfin_read_FIO1_FLAG_T()              bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val)          bfin_write16(FIO1_FLAG_T,val)
-#define bfin_read_FIO1_MASKA_D()             bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val)         bfin_write16(FIO1_MASKA_D,val)
-#define bfin_read_FIO1_MASKA_C()             bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val)         bfin_write16(FIO1_MASKA_C,val)
-#define bfin_read_FIO1_MASKA_S()             bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val)         bfin_write16(FIO1_MASKA_S,val)
-#define bfin_read_FIO1_MASKA_T()             bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val)         bfin_write16(FIO1_MASKA_T,val)
-#define bfin_read_FIO1_MASKB_D()             bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val)         bfin_write16(FIO1_MASKB_D,val)
-#define bfin_read_FIO1_MASKB_C()             bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val)         bfin_write16(FIO1_MASKB_C,val)
-#define bfin_read_FIO1_MASKB_S()             bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val)         bfin_write16(FIO1_MASKB_S,val)
-#define bfin_read_FIO1_MASKB_T()             bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val)         bfin_write16(FIO1_MASKB_T,val)
-#define bfin_read_FIO1_DIR()                 bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val)             bfin_write16(FIO1_DIR,val)
-#define bfin_read_FIO1_POLAR()               bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val)           bfin_write16(FIO1_POLAR,val)
-#define bfin_read_FIO1_EDGE()                bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val)            bfin_write16(FIO1_EDGE,val)
-#define bfin_read_FIO1_BOTH()                bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val)            bfin_write16(FIO1_BOTH,val)
-#define bfin_read_FIO1_INEN()                bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val)            bfin_write16(FIO1_INEN,val)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define bfin_read_FIO2_FLAG_D()              bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val)          bfin_write16(FIO2_FLAG_D,val)
-#define bfin_read_FIO2_FLAG_C()              bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val)          bfin_write16(FIO2_FLAG_C,val)
-#define bfin_read_FIO2_FLAG_S()              bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val)          bfin_write16(FIO2_FLAG_S,val)
-#define bfin_read_FIO2_FLAG_T()              bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val)          bfin_write16(FIO2_FLAG_T,val)
-#define bfin_read_FIO2_MASKA_D()             bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val)         bfin_write16(FIO2_MASKA_D,val)
-#define bfin_read_FIO2_MASKA_C()             bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val)         bfin_write16(FIO2_MASKA_C,val)
-#define bfin_read_FIO2_MASKA_S()             bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val)         bfin_write16(FIO2_MASKA_S,val)
-#define bfin_read_FIO2_MASKA_T()             bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val)         bfin_write16(FIO2_MASKA_T,val)
-#define bfin_read_FIO2_MASKB_D()             bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val)         bfin_write16(FIO2_MASKB_D,val)
-#define bfin_read_FIO2_MASKB_C()             bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val)         bfin_write16(FIO2_MASKB_C,val)
-#define bfin_read_FIO2_MASKB_S()             bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val)         bfin_write16(FIO2_MASKB_S,val)
-#define bfin_read_FIO2_MASKB_T()             bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val)         bfin_write16(FIO2_MASKB_T,val)
-#define bfin_read_FIO2_DIR()                 bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val)             bfin_write16(FIO2_DIR,val)
-#define bfin_read_FIO2_POLAR()               bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val)           bfin_write16(FIO2_POLAR,val)
-#define bfin_read_FIO2_EDGE()                bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val)            bfin_write16(FIO2_EDGE,val)
-#define bfin_read_FIO2_BOTH()                bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val)            bfin_write16(FIO2_BOTH,val)
-#define bfin_read_FIO2_INEN()                bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val)            bfin_write16(FIO2_INEN,val)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL()              bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)          bfin_write32(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define bfin_read_PPI0_CONTROL()             bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val)         bfin_write16(PPI0_CONTROL,val)
-#define bfin_read_PPI0_STATUS()              bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val)          bfin_write16(PPI0_STATUS,val)
-#define bfin_clear_PPI0_STATUS()             bfin_read_PPI0_STATUS()
-#define bfin_read_PPI0_COUNT()               bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val)           bfin_write16(PPI0_COUNT,val)
-#define bfin_read_PPI0_DELAY()               bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val)           bfin_write16(PPI0_DELAY,val)
-#define bfin_read_PPI0_FRAME()               bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val)           bfin_write16(PPI0_FRAME,val)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define bfin_read_PPI1_CONTROL()             bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val)         bfin_write16(PPI1_CONTROL,val)
-#define bfin_read_PPI1_STATUS()              bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val)          bfin_write16(PPI1_STATUS,val)
-#define bfin_clear_PPI1_STATUS()             bfin_read_PPI1_STATUS()
-#define bfin_read_PPI1_COUNT()               bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val)           bfin_write16(PPI1_COUNT,val)
-#define bfin_read_PPI1_DELAY()               bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val)           bfin_write16(PPI1_DELAY,val)
-#define bfin_read_PPI1_FRAME()               bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val)           bfin_write16(PPI1_FRAME,val)
-/*DMA traffic control registers */
-#define bfin_read_DMA1_TC_PER()              bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)          bfin_write16(DMA1_TC_PER,val)
-#define bfin_read_DMA1_TC_CNT()              bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)          bfin_write16(DMA1_TC_CNT,val)
-#define bfin_read_DMA2_TC_PER()              bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val)          bfin_write16(DMA2_TC_PER,val)
-#define bfin_read_DMA2_TC_CNT()              bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val)          bfin_write16(DMA2_TC_CNT,val)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define bfin_read_DMA1_0_CONFIG()            bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val)        bfin_write16(DMA1_0_CONFIG,val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR()     bfin_read32(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_0_START_ADDR()        bfin_read32(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val)    bfin_write32(DMA1_0_START_ADDR,val)
-#define bfin_read_DMA1_0_X_COUNT()           bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val)       bfin_write16(DMA1_0_X_COUNT,val)
-#define bfin_read_DMA1_0_Y_COUNT()           bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val)       bfin_write16(DMA1_0_Y_COUNT,val)
-#define bfin_read_DMA1_0_X_MODIFY()          bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val)      bfin_write16(DMA1_0_X_MODIFY,val)
-#define bfin_read_DMA1_0_Y_MODIFY()          bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val)      bfin_write16(DMA1_0_Y_MODIFY,val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR()     bfin_read32(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_0_CURR_ADDR()         bfin_read32(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val)     bfin_write32(DMA1_0_CURR_ADDR,val)
-#define bfin_read_DMA1_0_CURR_X_COUNT()      bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val)  bfin_write16(DMA1_0_CURR_X_COUNT,val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT()      bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val)  bfin_write16(DMA1_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_0_IRQ_STATUS()        bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val)    bfin_write16(DMA1_0_IRQ_STATUS,val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP()    bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_1_CONFIG()            bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val)        bfin_write16(DMA1_1_CONFIG,val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR()     bfin_read32(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_1_START_ADDR()        bfin_read32(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val)    bfin_write32(DMA1_1_START_ADDR,val)
-#define bfin_read_DMA1_1_X_COUNT()           bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val)       bfin_write16(DMA1_1_X_COUNT,val)
-#define bfin_read_DMA1_1_Y_COUNT()           bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val)       bfin_write16(DMA1_1_Y_COUNT,val)
-#define bfin_read_DMA1_1_X_MODIFY()          bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val)      bfin_write16(DMA1_1_X_MODIFY,val)
-#define bfin_read_DMA1_1_Y_MODIFY()          bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val)      bfin_write16(DMA1_1_Y_MODIFY,val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR()     bfin_read32(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_1_CURR_ADDR()         bfin_read32(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val)     bfin_write32(DMA1_1_CURR_ADDR,val)
-#define bfin_read_DMA1_1_CURR_X_COUNT()      bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val)  bfin_write16(DMA1_1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT()      bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val)  bfin_write16(DMA1_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_1_IRQ_STATUS()        bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val)    bfin_write16(DMA1_1_IRQ_STATUS,val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP()    bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_2_CONFIG()            bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val)        bfin_write16(DMA1_2_CONFIG,val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR()     bfin_read32(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_2_START_ADDR()        bfin_read32(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val)    bfin_write32(DMA1_2_START_ADDR,val)
-#define bfin_read_DMA1_2_X_COUNT()           bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val)       bfin_write16(DMA1_2_X_COUNT,val)
-#define bfin_read_DMA1_2_Y_COUNT()           bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val)       bfin_write16(DMA1_2_Y_COUNT,val)
-#define bfin_read_DMA1_2_X_MODIFY()          bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val)      bfin_write16(DMA1_2_X_MODIFY,val)
-#define bfin_read_DMA1_2_Y_MODIFY()          bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val)      bfin_write16(DMA1_2_Y_MODIFY,val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR()     bfin_read32(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_2_CURR_ADDR()         bfin_read32(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val)     bfin_write32(DMA1_2_CURR_ADDR,val)
-#define bfin_read_DMA1_2_CURR_X_COUNT()      bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val)  bfin_write16(DMA1_2_CURR_X_COUNT,val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT()      bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val)  bfin_write16(DMA1_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_2_IRQ_STATUS()        bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val)    bfin_write16(DMA1_2_IRQ_STATUS,val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP()    bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_3_CONFIG()            bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val)        bfin_write16(DMA1_3_CONFIG,val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR()     bfin_read32(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_3_START_ADDR()        bfin_read32(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val)    bfin_write32(DMA1_3_START_ADDR,val)
-#define bfin_read_DMA1_3_X_COUNT()           bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val)       bfin_write16(DMA1_3_X_COUNT,val)
-#define bfin_read_DMA1_3_Y_COUNT()           bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val)       bfin_write16(DMA1_3_Y_COUNT,val)
-#define bfin_read_DMA1_3_X_MODIFY()          bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val)      bfin_write16(DMA1_3_X_MODIFY,val)
-#define bfin_read_DMA1_3_Y_MODIFY()          bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val)      bfin_write16(DMA1_3_Y_MODIFY,val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR()     bfin_read32(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_3_CURR_ADDR()         bfin_read32(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val)     bfin_write32(DMA1_3_CURR_ADDR,val)
-#define bfin_read_DMA1_3_CURR_X_COUNT()      bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val)  bfin_write16(DMA1_3_CURR_X_COUNT,val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT()      bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val)  bfin_write16(DMA1_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_3_IRQ_STATUS()        bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val)    bfin_write16(DMA1_3_IRQ_STATUS,val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP()    bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_4_CONFIG()            bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val)        bfin_write16(DMA1_4_CONFIG,val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR()     bfin_read32(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_4_START_ADDR()        bfin_read32(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val)    bfin_write32(DMA1_4_START_ADDR,val)
-#define bfin_read_DMA1_4_X_COUNT()           bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val)       bfin_write16(DMA1_4_X_COUNT,val)
-#define bfin_read_DMA1_4_Y_COUNT()           bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val)       bfin_write16(DMA1_4_Y_COUNT,val)
-#define bfin_read_DMA1_4_X_MODIFY()          bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val)      bfin_write16(DMA1_4_X_MODIFY,val)
-#define bfin_read_DMA1_4_Y_MODIFY()          bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val)      bfin_write16(DMA1_4_Y_MODIFY,val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR()     bfin_read32(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_4_CURR_ADDR()         bfin_read32(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val)     bfin_write32(DMA1_4_CURR_ADDR,val)
-#define bfin_read_DMA1_4_CURR_X_COUNT()      bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val)  bfin_write16(DMA1_4_CURR_X_COUNT,val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT()      bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val)  bfin_write16(DMA1_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_4_IRQ_STATUS()        bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val)    bfin_write16(DMA1_4_IRQ_STATUS,val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP()    bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_5_CONFIG()            bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val)        bfin_write16(DMA1_5_CONFIG,val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR()     bfin_read32(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_5_START_ADDR()        bfin_read32(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val)    bfin_write32(DMA1_5_START_ADDR,val)
-#define bfin_read_DMA1_5_X_COUNT()           bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val)       bfin_write16(DMA1_5_X_COUNT,val)
-#define bfin_read_DMA1_5_Y_COUNT()           bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val)       bfin_write16(DMA1_5_Y_COUNT,val)
-#define bfin_read_DMA1_5_X_MODIFY()          bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val)      bfin_write16(DMA1_5_X_MODIFY,val)
-#define bfin_read_DMA1_5_Y_MODIFY()          bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val)      bfin_write16(DMA1_5_Y_MODIFY,val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR()     bfin_read32(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_5_CURR_ADDR()         bfin_read32(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val)     bfin_write32(DMA1_5_CURR_ADDR,val)
-#define bfin_read_DMA1_5_CURR_X_COUNT()      bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val)  bfin_write16(DMA1_5_CURR_X_COUNT,val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT()      bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val)  bfin_write16(DMA1_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_5_IRQ_STATUS()        bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val)    bfin_write16(DMA1_5_IRQ_STATUS,val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP()    bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_6_CONFIG()            bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val)        bfin_write16(DMA1_6_CONFIG,val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR()     bfin_read32(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_6_START_ADDR()        bfin_read32(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val)    bfin_write32(DMA1_6_START_ADDR,val)
-#define bfin_read_DMA1_6_X_COUNT()           bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val)       bfin_write16(DMA1_6_X_COUNT,val)
-#define bfin_read_DMA1_6_Y_COUNT()           bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val)       bfin_write16(DMA1_6_Y_COUNT,val)
-#define bfin_read_DMA1_6_X_MODIFY()          bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val)      bfin_write16(DMA1_6_X_MODIFY,val)
-#define bfin_read_DMA1_6_Y_MODIFY()          bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val)      bfin_write16(DMA1_6_Y_MODIFY,val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR()     bfin_read32(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_6_CURR_ADDR()         bfin_read32(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val)     bfin_write32(DMA1_6_CURR_ADDR,val)
-#define bfin_read_DMA1_6_CURR_X_COUNT()      bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val)  bfin_write16(DMA1_6_CURR_X_COUNT,val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT()      bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val)  bfin_write16(DMA1_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_6_IRQ_STATUS()        bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val)    bfin_write16(DMA1_6_IRQ_STATUS,val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP()    bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_7_CONFIG()            bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val)        bfin_write16(DMA1_7_CONFIG,val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR()     bfin_read32(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_7_START_ADDR()        bfin_read32(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val)    bfin_write32(DMA1_7_START_ADDR,val)
-#define bfin_read_DMA1_7_X_COUNT()           bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val)       bfin_write16(DMA1_7_X_COUNT,val)
-#define bfin_read_DMA1_7_Y_COUNT()           bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val)       bfin_write16(DMA1_7_Y_COUNT,val)
-#define bfin_read_DMA1_7_X_MODIFY()          bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val)      bfin_write16(DMA1_7_X_MODIFY,val)
-#define bfin_read_DMA1_7_Y_MODIFY()          bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val)      bfin_write16(DMA1_7_Y_MODIFY,val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR()     bfin_read32(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_7_CURR_ADDR()         bfin_read32(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val)     bfin_write32(DMA1_7_CURR_ADDR,val)
-#define bfin_read_DMA1_7_CURR_X_COUNT()      bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val)  bfin_write16(DMA1_7_CURR_X_COUNT,val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT()      bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val)  bfin_write16(DMA1_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_7_IRQ_STATUS()        bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val)    bfin_write16(DMA1_7_IRQ_STATUS,val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP()    bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_8_CONFIG()            bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val)        bfin_write16(DMA1_8_CONFIG,val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR()     bfin_read32(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_8_START_ADDR()        bfin_read32(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val)    bfin_write32(DMA1_8_START_ADDR,val)
-#define bfin_read_DMA1_8_X_COUNT()           bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val)       bfin_write16(DMA1_8_X_COUNT,val)
-#define bfin_read_DMA1_8_Y_COUNT()           bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val)       bfin_write16(DMA1_8_Y_COUNT,val)
-#define bfin_read_DMA1_8_X_MODIFY()          bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val)      bfin_write16(DMA1_8_X_MODIFY,val)
-#define bfin_read_DMA1_8_Y_MODIFY()          bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val)      bfin_write16(DMA1_8_Y_MODIFY,val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR()     bfin_read32(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_8_CURR_ADDR()         bfin_read32(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val)     bfin_write32(DMA1_8_CURR_ADDR,val)
-#define bfin_read_DMA1_8_CURR_X_COUNT()      bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val)  bfin_write16(DMA1_8_CURR_X_COUNT,val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT()      bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val)  bfin_write16(DMA1_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_8_IRQ_STATUS()        bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val)    bfin_write16(DMA1_8_IRQ_STATUS,val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP()    bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_9_CONFIG()            bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val)        bfin_write16(DMA1_9_CONFIG,val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR()     bfin_read32(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_9_START_ADDR()        bfin_read32(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val)    bfin_write32(DMA1_9_START_ADDR,val)
-#define bfin_read_DMA1_9_X_COUNT()           bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val)       bfin_write16(DMA1_9_X_COUNT,val)
-#define bfin_read_DMA1_9_Y_COUNT()           bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val)       bfin_write16(DMA1_9_Y_COUNT,val)
-#define bfin_read_DMA1_9_X_MODIFY()          bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val)      bfin_write16(DMA1_9_X_MODIFY,val)
-#define bfin_read_DMA1_9_Y_MODIFY()          bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val)      bfin_write16(DMA1_9_Y_MODIFY,val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR()     bfin_read32(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_9_CURR_ADDR()         bfin_read32(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val)     bfin_write32(DMA1_9_CURR_ADDR,val)
-#define bfin_read_DMA1_9_CURR_X_COUNT()      bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val)  bfin_write16(DMA1_9_CURR_X_COUNT,val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT()      bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val)  bfin_write16(DMA1_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_9_IRQ_STATUS()        bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val)    bfin_write16(DMA1_9_IRQ_STATUS,val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP()    bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_10_CONFIG()           bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val)       bfin_write16(DMA1_10_CONFIG,val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR()    bfin_read32(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_10_START_ADDR()       bfin_read32(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val)   bfin_write32(DMA1_10_START_ADDR,val)
-#define bfin_read_DMA1_10_X_COUNT()          bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val)      bfin_write16(DMA1_10_X_COUNT,val)
-#define bfin_read_DMA1_10_Y_COUNT()          bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val)      bfin_write16(DMA1_10_Y_COUNT,val)
-#define bfin_read_DMA1_10_X_MODIFY()         bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val)     bfin_write16(DMA1_10_X_MODIFY,val)
-#define bfin_read_DMA1_10_Y_MODIFY()         bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val)     bfin_write16(DMA1_10_Y_MODIFY,val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR()    bfin_read32(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_10_CURR_ADDR()        bfin_read32(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val)    bfin_write32(DMA1_10_CURR_ADDR,val)
-#define bfin_read_DMA1_10_CURR_X_COUNT()     bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT()     bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_10_IRQ_STATUS()       bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val)   bfin_write16(DMA1_10_IRQ_STATUS,val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP()   bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_11_CONFIG()           bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val)       bfin_write16(DMA1_11_CONFIG,val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR()    bfin_read32(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_11_START_ADDR()       bfin_read32(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val)   bfin_write32(DMA1_11_START_ADDR,val)
-#define bfin_read_DMA1_11_X_COUNT()          bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val)      bfin_write16(DMA1_11_X_COUNT,val)
-#define bfin_read_DMA1_11_Y_COUNT()          bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val)      bfin_write16(DMA1_11_Y_COUNT,val)
-#define bfin_read_DMA1_11_X_MODIFY()         bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val)     bfin_write16(DMA1_11_X_MODIFY,val)
-#define bfin_read_DMA1_11_Y_MODIFY()         bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val)     bfin_write16(DMA1_11_Y_MODIFY,val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR()    bfin_read32(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_11_CURR_ADDR()        bfin_read32(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val)    bfin_write32(DMA1_11_CURR_ADDR,val)
-#define bfin_read_DMA1_11_CURR_X_COUNT()     bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT()     bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_11_IRQ_STATUS()       bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val)   bfin_write16(DMA1_11_IRQ_STATUS,val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP()   bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA1_D0_CONFIG()          bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val)      bfin_write16(MDMA1_D0_CONFIG,val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR()   bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_START_ADDR()      bfin_read32(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val)  bfin_write32(MDMA1_D0_START_ADDR,val)
-#define bfin_read_MDMA1_D0_X_COUNT()         bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val)     bfin_write16(MDMA1_D0_X_COUNT,val)
-#define bfin_read_MDMA1_D0_Y_COUNT()         bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val)     bfin_write16(MDMA1_D0_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_X_MODIFY()        bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val)    bfin_write16(MDMA1_D0_X_MODIFY,val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()        bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val)    bfin_write16(MDMA1_D0_Y_MODIFY,val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR()   bfin_read32(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_CURR_ADDR()       bfin_read32(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val)   bfin_write32(MDMA1_D0_CURR_ADDR,val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT()    bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT()    bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS()      bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val)  bfin_write16(MDMA1_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP()  bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S0_CONFIG()          bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val)      bfin_write16(MDMA1_S0_CONFIG,val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR()   bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_START_ADDR()      bfin_read32(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val)  bfin_write32(MDMA1_S0_START_ADDR,val)
-#define bfin_read_MDMA1_S0_X_COUNT()         bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val)     bfin_write16(MDMA1_S0_X_COUNT,val)
-#define bfin_read_MDMA1_S0_Y_COUNT()         bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val)     bfin_write16(MDMA1_S0_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_X_MODIFY()        bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val)    bfin_write16(MDMA1_S0_X_MODIFY,val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()        bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val)    bfin_write16(MDMA1_S0_Y_MODIFY,val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR()   bfin_read32(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_CURR_ADDR()       bfin_read32(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val)   bfin_write32(MDMA1_S0_CURR_ADDR,val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT()    bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT()    bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS()      bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val)  bfin_write16(MDMA1_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP()  bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_D1_CONFIG()          bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val)      bfin_write16(MDMA1_D1_CONFIG,val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR()   bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_START_ADDR()      bfin_read32(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val)  bfin_write32(MDMA1_D1_START_ADDR,val)
-#define bfin_read_MDMA1_D1_X_COUNT()         bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val)     bfin_write16(MDMA1_D1_X_COUNT,val)
-#define bfin_read_MDMA1_D1_Y_COUNT()         bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val)     bfin_write16(MDMA1_D1_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_X_MODIFY()        bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val)    bfin_write16(MDMA1_D1_X_MODIFY,val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()        bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val)    bfin_write16(MDMA1_D1_Y_MODIFY,val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR()   bfin_read32(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_CURR_ADDR()       bfin_read32(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val)   bfin_write32(MDMA1_D1_CURR_ADDR,val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT()    bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT()    bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS()      bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val)  bfin_write16(MDMA1_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP()  bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S1_CONFIG()          bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val)      bfin_write16(MDMA1_S1_CONFIG,val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR()   bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_START_ADDR()      bfin_read32(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val)  bfin_write32(MDMA1_S1_START_ADDR,val)
-#define bfin_read_MDMA1_S1_X_COUNT()         bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val)     bfin_write16(MDMA1_S1_X_COUNT,val)
-#define bfin_read_MDMA1_S1_Y_COUNT()         bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val)     bfin_write16(MDMA1_S1_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_X_MODIFY()        bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val)    bfin_write16(MDMA1_S1_X_MODIFY,val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()        bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val)    bfin_write16(MDMA1_S1_Y_MODIFY,val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR()   bfin_read32(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_CURR_ADDR()       bfin_read32(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val)   bfin_write32(MDMA1_S1_CURR_ADDR,val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT()    bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT()    bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS()      bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val)  bfin_write16(MDMA1_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP()  bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define bfin_read_DMA2_0_CONFIG()            bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val)        bfin_write16(DMA2_0_CONFIG,val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR()     bfin_read32(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_0_START_ADDR()        bfin_read32(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val)    bfin_write32(DMA2_0_START_ADDR,val)
-#define bfin_read_DMA2_0_X_COUNT()           bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val)       bfin_write16(DMA2_0_X_COUNT,val)
-#define bfin_read_DMA2_0_Y_COUNT()           bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val)       bfin_write16(DMA2_0_Y_COUNT,val)
-#define bfin_read_DMA2_0_X_MODIFY()          bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val)      bfin_write16(DMA2_0_X_MODIFY,val)
-#define bfin_read_DMA2_0_Y_MODIFY()          bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val)      bfin_write16(DMA2_0_Y_MODIFY,val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR()     bfin_read32(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_0_CURR_ADDR()         bfin_read32(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val)     bfin_write32(DMA2_0_CURR_ADDR,val)
-#define bfin_read_DMA2_0_CURR_X_COUNT()      bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val)  bfin_write16(DMA2_0_CURR_X_COUNT,val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT()      bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val)  bfin_write16(DMA2_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_0_IRQ_STATUS()        bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val)    bfin_write16(DMA2_0_IRQ_STATUS,val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP()    bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_1_CONFIG()            bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val)        bfin_write16(DMA2_1_CONFIG,val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR()     bfin_read32(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_1_START_ADDR()        bfin_read32(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val)    bfin_write32(DMA2_1_START_ADDR,val)
-#define bfin_read_DMA2_1_X_COUNT()           bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val)       bfin_write16(DMA2_1_X_COUNT,val)
-#define bfin_read_DMA2_1_Y_COUNT()           bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val)       bfin_write16(DMA2_1_Y_COUNT,val)
-#define bfin_read_DMA2_1_X_MODIFY()          bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val)      bfin_write16(DMA2_1_X_MODIFY,val)
-#define bfin_read_DMA2_1_Y_MODIFY()          bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val)      bfin_write16(DMA2_1_Y_MODIFY,val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR()     bfin_read32(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_1_CURR_ADDR()         bfin_read32(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val)     bfin_write32(DMA2_1_CURR_ADDR,val)
-#define bfin_read_DMA2_1_CURR_X_COUNT()      bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val)  bfin_write16(DMA2_1_CURR_X_COUNT,val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT()      bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val)  bfin_write16(DMA2_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_1_IRQ_STATUS()        bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val)    bfin_write16(DMA2_1_IRQ_STATUS,val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP()    bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_2_CONFIG()            bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val)        bfin_write16(DMA2_2_CONFIG,val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR()     bfin_read32(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_2_START_ADDR()        bfin_read32(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val)    bfin_write32(DMA2_2_START_ADDR,val)
-#define bfin_read_DMA2_2_X_COUNT()           bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val)       bfin_write16(DMA2_2_X_COUNT,val)
-#define bfin_read_DMA2_2_Y_COUNT()           bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val)       bfin_write16(DMA2_2_Y_COUNT,val)
-#define bfin_read_DMA2_2_X_MODIFY()          bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val)      bfin_write16(DMA2_2_X_MODIFY,val)
-#define bfin_read_DMA2_2_Y_MODIFY()          bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val)      bfin_write16(DMA2_2_Y_MODIFY,val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR()     bfin_read32(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_2_CURR_ADDR()         bfin_read32(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val)     bfin_write32(DMA2_2_CURR_ADDR,val)
-#define bfin_read_DMA2_2_CURR_X_COUNT()      bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val)  bfin_write16(DMA2_2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT()      bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val)  bfin_write16(DMA2_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_2_IRQ_STATUS()        bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val)    bfin_write16(DMA2_2_IRQ_STATUS,val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP()    bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_3_CONFIG()            bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val)        bfin_write16(DMA2_3_CONFIG,val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR()     bfin_read32(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_3_START_ADDR()        bfin_read32(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val)    bfin_write32(DMA2_3_START_ADDR,val)
-#define bfin_read_DMA2_3_X_COUNT()           bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val)       bfin_write16(DMA2_3_X_COUNT,val)
-#define bfin_read_DMA2_3_Y_COUNT()           bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val)       bfin_write16(DMA2_3_Y_COUNT,val)
-#define bfin_read_DMA2_3_X_MODIFY()          bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val)      bfin_write16(DMA2_3_X_MODIFY,val)
-#define bfin_read_DMA2_3_Y_MODIFY()          bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val)      bfin_write16(DMA2_3_Y_MODIFY,val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR()     bfin_read32(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_3_CURR_ADDR()         bfin_read32(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val)     bfin_write32(DMA2_3_CURR_ADDR,val)
-#define bfin_read_DMA2_3_CURR_X_COUNT()      bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val)  bfin_write16(DMA2_3_CURR_X_COUNT,val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT()      bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val)  bfin_write16(DMA2_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_3_IRQ_STATUS()        bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val)    bfin_write16(DMA2_3_IRQ_STATUS,val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP()    bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_4_CONFIG()            bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val)        bfin_write16(DMA2_4_CONFIG,val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR()     bfin_read32(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_4_START_ADDR()        bfin_read32(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val)    bfin_write32(DMA2_4_START_ADDR,val)
-#define bfin_read_DMA2_4_X_COUNT()           bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val)       bfin_write16(DMA2_4_X_COUNT,val)
-#define bfin_read_DMA2_4_Y_COUNT()           bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val)       bfin_write16(DMA2_4_Y_COUNT,val)
-#define bfin_read_DMA2_4_X_MODIFY()          bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val)      bfin_write16(DMA2_4_X_MODIFY,val)
-#define bfin_read_DMA2_4_Y_MODIFY()          bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val)      bfin_write16(DMA2_4_Y_MODIFY,val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR()     bfin_read32(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_4_CURR_ADDR()         bfin_read32(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val)     bfin_write32(DMA2_4_CURR_ADDR,val)
-#define bfin_read_DMA2_4_CURR_X_COUNT()      bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val)  bfin_write16(DMA2_4_CURR_X_COUNT,val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT()      bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val)  bfin_write16(DMA2_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_4_IRQ_STATUS()        bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val)    bfin_write16(DMA2_4_IRQ_STATUS,val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP()    bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_5_CONFIG()            bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val)        bfin_write16(DMA2_5_CONFIG,val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR()     bfin_read32(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_5_START_ADDR()        bfin_read32(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val)    bfin_write32(DMA2_5_START_ADDR,val)
-#define bfin_read_DMA2_5_X_COUNT()           bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val)       bfin_write16(DMA2_5_X_COUNT,val)
-#define bfin_read_DMA2_5_Y_COUNT()           bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val)       bfin_write16(DMA2_5_Y_COUNT,val)
-#define bfin_read_DMA2_5_X_MODIFY()          bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val)      bfin_write16(DMA2_5_X_MODIFY,val)
-#define bfin_read_DMA2_5_Y_MODIFY()          bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val)      bfin_write16(DMA2_5_Y_MODIFY,val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR()     bfin_read32(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_5_CURR_ADDR()         bfin_read32(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val)     bfin_write32(DMA2_5_CURR_ADDR,val)
-#define bfin_read_DMA2_5_CURR_X_COUNT()      bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val)  bfin_write16(DMA2_5_CURR_X_COUNT,val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT()      bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val)  bfin_write16(DMA2_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_5_IRQ_STATUS()        bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val)    bfin_write16(DMA2_5_IRQ_STATUS,val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP()    bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_6_CONFIG()            bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val)        bfin_write16(DMA2_6_CONFIG,val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR()     bfin_read32(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_6_START_ADDR()        bfin_read32(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val)    bfin_write32(DMA2_6_START_ADDR,val)
-#define bfin_read_DMA2_6_X_COUNT()           bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val)       bfin_write16(DMA2_6_X_COUNT,val)
-#define bfin_read_DMA2_6_Y_COUNT()           bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val)       bfin_write16(DMA2_6_Y_COUNT,val)
-#define bfin_read_DMA2_6_X_MODIFY()          bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val)      bfin_write16(DMA2_6_X_MODIFY,val)
-#define bfin_read_DMA2_6_Y_MODIFY()          bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val)      bfin_write16(DMA2_6_Y_MODIFY,val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR()     bfin_read32(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_6_CURR_ADDR()         bfin_read32(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val)     bfin_write32(DMA2_6_CURR_ADDR,val)
-#define bfin_read_DMA2_6_CURR_X_COUNT()      bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val)  bfin_write16(DMA2_6_CURR_X_COUNT,val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT()      bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val)  bfin_write16(DMA2_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_6_IRQ_STATUS()        bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val)    bfin_write16(DMA2_6_IRQ_STATUS,val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP()    bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_7_CONFIG()            bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val)        bfin_write16(DMA2_7_CONFIG,val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR()     bfin_read32(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_7_START_ADDR()        bfin_read32(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val)    bfin_write32(DMA2_7_START_ADDR,val)
-#define bfin_read_DMA2_7_X_COUNT()           bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val)       bfin_write16(DMA2_7_X_COUNT,val)
-#define bfin_read_DMA2_7_Y_COUNT()           bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val)       bfin_write16(DMA2_7_Y_COUNT,val)
-#define bfin_read_DMA2_7_X_MODIFY()          bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val)      bfin_write16(DMA2_7_X_MODIFY,val)
-#define bfin_read_DMA2_7_Y_MODIFY()          bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val)      bfin_write16(DMA2_7_Y_MODIFY,val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR()     bfin_read32(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_7_CURR_ADDR()         bfin_read32(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val)     bfin_write32(DMA2_7_CURR_ADDR,val)
-#define bfin_read_DMA2_7_CURR_X_COUNT()      bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val)  bfin_write16(DMA2_7_CURR_X_COUNT,val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT()      bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val)  bfin_write16(DMA2_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_7_IRQ_STATUS()        bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val)    bfin_write16(DMA2_7_IRQ_STATUS,val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP()    bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_8_CONFIG()            bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val)        bfin_write16(DMA2_8_CONFIG,val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR()     bfin_read32(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_8_START_ADDR()        bfin_read32(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val)    bfin_write32(DMA2_8_START_ADDR,val)
-#define bfin_read_DMA2_8_X_COUNT()           bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val)       bfin_write16(DMA2_8_X_COUNT,val)
-#define bfin_read_DMA2_8_Y_COUNT()           bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val)       bfin_write16(DMA2_8_Y_COUNT,val)
-#define bfin_read_DMA2_8_X_MODIFY()          bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val)      bfin_write16(DMA2_8_X_MODIFY,val)
-#define bfin_read_DMA2_8_Y_MODIFY()          bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val)      bfin_write16(DMA2_8_Y_MODIFY,val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR()     bfin_read32(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_8_CURR_ADDR()         bfin_read32(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val)     bfin_write32(DMA2_8_CURR_ADDR,val)
-#define bfin_read_DMA2_8_CURR_X_COUNT()      bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val)  bfin_write16(DMA2_8_CURR_X_COUNT,val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT()      bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val)  bfin_write16(DMA2_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_8_IRQ_STATUS()        bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val)    bfin_write16(DMA2_8_IRQ_STATUS,val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP()    bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_9_CONFIG()            bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val)        bfin_write16(DMA2_9_CONFIG,val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR()     bfin_read32(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_9_START_ADDR()        bfin_read32(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val)    bfin_write32(DMA2_9_START_ADDR,val)
-#define bfin_read_DMA2_9_X_COUNT()           bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val)       bfin_write16(DMA2_9_X_COUNT,val)
-#define bfin_read_DMA2_9_Y_COUNT()           bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val)       bfin_write16(DMA2_9_Y_COUNT,val)
-#define bfin_read_DMA2_9_X_MODIFY()          bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val)      bfin_write16(DMA2_9_X_MODIFY,val)
-#define bfin_read_DMA2_9_Y_MODIFY()          bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val)      bfin_write16(DMA2_9_Y_MODIFY,val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR()     bfin_read32(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_9_CURR_ADDR()         bfin_read32(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val)     bfin_write32(DMA2_9_CURR_ADDR,val)
-#define bfin_read_DMA2_9_CURR_X_COUNT()      bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val)  bfin_write16(DMA2_9_CURR_X_COUNT,val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT()      bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val)  bfin_write16(DMA2_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_9_IRQ_STATUS()        bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val)    bfin_write16(DMA2_9_IRQ_STATUS,val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP()    bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_10_CONFIG()           bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val)       bfin_write16(DMA2_10_CONFIG,val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR()    bfin_read32(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_10_START_ADDR()       bfin_read32(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val)   bfin_write32(DMA2_10_START_ADDR,val)
-#define bfin_read_DMA2_10_X_COUNT()          bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val)      bfin_write16(DMA2_10_X_COUNT,val)
-#define bfin_read_DMA2_10_Y_COUNT()          bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val)      bfin_write16(DMA2_10_Y_COUNT,val)
-#define bfin_read_DMA2_10_X_MODIFY()         bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val)     bfin_write16(DMA2_10_X_MODIFY,val)
-#define bfin_read_DMA2_10_Y_MODIFY()         bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val)     bfin_write16(DMA2_10_Y_MODIFY,val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR()    bfin_read32(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_10_CURR_ADDR()        bfin_read32(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val)    bfin_write32(DMA2_10_CURR_ADDR,val)
-#define bfin_read_DMA2_10_CURR_X_COUNT()     bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT()     bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_10_IRQ_STATUS()       bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val)   bfin_write16(DMA2_10_IRQ_STATUS,val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP()   bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_11_CONFIG()           bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val)       bfin_write16(DMA2_11_CONFIG,val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR()    bfin_read32(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_11_START_ADDR()       bfin_read32(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val)   bfin_write32(DMA2_11_START_ADDR,val)
-#define bfin_read_DMA2_11_X_COUNT()          bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val)      bfin_write16(DMA2_11_X_COUNT,val)
-#define bfin_read_DMA2_11_Y_COUNT()          bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val)      bfin_write16(DMA2_11_Y_COUNT,val)
-#define bfin_read_DMA2_11_X_MODIFY()         bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val)     bfin_write16(DMA2_11_X_MODIFY,val)
-#define bfin_read_DMA2_11_Y_MODIFY()         bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val)     bfin_write16(DMA2_11_Y_MODIFY,val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR()    bfin_read32(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_11_CURR_ADDR()        bfin_read32(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val)    bfin_write32(DMA2_11_CURR_ADDR,val)
-#define bfin_read_DMA2_11_CURR_X_COUNT()     bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT()     bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_11_IRQ_STATUS()       bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val)   bfin_write16(DMA2_11_IRQ_STATUS,val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP()   bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA2_D0_CONFIG()          bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val)      bfin_write16(MDMA2_D0_CONFIG,val)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR()   bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_START_ADDR()      bfin_read32(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val)  bfin_write32(MDMA2_D0_START_ADDR,val)
-#define bfin_read_MDMA2_D0_X_COUNT()         bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val)     bfin_write16(MDMA2_D0_X_COUNT,val)
-#define bfin_read_MDMA2_D0_Y_COUNT()         bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val)     bfin_write16(MDMA2_D0_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_X_MODIFY()        bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val)    bfin_write16(MDMA2_D0_X_MODIFY,val)
-#define bfin_read_MDMA2_D0_Y_MODIFY()        bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val)    bfin_write16(MDMA2_D0_Y_MODIFY,val)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR()   bfin_read32(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_CURR_ADDR()       bfin_read32(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val)   bfin_write32(MDMA2_D0_CURR_ADDR,val)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT()    bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT()    bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_IRQ_STATUS()      bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val)  bfin_write16(MDMA2_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP()  bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S0_CONFIG()          bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val)      bfin_write16(MDMA2_S0_CONFIG,val)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR()   bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_START_ADDR()      bfin_read32(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val)  bfin_write32(MDMA2_S0_START_ADDR,val)
-#define bfin_read_MDMA2_S0_X_COUNT()         bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val)     bfin_write16(MDMA2_S0_X_COUNT,val)
-#define bfin_read_MDMA2_S0_Y_COUNT()         bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val)     bfin_write16(MDMA2_S0_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_X_MODIFY()        bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val)    bfin_write16(MDMA2_S0_X_MODIFY,val)
-#define bfin_read_MDMA2_S0_Y_MODIFY()        bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val)    bfin_write16(MDMA2_S0_Y_MODIFY,val)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR()   bfin_read32(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_CURR_ADDR()       bfin_read32(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val)   bfin_write32(MDMA2_S0_CURR_ADDR,val)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT()    bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT()    bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_IRQ_STATUS()      bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val)  bfin_write16(MDMA2_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP()  bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_D1_CONFIG()          bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val)      bfin_write16(MDMA2_D1_CONFIG,val)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR()   bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_START_ADDR()      bfin_read32(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val)  bfin_write32(MDMA2_D1_START_ADDR,val)
-#define bfin_read_MDMA2_D1_X_COUNT()         bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val)     bfin_write16(MDMA2_D1_X_COUNT,val)
-#define bfin_read_MDMA2_D1_Y_COUNT()         bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val)     bfin_write16(MDMA2_D1_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_X_MODIFY()        bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val)    bfin_write16(MDMA2_D1_X_MODIFY,val)
-#define bfin_read_MDMA2_D1_Y_MODIFY()        bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val)    bfin_write16(MDMA2_D1_Y_MODIFY,val)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR()   bfin_read32(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_CURR_ADDR()       bfin_read32(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val)   bfin_write32(MDMA2_D1_CURR_ADDR,val)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT()    bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT()    bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_IRQ_STATUS()      bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val)  bfin_write16(MDMA2_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP()  bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S1_CONFIG()          bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val)      bfin_write16(MDMA2_S1_CONFIG,val)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR()   bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_START_ADDR()      bfin_read32(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val)  bfin_write32(MDMA2_S1_START_ADDR,val)
-#define bfin_read_MDMA2_S1_X_COUNT()         bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val)     bfin_write16(MDMA2_S1_X_COUNT,val)
-#define bfin_read_MDMA2_S1_Y_COUNT()         bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val)     bfin_write16(MDMA2_S1_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_X_MODIFY()        bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val)    bfin_write16(MDMA2_S1_X_MODIFY,val)
-#define bfin_read_MDMA2_S1_Y_MODIFY()        bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val)    bfin_write16(MDMA2_S1_Y_MODIFY,val)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR()   bfin_read32(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_CURR_ADDR()       bfin_read32(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val)   bfin_write32(MDMA2_S1_CURR_ADDR,val)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT()    bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT()    bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_IRQ_STATUS()      bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val)  bfin_write16(MDMA2_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP()  bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define bfin_read_IMDMA_D0_CONFIG()          bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val)      bfin_write16(IMDMA_D0_CONFIG,val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR()   bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_START_ADDR()      bfin_read32(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val)  bfin_write32(IMDMA_D0_START_ADDR,val)
-#define bfin_read_IMDMA_D0_X_COUNT()         bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val)     bfin_write16(IMDMA_D0_X_COUNT,val)
-#define bfin_read_IMDMA_D0_Y_COUNT()         bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val)     bfin_write16(IMDMA_D0_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_X_MODIFY()        bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val)    bfin_write16(IMDMA_D0_X_MODIFY,val)
-#define bfin_read_IMDMA_D0_Y_MODIFY()        bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val)    bfin_write16(IMDMA_D0_Y_MODIFY,val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR()   bfin_read32(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_CURR_ADDR()       bfin_read32(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val)   bfin_write32(IMDMA_D0_CURR_ADDR,val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT()    bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT()    bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS()      bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val)  bfin_write16(IMDMA_D0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S0_CONFIG()          bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val)      bfin_write16(IMDMA_S0_CONFIG,val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR()   bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_START_ADDR()      bfin_read32(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val)  bfin_write32(IMDMA_S0_START_ADDR,val)
-#define bfin_read_IMDMA_S0_X_COUNT()         bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val)     bfin_write16(IMDMA_S0_X_COUNT,val)
-#define bfin_read_IMDMA_S0_Y_COUNT()         bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val)     bfin_write16(IMDMA_S0_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_X_MODIFY()        bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val)    bfin_write16(IMDMA_S0_X_MODIFY,val)
-#define bfin_read_IMDMA_S0_Y_MODIFY()        bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val)    bfin_write16(IMDMA_S0_Y_MODIFY,val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR()   bfin_read32(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_CURR_ADDR()       bfin_read32(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val)   bfin_write32(IMDMA_S0_CURR_ADDR,val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT()    bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT()    bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS()      bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val)  bfin_write16(IMDMA_S0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_D1_CONFIG()          bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val)      bfin_write16(IMDMA_D1_CONFIG,val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR()   bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_START_ADDR()      bfin_read32(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val)  bfin_write32(IMDMA_D1_START_ADDR,val)
-#define bfin_read_IMDMA_D1_X_COUNT()         bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val)     bfin_write16(IMDMA_D1_X_COUNT,val)
-#define bfin_read_IMDMA_D1_Y_COUNT()         bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val)     bfin_write16(IMDMA_D1_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_X_MODIFY()        bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val)    bfin_write16(IMDMA_D1_X_MODIFY,val)
-#define bfin_read_IMDMA_D1_Y_MODIFY()        bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val)    bfin_write16(IMDMA_D1_Y_MODIFY,val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR()   bfin_read32(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_CURR_ADDR()       bfin_read32(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val)   bfin_write32(IMDMA_D1_CURR_ADDR,val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT()    bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT()    bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS()      bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val)  bfin_write16(IMDMA_D1_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S1_CONFIG()          bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val)      bfin_write16(IMDMA_S1_CONFIG,val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR()   bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_START_ADDR()      bfin_read32(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val)  bfin_write32(IMDMA_S1_START_ADDR,val)
-#define bfin_read_IMDMA_S1_X_COUNT()         bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val)     bfin_write16(IMDMA_S1_X_COUNT,val)
-#define bfin_read_IMDMA_S1_Y_COUNT()         bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val)     bfin_write16(IMDMA_S1_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_X_MODIFY()        bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val)    bfin_write16(IMDMA_S1_X_MODIFY,val)
-#define bfin_read_IMDMA_S1_Y_MODIFY()        bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val)    bfin_write16(IMDMA_S1_Y_MODIFY,val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR()   bfin_read32(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_CURR_ADDR()       bfin_read32(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val)   bfin_write32(IMDMA_S1_CURR_ADDR,val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT()    bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT()    bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS()      bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val)  bfin_write16(IMDMA_S1_IRQ_STATUS,val)
-
-#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA1_S0_CONFIG()
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA1_S0_IRQ_STATUS()
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
-#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA1_S0_X_MODIFY()
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
-#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA1_S0_Y_MODIFY()
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
-#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA1_S0_X_COUNT()
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
-#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA1_S0_Y_COUNT()
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
-#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA1_S0_START_ADDR()
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
-#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA1_D0_CONFIG()
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA1_D0_IRQ_STATUS()
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
-#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA1_D0_X_MODIFY()
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
-#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA1_D0_Y_MODIFY()
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
-#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA1_D0_X_COUNT()
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
-#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA1_D0_Y_COUNT()
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
-#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
-
-#endif                          /* _CDEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
deleted file mode 100644
index 1ab50e906fe7..000000000000
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ /dev/null
@@ -1,1758 +0,0 @@
-
-/*
- * File:         include/asm-blackfin/mach-bf561/defBF561.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-/*
-#if !defined(__ADSPBF561__)
-#warning defBF561.h should only be included for BF561 chip.
-#endif
-*/
-/* include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register (16-bit) */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
-#define CHIPID                 0xFFC00014       /* Chip ID Register */
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define SWRST                   SICA_SWRST
-#define SYSCR                   SICA_SYSCR
-#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
-#define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
-#define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
-#define RESET_SOFTWARE          (SWRST_OCCURRED)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SICA_SWRST              0xFFC00100      /* Software Reset register */
-#define SICA_SYSCR              0xFFC00104      /* System Reset Configuration register */
-#define SICA_RVECT              0xFFC00108      /* SIC Reset Vector Address Register */
-#define SICA_IMASK              0xFFC0010C      /* SIC Interrupt Mask register 0 - hack to fix old tests */
-#define SICA_IMASK0             0xFFC0010C      /* SIC Interrupt Mask register 0 */
-#define SICA_IMASK1             0xFFC00110      /* SIC Interrupt Mask register 1 */
-#define SICA_IAR0               0xFFC00124      /* SIC Interrupt Assignment Register 0 */
-#define SICA_IAR1               0xFFC00128      /* SIC Interrupt Assignment Register 1 */
-#define SICA_IAR2               0xFFC0012C      /* SIC Interrupt Assignment Register 2 */
-#define SICA_IAR3               0xFFC00130      /* SIC Interrupt Assignment Register 3 */
-#define SICA_IAR4               0xFFC00134      /* SIC Interrupt Assignment Register 4 */
-#define SICA_IAR5               0xFFC00138      /* SIC Interrupt Assignment Register 5 */
-#define SICA_IAR6               0xFFC0013C      /* SIC Interrupt Assignment Register 6 */
-#define SICA_IAR7               0xFFC00140      /* SIC Interrupt Assignment Register 7 */
-#define SICA_ISR0               0xFFC00114      /* SIC Interrupt Status register 0 */
-#define SICA_ISR1               0xFFC00118      /* SIC Interrupt Status register 1 */
-#define SICA_IWR0               0xFFC0011C      /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICA_IWR1               0xFFC00120      /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST              0xFFC01100      /* reserved */
-#define SICB_SYSCR              0xFFC01104      /* reserved */
-#define SICB_RVECT              0xFFC01108      /* SIC Reset Vector Address Register */
-#define SICB_IMASK0             0xFFC0110C      /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1             0xFFC01110      /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0               0xFFC01124      /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1               0xFFC01128      /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2               0xFFC0112C      /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3               0xFFC01130      /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4               0xFFC01134      /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5               0xFFC01138      /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6               0xFFC0113C      /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7               0xFFC01140      /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0               0xFFC01114      /* SIC Interrupt Status register 0 */
-#define SICB_ISR1               0xFFC01118      /* SIC Interrupt Status register 1 */
-#define SICB_IWR0               0xFFC0111C      /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1               0xFFC01120      /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL                               0xFFC00200      /* Watchdog Control register */
-#define WDOGA_CNT                               0xFFC00204      /* Watchdog Count register */
-#define WDOGA_STAT                              0xFFC00208      /* Watchdog Status register */
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL                               0xFFC01200      /* Watchdog Control register */
-#define WDOGB_CNT                               0xFFC01204      /* Watchdog Count register */
-#define WDOGB_STAT                              0xFFC01208      /* Watchdog Status register */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
-#define BFIN_UART_THR                   0xFFC00400  /* Transmit Holding register */
-#define BFIN_UART_RBR                   0xFFC00400  /* Receive Buffer register */
-#define BFIN_UART_DLL                   0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER                   0xFFC00404  /* Interrupt Enable Register */
-#define BFIN_UART_DLH                   0xFFC00404  /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR                   0xFFC00408  /* Interrupt Identification Register */
-#define BFIN_UART_LCR                   0xFFC0040C  /* Line Control Register */
-#define BFIN_UART_MCR                   0xFFC00410  /* Modem Control Register */
-#define BFIN_UART_LSR                   0xFFC00414  /* Line Status Register */
-#define BFIN_UART_MSR                   0xFFC00418  /* Modem Status Register */
-#define BFIN_UART_SCR                   0xFFC0041C  /* SCR Scratch Register */
-#define BFIN_UART_GCTL                  0xFFC00424  /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG                           0xFFC00600      /* Timer0 Configuration register */
-#define TIMER0_COUNTER                          0xFFC00604      /* Timer0 Counter register */
-#define TIMER0_PERIOD                           0xFFC00608      /* Timer0 Period register */
-#define TIMER0_WIDTH                            0xFFC0060C      /* Timer0 Width register */
-
-#define TIMER1_CONFIG                           0xFFC00610      /* Timer1 Configuration register */
-#define TIMER1_COUNTER                          0xFFC00614      /* Timer1 Counter register */
-#define TIMER1_PERIOD                           0xFFC00618      /* Timer1 Period register */
-#define TIMER1_WIDTH                            0xFFC0061C      /* Timer1 Width register */
-
-#define TIMER2_CONFIG                           0xFFC00620      /* Timer2 Configuration register */
-#define TIMER2_COUNTER                          0xFFC00624      /* Timer2 Counter register */
-#define TIMER2_PERIOD                           0xFFC00628      /* Timer2 Period register */
-#define TIMER2_WIDTH                            0xFFC0062C      /* Timer2 Width register */
-
-#define TIMER3_CONFIG                           0xFFC00630      /* Timer3 Configuration register */
-#define TIMER3_COUNTER                          0xFFC00634      /* Timer3 Counter register */
-#define TIMER3_PERIOD                           0xFFC00638      /* Timer3 Period register */
-#define TIMER3_WIDTH                            0xFFC0063C      /* Timer3 Width register */
-
-#define TIMER4_CONFIG                           0xFFC00640      /* Timer4 Configuration register */
-#define TIMER4_COUNTER                          0xFFC00644      /* Timer4 Counter register */
-#define TIMER4_PERIOD                           0xFFC00648      /* Timer4 Period register */
-#define TIMER4_WIDTH                            0xFFC0064C      /* Timer4 Width register */
-
-#define TIMER5_CONFIG                           0xFFC00650      /* Timer5 Configuration register */
-#define TIMER5_COUNTER                          0xFFC00654      /* Timer5 Counter register */
-#define TIMER5_PERIOD                           0xFFC00658      /* Timer5 Period register */
-#define TIMER5_WIDTH                            0xFFC0065C      /* Timer5 Width register */
-
-#define TIMER6_CONFIG                           0xFFC00660      /* Timer6 Configuration register */
-#define TIMER6_COUNTER                          0xFFC00664      /* Timer6 Counter register */
-#define TIMER6_PERIOD                           0xFFC00668      /* Timer6 Period register */
-#define TIMER6_WIDTH                            0xFFC0066C      /* Timer6 Width register */
-
-#define TIMER7_CONFIG                           0xFFC00670      /* Timer7 Configuration register */
-#define TIMER7_COUNTER                          0xFFC00674      /* Timer7 Counter register */
-#define TIMER7_PERIOD                           0xFFC00678      /* Timer7 Period register */
-#define TIMER7_WIDTH                            0xFFC0067C      /* Timer7 Width register */
-
-#define TMRS8_ENABLE                            0xFFC00680      /* Timer Enable Register */
-#define TMRS8_DISABLE                           0xFFC00684      /* Timer Disable register */
-#define TMRS8_STATUS                            0xFFC00688      /* Timer Status register */
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG                           0xFFC01600      /* Timer8 Configuration register */
-#define TIMER8_COUNTER                          0xFFC01604      /* Timer8 Counter register */
-#define TIMER8_PERIOD                           0xFFC01608      /* Timer8 Period register */
-#define TIMER8_WIDTH                            0xFFC0160C      /* Timer8 Width register */
-
-#define TIMER9_CONFIG                           0xFFC01610      /* Timer9 Configuration register */
-#define TIMER9_COUNTER                          0xFFC01614      /* Timer9 Counter register */
-#define TIMER9_PERIOD                           0xFFC01618      /* Timer9 Period register */
-#define TIMER9_WIDTH                            0xFFC0161C      /* Timer9 Width register */
-
-#define TIMER10_CONFIG                          0xFFC01620      /* Timer10 Configuration register */
-#define TIMER10_COUNTER                         0xFFC01624      /* Timer10 Counter register */
-#define TIMER10_PERIOD                          0xFFC01628      /* Timer10 Period register */
-#define TIMER10_WIDTH                           0xFFC0162C      /* Timer10 Width register */
-
-#define TIMER11_CONFIG                          0xFFC01630      /* Timer11 Configuration register */
-#define TIMER11_COUNTER                         0xFFC01634      /* Timer11 Counter register */
-#define TIMER11_PERIOD                          0xFFC01638      /* Timer11 Period register */
-#define TIMER11_WIDTH                           0xFFC0163C      /* Timer11 Width register */
-
-#define TMRS4_ENABLE                            0xFFC01640      /* Timer Enable Register */
-#define TMRS4_DISABLE                           0xFFC01644      /* Timer Disable register */
-#define TMRS4_STATUS                            0xFFC01648      /* Timer Status register */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D                             0xFFC00700      /* Flag Data register */
-#define FIO0_FLAG_C                             0xFFC00704      /* Flag Clear register */
-#define FIO0_FLAG_S                             0xFFC00708      /* Flag Set register */
-#define FIO0_FLAG_T                             0xFFC0070C      /* Flag Toggle register */
-#define FIO0_MASKA_D                            0xFFC00710      /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C                            0xFFC00714      /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S                            0xFFC00718      /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T                            0xFFC0071C      /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D                            0xFFC00720      /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C                            0xFFC00724      /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S                            0xFFC00728      /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T                            0xFFC0072C      /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR                                        0xFFC00730      /* Flag Direction register */
-#define FIO0_POLAR                                      0xFFC00734      /* Flag Polarity register */
-#define FIO0_EDGE                                       0xFFC00738      /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH                                       0xFFC0073C      /* Flag Set on Both Edges register */
-#define FIO0_INEN                                       0xFFC00740      /* Flag Input Enable register */
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D                             0xFFC01500      /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C                             0xFFC01504      /* Flag Clear register */
-#define FIO1_FLAG_S                             0xFFC01508      /* Flag Set register */
-#define FIO1_FLAG_T                             0xFFC0150C      /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D                            0xFFC01510      /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C                            0xFFC01514      /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S                            0xFFC01518      /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T                            0xFFC0151C      /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D                            0xFFC01520      /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C                            0xFFC01524      /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S                            0xFFC01528      /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T                            0xFFC0152C      /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR                                        0xFFC01530      /* Flag Direction register */
-#define FIO1_POLAR                                      0xFFC01534      /* Flag Polarity register */
-#define FIO1_EDGE                                       0xFFC01538      /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH                                       0xFFC0153C      /* Flag Set on Both Edges register */
-#define FIO1_INEN                                       0xFFC01540      /* Flag Input Enable register */
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D                             0xFFC01700      /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C                             0xFFC01704      /* Flag Clear register */
-#define FIO2_FLAG_S                             0xFFC01708      /* Flag Set register */
-#define FIO2_FLAG_T                             0xFFC0170C      /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D                            0xFFC01710      /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C                            0xFFC01714      /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S                            0xFFC01718      /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T                            0xFFC0171C      /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D                            0xFFC01720      /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C                            0xFFC01724      /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S                            0xFFC01728      /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T                            0xFFC0172C      /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR                                        0xFFC01730      /* Flag Direction register */
-#define FIO2_POLAR                                      0xFFC01734      /* Flag Polarity register */
-#define FIO2_EDGE                                       0xFFC01738      /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH                                       0xFFC0173C      /* Flag Set on Both Edges register */
-#define FIO2_INEN                                       0xFFC01740      /* Flag Input Enable register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                             0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                             0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1                             0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                             0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                             0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                             0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit  */
-#define EBIU_AMGCTL                                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL                                     0xFFC00A10      /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                                     0xFFC00A14      /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                                     0xFFC00A1C      /* SDRAM Status Register */
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL                            0xFFC01000      /* PPI0 Control register */
-#define PPI0_STATUS                             0xFFC01004      /* PPI0 Status register */
-#define PPI0_COUNT                                      0xFFC01008      /* PPI0 Transfer Count register */
-#define PPI0_DELAY                                      0xFFC0100C      /* PPI0 Delay Count register */
-#define PPI0_FRAME                                      0xFFC01010      /* PPI0 Frame Length register */
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL                            0xFFC01300      /* PPI1 Control register */
-#define PPI1_STATUS                             0xFFC01304      /* PPI1 Status register */
-#define PPI1_COUNT                                      0xFFC01308      /* PPI1 Transfer Count register */
-#define PPI1_DELAY                                      0xFFC0130C      /* PPI1 Delay Count register */
-#define PPI1_FRAME                                      0xFFC01310      /* PPI1 Frame Length register */
-
-/*DMA traffic control registers */
-#define DMA1_TC_PER  0xFFC01B0C /* Traffic control periods */
-#define DMA1_TC_CNT  0xFFC01B10 /* Traffic control current counts */
-#define DMA2_TC_PER  0xFFC00B0C /* Traffic control periods */
-#define DMA2_TC_CNT  0xFFC00B10 /* Traffic control current counts        */
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08        /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04    /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10       /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18       /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14      /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C      /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24     /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30  /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38  /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28    /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C        /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48        /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44    /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50       /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58       /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54      /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C      /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64     /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70  /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78  /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68    /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C        /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88        /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84    /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90       /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98       /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94      /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C      /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4     /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0  /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8  /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8    /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC        /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8        /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4    /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0       /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8       /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4      /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC      /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4     /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0  /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8  /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8    /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC        /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08        /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04    /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10       /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18       /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14      /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C      /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24     /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30  /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38  /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28    /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C        /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48        /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44    /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50       /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58       /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54      /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C      /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64     /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70  /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78  /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68    /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C        /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88        /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84    /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90       /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98       /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94      /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C      /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4     /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0  /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8  /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8    /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC        /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8        /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4    /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0       /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8       /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4      /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC      /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4     /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0  /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8  /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8    /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC        /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08        /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04    /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10       /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18       /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14      /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C      /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24     /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30  /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38  /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28    /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C        /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48        /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44    /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50       /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58       /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54      /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C      /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64     /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70  /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78  /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68    /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C        /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88       /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80        /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84   /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90      /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98      /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94     /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C     /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0        /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4    /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8   /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC       /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8       /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0        /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4   /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0      /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8      /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4     /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC     /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0        /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4    /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8   /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA1_D0_CONFIG 0xFFC01F08      /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00       /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D0_START_ADDR 0xFFC01F04  /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA1_D0_X_COUNT 0xFFC01F10     /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA1_D0_Y_COUNT 0xFFC01F18     /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA1_D0_X_MODIFY 0xFFC01F14    /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C    /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20       /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24   /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30        /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38        /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28  /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA1_S0_CONFIG 0xFFC01F48      /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40       /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA1_S0_START_ADDR 0xFFC01F44  /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA1_S0_X_COUNT 0xFFC01F50     /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA1_S0_Y_COUNT 0xFFC01F58     /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA1_S0_X_MODIFY 0xFFC01F54    /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C    /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60       /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64   /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70        /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78        /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68  /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA1_D1_CONFIG 0xFFC01F88      /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80       /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D1_START_ADDR 0xFFC01F84  /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA1_D1_X_COUNT 0xFFC01F90     /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA1_D1_Y_COUNT 0xFFC01F98     /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA1_D1_X_MODIFY 0xFFC01F94    /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C    /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0       /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4   /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0        /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8        /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8  /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA1_S1_CONFIG 0xFFC01FC8      /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0       /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA1_S1_START_ADDR 0xFFC01FC4  /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA1_S1_X_COUNT 0xFFC01FD0     /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8     /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4    /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC    /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0       /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4   /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0        /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8        /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8  /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /*MemDMA1 Stream 1 Source Peripheral Map */
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04    /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10       /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18       /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14      /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C      /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24     /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30  /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38  /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28    /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C        /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48        /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44    /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50       /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58       /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54      /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C      /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64     /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70  /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78  /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68    /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C        /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88        /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84    /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90       /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98       /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94      /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C      /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4     /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0  /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8  /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8    /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC        /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8        /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4    /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0       /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8       /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4      /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC      /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4     /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0  /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8  /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8    /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC        /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08        /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04    /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10       /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18       /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14      /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C      /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24     /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30  /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38  /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28    /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C        /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48        /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44    /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50       /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58       /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54      /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C      /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64     /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70  /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78  /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68    /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C        /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88        /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84    /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90       /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98       /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94      /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C      /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4     /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0  /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8  /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8    /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC        /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8        /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4    /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0       /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8       /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4      /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC      /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4     /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0  /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8  /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8    /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC        /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08        /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04    /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10       /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18       /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14      /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C      /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24     /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30  /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38  /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28    /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C        /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48        /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44    /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50       /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58       /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54      /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C      /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64     /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70  /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78  /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68    /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C        /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88       /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80        /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84   /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90      /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98      /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94     /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C     /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0        /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4    /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8   /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC       /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8       /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0        /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4   /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0      /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8      /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4     /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC     /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0        /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4    /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8   /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA2_D0_CONFIG 0xFFC00F08      /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00       /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D0_START_ADDR 0xFFC00F04  /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA2_D0_X_COUNT 0xFFC00F10     /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA2_D0_Y_COUNT 0xFFC00F18     /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA2_D0_X_MODIFY 0xFFC00F14    /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C    /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20       /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24   /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30        /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38        /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28  /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C      /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA2_S0_CONFIG 0xFFC00F48      /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40       /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA2_S0_START_ADDR 0xFFC00F44  /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA2_S0_X_COUNT 0xFFC00F50     /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA2_S0_Y_COUNT 0xFFC00F58     /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA2_S0_X_MODIFY 0xFFC00F54    /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C    /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60       /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64   /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70        /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78        /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68  /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C      /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA2_D1_CONFIG 0xFFC00F88      /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80       /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D1_START_ADDR 0xFFC00F84  /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA2_D1_X_COUNT 0xFFC00F90     /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA2_D1_Y_COUNT 0xFFC00F98     /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA2_D1_X_MODIFY 0xFFC00F94    /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C    /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0       /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4   /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0        /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8        /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8  /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC      /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA2_S1_CONFIG 0xFFC00FC8      /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0       /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA2_S1_START_ADDR 0xFFC00FC4  /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA2_S1_X_COUNT 0xFFC00FD0     /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8     /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4    /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC    /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0       /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4   /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0        /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8        /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8  /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC      /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800       /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804  /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810     /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818     /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814    /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C    /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820       /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824   /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830        /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838        /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828  /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848      /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840       /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844  /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850     /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858     /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854    /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C    /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860       /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864   /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870        /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878        /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868  /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888      /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880       /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884  /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890     /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898     /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894    /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C    /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0       /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4   /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0        /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8        /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8  /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8      /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0       /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4  /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0     /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8     /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4    /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC    /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0       /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4   /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0        /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8        /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8  /*IMDMA Stream 1 Source Interrupt/Status */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN              0x00000000       /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2         0x00000001       /* Pass CLKIN/2 to PLL */
-#define PLL_OFF                0x00000002       /* Shut off PLL clocks */
-#define STOPCK_OFF             0x00000008       /* Core clock off */
-#define PDWN                   0x00000020       /* Put the PLL in a Deep Sleep state */
-#define BYPASS                 0x00000100       /* Bypass the PLL */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
-#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /* GAIN = 5*/
-#define GAIN_10                 0x0004  /* GAIN = 1*/
-#define GAIN_20                 0x0008  /* GAIN = 2*/
-#define GAIN_50                 0x000C  /* GAIN = 5*/
-
-#define VLEV                    0x00F0  /* Internal Voltage Level */
-#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* PLL_DIV Masks */
-#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
-
-#define CSEL                    0x30            /* Core Select */
-#define SSEL                    0xf             /* System Select */
-#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* SWRST Mask */
-#define SYSTEM_RESET           0x0007   /* Initiates a system software reset */
-#define DOUBLE_FAULT_A         0x0008   /* Core A Double Fault Causes Reset */
-#define DOUBLE_FAULT_B         0x0010   /* Core B Double Fault Causes Reset */
-#define SWRST_DBL_FAULT_A      0x0800   /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B      0x1000   /* SWRST Core B Double Fault */
-#define SWRST_WDT_B                    0x2000   /* SWRST Watchdog B */
-#define SWRST_WDT_A                    0x4000   /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x8000   /* SWRST Status */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks       */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15   */
-#define Peripheral_IVG(Per_number, IVG_number)    \
-    ((IVG_number) - 7) << (((Per_number) % 8) * 4)      /* Peripheral #Per_number assigned IVG #IVG_number  */
-    /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
-    /*        r0.h = hi(Peripheral_IVG(62, 10)); */
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
-#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
-#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001         /* TX enable  */
-#define ITCLK    0x0002         /* Internal TX Clock Select  */
-#define TDTYPE   0x000C         /* TX Data Formatting Select */
-#define TLSBIT   0x0010         /* TX Bit Order */
-#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400         /* TX Frame Sync Required Select  */
-#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000         /* Low TX Frame Sync Select  */
-#define LATFS    0x2000         /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN        0x001F      /*TX Word Length  */
-#define TXSE        0x0100      /*TX Secondary Enable */
-#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400      /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001         /* RX enable  */
-#define IRCLK    0x0002         /* Internal RX Clock Select  */
-#define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define RULAW    0x0008         /* u-Law enable  */
-#define RALAW    0x000C         /* A-Law enable  */
-#define RLSBIT   0x0010         /* RX Bit Order */
-#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400         /* RX Frame Sync Required Select  */
-#define LRFS     0x1000         /* Low RX Frame Sync Select  */
-#define LARFS    0x2000         /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN        0x001F      /*RX Word Length  */
-#define RXSE        0x0100      /*RX Secondary Enable */
-#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400      /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001  /*RX FIFO Not Empty Status */
-#define RUVF            0x0002  /*RX Underflow Status */
-#define ROVF            0x0004  /*RX Overflow Status */
-#define TXF             0x0008  /*TX FIFO Full Status */
-#define TUVF            0x0010  /*TX Underflow Status */
-#define TOVF            0x0020  /*TX Overflow Status */
-#define TXHRE           0x0040  /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
-#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-
-/*  PPI_CONTROL Masks         */
-#define PORT_EN              0x00000001 /* PPI Port Enable  */
-#define PORT_DIR             0x00000002 /* PPI Port Direction       */
-#define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
-#define PORT_CFG             0x00000030 /* PPI Port Configuration */
-#define FLD_SEL              0x00000040 /* PPI Active Field Select */
-#define PACK_EN              0x00000080 /* PPI Packing Mode */
-#define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH              0x00003800 /* PPI Data Length  */
-#define DLEN_8               0x0        /* PPI Data Length mask for DLEN=8 */
-#define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#define POL                  0x0000C000 /* PPI Signal Polarities       */
-
-/* PPI_STATUS Masks */
-#define FLD                  0x00000400 /* Field Indicator   */
-#define FT_ERR               0x00000800 /* Frame Track Error */
-#define OVR                  0x00001000 /* FIFO Overflow Error */
-#define UNDR                 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET              0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
-
-/* **********  DMA CONTROLLER MASKS  *********************8 */
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
-#define DMAEN           0x00000001      /* Channel Enable */
-#define WNR             0x00000002      /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
-#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
-#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
-#define DMA2D           0x00000010      /* 2D/1D* Mode */
-#define RESTART         0x00000020      /* Restart */
-#define DI_SEL          0x00000040      /* Data Interrupt Select */
-#define DI_EN           0x00000080      /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE          0x00000900      /* Next Descriptor Size */
-#define DMAFLOW         0x00007000      /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P                 0       /* Channel Enable */
-#define WNR_P                   1       /* Channel Direction (W/R*) */
-#define DMA2D_P                 4       /* 2D/1D* Mode */
-#define RESTART_P               5       /* Restart */
-#define DI_SEL_P                6       /* Data Interrupt Select */
-#define DI_EN_P                 7       /* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE                0x00000001      /* DMA Done Indicator */
-#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
-#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
-#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
-
-#define DMA_DONE_P              0       /* DMA Done Indicator */
-#define DMA_ERR_P               1       /* DMA Error Indicator */
-#define DFETCH_P                2       /* Descriptor Fetch Indicator */
-#define DMA_RUN_P               3       /* DMA Running Indicator */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE               0x00000040  /* DMA Channel Type Indicator */
-#define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
-#define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
-#define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
-#define PMAP                0x00007000  /* DMA Peripheral Map Field */
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0  0x0001
-#define TIMEN1  0x0002
-#define TIMEN2  0x0004
-#define TIMEN3  0x0008
-#define TIMEN4  0x0010
-#define TIMEN5  0x0020
-#define TIMEN6  0x0040
-#define TIMEN7  0x0080
-#define TIMEN8  0x0001
-#define TIMEN9  0x0002
-#define TIMEN10 0x0004
-#define TIMEN11 0x0008
-
-#define TIMEN0_P        0x00
-#define TIMEN1_P        0x01
-#define TIMEN2_P        0x02
-#define TIMEN3_P        0x03
-#define TIMEN4_P        0x04
-#define TIMEN5_P        0x05
-#define TIMEN6_P        0x06
-#define TIMEN7_P        0x07
-#define TIMEN8_P        0x00
-#define TIMEN9_P        0x01
-#define TIMEN10_P       0x02
-#define TIMEN11_P       0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0         0x0001
-#define TIMDIS1         0x0002
-#define TIMDIS2         0x0004
-#define TIMDIS3         0x0008
-#define TIMDIS4         0x0010
-#define TIMDIS5         0x0020
-#define TIMDIS6         0x0040
-#define TIMDIS7         0x0080
-#define TIMDIS8         0x0001
-#define TIMDIS9         0x0002
-#define TIMDIS10        0x0004
-#define TIMDIS11        0x0008
-
-#define TIMDIS0_P       0x00
-#define TIMDIS1_P       0x01
-#define TIMDIS2_P       0x02
-#define TIMDIS3_P       0x03
-#define TIMDIS4_P       0x04
-#define TIMDIS5_P       0x05
-#define TIMDIS6_P       0x06
-#define TIMDIS7_P       0x07
-#define TIMDIS8_P       0x00
-#define TIMDIS9_P       0x01
-#define TIMDIS10_P      0x02
-#define TIMDIS11_P      0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0          0x00000001
-#define TIMIL1          0x00000002
-#define TIMIL2          0x00000004
-#define TIMIL3          0x00000008
-#define TIMIL4          0x00010000
-#define TIMIL5          0x00020000
-#define TIMIL6          0x00040000
-#define TIMIL7          0x00080000
-#define TIMIL8          0x0001
-#define TIMIL9          0x0002
-#define TIMIL10         0x0004
-#define TIMIL11         0x0008
-#define TOVF_ERR0       0x00000010
-#define TOVF_ERR1       0x00000020
-#define TOVF_ERR2       0x00000040
-#define TOVF_ERR3       0x00000080
-#define TOVF_ERR4       0x00100000
-#define TOVF_ERR5       0x00200000
-#define TOVF_ERR6       0x00400000
-#define TOVF_ERR7       0x00800000
-#define TOVF_ERR8       0x0010
-#define TOVF_ERR9       0x0020
-#define TOVF_ERR10      0x0040
-#define TOVF_ERR11      0x0080
-#define TRUN0           0x00001000
-#define TRUN1           0x00002000
-#define TRUN2           0x00004000
-#define TRUN3           0x00008000
-#define TRUN4           0x10000000
-#define TRUN5           0x20000000
-#define TRUN6           0x40000000
-#define TRUN7           0x80000000
-#define TRUN8           0x1000
-#define TRUN9           0x2000
-#define TRUN10          0x4000
-#define TRUN11          0x8000
-
-#define TIMIL0_P        0x00
-#define TIMIL1_P        0x01
-#define TIMIL2_P        0x02
-#define TIMIL3_P        0x03
-#define TIMIL4_P        0x10
-#define TIMIL5_P        0x11
-#define TIMIL6_P        0x12
-#define TIMIL7_P        0x13
-#define TIMIL8_P        0x00
-#define TIMIL9_P        0x01
-#define TIMIL10_P       0x02
-#define TIMIL11_P       0x03
-#define TOVF_ERR0_P     0x04
-#define TOVF_ERR1_P     0x05
-#define TOVF_ERR2_P     0x06
-#define TOVF_ERR3_P     0x07
-#define TOVF_ERR4_P     0x14
-#define TOVF_ERR5_P     0x15
-#define TOVF_ERR6_P     0x16
-#define TOVF_ERR7_P     0x17
-#define TOVF_ERR8_P     0x04
-#define TOVF_ERR9_P     0x05
-#define TOVF_ERR10_P    0x06
-#define TOVF_ERR11_P    0x07
-#define TRUN0_P         0x0C
-#define TRUN1_P         0x0D
-#define TRUN2_P         0x0E
-#define TRUN3_P         0x0F
-#define TRUN4_P         0x1C
-#define TRUN5_P         0x1D
-#define TRUN6_P         0x1E
-#define TRUN7_P         0x1F
-#define TRUN8_P         0x0C
-#define TRUN9_P         0x0D
-#define TRUN10_P        0x0E
-#define TRUN11_P        0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT         0x0001
-#define WDTH_CAP        0x0002
-#define EXT_CLK         0x0003
-#define PULSE_HI        0x0004
-#define PERIOD_CNT      0x0008
-#define IRQ_ENA         0x0010
-#define TIN_SEL         0x0020
-#define OUT_DIS         0x0040
-#define CLK_SEL         0x0080
-#define TOGGLE_HI       0x0100
-#define EMU_RUN         0x0200
-#define ERR_TYP(x)      ((x & 0x03) << 14)
-
-#define TMODE_P0                0x00
-#define TMODE_P1                0x01
-#define PULSE_HI_P              0x02
-#define PERIOD_CNT_P            0x03
-#define IRQ_ENA_P               0x04
-#define TIN_SEL_P               0x05
-#define OUT_DIS_P               0x06
-#define CLK_SEL_P               0x07
-#define TOGGLE_HI_P             0x08
-#define EMU_RUN_P               0x09
-#define ERR_TYP_P0              0x0E
-#define ERR_TYP_P1              0x0F
-
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-
-/* SPI_CTL Masks */
-#define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
-#define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
-#define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
-#define SIZE                   0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR                   0x00001000       /* Configures SPI as master (=1) or slave (=0) */
-#define WOM                    0x00002000       /* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE                    0x00004000       /* SPI module enable (=1), disable (=0) */
-
-/* SPI_FLG Masks */
-#define FLS1                   0x00000002       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2                   0x00000004       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3                   0x00000008       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4                   0x00000010       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5                   0x00000020       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6                   0x00000040       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7                   0x00000080       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1                   0x00000200       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2                   0x00000400       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3                   0x00000800       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4                   0x00001000       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5                   0x00002000       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6                   0x00004000       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7                   0x00008000       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P                 0x00000001       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P                 0x00000002       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P                 0x00000003       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P                 0x00000004       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P                 0x00000005       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P                 0x00000006       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P                 0x00000007       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P                 0x00000009       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P                 0x0000000A       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P                 0x0000000B       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P                 0x0000000C       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P                 0x0000000D       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P                 0x0000000E       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P                 0x0000000F       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF                   0x00000001       /* Set (=1) when SPI single-word transfer complete */
-#define MODF                   0x00000002       /* Set (=1) in a master device when some other device tries to become master */
-#define TXE                    0x00000004       /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS                    0x00000008       /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY                   0x00000010       /* Set (=1) when data is received with RDBR full */
-#define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN                  0x0001  /* Enable CLKOUT */
-#define AMBEN_B0                0x0002  /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1             0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL               0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN                  0x0010  /* Enable 16-bit packing Bank 0  */
-#define B1_PEN                  0x0020  /* Enable 16-bit packing Bank 1  */
-#define B2_PEN                  0x0040  /* Enable 16-bit packing Bank 2  */
-#define B3_PEN                  0x0080  /* Enable 16-bit packing Bank 3  */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P                0x00000000      /* Enable CLKOUT */
-#define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P                        0x004   /* Enable 16-bit packing Bank 0  */
-#define B1_PEN_P                        0x005   /* Enable 16-bit packing Bank 1  */
-#define B2_PEN_P                        0x006   /* Enable 16-bit packing Bank 2  */
-#define B3_PEN_P                        0x007   /* Enable 16-bit packing Bank 3  */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
-#define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
-#define PFE                     0x00000010      /* Enable SDRAM prefetch */
-#define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
-#define PUPSD                   0x00200000      /*Power-up start delay */
-#define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
-#define EBUFE                   0x02000000      /* Enable external buffering timing */
-#define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
-#define EMREN                   0x10000000      /* Extended mode register enable */
-#define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
-#define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EB0_E                           0x00000001      /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16                       0x00000000      /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32                       0x00000002      /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64                       0x00000004      /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128                      0x00000006      /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8                       0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9                       0x00000010      /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10                      0x00000020      /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11                      0x00000030      /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E                           0x00000100      /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32                      0x00000200      /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64                      0x00000400      /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128                     0x00000600      /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9                      0x00001000      /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10                     0x00002000      /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11                     0x00003000      /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E                          0x00010000      /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32                      0x00020000      /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64                      0x00040000      /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128                     0x00060000      /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9                      0x00100000      /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10                     0x00200000      /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11                     0x00300000      /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E                          0x01000000      /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32                      0x02000000      /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64                      0x04000000      /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128                     0x06000000      /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9                      0x10000000      /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10                     0x20000000      /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11                     0x30000000      /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI                    0x00000001      /* SDRAM controller is idle  */
-#define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
-#define SDPUA                   0x00000004      /* SDRAM power up active  */
-#define SDRS                    0x00000008      /* SDRAM is in reset state */
-#define SDEASE              0x00000010  /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT                  0x00000020      /* Bus granted */
-
-#endif                          /* _DEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
deleted file mode 100644
index 8bc46cd89a02..000000000000
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-*
-*        BF-533/2/1 Specific Declarations
-*
-****************************************************************************/
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 36
-
-#define CH_PPI0                 0
-#define CH_PPI                  (CH_PPI0)
-#define CH_PPI1                 1
-#define CH_SPORT0_RX            12
-#define CH_SPORT0_TX            13
-#define CH_SPORT1_RX            14
-#define CH_SPORT1_TX            15
-#define CH_SPI                  16
-#define CH_UART_RX              17
-#define CH_UART_TX              18
-#define CH_MEM_STREAM0_DEST     24       /* TX */
-#define CH_MEM_STREAM0_SRC      25       /* RX */
-#define CH_MEM_STREAM1_DEST     26       /* TX */
-#define CH_MEM_STREAM1_SRC      27       /* RX */
-#define CH_MEM_STREAM2_DEST     28
-#define CH_MEM_STREAM2_SRC      29
-#define CH_MEM_STREAM3_DEST     30
-#define CH_MEM_STREAM3_SRC      31
-#define CH_IMEM_STREAM0_DEST    32
-#define CH_IMEM_STREAM0_SRC     33
-#define CH_IMEM_STREAM1_DEST    34
-#define CH_IMEM_STREAM1_SRC     35
-
-#endif
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
deleted file mode 100644
index 6698389c5564..000000000000
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ /dev/null
@@ -1,447 +0,0 @@
-
-/*
- * File:         include/asm-blackfin/mach-bf561/irq.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BF561_IRQ_H_
-#define _BF561_IRQ_H_
-
-/***********************************************************************
- * Interrupt source definitions:
-             Event Source               Core Event Name     IRQ No
-                                                (highest priority)
-            Emulation Events                    EMU         0
-            Reset                               RST         1
-            NMI                                 NMI         2
-            Exception                           EVX         3
-            Reserved                            --          4
-            Hardware Error                      IVHW        5
-            Core Timer                          IVTMR       6 *
-
-            PLL Wakeup Interrupt                IVG7        7
-            DMA1 Error (generic)                IVG7        8
-            DMA2 Error (generic)                IVG7        9
-            IMDMA Error (generic)               IVG7        10
-            PPI1 Error Interrupt                IVG7        11
-            PPI2 Error Interrupt                IVG7        12
-            SPORT0 Error Interrupt              IVG7        13
-            SPORT1 Error Interrupt              IVG7        14
-            SPI Error Interrupt                 IVG7        15
-            UART Error Interrupt                IVG7        16
-            Reserved Interrupt                  IVG7        17
-
-            DMA1 0  Interrupt(PPI1)             IVG8        18
-            DMA1 1  Interrupt(PPI2)             IVG8        19
-            DMA1 2  Interrupt                   IVG8        20
-            DMA1 3  Interrupt                   IVG8        21
-            DMA1 4  Interrupt                   IVG8        22
-            DMA1 5  Interrupt                   IVG8        23
-            DMA1 6  Interrupt                   IVG8        24
-            DMA1 7  Interrupt                   IVG8        25
-            DMA1 8  Interrupt                   IVG8        26
-            DMA1 9  Interrupt                   IVG8        27
-            DMA1 10 Interrupt                   IVG8        28
-            DMA1 11 Interrupt                   IVG8        29
-
-            DMA2 0  (SPORT0 RX)                 IVG9        30
-            DMA2 1  (SPORT0 TX)                 IVG9        31
-            DMA2 2  (SPORT1 RX)                 IVG9        32
-            DMA2 3  (SPORT2 TX)                 IVG9        33
-            DMA2 4  (SPI)                       IVG9        34
-            DMA2 5  (UART RX)                   IVG9        35
-            DMA2 6  (UART TX)                   IVG9        36
-            DMA2 7  Interrupt                   IVG9        37
-            DMA2 8  Interrupt                   IVG9        38
-            DMA2 9  Interrupt                   IVG9        39
-            DMA2 10 Interrupt                   IVG9        40
-            DMA2 11 Interrupt                   IVG9        41
-
-            TIMER 0  Interrupt                  IVG10       42
-            TIMER 1  Interrupt                  IVG10       43
-            TIMER 2  Interrupt                  IVG10       44
-            TIMER 3  Interrupt                  IVG10       45
-            TIMER 4  Interrupt                  IVG10       46
-            TIMER 5  Interrupt                  IVG10       47
-            TIMER 6  Interrupt                  IVG10       48
-            TIMER 7  Interrupt                  IVG10       49
-            TIMER 8  Interrupt                  IVG10       50
-            TIMER 9  Interrupt                  IVG10       51
-            TIMER 10 Interrupt                  IVG10       52
-            TIMER 11 Interrupt                  IVG10       53
-
-            Programmable Flags0 A (8)           IVG11       54
-            Programmable Flags0 B (8)           IVG11       55
-            Programmable Flags1 A (8)           IVG11       56
-            Programmable Flags1 B (8)           IVG11       57
-            Programmable Flags2 A (8)           IVG11       58
-            Programmable Flags2 B (8)           IVG11       59
-
-            MDMA1 0 write/read INT              IVG8        60
-            MDMA1 1 write/read INT              IVG8        61
-
-            MDMA2 0 write/read INT              IVG9        62
-            MDMA2 1 write/read INT              IVG9        63
-
-            IMDMA 0 write/read INT              IVG12       64
-            IMDMA 1 write/read INT              IVG12       65
-
-            Watch Dog Timer                     IVG13       66
-
-            Reserved interrupt                  IVG7        67
-            Reserved interrupt                  IVG7        68
-            Supplemental interrupt 0            IVG7        69
-            supplemental interrupt 1            IVG7        70
-
-            Softirq                             IVG14
-            System Call    --
-                 (lowest priority)              IVG15
-
- **********************************************************************/
-
-#define SYS_IRQS                71
-#define NR_PERI_INTS            64
-
-/*
- * The ABSTRACT IRQ definitions
- *  the first seven of the following are fixed,
- *  the rest you change if you need to.
- */
-/* IVG 0-6*/
-#define IRQ_EMU                 0       /* Emulation                */
-#define IRQ_RST                 1       /* Reset                    */
-#define IRQ_NMI                 2       /* Non Maskable Interrupt   */
-#define IRQ_EVX                 3       /* Exception                */
-#define IRQ_UNUSED              4       /* Reserved interrupt       */
-#define IRQ_HWERR               5       /* Hardware Error           */
-#define IRQ_CORETMR             6       /* Core timer               */
-
-#define IVG_BASE                7
-/* IVG 7  */
-#define IRQ_PLL_WAKEUP          (IVG_BASE + 0)  /* PLL Wakeup Interrupt     */
-#define IRQ_DMA1_ERROR          (IVG_BASE + 1)  /* DMA1   Error (general)   */
-#define IRQ_DMA_ERROR           IRQ_DMA1_ERROR  /* DMA1   Error (general)   */
-#define IRQ_DMA2_ERROR          (IVG_BASE + 2)  /* DMA2   Error (general)   */
-#define IRQ_IMDMA_ERROR         (IVG_BASE + 3)  /* IMDMA  Error Interrupt   */
-#define IRQ_PPI1_ERROR          (IVG_BASE + 4)  /* PPI1   Error Interrupt   */
-#define IRQ_PPI_ERROR           IRQ_PPI1_ERROR  /* PPI1   Error Interrupt   */
-#define IRQ_PPI2_ERROR          (IVG_BASE + 5)  /* PPI2   Error Interrupt   */
-#define IRQ_SPORT0_ERROR        (IVG_BASE + 6)  /* SPORT0 Error Interrupt   */
-#define IRQ_SPORT1_ERROR        (IVG_BASE + 7)  /* SPORT1 Error Interrupt   */
-#define IRQ_SPI_ERROR           (IVG_BASE + 8)  /* SPI    Error Interrupt   */
-#define IRQ_UART_ERROR          (IVG_BASE + 9)  /* UART   Error Interrupt   */
-#define IRQ_RESERVED_ERROR      (IVG_BASE + 10) /* Reversed     Interrupt   */
-/* IVG 8  */
-#define IRQ_DMA1_0              (IVG_BASE + 11) /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_PPI                 IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_PPI0                IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_DMA1_1              (IVG_BASE + 12) /* DMA1 1  Interrupt(PPI2)  */
-#define IRQ_PPI1                IRQ_DMA1_1      /* DMA1 1  Interrupt(PPI2)  */
-#define IRQ_DMA1_2              (IVG_BASE + 13) /* DMA1 2  Interrupt        */
-#define IRQ_DMA1_3              (IVG_BASE + 14) /* DMA1 3  Interrupt        */
-#define IRQ_DMA1_4              (IVG_BASE + 15) /* DMA1 4  Interrupt        */
-#define IRQ_DMA1_5              (IVG_BASE + 16) /* DMA1 5  Interrupt        */
-#define IRQ_DMA1_6              (IVG_BASE + 17) /* DMA1 6  Interrupt        */
-#define IRQ_DMA1_7              (IVG_BASE + 18) /* DMA1 7  Interrupt        */
-#define IRQ_DMA1_8              (IVG_BASE + 19) /* DMA1 8  Interrupt        */
-#define IRQ_DMA1_9              (IVG_BASE + 20) /* DMA1 9  Interrupt        */
-#define IRQ_DMA1_10             (IVG_BASE + 21) /* DMA1 10 Interrupt        */
-#define IRQ_DMA1_11             (IVG_BASE + 22) /* DMA1 11 Interrupt        */
-/* IVG 9  */
-#define IRQ_DMA2_0              (IVG_BASE + 23) /* DMA2 0  (SPORT0 RX)      */
-#define IRQ_SPORT0_RX           IRQ_DMA2_0      /* DMA2 0  (SPORT0 RX)      */
-#define IRQ_DMA2_1              (IVG_BASE + 24) /* DMA2 1  (SPORT0 TX)      */
-#define IRQ_SPORT0_TX           IRQ_DMA2_1      /* DMA2 1  (SPORT0 TX)      */
-#define IRQ_DMA2_2              (IVG_BASE + 25) /* DMA2 2  (SPORT1 RX)      */
-#define IRQ_SPORT1_RX           IRQ_DMA2_2      /* DMA2 2  (SPORT1 RX)      */
-#define IRQ_DMA2_3              (IVG_BASE + 26) /* DMA2 3  (SPORT2 TX)      */
-#define IRQ_SPORT1_TX           IRQ_DMA2_3      /* DMA2 3  (SPORT2 TX)      */
-#define IRQ_DMA2_4              (IVG_BASE + 27) /* DMA2 4  (SPI)            */
-#define IRQ_SPI                 IRQ_DMA2_4      /* DMA2 4  (SPI)            */
-#define IRQ_DMA2_5              (IVG_BASE + 28) /* DMA2 5  (UART RX)        */
-#define IRQ_UART_RX             IRQ_DMA2_5      /* DMA2 5  (UART RX)        */
-#define IRQ_DMA2_6              (IVG_BASE + 29) /* DMA2 6  (UART TX)        */
-#define IRQ_UART_TX             IRQ_DMA2_6      /* DMA2 6  (UART TX)        */
-#define IRQ_DMA2_7              (IVG_BASE + 30) /* DMA2 7  Interrupt        */
-#define IRQ_DMA2_8              (IVG_BASE + 31) /* DMA2 8  Interrupt        */
-#define IRQ_DMA2_9              (IVG_BASE + 32) /* DMA2 9  Interrupt        */
-#define IRQ_DMA2_10             (IVG_BASE + 33) /* DMA2 10 Interrupt        */
-#define IRQ_DMA2_11             (IVG_BASE + 34) /* DMA2 11 Interrupt        */
-/* IVG 10 */
-#define IRQ_TIMER0              (IVG_BASE + 35) /* TIMER 0  Interrupt       */
-#define IRQ_TIMER1              (IVG_BASE + 36) /* TIMER 1  Interrupt       */
-#define IRQ_TIMER2              (IVG_BASE + 37) /* TIMER 2  Interrupt       */
-#define IRQ_TIMER3              (IVG_BASE + 38) /* TIMER 3  Interrupt       */
-#define IRQ_TIMER4              (IVG_BASE + 39) /* TIMER 4  Interrupt       */
-#define IRQ_TIMER5              (IVG_BASE + 40) /* TIMER 5  Interrupt       */
-#define IRQ_TIMER6              (IVG_BASE + 41) /* TIMER 6  Interrupt       */
-#define IRQ_TIMER7              (IVG_BASE + 42) /* TIMER 7  Interrupt       */
-#define IRQ_TIMER8              (IVG_BASE + 43) /* TIMER 8  Interrupt       */
-#define IRQ_TIMER9              (IVG_BASE + 44) /* TIMER 9  Interrupt       */
-#define IRQ_TIMER10             (IVG_BASE + 45) /* TIMER 10 Interrupt       */
-#define IRQ_TIMER11             (IVG_BASE + 46) /* TIMER 11 Interrupt       */
-/* IVG 11 */
-#define IRQ_PROG0_INTA          (IVG_BASE + 47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA           IRQ_PROG0_INTA  /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB          (IVG_BASE + 48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB           IRQ_PROG0_INTB  /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA          (IVG_BASE + 49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB          (IVG_BASE + 50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA          (IVG_BASE + 51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB          (IVG_BASE + 52) /* Programmable Flags2 B (8) */
-/* IVG 8  */
-#define IRQ_DMA1_WRRD0          (IVG_BASE + 53) /* MDMA1 0 write/read INT   */
-#define IRQ_DMA_WRRD0           IRQ_DMA1_WRRD0  /* MDMA1 0 write/read INT   */
-#define IRQ_MEM_DMA0            IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1          (IVG_BASE + 54) /* MDMA1 1 write/read INT   */
-#define IRQ_DMA_WRRD1           IRQ_DMA1_WRRD1  /* MDMA1 1 write/read INT   */
-#define IRQ_MEM_DMA1            IRQ_DMA1_WRRD1
-/* IVG 9  */
-#define IRQ_DMA2_WRRD0          (IVG_BASE + 55) /* MDMA2 0 write/read INT   */
-#define IRQ_MEM_DMA2            IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1          (IVG_BASE + 56) /* MDMA2 1 write/read INT   */
-#define IRQ_MEM_DMA3            IRQ_DMA2_WRRD1
-/* IVG 12 */
-#define IRQ_IMDMA_WRRD0         (IVG_BASE + 57) /* IMDMA 0 write/read INT   */
-#define IRQ_IMEM_DMA0           IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1         (IVG_BASE + 58) /* IMDMA 1 write/read INT   */
-#define IRQ_IMEM_DMA1           IRQ_IMDMA_WRRD1
-/* IVG 13 */
-#define IRQ_WATCH               (IVG_BASE + 59) /* Watch Dog Timer          */
-/* IVG 7  */
-#define IRQ_RESERVED_1          (IVG_BASE + 60) /* Reserved interrupt       */
-#define IRQ_RESERVED_2          (IVG_BASE + 61) /* Reserved interrupt       */
-#define IRQ_SUPPLE_0            (IVG_BASE + 62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1            (IVG_BASE + 63) /* supplemental interrupt 1 */
-
-#define IRQ_PF0                 73
-#define IRQ_PF1                 74
-#define IRQ_PF2                 75
-#define IRQ_PF3                 76
-#define IRQ_PF4                 77
-#define IRQ_PF5                 78
-#define IRQ_PF6                 79
-#define IRQ_PF7                 80
-#define IRQ_PF8                 81
-#define IRQ_PF9                 82
-#define IRQ_PF10                83
-#define IRQ_PF11                84
-#define IRQ_PF12                85
-#define IRQ_PF13                86
-#define IRQ_PF14                87
-#define IRQ_PF15                88
-#define IRQ_PF16                89
-#define IRQ_PF17                90
-#define IRQ_PF18                91
-#define IRQ_PF19                92
-#define IRQ_PF20                93
-#define IRQ_PF21                94
-#define IRQ_PF22                95
-#define IRQ_PF23                96
-#define IRQ_PF24                97
-#define IRQ_PF25                98
-#define IRQ_PF26                99
-#define IRQ_PF27                100
-#define IRQ_PF28                101
-#define IRQ_PF29                102
-#define IRQ_PF30                103
-#define IRQ_PF31                104
-#define IRQ_PF32                105
-#define IRQ_PF33                106
-#define IRQ_PF34                107
-#define IRQ_PF35                108
-#define IRQ_PF36                109
-#define IRQ_PF37                110
-#define IRQ_PF38                111
-#define IRQ_PF39                112
-#define IRQ_PF40                113
-#define IRQ_PF41                114
-#define IRQ_PF42                115
-#define IRQ_PF43                116
-#define IRQ_PF44                117
-#define IRQ_PF45                118
-#define IRQ_PF46                119
-#define IRQ_PF47                120
-
-#define GPIO_IRQ_BASE           IRQ_PF0
-
-#define NR_IRQS                 (IRQ_PF47 + 1)
-
-#define IVG7                    7
-#define IVG8                    8
-#define IVG9                    9
-#define IVG10                   10
-#define IVG11                   11
-#define IVG12                   12
-#define IVG13                   13
-#define IVG14                   14
-#define IVG15                   15
-
-/*
- * DEFAULT PRIORITIES:
- */
-
-#define CONFIG_DEF_PLL_WAKEUP           7
-#define CONFIG_DEF_DMA1_ERROR           7
-#define CONFIG_DEF_DMA2_ERROR           7
-#define CONFIG_DEF_IMDMA_ERROR          7
-#define CONFIG_DEF_PPI1_ERROR           7
-#define CONFIG_DEF_PPI2_ERROR           7
-#define CONFIG_DEF_SPORT0_ERROR         7
-#define CONFIG_DEF_SPORT1_ERROR         7
-#define CONFIG_DEF_SPI_ERROR            7
-#define CONFIG_DEF_UART_ERROR           7
-#define CONFIG_DEF_RESERVED_ERROR       7
-#define CONFIG_DEF_DMA1_0               8
-#define CONFIG_DEF_DMA1_1               8
-#define CONFIG_DEF_DMA1_2               8
-#define CONFIG_DEF_DMA1_3               8
-#define CONFIG_DEF_DMA1_4               8
-#define CONFIG_DEF_DMA1_5               8
-#define CONFIG_DEF_DMA1_6               8
-#define CONFIG_DEF_DMA1_7               8
-#define CONFIG_DEF_DMA1_8               8
-#define CONFIG_DEF_DMA1_9               8
-#define CONFIG_DEF_DMA1_10              8
-#define CONFIG_DEF_DMA1_11              8
-#define CONFIG_DEF_DMA2_0               9
-#define CONFIG_DEF_DMA2_1               9
-#define CONFIG_DEF_DMA2_2               9
-#define CONFIG_DEF_DMA2_3               9
-#define CONFIG_DEF_DMA2_4               9
-#define CONFIG_DEF_DMA2_5               9
-#define CONFIG_DEF_DMA2_6               9
-#define CONFIG_DEF_DMA2_7               9
-#define CONFIG_DEF_DMA2_8               9
-#define CONFIG_DEF_DMA2_9               9
-#define CONFIG_DEF_DMA2_10              9
-#define CONFIG_DEF_DMA2_11              9
-#define CONFIG_DEF_TIMER0               10
-#define CONFIG_DEF_TIMER1               10
-#define CONFIG_DEF_TIMER2               10
-#define CONFIG_DEF_TIMER3               10
-#define CONFIG_DEF_TIMER4               10
-#define CONFIG_DEF_TIMER5               10
-#define CONFIG_DEF_TIMER6               10
-#define CONFIG_DEF_TIMER7               10
-#define CONFIG_DEF_TIMER8               10
-#define CONFIG_DEF_TIMER9               10
-#define CONFIG_DEF_TIMER10              10
-#define CONFIG_DEF_TIMER11              10
-#define CONFIG_DEF_PROG0_INTA           11
-#define CONFIG_DEF_PROG0_INTB           11
-#define CONFIG_DEF_PROG1_INTA           11
-#define CONFIG_DEF_PROG1_INTB           11
-#define CONFIG_DEF_PROG2_INTA           11
-#define CONFIG_DEF_PROG2_INTB           11
-#define CONFIG_DEF_DMA1_WRRD0           8
-#define CONFIG_DEF_DMA1_WRRD1           8
-#define CONFIG_DEF_DMA2_WRRD0           9
-#define CONFIG_DEF_DMA2_WRRD1           9
-#define CONFIG_DEF_IMDMA_WRRD0          12
-#define CONFIG_DEF_IMDMA_WRRD1          12
-#define CONFIG_DEF_WATCH                13
-#define CONFIG_DEF_RESERVED_1           7
-#define CONFIG_DEF_RESERVED_2           7
-#define CONFIG_DEF_SUPPLE_0             7
-#define CONFIG_DEF_SUPPLE_1             7
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS                      0
-#define IRQ_DMA1_ERROR_POS                      4
-#define IRQ_DMA2_ERROR_POS                      8
-#define IRQ_IMDMA_ERROR_POS                     12
-#define IRQ_PPI0_ERROR_POS                      16
-#define IRQ_PPI1_ERROR_POS                      20
-#define IRQ_SPORT0_ERROR_POS            24
-#define IRQ_SPORT1_ERROR_POS            28
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS                       0
-#define IRQ_UART_ERROR_POS                      4
-#define IRQ_RESERVED_ERROR_POS          8
-#define IRQ_DMA1_0_POS                  12
-#define IRQ_DMA1_1_POS                  16
-#define IRQ_DMA1_2_POS                  20
-#define IRQ_DMA1_3_POS                  24
-#define IRQ_DMA1_4_POS                  28
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS                  0
-#define IRQ_DMA1_6_POS                  4
-#define IRQ_DMA1_7_POS                  8
-#define IRQ_DMA1_8_POS                  12
-#define IRQ_DMA1_9_POS                  16
-#define IRQ_DMA1_10_POS                 20
-#define IRQ_DMA1_11_POS                 24
-#define IRQ_DMA2_0_POS                  28
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS                  0
-#define IRQ_DMA2_2_POS                  4
-#define IRQ_DMA2_3_POS                  8
-#define IRQ_DMA2_4_POS                  12
-#define IRQ_DMA2_5_POS                  16
-#define IRQ_DMA2_6_POS                  20
-#define IRQ_DMA2_7_POS                  24
-#define IRQ_DMA2_8_POS                  28
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS                  0
-#define IRQ_DMA2_10_POS                 4
-#define IRQ_DMA2_11_POS                 8
-#define IRQ_TIMER0_POS                  12
-#define IRQ_TIMER1_POS                  16
-#define IRQ_TIMER2_POS                  20
-#define IRQ_TIMER3_POS                  24
-#define IRQ_TIMER4_POS                  28
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS                  0
-#define IRQ_TIMER6_POS                  4
-#define IRQ_TIMER7_POS                  8
-#define IRQ_TIMER8_POS                  12
-#define IRQ_TIMER9_POS                  16
-#define IRQ_TIMER10_POS                 20
-#define IRQ_TIMER11_POS                 24
-#define IRQ_PROG0_INTA_POS                      28
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS                      0
-#define IRQ_PROG1_INTA_POS                      4
-#define IRQ_PROG1_INTB_POS                      8
-#define IRQ_PROG2_INTA_POS                      12
-#define IRQ_PROG2_INTB_POS                      16
-#define IRQ_DMA1_WRRD0_POS                      20
-#define IRQ_DMA1_WRRD1_POS                      24
-#define IRQ_DMA2_WRRD0_POS                      28
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS                      0
-#define IRQ_IMDMA_WRRD0_POS                     4
-#define IRQ_IMDMA_WRRD1_POS                     8
-#define IRQ_WDTIMER_POS                 12
-#define IRQ_RESERVED_1_POS                      16
-#define IRQ_RESERVED_2_POS                      20
-#define IRQ_SUPPLE_0_POS                        24
-#define IRQ_SUPPLE_1_POS                        28
-
-#endif                          /* _BF561_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf561/mem_init.h b/include/asm-blackfin/mach-bf561/mem_init.h
deleted file mode 100644
index e163260bca18..000000000000
--- a/include/asm-blackfin/mach-bf561/mem_init.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC8M32B2B5_7)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
deleted file mode 100644
index c26d8486cc4b..000000000000
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Memory MAP
- * Common header file for blackfin BF561 of processors.
- */
-
-#ifndef _MEM_MAP_561_H_
-#define _MEM_MAP_561_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x800
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF561 processors */
-
-#ifdef CONFIG_BF561
-#define L1_CODE_START     0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0x4000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Level 2 Memory */
-#define L2_START                0xFEB00000
-#define L2_LENGTH               0x20000
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
deleted file mode 100644
index a6ee8206efb6..000000000000
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ /dev/null
@@ -1,89 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK      (P_DONTCARE)
-#define P_PPI0_FS1      (P_DONTCARE)
-#define P_PPI0_FS2      (P_DONTCARE)
-#define P_PPI0_FS3      (P_DONTCARE)
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0       (P_DONTCARE)
-#define P_PPI0_D1       (P_DONTCARE)
-#define P_PPI0_D2       (P_DONTCARE)
-#define P_PPI0_D3       (P_DONTCARE)
-#define P_PPI0_D4       (P_DONTCARE)
-#define P_PPI0_D5       (P_DONTCARE)
-#define P_PPI0_D6       (P_DONTCARE)
-#define P_PPI0_D7       (P_DONTCARE)
-#define P_PPI1_CLK      (P_DONTCARE)
-#define P_PPI1_FS1      (P_DONTCARE)
-#define P_PPI1_FS2      (P_DONTCARE)
-#define P_PPI1_FS3      (P_DONTCARE)
-#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0       (P_DONTCARE)
-#define P_PPI1_D1       (P_DONTCARE)
-#define P_PPI1_D2       (P_DONTCARE)
-#define P_PPI1_D3       (P_DONTCARE)
-#define P_PPI1_D4       (P_DONTCARE)
-#define P_PPI1_D5       (P_DONTCARE)
-#define P_PPI1_D6       (P_DONTCARE)
-#define P_PPI1_D7       (P_DONTCARE)
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI  (P_DONTCARE)
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI  (P_DONTCARE)
-#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11         (P_DONTCARE)
-#define P_TMR10         (P_DONTCARE)
-#define P_TMR9          (P_DONTCARE)
-#define P_TMR8          (P_DONTCARE)
-#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI     (P_DONTCARE)
-#define P_SPI0_MISO     (P_DONTCARE)
-#define P_SPI0_SCK      (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
deleted file mode 100644
index ede210eca4ec..000000000000
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,336 +0,0 @@
- /*
-  * File:        include/asm-blackfin/mach-common/cdef_LPBlackfin.h
-  * Based on:
-  * Author:      unknown
-  *              COPYRIGHT 2005 Analog Devices
-  * Created:     ?
-  * Description:
-  *
-  * Modified:
-  *
-  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2, or (at your option)
-  * any later version.
-  *
-  * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
-  *
-  * You should have received a copy of the GNU General Public License
-  * along with this program; see the file COPYING.
-  * If not, write to the Free Software Foundation,
-  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-  */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/*Cache & SRAM Memory*/
-#define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
-#define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
-#define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
-#if ANOMALY_05000125
-extern void bfin_write_DMEM_CONTROL(unsigned int val);
-#else
-#define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
-#endif
-#define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
-#define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val)     bfin_write32(DCPLB_FAULT_ADDR,val)
-/*
-#define MMR_TIMEOUT            0xFFE00010
-*/
-#define bfin_read_DCPLB_ADDR0()              bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)          bfin_write32(DCPLB_ADDR0,val)
-#define bfin_read_DCPLB_ADDR1()              bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)          bfin_write32(DCPLB_ADDR1,val)
-#define bfin_read_DCPLB_ADDR2()              bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)          bfin_write32(DCPLB_ADDR2,val)
-#define bfin_read_DCPLB_ADDR3()              bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)          bfin_write32(DCPLB_ADDR3,val)
-#define bfin_read_DCPLB_ADDR4()              bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)          bfin_write32(DCPLB_ADDR4,val)
-#define bfin_read_DCPLB_ADDR5()              bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)          bfin_write32(DCPLB_ADDR5,val)
-#define bfin_read_DCPLB_ADDR6()              bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)          bfin_write32(DCPLB_ADDR6,val)
-#define bfin_read_DCPLB_ADDR7()              bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)          bfin_write32(DCPLB_ADDR7,val)
-#define bfin_read_DCPLB_ADDR8()              bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)          bfin_write32(DCPLB_ADDR8,val)
-#define bfin_read_DCPLB_ADDR9()              bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)          bfin_write32(DCPLB_ADDR9,val)
-#define bfin_read_DCPLB_ADDR10()             bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)         bfin_write32(DCPLB_ADDR10,val)
-#define bfin_read_DCPLB_ADDR11()             bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)         bfin_write32(DCPLB_ADDR11,val)
-#define bfin_read_DCPLB_ADDR12()             bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)         bfin_write32(DCPLB_ADDR12,val)
-#define bfin_read_DCPLB_ADDR13()             bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)         bfin_write32(DCPLB_ADDR13,val)
-#define bfin_read_DCPLB_ADDR14()             bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)         bfin_write32(DCPLB_ADDR14,val)
-#define bfin_read_DCPLB_ADDR15()             bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)         bfin_write32(DCPLB_ADDR15,val)
-#define bfin_read_DCPLB_DATA0()              bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)          bfin_write32(DCPLB_DATA0,val)
-#define bfin_read_DCPLB_DATA1()              bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)          bfin_write32(DCPLB_DATA1,val)
-#define bfin_read_DCPLB_DATA2()              bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)          bfin_write32(DCPLB_DATA2,val)
-#define bfin_read_DCPLB_DATA3()              bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)          bfin_write32(DCPLB_DATA3,val)
-#define bfin_read_DCPLB_DATA4()              bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)          bfin_write32(DCPLB_DATA4,val)
-#define bfin_read_DCPLB_DATA5()              bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)          bfin_write32(DCPLB_DATA5,val)
-#define bfin_read_DCPLB_DATA6()              bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)          bfin_write32(DCPLB_DATA6,val)
-#define bfin_read_DCPLB_DATA7()              bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)          bfin_write32(DCPLB_DATA7,val)
-#define bfin_read_DCPLB_DATA8()              bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)          bfin_write32(DCPLB_DATA8,val)
-#define bfin_read_DCPLB_DATA9()              bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)          bfin_write32(DCPLB_DATA9,val)
-#define bfin_read_DCPLB_DATA10()             bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)         bfin_write32(DCPLB_DATA10,val)
-#define bfin_read_DCPLB_DATA11()             bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)         bfin_write32(DCPLB_DATA11,val)
-#define bfin_read_DCPLB_DATA12()             bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)         bfin_write32(DCPLB_DATA12,val)
-#define bfin_read_DCPLB_DATA13()             bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)         bfin_write32(DCPLB_DATA13,val)
-#define bfin_read_DCPLB_DATA14()             bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)         bfin_write32(DCPLB_DATA14,val)
-#define bfin_read_DCPLB_DATA15()             bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)         bfin_write32(DCPLB_DATA15,val)
-#define bfin_read_DTEST_COMMAND()            bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)        bfin_write32(DTEST_COMMAND,val)
-/*
-#define DTEST_INDEX            0xFFE00304
-*/
-#define bfin_read_DTEST_DATA0()              bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)          bfin_write32(DTEST_DATA0,val)
-#define bfin_read_DTEST_DATA1()              bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)          bfin_write32(DTEST_DATA1,val)
-/*
-#define DTEST_DATA2            0xFFE00408
-#define DTEST_DATA3            0xFFE0040C
-*/
-#define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
-#if ANOMALY_05000125
-extern void bfin_write_IMEM_CONTROL(unsigned int val);
-#else
-#define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
-#endif
-#define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
-#define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val)     bfin_write32(ICPLB_FAULT_ADDR,val)
-#define bfin_read_ICPLB_ADDR0()              bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)          bfin_write32(ICPLB_ADDR0,val)
-#define bfin_read_ICPLB_ADDR1()              bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)          bfin_write32(ICPLB_ADDR1,val)
-#define bfin_read_ICPLB_ADDR2()              bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)          bfin_write32(ICPLB_ADDR2,val)
-#define bfin_read_ICPLB_ADDR3()              bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)          bfin_write32(ICPLB_ADDR3,val)
-#define bfin_read_ICPLB_ADDR4()              bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)          bfin_write32(ICPLB_ADDR4,val)
-#define bfin_read_ICPLB_ADDR5()              bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)          bfin_write32(ICPLB_ADDR5,val)
-#define bfin_read_ICPLB_ADDR6()              bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)          bfin_write32(ICPLB_ADDR6,val)
-#define bfin_read_ICPLB_ADDR7()              bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)          bfin_write32(ICPLB_ADDR7,val)
-#define bfin_read_ICPLB_ADDR8()              bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)          bfin_write32(ICPLB_ADDR8,val)
-#define bfin_read_ICPLB_ADDR9()              bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)          bfin_write32(ICPLB_ADDR9,val)
-#define bfin_read_ICPLB_ADDR10()             bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)         bfin_write32(ICPLB_ADDR10,val)
-#define bfin_read_ICPLB_ADDR11()             bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)         bfin_write32(ICPLB_ADDR11,val)
-#define bfin_read_ICPLB_ADDR12()             bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)         bfin_write32(ICPLB_ADDR12,val)
-#define bfin_read_ICPLB_ADDR13()             bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)         bfin_write32(ICPLB_ADDR13,val)
-#define bfin_read_ICPLB_ADDR14()             bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)         bfin_write32(ICPLB_ADDR14,val)
-#define bfin_read_ICPLB_ADDR15()             bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)         bfin_write32(ICPLB_ADDR15,val)
-#define bfin_read_ICPLB_DATA0()              bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)          bfin_write32(ICPLB_DATA0,val)
-#define bfin_read_ICPLB_DATA1()              bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)          bfin_write32(ICPLB_DATA1,val)
-#define bfin_read_ICPLB_DATA2()              bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)          bfin_write32(ICPLB_DATA2,val)
-#define bfin_read_ICPLB_DATA3()              bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)          bfin_write32(ICPLB_DATA3,val)
-#define bfin_read_ICPLB_DATA4()              bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)          bfin_write32(ICPLB_DATA4,val)
-#define bfin_read_ICPLB_DATA5()              bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)          bfin_write32(ICPLB_DATA5,val)
-#define bfin_read_ICPLB_DATA6()              bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)          bfin_write32(ICPLB_DATA6,val)
-#define bfin_read_ICPLB_DATA7()              bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)          bfin_write32(ICPLB_DATA7,val)
-#define bfin_read_ICPLB_DATA8()              bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)          bfin_write32(ICPLB_DATA8,val)
-#define bfin_read_ICPLB_DATA9()              bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)          bfin_write32(ICPLB_DATA9,val)
-#define bfin_read_ICPLB_DATA10()             bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)         bfin_write32(ICPLB_DATA10,val)
-#define bfin_read_ICPLB_DATA11()             bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)         bfin_write32(ICPLB_DATA11,val)
-#define bfin_read_ICPLB_DATA12()             bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)         bfin_write32(ICPLB_DATA12,val)
-#define bfin_read_ICPLB_DATA13()             bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)         bfin_write32(ICPLB_DATA13,val)
-#define bfin_read_ICPLB_DATA14()             bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)         bfin_write32(ICPLB_DATA14,val)
-#define bfin_read_ICPLB_DATA15()             bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)         bfin_write32(ICPLB_DATA15,val)
-#define bfin_read_ITEST_COMMAND()            bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)        bfin_write32(ITEST_COMMAND,val)
-#if 0
-#define ITEST_INDEX            0xFFE01304   /* Instruction Test Index Register */
-#endif
-#define bfin_read_ITEST_DATA0()              bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)          bfin_write32(ITEST_DATA0,val)
-#define bfin_read_ITEST_DATA1()              bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)          bfin_write32(ITEST_DATA1,val)
-
-/* Event/Interrupt Registers*/
-
-#define bfin_read_EVT0()                     bfin_read32(EVT0)
-#define bfin_write_EVT0(val)                 bfin_write32(EVT0,val)
-#define bfin_read_EVT1()                     bfin_read32(EVT1)
-#define bfin_write_EVT1(val)                 bfin_write32(EVT1,val)
-#define bfin_read_EVT2()                     bfin_read32(EVT2)
-#define bfin_write_EVT2(val)                 bfin_write32(EVT2,val)
-#define bfin_read_EVT3()                     bfin_read32(EVT3)
-#define bfin_write_EVT3(val)                 bfin_write32(EVT3,val)
-#define bfin_read_EVT4()                     bfin_read32(EVT4)
-#define bfin_write_EVT4(val)                 bfin_write32(EVT4,val)
-#define bfin_read_EVT5()                     bfin_read32(EVT5)
-#define bfin_write_EVT5(val)                 bfin_write32(EVT5,val)
-#define bfin_read_EVT6()                     bfin_read32(EVT6)
-#define bfin_write_EVT6(val)                 bfin_write32(EVT6,val)
-#define bfin_read_EVT7()                     bfin_read32(EVT7)
-#define bfin_write_EVT7(val)                 bfin_write32(EVT7,val)
-#define bfin_read_EVT8()                     bfin_read32(EVT8)
-#define bfin_write_EVT8(val)                 bfin_write32(EVT8,val)
-#define bfin_read_EVT9()                     bfin_read32(EVT9)
-#define bfin_write_EVT9(val)                 bfin_write32(EVT9,val)
-#define bfin_read_EVT10()                    bfin_read32(EVT10)
-#define bfin_write_EVT10(val)                bfin_write32(EVT10,val)
-#define bfin_read_EVT11()                    bfin_read32(EVT11)
-#define bfin_write_EVT11(val)                bfin_write32(EVT11,val)
-#define bfin_read_EVT12()                    bfin_read32(EVT12)
-#define bfin_write_EVT12(val)                bfin_write32(EVT12,val)
-#define bfin_read_EVT13()                    bfin_read32(EVT13)
-#define bfin_write_EVT13(val)                bfin_write32(EVT13,val)
-#define bfin_read_EVT14()                    bfin_read32(EVT14)
-#define bfin_write_EVT14(val)                bfin_write32(EVT14,val)
-#define bfin_read_EVT15()                    bfin_read32(EVT15)
-#define bfin_write_EVT15(val)                bfin_write32(EVT15,val)
-#define bfin_read_IMASK()                    bfin_read32(IMASK)
-#define bfin_write_IMASK(val)                bfin_write32(IMASK,val)
-#define bfin_read_IPEND()                    bfin_read32(IPEND)
-#define bfin_write_IPEND(val)                bfin_write32(IPEND,val)
-#define bfin_read_ILAT()                     bfin_read32(ILAT)
-#define bfin_write_ILAT(val)                 bfin_write32(ILAT,val)
-
-/*Core Timer Registers*/
-#define bfin_read_TCNTL()                    bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)                bfin_write32(TCNTL,val)
-#define bfin_read_TPERIOD()                  bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)              bfin_write32(TPERIOD,val)
-#define bfin_read_TSCALE()                   bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)               bfin_write32(TSCALE,val)
-#define bfin_read_TCOUNT()                   bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)               bfin_write32(TCOUNT,val)
-
-/*Debug/MP/Emulation Registers*/
-#define bfin_read_DSPID()                    bfin_read32(DSPID)
-#define bfin_write_DSPID(val)                bfin_write32(DSPID,val)
-#define bfin_read_DBGCTL()                   bfin_read32(DBGCTL)
-#define bfin_write_DBGCTL(val)               bfin_write32(DBGCTL,val)
-#define bfin_read_DBGSTAT()                  bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val)              bfin_write32(DBGSTAT,val)
-#define bfin_read_EMUDAT()                   bfin_read32(EMUDAT)
-#define bfin_write_EMUDAT(val)               bfin_write32(EMUDAT,val)
-
-/*Trace Buffer Registers*/
-#define bfin_read_TBUFCTL()                  bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)              bfin_write32(TBUFCTL,val)
-#define bfin_read_TBUFSTAT()                 bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)             bfin_write32(TBUFSTAT,val)
-#define bfin_read_TBUF()                     bfin_read32(TBUF)
-#define bfin_write_TBUF(val)                 bfin_write32(TBUF,val)
-
-/*Watch Point Control Registers*/
-#define bfin_read_WPIACTL()                  bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val)              bfin_write32(WPIACTL,val)
-#define bfin_read_WPIA0()                    bfin_read32(WPIA0)
-#define bfin_write_WPIA0(val)                bfin_write32(WPIA0,val)
-#define bfin_read_WPIA1()                    bfin_read32(WPIA1)
-#define bfin_write_WPIA1(val)                bfin_write32(WPIA1,val)
-#define bfin_read_WPIA2()                    bfin_read32(WPIA2)
-#define bfin_write_WPIA2(val)                bfin_write32(WPIA2,val)
-#define bfin_read_WPIA3()                    bfin_read32(WPIA3)
-#define bfin_write_WPIA3(val)                bfin_write32(WPIA3,val)
-#define bfin_read_WPIA4()                    bfin_read32(WPIA4)
-#define bfin_write_WPIA4(val)                bfin_write32(WPIA4,val)
-#define bfin_read_WPIA5()                    bfin_read32(WPIA5)
-#define bfin_write_WPIA5(val)                bfin_write32(WPIA5,val)
-#define bfin_read_WPIACNT0()                 bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val)             bfin_write32(WPIACNT0,val)
-#define bfin_read_WPIACNT1()                 bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val)             bfin_write32(WPIACNT1,val)
-#define bfin_read_WPIACNT2()                 bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val)             bfin_write32(WPIACNT2,val)
-#define bfin_read_WPIACNT3()                 bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val)             bfin_write32(WPIACNT3,val)
-#define bfin_read_WPIACNT4()                 bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val)             bfin_write32(WPIACNT4,val)
-#define bfin_read_WPIACNT5()                 bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val)             bfin_write32(WPIACNT5,val)
-#define bfin_read_WPDACTL()                  bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val)              bfin_write32(WPDACTL,val)
-#define bfin_read_WPDA0()                    bfin_read32(WPDA0)
-#define bfin_write_WPDA0(val)                bfin_write32(WPDA0,val)
-#define bfin_read_WPDA1()                    bfin_read32(WPDA1)
-#define bfin_write_WPDA1(val)                bfin_write32(WPDA1,val)
-#define bfin_read_WPDACNT0()                 bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val)             bfin_write32(WPDACNT0,val)
-#define bfin_read_WPDACNT1()                 bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val)             bfin_write32(WPDACNT1,val)
-#define bfin_read_WPSTAT()                   bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val)               bfin_write32(WPSTAT,val)
-
-/*Performance Monitor Registers*/
-#define bfin_read_PFCTL()                    bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)                bfin_write32(PFCTL,val)
-#define bfin_read_PFCNTR0()                  bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)              bfin_write32(PFCNTR0,val)
-#define bfin_read_PFCNTR1()                  bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)              bfin_write32(PFCNTR1,val)
-
-/*
-#define IPRIO                  0xFFE02110
-*/
-
-#endif                          /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h
deleted file mode 100644
index 033bba92d61c..000000000000
--- a/include/asm-blackfin/mach-common/clocks.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-common/clocks.h
- * Based on:     include/asm-blackfin/mach-bf537/bf537.h
- * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
- *
- * Created:      25Jul07
- * Description:  Common Clock definitions for various kernel files
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _BFIN_CLOCKS_H
-#define _BFIN_CLOCKS_H
-
-#ifdef CONFIG_CCLK_DIV_1
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-# define CONFIG_CCLK_DIV 1
-#endif
-
-#ifdef CONFIG_CCLK_DIV_2
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-# define CONFIG_CCLK_DIV 2
-#endif
-
-#ifdef CONFIG_CCLK_DIV_4
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-# define CONFIG_CCLK_DIV 4
-#endif
-
-#ifdef CONFIG_CCLK_DIV_8
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-# define CONFIG_CCLK_DIV 8
-#endif
-
-#ifndef CONFIG_PLL_BYPASS
-# ifndef CONFIG_CLKIN_HALF
-#  define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-#  define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-# endif
-
-# define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-# define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-
-#else
-# define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ)
-# define CONFIG_CCLK_HZ  (CONFIG_CLKIN_HZ)
-# define CONFIG_SCLK_HZ  (CONFIG_CLKIN_HZ)
-# define CONFIG_VCO_MULT 0
-#endif
-
-#endif
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
deleted file mode 100644
index c0e630edfb9a..000000000000
--- a/include/asm-blackfin/mach-common/context.S
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * File:         arch/blackfin/kernel/context.S
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-/*
- * NOTE!  The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/*
- * Code to save processor context.
- *  We even save the register which are preserved by a function call
- *       - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
-        [--sp] = SYSCFG;
-
-        [--sp] = P0;    /*orig_p0*/
-        [--sp] = R0;    /*orig_r0*/
-
-        [--sp] = ( R7:0, P5:0 );
-        [--sp] = fp;
-        [--sp] = usp;
-
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-
-        [--sp] = ASTAT;
-
-        [--sp] = r0;    /* Skip reserved */
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
-        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
-        [--sp] = SEQSTAT;
-        [--sp] = r0;    /* Skip IPEND as well. */
-        /* Switch to other method of keeping interrupts disabled.  */
-#ifdef CONFIG_DEBUG_HWERR
-        r0 = 0x3f;
-        sti r0;
-#else
-        cli r0;
-#endif
-        [--sp] = RETI;  /*orig_pc*/
-        /* Clear all L registers.  */
-        r0 = 0 (x);
-        l0 = r0;
-        l1 = r0;
-        l2 = r0;
-        l3 = r0;
-.endm
-
-.macro save_context_syscall
-        [--sp] = SYSCFG;
-
-        [--sp] = P0;    /*orig_p0*/
-        [--sp] = R0;    /*orig_r0*/
-        [--sp] = ( R7:0, P5:0 );
-        [--sp] = fp;
-        [--sp] = usp;
-
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-
-        [--sp] = ASTAT;
-
-        [--sp] = r0;    /* Skip reserved */
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
-        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
-        [--sp] = SEQSTAT;
-        [--sp] = r0;    /* Skip IPEND as well. */
-        [--sp] = RETI;  /*orig_pc*/
-        /* Clear all L registers.  */
-        r0 = 0 (x);
-        l0 = r0;
-        l1 = r0;
-        l2 = r0;
-        l3 = r0;
-.endm
-
-.macro save_context_no_interrupts
-        [--sp] = SYSCFG;
-        [--sp] = P0;    /* orig_p0 */
-        [--sp] = R0;    /* orig_r0 */
-        [--sp] = ( R7:0, P5:0 );
-        [--sp] = fp;
-        [--sp] = usp;
-
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-
-        [--sp] = ASTAT;
-
-#ifdef CONFIG_KGDB
-        fp     = 0(Z);
-        r1     = sp;
-        r1    += 60;
-        r1    += 60;
-        r1    += 60;
-        [--sp] = r1;
-#else
-        [--sp] = r0;    /* Skip reserved */
-#endif
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
-        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
-        [--sp] = SEQSTAT;
-#ifdef CONFIG_KGDB
-        r1.l = lo(IPEND);
-        r1.h = hi(IPEND);
-        [--sp] = r1;
-#else
-        [--sp] = r0;    /* Skip IPEND as well. */
-#endif
-        [--sp] = r0;  /*orig_pc*/
-        /* Clear all L registers.  */
-        r0 = 0 (x);
-        l0 = r0;
-        l1 = r0;
-        l2 = r0;
-        l3 = r0;
-.endm
-
-.macro restore_context_no_interrupts
-        sp += 4;        /* Skip orig_pc */
-        sp += 4;        /* Skip IPEND */
-        SEQSTAT = [sp++];
-        RETE = [sp++];
-        RETN = [sp++];
-        RETX = [sp++];
-        r0 = [sp++];
-        RETI = r0;      /* Restore RETI indirectly when in exception */
-        RETS = [sp++];
-
-        sp += 4;        /* Skip Reserved */
-
-        ASTAT = [sp++];
-
-        LB1 = [sp++];
-        LB0 = [sp++];
-        LT1 = [sp++];
-        LT0 = [sp++];
-        LC1 = [sp++];
-        LC0 = [sp++];
-
-        a1.w = [sp++];
-        a1.x = [sp++];
-        a0.w = [sp++];
-        a0.x = [sp++];
-        b3 = [sp++];
-        b2 = [sp++];
-        b1 = [sp++];
-        b0 = [sp++];
-
-        l3 = [sp++];
-        l2 = [sp++];
-        l1 = [sp++];
-        l0 = [sp++];
-
-        m3 = [sp++];
-        m2 = [sp++];
-        m1 = [sp++];
-        m0 = [sp++];
-
-        i3 = [sp++];
-        i2 = [sp++];
-        i1 = [sp++];
-        i0 = [sp++];
-
-        sp += 4;
-        fp = [sp++];
-
-        ( R7 : 0, P5 : 0) = [ SP ++ ];
-        sp += 8;        /* Skip orig_r0/orig_p0 */
-        SYSCFG = [sp++];
-.endm
-
-.macro restore_context_with_interrupts
-        sp += 4;        /* Skip orig_pc */
-        sp += 4;        /* Skip IPEND */
-        SEQSTAT = [sp++];
-        RETE = [sp++];
-        RETN = [sp++];
-        RETX = [sp++];
-        RETI = [sp++];
-        RETS = [sp++];
-
-        p0.h = _irq_flags;
-        p0.l = _irq_flags;
-        r0 = [p0];
-        sti r0;
-
-        sp += 4;        /* Skip Reserved */
-
-        ASTAT = [sp++];
-
-        LB1 = [sp++];
-        LB0 = [sp++];
-        LT1 = [sp++];
-        LT0 = [sp++];
-        LC1 = [sp++];
-        LC0 = [sp++];
-
-        a1.w = [sp++];
-        a1.x = [sp++];
-        a0.w = [sp++];
-        a0.x = [sp++];
-        b3 = [sp++];
-        b2 = [sp++];
-        b1 = [sp++];
-        b0 = [sp++];
-
-        l3 = [sp++];
-        l2 = [sp++];
-        l1 = [sp++];
-        l0 = [sp++];
-
-        m3 = [sp++];
-        m2 = [sp++];
-        m1 = [sp++];
-        m0 = [sp++];
-
-        i3 = [sp++];
-        i2 = [sp++];
-        i1 = [sp++];
-        i0 = [sp++];
-
-        sp += 4;
-        fp = [sp++];
-
-        ( R7 : 0, P5 : 0) = [ SP ++ ];
-        sp += 8;        /* Skip orig_r0/orig_p0 */
-        csync;
-        SYSCFG = [sp++];
-        csync;
-.endm
-
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
deleted file mode 100644
index e8967f6124f7..000000000000
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ /dev/null
@@ -1,712 +0,0 @@
- /*
-  * File:        include/asm-blackfin/mach-common/def_LPBlackfin.h
-  * Based on:
-  * Author:      unknown
-  *              COPYRIGHT 2005 Analog Devices
-  * Created:     ?
-  * Description:
-  *
-  * Modified:
-  *
-  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2, or (at your option)
-  * any later version.
-  *
-  * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
-  *
-  * You should have received a copy of the GNU General Public License
-  * along with this program; see the file COPYING.
-  * If not, write to the Free Software Foundation,
-  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-  */
-
-/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#include <asm/mach/anomaly.h>
-
-#define MK_BMSK_(x) (1<<x)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define bfin_read8(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = b[%1] (z);" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_read16(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = w[%1] (z);" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_read32(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = [%1];" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_write8(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "b[%0] = %1;" \
-                : \
-                : "a" (addr), "d" ((uint8_t)(val)) \
-                : "memory" \
-        )
-
-#define bfin_write16(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "w[%0] = %1;" \
-                : \
-                : "a" (addr), "d" ((uint16_t)(val)) \
-                : "memory" \
-        )
-
-#define bfin_write32(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "[%0] = %1;" \
-                : \
-                : "a" (addr), "d" (val) \
-                : "memory" \
-        )
-
-#endif /* __ASSEMBLY__ */
-
-/**************************************************
- * System Register Bits
- **************************************************/
-
-/**************************************************
- * ASTAT register
- **************************************************/
-
-/* definitions of ASTAT bit positions*/
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ_P         0x00000000
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN_P         0x00000001
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC_P         0x00000005
-/*Quotient Bit*/
-#define ASTAT_AQ_P         0x00000006
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD_P    0x00000008
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_P        0x0000000C
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY_P   0x00000002
-/*Result of last ALU1 operation generated a carry*/
-#define ASTAT_AC1_P        0x0000000D
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0_P        0x00000010
-/*Sticky version of ASTAT_AV0 */
-#define ASTAT_AV0S_P       0x00000011
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1_P        0x00000012
-/*Sticky version of ASTAT_AV1 */
-#define ASTAT_AV1S_P       0x00000013
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_P          0x00000018
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_COPY_P     0x00000003
-/*Sticky version of ASTAT_V*/
-#define ASTAT_VS_P         0x00000019
-
-/* Masks */
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)
-/*Quotient Bit*/
-#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)
-/*Overflow Bit*/
-#define ASTAT_V            MK_BMSK_(ASTAT_V_P)
-/*Overflow Bit*/
-#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)
-
-/**************************************************
- *   SEQSTAT register
- **************************************************/
-
-/* Bit Positions  */
-#define SEQSTAT_EXCAUSE0_P      0x00000000      /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P      0x00000001      /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P      0x00000002      /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P      0x00000003      /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P      0x00000004      /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P      0x00000005      /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P      0x0000000C      /* Pending idle mode request,
-                                                 * set by IDLE instruction.
-                                                 */
-#define SEQSTAT_SFTRESET_P      0x0000000D      /* Indicates whether the last
-                                                 * reset was a software reset
-                                                 * (=1)
-                                                 */
-#define SEQSTAT_HWERRCAUSE0_P   0x0000000E      /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P   0x0000000F      /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P   0x00000010      /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P   0x00000011      /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P   0x00000012      /* Last hw error cause bit 4 */
-/* Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE        (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
-                                0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET       (MK_BMSK_(SEQSTAT_SFTRESET_P))
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE     (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
-                                0)
-
-/* Translate bits to something useful */
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE_SHIFT         (14)
-#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR    (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR   (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_PERF_FLOW     (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_RAISE_5       (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
-
-/**************************************************
- *   SYSCFG register
- **************************************************/
-
-/* Bit Positions */
-#define SYSCFG_SSSTEP_P     0x00000000  /* Supervisor single step, when
-                                         * set it forces an exception
-                                         * for each instruction executed
-                                         */
-#define SYSCFG_CCEN_P       0x00000001  /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P       0x00000002  /* Self nesting Interrupt Enable */
-
-/* Masks */
-
-/* Supervisor single step, when set it forces an exception for each
- *instruction executed
- */
-#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )
-/* Enable cycle counter (=1) */
-#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )
-/* Self Nesting Interrupt Enable */
-#define SYSCFG_SNEN            MK_BMSK_(SYSCFG_SNEN_P)
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
-#define SYSCFG_CCCEN           SYSCFG_CCEN
-
-/****************************************************
- * Core MMR Register Map
- ****************************************************/
-
-/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
-
-#define SRAM_BASE_ADDRESS  0xFFE00000   /* SRAM Base Address Register */
-#define DMEM_CONTROL       0xFFE00004   /* Data memory control */
-#define DCPLB_STATUS       0xFFE00008   /* Data Cache Programmable Look-Aside
-                                         * Buffer Status
-                                         */
-#define DCPLB_FAULT_STATUS 0xFFE00008   /* "" (older define) */
-#define DCPLB_FAULT_ADDR   0xFFE0000C   /* Data Cache Programmable Look-Aside
-                                         * Buffer Fault Address
-                                         */
-#define DCPLB_ADDR0        0xFFE00100   /* Data Cache Protection Lookaside
-                                         * Buffer 0
-                                         */
-#define DCPLB_ADDR1        0xFFE00104   /* Data Cache Protection Lookaside
-                                         * Buffer 1
-                                         */
-#define DCPLB_ADDR2        0xFFE00108   /* Data Cache Protection Lookaside
-                                         * Buffer 2
-                                         */
-#define DCPLB_ADDR3        0xFFE0010C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 3
-                                         */
-#define DCPLB_ADDR4        0xFFE00110   /* Data Cacheability Protection
-                                         * Lookaside Buffer 4
-                                         */
-#define DCPLB_ADDR5        0xFFE00114   /* Data Cacheability Protection
-                                         * Lookaside Buffer 5
-                                         */
-#define DCPLB_ADDR6        0xFFE00118   /* Data Cacheability Protection
-                                         * Lookaside Buffer 6
-                                         */
-#define DCPLB_ADDR7        0xFFE0011C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 7
-                                         */
-#define DCPLB_ADDR8        0xFFE00120   /* Data Cacheability Protection
-                                         * Lookaside Buffer 8
-                                         */
-#define DCPLB_ADDR9        0xFFE00124   /* Data Cacheability Protection
-                                         * Lookaside Buffer 9
-                                         */
-#define DCPLB_ADDR10       0xFFE00128   /* Data Cacheability Protection
-                                         * Lookaside Buffer 10
-                                         */
-#define DCPLB_ADDR11       0xFFE0012C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 11
-                                         */
-#define DCPLB_ADDR12       0xFFE00130   /* Data Cacheability Protection
-                                         * Lookaside Buffer 12
-                                         */
-#define DCPLB_ADDR13       0xFFE00134   /* Data Cacheability Protection
-                                         * Lookaside Buffer 13
-                                         */
-#define DCPLB_ADDR14       0xFFE00138   /* Data Cacheability Protection
-                                         * Lookaside Buffer 14
-                                         */
-#define DCPLB_ADDR15       0xFFE0013C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 15
-                                         */
-#define DCPLB_DATA0        0xFFE00200   /* Data Cache 0 Status */
-#define DCPLB_DATA1        0xFFE00204   /* Data Cache 1 Status */
-#define DCPLB_DATA2        0xFFE00208   /* Data Cache 2 Status */
-#define DCPLB_DATA3        0xFFE0020C   /* Data Cache 3 Status */
-#define DCPLB_DATA4        0xFFE00210   /* Data Cache 4 Status */
-#define DCPLB_DATA5        0xFFE00214   /* Data Cache 5 Status */
-#define DCPLB_DATA6        0xFFE00218   /* Data Cache 6 Status */
-#define DCPLB_DATA7        0xFFE0021C   /* Data Cache 7 Status */
-#define DCPLB_DATA8        0xFFE00220   /* Data Cache 8 Status */
-#define DCPLB_DATA9        0xFFE00224   /* Data Cache 9 Status */
-#define DCPLB_DATA10       0xFFE00228   /* Data Cache 10 Status */
-#define DCPLB_DATA11       0xFFE0022C   /* Data Cache 11 Status */
-#define DCPLB_DATA12       0xFFE00230   /* Data Cache 12 Status */
-#define DCPLB_DATA13       0xFFE00234   /* Data Cache 13 Status */
-#define DCPLB_DATA14       0xFFE00238   /* Data Cache 14 Status */
-#define DCPLB_DATA15       0xFFE0023C   /* Data Cache 15 Status */
-#define DCPLB_DATA16       0xFFE00240   /* Extra Dummy entry */
-
-#define DTEST_COMMAND      0xFFE00300   /* Data Test Command Register */
-#define DTEST_DATA0        0xFFE00400   /* Data Test Data Register */
-#define DTEST_DATA1        0xFFE00404   /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL       0xFFE01004   /* Instruction Memory Control */
-#define ICPLB_STATUS       0xFFE01008   /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS  0xFFE01008   /* "" (older define) */
-#define ICPLB_FAULT_ADDR   0xFFE0100C   /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR    0xFFE0100C   /* "" (older define) */
-#define ICPLB_ADDR0        0xFFE01100   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 0
-                                         */
-#define ICPLB_ADDR1        0xFFE01104   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 1
-                                         */
-#define ICPLB_ADDR2        0xFFE01108   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 2
-                                         */
-#define ICPLB_ADDR3        0xFFE0110C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 3
-                                         */
-#define ICPLB_ADDR4        0xFFE01110   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 4
-                                         */
-#define ICPLB_ADDR5        0xFFE01114   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 5
-                                         */
-#define ICPLB_ADDR6        0xFFE01118   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 6
-                                         */
-#define ICPLB_ADDR7        0xFFE0111C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 7
-                                         */
-#define ICPLB_ADDR8        0xFFE01120   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 8
-                                         */
-#define ICPLB_ADDR9        0xFFE01124   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 9
-                                         */
-#define ICPLB_ADDR10       0xFFE01128   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 10
-                                         */
-#define ICPLB_ADDR11       0xFFE0112C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 11
-                                         */
-#define ICPLB_ADDR12       0xFFE01130   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 12
-                                         */
-#define ICPLB_ADDR13       0xFFE01134   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 13
-                                         */
-#define ICPLB_ADDR14       0xFFE01138   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 14
-                                         */
-#define ICPLB_ADDR15       0xFFE0113C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 15
-                                         */
-#define ICPLB_DATA0        0xFFE01200   /* Instruction Cache 0 Status */
-#define ICPLB_DATA1        0xFFE01204   /* Instruction Cache 1 Status */
-#define ICPLB_DATA2        0xFFE01208   /* Instruction Cache 2 Status */
-#define ICPLB_DATA3        0xFFE0120C   /* Instruction Cache 3 Status */
-#define ICPLB_DATA4        0xFFE01210   /* Instruction Cache 4 Status */
-#define ICPLB_DATA5        0xFFE01214   /* Instruction Cache 5 Status */
-#define ICPLB_DATA6        0xFFE01218   /* Instruction Cache 6 Status */
-#define ICPLB_DATA7        0xFFE0121C   /* Instruction Cache 7 Status */
-#define ICPLB_DATA8        0xFFE01220   /* Instruction Cache 8 Status */
-#define ICPLB_DATA9        0xFFE01224   /* Instruction Cache 9 Status */
-#define ICPLB_DATA10       0xFFE01228   /* Instruction Cache 10 Status */
-#define ICPLB_DATA11       0xFFE0122C   /* Instruction Cache 11 Status */
-#define ICPLB_DATA12       0xFFE01230   /* Instruction Cache 12 Status */
-#define ICPLB_DATA13       0xFFE01234   /* Instruction Cache 13 Status */
-#define ICPLB_DATA14       0xFFE01238   /* Instruction Cache 14 Status */
-#define ICPLB_DATA15       0xFFE0123C   /* Instruction Cache 15 Status */
-#define ITEST_COMMAND      0xFFE01300   /* Instruction Test Command Register */
-#define ITEST_DATA0        0xFFE01400   /* Instruction Test Data Register */
-#define ITEST_DATA1        0xFFE01404   /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers   (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0               0xFFE02000   /* Event Vector 0 ESR Address */
-#define EVT1               0xFFE02004   /* Event Vector 1 ESR Address */
-#define EVT2               0xFFE02008   /* Event Vector 2 ESR Address */
-#define EVT3               0xFFE0200C   /* Event Vector 3 ESR Address */
-#define EVT4               0xFFE02010   /* Event Vector 4 ESR Address */
-#define EVT5               0xFFE02014   /* Event Vector 5 ESR Address */
-#define EVT6               0xFFE02018   /* Event Vector 6 ESR Address */
-#define EVT7               0xFFE0201C   /* Event Vector 7 ESR Address */
-#define EVT8               0xFFE02020   /* Event Vector 8 ESR Address */
-#define EVT9               0xFFE02024   /* Event Vector 9 ESR Address */
-#define EVT10              0xFFE02028   /* Event Vector 10 ESR Address */
-#define EVT11              0xFFE0202C   /* Event Vector 11 ESR Address */
-#define EVT12              0xFFE02030   /* Event Vector 12 ESR Address */
-#define EVT13              0xFFE02034   /* Event Vector 13 ESR Address */
-#define EVT14              0xFFE02038   /* Event Vector 14 ESR Address */
-#define EVT15              0xFFE0203C   /* Event Vector 15 ESR Address */
-#define IMASK              0xFFE02104   /* Interrupt Mask Register */
-#define IPEND              0xFFE02108   /* Interrupt Pending Register */
-#define ILAT               0xFFE0210C   /* Interrupt Latch Register */
-#define IPRIO              0xFFE02110   /* Core Interrupt Priority Register */
-
-/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL              0xFFE03000   /* Core Timer Control Register */
-#define TPERIOD            0xFFE03004   /* Core Timer Period Register */
-#define TSCALE             0xFFE03008   /* Core Timer Scale Register */
-#define TCOUNT             0xFFE0300C   /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers     (0xFFE05000 - 0xFFE05008) */
-#define DSPID              0xFFE05000   /* DSP Processor ID Register for
-                                         * MP implementations
-                                         */
-
-#define DBGSTAT            0xFFE05008   /* Debug Status Register */
-
-/* Trace Buffer Registers     (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL            0xFFE06000   /* Trace Buffer Control Register */
-#define TBUFSTAT           0xFFE06004   /* Trace Buffer Status Register */
-#define TBUF               0xFFE06100   /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-/* Watchpoint Instruction Address Control Register */
-#define WPIACTL            0xFFE07000
-/* Watchpoint Instruction Address Register 0 */
-#define WPIA0              0xFFE07040
-/* Watchpoint Instruction Address Register 1 */
-#define WPIA1              0xFFE07044
-/* Watchpoint Instruction Address Register 2 */
-#define WPIA2              0xFFE07048
-/* Watchpoint Instruction Address Register 3 */
-#define WPIA3              0xFFE0704C
-/* Watchpoint Instruction Address Register 4 */
-#define WPIA4              0xFFE07050
-/* Watchpoint Instruction Address Register 5 */
-#define WPIA5              0xFFE07054
-/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT0           0xFFE07080
-/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT1           0xFFE07084
-/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT2           0xFFE07088
-/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT3           0xFFE0708C
-/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT4           0xFFE07090
-/* Watchpoint Instruction Address Count Register 5 */
-#define WPIACNT5           0xFFE07094
-/* Watchpoint Data Address Control Register */
-#define WPDACTL            0xFFE07100
-/* Watchpoint Data Address Register 0 */
-#define WPDA0              0xFFE07140
-/* Watchpoint Data Address Register 1 */
-#define WPDA1              0xFFE07144
-/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT0           0xFFE07180
-/* Watchpoint Data Address Count Value Register 1 */
-#define WPDACNT1           0xFFE07184
-/* Watchpoint Status Register */
-#define WPSTAT             0xFFE07200
-
-/* Performance Monitor Registers    (0xFFE08000 - 0xFFE08104) */
-
-/* Performance Monitor Control Register */
-#define PFCTL              0xFFE08000
-/* Performance Monitor Counter Register 0 */
-#define PFCNTR0            0xFFE08100
-/* Performance Monitor Counter Register 1 */
-#define PFCNTR1            0xFFE08104
-
-/****************************************************
- * Core MMR Register Bits
- ****************************************************/
-
-/**************************************************
- * EVT registers (ILAT, IMASK, and IPEND).
- **************************************************/
-
-/* Bit Positions */
-#define EVT_EMU_P        0x00000000     /* Emulator interrupt bit position */
-#define EVT_RST_P        0x00000001     /* Reset interrupt bit position */
-#define EVT_NMI_P        0x00000002     /* Non Maskable interrupt bit position */
-#define EVT_EVX_P        0x00000003     /* Exception bit position */
-#define EVT_IRPTEN_P     0x00000004     /* Global interrupt enable bit position */
-#define EVT_IVHW_P       0x00000005     /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P      0x00000006     /* Timer interrupt bit position */
-#define EVT_IVG7_P       0x00000007     /* IVG7 interrupt bit position */
-#define EVT_IVG8_P       0x00000008     /* IVG8 interrupt bit position */
-#define EVT_IVG9_P       0x00000009     /* IVG9 interrupt bit position */
-#define EVT_IVG10_P      0x0000000a     /* IVG10 interrupt bit position */
-#define EVT_IVG11_P      0x0000000b     /* IVG11 interrupt bit position */
-#define EVT_IVG12_P      0x0000000c     /* IVG12 interrupt bit position */
-#define EVT_IVG13_P      0x0000000d     /* IVG13 interrupt bit position */
-#define EVT_IVG14_P      0x0000000e     /* IVG14 interrupt bit position */
-#define EVT_IVG15_P      0x0000000f     /* IVG15 interrupt bit position */
-
-/* Masks */
-#define EVT_EMU       MK_BMSK_(EVT_EMU_P   )    /* Emulator interrupt mask */
-#define EVT_RST       MK_BMSK_(EVT_RST_P   )    /* Reset interrupt mask */
-#define EVT_NMI       MK_BMSK_(EVT_NMI_P   )    /* Non Maskable interrupt mask */
-#define EVT_EVX       MK_BMSK_(EVT_EVX_P   )    /* Exception mask */
-#define EVT_IRPTEN    MK_BMSK_(EVT_IRPTEN_P)    /* Global interrupt enable mask */
-#define EVT_IVHW      MK_BMSK_(EVT_IVHW_P  )    /* Hardware Error interrupt mask */
-#define EVT_IVTMR     MK_BMSK_(EVT_IVTMR_P )    /* Timer interrupt mask */
-#define EVT_IVG7      MK_BMSK_(EVT_IVG7_P  )    /* IVG7 interrupt mask */
-#define EVT_IVG8      MK_BMSK_(EVT_IVG8_P  )    /* IVG8 interrupt mask */
-#define EVT_IVG9      MK_BMSK_(EVT_IVG9_P  )    /* IVG9 interrupt mask */
-#define EVT_IVG10     MK_BMSK_(EVT_IVG10_P )    /* IVG10 interrupt mask */
-#define EVT_IVG11     MK_BMSK_(EVT_IVG11_P )    /* IVG11 interrupt mask */
-#define EVT_IVG12     MK_BMSK_(EVT_IVG12_P )    /* IVG12 interrupt mask */
-#define EVT_IVG13     MK_BMSK_(EVT_IVG13_P )    /* IVG13 interrupt mask */
-#define EVT_IVG14     MK_BMSK_(EVT_IVG14_P )    /* IVG14 interrupt mask */
-#define EVT_IVG15     MK_BMSK_(EVT_IVG15_P )    /* IVG15 interrupt mask */
-
-/**************************************************
- *  DMEM_CONTROL Register
- **************************************************/
-/* Bit Positions */
-#define ENDM_P                  0x00    /* (doesn't really exist) Enable
-                                         *Data Memory L1
-                                         */
-#define DMCTL_ENDM_P            ENDM_P  /* "" (older define) */
-
-#define ENDCPLB_P               0x01    /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P         ENDCPLB_P       /* "" (older define) */
-#define DMC0_P                  0x02    /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P            DMC0_P  /* "" (older define) */
-#define DMC1_P                  0x03    /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P            DMC1_P  /* "" (older define) */
-#define DCBS_P                  0x04    /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P            0x12    /* DAG0 Port Preference */
-#define PORT_PREF1_P            0x13    /* DAG1 Port Preference */
-
-/* Masks */
-#define ENDM               0x00000001   /* (doesn't really exist) Enable
-                                         * Data Memory L1
-                                         */
-#define ENDCPLB            0x00000002   /* Enable DCPLB */
-#define ASRAM_BSRAM        0x00000000
-#define ACACHE_BSRAM       0x00000008
-#define ACACHE_BCACHE      0x0000000C
-#define DCBS               0x00000010   /*  L1 Data Cache Bank Select */
-#define PORT_PREF0         0x00001000   /* DAG0 Port Preference */
-#define PORT_PREF1         0x00002000   /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* Bit Positions */
-#define ENIM_P                  0x00    /* Enable L1 Code Memory  */
-#define IMCTL_ENIM_P            0x00    /* "" (older define) */
-#define ENICPLB_P               0x01    /* Enable ICPLB */
-#define IMCTL_ENICPLB_P         0x01    /* "" (older define) */
-#define IMC_P                   0x02    /* Enable  */
-#define IMCTL_IMC_P             0x02    /* Configure L1 code memory as
-                                         * cache (0=SRAM)
-                                         */
-#define ILOC0_P                 0x03    /* Lock Way 0 */
-#define ILOC1_P                 0x04    /* Lock Way 1 */
-#define ILOC2_P                 0x05    /* Lock Way 2 */
-#define ILOC3_P                 0x06    /* Lock Way 3 */
-#define LRUPRIORST_P            0x0D    /* Least Recently Used Replacement
-                                         * Priority
-                                         */
-/* Masks */
-#define ENIM               0x00000001   /* Enable L1 Code Memory */
-#define ENICPLB            0x00000002   /* Enable ICPLB */
-#define IMC                0x00000004   /* Configure L1 code memory as
-                                         * cache (0=SRAM)
-                                         */
-#define ILOC0              0x00000008   /* Lock Way 0 */
-#define ILOC1              0x00000010   /* Lock Way 1 */
-#define ILOC2              0x00000020   /* Lock Way 2 */
-#define ILOC3              0x00000040   /* Lock Way 3 */
-#define LRUPRIORST         0x00002000   /* Least Recently Used Replacement
-                                         * Priority
-                                         */
-
-/* TCNTL Masks */
-#define TMPWR              0x00000001   /* Timer Low Power Control,
-                                         * 0=low power mode, 1=active state
-                                         */
-#define TMREN              0x00000002   /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD           0x00000004   /* Timer auto reload */
-#define TINT               0x00000008   /* Timer generated interrupt 0=no
-                                         * interrupt has been generated,
-                                         * 1=interrupt has been generated
-                                         * (sticky)
-                                         */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* Bit Positions */
-#define CPLB_VALID_P       0x00000000   /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P        0x00000001   /* 0=entry may be replaced, 1=entry
-                                         * locked
-                                         */
-#define CPLB_USER_RD_P     0x00000002   /* 0=no read access, 1=read access
-                                         * allowed (user mode)
-                                         */
-/* Masks */
-#define CPLB_VALID         0x00000001   /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK          0x00000002   /* 0=entry may be replaced, 1=entry
-                                         * locked
-                                         */
-#define CPLB_USER_RD       0x00000004   /* 0=no read access, 1=read access
-                                         * allowed (user mode)
-                                         */
-
-#define PAGE_SIZE_1KB      0x00000000   /* 1 KB page size */
-#define PAGE_SIZE_4KB      0x00010000   /* 4 KB page size */
-#define PAGE_SIZE_1MB      0x00020000   /* 1 MB page size */
-#define PAGE_SIZE_4MB      0x00030000   /* 4 MB page size */
-#define CPLB_L1SRAM        0x00000020   /* 0=SRAM mapped in L1, 0=SRAM not
-                                         * mapped to L1
-                                         */
-#define CPLB_PORTPRIO      0x00000200   /* 0=low priority port, 1= high
-                                         * priority port
-                                         */
-#define CPLB_L1_CHBL       0x00001000   /* 0=non-cacheable in L1, 1=cacheable
-                                         * in L1
-                                         */
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO       0x00000100   /* 0=can be replaced by any line,
-                                         * 1=priority for non-replacement
-                                         */
-/* DCPLB_DATA only */
-#define CPLB_USER_WR       0x00000008   /* 0=no write access, 0=write
-                                         * access allowed (user mode)
-                                         */
-#define CPLB_SUPV_WR       0x00000010   /* 0=no write access, 0=write
-                                         * access allowed (supervisor mode)
-                                         */
-#define CPLB_DIRTY         0x00000080   /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW        0x00008000   /* 0=do not allocate cache lines on
-                                         * write-through writes,
-                                         * 1= allocate cache lines on
-                                         * write-through writes.
-                                         */
-#define CPLB_WT            0x00004000   /* 0=write-back, 1=write-through */
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-/* TBUFCTL Masks */
-#define TBUFPWR            0x0001
-#define TBUFEN             0x0002
-#define TBUFOVF            0x0004
-#define TBUFCMPLP_SINGLE   0x0008
-#define TBUFCMPLP_DOUBLE   0x0010
-#define TBUFCMPLP          (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
-
-/* TBUFSTAT Masks */
-#define TBUFCNT            0x001F
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* Masks */
-#define TEST_READ          0x00000000   /* Read Access */
-#define TEST_WRITE         0x00000002   /* Write Access */
-#define TEST_TAG           0x00000000   /* Access TAG */
-#define TEST_DATA          0x00000004   /* Access DATA */
-#define TEST_DW0           0x00000000   /* Select Double Word 0 */
-#define TEST_DW1           0x00000008   /* Select Double Word 1 */
-#define TEST_DW2           0x00000010   /* Select Double Word 2 */
-#define TEST_DW3           0x00000018   /* Select Double Word 3 */
-#define TEST_MB0           0x00000000   /* Select Mini-Bank 0 */
-#define TEST_MB1           0x00010000   /* Select Mini-Bank 1 */
-#define TEST_MB2           0x00020000   /* Select Mini-Bank 2 */
-#define TEST_MB3           0x00030000   /* Select Mini-Bank 3 */
-#define TEST_SET(x)        ((x << 5) & 0x03E0)  /* Set Index 0->31 */
-#define TEST_WAY0          0x00000000   /* Access Way0 */
-#define TEST_WAY1          0x04000000   /* Access Way1 */
-/* ITEST_COMMAND only */
-#define TEST_WAY2          0x08000000   /* Access Way2 */
-#define TEST_WAY3          0x0C000000   /* Access Way3 */
-/* DTEST_COMMAND only */
-#define TEST_BNKSELA       0x00000000   /* Access SuperBank A */
-#define TEST_BNKSELB       0x00800000   /* Access SuperBank B */
-
-#endif                          /* _DEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h
deleted file mode 100644
index 42d1f37f6d9c..000000000000
--- a/include/asm-blackfin/mem_map.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * mem_map.h
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _MEM_MAP_H_
-#define _MEM_MAP_H_
-
-#include <asm/mach/mem_map.h>
-
-#endif                          /* _MEM_MAP_H_ */
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
deleted file mode 100644
index b58f5ad3f024..000000000000
--- a/include/asm-blackfin/mman.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef __BFIN_MMAN_H__
-#define __BFIN_MMAN_H__
-
-#define PROT_READ       0x1     /* page can be read */
-#define PROT_WRITE      0x2     /* page can be written */
-#define PROT_EXEC       0x4     /* page can be executed */
-#define PROT_SEM        0x8     /* page may be used for atomic ops */
-#define PROT_NONE       0x0     /* page can not be accessed */
-#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
-#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
-
-#define MAP_SHARED      0x01    /* Share changes */
-#define MAP_PRIVATE     0x02    /* Changes are private */
-#define MAP_TYPE        0x0f    /* Mask for type of mapping */
-#define MAP_FIXED       0x10    /* Interpret addr exactly */
-#define MAP_ANONYMOUS   0x20    /* don't use a file */
-
-#define MAP_GROWSDOWN   0x0100  /* stack-like segment */
-#define MAP_DENYWRITE   0x0800  /* ETXTBSY */
-#define MAP_EXECUTABLE  0x1000  /* mark it as an executable */
-#define MAP_LOCKED      0x2000  /* pages are locked */
-#define MAP_NORESERVE   0x4000  /* don't check for reservations */
-#define MAP_POPULATE    0x8000  /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x10000 /* do not block on IO */
-
-#define MS_ASYNC        1       /* sync memory asynchronously */
-#define MS_INVALIDATE   2       /* invalidate the caches */
-#define MS_SYNC         4       /* synchronous memory sync */
-
-#define MCL_CURRENT     1       /* lock all current mappings */
-#define MCL_FUTURE      2       /* lock all future mappings */
-
-#define MADV_NORMAL     0x0     /* default page-in behavior */
-#define MADV_RANDOM     0x1     /* page-in minimum required */
-#define MADV_SEQUENTIAL 0x2     /* read-ahead aggressively */
-#define MADV_WILLNEED   0x3     /* pre-fault pages */
-#define MADV_DONTNEED   0x4     /* discard these pages */
-
-/* compatibility flags */
-#define MAP_ANON        MAP_ANONYMOUS
-#define MAP_FILE        0
-
-#endif                          /* __BFIN_MMAN_H__ */
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
deleted file mode 100644
index 757e43906ed4..000000000000
--- a/include/asm-blackfin/mmu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __MMU_H
-#define __MMU_H
-
-/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
-
-struct sram_list_struct {
-        struct sram_list_struct *next;
-        void *addr;
-        size_t length;
-};
-
-typedef struct {
-        struct vm_list_struct *vmlist;
-        unsigned long end_brk;
-        unsigned long stack_start;
-
-        /* Points to the location in SDRAM where the L1 stack is normally
-           saved, or NULL if the stack is always in SDRAM.  */
-        void *l1_stack_save;
-
-        struct sram_list_struct *sram_list;
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
-        unsigned long   exec_fdpic_loadmap;
-        unsigned long   interp_fdpic_loadmap;
-#endif
-#ifdef CONFIG_MPU
-        unsigned long *page_rwx_mask;
-#endif
-} mm_context_t;
-
-#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
deleted file mode 100644
index f55ec3c23a92..000000000000
--- a/include/asm-blackfin/mmu_context.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * File:         include/asm-blackfin/mmu_context.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __BLACKFIN_MMU_CONTEXT_H__
-#define __BLACKFIN_MMU_CONTEXT_H__
-
-#include <linux/gfp.h>
-#include <linux/sched.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/cplbinit.h>
-
-extern void *current_l1_stack_save;
-extern int nr_l1stack_tasks;
-extern void *l1_stack_base;
-extern unsigned long l1_stack_len;
-
-extern int l1sram_free(const void*);
-extern void *l1sram_alloc_max(void*);
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* Called when creating a new context during fork() or execve().  */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-#ifdef CONFIG_MPU
-        unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
-        mm->context.page_rwx_mask = (unsigned long *)p;
-        memset(mm->context.page_rwx_mask, 0,
-               page_mask_nelts * 3 * sizeof(long));
-#endif
-        return 0;
-}
-
-static inline void free_l1stack(void)
-{
-        nr_l1stack_tasks--;
-        if (nr_l1stack_tasks == 0)
-                l1sram_free(l1_stack_base);
-}
-static inline void destroy_context(struct mm_struct *mm)
-{
-        struct sram_list_struct *tmp;
-
-        if (current_l1_stack_save == mm->context.l1_stack_save)
-                current_l1_stack_save = NULL;
-        if (mm->context.l1_stack_save)
-                free_l1stack();
-
-        while ((tmp = mm->context.sram_list)) {
-                mm->context.sram_list = tmp->next;
-                sram_free(tmp->addr);
-                kfree(tmp);
-        }
-#ifdef CONFIG_MPU
-        if (current_rwx_mask == mm->context.page_rwx_mask)
-                current_rwx_mask = NULL;
-        free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
-#endif
-}
-
-static inline unsigned long
-alloc_l1stack(unsigned long length, unsigned long *stack_base)
-{
-        if (nr_l1stack_tasks == 0) {
-                l1_stack_base = l1sram_alloc_max(&l1_stack_len);
-                if (!l1_stack_base)
-                        return 0;
-        }
-
-        if (l1_stack_len < length) {
-                if (nr_l1stack_tasks == 0)
-                        l1sram_free(l1_stack_base);
-                return 0;
-        }
-        *stack_base = (unsigned long)l1_stack_base;
-        nr_l1stack_tasks++;
-        return l1_stack_len;
-}
-
-static inline int
-activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
-{
-        if (current_l1_stack_save)
-                memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
-        mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
-        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-        return 1;
-}
-
-#define deactivate_mm(tsk,mm)   do { } while (0)
-
-#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-
-static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-                             struct task_struct *tsk)
-{
-        if (prev_mm == next_mm)
-                return;
-#ifdef CONFIG_MPU
-        if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
-                flush_switched_cplbs();
-                set_mask_dcplbs(next_mm->context.page_rwx_mask);
-        }
-#endif
-
-        /* L1 stack switching.  */
-        if (!next_mm->context.l1_stack_save)
-                return;
-        if (next_mm->context.l1_stack_save == current_l1_stack_save)
-                return;
-        if (current_l1_stack_save) {
-                memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
-        }
-        current_l1_stack_save = next_mm->context.l1_stack_save;
-        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-}
-
-#ifdef CONFIG_MPU
-static inline void protect_page(struct mm_struct *mm, unsigned long addr,
-                                unsigned long flags)
-{
-        unsigned long *mask = mm->context.page_rwx_mask;
-        unsigned long page = addr >> 12;
-        unsigned long idx = page >> 5;
-        unsigned long bit = 1 << (page & 31);
-
-        if (flags & VM_MAYREAD)
-                mask[idx] |= bit;
-        else
-                mask[idx] &= ~bit;
-        mask += page_mask_nelts;
-        if (flags & VM_MAYWRITE)
-                mask[idx] |= bit;
-        else
-                mask[idx] &= ~bit;
-        mask += page_mask_nelts;
-        if (flags & VM_MAYEXEC)
-                mask[idx] |= bit;
-        else
-                mask[idx] &= ~bit;
-}
-
-static inline void update_protections(struct mm_struct *mm)
-{
-        flush_switched_cplbs();
-        set_mask_dcplbs(mm->context.page_rwx_mask);
-}
-#endif
-
-#endif
diff --git a/include/asm-blackfin/module.h b/include/asm-blackfin/module.h
deleted file mode 100644
index e3128df139d6..000000000000
--- a/include/asm-blackfin/module.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#define MODULE_SYMBOL_PREFIX "_"
-
-#define Elf_Shdr        Elf32_Shdr
-#define Elf_Sym         Elf32_Sym
-#define Elf_Ehdr        Elf32_Ehdr
-
-struct mod_arch_specific {
-        Elf_Shdr        *text_l1;
-        Elf_Shdr        *data_a_l1;
-        Elf_Shdr        *bss_a_l1;
-        Elf_Shdr        *data_b_l1;
-        Elf_Shdr        *bss_b_l1;
-        Elf_Shdr        *text_l2;
-        Elf_Shdr        *data_l2;
-        Elf_Shdr        *bss_l2;
-};
-#endif                          /* _ASM_BFIN_MODULE_H */
diff --git a/include/asm-blackfin/msgbuf.h b/include/asm-blackfin/msgbuf.h
deleted file mode 100644
index 6fcbe8cd801d..000000000000
--- a/include/asm-blackfin/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _BFIN_MSGBUF_H
-#define _BFIN_MSGBUF_H
-
-/*
- * The msqid64_ds structure for bfin architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        unsigned long __unused1;
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        unsigned long __unused2;
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long __unused3;
-        unsigned long msg_cbytes;       /* current number of bytes on queue */
-        unsigned long msg_qnum; /* number of messages in queue */
-        unsigned long msg_qbytes;       /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long __unused4;
-        unsigned long __unused5;
-};
-
-#endif                          /* _BFIN_MSGBUF_H */
diff --git a/include/asm-blackfin/mutex.h b/include/asm-blackfin/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-blackfin/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-blackfin/nand.h b/include/asm-blackfin/nand.h
deleted file mode 100644
index afbaafa793f1..000000000000
--- a/include/asm-blackfin/nand.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* linux/include/asm-blackfin/nand.h
- *
- * Copyright (c) 2007 Analog Devices, Inc.
- *      Bryan Wu <bryan.wu@analog.com>
- *
- * BF5XX - NAND flash controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* struct bf5xx_nand_platform
- *
- * define a interface between platfrom board specific code and
- * bf54x NFC driver.
- *
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * partitions    = mtd partition list
- */
-
-#define NFC_PG_SIZE_256         0
-#define NFC_PG_SIZE_512         1
-#define NFC_PG_SIZE_OFFSET      9
-
-#define NFC_NWIDTH_8            0
-#define NFC_NWIDTH_16           1
-#define NFC_NWIDTH_OFFSET       8
-
-#define NFC_RDDLY_OFFSET        4
-#define NFC_WRDLY_OFFSET        0
-
-#define NFC_STAT_NBUSY          1
-
-struct bf5xx_nand_platform {
-        /* NAND chip information */
-        unsigned short          page_size;
-        unsigned short          data_width;
-
-        /* RD/WR strobe delay timing information, all times in SCLK cycles */
-        unsigned short          rd_dly;
-        unsigned short          wr_dly;
-
-        /* NAND MTD partition information */
-        int                     nr_partitions;
-        struct mtd_partition    *partitions;
-};
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
deleted file mode 100644
index 344f6a8c1f22..000000000000
--- a/include/asm-blackfin/page.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-/* PAGE_SHIFT determines the page size */
-
-#define PAGE_SHIFT      12
-#ifdef __ASSEMBLY__
-#define PAGE_SIZE       (1 << PAGE_SHIFT)
-#else
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#endif
-#define PAGE_MASK       (~(PAGE_SIZE-1))
-
-#include <asm/setup.h>
-
-#ifndef __ASSEMBLY__
-
-#define get_user_page(vaddr)            __get_free_page(GFP_KERNEL)
-#define free_user_page(page, addr)      free_page(addr)
-
-#define clear_page(page)        memset((page), 0, PAGE_SIZE)
-#define copy_page(to,from)      memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr,pg) clear_page(page)
-#define copy_user_page(to, from, vaddr,pg)      copy_page(to, from)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct {
-        unsigned long pte;
-} pte_t;
-typedef struct {
-        unsigned long pmd[16];
-} pmd_t;
-typedef struct {
-        unsigned long pgd;
-} pgd_t;
-typedef struct {
-        unsigned long pgprot;
-} pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((&x)->pmd[0])
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-#endif                          /* !__ASSEMBLY__ */
-
-#include <asm/page_offset.h>
-#include <asm/io.h>
-
-#define PAGE_OFFSET             (PAGE_OFFSET_RAW)
-
-#ifndef __ASSEMBLY__
-
-#define __pa(vaddr)             virt_to_phys((void *)(vaddr))
-#define __va(paddr)             phys_to_virt((unsigned long)(paddr))
-
-#define MAP_NR(addr)            (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
-
-#define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
-#define virt_to_page(addr)      (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
-#define page_to_virt(page)      ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-#define VALID_PAGE(page)        ((page - mem_map) < max_mapnr)
-
-#define pfn_to_page(pfn)        virt_to_page(pfn_to_virt(pfn))
-#define page_to_pfn(page)       virt_to_pfn(page_to_virt(page))
-#define pfn_valid(pfn)          ((pfn) < max_mapnr)
-
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                ((void *)(kaddr) < (void *)memory_end))
-
-#include <asm-generic/page.h>
-
-#endif                          /* __ASSEMBLY__ */
-
-#endif                          /* _BLACKFIN_PAGE_H */
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
deleted file mode 100644
index cbaff24b4b25..000000000000
--- a/include/asm-blackfin/page_offset.h
+++ /dev/null
@@ -1,6 +0,0 @@
-
-/* This handles the memory map.. */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW         0x00000000
-#endif
diff --git a/include/asm-blackfin/param.h b/include/asm-blackfin/param.h
deleted file mode 100644
index 41564a6347f8..000000000000
--- a/include/asm-blackfin/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _BLACKFIN_PARAM_H
-#define _BLACKFIN_PARAM_H
-
-#ifdef __KERNEL__
-#define HZ              CONFIG_HZ
-#define USER_HZ         100
-#define CLOCKS_PER_SEC  (USER_HZ)
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#endif                          /* _BLACKFIN_PARAM_H */
diff --git a/include/asm-blackfin/pci.h b/include/asm-blackfin/pci.h
deleted file mode 100644
index 61277358c865..000000000000
--- a/include/asm-blackfin/pci.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Changed from asm-m68k version, Lineo Inc.    May 2001        */
-
-#ifndef _ASM_BFIN_PCI_H
-#define _ASM_BFIN_PCI_H
-
-#include <asm/scatterlist.h>
-
-/*
- *
- * Written by Wout Klaren.
- */
-
-/* Added by Chang Junxiao */
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#define PCI_DMA_BUS_IS_PHYS       (1)
-struct pci_ops;
-
-/*
- * Structure with hardware dependent information and functions of the
- * PCI bus.
- */
-struct pci_bus_info {
-
-        /*
-         * Resources of the PCI bus.
-         */
-        struct resource mem_space;
-        struct resource io_space;
-
-        /*
-         * System dependent functions.
-         */
-        struct pci_ops *bfin_pci_ops;
-        void (*fixup) (int pci_modify);
-        void (*conf_device) (unsigned char bus, unsigned char device_fn);
-};
-
-#define pcibios_assign_all_busses()     0
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
-
-        /* No special bus mastering setup handling */
-}
-static inline void pcibios_penalize_isa_irq(int irq)
-{
-
-        /* We don't do dynamic PCI IRQ allocation */
-}
-static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
-                                        size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-         /* return virt_to_bus(ptr); */
-        return (dma_addr_t) ptr;
-}
-
-/* Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
-                                    size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                             int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-        return nents;
-}
-
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                                int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so.  At the
- * next point you give the PCI dma address back to the card, the
- * device again owns the buffer.
- */
-static inline void pci_dma_sync_single(struct pci_dev *hwdev,
-                                       dma_addr_t dma_handle, size_t size,
-                                       int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as pci_dma_sync_single but for a scatter-gather list,
- * same rules and usage.
- */
-static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
-                                   struct scatterlist *sg, int nelems,
-                                   int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-#endif                          /* _ASM_BFIN_PCI_H */
diff --git a/include/asm-blackfin/percpu.h b/include/asm-blackfin/percpu.h
deleted file mode 100644
index 78dd61f6b39f..000000000000
--- a/include/asm-blackfin/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARCH_BLACKFIN_PERCPU__
-#define __ARCH_BLACKFIN_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif                          /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/include/asm-blackfin/pgalloc.h b/include/asm-blackfin/pgalloc.h
deleted file mode 100644
index c686e0542fd0..000000000000
--- a/include/asm-blackfin/pgalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _BLACKFIN_PGALLOC_H
-#define _BLACKFIN_PGALLOC_H
-
-#include <asm/setup.h>
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif                          /* _BLACKFIN_PGALLOC_H */
diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h
deleted file mode 100644
index b11b114689c0..000000000000
--- a/include/asm-blackfin/pgtable.h
+++ /dev/null
@@ -1,96 +0,0 @@
-#ifndef _BLACKFIN_PGTABLE_H
-#define _BLACKFIN_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/page.h>
-#include <asm/mach-common/def_LPBlackfin.h>
-
-typedef pte_t *pte_addr_t;
-/*
-* Trivial page table functions.
-*/
-#define pgd_present(pgd)        (1)
-#define pgd_none(pgd)           (0)
-#define pgd_bad(pgd)            (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr)   (1)
-
-#define pmd_offset(a, b)        ((void *)0)
-#define pmd_none(x)             (!pmd_val(x))
-#define pmd_present(x)          (pmd_val(x))
-#define pmd_clear(xp)           do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x)              (pmd_val(x) & ~PAGE_MASK)
-
-#define kern_addr_valid(addr) (1)
-
-#define PAGE_NONE               __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_SHARED             __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_COPY               __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_READONLY           __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_KERNEL             __pgprot(0)     /* these mean nothing to NO_MM */
-
-extern void paging_init(void);
-
-#define __swp_type(x)           (0)
-#define __swp_offset(x)         (0)
-#define __swp_entry(typ,off)    ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-
-static inline int pte_file(pte_t pte)
-{
-        return 0;
-}
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-/*
- * Page assess control based on Blackfin CPLB management
- */
-#define _PAGE_RD        (CPLB_USER_RD)
-#define _PAGE_WR        (CPLB_USER_WR)
-#define _PAGE_USER      (CPLB_USER_RD | CPLB_USER_WR)
-#define _PAGE_ACCESSED  CPLB_ALL_ACCESS
-#define _PAGE_DIRTY     (CPLB_DIRTY)
-
-#define PTE_BIT_FUNC(fn, op) \
-        static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
-
-PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
-PTE_BIT_FUNC(mkread, |= _PAGE_RD);
-PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
-PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
-PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
-PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
-PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
-PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
-PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
-PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr)        (virt_to_page(0))
-
-extern unsigned int kobjsize(const void *objp);
-
-#define swapper_pg_dir ((pgd_t *) 0)
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init()    do { } while (0)
-#define io_remap_pfn_range      remap_pfn_range
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
-
-#include <asm-generic/pgtable.h>
-
-#endif                          /* _BLACKFIN_PGTABLE_H */
diff --git a/include/asm-blackfin/poll.h b/include/asm-blackfin/poll.h
deleted file mode 100644
index 94cc2636e0e2..000000000000
--- a/include/asm-blackfin/poll.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __BFIN_POLL_H
-#define __BFIN_POLL_H
-
-#define POLLIN            1
-#define POLLPRI           2
-#define POLLOUT           4
-#define POLLERR           8
-#define POLLHUP          16
-#define POLLNVAL         32
-#define POLLRDNORM       64
-#define POLLWRNORM      POLLOUT
-#define POLLRDBAND      128
-#define POLLWRBAND      256
-#define POLLMSG         0x0400
-#define POLLREMOVE      0x1000
-#define POLLRDHUP       0x2000
-
-struct pollfd {
-        int fd;
-        short events;
-        short revents;
-};
-
-#endif                          /* __BFIN_POLL_H */
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
deleted file mode 100644
index 0807b286cd9e..000000000000
--- a/include/asm-blackfin/portmux.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-/*
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x)      ((x) & 0x1FF)
-#define P_FUNCT(x)      (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x)  (((x) >> 9) & 0x3)
-#define P_DEFINED       0x8000
-#define P_UNDEF         0x4000
-#define P_MAYSHARE      0x2000
-#define P_DONTCARE      0x1000
-
-
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-
-#include <asm/gpio.h>
-#include <asm/mach/portmux.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef  P_TMRCLK
-#define  P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif                          /* _PORTMUX_H_ */
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
deleted file mode 100644
index 23aa1f8c1bd1..000000000000
--- a/include/asm-blackfin/posix_types.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __ARCH_BFIN_POSIX_TYPES_H
-#define __ARCH_BFIN_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long __kernel_ino_t;
-typedef unsigned short __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_timer_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-typedef unsigned short __kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
-        int val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef  __FD_SET
-#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-
-#undef  __FD_CLR
-#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-
-#undef  __FD_ISSET
-#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-
-#undef  __FD_ZERO
-#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-
-#endif                          /* defined(__KERNEL__) */
-
-#endif
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
deleted file mode 100644
index 6f3995b119d8..000000000000
--- a/include/asm-blackfin/processor.h
+++ /dev/null
@@ -1,158 +0,0 @@
-#ifndef __ASM_BFIN_PROCESSOR_H
-#define __ASM_BFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <asm/blackfin.h>
-#include <asm/segment.h>
-#include <linux/compiler.h>
-
-static inline unsigned long rdusp(void)
-{
-        unsigned long usp;
-
-        __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
-        return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
-        __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-/*
- * User space process size: 1st byte beyond user address space.
- * Fairly meaningless on nommu.  Parts of user programs can be scattered
- * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
- */
-#define TASK_SIZE       0xFFFFFFFF
-
-#ifdef __KERNEL__
-#define STACK_TOP       TASK_SIZE
-#endif
-
-#define TASK_UNMAPPED_BASE      0
-
-struct thread_struct {
-        unsigned long ksp;      /* kernel stack pointer */
-        unsigned long usp;      /* user stack pointer */
-        unsigned short seqstat; /* saved status register */
-        unsigned long esp0;     /* points to SR of stack frame pt_regs */
-        unsigned long pc;       /* instruction pointer */
-        void *        debuggerinfo;
-};
-
-#define INIT_THREAD  {                                          \
-        sizeof(init_stack) + (unsigned long) init_stack, 0,     \
-        PS_S, 0, 0                                              \
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-#define start_thread(_regs, _pc, _usp)                                  \
-do {                                                                    \
-        set_fs(USER_DS);                                                \
-        (_regs)->pc = (_pc);                                            \
-        if (current->mm)                                                \
-                (_regs)->p5 = current->mm->start_data;                  \
-        task_thread_info(current)->l1_task_info.stack_start             \
-                = (void *)current->mm->context.stack_start;             \
-        task_thread_info(current)->l1_task_info.lowest_sp = (void *)(_usp); \
-        memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, \
-                sizeof(*L1_SCRATCH_TASK_INFO));                         \
-        wrusp(_usp);                                                    \
-} while(0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-#define prepare_to_copy(tsk)    do { } while (0)
-
-extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
-
-/*
- * Free current thread data structures etc..
- */
-static inline void exit_thread(void)
-{
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-#define thread_saved_pc(tsk)    (tsk->thread.pc)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)                                                   \
-    ({                                                                  \
-        unsigned long eip = 0;                                          \
-        if ((tsk)->thread.esp0 > PAGE_SIZE &&                           \
-            MAP_NR((tsk)->thread.esp0) < max_mapnr)                     \
-              eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc;        \
-        eip; })
-#define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax()     barrier()
-
-/* Get the Silicon Revision of the chip */
-static inline uint32_t __pure bfin_revid(void)
-{
-        /* stored in the upper 4 bits */
-        uint32_t revid = bfin_read_CHIPID() >> 28;
-
-#ifdef CONFIG_BF52x
-        /* ANOMALY_05000357
-         * Incorrect Revision Number in DSPID Register
-         */
-        if (revid == 0)
-                switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) {
-                case 0x0010:
-                        revid = 0;
-                        break;
-                case 0x2796:
-                        revid = 1;
-                        break;
-                default:
-                        revid = 0xFFFF;
-                        break;
-                }
-#endif
-        return revid;
-}
-
-static inline uint32_t __pure bfin_compiled_revid(void)
-{
-#if defined(CONFIG_BF_REV_0_0)
-        return 0;
-#elif defined(CONFIG_BF_REV_0_1)
-        return 1;
-#elif defined(CONFIG_BF_REV_0_2)
-        return 2;
-#elif defined(CONFIG_BF_REV_0_3)
-        return 3;
-#elif defined(CONFIG_BF_REV_0_4)
-        return 4;
-#elif defined(CONFIG_BF_REV_0_5)
-        return 5;
-#elif defined(CONFIG_BF_REV_ANY)
-        return 0xffff;
-#else
-        return -1;
-#endif
-}
-
-#endif
diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
deleted file mode 100644
index a45a80e54adc..000000000000
--- a/include/asm-blackfin/ptrace.h
+++ /dev/null
@@ -1,168 +0,0 @@
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- *       0 - 7 are data registers R0-R7
- *       8 - 15 are address registers P0-P7
- *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- *      32 - 33 A registers A0 & A1
- *      34 -    status register
- * -----------------------------
- *
- * We follows above, except:
- *      32-33 --- Low 32-bit of A0&1
- *      34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-struct pt_regs {
-        long orig_pc;
-        long ipend;
-        long seqstat;
-        long rete;
-        long retn;
-        long retx;
-        long pc;                /* PC == RETI */
-        long rets;
-        long reserved;          /* Used as scratch during system calls */
-        long astat;
-        long lb1;
-        long lb0;
-        long lt1;
-        long lt0;
-        long lc1;
-        long lc0;
-        long a1w;
-        long a1x;
-        long a0w;
-        long a0x;
-        long b3;
-        long b2;
-        long b1;
-        long b0;
-        long l3;
-        long l2;
-        long l1;
-        long l0;
-        long m3;
-        long m2;
-        long m1;
-        long m0;
-        long i3;
-        long i2;
-        long i1;
-        long i0;
-        long usp;
-        long fp;
-        long p5;
-        long p4;
-        long p3;
-        long p2;
-        long p1;
-        long p0;
-        long r7;
-        long r6;
-        long r5;
-        long r4;
-        long r3;
-        long r2;
-        long r1;
-        long r0;
-        long orig_r0;
-        long orig_p0;
-        long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13    /* ptrace signal  */
-
-#define PTRACE_GETFDPIC           31
-#define PTRACE_GETFDPIC_EXEC      0
-#define PTRACE_GETFDPIC_INTERP    1
-
-#define PS_S  (0x0002)
-
-#ifdef __KERNEL__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
-   master interrupt enable.  */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-#define instruction_pointer(regs) ((regs)->pc)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-
-#endif  /*  __KERNEL__  */
-
-#endif                          /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#endif                          /* _BFIN_PTRACE_H */
diff --git a/include/asm-blackfin/reboot.h b/include/asm-blackfin/reboot.h
deleted file mode 100644
index 6d448b5f5985..000000000000
--- a/include/asm-blackfin/reboot.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-blackfin/reboot.h - shutdown/reboot header
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_REBOOT_H__
-#define __ASM_REBOOT_H__
-
-/* optional board specific hooks */
-extern void native_machine_restart(char *cmd);
-extern void native_machine_halt(void);
-extern void native_machine_power_off(void);
-
-/* common reboot workarounds */
-extern void bfin_gpio_reset_spi0_ssel1(void);
-
-#endif
diff --git a/include/asm-blackfin/resource.h b/include/asm-blackfin/resource.h
deleted file mode 100644
index 091355ab3495..000000000000
--- a/include/asm-blackfin/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_RESOURCE_H
-#define _BFIN_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif                          /* _BFIN_RESOURCE_H */
diff --git a/include/asm-blackfin/scatterlist.h b/include/asm-blackfin/scatterlist.h
deleted file mode 100644
index 04f448711cd0..000000000000
--- a/include/asm-blackfin/scatterlist.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _BLACKFIN_SCATTERLIST_H
-#define _BLACKFIN_SCATTERLIST_H
-
-#include <linux/mm.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long sg_magic;
-#endif
-        unsigned long page_link;
-        unsigned int offset;
-        dma_addr_t dma_address;
-        unsigned int length;
-};
-
-/*
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns, or alternatively stop on the first sg_dma_len(sg) which
- * is 0.
- */
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->length)
-
-#define ISA_DMA_THRESHOLD       (0xffffffff)
-
-#endif                          /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/include/asm-blackfin/sections.h b/include/asm-blackfin/sections.h
deleted file mode 100644
index 1443c3353a8c..000000000000
--- a/include/asm-blackfin/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _BLACKFIN_SECTIONS_H
-#define _BLACKFIN_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
deleted file mode 100644
index 02cfd09b5a99..000000000000
--- a/include/asm-blackfin/segment.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _BFIN_SEGMENT_H
-#define _BFIN_SEGMENT_H
-
-#define KERNEL_DS   (0x5)
-#define USER_DS     (0x1)
-
-#endif                          /* _BFIN_SEGMENT_H */
diff --git a/include/asm-blackfin/sembuf.h b/include/asm-blackfin/sembuf.h
deleted file mode 100644
index 18deb5c7fa5d..000000000000
--- a/include/asm-blackfin/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _BFIN_SEMBUF_H
-#define _BFIN_SEMBUF_H
-
-/*
- * The semid64_ds structure for bfin architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;      /* last semop time */
-        unsigned long __unused1;
-        __kernel_time_t sem_ctime;      /* last change time */
-        unsigned long __unused2;
-        unsigned long sem_nsems;        /* no. of semaphores in array */
-        unsigned long __unused3;
-        unsigned long __unused4;
-};
-
-#endif                          /* _BFIN_SEMBUF_H */
diff --git a/include/asm-blackfin/serial.h b/include/asm-blackfin/serial.h
deleted file mode 100644
index 994dd869558c..000000000000
--- a/include/asm-blackfin/serial.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-blackfin/serial.h
- */
-
-#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
deleted file mode 100644
index 01c8c6cbe6fc..000000000000
--- a/include/asm-blackfin/setup.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
-** asm/setup.h -- Definition of the Linux/bfin setup information
-**
-** This file is subject to the terms and conditions of the GNU General Public
-** License.  See the file COPYING in the main directory of this archive
-** for more details.
-**
-** Copyright Lineo, Inc 2001          Tony Kou
-**
-*/
-
-#ifndef _BFIN_SETUP_H
-#define _BFIN_SETUP_H
-
-#define COMMAND_LINE_SIZE       512
-
-#endif                          /* _BFIN_SETUP_H */
diff --git a/include/asm-blackfin/shmbuf.h b/include/asm-blackfin/shmbuf.h
deleted file mode 100644
index 612436303e89..000000000000
--- a/include/asm-blackfin/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _BFIN_SHMBUF_H
-#define _BFIN_SHMBUF_H
-
-/*
- * The shmid64_ds structure for bfin architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm shm_perm;     /* operation perms */
-        size_t shm_segsz;       /* size of segment (bytes) */
-        __kernel_time_t shm_atime;      /* last attach time */
-        unsigned long __unused1;
-        __kernel_time_t shm_dtime;      /* last detach time */
-        unsigned long __unused2;
-        __kernel_time_t shm_ctime;      /* last change time */
-        unsigned long __unused3;
-        __kernel_pid_t shm_cpid;        /* pid of creator */
-        __kernel_pid_t shm_lpid;        /* pid of last operator */
-        unsigned long shm_nattch;       /* no. of current attaches */
-        unsigned long __unused4;
-        unsigned long __unused5;
-};
-
-struct shminfo64 {
-        unsigned long shmmax;
-        unsigned long shmmin;
-        unsigned long shmmni;
-        unsigned long shmseg;
-        unsigned long shmall;
-        unsigned long __unused1;
-        unsigned long __unused2;
-        unsigned long __unused3;
-        unsigned long __unused4;
-};
-
-#endif                          /* _BFIN_SHMBUF_H */
diff --git a/include/asm-blackfin/shmparam.h b/include/asm-blackfin/shmparam.h
deleted file mode 100644
index 3c03906b7664..000000000000
--- a/include/asm-blackfin/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_SHMPARAM_H
-#define _BFIN_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE        /* attach addr a multiple of this */
-
-#endif                          /* _BFIN_SHMPARAM_H */
diff --git a/include/asm-blackfin/sigcontext.h b/include/asm-blackfin/sigcontext.h
deleted file mode 100644
index ce00b03c2775..000000000000
--- a/include/asm-blackfin/sigcontext.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
-#define _ASM_BLACKFIN_SIGCONTEXT_H
-
-/* Add new entries at the end of the structure only.  */
-struct sigcontext {
-        unsigned long sc_r0;
-        unsigned long sc_r1;
-        unsigned long sc_r2;
-        unsigned long sc_r3;
-        unsigned long sc_r4;
-        unsigned long sc_r5;
-        unsigned long sc_r6;
-        unsigned long sc_r7;
-        unsigned long sc_p0;
-        unsigned long sc_p1;
-        unsigned long sc_p2;
-        unsigned long sc_p3;
-        unsigned long sc_p4;
-        unsigned long sc_p5;
-        unsigned long sc_usp;
-        unsigned long sc_a0w;
-        unsigned long sc_a1w;
-        unsigned long sc_a0x;
-        unsigned long sc_a1x;
-        unsigned long sc_astat;
-        unsigned long sc_rets;
-        unsigned long sc_pc;
-        unsigned long sc_retx;
-        unsigned long sc_fp;
-        unsigned long sc_i0;
-        unsigned long sc_i1;
-        unsigned long sc_i2;
-        unsigned long sc_i3;
-        unsigned long sc_m0;
-        unsigned long sc_m1;
-        unsigned long sc_m2;
-        unsigned long sc_m3;
-        unsigned long sc_l0;
-        unsigned long sc_l1;
-        unsigned long sc_l2;
-        unsigned long sc_l3;
-        unsigned long sc_b0;
-        unsigned long sc_b1;
-        unsigned long sc_b2;
-        unsigned long sc_b3;
-        unsigned long sc_lc0;
-        unsigned long sc_lc1;
-        unsigned long sc_lt0;
-        unsigned long sc_lt1;
-        unsigned long sc_lb0;
-        unsigned long sc_lb1;
-        unsigned long sc_seqstat;
-};
-
-#endif
diff --git a/include/asm-blackfin/siginfo.h b/include/asm-blackfin/siginfo.h
deleted file mode 100644
index eca4565cea37..000000000000
--- a/include/asm-blackfin/siginfo.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef _BFIN_SIGINFO_H
-#define _BFIN_SIGINFO_H
-
-#include <linux/types.h>
-#include <asm-generic/siginfo.h>
-
-#define UID16_SIGINFO_COMPAT_NEEDED
-
-#define si_uid16        _sifields._kill._uid
-
-#define ILL_ILLPARAOP   (__SI_FAULT|2)  /* illegal opcode combine ********** */
-#define ILL_ILLEXCPT    (__SI_FAULT|4)  /* unrecoverable exception ********** */
-#define ILL_CPLB_VI     (__SI_FAULT|9)  /* D/I CPLB protect violation ******** */
-#define ILL_CPLB_MISS   (__SI_FAULT|10) /* D/I CPLB miss ******** */
-#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */
-
-/*
- * SIGBUS si_codes
- */
-#define BUS_OPFETCH     (__SI_FAULT|4)  /* error from instruction fetch ******** */
-
-/*
- * SIGTRAP si_codes
- */
-#define TRAP_STEP       (__SI_FAULT|1)  /* single-step breakpoint************* */
-#define TRAP_TRACEFLOW  (__SI_FAULT|2)  /* trace buffer overflow ************* */
-#define TRAP_WATCHPT    (__SI_FAULT|3)  /* watchpoint match      ************* */
-#define TRAP_ILLTRAP    (__SI_FAULT|4)  /* illegal trap          ************* */
-
-/*
- * SIGSEGV si_codes
- */
-#define SEGV_STACKFLOW  (__SI_FAULT|3)  /* stack overflow */
-
-#endif
diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h
deleted file mode 100644
index 87951d251458..000000000000
--- a/include/asm-blackfin/signal.h
+++ /dev/null
@@ -1,160 +0,0 @@
-#ifndef _BLACKFIN_SIGNAL_H
-#define _BLACKFIN_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-#define _NSIG           64
-#define _NSIG_BPW       32
-#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;     /* at least 32 bits */
-
-typedef struct {
-        unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG            32
-typedef unsigned long sigset_t;
-
-#endif                          /* __KERNEL__ */
-
-#define SIGHUP           1
-#define SIGINT           2
-#define SIGQUIT          3
-#define SIGILL           4
-#define SIGTRAP          5
-#define SIGABRT          6
-#define SIGIOT           6
-#define SIGBUS           7
-#define SIGFPE           8
-#define SIGKILL          9
-#define SIGUSR1         10
-#define SIGSEGV         11
-#define SIGUSR2         12
-#define SIGPIPE         13
-#define SIGALRM         14
-#define SIGTERM         15
-#define SIGSTKFLT       16
-#define SIGCHLD         17
-#define SIGCONT         18
-#define SIGSTOP         19
-#define SIGTSTP         20
-#define SIGTTIN         21
-#define SIGTTOU         22
-#define SIGURG          23
-#define SIGXCPU         24
-#define SIGXFSZ         25
-#define SIGVTALRM       26
-#define SIGPROF         27
-#define SIGWINCH        28
-#define SIGIO           29
-#define SIGPOLL         SIGIO
-/*
-#define SIGLOST         29
-*/
-#define SIGPWR          30
-#define SIGSYS          31
-#define SIGUNUSED       31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP    0x00000001
-#define SA_NOCLDWAIT    0x00000002      /* not supported yet */
-#define SA_SIGINFO      0x00000004
-#define SA_ONSTACK      0x08000000
-#define SA_RESTART      0x10000000
-#define SA_NODEFER      0x40000000
-#define SA_RESETHAND    0x80000000
-
-#define SA_NOMASK       SA_NODEFER
-#define SA_ONESHOT      SA_RESETHAND
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK      1
-#define SS_DISABLE      2
-
-#define MINSIGSTKSZ     2048
-#define SIGSTKSZ        8192
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct old_sigaction {
-        __sighandler_t sa_handler;
-        old_sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer) (void);
-};
-
-struct sigaction {
-        __sighandler_t sa_handler;
-        unsigned long sa_flags;
-        void (*sa_restorer) (void);
-        sigset_t sa_mask;       /* mask last for extensibility */
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-};
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-        union {
-                __sighandler_t _sa_handler;
-                void (*_sa_sigaction) (int, struct siginfo *, void *);
-        } _u;
-        sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer) (void);
-};
-
-#define sa_handler      _u._sa_handler
-#define sa_sigaction    _u._sa_sigaction
-
-#endif                          /* __KERNEL__ */
-
-typedef struct sigaltstack {
-        void __user *ss_sp;
-        int ss_flags;
-        size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-
-#include <asm/sigcontext.h>
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BLACKFIN_SIGNAL_H */
diff --git a/include/asm-blackfin/socket.h b/include/asm-blackfin/socket.h
deleted file mode 100644
index 2ca702e44d47..000000000000
--- a/include/asm-blackfin/socket.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockoptions(2) */
-#define SOL_SOCKET      1
-
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_ACCEPTCONN           30
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-#define SO_MARK                 36
-
-#endif                          /* _ASM_SOCKET_H */
diff --git a/include/asm-blackfin/sockios.h b/include/asm-blackfin/sockios.h
deleted file mode 100644
index 426b89bfaa8b..000000000000
--- a/include/asm-blackfin/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_BFIN_SOCKIOS__
-#define __ARCH_BFIN_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906  /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907  /* Get stamp (timespec) */
-
-#endif                          /* __ARCH_BFIN_SOCKIOS__ */
diff --git a/include/asm-blackfin/spinlock.h b/include/asm-blackfin/spinlock.h
deleted file mode 100644
index 64e908a50646..000000000000
--- a/include/asm-blackfin/spinlock.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BFIN_SPINLOCK_H
-#define __BFIN_SPINLOCK_H
-
-#error blackfin architecture does not support SMP spin lock yet
-
-#endif
diff --git a/include/asm-blackfin/stat.h b/include/asm-blackfin/stat.h
deleted file mode 100644
index d2b6f11ec231..000000000000
--- a/include/asm-blackfin/stat.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef _BFIN_STAT_H
-#define _BFIN_STAT_H
-
-struct stat {
-        unsigned short st_dev;
-        unsigned short __pad1;
-        unsigned long st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned short __pad2;
-        unsigned long st_size;
-        unsigned long st_blksize;
-        unsigned long st_blocks;
-        unsigned long st_atime;
-        unsigned long __unused1;
-        unsigned long st_mtime;
-        unsigned long __unused2;
-        unsigned long st_ctime;
-        unsigned long __unused3;
-        unsigned long __unused4;
-        unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-        unsigned long long st_dev;
-        unsigned char __pad1[4];
-
-#define STAT64_HAS_BROKEN_ST_INO        1
-        unsigned long __st_ino;
-
-        unsigned int st_mode;
-        unsigned int st_nlink;
-
-        unsigned long st_uid;
-        unsigned long st_gid;
-
-        unsigned long long st_rdev;
-        unsigned char __pad2[4];
-
-        long long st_size;
-        unsigned long st_blksize;
-
-        long long st_blocks;    /* Number 512-byte blocks allocated. */
-
-        unsigned long st_atime;
-        unsigned long st_atime_nsec;
-
-        unsigned long st_mtime;
-        unsigned long st_mtime_nsec;
-
-        unsigned long st_ctime;
-        unsigned long st_ctime_nsec;
-
-        unsigned long long st_ino;
-};
-
-#endif                          /* _BFIN_STAT_H */
diff --git a/include/asm-blackfin/statfs.h b/include/asm-blackfin/statfs.h
deleted file mode 100644
index 350672091ba3..000000000000
--- a/include/asm-blackfin/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_STATFS_H
-#define _BFIN_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif                          /* _BFIN_STATFS_H */
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
deleted file mode 100644
index 321f4d96e4ae..000000000000
--- a/include/asm-blackfin/string.h
+++ /dev/null
@@ -1,137 +0,0 @@
-#ifndef _BLACKFIN_STRING_H_
-#define _BLACKFIN_STRING_H_
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__               /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-extern inline char *strcpy(char *dest, const char *src)
-{
-        char *xdest = dest;
-        char temp = 0;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%2 = B [%1++] (Z);"
-                "B [%0++] = %2;"
-                "CC = %2;"
-                "if cc jump 1b (bp);"
-                : "+&a" (dest), "+&a" (src), "=&d" (temp)
-                :
-                : "memory", "CC");
-
-        return xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-extern inline char *strncpy(char *dest, const char *src, size_t n)
-{
-        char *xdest = dest;
-        char temp = 0;
-
-        if (n == 0)
-                return xdest;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%3 = B [%1++] (Z);"
-                "B [%0++] = %3;"
-                "CC = %3;"
-                "if ! cc jump 2f;"
-                "%2 += -1;"
-                "CC = %2 == 0;"
-                "if ! cc jump 1b (bp);"
-                "jump 4f;"
-                "2:"
-                /* if src is shorter than n, we need to null pad bytes now */
-                "%3 = 0;"
-                "3:"
-                "%2 += -1;"
-                "CC = %2 == 0;"
-                "if cc jump 4f;"
-                "B [%0++] = %3;"
-                "jump 3b;"
-                "4:"
-                : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
-                :
-                : "memory", "CC");
-
-        return xdest;
-}
-
-#define __HAVE_ARCH_STRCMP
-extern inline int strcmp(const char *cs, const char *ct)
-{
-        /* need to use int's here so the char's in the assembly don't get
-         * sign extended incorrectly when we don't want them to be
-         */
-        int __res1, __res2;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%2 = B[%0++] (Z);"      /* get *cs */
-                "%3 = B[%1++] (Z);"      /* get *ct */
-                "CC = %2 == %3;"         /* compare a byte */
-                "if ! cc jump 2f;"       /* not equal, break out */
-                "CC = %2;"               /* at end of cs? */
-                "if cc jump 1b (bp);"    /* no, keep going */
-                "jump.s 3f;"             /* strings are equal */
-                "2:"
-                "%2 = %2 - %3;"          /* *cs - *ct */
-                "3:"
-                : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
-                :
-                : "memory", "CC");
-
-        return __res1;
-}
-
-#define __HAVE_ARCH_STRNCMP
-extern inline int strncmp(const char *cs, const char *ct, size_t count)
-{
-        /* need to use int's here so the char's in the assembly don't get
-         * sign extended incorrectly when we don't want them to be
-         */
-        int __res1, __res2;
-
-        if (!count)
-                return 0;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%3 = B[%0++] (Z);"      /* get *cs */
-                "%4 = B[%1++] (Z);"      /* get *ct */
-                "CC = %3 == %4;"         /* compare a byte */
-                "if ! cc jump 3f;"       /* not equal, break out */
-                "CC = %3;"               /* at end of cs? */
-                "if ! cc jump 4f;"       /* yes, all done */
-                "%2 += -1;"              /* no, adjust count */
-                "CC = %2 == 0;"
-                "if ! cc jump 1b;"       /* more to do, keep going */
-                "2:"
-                "%3 = 0;"                /* strings are equal */
-                "jump.s 4f;"
-                "3:"
-                "%3 = %3 - %4;"          /* *cs - *ct */
-                "4:"
-                : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
-                :
-                : "memory", "CC");
-
-        return __res1;
-}
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t count);
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *d, const void *s, size_t count);
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *s, int c, size_t n);
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#endif /*__KERNEL__*/
-#endif                          /* _BLACKFIN_STRING_H_ */
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
deleted file mode 100644
index 51494ef5bb41..000000000000
--- a/include/asm-blackfin/system.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * File:        include/asm/system.h
- * Based on:
- * Author:      Tony Kou (tonyko@lineo.ca)
- *              Copyright (c) 2002 Arcturus Networks Inc.
- *                    (www.arcturusnetworks.com)
- *              Copyright (c) 2003 Metrowerks (www.metrowerks.com)
- *              Copyright (c) 2004 Analog Device Inc.
- * Created:     25Jan2001 - Tony Kou
- * Description: system.h include file
- *
- * Modified:     22Sep2006 - Robin Getz
- *                - move include blackfin.h down, so I can get access to
- *                   irq functions in other include files.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BLACKFIN_SYSTEM_H
-#define _BLACKFIN_SYSTEM_H
-
-#include <linux/linkage.h>
-#include <linux/compiler.h>
-#include <asm/mach/anomaly.h>
-
-/*
- * Interrupt configuring macros.
- */
-
-extern unsigned long irq_flags;
-
-#define local_irq_enable() \
-        __asm__ __volatile__( \
-                "sti %0;" \
-                : \
-                : "d" (irq_flags) \
-        )
-
-#define local_irq_disable() \
-        do { \
-                int __tmp_dummy; \
-                __asm__ __volatile__( \
-                        "cli %0;" \
-                        : "=d" (__tmp_dummy) \
-                ); \
-        } while (0)
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000244 \
-                ".align 8;" \
-                "sti %0;" \
-                "idle;" \
-                : \
-                : "d" (irq_flags) \
-        )
-
-#ifdef CONFIG_DEBUG_HWERR
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %1;" \
-                : "=&d" (x) \
-                : "d" (0x3F) \
-        )
-#else
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                : "=&d" (x) \
-        )
-#endif
-
-#define local_save_flags(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %0;" \
-                : "=d" (x) \
-        )
-
-#ifdef CONFIG_DEBUG_HWERR
-#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
-#else
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
-#endif
-
-#define local_irq_restore(x) \
-        do { \
-                if (irqs_enabled_from_flags(x)) \
-                        local_irq_enable(); \
-        } while (0)
-
-/* For spinlocks etc */
-#define local_irq_save(x) __save_and_cli(x)
-
-#define irqs_disabled()                         \
-({                                              \
-        unsigned long flags;                    \
-        local_save_flags(flags);                \
-        !irqs_enabled_from_flags(flags);        \
-})
-
-/*
- * Force strict CPU ordering.
- */
-#define nop()  asm volatile ("nop;\n\t"::)
-#define mb()   asm volatile (""   : : :"memory")
-#define rmb()  asm volatile (""   : : :"memory")
-#define wmb()  asm volatile (""   : : :"memory")
-#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
-
-#define read_barrier_depends()          do { } while(0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while(0)
-#endif
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-struct __xchg_dummy {
-        unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-                                   int size)
-{
-        unsigned long tmp = 0;
-        unsigned long flags = 0;
-
-        local_irq_save(flags);
-
-        switch (size) {
-        case 1:
-                __asm__ __volatile__
-                        ("%0 = b%2 (z);\n\t"
-                         "b%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        case 2:
-                __asm__ __volatile__
-                        ("%0 = w%2 (z);\n\t"
-                         "w%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        case 4:
-                __asm__ __volatile__
-                        ("%0 = %2;\n\t"
-                         "%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        }
-        local_irq_restore(flags);
-        return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)                                               \
-        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-                        (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#define prepare_to_switch()     do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/blackfin.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#define switch_to(prev,next,last) \
-do {    \
-        memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
-                sizeof *L1_SCRATCH_TASK_INFO); \
-        memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
-                sizeof *L1_SCRATCH_TASK_INFO); \
-        (last) = resume (prev, next);   \
-} while (0)
-
-#endif                          /* _BLACKFIN_SYSTEM_H */
diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h
deleted file mode 100644
index f37feb7cf895..000000000000
--- a/include/asm-blackfin/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __ARCH_BFIN_TERMBITS_H__
-#define __ARCH_BFIN_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;       /* input mode flags */
-        tcflag_t c_oflag;       /* output mode flags */
-        tcflag_t c_cflag;       /* control mode flags */
-        tcflag_t c_lflag;       /* local mode flags */
-        cc_t c_line;            /* line discipline */
-        cc_t c_cc[NCCS];        /* control characters */
-};
-
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define BOTHER  0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate */
-#define CMSPAR    010000000000  /* mark or space (stick) parity */
-#define CRTSCTS   020000000000  /* flow control */
-
-#define IBSHIFT 16      /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif                          /* __ARCH_BFIN_TERMBITS_H__ */
diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h
deleted file mode 100644
index d50d063c605a..000000000000
--- a/include/asm-blackfin/termios.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef __BFIN_TERMIOS_H__
-#define __BFIN_TERMIOS_H__
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-        unsigned short c_iflag; /* input mode flags */
-        unsigned short c_oflag; /* output mode flags */
-        unsigned short c_cflag; /* control mode flags */
-        unsigned short c_lflag; /* local mode flags */
-        unsigned char c_line;   /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*      intr=^C         quit=^\         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-        unsigned short __tmp; \
-        get_user(__tmp,&(termio)->x); \
-        *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) \
-        copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) \
-        copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) \
-        copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) \
-        copy_to_user(u, k, sizeof(struct termios))
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* __BFIN_TERMIOS_H__ */
diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h
deleted file mode 100644
index 642769329d12..000000000000
--- a/include/asm-blackfin/thread_info.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * File:         include/asm-blackfin/thread_info.h
- * Based on:     include/asm-m68knommu/thread_info.h
- * Author:       LG Soft India
- *               Copyright (C) 2004-2005 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  Blackfin low-level thread information
- * Modified:
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-#include <asm/entry.h>
-#include <asm/l1layout.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-
-/* Thread Align Mask to reach to the top of the stack
- * for any process
- */
-#define ALIGN_PAGE_MASK         0xffffe000
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE             8192    /* 2 pages */
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long mm_segment_t;
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-
-struct thread_info {
-        struct task_struct *task;       /* main task structure */
-        struct exec_domain *exec_domain;        /* execution domain */
-        unsigned long flags;    /* low level flags */
-        int cpu;                /* cpu we're on */
-        int preempt_count;      /* 0 => preemptable, <0 => BUG */
-        mm_segment_t addr_limit;        /* address limit */
-        struct restart_block restart_block;
-        struct l1_scratch_task_info l1_task_info;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task           = &tsk,                 \
-        .exec_domain    = &default_exec_domain, \
-        .flags          = 0,                    \
-        .cpu            = 0,                    \
-        .preempt_count  = 1,                    \
-        .restart_block  = {                     \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-/* Given a task stack pointer, you can find its corresponding
- * thread_info structure just by masking it to the THREAD_SIZE
- * boundary (currently 8K as you can see above).
- */
-__attribute_const__
-static inline struct thread_info *current_thread_info(void)
-{
-        struct thread_info *ti;
-      __asm__("%0 = sp;": "=&d"(ti):
-        );
-        return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
-}
-
-#endif                          /* __ASSEMBLY__ */
-
-/*
- * Offsets in thread_info structure, used in assembly code
- */
-#define TI_TASK         0
-#define TI_EXECDOMAIN   4
-#define TI_FLAGS        8
-#define TI_CPU          12
-#define TI_PREEMPT      16
-
-#define PREEMPT_ACTIVE  0x4000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_SIGPENDING          1       /* signal pending */
-#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
-                                           TIF_NEED_RESCHED */
-#define TIF_MEMDIE              4
-#define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
-#define TIF_FREEZE              6       /* is freezing for suspend */
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
-
-#define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
deleted file mode 100644
index ddc43ce38533..000000000000
--- a/include/asm-blackfin/time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * asm-blackfin/time.h:
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIME_H
-#define _ASM_BLACKFIN_TIME_H
-
-/*
- * The way that the Blackfin core timer works is:
- *  - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
- *  - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
- *
- * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
- *    10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
- *    (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
- *    to use TSCALE, and program it to zero (which is pass CCLK through).
- *    If you feel like using it, try to keep HZ * TIMESCALE to some
- *    value that divides easy (like power of 2).
- */
-
-#ifndef CONFIG_CPU_FREQ
-#define TIME_SCALE 1
-#define __bfin_cycles_off (0)
-#define __bfin_cycles_mod (0)
-#else
-/*
- * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
- * Whenever we change the Core Clock frequency changes we immediately
- * adjust the Core Timer Presale Register. This way we don't lose time.
- */
-#define TIME_SCALE 4
-extern unsigned long long __bfin_cycles_off;
-extern unsigned int __bfin_cycles_mod;
-#endif
-
-#endif
diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h
deleted file mode 100644
index 22b0806161bb..000000000000
--- a/include/asm-blackfin/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * asm-blackfin/timex.h: cpu cycles!
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIMEX_H
-#define _ASM_BLACKFIN_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
-        unsigned long tmp, tmp2;
-        __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
-        return tmp | ((cycles_t)tmp2 << 32);
-}
-
-#endif
diff --git a/include/asm-blackfin/tlb.h b/include/asm-blackfin/tlb.h
deleted file mode 100644
index 89a12ee916d8..000000000000
--- a/include/asm-blackfin/tlb.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _BLACKFIN_TLB_H
-#define _BLACKFIN_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma)   do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address)      do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb)          flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif                          /* _BLACKFIN_TLB_H */
diff --git a/include/asm-blackfin/tlbflush.h b/include/asm-blackfin/tlbflush.h
deleted file mode 100644
index 277b400924b8..000000000000
--- a/include/asm-blackfin/tlbflush.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _BLACKFIN_TLBFLUSH_H
-#define _BLACKFIN_TLBFLUSH_H
-
-/*
- * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
- * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
- */
-
-#include <asm/setup.h>
-
-/*
- * flush all user-space atc entries.
- */
-static inline void __flush_tlb(void)
-{
-        BUG();
-}
-
-static inline void __flush_tlb_one(unsigned long addr)
-{
-        BUG();
-}
-
-#define flush_tlb() __flush_tlb()
-
-/*
- * flush all atc entries (both kernel and user-space entries).
- */
-static inline void flush_tlb_all(void)
-{
-        BUG();
-}
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-        BUG();
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-                                  unsigned long addr)
-{
-        BUG();
-}
-
-static inline void flush_tlb_range(struct mm_struct *mm,
-                                   unsigned long start, unsigned long end)
-{
-        BUG();
-}
-
-static inline void flush_tlb_kernel_page(unsigned long addr)
-{
-        BUG();
-}
-
-#endif
diff --git a/include/asm-blackfin/topology.h b/include/asm-blackfin/topology.h
deleted file mode 100644
index acee23987897..000000000000
--- a/include/asm-blackfin/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_BLACKFIN_TOPOLOGY_H
-#define _ASM_BLACKFIN_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif                          /* _ASM_BLACKFIN_TOPOLOGY_H */
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
deleted file mode 100644
index 312b596b9731..000000000000
--- a/include/asm-blackfin/trace.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _BLACKFIN_TRACE_
-#define _BLACKFIN_TRACE_
-
-/* Normally, we use ON, but you can't turn on software expansion until
- * interrupts subsystem is ready
- */
-
-#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-#define BFIN_TRACE_ON   (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
-#else
-#define BFIN_TRACE_ON   (BFIN_TRACE_INIT)
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long trace_buff_offset;
-extern unsigned long software_trace_buff[];
-
-/* Trace Macros for C files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_save(x) \
-        do { \
-                (x) = bfin_read_TBUFCTL(); \
-                bfin_write_TBUFCTL((x) & ~TBUFEN); \
-        } while (0)
-
-#define trace_buffer_restore(x) \
-        do { \
-                bfin_write_TBUFCTL((x));        \
-        } while (0)
-#else /* DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_save(x)
-#define trace_buffer_restore(x)
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#else
-/* Trace Macros for Assembly files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_stop(preg, dreg)   \
-        preg.L = LO(TBUFCTL);           \
-        preg.H = HI(TBUFCTL);           \
-        dreg = 0x1;                     \
-        [preg] = dreg;
-
-#define trace_buffer_init(preg, dreg) \
-        preg.L = LO(TBUFCTL);         \
-        preg.H = HI(TBUFCTL);         \
-        dreg = BFIN_TRACE_INIT;       \
-        [preg] = dreg;
-
-#define trace_buffer_save(preg, dreg) \
-        preg.L = LO(TBUFCTL); \
-        preg.H = HI(TBUFCTL); \
-        dreg = [preg]; \
-        [--sp] = dreg; \
-        dreg = 0x1; \
-        [preg] = dreg;
-
-#define trace_buffer_restore(preg, dreg) \
-        preg.L = LO(TBUFCTL); \
-        preg.H = HI(TBUFCTL); \
-        dreg = [sp++]; \
-        [preg] = dreg;
-
-#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_init(preg, dreg)
-#define trace_buffer_save(preg, dreg)
-#define trace_buffer_restore(preg, dreg)
-
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_HWTRACE_SAVE(preg, dreg)    trace_buffer_save(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
-#else
-# define DEBUG_HWTRACE_SAVE(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif                          /* _BLACKFIN_TRACE_ */
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
deleted file mode 100644
index f0e5f940d9ca..000000000000
--- a/include/asm-blackfin/traps.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- *  linux/include/asm/traps.h
- *
- *  Copyright (C) 1993        Hamish Macdonald
- *
- *  Lineo, Inc    Jul 2001    Tony Kou
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS         (0)
-#define VEC_EXCPT01     (1)
-#define VEC_EXCPT02     (2)
-#define VEC_EXCPT03     (3)
-#define VEC_EXCPT04     (4)
-#define VEC_EXCPT05     (5)
-#define VEC_EXCPT06     (6)
-#define VEC_EXCPT07     (7)
-#define VEC_EXCPT08     (8)
-#define VEC_EXCPT09     (9)
-#define VEC_EXCPT10     (10)
-#define VEC_EXCPT11     (11)
-#define VEC_EXCPT12     (12)
-#define VEC_EXCPT13     (13)
-#define VEC_EXCPT14     (14)
-#define VEC_EXCPT15     (15)
-#define VEC_STEP        (16)
-#define VEC_OVFLOW      (17)
-#define VEC_UNDEF_I     (33)
-#define VEC_ILGAL_I     (34)
-#define VEC_CPLB_VL     (35)
-#define VEC_MISALI_D    (36)
-#define VEC_UNCOV       (37)
-#define VEC_CPLB_M      (38)
-#define VEC_CPLB_MHIT   (39)
-#define VEC_WATCH       (40)
-#define VEC_ISTRU_VL    (41)    /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I    (42)
-#define VEC_CPLB_I_VL   (43)
-#define VEC_CPLB_I_M    (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES     (46)    /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR       (63)
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2(level) \
-        "System MMR Error\n" \
-        level " - An error occurred due to an invalid access to an System MMR location\n" \
-        level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
-        level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3(level) \
-        "External Memory Addressing Error\n"
-#define HWC_x12(level) \
-        "Performance Monitor Overflow\n"
-#define HWC_x18(level) \
-        "RAISE 5 instruction\n" \
-        level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default(level) \
-         "Reserved\n"
-#define EXC_0x03(level) \
-        "Application stack overflow\n" \
-        level " - Please increase the stack size of the application using elf2flt -s option,\n" \
-        level "   and/or reduce the stack use of the application.\n"
-#define EXC_0x10(level) \
-        "Single step\n" \
-        level " - When the processor is in single step mode, every instruction\n" \
-        level "   generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11(level) \
-        "Exception caused by a trace buffer full condition\n" \
-        level " - The processor takes this exception when the trace\n" \
-        level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21(level) \
-        "Undefined instruction\n" \
-        level " - May be used to emulate instructions that are not defined for\n" \
-        level "   a particular processor implementation.\n"
-#define EXC_0x22(level) \
-        "Illegal instruction combination\n" \
-        level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
-        level "   Processor Instruction Set Reference.\n"
-#define EXC_0x23(level) \
-        "Data access CPLB protection violation\n" \
-        level " - Attempted read or write to Supervisor resource,\n" \
-        level "   or illegal data memory access. \n"
-#define EXC_0x24(level) \
-        "Data access misaligned address violation\n" \
-        level " - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25(level) \
-        "Unrecoverable event\n" \
-        level " - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26(level) \
-        "Data access CPLB miss\n" \
-        level " - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27(level) \
-        "Data access multiple CPLB hits\n" \
-        level " - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28(level) \
-        "Program Sequencer Exception caused by an emulation watchpoint match\n" \
-        level " - There is a watchpoint match, and one of the EMUSW\n" \
-        level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A(level) \
-        "Instruction fetch misaligned address violation\n" \
-        level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
-        level "   exception, the return address provided in RETX is the destination address which is\n" \
-        level "   misaligned, rather than the address of the offending instruction.\n"
-#define EXC_0x2B(level) \
-        "CPLB protection violation\n" \
-        level " - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C(level) \
-        "Instruction fetch CPLB miss\n" \
-        level " - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D(level) \
-        "Instruction fetch multiple CPLB hits\n" \
-        level " - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E(level) \
-        "Illegal use of supervisor resource\n" \
-        level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
-        level "   Supervisor resources are registers and instructions that are reserved\n" \
-        level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
-        level "   only instructions.\n"
-
-#endif                          /* __ASSEMBLY__ */
-#endif                          /* _BFIN_TRAPS_H */
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
deleted file mode 100644
index 8441cbc2bf9e..000000000000
--- a/include/asm-blackfin/types.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _BFIN_TYPES_H
-#define _BFIN_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-#include <asm-generic/int-ll64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif                          /* __ASSEMBLY__ */
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#ifndef __ASSEMBLY__
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-
-#endif                          /* __ASSEMBLY__ */
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BFIN_TYPES_H */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
deleted file mode 100644
index d928b8099056..000000000000
--- a/include/asm-blackfin/uaccess.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* Changes made by Lineo Inc.    May 2001
- *
- * Based on: include/asm-m68knommu/uaccess.h
- */
-
-#ifndef __BLACKFIN_UACCESS_H
-#define __BLACKFIN_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-#ifdef CONFIG_ACCESS_CHECK
-# include <asm/bfin-global.h>
-#endif
-
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current_thread_info()->addr_limit)
-
-static inline void set_fs(mm_segment_t fs)
-{
-        current_thread_info()->addr_limit = fs;
-}
-
-#define segment_eq(a,b) ((a) == (b))
-
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-
-#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
-
-static inline int is_in_rom(unsigned long addr)
-{
-        /*
-         * What we are really trying to do is determine if addr is
-         * in an allocated kernel memory region. If not then assume
-         * we cannot free it or otherwise de-allocate it. Ideally
-         * we could restrict this to really being in a ROM or flash,
-         * but that would need to be done on a board by board basis,
-         * not globally.
-         */
-        if ((addr < _ramstart) || (addr >= _ramend))
-                return (1);
-
-        /* Default case, not in ROM */
-        return (0);
-}
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- */
-
-#ifndef CONFIG_ACCESS_CHECK
-static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
-#else
-#ifdef CONFIG_ACCESS_OK_L1
-extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
-#else
-extern int _access_ok(unsigned long addr, unsigned long size);
-#endif
-#endif
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
-        unsigned long insn, fixup;
-};
-
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x,p)                                           \
-        ({                                                      \
-                int _err = 0;                                   \
-                typeof(*(p)) _x = (x);                          \
-                typeof(*(p)) *_p = (p);                         \
-                if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
-                        _err = -EFAULT;                         \
-                }                                               \
-                else {                                          \
-                switch (sizeof (*(_p))) {                       \
-                case 1:                                         \
-                        __put_user_asm(_x, _p, B);              \
-                        break;                                  \
-                case 2:                                         \
-                        __put_user_asm(_x, _p, W);              \
-                        break;                                  \
-                case 4:                                         \
-                        __put_user_asm(_x, _p,  );              \
-                        break;                                  \
-                case 8: {                                       \
-                        long _xl, _xh;                          \
-                        _xl = ((long *)&_x)[0];                 \
-                        _xh = ((long *)&_x)[1];                 \
-                        __put_user_asm(_xl, ((long *)_p)+0, );  \
-                        __put_user_asm(_xh, ((long *)_p)+1, );  \
-                } break;                                        \
-                default:                                        \
-                        _err = __put_user_bad();                \
-                        break;                                  \
-                }                                               \
-                }                                               \
-                _err;                                           \
-        })
-
-#define __put_user(x,p) put_user(x,p)
-static inline int bad_user_access_length(void)
-{
-        panic("bad_user_access_length");
-        return -1;
-}
-
-#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
-                           __FILE__, __LINE__, __func__),\
-                           bad_user_access_length(), (-EFAULT))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long *)(x))
-
-#define __put_user_asm(x,p,bhw)                         \
-        __asm__ (#bhw"[%1] = %0;\n\t"                   \
-                 : /* no outputs */                     \
-                 :"d" (x),"a" (__ptr(p)) : "memory")
-
-#define get_user(x,p)                                                   \
-        ({                                                              \
-                int _err = 0;                                           \
-                typeof(*(p)) *_p = (p);                                 \
-                if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) {       \
-                        _err = -EFAULT;                                 \
-                }                                                       \
-                else {                                                  \
-                switch (sizeof(*(_p))) {                                \
-                case 1:                                                 \
-                        __get_user_asm(x, _p, B,(Z));                   \
-                        break;                                          \
-                case 2:                                                 \
-                        __get_user_asm(x, _p, W,(Z));                   \
-                        break;                                          \
-                case 4:                                                 \
-                        __get_user_asm(x, _p,  , );                     \
-                        break;                                          \
-                case 8: {                                               \
-                        unsigned long _xl, _xh;                         \
-                        __get_user_asm(_xl, ((unsigned long *)_p)+0,  , ); \
-                        __get_user_asm(_xh, ((unsigned long *)_p)+1,  , ); \
-                        ((unsigned long *)&x)[0] = _xl;                 \
-                        ((unsigned long *)&x)[1] = _xh;                 \
-                } break;                                                \
-                default:                                                \
-                        x = 0;                                          \
-                        printk(KERN_INFO "get_user_bad: %s:%d %s\n",    \
-                               __FILE__, __LINE__, __func__);   \
-                        _err = __get_user_bad();                        \
-                        break;                                          \
-                }                                                       \
-                }                                                       \
-                _err;                                                   \
-        })
-
-#define __get_user(x,p) get_user(x,p)
-
-#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
-
-#define __get_user_asm(x,p,bhw,option)                          \
-        {                                                       \
-                unsigned long _tmp;                             \
-                __asm__ ("%0 =" #bhw "[%1]"#option";\n\t"       \
-                         : "=d" (_tmp)                          \
-                         : "a" (__ptr(p)));                     \
-                (x) = (__typeof__(*(p))) _tmp;                  \
-        }
-
-#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
-#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n))\
-                                                 return retval; })
-
-#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
-                                                   return retval; })
-
-static inline long copy_from_user(void *to,
-                                  const void __user * from, unsigned long n)
-{
-        if (access_ok(VERIFY_READ, from, n))
-                memcpy(to, from, n);
-        else
-                return n;
-        return 0;
-}
-
-static inline long copy_to_user(void *to,
-                                const void __user * from, unsigned long n)
-{
-        if (access_ok(VERIFY_WRITE, to, n))
-                memcpy(to, from, n);
-        else
-                return n;
-        return 0;
-}
-
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long strncpy_from_user(char *dst,
-                                     const char *src, long count)
-{
-        char *tmp;
-        if (!access_ok(VERIFY_READ, src, 1))
-                return -EFAULT;
-        strncpy(dst, src, count);
-        for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
-        return (tmp - dst);
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-static inline long strnlen_user(const char *src, long n)
-{
-        return (strlen(src) + 1);
-}
-
-#define strlen_user(str) strnlen_user(str, 32767)
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long __clear_user(void *to, unsigned long n)
-{
-        memset(to, 0, n);
-        return 0;
-}
-
-#define clear_user(to, n) __clear_user(to, n)
-
-#endif                          /* _BLACKFIN_UACCESS_H */
diff --git a/include/asm-blackfin/ucontext.h b/include/asm-blackfin/ucontext.h
deleted file mode 100644
index 4a4e3856beba..000000000000
--- a/include/asm-blackfin/ucontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/** Changes made by Tony Kou   Lineo Inc.    May 2001
- *
- *  Based on: include/m68knommu/ucontext.h
- */
-
-#ifndef _BLACKFIN_UCONTEXT_H
-#define _BLACKFIN_UCONTEXT_H
-
-struct ucontext {
-        unsigned long uc_flags; /* the others are necessary */
-        struct ucontext *uc_link;
-        stack_t uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t uc_sigmask;    /* mask last for extensibility */
-};
-
-#endif                          /* _BLACKFIN_UCONTEXT_H */
diff --git a/include/asm-blackfin/unaligned.h b/include/asm-blackfin/unaligned.h
deleted file mode 100644
index fd8a1d634945..000000000000
--- a/include/asm-blackfin/unaligned.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_BLACKFIN_UNALIGNED_H
-#define _ASM_BLACKFIN_UNALIGNED_H
-
-#include <linux/unaligned/le_struct.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned   __get_unaligned_le
-#define put_unaligned   __put_unaligned_le
-
-#endif /* _ASM_BLACKFIN_UNALIGNED_H */
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
deleted file mode 100644
index 42955d0c439b..000000000000
--- a/include/asm-blackfin/unistd.h
+++ /dev/null
@@ -1,432 +0,0 @@
-#ifndef __ASM_BFIN_UNISTD_H
-#define __ASM_BFIN_UNISTD_H
-/*
- * This file contains the system call numbers.
- */
-#define __NR_restart_syscall      0
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-                                /* 7 __NR_waitpid obsolete */
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_time                13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_chown               16
-                                /* 17 __NR_break obsolete */
-                                /* 18 __NR_oldstat obsolete */
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-                                /* 22 __NR_umount obsolete */
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_ptrace              26
-#define __NR_alarm               27
-                                /* 28 __NR_oldfstat obsolete */
-#define __NR_pause               29
-                                /* 30 __NR_utime obsolete */
-                                /* 31 __NR_stty obsolete */
-                                /* 32 __NR_gtty obsolete */
-#define __NR_access              33
-#define __NR_nice                34
-                                /* 35 __NR_ftime obsolete */
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-                                /* 44 __NR_prof obsolete */
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-                                /* 48 __NR_signal obsolete */
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_umount2             52
-                                /* 53 __NR_lock obsolete */
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-                                /* 56 __NR_mpx obsolete */
-#define __NR_setpgid             57
-                                /* 58 __NR_ulimit obsolete */
-                                /* 59 __NR_oldolduname obsolete */
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-                                /* 67 __NR_sigaction obsolete */
-#define __NR_sgetmask            68
-#define __NR_ssetmask            69
-#define __NR_setreuid            70
-#define __NR_setregid            71
-                                /* 72 __NR_sigsuspend obsolete */
-                                /* 73 __NR_sigpending obsolete */
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-                                /* 76 __NR_old_getrlimit obsolete */
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-                                /* 82 __NR_select obsolete */
-#define __NR_symlink             83
-                                /* 84 __NR_oldlstat obsolete */
-#define __NR_readlink            85
-                                /* 86 __NR_uselib obsolete */
-                                /* 87 __NR_swapon obsolete */
-#define __NR_reboot              88
-                                /* 89 __NR_readdir obsolete */
-                                /* 90 __NR_mmap obsolete */
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-                                /* 98 __NR_profil obsolete */
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-                                /* 101 __NR_ioperm */
-                                /* 102 __NR_socketcall obsolete */
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-                                /* 109 __NR_olduname obsolete */
-                                /* 110 __NR_iopl obsolete */
-#define __NR_vhangup            111
-                                /* 112 __NR_idle obsolete */
-                                /* 113 __NR_vm86old */
-#define __NR_wait4              114
-                                /* 115 __NR_swapoff obsolete */
-#define __NR_sysinfo            116
-                                /* 117 __NR_ipc oboslete */
-#define __NR_fsync              118
-                                /* 119 __NR_sigreturn obsolete */
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-                                /* 123 __NR_modify_ldt obsolete */
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-                                /* 126 __NR_sigprocmask obsolete */
-                                /* 127 __NR_create_module obsolete */
-#define __NR_init_module        128
-#define __NR_delete_module      129
-                                /* 130 __NR_get_kernel_syms obsolete */
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-                                /* 135 was sysfs */
-#define __NR_personality        136
-                                /* 137 __NR_afs_syscall */
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-                                /* 142 __NR__newselect obsolete */
-#define __NR_flock              143
-                                /* 144 __NR_msync obsolete */
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-                                /* 150 __NR_mlock */
-                                /* 151 __NR_munlock */
-                                /* 152 __NR_mlockall */
-                                /* 153 __NR_munlockall */
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-                                /* 166 __NR_vm86 */
-                                /* 167 __NR_query_module */
-                                /* 168 __NR_poll */
-#define __NR_nfsservctl         169
-#define __NR_setresgid          170
-#define __NR_getresgid          171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn       173
-#define __NR_rt_sigaction       174
-#define __NR_rt_sigprocmask     175
-#define __NR_rt_sigpending      176
-#define __NR_rt_sigtimedwait    177
-#define __NR_rt_sigqueueinfo    178
-#define __NR_rt_sigsuspend      179
-#define __NR_pread              180
-#define __NR_pwrite             181
-#define __NR_lchown             182
-#define __NR_getcwd             183
-#define __NR_capget             184
-#define __NR_capset             185
-#define __NR_sigaltstack        186
-#define __NR_sendfile           187
-                                /* 188 __NR_getpmsg */
-                                /* 189 __NR_putpmsg */
-#define __NR_vfork              190
-#define __NR_getrlimit          191
-#define __NR_mmap2              192
-#define __NR_truncate64         193
-#define __NR_ftruncate64        194
-#define __NR_stat64             195
-#define __NR_lstat64            196
-#define __NR_fstat64            197
-#define __NR_chown32            198
-#define __NR_getuid32           199
-#define __NR_getgid32           200
-#define __NR_geteuid32          201
-#define __NR_getegid32          202
-#define __NR_setreuid32         203
-#define __NR_setregid32         204
-#define __NR_getgroups32        205
-#define __NR_setgroups32        206
-#define __NR_fchown32           207
-#define __NR_setresuid32        208
-#define __NR_getresuid32        209
-#define __NR_setresgid32        210
-#define __NR_getresgid32        211
-#define __NR_lchown32           212
-#define __NR_setuid32           213
-#define __NR_setgid32           214
-#define __NR_setfsuid32         215
-#define __NR_setfsgid32         216
-#define __NR_pivot_root         217
-                                /* 218 __NR_mincore */
-                                /* 219 __NR_madvise */
-#define __NR_getdents64         220
-#define __NR_fcntl64            221
-                                /* 222 reserved for TUX */
-                                /* 223 reserved for TUX */
-#define __NR_gettid             224
-#define __NR_readahead          225
-#define __NR_setxattr           226
-#define __NR_lsetxattr          227
-#define __NR_fsetxattr          228
-#define __NR_getxattr           229
-#define __NR_lgetxattr          230
-#define __NR_fgetxattr          231
-#define __NR_listxattr          232
-#define __NR_llistxattr         233
-#define __NR_flistxattr         234
-#define __NR_removexattr        235
-#define __NR_lremovexattr       236
-#define __NR_fremovexattr       237
-#define __NR_tkill              238
-#define __NR_sendfile64         239
-#define __NR_futex              240
-#define __NR_sched_setaffinity  241
-#define __NR_sched_getaffinity  242
-                                /* 243 __NR_set_thread_area */
-                                /* 244 __NR_get_thread_area */
-#define __NR_io_setup           245
-#define __NR_io_destroy         246
-#define __NR_io_getevents       247
-#define __NR_io_submit          248
-#define __NR_io_cancel          249
-                                /* 250 __NR_alloc_hugepages */
-                                /* 251 __NR_free_hugepages */
-#define __NR_exit_group         252
-#define __NR_lookup_dcookie     253
-#define __NR_bfin_spinlock      254
-
-#define __NR_epoll_create       255
-#define __NR_epoll_ctl          256
-#define __NR_epoll_wait         257
-                                /* 258 __NR_remap_file_pages */
-#define __NR_set_tid_address    259
-#define __NR_timer_create       260
-#define __NR_timer_settime      261
-#define __NR_timer_gettime      262
-#define __NR_timer_getoverrun   263
-#define __NR_timer_delete       264
-#define __NR_clock_settime      265
-#define __NR_clock_gettime      266
-#define __NR_clock_getres       267
-#define __NR_clock_nanosleep    268
-#define __NR_statfs64           269
-#define __NR_fstatfs64          270
-#define __NR_tgkill             271
-#define __NR_utimes             272
-#define __NR_fadvise64_64       273
-                                /* 274 __NR_vserver */
-                                /* 275 __NR_mbind */
-                                /* 276 __NR_get_mempolicy */
-                                /* 277 __NR_set_mempolicy */
-#define __NR_mq_open            278
-#define __NR_mq_unlink          279
-#define __NR_mq_timedsend       280
-#define __NR_mq_timedreceive    281
-#define __NR_mq_notify          282
-#define __NR_mq_getsetattr      283
-#define __NR_kexec_load         284
-#define __NR_waitid             285
-#define __NR_add_key            286
-#define __NR_request_key        287
-#define __NR_keyctl             288
-#define __NR_ioprio_set         289
-#define __NR_ioprio_get         290
-#define __NR_inotify_init       291
-#define __NR_inotify_add_watch  292
-#define __NR_inotify_rm_watch   293
-                                /* 294 __NR_migrate_pages */
-#define __NR_openat             295
-#define __NR_mkdirat            296
-#define __NR_mknodat            297
-#define __NR_fchownat           298
-#define __NR_futimesat          299
-#define __NR_fstatat64          300
-#define __NR_unlinkat           301
-#define __NR_renameat           302
-#define __NR_linkat             303
-#define __NR_symlinkat          304
-#define __NR_readlinkat         305
-#define __NR_fchmodat           306
-#define __NR_faccessat          307
-#define __NR_pselect6           308
-#define __NR_ppoll              309
-#define __NR_unshare            310
-
-/* Blackfin private syscalls */
-#define __NR_sram_alloc         311
-#define __NR_sram_free          312
-#define __NR_dma_memcpy         313
-
-/* socket syscalls */
-#define __NR_accept             314
-#define __NR_bind               315
-#define __NR_connect            316
-#define __NR_getpeername        317
-#define __NR_getsockname        318
-#define __NR_getsockopt         319
-#define __NR_listen             320
-#define __NR_recv               321
-#define __NR_recvfrom           322
-#define __NR_recvmsg            323
-#define __NR_send               324
-#define __NR_sendmsg            325
-#define __NR_sendto             326
-#define __NR_setsockopt         327
-#define __NR_shutdown           328
-#define __NR_socket             329
-#define __NR_socketpair         330
-
-/* sysv ipc syscalls */
-#define __NR_semctl             331
-#define __NR_semget             332
-#define __NR_semop              333
-#define __NR_msgctl             334
-#define __NR_msgget             335
-#define __NR_msgrcv             336
-#define __NR_msgsnd             337
-#define __NR_shmat              338
-#define __NR_shmctl             339
-#define __NR_shmdt              340
-#define __NR_shmget             341
-
-#define __NR_splice             342
-#define __NR_sync_file_range    343
-#define __NR_tee                344
-#define __NR_vmsplice           345
-
-#define __NR_epoll_pwait        346
-#define __NR_utimensat          347
-#define __NR_signalfd           348
-#define __NR_timerfd_create     349
-#define __NR_eventfd            350
-#define __NR_pread64            351
-#define __NR_pwrite64           352
-#define __NR_fadvise64          353
-#define __NR_set_robust_list    354
-#define __NR_get_robust_list    355
-#define __NR_fallocate          356
-#define __NR_semtimedop         357
-#define __NR_timerfd_settime    358
-#define __NR_timerfd_gettime    359
-
-#define __NR_syscall            360
-#define NR_syscalls             __NR_syscall
-
-/* Old optional stuff no one actually uses */
-#define __IGNORE_sysfs
-#define __IGNORE_uselib
-
-/* Implement the newer interfaces */
-#define __IGNORE_mmap
-#define __IGNORE_poll
-#define __IGNORE_select
-#define __IGNORE_utime
-
-/* Not relevant on no-mmu */
-#define __IGNORE_swapon
-#define __IGNORE_swapoff
-#define __IGNORE_msync
-#define __IGNORE_mlock
-#define __IGNORE_munlock
-#define __IGNORE_mlockall
-#define __IGNORE_munlockall
-#define __IGNORE_mincore
-#define __IGNORE_madvise
-#define __IGNORE_remap_file_pages
-#define __IGNORE_mbind
-#define __IGNORE_get_mempolicy
-#define __IGNORE_set_mempolicy
-#define __IGNORE_migrate_pages
-#define __IGNORE_move_pages
-#define __IGNORE_getcpu
-
-#ifdef __KERNEL__
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
-
-#endif  /* __KERNEL__ */
-
-#endif                          /* __ASM_BFIN_UNISTD_H */
diff --git a/include/asm-blackfin/user.h b/include/asm-blackfin/user.h
deleted file mode 100644
index afe6a0e1f7ce..000000000000
--- a/include/asm-blackfin/user.h
+++ /dev/null
@@ -1,89 +0,0 @@
-#ifndef _BFIN_USER_H
-#define _BFIN_USER_H
-
-/* Changes by Tony Kou   Lineo, Inc.  July, 2001
- *
- * Based include/asm-m68knommu/user.h
- *
- */
-
-/* Core file format: The core file is written in such a way that gdb
-   can understand it and provide useful information to the user (under
-   linux we use the 'trad-core' bfd).  There are quite a number of
-   obstacles to being able to view the contents of the floating point
-   registers, and until these are solved you will not be able to view the
-   contents of them.  Actually, you can read in the core file and look at
-   the contents of the user struct to find out what the floating point
-   registers contain.
-   The actual file contents are as follows:
-   UPAGE: 1 page consisting of a user struct that tells gdb what is present
-   in the file.  Directly after this is a copy of the task_struct, which
-   is currently not used by gdb, but it may come in useful at some point.
-   All of the registers are stored as part of the upage.  The upage should
-   always be only one page.
-   DATA: The data area is stored.  We use current->end_text to
-   current->brk to pick up all of the user variables, plus any memory
-   that may have been malloced.  No attempt is made to determine if a page
-   is demand-zero or if a page is totally unused, we just cover the entire
-   range.  All of the addresses are rounded in such a way that an integral
-   number of pages is written.
-   STACK: We need the stack information in order to get a meaningful
-   backtrace.  We need to write the data from (esp) to
-   current->start_stack, so we round each of these off in order to be able
-   to write an integer number of pages.
-   The minimum core file size is 3 pages, or 12288 bytes.
-*/
-struct user_bfinfp_struct {
-};
-
-/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
-   is still the layout used by user (the new pt_regs doesn't have
-   all registers). */
-struct user_regs_struct {
-        long r0, r1, r2, r3, r4, r5, r6, r7;
-        long p0, p1, p2, p3, p4, p5, usp, fp;
-        long i0, i1, i2, i3;
-        long l0, l1, l2, l3;
-        long b0, b1, b2, b3;
-        long m0, m1, m2, m3;
-        long a0w, a1w;
-        long a0x, a1x;
-        unsigned long rets;
-        unsigned long astat;
-        unsigned long pc;
-        unsigned long orig_p0;
-};
-
-/* When the kernel dumps core, it starts by dumping the user struct -
-   this will be used by gdb to figure out where the data and stack segments
-   are within the file, and what virtual addresses to use. */
-
-struct user {
-/* We start with the registers, to mimic the way that "memory" is returned
-   from the ptrace(3,...) function.  */
-
-        struct user_regs_struct regs;   /* Where the registers are actually stored */
-
-/* The rest of this junk is to help gdb figure out what goes where */
-        unsigned long int u_tsize;      /* Text segment size (pages). */
-        unsigned long int u_dsize;      /* Data segment size (pages). */
-        unsigned long int u_ssize;      /* Stack segment size (pages). */
-        unsigned long start_code;       /* Starting virtual address of text. */
-        unsigned long start_stack;      /* Starting virtual address of stack area.
-                                           This is actually the bottom of the stack,
-                                           the top of the stack is always found in the
-                                           esp register.  */
-        long int signal;        /* Signal that caused the core dump. */
-        int reserved;           /* No longer used */
-        unsigned long u_ar0;
-        /* Used by gdb to help find the values for */
-        /* the registers. */
-        unsigned long magic;    /* To uniquely identify a core file */
-        char u_comm[32];        /* User command that was responsible */
-};
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif
diff --git a/include/asm-cris/Kbuild b/include/asm-cris/Kbuild
index b7037d80d461..d5b631935ec8 100644
--- a/include/asm-cris/Kbuild
+++ b/include/asm-cris/Kbuild
@@ -1,6 +1,5 @@
 include include/asm-generic/Kbuild.asm
 
-header-y += arch/
 header-y += arch-v10/
 header-y += arch-v32/
 
diff --git a/include/asm-frv/io.h b/include/asm-frv/io.h
index 20e44fe00abf..ca7475e73b5e 100644
--- a/include/asm-frv/io.h
+++ b/include/asm-frv/io.h
@@ -271,6 +271,8 @@ static inline void __iomem *ioremap_fullcache(unsigned long physaddr, unsigned l
         return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
 }
 
+#define ioremap_wc ioremap_nocache
+
 extern void iounmap(void volatile __iomem *addr);
 
 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
diff --git a/include/asm-generic/ioctl.h b/include/asm-generic/ioctl.h
index 864181385579..15828b2d663c 100644
--- a/include/asm-generic/ioctl.h
+++ b/include/asm-generic/ioctl.h
@@ -68,12 +68,16 @@
          ((nr)   << _IOC_NRSHIFT) | \
          ((size) << _IOC_SIZESHIFT))
 
+#ifdef __KERNEL__
 /* provoke compile error for invalid uses of size argument */
 extern unsigned int __invalid_size_argument_for_IOC;
 #define _IOC_TYPECHECK(t) \
         ((sizeof(t) == sizeof(t[1]) && \
           sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
           sizeof(t) : __invalid_size_argument_for_IOC)
+#else
+#define _IOC_TYPECHECK(t) (sizeof(t))
+#endif
 
 /* used to create numbers */
 #define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
diff --git a/include/asm-generic/rtc.h b/include/asm-generic/rtc.h
index be4af0029ac0..71ef3f0b9685 100644
--- a/include/asm-generic/rtc.h
+++ b/include/asm-generic/rtc.h
@@ -15,6 +15,7 @@
 #include <linux/mc146818rtc.h>
 #include <linux/rtc.h>
 #include <linux/bcd.h>
+#include <linux/delay.h>
 
 #define RTC_PIE 0x40            /* periodic interrupt enable */
 #define RTC_AIE 0x20            /* alarm interrupt enable */
@@ -43,7 +44,6 @@ static inline unsigned char rtc_is_updating(void)
 
 static inline unsigned int get_rtc_time(struct rtc_time *time)
 {
-        unsigned long uip_watchdog = jiffies;
         unsigned char ctrl;
         unsigned long flags;
 
@@ -53,19 +53,15 @@ static inline unsigned int get_rtc_time(struct rtc_time *time)
 
         /*
          * read RTC once any update in progress is done. The update
-         * can take just over 2ms. We wait 10 to 20ms. There is no need to
+         * can take just over 2ms. We wait 20ms. There is no need to
          * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP.
          * If you need to know *exactly* when a second has started, enable
          * periodic update complete interrupts, (via ioctl) and then 
          * immediately read /dev/rtc which will block until you get the IRQ.
          * Once the read clears, read the RTC time (again via ioctl). Easy.
          */
-
-        if (rtc_is_updating() != 0)
-                while (jiffies - uip_watchdog < 2*HZ/100) {
-                        barrier();
-                        cpu_relax();
-                }
+        if (rtc_is_updating())
+                mdelay(20);
 
         /*
          * Only the values that we read from the RTC are set. We leave
diff --git a/include/asm-h8300/Kbuild b/include/asm-h8300/Kbuild
deleted file mode 100644
index c68e1680da01..000000000000
--- a/include/asm-h8300/Kbuild
+++ /dev/null
@@ -1 +0,0 @@
-include include/asm-generic/Kbuild.asm
diff --git a/include/asm-h8300/a.out.h b/include/asm-h8300/a.out.h
deleted file mode 100644
index ded780f0a492..000000000000
--- a/include/asm-h8300/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __H8300_A_OUT_H__
-#define __H8300_A_OUT_H__
-
-struct exec
-{
-  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif /* __H8300_A_OUT_H__ */
diff --git a/include/asm-h8300/atomic.h b/include/asm-h8300/atomic.h
deleted file mode 100644
index b4cf0ea97ede..000000000000
--- a/include/asm-h8300/atomic.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __ARCH_H8300_ATOMIC__
-#define __ARCH_H8300_ATOMIC__
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- */
-
-typedef struct { int counter; } atomic_t;
-#define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v)          ((v)->counter)
-#define atomic_set(v, i)        (((v)->counter) = i)
-
-#include <asm/system.h>
-#include <linux/kernel.h>
-
-static __inline__ int atomic_add_return(int i, atomic_t *v)
-{
-        int ret,flags;
-        local_irq_save(flags);
-        ret = v->counter += i;
-        local_irq_restore(flags);
-        return ret;
-}
-
-#define atomic_add(i, v) atomic_add_return(i, v)
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-
-static __inline__ int atomic_sub_return(int i, atomic_t *v)
-{
-        int ret,flags;
-        local_irq_save(flags);
-        ret = v->counter -= i;
-        local_irq_restore(flags);
-        return ret;
-}
-
-#define atomic_sub(i, v) atomic_sub_return(i, v)
-#define atomic_sub_and_test(i,v) (atomic_sub_return(i, v) == 0)
-
-static __inline__ int atomic_inc_return(atomic_t *v)
-{
-        int ret,flags;
-        local_irq_save(flags);
-        v->counter++;
-        ret = v->counter;
-        local_irq_restore(flags);
-        return ret;
-}
-
-#define atomic_inc(v) atomic_inc_return(v)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-static __inline__ int atomic_dec_return(atomic_t *v)
-{
-        int ret,flags;
-        local_irq_save(flags);
-        --v->counter;
-        ret = v->counter;
-        local_irq_restore(flags);
-        return ret;
-}
-
-#define atomic_dec(v) atomic_dec_return(v)
-
-static __inline__ int atomic_dec_and_test(atomic_t *v)
-{
-        int ret,flags;
-        local_irq_save(flags);
-        --v->counter;
-        ret = v->counter;
-        local_irq_restore(flags);
-        return ret == 0;
-}
-
-static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
-{
-        int ret;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        ret = v->counter;
-        if (likely(ret == old))
-                v->counter = new;
-        local_irq_restore(flags);
-        return ret;
-}
-
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int ret;
-        unsigned long flags;
-
-        local_irq_save(flags);
-        ret = v->counter;
-        if (ret != u)
-                v->counter += a;
-        local_irq_restore(flags);
-        return ret != u;
-}
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-static __inline__ void atomic_clear_mask(unsigned long mask, unsigned long *v)
-{
-        __asm__ __volatile__("stc ccr,r1l\n\t"
-                             "orc #0x80,ccr\n\t"
-                             "mov.l %0,er0\n\t"
-                             "and.l %1,er0\n\t"
-                             "mov.l er0,%0\n\t"
-                             "ldc r1l,ccr" 
-                             : "=m" (*v) : "g" (~(mask)) :"er0","er1");
-}
-
-static __inline__ void atomic_set_mask(unsigned long mask, unsigned long *v)
-{
-        __asm__ __volatile__("stc ccr,r1l\n\t"
-                             "orc #0x80,ccr\n\t"
-                             "mov.l %0,er0\n\t"
-                             "or.l %1,er0\n\t"
-                             "mov.l er0,%0\n\t"
-                             "ldc r1l,ccr" 
-                             : "=m" (*v) : "g" (mask) :"er0","er1");
-}
-
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec()    barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc()    barrier()
-#define smp_mb__after_atomic_inc() barrier()
-
-#include <asm-generic/atomic.h>
-#endif /* __ARCH_H8300_ATOMIC __ */
diff --git a/include/asm-h8300/auxvec.h b/include/asm-h8300/auxvec.h
deleted file mode 100644
index 1d36fe38b088..000000000000
--- a/include/asm-h8300/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASMH8300_AUXVEC_H
-#define __ASMH8300_AUXVEC_H
-
-#endif
diff --git a/include/asm-h8300/bitops.h b/include/asm-h8300/bitops.h
deleted file mode 100644
index cb18e3b0aa94..000000000000
--- a/include/asm-h8300/bitops.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef _H8300_BITOPS_H
-#define _H8300_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- * Copyright 2002, Yoshinori Sato
- */
-
-#include <linux/compiler.h>
-#include <asm/system.h>
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-/*
- * Function prototypes to keep gcc -Wall happy
- */
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static __inline__ unsigned long ffz(unsigned long word)
-{
-        unsigned long result;
-
-        result = -1;
-        __asm__("1:\n\t"
-                "shlr.l %2\n\t"
-                "adds #1,%0\n\t"
-                "bcs 1b"
-                : "=r" (result)
-                : "0"  (result),"r" (word));
-        return result;
-}
-
-#define H8300_GEN_BITOP_CONST(OP,BIT)                       \
-        case BIT:                                           \
-        __asm__(OP " #" #BIT ",@%0"::"r"(b_addr):"memory"); \
-        break;
-
-#define H8300_GEN_BITOP(FNAME,OP)                                     \
-static __inline__ void FNAME(int nr, volatile unsigned long* addr)    \
-{                                                                     \
-        volatile unsigned char *b_addr;                               \
-        b_addr = (volatile unsigned char *)addr + ((nr >> 3) ^ 3);    \
-        if (__builtin_constant_p(nr)) {                               \
-                switch(nr & 7) {                                      \
-                        H8300_GEN_BITOP_CONST(OP,0)                   \
-                        H8300_GEN_BITOP_CONST(OP,1)                   \
-                        H8300_GEN_BITOP_CONST(OP,2)                   \
-                        H8300_GEN_BITOP_CONST(OP,3)                   \
-                        H8300_GEN_BITOP_CONST(OP,4)                   \
-                        H8300_GEN_BITOP_CONST(OP,5)                   \
-                        H8300_GEN_BITOP_CONST(OP,6)                   \
-                        H8300_GEN_BITOP_CONST(OP,7)                   \
-                }                                                     \
-        } else {                                                      \
-                __asm__(OP " %w0,@%1"::"r"(nr),"r"(b_addr):"memory"); \
-        }                                                             \
-}
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
-
-H8300_GEN_BITOP(set_bit   ,"bset")
-H8300_GEN_BITOP(clear_bit ,"bclr")
-H8300_GEN_BITOP(change_bit,"bnot")
-#define __set_bit(nr,addr)    set_bit((nr),(addr))
-#define __clear_bit(nr,addr)  clear_bit((nr),(addr))
-#define __change_bit(nr,addr) change_bit((nr),(addr))
-
-#undef H8300_GEN_BITOP
-#undef H8300_GEN_BITOP_CONST
-
-static __inline__ int test_bit(int nr, const unsigned long* addr)
-{
-        return (*((volatile unsigned char *)addr + 
-               ((nr >> 3) ^ 3)) & (1UL << (nr & 7))) != 0;
-}
-
-#define __test_bit(nr, addr) test_bit(nr, addr)
-
-#define H8300_GEN_TEST_BITOP_CONST_INT(OP,BIT)                       \
-        case BIT:                                                    \
-        __asm__("stc ccr,%w1\n\t"                                    \
-                "orc #0x80,ccr\n\t"                                  \
-                "bld #" #BIT ",@%4\n\t"                              \
-                OP " #" #BIT ",@%4\n\t"                              \
-                "rotxl.l %0\n\t"                                     \
-                "ldc %w1,ccr"                                        \
-                : "=r"(retval),"=&r"(ccrsave),"=m"(*b_addr)          \
-                : "0" (retval),"r" (b_addr)                          \
-                : "memory");                                         \
-        break;
-
-#define H8300_GEN_TEST_BITOP_CONST(OP,BIT)                           \
-        case BIT:                                                    \
-        __asm__("bld #" #BIT ",@%3\n\t"                              \
-                OP " #" #BIT ",@%3\n\t"                              \
-                "rotxl.l %0\n\t"                                     \
-                : "=r"(retval),"=m"(*b_addr)                         \
-                : "0" (retval),"r" (b_addr)                          \
-                : "memory");                                         \
-        break;
-
-#define H8300_GEN_TEST_BITOP(FNNAME,OP)                              \
-static __inline__ int FNNAME(int nr, volatile void * addr)           \
-{                                                                    \
-        int retval = 0;                                              \
-        char ccrsave;                                                \
-        volatile unsigned char *b_addr;                              \
-        b_addr = (volatile unsigned char *)addr + ((nr >> 3) ^ 3);   \
-        if (__builtin_constant_p(nr)) {                              \
-                switch(nr & 7) {                                     \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,0)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,1)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,2)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,3)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,4)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,5)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,6)         \
-                        H8300_GEN_TEST_BITOP_CONST_INT(OP,7)         \
-                }                                                    \
-        } else {                                                     \
-                __asm__("stc ccr,%w1\n\t"                            \
-                        "orc #0x80,ccr\n\t"                          \
-                        "btst %w5,@%4\n\t"                           \
-                        OP " %w5,@%4\n\t"                            \
-                        "beq 1f\n\t"                                 \
-                        "inc.l #1,%0\n"                              \
-                        "1:\n\t"                                     \
-                        "ldc %w1,ccr"                                \
-                        : "=r"(retval),"=&r"(ccrsave),"=m"(*b_addr)  \
-                        : "0" (retval),"r" (b_addr),"r"(nr)          \
-                        : "memory");                                 \
-        }                                                            \
-        return retval;                                               \
-}                                                                    \
-                                                                     \
-static __inline__ int __ ## FNNAME(int nr, volatile void * addr)     \
-{                                                                    \
-        int retval = 0;                                              \
-        volatile unsigned char *b_addr;                              \
-        b_addr = (volatile unsigned char *)addr + ((nr >> 3) ^ 3);   \
-        if (__builtin_constant_p(nr)) {                              \
-                switch(nr & 7) {                                     \
-                        H8300_GEN_TEST_BITOP_CONST(OP,0)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,1)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,2)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,3)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,4)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,5)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,6)             \
-                        H8300_GEN_TEST_BITOP_CONST(OP,7)             \
-                }                                                    \
-        } else {                                                     \
-                __asm__("btst %w4,@%3\n\t"                           \
-                        OP " %w4,@%3\n\t"                            \
-                        "beq 1f\n\t"                                 \
-                        "inc.l #1,%0\n"                              \
-                        "1:"                                         \
-                        : "=r"(retval),"=m"(*b_addr)                 \
-                        : "0" (retval),"r" (b_addr),"r"(nr)          \
-                        : "memory");                                 \
-        }                                                            \
-        return retval;                                               \
-}
-
-H8300_GEN_TEST_BITOP(test_and_set_bit,   "bset")
-H8300_GEN_TEST_BITOP(test_and_clear_bit, "bclr")
-H8300_GEN_TEST_BITOP(test_and_change_bit,"bnot")
-#undef H8300_GEN_TEST_BITOP_CONST
-#undef H8300_GEN_TEST_BITOP_CONST_INT
-#undef H8300_GEN_TEST_BITOP
-
-#include <asm-generic/bitops/ffs.h>
-
-static __inline__ unsigned long __ffs(unsigned long word)
-{
-        unsigned long result;
-
-        result = -1;
-        __asm__("1:\n\t"
-                "shlr.l %2\n\t"
-                "adds #1,%0\n\t"
-                "bcc 1b"
-                : "=r" (result)
-                : "0"(result),"r"(word));
-        return result;
-}
-
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif /* _H8300_BITOPS_H */
diff --git a/include/asm-h8300/bootinfo.h b/include/asm-h8300/bootinfo.h
deleted file mode 100644
index 5bed7e7aac0a..000000000000
--- a/include/asm-h8300/bootinfo.h
+++ /dev/null
@@ -1,2 +0,0 @@
-
-/* Nothing for h8300 */
diff --git a/include/asm-h8300/bug.h b/include/asm-h8300/bug.h
deleted file mode 100644
index edddf5b086e5..000000000000
--- a/include/asm-h8300/bug.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _H8300_BUG_H
-#define _H8300_BUG_H
-#include <asm-generic/bug.h>
-#endif
diff --git a/include/asm-h8300/bugs.h b/include/asm-h8300/bugs.h
deleted file mode 100644
index 1cb4afba6eb1..000000000000
--- a/include/asm-h8300/bugs.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  include/asm-h8300/bugs.h
- *
- *  Copyright (C) 1994  Linus Torvalds
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *      void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
diff --git a/include/asm-h8300/byteorder.h b/include/asm-h8300/byteorder.h
deleted file mode 100644
index 36e597d61619..000000000000
--- a/include/asm-h8300/byteorder.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _H8300_BYTEORDER_H
-#define _H8300_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/big_endian.h>
-
-#endif /* _H8300_BYTEORDER_H */
diff --git a/include/asm-h8300/cache.h b/include/asm-h8300/cache.h
deleted file mode 100644
index c6350283649d..000000000000
--- a/include/asm-h8300/cache.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __ARCH_H8300_CACHE_H
-#define __ARCH_H8300_CACHE_H
-
-/* bytes per L1 cache line */
-#define        L1_CACHE_BYTES  4
-
-/* m68k-elf-gcc  2.95.2 doesn't like these */
-
-#define __cacheline_aligned
-#define ____cacheline_aligned
-
-#endif
diff --git a/include/asm-h8300/cachectl.h b/include/asm-h8300/cachectl.h
deleted file mode 100644
index c464022d8e26..000000000000
--- a/include/asm-h8300/cachectl.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _H8300_CACHECTL_H
-#define _H8300_CACHECTL_H
-
-/* Definitions for the cacheflush system call.  */
-
-#define FLUSH_SCOPE_LINE    0   /* Flush a cache line */
-#define FLUSH_SCOPE_PAGE    0   /* Flush a page */
-#define FLUSH_SCOPE_ALL     0   /* Flush the whole cache -- superuser only */
-
-#define FLUSH_CACHE_DATA    0   /* Writeback and flush data cache */
-#define FLUSH_CACHE_INSN    0   /* Flush instruction cache */
-#define FLUSH_CACHE_BOTH    0   /* Flush both caches */
-
-#endif /* _H8300_CACHECTL_H */
diff --git a/include/asm-h8300/cacheflush.h b/include/asm-h8300/cacheflush.h
deleted file mode 100644
index 5ffdca217b95..000000000000
--- a/include/asm-h8300/cacheflush.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * (C) Copyright 2002, Yoshinori Sato <ysato@users.sourceforge.jp>
- */
-
-#ifndef _ASM_H8300_CACHEFLUSH_H
-#define _ASM_H8300_CACHEFLUSH_H
-
-/*
- * Cache handling functions
- * No Cache memory all dummy functions
- */
-
-#define flush_cache_all()
-#define flush_cache_mm(mm)
-#define flush_cache_dup_mm(mm)          do { } while (0)
-#define flush_cache_range(vma,a,b)
-#define flush_cache_page(vma,p,pfn)
-#define flush_dcache_page(page)
-#define flush_dcache_mmap_lock(mapping)
-#define flush_dcache_mmap_unlock(mapping)
-#define flush_icache()
-#define flush_icache_page(vma,page)
-#define flush_icache_range(start,len)
-#define flush_cache_vmap(start, end)
-#define flush_cache_vunmap(start, end)
-#define cache_push_v(vaddr,len)
-#define cache_push(paddr,len)
-#define cache_clear(paddr,len)
-
-#define flush_dcache_range(a,b)
-
-#define flush_icache_user_range(vma,page,addr,len)
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-        memcpy(dst, src, len)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
-        memcpy(dst, src, len)
-
-#endif /* _ASM_H8300_CACHEFLUSH_H */
diff --git a/include/asm-h8300/checksum.h b/include/asm-h8300/checksum.h
deleted file mode 100644
index 98724e12508c..000000000000
--- a/include/asm-h8300/checksum.h
+++ /dev/null
@@ -1,102 +0,0 @@
-#ifndef _H8300_CHECKSUM_H
-#define _H8300_CHECKSUM_H
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len, __wsum sum);
-
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-                                                int len, __wsum sum, int *csum_err);
-
-__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
-
-
-/*
- *      Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-        __asm__("mov.l %0,er0\n\t"
-                "add.w e0,r0\n\t"
-                "xor.w e0,e0\n\t"
-                "rotxl.w e0\n\t"
-                "add.w e0,r0\n\t"
-                "sub.w e0,e0\n\t"
-                "mov.l er0,%0"
-                : "=r"(sum)
-                : "0"(sum)
-                : "er0");
-        return (__force __sum16)~sum;
-}
-
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        __asm__ ("sub.l er0,er0\n\t"
-                 "add.l %2,%0\n\t"
-                 "addx  #0,r0l\n\t"
-                 "add.l %3,%0\n\t"
-                 "addx  #0,r0l\n\t"
-                 "add.l %4,%0\n\t"
-                 "addx  #0,r0l\n\t"
-                 "add.l er0,%0\n\t"
-                 "bcc   1f\n\t"
-                 "inc.l #1,%0\n"
-                 "1:"
-                 : "=&r" (sum)
-                 : "0" (sum), "r" (daddr), "r" (saddr), "r" (len + proto)
-                 :"er0");
-        return sum;
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#endif /* _H8300_CHECKSUM_H */
diff --git a/include/asm-h8300/cputime.h b/include/asm-h8300/cputime.h
deleted file mode 100644
index 092e187c7b08..000000000000
--- a/include/asm-h8300/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __H8300_CPUTIME_H
-#define __H8300_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __H8300_CPUTIME_H */
diff --git a/include/asm-h8300/current.h b/include/asm-h8300/current.h
deleted file mode 100644
index 57d74ee55a14..000000000000
--- a/include/asm-h8300/current.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _H8300_CURRENT_H
-#define _H8300_CURRENT_H
-/*
- *      current.h
- *      (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
- *      (C) Copyright 2002, Greg Ungerer (gerg@snapgear.com)
- *
- *      rather than dedicate a register (as the m68k source does), we
- *      just keep a global,  we should probably just change it all to be
- *      current and lose _current_task.
- */
-
-#include <linux/thread_info.h>
-#include <asm/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct *get_current(void)
-{
-        return(current_thread_info()->task);
-}
-
-#define current get_current()
-
-#endif /* _H8300_CURRENT_H */
diff --git a/include/asm-h8300/dbg.h b/include/asm-h8300/dbg.h
deleted file mode 100644
index 2c6d1cbcf736..000000000000
--- a/include/asm-h8300/dbg.h
+++ /dev/null
@@ -1,2 +0,0 @@
-#define DEBUG 1
-#define BREAK asm volatile ("trap #3")
diff --git a/include/asm-h8300/delay.h b/include/asm-h8300/delay.h
deleted file mode 100644
index 743beba70f82..000000000000
--- a/include/asm-h8300/delay.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef _H8300_DELAY_H
-#define _H8300_DELAY_H
-
-#include <asm/param.h>
-
-/*
- * Copyright (C) 2002 Yoshinori Sato <ysato@sourceforge.jp>
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-static inline void __delay(unsigned long loops)
-{
-        __asm__ __volatile__ ("1:\n\t"
-                              "dec.l #1,%0\n\t"
-                              "bne 1b"
-                              :"=r" (loops):"0"(loops));
-}
-
-/*
- * Use only for very small delays ( < 1 msec).  Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays.  This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)  
- */
-
-extern unsigned long loops_per_jiffy;
-
-static inline void udelay(unsigned long usecs)
-{
-        usecs *= 4295;          /* 2**32 / 1000000 */
-        usecs /= (loops_per_jiffy*HZ);
-        if (usecs)
-                __delay(usecs);
-}
-
-#endif /* _H8300_DELAY_H */
diff --git a/include/asm-h8300/device.h b/include/asm-h8300/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-h8300/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-h8300/div64.h b/include/asm-h8300/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-h8300/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-h8300/dma.h b/include/asm-h8300/dma.h
deleted file mode 100644
index 3edbaaaedf5b..000000000000
--- a/include/asm-h8300/dma.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef _H8300_DMA_H
-#define _H8300_DMA_H 
- 
-
-/*
- * Set number of channels of DMA on ColdFire for different implementations.
- */
-#define MAX_DMA_CHANNELS 0
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char *device_id);      /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
- 
-#endif /* _H8300_DMA_H */
diff --git a/include/asm-h8300/elf.h b/include/asm-h8300/elf.h
deleted file mode 100644
index a8b57d1f4128..000000000000
--- a/include/asm-h8300/elf.h
+++ /dev/null
@@ -1,104 +0,0 @@
-#ifndef __ASMH8300_ELF_H
-#define __ASMH8300_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-typedef unsigned long elf_fpregset_t;
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_H8_300)
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2MSB
-#define ELF_ARCH        EM_H8_300
-#if defined(__H8300H__)
-#define ELF_CORE_EFLAGS 0x810000
-#endif
-#if defined(__H8300S__)
-#define ELF_CORE_EFLAGS 0x820000
-#endif
-
-#define ELF_PLAT_INIT(_r)       _r->er1 = 0
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       4096
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         0xD0000000UL
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  */
-
-#define ELF_HWCAP       (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM  (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
-
-#define R_H8_NONE       0
-#define R_H8_DIR32      1
-#define R_H8_DIR32_28   2
-#define R_H8_DIR32_24   3
-#define R_H8_DIR32_16   4
-#define R_H8_DIR32U     6
-#define R_H8_DIR32U_28  7
-#define R_H8_DIR32U_24  8
-#define R_H8_DIR32U_20  9
-#define R_H8_DIR32U_16 10
-#define R_H8_DIR24     11
-#define R_H8_DIR24_20  12
-#define R_H8_DIR24_16  13
-#define R_H8_DIR24U    14
-#define R_H8_DIR24U_20 15
-#define R_H8_DIR24U_16 16
-#define R_H8_DIR16     17
-#define R_H8_DIR16U    18
-#define R_H8_DIR16S_32 19
-#define R_H8_DIR16S_28 20
-#define R_H8_DIR16S_24 21
-#define R_H8_DIR16S_20 22
-#define R_H8_DIR16S    23
-#define R_H8_DIR8      24
-#define R_H8_DIR8U     25
-#define R_H8_DIR8Z_32  26
-#define R_H8_DIR8Z_28  27
-#define R_H8_DIR8Z_24  28
-#define R_H8_DIR8Z_20  29
-#define R_H8_DIR8Z_16  30
-#define R_H8_PCREL16   31
-#define R_H8_PCREL8    32
-#define R_H8_BPOS      33
-#define R_H8_PCREL32   34
-#define R_H8_GOT32O    35
-#define R_H8_GOT16O    36
-#define R_H8_DIR16A8   59
-#define R_H8_DIR16R8   60
-#define R_H8_DIR24A8   61
-#define R_H8_DIR24R8   62
-#define R_H8_DIR32A16  63
-#define R_H8_ABS32     65
-#define R_H8_ABS32A16 127
-
-#endif
diff --git a/include/asm-h8300/emergency-restart.h b/include/asm-h8300/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-h8300/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-h8300/errno.h b/include/asm-h8300/errno.h
deleted file mode 100644
index 0c2f5641fdcc..000000000000
--- a/include/asm-h8300/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_ERRNO_H
-#define _H8300_ERRNO_H
-
-#include <asm-generic/errno.h>
-
-#endif /* _H8300_ERRNO_H */
diff --git a/include/asm-h8300/fb.h b/include/asm-h8300/fb.h
deleted file mode 100644
index c7df38030992..000000000000
--- a/include/asm-h8300/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-        return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-h8300/fcntl.h b/include/asm-h8300/fcntl.h
deleted file mode 100644
index 1952cb2e3b06..000000000000
--- a/include/asm-h8300/fcntl.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _H8300_FCNTL_H
-#define _H8300_FCNTL_H
-
-#define O_DIRECTORY     040000  /* must be a directory */
-#define O_NOFOLLOW      0100000 /* don't follow links */
-#define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE     0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _H8300_FCNTL_H */
diff --git a/include/asm-h8300/flat.h b/include/asm-h8300/flat.h
deleted file mode 100644
index 2a873508a9a1..000000000000
--- a/include/asm-h8300/flat.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * include/asm-h8300/flat.h -- uClinux flat-format executables
- */
-
-#ifndef __H8300_FLAT_H__
-#define __H8300_FLAT_H__
-
-#define flat_stack_align(sp)                    /* nothing needed */
-#define flat_argvp_envp_on_stack()              1
-#define flat_old_ram_flag(flags)                1
-#define flat_reloc_valid(reloc, size)           ((reloc) <= (size))
-#define flat_set_persistent(relval, p)          0
-
-/*
- * on the H8 a couple of the relocations have an instruction in the
- * top byte.  As there can only be 24bits of address space,  we just
- * always preserve that 8bits at the top,  when it isn't an instruction
- * is is 0 (davidm@snapgear.com)
- */
-
-#define flat_get_relocate_addr(rel)             (rel)
-#define flat_get_addr_from_rp(rp, relval, flags, persistent) \
-        (get_unaligned(rp) & ((flags & FLAT_FLAG_GOTPIC) ? 0xffffffff: 0x00ffffff))
-#define flat_put_addr_at_rp(rp, addr, rel) \
-        put_unaligned (((*(char *)(rp)) << 24) | ((addr) & 0x00ffffff), rp)
-
-#endif /* __H8300_FLAT_H__ */
diff --git a/include/asm-h8300/fpu.h b/include/asm-h8300/fpu.h
deleted file mode 100644
index 4fc416e80bef..000000000000
--- a/include/asm-h8300/fpu.h
+++ /dev/null
@@ -1 +0,0 @@
-/* Nothing do */
diff --git a/include/asm-h8300/futex.h b/include/asm-h8300/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/include/asm-h8300/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/include/asm-h8300/gpio.h b/include/asm-h8300/gpio.h
deleted file mode 100644
index a714f0c0efbc..000000000000
--- a/include/asm-h8300/gpio.h
+++ /dev/null
@@ -1,52 +0,0 @@
-#ifndef _H8300_GPIO_H
-#define _H8300_GPIO_H
-
-#define H8300_GPIO_P1 0
-#define H8300_GPIO_P2 1
-#define H8300_GPIO_P3 2
-#define H8300_GPIO_P4 3
-#define H8300_GPIO_P5 4
-#define H8300_GPIO_P6 5
-#define H8300_GPIO_P7 6
-#define H8300_GPIO_P8 7
-#define H8300_GPIO_P9 8
-#define H8300_GPIO_PA 9
-#define H8300_GPIO_PB 10
-#define H8300_GPIO_PC 11
-#define H8300_GPIO_PD 12
-#define H8300_GPIO_PE 13
-#define H8300_GPIO_PF 14
-#define H8300_GPIO_PG 15
-#define H8300_GPIO_PH 16
-
-#define H8300_GPIO_B7 0x80
-#define H8300_GPIO_B6 0x40
-#define H8300_GPIO_B5 0x20
-#define H8300_GPIO_B4 0x10
-#define H8300_GPIO_B3 0x08
-#define H8300_GPIO_B2 0x04
-#define H8300_GPIO_B1 0x02
-#define H8300_GPIO_B0 0x01
-
-#define H8300_GPIO_INPUT 0
-#define H8300_GPIO_OUTPUT 1
-
-#define H8300_GPIO_RESERVE(port, bits) \
-        h8300_reserved_gpio(port, bits)
-
-#define H8300_GPIO_FREE(port, bits) \
-        h8300_free_gpio(port, bits)
-
-#define H8300_GPIO_DDR(port, bit, dir) \
-        h8300_set_gpio_dir(((port) << 8) | (bit), dir)
-
-#define H8300_GPIO_GETDIR(port, bit) \
-        h8300_get_gpio_dir(((port) << 8) | (bit))
-
-extern int h8300_reserved_gpio(int port, int bits);
-extern int h8300_free_gpio(int port, int bits);
-extern int h8300_set_gpio_dir(int port_bit, int dir);
-extern int h8300_get_gpio_dir(int port_bit);
-extern int h8300_init_gpio(void);
-
-#endif
diff --git a/include/asm-h8300/hardirq.h b/include/asm-h8300/hardirq.h
deleted file mode 100644
index 9d7f7a7462b2..000000000000
--- a/include/asm-h8300/hardirq.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __H8300_HARDIRQ_H
-#define __H8300_HARDIRQ_H
-
-#include <linux/kernel.h>
-#include <linux/threads.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-extern void ack_bad_irq(unsigned int irq);
-
-#define HARDIRQ_BITS    8
-
-/*
- * The hardirq mask has to be large enough to have
- * space for potentially all IRQ sources in the system
- * nesting on a single CPU:
- */
-#if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-#endif
-
-#endif
diff --git a/include/asm-h8300/hw_irq.h b/include/asm-h8300/hw_irq.h
deleted file mode 100644
index d75a5a1119e8..000000000000
--- a/include/asm-h8300/hw_irq.h
+++ /dev/null
@@ -1 +0,0 @@
-/* Do Nothing */
diff --git a/include/asm-h8300/io.h b/include/asm-h8300/io.h
deleted file mode 100644
index 26dc6ccd9441..000000000000
--- a/include/asm-h8300/io.h
+++ /dev/null
@@ -1,324 +0,0 @@
-#ifndef _H8300_IO_H
-#define _H8300_IO_H
-
-#ifdef __KERNEL__
-
-#include <asm/virtconvert.h>
-
-#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
-#include <asm/regs306x.h>
-#elif defined(CONFIG_H8S2678)
-#include <asm/regs267x.h>
-#else
-#error UNKNOWN CPU TYPE
-#endif
-
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the m68k architecture, we just read/write the
- * memory location directly.
- */
-/* ++roman: The assignments to temp. vars avoid that gcc sometimes generates
- * two accesses to memory, which may be undesireable for some devices.
- */
-
-/*
- * swap functions are sometimes needed to interface little-endian hardware
- */
-
-static inline unsigned short _swapw(volatile unsigned short v)
-{
-#ifndef H8300_IO_NOSWAP
-        unsigned short r;
-        __asm__("xor.b %w0,%x0\n\t"
-                "xor.b %x0,%w0\n\t"
-                "xor.b %w0,%x0"
-                :"=r"(r)
-                :"0"(v));
-        return r;
-#else
-        return v;
-#endif
-}
-
-static inline unsigned long _swapl(volatile unsigned long v)
-{
-#ifndef H8300_IO_NOSWAP
-        unsigned long r;
-        __asm__("xor.b %w0,%x0\n\t"
-                "xor.b %x0,%w0\n\t"
-                "xor.b %w0,%x0\n\t"
-                "xor.w %e0,%f0\n\t"
-                "xor.w %f0,%e0\n\t"
-                "xor.w %e0,%f0\n\t"
-                "xor.b %w0,%x0\n\t"
-                "xor.b %x0,%w0\n\t"
-                "xor.b %w0,%x0"
-                :"=r"(r)
-                :"0"(v));
-        return r;
-#else
-        return v;
-#endif
-}
-
-#define readb(addr) \
-    ({ unsigned char __v = \
-     *(volatile unsigned char *)((unsigned long)(addr) & 0x00ffffff); \
-     __v; })
-#define readw(addr) \
-    ({ unsigned short __v = \
-     *(volatile unsigned short *)((unsigned long)(addr) & 0x00ffffff); \
-     __v; })
-#define readl(addr) \
-    ({ unsigned long __v = \
-     *(volatile unsigned long *)((unsigned long)(addr) & 0x00ffffff); \
-     __v; })
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) \
-                             ((unsigned long)(addr) & 0x00ffffff)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) \
-                             ((unsigned long)(addr) & 0x00ffffff)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned long *) \
-                             ((unsigned long)(addr) & 0x00ffffff)) = (b))
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-
-static inline int h8300_buswidth(unsigned int addr)
-{
-        return (*(volatile unsigned char *)ABWCR & (1 << ((addr >> 21) & 7))) == 0;
-}
-
-static inline void io_outsb(unsigned int addr, const void *buf, int len)
-{
-        volatile unsigned char  *ap_b = (volatile unsigned char *) addr;
-        volatile unsigned short *ap_w = (volatile unsigned short *) addr;
-        unsigned char *bp = (unsigned char *) buf;
-
-        if(h8300_buswidth(addr) && (addr & 1)) {
-                while (len--)
-                        *ap_w = *bp++;
-        } else {
-                while (len--)
-                        *ap_b = *bp++;
-        }
-}
-
-static inline void io_outsw(unsigned int addr, const void *buf, int len)
-{
-        volatile unsigned short *ap = (volatile unsigned short *) addr;
-        unsigned short *bp = (unsigned short *) buf;
-        while (len--)
-                *ap = _swapw(*bp++);
-}
-
-static inline void io_outsl(unsigned int addr, const void *buf, int len)
-{
-        volatile unsigned long *ap = (volatile unsigned long *) addr;
-        unsigned long *bp = (unsigned long *) buf;
-        while (len--)
-                *ap = _swapl(*bp++);
-}
-
-static inline void io_outsw_noswap(unsigned int addr, const void *buf, int len)
-{
-        volatile unsigned short *ap = (volatile unsigned short *) addr;
-        unsigned short *bp = (unsigned short *) buf;
-        while (len--)
-                *ap = *bp++;
-}
-
-static inline void io_outsl_noswap(unsigned int addr, const void *buf, int len)
-{
-        volatile unsigned long *ap = (volatile unsigned long *) addr;
-        unsigned long *bp = (unsigned long *) buf;
-        while (len--)
-                *ap = *bp++;
-}
-
-static inline void io_insb(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned char  *ap_b;
-        volatile unsigned short *ap_w;
-        unsigned char *bp = (unsigned char *) buf;
-
-        if(h8300_buswidth(addr)) {
-                ap_w = (volatile unsigned short *)(addr & ~1);
-                while (len--)
-                        *bp++ = *ap_w & 0xff;
-        } else {
-                ap_b = (volatile unsigned char *)addr;
-                while (len--)
-                        *bp++ = *ap_b;
-        }
-}
-
-static inline void io_insw(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned short *ap = (volatile unsigned short *) addr;
-        unsigned short *bp = (unsigned short *) buf;
-        while (len--)
-                *bp++ = _swapw(*ap);
-}
-
-static inline void io_insl(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned long *ap = (volatile unsigned long *) addr;
-        unsigned long *bp = (unsigned long *) buf;
-        while (len--)
-                *bp++ = _swapl(*ap);
-}
-
-static inline void io_insw_noswap(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned short *ap = (volatile unsigned short *) addr;
-        unsigned short *bp = (unsigned short *) buf;
-        while (len--)
-                *bp++ = *ap;
-}
-
-static inline void io_insl_noswap(unsigned int addr, void *buf, int len)
-{
-        volatile unsigned long *ap = (volatile unsigned long *) addr;
-        unsigned long *bp = (unsigned long *) buf;
-        while (len--)
-                *bp++ = *ap;
-}
-
-/*
- *      make the short names macros so specific devices
- *      can override them as required
- */
-
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
-
-#define mmiowb()
-
-#define inb(addr)    ((h8300_buswidth(addr))?readw((addr) & ~1) & 0xff:readb(addr))
-#define inw(addr)    _swapw(readw(addr))
-#define inl(addr)    _swapl(readl(addr))
-#define outb(x,addr) ((void)((h8300_buswidth(addr) && \
-                      ((addr) & 1))?writew(x,(addr) & ~1):writeb(x,addr)))
-#define outw(x,addr) ((void) writew(_swapw(x),addr))
-#define outl(x,addr) ((void) writel(_swapl(x),addr))
-
-#define inb_p(addr)    inb(addr)
-#define inw_p(addr)    inw(addr)
-#define inl_p(addr)    inl(addr)
-#define outb_p(x,addr) outb(x,addr)
-#define outw_p(x,addr) outw(x,addr)
-#define outl_p(x,addr) outl(x,addr)
-
-#define outsb(a,b,l) io_outsb(a,b,l)
-#define outsw(a,b,l) io_outsw(a,b,l)
-#define outsl(a,b,l) io_outsl(a,b,l)
-
-#define insb(a,b,l) io_insb(a,b,l)
-#define insw(a,b,l) io_insw(a,b,l)
-#define insl(a,b,l) io_insl(a,b,l)
-
-#define IO_SPACE_LIMIT 0xffffff
-
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_FULL_CACHING              0
-#define IOMAP_NOCACHE_SER               1
-#define IOMAP_NOCACHE_NONSER            2
-#define IOMAP_WRITETHROUGH              3
-
-extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
-extern void __iounmap(void *addr, unsigned long size);
-
-static inline void *ioremap(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void *ioremap_nocache(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void *ioremap_writethrough(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
-}
-static inline void *ioremap_fullcache(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
-}
-
-extern void iounmap(void *addr);
-
-/* H8/300 internal I/O functions */
-static __inline__ unsigned char ctrl_inb(unsigned long addr)
-{
-        return *(volatile unsigned char*)addr;
-}
-
-static __inline__ unsigned short ctrl_inw(unsigned long addr)
-{
-        return *(volatile unsigned short*)addr;
-}
-
-static __inline__ unsigned long ctrl_inl(unsigned long addr)
-{
-        return *(volatile unsigned long*)addr;
-}
-
-static __inline__ void ctrl_outb(unsigned char b, unsigned long addr)
-{
-        *(volatile unsigned char*)addr = b;
-}
-
-static __inline__ void ctrl_outw(unsigned short b, unsigned long addr)
-{
-        *(volatile unsigned short*)addr = b;
-}
-
-static __inline__ void ctrl_outl(unsigned long b, unsigned long addr)
-{
-        *(volatile unsigned long*)addr = b;
-}
-
-/* Pages to physical address... */
-#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-/*
- * Macros used for converting between virtual and physical mappings.
- */
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif /* __KERNEL__ */
-
-#endif /* _H8300_IO_H */
diff --git a/include/asm-h8300/ioctl.h b/include/asm-h8300/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/include/asm-h8300/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/include/asm-h8300/ioctls.h b/include/asm-h8300/ioctls.h
deleted file mode 100644
index 98a53d067269..000000000000
--- a/include/asm-h8300/ioctls.h
+++ /dev/null
@@ -1,85 +0,0 @@
-#ifndef __ARCH_H8300_IOCTLS_H__
-#define __ARCH_H8300_IOCTLS_H__
-
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS          0x5401
-#define TCSETS          0x5402
-#define TCSETSW         0x5403
-#define TCSETSF         0x5404
-#define TCGETA          0x5405
-#define TCSETA          0x5406
-#define TCSETAW         0x5407
-#define TCSETAF         0x5408
-#define TCSBRK          0x5409
-#define TCXONC          0x540A
-#define TCFLSH          0x540B
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-#define TIOCGPGRP       0x540F
-#define TIOCSPGRP       0x5410
-#define TIOCOUTQ        0x5411
-#define TIOCSTI         0x5412
-#define TIOCGWINSZ      0x5413
-#define TIOCSWINSZ      0x5414
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define FIONREAD        0x541B
-#define TIOCINQ         FIONREAD
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-#define FIONBIO         0x5421
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCTTYGSTRUCT  0x5426  /* For debugging only */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TCGETS2         _IOR('T',0x2A, struct termios2)
-#define TCSETS2         _IOW('T',0x2B, struct termios2)
-#define TCSETSW2        _IOW('T',0x2C, struct termios2)
-#define TCSETSF2        _IOW('T',0x2D, struct termios2)
-#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
-
-#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
-#define FIOCLEX         0x5451
-#define FIOASYNC        0x5452
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
-#define TIOCSERGETLSR   0x5459 /* Get line status register */
-#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-#define FIOQSIZE        0x545E
-
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
-
-#endif /* __ARCH_H8300_IOCTLS_H__ */
diff --git a/include/asm-h8300/ipcbuf.h b/include/asm-h8300/ipcbuf.h
deleted file mode 100644
index 2cd1ebcc109d..000000000000
--- a/include/asm-h8300/ipcbuf.h
+++ /dev/null
@@ -1,29 +0,0 @@
-#ifndef __H8300_IPCBUF_H__
-#define __H8300_IPCBUF_H__
-
-/*
- * The user_ipc_perm structure for H8/300 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-
-struct ipc64_perm
-{
-        __kernel_key_t          key;
-        __kernel_uid32_t        uid;
-        __kernel_gid32_t        gid;
-        __kernel_uid32_t        cuid;
-        __kernel_gid32_t        cgid;
-        __kernel_mode_t         mode;
-        unsigned short          __pad1;
-        unsigned short          seq;
-        unsigned short          __pad2;
-        unsigned long           __unused1;
-        unsigned long           __unused2;
-};
-
-#endif /* __H8300_IPCBUF_H__ */
diff --git a/include/asm-h8300/irq.h b/include/asm-h8300/irq.h
deleted file mode 100644
index 13d7c601cd0a..000000000000
--- a/include/asm-h8300/irq.h
+++ /dev/null
@@ -1,49 +0,0 @@
-#ifndef _H8300_IRQ_H_
-#define _H8300_IRQ_H_
-
-#include <asm/ptrace.h>
-
-#if defined(CONFIG_CPU_H8300H)
-#define NR_IRQS 64
-#define EXT_IRQ0 12
-#define EXT_IRQ1 13
-#define EXT_IRQ2 14
-#define EXT_IRQ3 15
-#define EXT_IRQ4 16
-#define EXT_IRQ5 17
-#define EXT_IRQ6 18
-#define EXT_IRQ7 19
-#define EXT_IRQS 5
-#define IER_REGS *(volatile unsigned char *)IER
-#endif
-#if defined(CONFIG_CPU_H8S)
-#define NR_IRQS 128
-#define EXT_IRQ0 16
-#define EXT_IRQ1 17
-#define EXT_IRQ2 18
-#define EXT_IRQ3 19
-#define EXT_IRQ4 20
-#define EXT_IRQ5 21
-#define EXT_IRQ6 22
-#define EXT_IRQ7 23
-#define EXT_IRQ8 24
-#define EXT_IRQ9 25
-#define EXT_IRQ10 26
-#define EXT_IRQ11 27
-#define EXT_IRQ12 28
-#define EXT_IRQ13 29
-#define EXT_IRQ14 30
-#define EXT_IRQ15 31
-#define EXT_IRQS 15
-
-#define IER_REGS *(volatile unsigned short *)IER
-#endif
-
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
-typedef void (*h8300_vector)(void);
-
-#endif /* _H8300_IRQ_H_ */
diff --git a/include/asm-h8300/irq_regs.h b/include/asm-h8300/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-h8300/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-h8300/kdebug.h b/include/asm-h8300/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-h8300/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-h8300/kmap_types.h b/include/asm-h8300/kmap_types.h
deleted file mode 100644
index 1ec8a3427120..000000000000
--- a/include/asm-h8300/kmap_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_H8300_KMAP_TYPES_H
-#define _ASM_H8300_KMAP_TYPES_H
-
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
-
-#endif
diff --git a/include/asm-h8300/linkage.h b/include/asm-h8300/linkage.h
deleted file mode 100644
index 6f4df7d46180..000000000000
--- a/include/asm-h8300/linkage.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _H8300_LINKAGE_H
-#define _H8300_LINKAGE_H
-
-#undef SYMBOL_NAME_LABEL
-#undef SYMBOL_NAME
-#define SYMBOL_NAME_LABEL(_name_) _##_name_##:
-#define SYMBOL_NAME(_name_) _##_name_
-#endif
diff --git a/include/asm-h8300/local.h b/include/asm-h8300/local.h
deleted file mode 100644
index fdd4efe437cd..000000000000
--- a/include/asm-h8300/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_LOCAL_H_
-#define _H8300_LOCAL_H_
-
-#include <asm-generic/local.h>
-
-#endif
diff --git a/include/asm-h8300/mc146818rtc.h b/include/asm-h8300/mc146818rtc.h
deleted file mode 100644
index ab9d9646d241..000000000000
--- a/include/asm-h8300/mc146818rtc.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Machine dependent access functions for RTC registers.
- */
-#ifndef _H8300_MC146818RTC_H
-#define _H8300_MC146818RTC_H
-
-/* empty include file to satisfy the include in genrtc.c/ide-geometry.c */
-
-#endif /* _H8300_MC146818RTC_H */
diff --git a/include/asm-h8300/md.h b/include/asm-h8300/md.h
deleted file mode 100644
index 1a47dc6691fb..000000000000
--- a/include/asm-h8300/md.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* $Id: md.h,v 1.1 2002/11/19 02:09:26 gerg Exp $
- * md.h: High speed xor_block operation for RAID4/5 
- *
- */
- 
-#ifndef __ASM_MD_H
-#define __ASM_MD_H
-
-/* #define HAVE_ARCH_XORBLOCK */
-
-#define MD_XORBLOCK_ALIGNMENT   sizeof(long)
-
-#endif /* __ASM_MD_H */
diff --git a/include/asm-h8300/mman.h b/include/asm-h8300/mman.h
deleted file mode 100644
index b9f104f22a36..000000000000
--- a/include/asm-h8300/mman.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef __H8300_MMAN_H__
-#define __H8300_MMAN_H__
-
-#include <asm-generic/mman.h>
-
-#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
-#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
-#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
-#define MAP_LOCKED      0x2000          /* pages are locked */
-#define MAP_NORESERVE   0x4000          /* don't check for reservations */
-#define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x10000         /* do not block on IO */
-
-#define MCL_CURRENT     1               /* lock all current mappings */
-#define MCL_FUTURE      2               /* lock all future mappings */
-
-#endif /* __H8300_MMAN_H__ */
diff --git a/include/asm-h8300/mmu.h b/include/asm-h8300/mmu.h
deleted file mode 100644
index 2ce06ea46104..000000000000
--- a/include/asm-h8300/mmu.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __MMU_H
-#define __MMU_H
-
-/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
-
-typedef struct {
-        struct vm_list_struct   *vmlist;
-        unsigned long           end_brk;
-} mm_context_t;
-
-#endif
diff --git a/include/asm-h8300/mmu_context.h b/include/asm-h8300/mmu_context.h
deleted file mode 100644
index f44b730da54d..000000000000
--- a/include/asm-h8300/mmu_context.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __H8300_MMU_CONTEXT_H
-#define __H8300_MMU_CONTEXT_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm-generic/mm_hooks.h>
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-        // mm->context = virt_to_phys(mm->pgd);
-        return(0);
-}
-
-#define destroy_context(mm)             do { } while(0)
-#define deactivate_mm(tsk,mm)           do { } while(0)
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, struct task_struct *tsk)
-{
-}
-
-static inline void activate_mm(struct mm_struct *prev_mm,
-                               struct mm_struct *next_mm)
-{
-}
-
-#endif
diff --git a/include/asm-h8300/module.h b/include/asm-h8300/module.h
deleted file mode 100644
index de23231f3196..000000000000
--- a/include/asm-h8300/module.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_H8300_MODULE_H
-#define _ASM_H8300_MODULE_H
-/*
- * This file contains the H8/300 architecture specific module code.
- */
-struct mod_arch_specific { };
-#define Elf_Shdr Elf32_Shdr
-#define Elf_Sym Elf32_Sym
-#define Elf_Ehdr Elf32_Ehdr
-
-#define MODULE_SYMBOL_PREFIX "_"
-
-#endif /* _ASM_H8/300_MODULE_H */
diff --git a/include/asm-h8300/msgbuf.h b/include/asm-h8300/msgbuf.h
deleted file mode 100644
index 6b148cd09aa5..000000000000
--- a/include/asm-h8300/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _H8300_MSGBUF_H
-#define _H8300_MSGBUF_H
-
-/* 
- * The msqid64_ds structure for H8/300 architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        unsigned long   __unused1;
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        unsigned long   __unused2;
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long   __unused3;
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-
-#endif /* _H8300_MSGBUF_H */
diff --git a/include/asm-h8300/mutex.h b/include/asm-h8300/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-h8300/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-h8300/page.h b/include/asm-h8300/page.h
deleted file mode 100644
index 0b6acf0b03aa..000000000000
--- a/include/asm-h8300/page.h
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef _H8300_PAGE_H
-#define _H8300_PAGE_H
-
-/* PAGE_SHIFT determines the page size */
-
-#define PAGE_SHIFT      (12)
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#define PAGE_MASK       (~(PAGE_SIZE-1))
-
-#include <asm/setup.h>
-
-#ifndef __ASSEMBLY__
- 
-#define get_user_page(vaddr)            __get_free_page(GFP_KERNEL)
-#define free_user_page(page, addr)      free_page(addr)
-
-#define clear_page(page)        memset((page), 0, PAGE_SIZE)
-#define copy_page(to,from)      memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr, pg)        clear_page(page)
-#define copy_user_page(to, from, vaddr, pg)     copy_page(to, from)
-
-#define __alloc_zeroed_user_highpage(movableflags, vma, vaddr) \
-        alloc_page_vma(GFP_HIGHUSER | __GFP_ZERO | movableflags, vma, vaddr)
-#define __HAVE_ARCH_ALLOC_ZEROED_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct { unsigned long pte; } pte_t;
-typedef struct { unsigned long pmd[16]; } pmd_t;
-typedef struct { unsigned long pgd; } pgd_t;
-typedef struct { unsigned long pgprot; } pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((&x)->pmd[0])
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-#endif /* !__ASSEMBLY__ */
-
-#include <asm/page_offset.h>
-
-#define PAGE_OFFSET             (PAGE_OFFSET_RAW)
-
-#ifndef __ASSEMBLY__
-
-#define __pa(vaddr)             virt_to_phys(vaddr)
-#define __va(paddr)             phys_to_virt((unsigned long)paddr)
-
-#define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
-
-#define MAP_NR(addr)            (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
-#define virt_to_page(addr)      (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
-#define page_to_virt(page)      ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-#define pfn_valid(page)         (page < max_mapnr)
-
-#define ARCH_PFN_OFFSET         (PAGE_OFFSET >> PAGE_SHIFT)
-
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                ((void *)(kaddr) < (void *)memory_end))
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif /* _H8300_PAGE_H */
diff --git a/include/asm-h8300/page_offset.h b/include/asm-h8300/page_offset.h
deleted file mode 100644
index f8706463008c..000000000000
--- a/include/asm-h8300/page_offset.h
+++ /dev/null
@@ -1,3 +0,0 @@
-
-#define PAGE_OFFSET_RAW         0x00000000
-
diff --git a/include/asm-h8300/param.h b/include/asm-h8300/param.h
deleted file mode 100644
index 1c72fb8080ff..000000000000
--- a/include/asm-h8300/param.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _H8300_PARAM_H
-#define _H8300_PARAM_H
-
-#ifdef __KERNEL__
-#define HZ              CONFIG_HZ
-#define USER_HZ         HZ
-#define CLOCKS_PER_SEC  (USER_HZ)
-#else
-#define HZ              100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#endif /* _H8300_PARAM_H */
diff --git a/include/asm-h8300/pci.h b/include/asm-h8300/pci.h
deleted file mode 100644
index 97389b35aa35..000000000000
--- a/include/asm-h8300/pci.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _ASM_H8300_PCI_H
-#define _ASM_H8300_PCI_H
-
-/*
- * asm-h8300/pci.h - H8/300 specific PCI declarations.
- *
- * Yoshinori Sato <ysato@users.sourceforge.jp>
- */
-
-#define pcibios_assign_all_busses()     0
-#define pcibios_scan_all_fns(a, b)      0
-
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
-        /* No special bus mastering setup handling */
-}
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-        /* We don't do dynamic PCI IRQ allocation */
-}
-
-#define PCI_DMA_BUS_IS_PHYS     (1)
-
-#endif /* _ASM_H8300_PCI_H */
diff --git a/include/asm-h8300/percpu.h b/include/asm-h8300/percpu.h
deleted file mode 100644
index 72c03e3666d8..000000000000
--- a/include/asm-h8300/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARCH_H8300_PERCPU__
-#define __ARCH_H8300_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ARCH_H8300_PERCPU__ */
diff --git a/include/asm-h8300/pgalloc.h b/include/asm-h8300/pgalloc.h
deleted file mode 100644
index c2e89a286d23..000000000000
--- a/include/asm-h8300/pgalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _H8300_PGALLOC_H
-#define _H8300_PGALLOC_H
-
-#include <asm/setup.h>
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif /* _H8300_PGALLOC_H */
diff --git a/include/asm-h8300/pgtable.h b/include/asm-h8300/pgtable.h
deleted file mode 100644
index a09230a08e02..000000000000
--- a/include/asm-h8300/pgtable.h
+++ /dev/null
@@ -1,73 +0,0 @@
-#ifndef _H8300_PGTABLE_H
-#define _H8300_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <linux/slab.h>
-#include <asm/processor.h>
-#include <asm/page.h>
-#include <asm/io.h>
-
-#define pgd_present(pgd)     (1)       /* pages are always present on NO_MM */
-#define pgd_none(pgd)           (0)
-#define pgd_bad(pgd)            (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr)   (1)
-#define pmd_offset(a, b)        ((void *)0)
-#define pmd_none(pmd)           (1)
-#define pgd_offset_k(adrdress)  ((pgd_t *)0)
-#define pte_offset_kernel(dir, address) ((pte_t *)0)
-
-#define PAGE_NONE               __pgprot(0)    /* these mean nothing to NO_MM */
-#define PAGE_SHARED             __pgprot(0)    /* these mean nothing to NO_MM */
-#define PAGE_COPY               __pgprot(0)    /* these mean nothing to NO_MM */
-#define PAGE_READONLY   __pgprot(0)    /* these mean nothing to NO_MM */
-#define PAGE_KERNEL             __pgprot(0)    /* these mean nothing to NO_MM */
-
-extern void paging_init(void);
-#define swapper_pg_dir ((pgd_t *) 0)
-
-#define __swp_type(x)           (0)
-#define __swp_offset(x)         (0)
-#define __swp_entry(typ,off)    ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-
-static inline int pte_file(pte_t pte) { return 0; }
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr)        (virt_to_page(0))
-
-/*
- * These would be in other places but having them here reduces the diffs.
- */
-extern unsigned int kobjsize(const void *objp);
-extern int is_in_rom(unsigned long);
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()   do { } while (0)
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
-
-#define arch_enter_lazy_cpu_mode()    do {} while (0)
-#endif /* _H8300_PGTABLE_H */
diff --git a/include/asm-h8300/poll.h b/include/asm-h8300/poll.h
deleted file mode 100644
index f61540c22d94..000000000000
--- a/include/asm-h8300/poll.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __H8300_POLL_H
-#define __H8300_POLL_H
-
-#define POLLWRNORM      POLLOUT
-#define POLLWRBAND      256
-
-#include <asm-generic/poll.h>
-
-#undef POLLREMOVE
-
-#endif
diff --git a/include/asm-h8300/posix_types.h b/include/asm-h8300/posix_types.h
deleted file mode 100644
index 5c553927fc53..000000000000
--- a/include/asm-h8300/posix_types.h
+++ /dev/null
@@ -1,60 +0,0 @@
-#ifndef __ARCH_H8300_POSIX_TYPES_H
-#define __ARCH_H8300_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long   __kernel_ino_t;
-typedef unsigned short  __kernel_mode_t;
-typedef unsigned short  __kernel_nlink_t;
-typedef long            __kernel_off_t;
-typedef int             __kernel_pid_t;
-typedef unsigned short  __kernel_ipc_pid_t;
-typedef unsigned short  __kernel_uid_t;
-typedef unsigned short  __kernel_gid_t;
-typedef unsigned int    __kernel_size_t;
-typedef int             __kernel_ssize_t;
-typedef int             __kernel_ptrdiff_t;
-typedef long            __kernel_time_t;
-typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
-typedef int             __kernel_timer_t;
-typedef int             __kernel_clockid_t;
-typedef int             __kernel_daddr_t;
-typedef char *          __kernel_caddr_t;
-typedef unsigned short  __kernel_uid16_t;
-typedef unsigned short  __kernel_gid16_t;
-typedef unsigned int    __kernel_uid32_t;
-typedef unsigned int    __kernel_gid32_t;
-
-typedef unsigned short  __kernel_old_uid_t;
-typedef unsigned short  __kernel_old_gid_t;
-
-#ifdef __GNUC__
-typedef long long       __kernel_loff_t;
-#endif
-
-typedef struct {
-        int     val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef  __FD_SET
-#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-
-#undef  __FD_CLR
-#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-
-#undef  __FD_ISSET
-#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-
-#undef  __FD_ZERO
-#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-
-#endif /* defined(__KERNEL__) */
-
-#endif
diff --git a/include/asm-h8300/processor.h b/include/asm-h8300/processor.h
deleted file mode 100644
index 69e8a34eb6d5..000000000000
--- a/include/asm-h8300/processor.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * include/asm-h8300/processor.h
- *
- * Copyright (C) 2002 Yoshinori Sato
- *
- * Based on: linux/asm-m68nommu/processor.h
- *
- * Copyright (C) 1995 Hamish Macdonald
- */
-
-#ifndef __ASM_H8300_PROCESSOR_H
-#define __ASM_H8300_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <linux/compiler.h>
-#include <asm/segment.h>
-#include <asm/fpu.h>
-#include <asm/ptrace.h>
-#include <asm/current.h>
-
-static inline unsigned long rdusp(void) {
-        extern unsigned int     sw_usp;
-        return(sw_usp);
-}
-
-static inline void wrusp(unsigned long usp) {
-        extern unsigned int     sw_usp;
-        sw_usp = usp;
-}
-
-/*
- * User space process size: 3.75GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-#define TASK_SIZE       (0xFFFFFFFFUL)
-
-#ifdef __KERNEL__
-#define STACK_TOP       TASK_SIZE
-#define STACK_TOP_MAX   STACK_TOP
-#endif
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's. We won't be using it
- */
-#define TASK_UNMAPPED_BASE      0
-
-struct thread_struct {
-        unsigned long  ksp;             /* kernel stack pointer */
-        unsigned long  usp;             /* user stack pointer */
-        unsigned long  ccr;             /* saved status register */
-        unsigned long  esp0;            /* points to SR of stack frame */
-        struct {
-                unsigned short *addr;
-                unsigned short inst;
-        } breakinfo;
-};
-
-#define INIT_THREAD  {                                          \
-        .ksp  = sizeof(init_stack) + (unsigned long)init_stack, \
-        .usp  = 0,                                              \
-        .ccr  = PS_S,                                           \
-        .esp0 = 0,                                              \
-        .breakinfo = {                                          \
-                .addr = (unsigned short *)-1,                   \
-                .inst = 0                                       \
-        }                                                       \
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-#if defined(__H8300H__)
-#define start_thread(_regs, _pc, _usp)                          \
-do {                                                            \
-        set_fs(USER_DS);           /* reads from user space */  \
-        (_regs)->pc = (_pc);                                    \
-        (_regs)->ccr = 0x00;       /* clear all flags */        \
-        (_regs)->er5 = current->mm->start_data; /* GOT base */  \
-        wrusp((unsigned long)(_usp) - sizeof(unsigned long)*3); \
-} while(0)
-#endif
-#if defined(__H8300S__)
-#define start_thread(_regs, _pc, _usp)                          \
-do {                                                            \
-        set_fs(USER_DS);           /* reads from user space */  \
-        (_regs)->pc = (_pc);                                    \
-        (_regs)->ccr = 0x00;       /* clear kernel flag */      \
-        (_regs)->exr = 0x78;       /* enable all interrupts */  \
-        (_regs)->er5 = current->mm->start_data; /* GOT base */  \
-        /* 14 = space for retaddr(4), vector(4), er0(4) and ext(2) on stack */ \
-        wrusp(((unsigned long)(_usp)) - 14);                    \
-} while(0)
-#endif
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-#define prepare_to_copy(tsk)    do { } while (0)
-
-/*
- * Free current thread data structures etc..
- */
-static inline void exit_thread(void)
-{
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-unsigned long thread_saved_pc(struct task_struct *tsk);
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)   \
-    ({                  \
-        unsigned long eip = 0;   \
-        if ((tsk)->thread.esp0 > PAGE_SIZE && \
-            MAP_NR((tsk)->thread.esp0) < max_mapnr) \
-              eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc; \
-        eip; })
-#define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax()    barrier()
-
-#endif
diff --git a/include/asm-h8300/ptrace.h b/include/asm-h8300/ptrace.h
deleted file mode 100644
index c2e05e4b512e..000000000000
--- a/include/asm-h8300/ptrace.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _H8300_PTRACE_H
-#define _H8300_PTRACE_H
-
-#ifndef __ASSEMBLY__
-
-#define PT_ER1     0
-#define PT_ER2     1
-#define PT_ER3     2
-#define PT_ER4     3
-#define PT_ER5     4
-#define PT_ER6     5
-#define PT_ER0     6
-#define PT_ORIG_ER0        7
-#define PT_CCR     8
-#define PT_PC      9
-#define PT_USP     10
-#define PT_EXR     12
-
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-struct pt_regs {
-        long     retpc;
-        long     er4;
-        long     er5;
-        long     er6;
-        long     er3;
-        long     er2;
-        long     er1;
-        long     orig_er0;
-        unsigned short ccr;
-        long     er0;
-        long     vector;
-#if defined(CONFIG_CPU_H8S)
-        unsigned short exr;
-#endif
-        unsigned long  pc;
-} __attribute__((aligned(2),packed));
-
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13
-
-#ifdef __KERNEL__
-#ifndef PS_S
-#define PS_S  (0x10)
-#endif
-
-#if defined(__H8300H__)
-#define H8300_REGS_NO 11
-#endif
-#if defined(__H8300S__)
-#define H8300_REGS_NO 12
-#endif
-
-/* Find the stack offset for a register, relative to thread.esp0. */
-#define PT_REG(reg)     ((long)&((struct pt_regs *)0)->reg)
-
-#define user_mode(regs) (!((regs)->ccr & PS_S))
-#define instruction_pointer(regs) ((regs)->pc)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-#endif /* __KERNEL__ */
-#endif /* __ASSEMBLY__ */
-#endif /* _H8300_PTRACE_H */
diff --git a/include/asm-h8300/regs267x.h b/include/asm-h8300/regs267x.h
deleted file mode 100644
index 1bff731a9f77..000000000000
--- a/include/asm-h8300/regs267x.h
+++ /dev/null
@@ -1,336 +0,0 @@
-/* internal Peripherals Register address define */
-/* CPU: H8/306x                                 */
-
-#if !defined(__REGS_H8S267x__)
-#define __REGS_H8S267x__ 
-
-#if defined(__KERNEL__)
-
-#define DASTCR 0xFEE01A
-#define DADR0  0xFFFFA4
-#define DADR1  0xFFFFA5
-#define DACR01 0xFFFFA6
-#define DADR2  0xFFFFA8
-#define DADR3  0xFFFFA9
-#define DACR23 0xFFFFAA
-
-#define ADDRA  0xFFFF90
-#define ADDRAH 0xFFFF90
-#define ADDRAL 0xFFFF91
-#define ADDRB  0xFFFF92
-#define ADDRBH 0xFFFF92
-#define ADDRBL 0xFFFF93
-#define ADDRC  0xFFFF94
-#define ADDRCH 0xFFFF94
-#define ADDRCL 0xFFFF95
-#define ADDRD  0xFFFF96
-#define ADDRDH 0xFFFF96
-#define ADDRDL 0xFFFF97
-#define ADDRE  0xFFFF98
-#define ADDREH 0xFFFF98
-#define ADDREL 0xFFFF99
-#define ADDRF  0xFFFF9A
-#define ADDRFH 0xFFFF9A
-#define ADDRFL 0xFFFF9B
-#define ADDRG  0xFFFF9C
-#define ADDRGH 0xFFFF9C
-#define ADDRGL 0xFFFF9D
-#define ADDRH  0xFFFF9E
-#define ADDRHH 0xFFFF9E
-#define ADDRHL 0xFFFF9F
-
-#define ADCSR  0xFFFFA0
-#define ADCR   0xFFFFA1
-
-#define ABWCR  0xFFFEC0
-#define ASTCR  0xFFFEC1
-#define WTCRAH 0xFFFEC2
-#define WTCRAL 0xFFFEC3
-#define WTCRBH 0xFFFEC4
-#define WTCRBL 0xFFFEC5
-#define RDNCR  0xFFFEC6
-#define CSACRH 0xFFFEC8
-#define CSACRL 0xFFFEC9
-#define BROMCRH 0xFFFECA
-#define BROMCRL 0xFFFECB
-#define BCR    0xFFFECC
-#define DRAMCR 0xFFFED0
-#define DRACCR 0xFFFED2
-#define REFCR  0xFFFED4
-#define RTCNT  0xFFFED6
-#define RTCOR  0xFFFED7
-
-#define MAR0AH  0xFFFEE0
-#define MAR0AL  0xFFFEE2
-#define IOAR0A  0xFFFEE4
-#define ETCR0A  0xFFFEE6
-#define MAR0BH  0xFFFEE8
-#define MAR0BL  0xFFFEEA
-#define IOAR0B  0xFFFEEC
-#define ETCR0B  0xFFFEEE
-#define MAR1AH  0xFFFEF0
-#define MAR1AL  0xFFFEF2
-#define IOAR1A  0xFFFEF4
-#define ETCR1A  0xFFFEF6
-#define MAR1BH  0xFFFEF8
-#define MAR1BL  0xFFFEFA
-#define IOAR1B  0xFFFEFC
-#define ETCR1B  0xFFFEFE
-#define DMAWER  0xFFFF20
-#define DMATCR  0xFFFF21
-#define DMACR0A 0xFFFF22
-#define DMACR0B 0xFFFF23
-#define DMACR1A 0xFFFF24
-#define DMACR1B 0xFFFF25
-#define DMABCRH 0xFFFF26
-#define DMABCRL 0xFFFF27
-
-#define EDSAR0  0xFFFDC0
-#define EDDAR0  0xFFFDC4
-#define EDTCR0  0xFFFDC8
-#define EDMDR0  0xFFFDCC
-#define EDMDR0H 0xFFFDCC
-#define EDMDR0L 0xFFFDCD
-#define EDACR0  0xFFFDCE
-#define EDSAR1  0xFFFDD0
-#define EDDAR1  0xFFFDD4
-#define EDTCR1  0xFFFDD8
-#define EDMDR1  0xFFFDDC
-#define EDMDR1H 0xFFFDDC
-#define EDMDR1L 0xFFFDDD
-#define EDACR1  0xFFFDDE
-#define EDSAR2  0xFFFDE0
-#define EDDAR2  0xFFFDE4
-#define EDTCR2  0xFFFDE8
-#define EDMDR2  0xFFFDEC
-#define EDMDR2H 0xFFFDEC
-#define EDMDR2L 0xFFFDED
-#define EDACR2  0xFFFDEE
-#define EDSAR3  0xFFFDF0
-#define EDDAR3  0xFFFDF4
-#define EDTCR3  0xFFFDF8
-#define EDMDR3  0xFFFDFC
-#define EDMDR3H 0xFFFDFC
-#define EDMDR3L 0xFFFDFD
-#define EDACR3  0xFFFDFE
-
-#define IPRA  0xFFFE00
-#define IPRB  0xFFFE02
-#define IPRC  0xFFFE04
-#define IPRD  0xFFFE06
-#define IPRE  0xFFFE08
-#define IPRF  0xFFFE0A
-#define IPRG  0xFFFE0C
-#define IPRH  0xFFFE0E
-#define IPRI  0xFFFE10
-#define IPRJ  0xFFFE12
-#define IPRK  0xFFFE14
-#define ITSR  0xFFFE16
-#define SSIER 0xFFFE18
-#define ISCRH 0xFFFE1A
-#define ISCRL 0xFFFE1C
-
-#define INTCR 0xFFFF31
-#define IER   0xFFFF32
-#define IERH  0xFFFF32
-#define IERL  0xFFFF33
-#define ISR   0xFFFF34
-#define ISRH  0xFFFF34
-#define ISRL  0xFFFF35
-
-#define P1DDR 0xFFFE20
-#define P2DDR 0xFFFE21
-#define P3DDR 0xFFFE22
-#define P4DDR 0xFFFE23
-#define P5DDR 0xFFFE24
-#define P6DDR 0xFFFE25
-#define P7DDR 0xFFFE26
-#define P8DDR 0xFFFE27
-#define P9DDR 0xFFFE28
-#define PADDR 0xFFFE29
-#define PBDDR 0xFFFE2A
-#define PCDDR 0xFFFE2B
-#define PDDDR 0xFFFE2C
-#define PEDDR 0xFFFE2D
-#define PFDDR 0xFFFE2E
-#define PGDDR 0xFFFE2F
-#define PHDDR 0xFFFF74
-
-#define PFCR0 0xFFFE32
-#define PFCR1 0xFFFE33
-#define PFCR2 0xFFFE34
-
-#define PAPCR 0xFFFE36
-#define PBPCR 0xFFFE37
-#define PCPCR 0xFFFE38
-#define PDPCR 0xFFFE39
-#define PEPCR 0xFFFE3A
-
-#define P3ODR 0xFFFE3C
-#define PAODR 0xFFFE3D
-
-#define P1DR  0xFFFF60
-#define P2DR  0xFFFF61
-#define P3DR  0xFFFF62
-#define P4DR  0xFFFF63
-#define P5DR  0xFFFF64
-#define P6DR  0xFFFF65
-#define P7DR  0xFFFF66
-#define P8DR  0xFFFF67
-#define P9DR  0xFFFF68
-#define PADR  0xFFFF69
-#define PBDR  0xFFFF6A
-#define PCDR  0xFFFF6B
-#define PDDR  0xFFFF6C
-#define PEDR  0xFFFF6D
-#define PFDR  0xFFFF6E
-#define PGDR  0xFFFF6F
-#define PHDR  0xFFFF72
-
-#define PORT1 0xFFFF50
-#define PORT2 0xFFFF51
-#define PORT3 0xFFFF52
-#define PORT4 0xFFFF53
-#define PORT5 0xFFFF54
-#define PORT6 0xFFFF55
-#define PORT7 0xFFFF56
-#define PORT8 0xFFFF57
-#define PORT9 0xFFFF58
-#define PORTA 0xFFFF59
-#define PORTB 0xFFFF5A
-#define PORTC 0xFFFF5B
-#define PORTD 0xFFFF5C
-#define PORTE 0xFFFF5D
-#define PORTF 0xFFFF5E
-#define PORTG 0xFFFF5F
-#define PORTH 0xFFFF70
-
-#define PCR   0xFFFF46
-#define PMR   0xFFFF47
-#define NDERH 0xFFFF48
-#define NDERL 0xFFFF49
-#define PODRH 0xFFFF4A
-#define PODRL 0xFFFF4B
-#define NDRH1 0xFFFF4C
-#define NDRL1 0xFFFF4D
-#define NDRH2 0xFFFF4E
-#define NDRL2 0xFFFF4F
-
-#define SMR0  0xFFFF78
-#define BRR0  0xFFFF79
-#define SCR0  0xFFFF7A
-#define TDR0  0xFFFF7B
-#define SSR0  0xFFFF7C
-#define RDR0  0xFFFF7D
-#define SCMR0 0xFFFF7E
-#define SMR1  0xFFFF80
-#define BRR1  0xFFFF81
-#define SCR1  0xFFFF82
-#define TDR1  0xFFFF83
-#define SSR1  0xFFFF84
-#define RDR1  0xFFFF85
-#define SCMR1 0xFFFF86
-#define SMR2  0xFFFF88
-#define BRR2  0xFFFF89
-#define SCR2  0xFFFF8A
-#define TDR2  0xFFFF8B
-#define SSR2  0xFFFF8C
-#define RDR2  0xFFFF8D
-#define SCMR2 0xFFFF8E
-
-#define IRCR0 0xFFFE1E
-#define SEMR  0xFFFDA8
-
-#define MDCR    0xFFFF3E
-#define SYSCR   0xFFFF3D
-#define MSTPCRH 0xFFFF40
-#define MSTPCRL 0xFFFF41
-#define FLMCR1  0xFFFFC8
-#define FLMCR2  0xFFFFC9
-#define EBR1    0xFFFFCA
-#define EBR2    0xFFFFCB
-#define CTGARC_RAMCR   0xFFFECE
-#define SBYCR   0xFFFF3A
-#define SCKCR   0xFFFF3B
-#define PLLCR   0xFFFF45
-
-#define TSTR   0xFFFFC0
-#define TSNC   0XFFFFC1
-
-#define TCR0   0xFFFFD0
-#define TMDR0  0xFFFFD1
-#define TIORH0 0xFFFFD2
-#define TIORL0 0xFFFFD3
-#define TIER0  0xFFFFD4
-#define TSR0   0xFFFFD5
-#define TCNT0  0xFFFFD6
-#define GRA0   0xFFFFD8
-#define GRB0   0xFFFFDA
-#define GRC0   0xFFFFDC
-#define GRD0   0xFFFFDE
-#define TCR1   0xFFFFE0
-#define TMDR1  0xFFFFE1
-#define TIORH1 0xFFFFE2
-#define TIORL1 0xFFFFE3
-#define TIER1  0xFFFFE4
-#define TSR1   0xFFFFE5
-#define TCNT1  0xFFFFE6
-#define GRA1   0xFFFFE8
-#define GRB1   0xFFFFEA
-#define TCR2   0xFFFFF0
-#define TMDR2  0xFFFFF1
-#define TIORH2 0xFFFFF2
-#define TIORL2 0xFFFFF3
-#define TIER2  0xFFFFF4
-#define TSR2   0xFFFFF5
-#define TCNT2  0xFFFFF6
-#define GRA2   0xFFFFF8
-#define GRB2   0xFFFFFA
-#define TCR3   0xFFFE80
-#define TMDR3  0xFFFE81
-#define TIORH3 0xFFFE82
-#define TIORL3 0xFFFE83
-#define TIER3  0xFFFE84
-#define TSR3   0xFFFE85
-#define TCNT3  0xFFFE86
-#define GRA3   0xFFFE88
-#define GRB3   0xFFFE8A
-#define GRC3   0xFFFE8C
-#define GRD3   0xFFFE8E
-#define TCR4   0xFFFE90
-#define TMDR4  0xFFFE91
-#define TIORH4 0xFFFE92
-#define TIORL4 0xFFFE93
-#define TIER4  0xFFFE94
-#define TSR4   0xFFFE95
-#define TCNT4  0xFFFE96
-#define GRA4   0xFFFE98
-#define GRB4   0xFFFE9A
-#define TCR5   0xFFFEA0
-#define TMDR5  0xFFFEA1
-#define TIORH5 0xFFFEA2
-#define TIORL5 0xFFFEA3
-#define TIER5  0xFFFEA4
-#define TSR5   0xFFFEA5
-#define TCNT5  0xFFFEA6
-#define GRA5   0xFFFEA8
-#define GRB5   0xFFFEAA
-
-#define _8TCR0   0xFFFFB0
-#define _8TCR1   0xFFFFB1
-#define _8TCSR0  0xFFFFB2
-#define _8TCSR1  0xFFFFB3
-#define _8TCORA0 0xFFFFB4
-#define _8TCORA1 0xFFFFB5
-#define _8TCORB0 0xFFFFB6
-#define _8TCORB1 0xFFFFB7
-#define _8TCNT0  0xFFFFB8
-#define _8TCNT1  0xFFFFB9
-
-#define TCSR    0xFFFFBC
-#define TCNT    0xFFFFBD
-#define RSTCSRW 0xFFFFBE
-#define RSTCSRR 0xFFFFBF
-
-#endif /* __KERNEL__ */
-#endif /* __REGS_H8S267x__ */
diff --git a/include/asm-h8300/regs306x.h b/include/asm-h8300/regs306x.h
deleted file mode 100644
index 027dd633fa25..000000000000
--- a/include/asm-h8300/regs306x.h
+++ /dev/null
@@ -1,212 +0,0 @@
-/* internal Peripherals Register address define */
-/* CPU: H8/306x                                 */
-
-#if !defined(__REGS_H8306x__)
-#define __REGS_H8306x__ 
-
-#if defined(__KERNEL__)
-
-#define DASTCR 0xFEE01A
-#define DADR0  0xFEE09C
-#define DADR1  0xFEE09D
-#define DACR   0xFEE09E
-
-#define ADDRAH 0xFFFFE0
-#define ADDRAL 0xFFFFE1
-#define ADDRBH 0xFFFFE2
-#define ADDRBL 0xFFFFE3
-#define ADDRCH 0xFFFFE4
-#define ADDRCL 0xFFFFE5
-#define ADDRDH 0xFFFFE6
-#define ADDRDL 0xFFFFE7
-#define ADCSR  0xFFFFE8
-#define ADCR   0xFFFFE9
-
-#define BRCR   0xFEE013
-#define ADRCR  0xFEE01E
-#define CSCR   0xFEE01F
-#define ABWCR  0xFEE020
-#define ASTCR  0xFEE021
-#define WCRH   0xFEE022
-#define WCRL   0xFEE023
-#define BCR    0xFEE024
-#define DRCRA  0xFEE026
-#define DRCRB  0xFEE027
-#define RTMCSR 0xFEE028
-#define RTCNT  0xFEE029
-#define RTCOR  0xFEE02A
-
-#define MAR0AR  0xFFFF20
-#define MAR0AE  0xFFFF21
-#define MAR0AH  0xFFFF22
-#define MAR0AL  0xFFFF23
-#define ETCR0AL 0xFFFF24
-#define ETCR0AH 0xFFFF25
-#define IOAR0A  0xFFFF26
-#define DTCR0A  0xFFFF27
-#define MAR0BR  0xFFFF28
-#define MAR0BE  0xFFFF29
-#define MAR0BH  0xFFFF2A
-#define MAR0BL  0xFFFF2B
-#define ETCR0BL 0xFFFF2C
-#define ETCR0BH 0xFFFF2D
-#define IOAR0B  0xFFFF2E
-#define DTCR0B  0xFFFF2F
-#define MAR1AR  0xFFFF30
-#define MAR1AE  0xFFFF31
-#define MAR1AH  0xFFFF32
-#define MAR1AL  0xFFFF33
-#define ETCR1AL 0xFFFF34
-#define ETCR1AH 0xFFFF35
-#define IOAR1A  0xFFFF36
-#define DTCR1A  0xFFFF37
-#define MAR1BR  0xFFFF38
-#define MAR1BE  0xFFFF39
-#define MAR1BH  0xFFFF3A
-#define MAR1BL  0xFFFF3B
-#define ETCR1BL 0xFFFF3C
-#define ETCR1BH 0xFFFF3D
-#define IOAR1B  0xFFFF3E
-#define DTCR1B  0xFFFF3F
-
-#define ISCR 0xFEE014
-#define IER  0xFEE015
-#define ISR  0xFEE016
-#define IPRA 0xFEE018
-#define IPRB 0xFEE019
-
-#define P1DDR 0xFEE000
-#define P2DDR 0xFEE001
-#define P3DDR 0xFEE002
-#define P4DDR 0xFEE003
-#define P5DDR 0xFEE004
-#define P6DDR 0xFEE005
-/*#define P7DDR 0xFEE006*/
-#define P8DDR 0xFEE007
-#define P9DDR 0xFEE008
-#define PADDR 0xFEE009
-#define PBDDR 0xFEE00A
-
-#define P1DR  0xFFFFD0
-#define P2DR  0xFFFFD1
-#define P3DR  0xFFFFD2
-#define P4DR  0xFFFFD3
-#define P5DR  0xFFFFD4
-#define P6DR  0xFFFFD5
-/*#define P7DR  0xFFFFD6*/
-#define P8DR  0xFFFFD7
-#define P9DR  0xFFFFD8
-#define PADR  0xFFFFD9
-#define PBDR  0xFFFFDA
-
-#define P2CR  0xFEE03C
-#define P4CR  0xFEE03E
-#define P5CR  0xFEE03F
-
-#define SMR0  0xFFFFB0
-#define BRR0  0xFFFFB1
-#define SCR0  0xFFFFB2
-#define TDR0  0xFFFFB3
-#define SSR0  0xFFFFB4
-#define RDR0  0xFFFFB5
-#define SCMR0 0xFFFFB6
-#define SMR1  0xFFFFB8
-#define BRR1  0xFFFFB9
-#define SCR1  0xFFFFBA
-#define TDR1  0xFFFFBB
-#define SSR1  0xFFFFBC
-#define RDR1  0xFFFFBD
-#define SCMR1 0xFFFFBE
-#define SMR2  0xFFFFC0
-#define BRR2  0xFFFFC1
-#define SCR2  0xFFFFC2
-#define TDR2  0xFFFFC3
-#define SSR2  0xFFFFC4
-#define RDR2  0xFFFFC5
-#define SCMR2 0xFFFFC6
-
-#define MDCR   0xFEE011
-#define SYSCR  0xFEE012
-#define DIVCR  0xFEE01B
-#define MSTCRH 0xFEE01C
-#define MSTCRL 0xFEE01D
-#define FLMCR1 0xFEE030
-#define FLMCR2 0xFEE031
-#define EBR1   0xFEE032
-#define EBR2   0xFEE033
-#define RAMCR  0xFEE077
-
-#define TSTR   0xFFFF60
-#define TSNC   0XFFFF61
-#define TMDR   0xFFFF62
-#define TOLR   0xFFFF63
-#define TISRA  0xFFFF64
-#define TISRB  0xFFFF65
-#define TISRC  0xFFFF66
-#define TCR0   0xFFFF68
-#define TIOR0  0xFFFF69
-#define TCNT0H 0xFFFF6A
-#define TCNT0L 0xFFFF6B
-#define GRA0H  0xFFFF6C
-#define GRA0L  0xFFFF6D
-#define GRB0H  0xFFFF6E
-#define GRB0L  0xFFFF6F
-#define TCR1   0xFFFF70
-#define TIOR1  0xFFFF71
-#define TCNT1H 0xFFFF72
-#define TCNT1L 0xFFFF73
-#define GRA1H  0xFFFF74
-#define GRA1L  0xFFFF75
-#define GRB1H  0xFFFF76
-#define GRB1L  0xFFFF77
-#define TCR3   0xFFFF78
-#define TIOR3  0xFFFF79
-#define TCNT3H 0xFFFF7A
-#define TCNT3L 0xFFFF7B
-#define GRA3H  0xFFFF7C
-#define GRA3L  0xFFFF7D
-#define GRB3H  0xFFFF7E
-#define GRB3L  0xFFFF7F
-
-#define _8TCR0  0xFFFF80
-#define _8TCR1  0xFFFF81
-#define _8TCSR0 0xFFFF82
-#define _8TCSR1 0xFFFF83
-#define TCORA0 0xFFFF84
-#define TCORA1 0xFFFF85
-#define TCORB0 0xFFFF86
-#define TCORB1 0xFFFF87
-#define _8TCNT0 0xFFFF88
-#define _8TCNT1 0xFFFF89
-
-#define _8TCR2  0xFFFF90
-#define _8TCR3  0xFFFF91
-#define _8TCSR2 0xFFFF92
-#define _8TCSR3 0xFFFF93
-#define TCORA2 0xFFFF94
-#define TCORA3 0xFFFF95
-#define TCORB2 0xFFFF96
-#define TCORB3 0xFFFF97
-#define _8TCNT2 0xFFFF98
-#define _8TCNT3 0xFFFF99
-
-#define TCSR   0xFFFF8C
-#define TCNT   0xFFFF8D
-#define RSTCSR 0xFFFF8F
-
-#define TPMR  0xFFFFA0
-#define TPCR  0xFFFFA1
-#define NDERB 0xFFFFA2
-#define NDERA 0xFFFFA3
-#define NDRB1 0xFFFFA4
-#define NDRA1 0xFFFFA5
-#define NDRB2 0xFFFFA6
-#define NDRA2 0xFFFFA7
-
-#define TCSR    0xFFFF8C
-#define TCNT    0xFFFF8D
-#define RSTCSRW 0xFFFF8E
-#define RSTCSRR 0xFFFF8F
-
-#endif /* __KERNEL__ */
-#endif /* __REGS_H8306x__ */
diff --git a/include/asm-h8300/resource.h b/include/asm-h8300/resource.h
deleted file mode 100644
index 46c5f4391607..000000000000
--- a/include/asm-h8300/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_RESOURCE_H
-#define _H8300_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif /* _H8300_RESOURCE_H */
diff --git a/include/asm-h8300/scatterlist.h b/include/asm-h8300/scatterlist.h
deleted file mode 100644
index d3ecdd87ac90..000000000000
--- a/include/asm-h8300/scatterlist.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _H8300_SCATTERLIST_H
-#define _H8300_SCATTERLIST_H
-
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long   sg_magic;
-#endif
-        unsigned long   page_link;
-        unsigned int    offset;
-        dma_addr_t      dma_address;
-        unsigned int    length;
-};
-
-#define ISA_DMA_THRESHOLD       (0xffffffff)
-
-#endif /* !(_H8300_SCATTERLIST_H) */
diff --git a/include/asm-h8300/sections.h b/include/asm-h8300/sections.h
deleted file mode 100644
index a81743e8b743..000000000000
--- a/include/asm-h8300/sections.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_SECTIONS_H_
-#define _H8300_SECTIONS_H_
-
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/include/asm-h8300/segment.h b/include/asm-h8300/segment.h
deleted file mode 100644
index b79a82d0f99d..000000000000
--- a/include/asm-h8300/segment.h
+++ /dev/null
@@ -1,49 +0,0 @@
-#ifndef _H8300_SEGMENT_H
-#define _H8300_SEGMENT_H
-
-/* define constants */
-#define USER_DATA     (1)
-#ifndef __USER_DS
-#define __USER_DS     (USER_DATA)
-#endif
-#define USER_PROGRAM  (2)
-#define SUPER_DATA    (3)
-#ifndef __KERNEL_DS
-#define __KERNEL_DS   (SUPER_DATA)
-#endif
-#define SUPER_PROGRAM (4)
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
-        unsigned long seg;
-} mm_segment_t;
-
-#define MAKE_MM_SEG(s)  ((mm_segment_t) { (s) })
-#define USER_DS         MAKE_MM_SEG(__USER_DS)
-#define KERNEL_DS       MAKE_MM_SEG(__KERNEL_DS)
-
-/*
- * Get/set the SFC/DFC registers for MOVES instructions
- */
-
-static inline mm_segment_t get_fs(void)
-{
-    return USER_DS;
-}
-
-static inline mm_segment_t get_ds(void)
-{
-    /* return the supervisor data space code */
-    return KERNEL_DS;
-}
-
-static inline void set_fs(mm_segment_t val)
-{
-}
-
-#define segment_eq(a,b) ((a).seg == (b).seg)
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _H8300_SEGMENT_H */
diff --git a/include/asm-h8300/sembuf.h b/include/asm-h8300/sembuf.h
deleted file mode 100644
index e04a3ec0cb92..000000000000
--- a/include/asm-h8300/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _H8300_SEMBUF_H
-#define _H8300_SEMBUF_H
-
-/* 
- * The semid64_ds structure for m68k architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;              /* last semop time */
-        unsigned long   __unused1;
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   __unused2;
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _H8300_SEMBUF_H */
diff --git a/include/asm-h8300/setup.h b/include/asm-h8300/setup.h
deleted file mode 100644
index e2c600e96733..000000000000
--- a/include/asm-h8300/setup.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __H8300_SETUP_H
-#define __H8300_SETUP_H
-
-#define COMMAND_LINE_SIZE       512
-
-#endif
diff --git a/include/asm-h8300/sh_bios.h b/include/asm-h8300/sh_bios.h
deleted file mode 100644
index b6bb6e58295c..000000000000
--- a/include/asm-h8300/sh_bios.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* eCos HAL interface header */
-
-#ifndef SH_BIOS_H
-#define SH_BIOS_H
-
-#define HAL_IF_VECTOR_TABLE 0xfffe20
-#define CALL_IF_SET_CONSOLE_COMM  13
-#define QUERY_CURRENT -1
-#define MANGLER       -3
-
-/* Checking for GDB stub active */
-/* suggestion Jonathan Larmour */
-static int sh_bios_in_gdb_mode(void)
-{
-        static int gdb_active = -1;
-        if (gdb_active == -1) {
-                int (*set_console_comm)(int);
-                set_console_comm = ((void **)HAL_IF_VECTOR_TABLE)[CALL_IF_SET_CONSOLE_COMM];
-                gdb_active = (set_console_comm(QUERY_CURRENT) == MANGLER);
-        }
-        return gdb_active;
-}
-
-static void sh_bios_gdb_detach(void)
-{
-
-}
-
-#endif
diff --git a/include/asm-h8300/shm.h b/include/asm-h8300/shm.h
deleted file mode 100644
index ed6623c0545d..000000000000
--- a/include/asm-h8300/shm.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _H8300_SHM_H
-#define _H8300_SHM_H
-
-
-/* format of page table entries that correspond to shared memory pages
-   currently out in swap space (see also mm/swap.c):
-   bits 0-1 (PAGE_PRESENT) is  = 0
-   bits 8..2 (SWP_TYPE) are = SHM_SWP_TYPE
-   bits 31..9 are used like this:
-   bits 15..9 (SHM_ID) the id of the shared memory segment
-   bits 30..16 (SHM_IDX) the index of the page within the shared memory segment
-                    (actually only bits 25..16 get used since SHMMAX is so low)
-   bit 31 (SHM_READ_ONLY) flag whether the page belongs to a read-only attach
-*/
-/* on the m68k both bits 0 and 1 must be zero */
-/* format on the sun3 is similar, but bits 30, 31 are set to zero and all
-   others are reduced by 2. --m */
-
-#ifndef CONFIG_SUN3
-#define SHM_ID_SHIFT    9
-#else
-#define SHM_ID_SHIFT    7
-#endif
-#define _SHM_ID_BITS    7
-#define SHM_ID_MASK     ((1<<_SHM_ID_BITS)-1)
-
-#define SHM_IDX_SHIFT   (SHM_ID_SHIFT+_SHM_ID_BITS)
-#define _SHM_IDX_BITS   15
-#define SHM_IDX_MASK    ((1<<_SHM_IDX_BITS)-1)
-
-#endif /* _H8300_SHM_H */
diff --git a/include/asm-h8300/shmbuf.h b/include/asm-h8300/shmbuf.h
deleted file mode 100644
index 64e77993a7a9..000000000000
--- a/include/asm-h8300/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _H8300_SHMBUF_H
-#define _H8300_SHMBUF_H
-
-/* 
- * The shmid64_ds structure for m68k architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-        unsigned long           __unused1;
-        __kernel_time_t         shm_dtime;      /* last detach time */
-        unsigned long           __unused2;
-        __kernel_time_t         shm_ctime;      /* last change time */
-        unsigned long           __unused3;
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused4;
-        unsigned long           __unused5;
-};
-
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _H8300_SHMBUF_H */
diff --git a/include/asm-h8300/shmparam.h b/include/asm-h8300/shmparam.h
deleted file mode 100644
index d1863953ec64..000000000000
--- a/include/asm-h8300/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_SHMPARAM_H
-#define _H8300_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE                 /* attach addr a multiple of this */
-
-#endif /* _H8300_SHMPARAM_H */
diff --git a/include/asm-h8300/sigcontext.h b/include/asm-h8300/sigcontext.h
deleted file mode 100644
index e4b81505f8f8..000000000000
--- a/include/asm-h8300/sigcontext.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _ASM_H8300_SIGCONTEXT_H
-#define _ASM_H8300_SIGCONTEXT_H
-
-struct sigcontext {
-        unsigned long  sc_mask;         /* old sigmask */
-        unsigned long  sc_usp;          /* old user stack pointer */
-        unsigned long  sc_er0;
-        unsigned long  sc_er1;
-        unsigned long  sc_er2;
-        unsigned long  sc_er3;
-        unsigned long  sc_er4;
-        unsigned long  sc_er5;
-        unsigned long  sc_er6;
-        unsigned short sc_ccr;
-        unsigned long  sc_pc;
-};
-
-#endif
diff --git a/include/asm-h8300/siginfo.h b/include/asm-h8300/siginfo.h
deleted file mode 100644
index bc8fbea931a5..000000000000
--- a/include/asm-h8300/siginfo.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_SIGINFO_H
-#define _H8300_SIGINFO_H
-
-#include <asm-generic/siginfo.h>
-
-#endif
diff --git a/include/asm-h8300/signal.h b/include/asm-h8300/signal.h
deleted file mode 100644
index 7bc15048a64f..000000000000
--- a/include/asm-h8300/signal.h
+++ /dev/null
@@ -1,161 +0,0 @@
-#ifndef _H8300_SIGNAL_H
-#define _H8300_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-#define _NSIG           64
-#define _NSIG_BPW       32
-#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;             /* at least 32 bits */
-
-typedef struct {
-        unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG            32
-typedef unsigned long sigset_t;
-
-#endif /* __KERNEL__ */
-
-#define SIGHUP           1
-#define SIGINT           2
-#define SIGQUIT          3
-#define SIGILL           4
-#define SIGTRAP          5
-#define SIGABRT          6
-#define SIGIOT           6
-#define SIGBUS           7
-#define SIGFPE           8
-#define SIGKILL          9
-#define SIGUSR1         10
-#define SIGSEGV         11
-#define SIGUSR2         12
-#define SIGPIPE         13
-#define SIGALRM         14
-#define SIGTERM         15
-#define SIGSTKFLT       16
-#define SIGCHLD         17
-#define SIGCONT         18
-#define SIGSTOP         19
-#define SIGTSTP         20
-#define SIGTTIN         21
-#define SIGTTOU         22
-#define SIGURG          23
-#define SIGXCPU         24
-#define SIGXFSZ         25
-#define SIGVTALRM       26
-#define SIGPROF         27
-#define SIGWINCH        28
-#define SIGIO           29
-#define SIGPOLL         SIGIO
-/*
-#define SIGLOST         29
-*/
-#define SIGPWR          30
-#define SIGSYS          31
-#define SIGUNUSED       31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP    0x00000001
-#define SA_NOCLDWAIT    0x00000002 /* not supported yet */
-#define SA_SIGINFO      0x00000004
-#define SA_ONSTACK      0x08000000
-#define SA_RESTART      0x10000000
-#define SA_NODEFER      0x40000000
-#define SA_RESETHAND    0x80000000
-
-#define SA_NOMASK       SA_NODEFER
-#define SA_ONESHOT      SA_RESETHAND
-
-#define SA_RESTORER     0x04000000
-
-/* 
- * sigaltstack controls
- */
-#define SS_ONSTACK      1
-#define SS_DISABLE      2
-
-#define MINSIGSTKSZ     2048
-#define SIGSTKSZ        8192
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct old_sigaction {
-        __sighandler_t sa_handler;
-        old_sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-};
-
-struct sigaction {
-        __sighandler_t sa_handler;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-        sigset_t sa_mask;               /* mask last for extensibility */
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-};
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-        union {
-          __sighandler_t _sa_handler;
-          void (*_sa_sigaction)(int, struct siginfo *, void *);
-        } _u;
-        sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer)(void);
-};
-
-#define sa_handler      _u._sa_handler
-#define sa_sigaction    _u._sa_sigaction
-
-#endif /* __KERNEL__ */
-
-typedef struct sigaltstack {
-        void *ss_sp;
-        int ss_flags;
-        size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-
-#include <asm/sigcontext.h>
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* __KERNEL__ */
-
-#endif /* _H8300_SIGNAL_H */
diff --git a/include/asm-h8300/smp.h b/include/asm-h8300/smp.h
deleted file mode 100644
index 9e9bd7e58922..000000000000
--- a/include/asm-h8300/smp.h
+++ /dev/null
@@ -1 +0,0 @@
-/* nothing required here yet */
diff --git a/include/asm-h8300/socket.h b/include/asm-h8300/socket.h
deleted file mode 100644
index da2520dbf254..000000000000
--- a/include/asm-h8300/socket.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockoptions(2) */
-#define SOL_SOCKET      1
-
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_ACCEPTCONN           30
-
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-#define SO_MARK                 36
-
-#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-h8300/sockios.h b/include/asm-h8300/sockios.h
deleted file mode 100644
index e9c7ec810c23..000000000000
--- a/include/asm-h8300/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_H8300_SOCKIOS__
-#define __ARCH_H8300_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-
-#endif /* __ARCH_H8300_SOCKIOS__ */
diff --git a/include/asm-h8300/spinlock.h b/include/asm-h8300/spinlock.h
deleted file mode 100644
index d5407fa173e4..000000000000
--- a/include/asm-h8300/spinlock.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __H8300_SPINLOCK_H
-#define __H8300_SPINLOCK_H
-
-#error "H8/300 doesn't do SMP yet"
-
-#endif
diff --git a/include/asm-h8300/stat.h b/include/asm-h8300/stat.h
deleted file mode 100644
index 62c3cc24dfe6..000000000000
--- a/include/asm-h8300/stat.h
+++ /dev/null
@@ -1,78 +0,0 @@
-#ifndef _H8300_STAT_H
-#define _H8300_STAT_H
-
-struct __old_kernel_stat {
-        unsigned short st_dev;
-        unsigned short st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned long  st_size;
-        unsigned long  st_atime;
-        unsigned long  st_mtime;
-        unsigned long  st_ctime;
-};
-
-struct stat {
-        unsigned short st_dev;
-        unsigned short __pad1;
-        unsigned long st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned short __pad2;
-        unsigned long  st_size;
-        unsigned long  st_blksize;
-        unsigned long  st_blocks;
-        unsigned long  st_atime;
-        unsigned long  __unused1;
-        unsigned long  st_mtime;
-        unsigned long  __unused2;
-        unsigned long  st_ctime;
-        unsigned long  __unused3;
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-        unsigned long long      st_dev;
-        unsigned char   __pad1[2];
-
-#define STAT64_HAS_BROKEN_ST_INO        1
-        unsigned long   __st_ino;
-
-        unsigned int    st_mode;
-        unsigned int    st_nlink;
-
-        unsigned long   st_uid;
-        unsigned long   st_gid;
-
-        unsigned long long      st_rdev;
-        unsigned char   __pad3[2];
-
-        long long       st_size;
-        unsigned long   st_blksize;
-
-        unsigned long   __pad4;         /* future possible st_blocks high bits */
-        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
-
-        unsigned long   st_atime;
-        unsigned long   st_atime_nsec;
-
-        unsigned long   st_mtime;
-        unsigned long   st_mtime_nsec;
-
-        unsigned long   st_ctime;
-        unsigned long   st_ctime_nsec;
-
-        unsigned long long      st_ino;
-};
-
-#endif /* _H8300_STAT_H */
diff --git a/include/asm-h8300/statfs.h b/include/asm-h8300/statfs.h
deleted file mode 100644
index b96efa712aac..000000000000
--- a/include/asm-h8300/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _H8300_STATFS_H
-#define _H8300_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif /* _H8300_STATFS_H */
diff --git a/include/asm-h8300/string.h b/include/asm-h8300/string.h
deleted file mode 100644
index ca5034897d87..000000000000
--- a/include/asm-h8300/string.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef _H8300_STRING_H_
-#define _H8300_STRING_H_
-
-#ifdef __KERNEL__ /* only set these up for kernel code */
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#define __HAVE_ARCH_MEMSET
-extern void * memset(void * s, int c, size_t count);
-
-#define __HAVE_ARCH_MEMCPY
-extern void * memcpy(void *d, const void *s, size_t count);
-
-#else /* KERNEL */
-
-/*
- *      let user libraries deal with these,
- *      IMHO the kernel has no place defining these functions for user apps
- */
-
-#define __HAVE_ARCH_STRCPY 1
-#define __HAVE_ARCH_STRNCPY 1
-#define __HAVE_ARCH_STRCAT 1
-#define __HAVE_ARCH_STRNCAT 1
-#define __HAVE_ARCH_STRCMP 1
-#define __HAVE_ARCH_STRNCMP 1
-#define __HAVE_ARCH_STRNICMP 1
-#define __HAVE_ARCH_STRCHR 1
-#define __HAVE_ARCH_STRRCHR 1
-#define __HAVE_ARCH_STRSTR 1
-#define __HAVE_ARCH_STRLEN 1
-#define __HAVE_ARCH_STRNLEN 1
-#define __HAVE_ARCH_MEMSET 1
-#define __HAVE_ARCH_MEMCPY 1
-#define __HAVE_ARCH_MEMMOVE 1
-#define __HAVE_ARCH_MEMSCAN 1
-#define __HAVE_ARCH_MEMCMP 1
-#define __HAVE_ARCH_MEMCHR 1
-#define __HAVE_ARCH_STRTOK 1
-
-#endif /* KERNEL */
-
-#endif /* _M68K_STRING_H_ */
diff --git a/include/asm-h8300/system.h b/include/asm-h8300/system.h
deleted file mode 100644
index 4b8e475908ae..000000000000
--- a/include/asm-h8300/system.h
+++ /dev/null
@@ -1,158 +0,0 @@
-#ifndef _H8300_SYSTEM_H
-#define _H8300_SYSTEM_H
-
-#include <linux/linkage.h>
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.  This
- * also clears the TS-flag if the task we switched to has used the
- * math co-processor latest.
- */
-/*
- * switch_to() saves the extra registers, that are not saved
- * automatically by SAVE_SWITCH_STACK in resume(), ie. d0-d5 and
- * a0-a1. Some of these are used by schedule() and its predecessors
- * and so we might get see unexpected behaviors when a task returns
- * with unexpected register values.
- *
- * syscall stores these registers itself and none of them are used
- * by syscall after the function in the syscall has been called.
- *
- * Beware that resume now expects *next to be in d1 and the offset of
- * tss to be in a1. This saves a few instructions as we no longer have
- * to push them onto the stack and read them back right after.
- *
- * 02/17/96 - Jes Sorensen (jds@kom.auc.dk)
- *
- * Changed 96/09/19 by Andreas Schwab
- * pass prev in a0, next in a1, offset of tss in d1, and whether
- * the mm structures are shared in d2 (to avoid atc flushing).
- *
- * H8/300 Porting 2002/09/04 Yoshinori Sato
- */
-
-asmlinkage void resume(void);
-#define switch_to(prev,next,last) {                         \
-  void *_last;                                              \
-  __asm__ __volatile__(                                     \
-                        "mov.l  %1, er0\n\t"                \
-                        "mov.l  %2, er1\n\t"                \
-                        "mov.l  %3, er2\n\t"                \
-                        "jsr @_resume\n\t"                  \
-                        "mov.l  er2,%0\n\t"                 \
-                       : "=r" (_last)                       \
-                       : "r" (&(prev->thread)),             \
-                         "r" (&(next->thread)),             \
-                         "g" (prev)                         \
-                       : "cc", "er0", "er1", "er2", "er3"); \
-  (last) = _last;                                           \
-}
-
-#define __sti() asm volatile ("andc #0x7f,ccr")
-#define __cli() asm volatile ("orc  #0x80,ccr")
-
-#define __save_flags(x) \
-       asm volatile ("stc ccr,%w0":"=r" (x))
-
-#define __restore_flags(x) \
-       asm volatile ("ldc %w0,ccr": :"r" (x))
-
-#define irqs_disabled()                 \
-({                                      \
-        unsigned char flags;            \
-        __save_flags(flags);            \
-        ((flags & 0x80) == 0x80);       \
-})
-
-#define iret() __asm__ __volatile__ ("rte": : :"memory", "sp", "cc")
-
-/* For spinlocks etc */
-#define local_irq_disable()     __cli()
-#define local_irq_enable()      __sti()
-#define local_irq_save(x)       ({ __save_flags(x); local_irq_disable(); })
-#define local_irq_restore(x)    __restore_flags(x)
-#define local_save_flags(x)     __save_flags(x)
-
-/*
- * Force strict CPU ordering.
- * Not really required on H8...
- */
-#define nop()  asm volatile ("nop"::)
-#define mb()   asm volatile (""   : : :"memory")
-#define rmb()  asm volatile (""   : : :"memory")
-#define wmb()  asm volatile (""   : : :"memory")
-#define set_mb(var, value) do { xchg(&var, value); } while (0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while(0)
-#endif
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-  unsigned long tmp, flags;
-
-  local_irq_save(flags);
-
-  switch (size) {
-  case 1:
-    __asm__ __volatile__
-    ("mov.b %2,%0\n\t"
-     "mov.b %1,%2"
-    : "=&r" (tmp) : "r" (x), "m" (*__xg(ptr)) : "memory");
-    break;
-  case 2:
-    __asm__ __volatile__
-    ("mov.w %2,%0\n\t"
-     "mov.w %1,%2"
-    : "=&r" (tmp) : "r" (x), "m" (*__xg(ptr)) : "memory");
-    break;
-  case 4:
-    __asm__ __volatile__
-    ("mov.l %2,%0\n\t"
-     "mov.l %1,%2"
-    : "=&r" (tmp) : "r" (x), "m" (*__xg(ptr)) : "memory");
-    break;
-  default:
-    tmp = 0;      
-  }
-  local_irq_restore(flags);
-  return tmp;
-}
-
-#define HARD_RESET_NOW() ({             \
-        local_irq_disable();            \
-        asm("jmp @@0");                 \
-})
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)                                               \
-        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-                        (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#define arch_align_stack(x) (x)
-
-#endif /* _H8300_SYSTEM_H */
diff --git a/include/asm-h8300/target_time.h b/include/asm-h8300/target_time.h
deleted file mode 100644
index 9f2a9aa1fe6f..000000000000
--- a/include/asm-h8300/target_time.h
+++ /dev/null
@@ -1,4 +0,0 @@
-extern int platform_timer_setup(void (*timer_int)(int, void *, struct pt_regs *));
-extern void platform_timer_eoi(void);
-extern void platform_gettod(unsigned int *year, unsigned int *mon, unsigned int *day, 
-                            unsigned int *hour, unsigned int *min, unsigned int *sec);
diff --git a/include/asm-h8300/termbits.h b/include/asm-h8300/termbits.h
deleted file mode 100644
index 31eca81db3f7..000000000000
--- a/include/asm-h8300/termbits.h
+++ /dev/null
@@ -1,200 +0,0 @@
-#ifndef __ARCH_H8300_TERMBITS_H__
-#define __ARCH_H8300_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char   cc_t;
-typedef unsigned int    speed_t;
-typedef unsigned int    tcflag_t;
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-};
-
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000          /* input baud rate */
-#define CMSPAR    010000000000          /* mark or space (stick) parity */
-#define CRTSCTS   020000000000          /* flow control */
-
-#define IBSHIFT   16                    /* shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif /* __ARCH_H8300_TERMBITS_H__ */
diff --git a/include/asm-h8300/termios.h b/include/asm-h8300/termios.h
deleted file mode 100644
index 70eea64b4213..000000000000
--- a/include/asm-h8300/termios.h
+++ /dev/null
@@ -1,92 +0,0 @@
-#ifndef _H8300_TERMIOS_H
-#define _H8300_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
- 
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        unsigned char c_line;           /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-#ifdef __KERNEL__
-/*      intr=^C         quit=^|         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-#endif
-
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        unsigned short tmp; \
-        get_user(tmp, &(termio)->c_iflag); \
-        (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
-        get_user(tmp, &(termio)->c_oflag); \
-        (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
-        get_user(tmp, &(termio)->c_cflag); \
-        (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
-        get_user(tmp, &(termio)->c_lflag); \
-        (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
-        get_user((termios)->c_line, &(termio)->c_line); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif  /* __KERNEL__ */
-
-#endif /* _H8300_TERMIOS_H */
diff --git a/include/asm-h8300/thread_info.h b/include/asm-h8300/thread_info.h
deleted file mode 100644
index aafd4d322ec3..000000000000
--- a/include/asm-h8300/thread_info.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/* thread_info.h: h8300 low-level thread information
- * adapted from the i386 and PPC versions by Yoshinori Sato <ysato@users.sourceforge.jp>
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-struct thread_info {
-        struct task_struct *task;               /* main task structure */
-        struct exec_domain *exec_domain;        /* execution domain */
-        unsigned long      flags;               /* low level flags */
-        int                cpu;                 /* cpu we're on */
-        int                preempt_count;       /* 0 => preemptable, <0 => BUG */
-        struct restart_block restart_block;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task =         &tsk,                   \
-        .exec_domain =  &default_exec_domain,   \
-        .flags =        0,                      \
-        .cpu =          0,                      \
-        .preempt_count = 1,                     \
-        .restart_block  = {                     \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE             8192    /* 2 pages */
-
-
-/* how to get the thread information struct from C */
-static inline struct thread_info *current_thread_info(void)
-{
-        struct thread_info *ti;
-        __asm__(
-                "mov.l  sp, %0 \n\t"
-                "and.l  %1, %0"
-                : "=&r"(ti)
-                : "i" (~(THREAD_SIZE-1))
-                );
-        return ti;
-}
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * Offsets in thread_info structure, used in assembly code
- */
-#define TI_TASK         0
-#define TI_EXECDOMAIN   4
-#define TI_FLAGS        8
-#define TI_CPU          12
-#define TI_PRE_COUNT    16
-
-#define PREEMPT_ACTIVE  0x4000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_SIGPENDING          1       /* signal pending */
-#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
-                                           TIF_NEED_RESCHED */
-#define TIF_MEMDIE              4
-#define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-
-#define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-h8300/timex.h b/include/asm-h8300/timex.h
deleted file mode 100644
index 23e67013439f..000000000000
--- a/include/asm-h8300/timex.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * linux/include/asm-h8300/timex.h
- *
- * H8/300 architecture timex specifications
- */
-#ifndef _ASM_H8300_TIMEX_H
-#define _ASM_H8300_TIMEX_H
-
-#define CLOCK_TICK_RATE (CONFIG_CPU_CLOCK*1000/8192) /* Timer input freq. */
-
-typedef unsigned long cycles_t;
-extern short h8300_timer_count;
-
-static inline cycles_t get_cycles(void)
-{
-        return 0;
-}
-
-#endif
diff --git a/include/asm-h8300/tlb.h b/include/asm-h8300/tlb.h
deleted file mode 100644
index 3dea80ad9e6f..000000000000
--- a/include/asm-h8300/tlb.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* 
-  include/asm-h8300/tlb.h 
-*/
-
-#ifndef __H8300_TLB_H__
-#define __H8300_TLB_H__
-
-#define tlb_flush(tlb)  do { } while(0)
-
-/* 
-  include/asm-h8300/tlb.h 
-*/
-
-#ifndef __H8300_TLB_H__
-#define __H8300_TLB_H__
-
-#define tlb_flush(tlb)  do { } while(0)
-
-#include <asm-generic/tlb.h>
-
-#endif
-
-#endif
diff --git a/include/asm-h8300/tlbflush.h b/include/asm-h8300/tlbflush.h
deleted file mode 100644
index 41c148a9208e..000000000000
--- a/include/asm-h8300/tlbflush.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _H8300_TLBFLUSH_H
-#define _H8300_TLBFLUSH_H
-
-/*
- * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
- * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
- */
-
-#include <asm/setup.h>
-
-/*
- * flush all user-space atc entries.
- */
-static inline void __flush_tlb(void)
-{
-        BUG();
-}
-
-static inline void __flush_tlb_one(unsigned long addr)
-{
-        BUG();
-}
-
-#define flush_tlb() __flush_tlb()
-
-/*
- * flush all atc entries (both kernel and user-space entries).
- */
-static inline void flush_tlb_all(void)
-{
-        BUG();
-}
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-        BUG();
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
-{
-        BUG();
-}
-
-static inline void flush_tlb_range(struct mm_struct *mm,
-                                   unsigned long start, unsigned long end)
-{
-        BUG();
-}
-
-static inline void flush_tlb_kernel_page(unsigned long addr)
-{
-        BUG();
-}
-
-#endif /* _H8300_TLBFLUSH_H */
diff --git a/include/asm-h8300/topology.h b/include/asm-h8300/topology.h
deleted file mode 100644
index fdc121924d4c..000000000000
--- a/include/asm-h8300/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_H8300_TOPOLOGY_H
-#define _ASM_H8300_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_H8300_TOPOLOGY_H */
diff --git a/include/asm-h8300/traps.h b/include/asm-h8300/traps.h
deleted file mode 100644
index 41cf6be02f68..000000000000
--- a/include/asm-h8300/traps.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  linux/include/asm-h8300/traps.h
- *
- *  Copyright (C) 2003 Yoshinori Sato <ysato@users.sourceforge.jp>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _H8300_TRAPS_H
-#define _H8300_TRAPS_H
-
-extern void system_call(void);
-extern void interrupt_entry(void);
-extern void trace_break(void);
-
-#define JMP_OP 0x5a000000
-#define JSR_OP 0x5e000000
-#define VECTOR(address) ((JMP_OP)|((unsigned long)address))
-#define REDIRECT(address) ((JSR_OP)|((unsigned long)address))
-
-#define TRACE_VEC 5
-
-#define TRAP0_VEC 8
-#define TRAP1_VEC 9
-#define TRAP2_VEC 10
-#define TRAP3_VEC 11
-
-#if defined(__H8300H__)
-#define NR_TRAPS 12
-#endif
-#if defined(__H8300S__)
-#define NR_TRAPS 16
-#endif
-
-#endif /* _H8300_TRAPS_H */
diff --git a/include/asm-h8300/types.h b/include/asm-h8300/types.h
deleted file mode 100644
index 12875190b156..000000000000
--- a/include/asm-h8300/types.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _H8300_TYPES_H
-#define _H8300_TYPES_H
-
-#include <asm-generic/int-ll64.h>
-
-#if !defined(__ASSEMBLY__)
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-
-typedef unsigned short umode_t;
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _H8300_TYPES_H */
diff --git a/include/asm-h8300/uaccess.h b/include/asm-h8300/uaccess.h
deleted file mode 100644
index 356068cd0879..000000000000
--- a/include/asm-h8300/uaccess.h
+++ /dev/null
@@ -1,162 +0,0 @@
-#ifndef __H8300_UACCESS_H
-#define __H8300_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-
-/* We let the MMU do all checking */
-#define access_ok(type, addr, size) __access_ok((unsigned long)addr,size)
-static inline int __access_ok(unsigned long addr, unsigned long size)
-{
-#define RANGE_CHECK_OK(addr, size, lower, upper) \
-        (((addr) >= (lower)) && (((addr) + (size)) < (upper)))
-
-        extern unsigned long _ramend;
-        return(RANGE_CHECK_OK(addr, size, 0L, (unsigned long)&_ramend));
-}
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry
-{
-        unsigned long insn, fixup;
-};
-
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x, ptr)                                \
-({                                                      \
-    int __pu_err = 0;                                   \
-    typeof(*(ptr)) __pu_val = (x);                      \
-    switch (sizeof (*(ptr))) {                          \
-    case 1:                                             \
-    case 2:                                             \
-    case 4:                                             \
-        *(ptr) = (__pu_val);                            \
-        break;                                          \
-    case 8:                                             \
-        memcpy(ptr, &__pu_val, sizeof (*(ptr)));        \
-        break;                                          \
-    default:                                            \
-        __pu_err = __put_user_bad();                    \
-        break;                                          \
-    }                                                   \
-    __pu_err;                                           \
-})
-#define __put_user(x, ptr) put_user(x, ptr)
-
-extern int __put_user_bad(void);
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long *)(x))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define get_user(x, ptr)                                        \
-({                                                              \
-    int __gu_err = 0;                                           \
-    typeof(*(ptr)) __gu_val = *ptr;                             \
-    switch (sizeof(*(ptr))) {                                   \
-    case 1:                                                     \
-    case 2:                                                     \
-    case 4:                                                     \
-    case 8:                                                     \
-        break;                                                  \
-    default:                                                    \
-        __gu_err = __get_user_bad();                            \
-        __gu_val = 0;                                           \
-        break;                                                  \
-    }                                                           \
-    (x) = __gu_val;                                             \
-    __gu_err;                                                   \
-})
-#define __get_user(x, ptr) get_user(x, ptr)
-
-extern int __get_user_bad(void);
-
-#define copy_from_user(to, from, n)             (memcpy(to, from, n), 0)
-#define copy_to_user(to, from, n)               (memcpy(to, from, n), 0)
-
-#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
-#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n)) return retval; })
-
-#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n)) return retval; })
-
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long
-strncpy_from_user(char *dst, const char *src, long count)
-{
-        char *tmp;
-        strncpy(dst, src, count);
-        for (tmp = dst; *tmp && count > 0; tmp++, count--)
-                ;
-        return(tmp - dst); /* DAVIDM should we count a NUL ?  check getname */
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-static inline long strnlen_user(const char *src, long n)
-{
-        return(strlen(src) + 1); /* DAVIDM make safer */
-}
-
-#define strlen_user(str) strnlen_user(str, 32767)
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long
-clear_user(void *to, unsigned long n)
-{
-        memset(to, 0, n);
-        return 0;
-}
-
-#endif /* _H8300_UACCESS_H */
diff --git a/include/asm-h8300/ucontext.h b/include/asm-h8300/ucontext.h
deleted file mode 100644
index 0bcf8f85fab9..000000000000
--- a/include/asm-h8300/ucontext.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _H8300_UCONTEXT_H
-#define _H8300_UCONTEXT_H
-
-struct ucontext {
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        stack_t           uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
-
-#endif
diff --git a/include/asm-h8300/unaligned.h b/include/asm-h8300/unaligned.h
deleted file mode 100644
index b8d06c70c2da..000000000000
--- a/include/asm-h8300/unaligned.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_H8300_UNALIGNED_H
-#define _ASM_H8300_UNALIGNED_H
-
-#include <linux/unaligned/be_memmove.h>
-#include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned   __get_unaligned_be
-#define put_unaligned   __put_unaligned_be
-
-#endif /* _ASM_H8300_UNALIGNED_H */
diff --git a/include/asm-h8300/unistd.h b/include/asm-h8300/unistd.h
deleted file mode 100644
index 99f3c3561ecb..000000000000
--- a/include/asm-h8300/unistd.h
+++ /dev/null
@@ -1,364 +0,0 @@
-#ifndef _ASM_H8300_UNISTD_H_
-#define _ASM_H8300_UNISTD_H_
-
-/*
- * This file contains the system call numbers.
- */
-
-#define __NR_restart_syscall      0
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-#define __NR_waitpid              7
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_time                13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_lchown              16
-#define __NR_break               17
-#define __NR_oldstat             18
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-#define __NR_umount              22
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_ptrace              26
-#define __NR_alarm               27
-#define __NR_oldfstat            28
-#define __NR_pause               29
-#define __NR_utime               30
-#define __NR_stty                31
-#define __NR_gtty                32
-#define __NR_access              33
-#define __NR_nice                34
-#define __NR_ftime               35
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-#define __NR_prof                44
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-#define __NR_signal              48
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_umount2             52
-#define __NR_lock                53
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-#define __NR_mpx                 56
-#define __NR_setpgid             57
-#define __NR_ulimit              58
-#define __NR_oldolduname         59
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-#define __NR_sigaction           67
-#define __NR_sgetmask            68
-#define __NR_ssetmask            69
-#define __NR_setreuid            70
-#define __NR_setregid            71
-#define __NR_sigsuspend          72
-#define __NR_sigpending          73
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-#define __NR_getrlimit           76
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-#define __NR_select              82
-#define __NR_symlink             83
-#define __NR_oldlstat            84
-#define __NR_readlink            85
-#define __NR_uselib              86
-#define __NR_swapon              87
-#define __NR_reboot              88
-#define __NR_readdir             89
-#define __NR_mmap                90
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-#define __NR_profil              98
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-#define __NR_ioperm             101
-#define __NR_socketcall         102
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-#define __NR_olduname           109
-#define __NR_iopl               110
-#define __NR_vhangup            111
-#define __NR_idle               112
-#define __NR_vm86old            113
-#define __NR_wait4              114
-#define __NR_swapoff            115
-#define __NR_sysinfo            116
-#define __NR_ipc                117
-#define __NR_fsync              118
-#define __NR_sigreturn          119
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-#define __NR_modify_ldt         123
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-#define __NR_sigprocmask        126
-#define __NR_create_module      127
-#define __NR_init_module        128
-#define __NR_delete_module      129
-#define __NR_get_kernel_syms    130
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-#define __NR_sysfs              135
-#define __NR_personality        136
-#define __NR_afs_syscall        137 /* Syscall for Andrew File System */
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-#define __NR__newselect         142
-#define __NR_flock              143
-#define __NR_msync              144
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-#define __NR_mlock              150
-#define __NR_munlock            151
-#define __NR_mlockall           152
-#define __NR_munlockall         153
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-#define __NR_vm86               166
-#define __NR_query_module       167
-#define __NR_poll               168
-#define __NR_nfsservctl         169
-#define __NR_setresgid          170
-#define __NR_getresgid          171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn       173
-#define __NR_rt_sigaction       174
-#define __NR_rt_sigprocmask     175
-#define __NR_rt_sigpending      176
-#define __NR_rt_sigtimedwait    177
-#define __NR_rt_sigqueueinfo    178
-#define __NR_rt_sigsuspend      179
-#define __NR_pread64            180
-#define __NR_pwrite64           181
-#define __NR_chown              182
-#define __NR_getcwd             183
-#define __NR_capget             184
-#define __NR_capset             185
-#define __NR_sigaltstack        186
-#define __NR_sendfile           187
-#define __NR_getpmsg            188     /* some people actually want streams */
-#define __NR_putpmsg            189     /* some people actually want streams */
-#define __NR_vfork              190
-#define __NR_ugetrlimit         191
-#define __NR_mmap2              192
-#define __NR_truncate64         193
-#define __NR_ftruncate64        194
-#define __NR_stat64             195
-#define __NR_lstat64            196
-#define __NR_fstat64            197
-#define __NR_lchown32           198
-#define __NR_getuid32           199
-#define __NR_getgid32           200
-#define __NR_geteuid32          201
-#define __NR_getegid32          202
-#define __NR_setreuid32         203
-#define __NR_setregid32         204
-#define __NR_getgroups32        205
-#define __NR_setgroups32        206
-#define __NR_fchown32           207
-#define __NR_setresuid32        208
-#define __NR_getresuid32        209
-#define __NR_setresgid32        210
-#define __NR_getresgid32        211
-#define __NR_chown32            212
-#define __NR_setuid32           213
-#define __NR_setgid32           214
-#define __NR_setfsuid32         215
-#define __NR_setfsgid32         216
-#define __NR_pivot_root         217
-#define __NR_mincore            218
-#define __NR_madvise            219
-#define __NR_madvise1           219
-#define __NR_getdents64         220
-#define __NR_fcntl64            221
-/* 223 is unused */
-#define __NR_gettid             224
-#define __NR_readahead          225
-#define __NR_setxattr           226
-#define __NR_lsetxattr          227
-#define __NR_fsetxattr          228
-#define __NR_getxattr           229
-#define __NR_lgetxattr          230
-#define __NR_fgetxattr          231
-#define __NR_listxattr          232
-#define __NR_llistxattr         233
-#define __NR_flistxattr         234
-#define __NR_removexattr        235
-#define __NR_lremovexattr       236
-#define __NR_fremovexattr       237
-#define __NR_tkill              238
-#define __NR_sendfile64         239
-#define __NR_futex              240
-#define __NR_sched_setaffinity  241
-#define __NR_sched_getaffinity  242
-#define __NR_set_thread_area    243
-#define __NR_get_thread_area    244
-#define __NR_io_setup           245
-#define __NR_io_destroy         246
-#define __NR_io_getevents       247
-#define __NR_io_submit          248
-#define __NR_io_cancel          249
-#define __NR_fadvise64          250
-/* 251 is available for reuse (was briefly sys_set_zone_reclaim) */
-#define __NR_exit_group         252
-#define __NR_lookup_dcookie     253
-#define __NR_epoll_create       254
-#define __NR_epoll_ctl          255
-#define __NR_epoll_wait         256
-#define __NR_remap_file_pages   257
-#define __NR_set_tid_address    258
-#define __NR_timer_create       259
-#define __NR_timer_settime      (__NR_timer_create+1)
-#define __NR_timer_gettime      (__NR_timer_create+2)
-#define __NR_timer_getoverrun   (__NR_timer_create+3)
-#define __NR_timer_delete       (__NR_timer_create+4)
-#define __NR_clock_settime      (__NR_timer_create+5)
-#define __NR_clock_gettime      (__NR_timer_create+6)
-#define __NR_clock_getres       (__NR_timer_create+7)
-#define __NR_clock_nanosleep    (__NR_timer_create+8)
-#define __NR_statfs64           268
-#define __NR_fstatfs64          269
-#define __NR_tgkill             270
-#define __NR_utimes             271
-#define __NR_fadvise64_64       272
-#define __NR_vserver            273
-#define __NR_mbind              274
-#define __NR_get_mempolicy      275
-#define __NR_set_mempolicy      276
-#define __NR_mq_open            277
-#define __NR_mq_unlink          (__NR_mq_open+1)
-#define __NR_mq_timedsend       (__NR_mq_open+2)
-#define __NR_mq_timedreceive    (__NR_mq_open+3)
-#define __NR_mq_notify          (__NR_mq_open+4)
-#define __NR_mq_getsetattr      (__NR_mq_open+5)
-#define __NR_kexec_load         283
-#define __NR_waitid             284
-/* #define __NR_sys_setaltroot  285 */
-#define __NR_add_key            286
-#define __NR_request_key        287
-#define __NR_keyctl             288
-#define __NR_ioprio_set         289
-#define __NR_ioprio_get         290
-#define __NR_inotify_init       291
-#define __NR_inotify_add_watch  292
-#define __NR_inotify_rm_watch   293
-#define __NR_migrate_pages      294
-#define __NR_openat             295
-#define __NR_mkdirat            296
-#define __NR_mknodat            297
-#define __NR_fchownat           298
-#define __NR_futimesat          299
-#define __NR_fstatat64          300
-#define __NR_unlinkat           301
-#define __NR_renameat           302
-#define __NR_linkat             303
-#define __NR_symlinkat          304
-#define __NR_readlinkat         305
-#define __NR_fchmodat           306
-#define __NR_faccessat          307
-#define __NR_pselect6           308
-#define __NR_ppoll              309
-#define __NR_unshare            310
-#define __NR_set_robust_list    311
-#define __NR_get_robust_list    312
-#define __NR_splice             313
-#define __NR_sync_file_range    314
-#define __NR_tee                315
-#define __NR_vmsplice           316
-#define __NR_move_pages         317
-#define __NR_getcpu             318
-#define __NR_epoll_pwait        319
-
-#ifdef __KERNEL__
-
-#define NR_syscalls 320
-
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_OLD_STAT
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_SIGNAL
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-
-/*
- * "Conditional" syscalls
- */
-#define cond_syscall(name)                                              \
-  asm (".weak\t_" #name "\n"                            \
-       ".set\t_" #name ",_sys_ni_syscall");
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_H8300_UNISTD_H_ */
diff --git a/include/asm-h8300/user.h b/include/asm-h8300/user.h
deleted file mode 100644
index 14a9e18950f1..000000000000
--- a/include/asm-h8300/user.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef _H8300_USER_H
-#define _H8300_USER_H
-
-#include <asm/page.h>
-
-/* Core file format: The core file is written in such a way that gdb
-   can understand it and provide useful information to the user (under
-   linux we use the 'trad-core' bfd).  There are quite a number of
-   obstacles to being able to view the contents of the floating point
-   registers, and until these are solved you will not be able to view the
-   contents of them.  Actually, you can read in the core file and look at
-   the contents of the user struct to find out what the floating point
-   registers contain.
-   The actual file contents are as follows:
-   UPAGE: 1 page consisting of a user struct that tells gdb what is present
-   in the file.  Directly after this is a copy of the task_struct, which
-   is currently not used by gdb, but it may come in useful at some point.
-   All of the registers are stored as part of the upage.  The upage should
-   always be only one page.
-   DATA: The data area is stored.  We use current->end_text to
-   current->brk to pick up all of the user variables, plus any memory
-   that may have been malloced.  No attempt is made to determine if a page
-   is demand-zero or if a page is totally unused, we just cover the entire
-   range.  All of the addresses are rounded in such a way that an integral
-   number of pages is written.
-   STACK: We need the stack information in order to get a meaningful
-   backtrace.  We need to write the data from (esp) to
-   current->start_stack, so we round each of these off in order to be able
-   to write an integer number of pages.
-   The minimum core file size is 3 pages, or 12288 bytes.
-*/
-
-/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
-   is still the layout used by user (the new pt_regs doesn't have
-   all registers). */
-struct user_regs_struct {
-        long er1,er2,er3,er4,er5,er6;
-        long er0;
-        long usp;
-        long orig_er0;
-        short ccr;
-        long pc;
-};
-
-        
-/* When the kernel dumps core, it starts by dumping the user struct -
-   this will be used by gdb to figure out where the data and stack segments
-   are within the file, and what virtual addresses to use. */
-struct user{
-/* We start with the registers, to mimic the way that "memory" is returned
-   from the ptrace(3,...) function.  */
-  struct user_regs_struct regs; /* Where the registers are actually stored */
-/* ptrace does not yet supply these.  Someday.... */
-/* The rest of this junk is to help gdb figure out what goes where */
-  unsigned long int u_tsize;    /* Text segment size (pages). */
-  unsigned long int u_dsize;    /* Data segment size (pages). */
-  unsigned long int u_ssize;    /* Stack segment size (pages). */
-  unsigned long start_code;     /* Starting virtual address of text. */
-  unsigned long start_stack;    /* Starting virtual address of stack area.
-                                   This is actually the bottom of the stack,
-                                   the top of the stack is always found in the
-                                   esp register.  */
-  long int signal;              /* Signal that caused the core dump. */
-  int reserved;                 /* No longer used */
-  unsigned long u_ar0;          /* Used by gdb to help find the values for */
-                                /* the registers. */
-  unsigned long magic;          /* To uniquely identify a core file */
-  char u_comm[32];              /* User command that was responsible */
-};
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif
diff --git a/include/asm-h8300/virtconvert.h b/include/asm-h8300/virtconvert.h
deleted file mode 100644
index 19cfd62b11c3..000000000000
--- a/include/asm-h8300/virtconvert.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __H8300_VIRT_CONVERT__
-#define __H8300_VIRT_CONVERT__
-
-/*
- * Macros used for converting between virtual and physical mappings.
- */
-
-#ifdef __KERNEL__
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-#endif
-#endif
diff --git a/include/asm-mips/kexec.h b/include/asm-mips/kexec.h
index cdbab43b7d3a..4314892aaebb 100644
--- a/include/asm-mips/kexec.h
+++ b/include/asm-mips/kexec.h
@@ -16,7 +16,7 @@
  /* Maximum address we can use for the control code buffer */
 #define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
 
-#define KEXEC_CONTROL_CODE_SIZE 4096
+#define KEXEC_CONTROL_PAGE_SIZE 4096
 
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_MIPS
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
index 4964c82f85f9..a73e1531e151 100644
--- a/include/asm-mips/unistd.h
+++ b/include/asm-mips/unistd.h
@@ -344,16 +344,22 @@
 #define __NR_timerfd_create             (__NR_Linux + 321)
 #define __NR_timerfd_gettime            (__NR_Linux + 322)
 #define __NR_timerfd_settime            (__NR_Linux + 323)
+#define __NR_signalfd4                  (__NR_Linux + 324)
+#define __NR_eventfd2                   (__NR_Linux + 325)
+#define __NR_epoll_create1              (__NR_Linux + 326)
+#define __NR_dup3                       (__NR_Linux + 327)
+#define __NR_pipe2                      (__NR_Linux + 328)
+#define __NR_inotify_init1              (__NR_Linux + 329)
 
 /*
  * Offset of the last Linux o32 flavoured syscall
  */
-#define __NR_Linux_syscalls             323
+#define __NR_Linux_syscalls             329
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
 
 #define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         323
+#define __NR_O32_Linux_syscalls         329
 
 #if _MIPS_SIM == _MIPS_SIM_ABI64
 
@@ -644,16 +650,22 @@
 #define __NR_timerfd_create             (__NR_Linux + 280)
 #define __NR_timerfd_gettime            (__NR_Linux + 281)
 #define __NR_timerfd_settime            (__NR_Linux + 282)
+#define __NR_signalfd4                  (__NR_Linux + 283)
+#define __NR_eventfd2                   (__NR_Linux + 284)
+#define __NR_epoll_create1              (__NR_Linux + 285)
+#define __NR_dup3                       (__NR_Linux + 286)
+#define __NR_pipe2                      (__NR_Linux + 287)
+#define __NR_inotify_init1              (__NR_Linux + 288)
 
 /*
  * Offset of the last Linux 64-bit flavoured syscall
  */
-#define __NR_Linux_syscalls             282
+#define __NR_Linux_syscalls             288
 
 #endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
 
 #define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          282
+#define __NR_64_Linux_syscalls          288
 
 #if _MIPS_SIM == _MIPS_SIM_NABI32
 
@@ -948,16 +960,22 @@
 #define __NR_timerfd_create             (__NR_Linux + 284)
 #define __NR_timerfd_gettime            (__NR_Linux + 285)
 #define __NR_timerfd_settime            (__NR_Linux + 286)
+#define __NR_signalfd4                  (__NR_Linux + 287)
+#define __NR_eventfd2                   (__NR_Linux + 288)
+#define __NR_epoll_create1              (__NR_Linux + 289)
+#define __NR_dup3                       (__NR_Linux + 290)
+#define __NR_pipe2                      (__NR_Linux + 291)
+#define __NR_inotify_init1              (__NR_Linux + 292)
 
 /*
  * Offset of the last N32 flavoured syscall
  */
-#define __NR_Linux_syscalls             286
+#define __NR_Linux_syscalls             292
 
 #endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
 
 #define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         286
+#define __NR_N32_Linux_syscalls         292
 
 #ifdef __KERNEL__
 
diff --git a/include/asm-mn10300/io.h b/include/asm-mn10300/io.h
index b8b6dc878250..c1a4119e6497 100644
--- a/include/asm-mn10300/io.h
+++ b/include/asm-mn10300/io.h
@@ -259,6 +259,8 @@ static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
         return (void *) (offset | 0x20000000);
 }
 
+#define ioremap_wc ioremap_nocache
+
 static inline void iounmap(void *addr)
 {
 }
diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
index 22aa58ca1991..dcc812067394 100644
--- a/include/asm-x86/amd_iommu_types.h
+++ b/include/asm-x86/amd_iommu_types.h
@@ -31,9 +31,6 @@
 #define ALIAS_TABLE_ENTRY_SIZE          2
 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
 
-/* helper macros */
-#define LOW_U32(x) ((x) & ((1ULL << 32)-1))
-
 /* Length of the MMIO region for the AMD IOMMU */
 #define MMIO_REGION_LENGTH       0x4000
 
@@ -69,6 +66,9 @@
 #define MMIO_EVT_TAIL_OFFSET    0x2018
 #define MMIO_STATUS_OFFSET      0x2020
 
+/* MMIO status bits */
+#define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
+
 /* feature control bits */
 #define CONTROL_IOMMU_EN        0x00ULL
 #define CONTROL_HT_TUN_EN       0x01ULL
@@ -89,6 +89,7 @@
 #define CMD_INV_IOMMU_PAGES     0x03
 
 #define CMD_COMPL_WAIT_STORE_MASK       0x01
+#define CMD_COMPL_WAIT_INT_MASK         0x02
 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 
@@ -99,6 +100,7 @@
 #define DEV_ENTRY_TRANSLATION   0x01
 #define DEV_ENTRY_IR            0x3d
 #define DEV_ENTRY_IW            0x3e
+#define DEV_ENTRY_NO_PAGE_FAULT 0x62
 #define DEV_ENTRY_EX            0x67
 #define DEV_ENTRY_SYSMGT1       0x68
 #define DEV_ENTRY_SYSMGT2       0x69
diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h
index a0095191c02e..91c7d03e65bc 100644
--- a/include/asm-x86/atomic_64.h
+++ b/include/asm-x86/atomic_64.h
@@ -228,7 +228,7 @@ static inline void atomic64_add(long i, atomic64_t *v)
 {
         asm volatile(LOCK_PREFIX "addq %1,%0"
                      : "=m" (v->counter)
-                     : "ir" (i), "m" (v->counter));
+                     : "er" (i), "m" (v->counter));
 }
 
 /**
@@ -242,7 +242,7 @@ static inline void atomic64_sub(long i, atomic64_t *v)
 {
         asm volatile(LOCK_PREFIX "subq %1,%0"
                      : "=m" (v->counter)
-                     : "ir" (i), "m" (v->counter));
+                     : "er" (i), "m" (v->counter));
 }
 
 /**
@@ -260,7 +260,7 @@ static inline int atomic64_sub_and_test(long i, atomic64_t *v)
 
         asm volatile(LOCK_PREFIX "subq %2,%0; sete %1"
                      : "=m" (v->counter), "=qm" (c)
-                     : "ir" (i), "m" (v->counter) : "memory");
+                     : "er" (i), "m" (v->counter) : "memory");
         return c;
 }
 
@@ -341,7 +341,7 @@ static inline int atomic64_add_negative(long i, atomic64_t *v)
 
         asm volatile(LOCK_PREFIX "addq %2,%0; sets %1"
                      : "=m" (v->counter), "=qm" (c)
-                     : "ir" (i), "m" (v->counter) : "memory");
+                     : "er" (i), "m" (v->counter) : "memory");
         return c;
 }
 
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 2f5a792b0acc..762f6a6bc707 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -91,6 +91,7 @@
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_2      (4*32+20) /* Streaming SIMD Extensions-4.2 */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
 #define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
@@ -189,6 +190,7 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_gbpages         boot_cpu_has(X86_FEATURE_GBPAGES)
 #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 #define cpu_has_pat             boot_cpu_has(X86_FEATURE_PAT)
+#define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
 
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 # define cpu_has_invlpg         1
diff --git a/include/asm-x86/efi.h b/include/asm-x86/efi.h
index 7ed2bd7a7f51..d4f2b0abe929 100644
--- a/include/asm-x86/efi.h
+++ b/include/asm-x86/efi.h
@@ -86,7 +86,7 @@ extern u64 efi_call6(void *fp, u64 arg1, u64 arg2, u64 arg3,
         efi_call6((void *)(efi.systab->runtime->f), (u64)(a1), (u64)(a2), \
                   (u64)(a3), (u64)(a4), (u64)(a5), (u64)(a6))
 
-extern void *efi_ioremap(unsigned long addr, unsigned long size);
+extern void __iomem *efi_ioremap(unsigned long addr, unsigned long size);
 
 #endif /* CONFIG_X86_32 */
 
diff --git a/include/asm-x86/genapic_32.h b/include/asm-x86/genapic_32.h
index b02ea6e17de8..754d635f90ff 100644
--- a/include/asm-x86/genapic_32.h
+++ b/include/asm-x86/genapic_32.h
@@ -118,6 +118,7 @@ enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
 #define get_uv_system_type()            UV_NONE
 #define is_uv_system()                  0
 #define uv_wakeup_secondary(a, b)       1
+#define uv_system_init()                do {} while (0)
 
 
 #endif
diff --git a/include/asm-x86/genapic_64.h b/include/asm-x86/genapic_64.h
index 0f8504627c41..a47d63129135 100644
--- a/include/asm-x86/genapic_64.h
+++ b/include/asm-x86/genapic_64.h
@@ -42,6 +42,7 @@ extern int is_uv_system(void);
 extern struct genapic apic_x2apic_uv_x;
 DECLARE_PER_CPU(int, x2apic_extra_bits);
 extern void uv_cpu_init(void);
+extern void uv_system_init(void);
 extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip);
 
 extern void setup_apic_routing(void);
diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h
index bb06027fc83e..2c1cda0b8a86 100644
--- a/include/asm-x86/geode.h
+++ b/include/asm-x86/geode.h
@@ -50,6 +50,7 @@ extern int geode_get_dev_base(unsigned int dev);
 #define MSR_PIC_YSEL_HIGH       0x51400021
 #define MSR_PIC_ZSEL_LOW        0x51400022
 #define MSR_PIC_ZSEL_HIGH       0x51400023
+#define MSR_PIC_IRQM_LPC        0x51400025
 
 #define MSR_MFGPT_IRQ           0x51400028
 #define MSR_MFGPT_NR            0x51400029
@@ -237,7 +238,7 @@ static inline u16 geode_mfgpt_read(int timer, u16 reg)
 }
 
 extern int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable);
-extern int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable);
+extern int geode_mfgpt_set_irq(int timer, int cmp, int *irq, int enable);
 extern int geode_mfgpt_alloc_timer(int timer, int domain);
 
 #define geode_mfgpt_setup_irq(t, c, i) geode_mfgpt_set_irq((t), (c), (i), 1)
diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h
index 77ba51df5668..edd0b95f14d0 100644
--- a/include/asm-x86/hw_irq.h
+++ b/include/asm-x86/hw_irq.h
@@ -98,9 +98,17 @@ extern void (*const interrupt[NR_IRQS])(void);
 #else
 typedef int vector_irq_t[NR_VECTORS];
 DECLARE_PER_CPU(vector_irq_t, vector_irq);
-extern spinlock_t vector_lock;
 #endif
-extern void setup_vector_irq(int cpu);
+
+#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_X86_64)
+extern void lock_vector_lock(void);
+extern void unlock_vector_lock(void);
+extern void __setup_vector_irq(int cpu);
+#else
+static inline void lock_vector_lock(void) {}
+static inline void unlock_vector_lock(void) {}
+static inline void __setup_vector_irq(int cpu) {}
+#endif
 
 #endif /* !ASSEMBLY_ */
 
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index 96fa8449ff11..56d00e31aec0 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -13,6 +13,7 @@
 #include <linux/sched.h>
 #include <linux/kernel_stat.h>
 #include <linux/regset.h>
+#include <linux/hardirq.h>
 #include <asm/asm.h>
 #include <asm/processor.h>
 #include <asm/sigcontext.h>
@@ -62,8 +63,6 @@ static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
 #else
                      : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
 #endif
-        if (unlikely(err))
-                init_fpu(current);
         return err;
 }
 
@@ -236,6 +235,37 @@ static inline void kernel_fpu_end(void)
         preempt_enable();
 }
 
+/*
+ * Some instructions like VIA's padlock instructions generate a spurious
+ * DNA fault but don't modify SSE registers. And these instructions
+ * get used from interrupt context aswell. To prevent these kernel instructions
+ * in interrupt context interact wrongly with other user/kernel fpu usage, we
+ * should use them only in the context of irq_ts_save/restore()
+ */
+static inline int irq_ts_save(void)
+{
+        /*
+         * If we are in process context, we are ok to take a spurious DNA fault.
+         * Otherwise, doing clts() in process context require pre-emption to
+         * be disabled or some heavy lifting like kernel_fpu_begin()
+         */
+        if (!in_interrupt())
+                return 0;
+
+        if (read_cr0() & X86_CR0_TS) {
+                clts();
+                return 1;
+        }
+
+        return 0;
+}
+
+static inline void irq_ts_restore(int TS_state)
+{
+        if (TS_state)
+                stts();
+}
+
 #ifdef CONFIG_X86_64
 
 static inline void save_init_fpu(struct task_struct *tsk)
diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h
index bf5d629b3a39..0f954dc89cb3 100644
--- a/include/asm-x86/io.h
+++ b/include/asm-x86/io.h
@@ -21,7 +21,7 @@ extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
 
 #define build_mmio_read(name, size, type, reg, barrier) \
 static inline type name(const volatile void __iomem *addr) \
-{ type ret; asm volatile("mov" size " %1,%0":"=" reg (ret) \
+{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
 :"m" (*(volatile type __force *)addr) barrier); return ret; }
 
 #define build_mmio_write(name, size, type, reg, barrier) \
@@ -29,13 +29,13 @@ static inline void name(type val, volatile void __iomem *addr) \
 { asm volatile("mov" size " %0,%1": :reg (val), \
 "m" (*(volatile type __force *)addr) barrier); }
 
-build_mmio_read(readb, "b", unsigned char, "q", :"memory")
-build_mmio_read(readw, "w", unsigned short, "r", :"memory")
-build_mmio_read(readl, "l", unsigned int, "r", :"memory")
+build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
+build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
+build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
 
-build_mmio_read(__readb, "b", unsigned char, "q", )
-build_mmio_read(__readw, "w", unsigned short, "r", )
-build_mmio_read(__readl, "l", unsigned int, "r", )
+build_mmio_read(__readb, "b", unsigned char, "=q", )
+build_mmio_read(__readw, "w", unsigned short, "=r", )
+build_mmio_read(__readl, "l", unsigned int, "=r", )
 
 build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
 build_mmio_write(writew, "w", unsigned short, "r", :"memory")
@@ -59,8 +59,8 @@ build_mmio_write(__writel, "l", unsigned int, "r", )
 #define mmiowb() barrier()
 
 #ifdef CONFIG_X86_64
-build_mmio_read(readq, "q", unsigned long, "r", :"memory")
-build_mmio_read(__readq, "q", unsigned long, "r", )
+build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
+build_mmio_read(__readq, "q", unsigned long, "=r", )
 build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
 build_mmio_write(__writeq, "q", unsigned long, "r", )
 
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
index 90b1d1f12f08..a48c7f2dbdc0 100644
--- a/include/asm-x86/irq_vectors.h
+++ b/include/asm-x86/irq_vectors.h
@@ -76,6 +76,7 @@
 #define CALL_FUNCTION_SINGLE_VECTOR     0xfb
 #define THERMAL_APIC_VECTOR             0xfa
 #define THRESHOLD_APIC_VECTOR           0xf9
+#define UV_BAU_MESSAGE                  0xf8
 #define INVALIDATE_TLB_VECTOR_END       0xf7
 #define INVALIDATE_TLB_VECTOR_START     0xf0    /* f0-f7 used for TLB flush */
 
@@ -109,7 +110,15 @@
 #define LAST_VM86_IRQ           15
 #define invalid_vm86_irq(irq)   ((irq) < 3 || (irq) > 15)
 
-#if !defined(CONFIG_X86_VOYAGER)
+#ifdef CONFIG_X86_64
+# if NR_CPUS < MAX_IO_APICS
+#  define NR_IRQS (NR_VECTORS + (32 * NR_CPUS))
+# else
+#  define NR_IRQS (NR_VECTORS + (32 * MAX_IO_APICS))
+# endif
+# define NR_IRQ_VECTORS NR_IRQS
+
+#elif !defined(CONFIG_X86_VOYAGER)
 
 # if defined(CONFIG_X86_IO_APIC) || defined(CONFIG_PARAVIRT) || defined(CONFIG_X86_VISWS)
 
diff --git a/include/asm-x86/kexec.h b/include/asm-x86/kexec.h
index c0e52a14fd4d..4246ab7dc988 100644
--- a/include/asm-x86/kexec.h
+++ b/include/asm-x86/kexec.h
@@ -41,6 +41,10 @@
 # define PAGES_NR               17
 #endif
 
+#ifdef CONFIG_X86_32
+# define KEXEC_CONTROL_CODE_MAX_SIZE    2048
+#endif
+
 #ifndef __ASSEMBLY__
 
 #include <linux/string.h>
@@ -63,7 +67,7 @@
 /* Maximum address we can use for the control code buffer */
 # define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
 
-# define KEXEC_CONTROL_CODE_SIZE        4096
+# define KEXEC_CONTROL_PAGE_SIZE        4096
 
 /* The native architecture */
 # define KEXEC_ARCH KEXEC_ARCH_386
@@ -79,7 +83,7 @@
 # define KEXEC_CONTROL_MEMORY_LIMIT     (0xFFFFFFFFFFUL)
 
 /* Allocate one page for the pdp and the second for the code */
-# define KEXEC_CONTROL_CODE_SIZE  (4096UL + 4096UL)
+# define KEXEC_CONTROL_PAGE_SIZE  (4096UL + 4096UL)
 
 /* The native architecture */
 # define KEXEC_ARCH KEXEC_ARCH_X86_64
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 0f3c53114614..c2e34c275900 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -722,7 +722,7 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
 
 #define __kvm_handle_fault_on_reboot(insn) \
         "666: " insn "\n\t" \
-        ".pushsection .text.fixup, \"ax\" \n" \
+        ".pushsection .fixup, \"ax\" \n" \
         "667: \n\t" \
         KVM_EX_PUSH " $666b \n\t" \
         "jmp kvm_handle_fault_on_reboot \n\t" \
diff --git a/include/asm-x86/mce.h b/include/asm-x86/mce.h
index 94f1fd79e22a..531eaa587455 100644
--- a/include/asm-x86/mce.h
+++ b/include/asm-x86/mce.h
@@ -92,6 +92,7 @@ extern int mce_disabled;
 
 void mce_log(struct mce *m);
 DECLARE_PER_CPU(struct sys_device, device_mce);
+extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 
 #ifdef CONFIG_X86_MCE_INTEL
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
diff --git a/include/asm-x86/mman.h b/include/asm-x86/mman.h
index c1682b542daf..90bc4108a4fd 100644
--- a/include/asm-x86/mman.h
+++ b/include/asm-x86/mman.h
@@ -12,6 +12,7 @@
 #define MAP_NORESERVE   0x4000          /* don't check for reservations */
 #define MAP_POPULATE    0x8000          /* populate (prefault) pagetables */
 #define MAP_NONBLOCK    0x10000         /* do not block on IO */
+#define MAP_STACK       0x20000         /* give out an address that is best suited for process/thread stacks */
 
 #define MCL_CURRENT     1               /* lock all current mappings */
 #define MCL_FUTURE      2               /* lock all future mappings */
diff --git a/include/asm-x86/mmconfig.h b/include/asm-x86/mmconfig.h
index 95beda07c6fa..e293ab81e850 100644
--- a/include/asm-x86/mmconfig.h
+++ b/include/asm-x86/mmconfig.h
@@ -3,7 +3,7 @@
 
 #ifdef CONFIG_PCI_MMCONFIG
 extern void __cpuinit fam10h_check_enable_mmcfg(void);
-extern void __init check_enable_amd_mmconf_dmi(void);
+extern void __cpuinit check_enable_amd_mmconf_dmi(void);
 #else
 static inline void fam10h_check_enable_mmcfg(void) { }
 static inline void check_enable_amd_mmconf_dmi(void) { }
diff --git a/include/asm-x86/mmzone_32.h b/include/asm-x86/mmzone_32.h
index b2298a227567..5862e6460658 100644
--- a/include/asm-x86/mmzone_32.h
+++ b/include/asm-x86/mmzone_32.h
@@ -97,10 +97,16 @@ static inline int pfn_valid(int pfn)
         reserve_bootmem_node(NODE_DATA(0), (addr), (size), (flags))
 #define alloc_bootmem(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_nopanic(x) \
+        __alloc_bootmem_node_nopanic(NODE_DATA(0), (x), SMP_CACHE_BYTES, \
+                                __pa(MAX_DMA_ADDRESS))
 #define alloc_bootmem_low(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), SMP_CACHE_BYTES, 0)
 #define alloc_bootmem_pages(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_pages_nopanic(x) \
+        __alloc_bootmem_node_nopanic(NODE_DATA(0), (x), PAGE_SIZE, \
+                                __pa(MAX_DMA_ADDRESS))
 #define alloc_bootmem_low_pages(x) \
         __alloc_bootmem_node(NODE_DATA(0), (x), PAGE_SIZE, 0)
 #define alloc_bootmem_node(pgdat, x)                                    \
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index ca110ee73f07..2362cfda1fbc 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -52,14 +52,14 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
 {
         DECLARE_ARGS(val, low, high);
 
-        asm volatile("2: rdmsr ; xor %0,%0\n"
+        asm volatile("2: rdmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %3,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=r" (*err), EAX_EDX_RET(val, low, high)
-                     : "c" (msr), "i" (-EFAULT));
+                     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
+                     : "c" (msr), [fault] "i" (-EFAULT));
         return EAX_EDX_VAL(val, low, high);
 }
 
@@ -73,15 +73,15 @@ static inline int native_write_msr_safe(unsigned int msr,
                                         unsigned low, unsigned high)
 {
         int err;
-        asm volatile("2: wrmsr ; xor %0,%0\n"
+        asm volatile("2: wrmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %4,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=a" (err)
+                     : [err] "=a" (err)
                      : "c" (msr), "0" (low), "d" (high),
-                       "i" (-EFAULT)
+                       [fault] "i" (-EFAULT)
                      : "memory");
         return err;
 }
@@ -192,19 +192,20 @@ do {                                                            \
 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
 
 #ifdef CONFIG_SMP
-void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-
 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 #else  /*  CONFIG_SMP  */
-static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
         rdmsr(msr_no, *l, *h);
+        return 0;
 }
-static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
         wrmsr(msr_no, l, h);
+        return 0;
 }
 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
                                     u32 *l, u32 *h)
diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h
index 4e91ee1e37aa..f643a3a92da0 100644
--- a/include/asm-x86/percpu.h
+++ b/include/asm-x86/percpu.h
@@ -182,7 +182,7 @@ do {							\
         DEFINE_PER_CPU(_type, _name) = _initvalue;                      \
         __typeof__(_type) _name##_early_map[NR_CPUS] __initdata =       \
                                 { [0 ... NR_CPUS-1] = _initvalue };     \
-        __typeof__(_type) *_name##_early_ptr = _name##_early_map
+        __typeof__(_type) *_name##_early_ptr __refdata = _name##_early_map
 
 #define EXPORT_EARLY_PER_CPU_SYMBOL(_name)                      \
         EXPORT_PER_CPU_SYMBOL(_name)
diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
index ac5fff4cc58a..549144d03d99 100644
--- a/include/asm-x86/pgtable_64.h
+++ b/include/asm-x86/pgtable_64.h
@@ -151,7 +151,7 @@ static inline void native_pgd_clear(pgd_t *pgd)
 #define VMALLOC_END      _AC(0xffffe1ffffffffff, UL)
 #define VMEMMAP_START    _AC(0xffffe20000000000, UL)
 #define MODULES_VADDR    _AC(0xffffffffa0000000, UL)
-#define MODULES_END      _AC(0xfffffffffff00000, UL)
+#define MODULES_END      _AC(0xffffffffff000000, UL)
 #define MODULES_LEN   (MODULES_END - MODULES_VADDR)
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 5f58da401b43..4df3e2f6fb56 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -728,6 +728,29 @@ extern unsigned long		boot_option_idle_override;
 extern unsigned long            idle_halt;
 extern unsigned long            idle_nomwait;
 
+/*
+ * on systems with caches, caches must be flashed as the absolute
+ * last instruction before going into a suspended halt.  Otherwise,
+ * dirty data can linger in the cache and become stale on resume,
+ * leading to strange errors.
+ *
+ * perform a variety of operations to guarantee that the compiler
+ * will not reorder instructions.  wbinvd itself is serializing
+ * so the processor will not reorder.
+ *
+ * Systems without cache can just go into halt.
+ */
+static inline void wbinvd_halt(void)
+{
+        mb();
+        /* check for clflush to determine if wbinvd is legal */
+        if (cpu_has_clflush)
+                asm volatile("cli; wbinvd; 1: hlt; jmp 1b" : : : "memory");
+        else
+                while (1)
+                        halt();
+}
+
 extern void enable_sep_cpu(void);
 extern int sysenter_setup(void);
 
diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h
index 4f9a9861799a..e39c790dbfd2 100644
--- a/include/asm-x86/spinlock.h
+++ b/include/asm-x86/spinlock.h
@@ -65,7 +65,7 @@ static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->slock);
 
-        return (((tmp >> 8) & 0xff) - (tmp & 0xff)) > 1;
+        return (((tmp >> 8) - tmp) & 0xff) > 1;
 }
 
 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
@@ -127,7 +127,7 @@ static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
 {
         int tmp = ACCESS_ONCE(lock->slock);
 
-        return (((tmp >> 16) & 0xffff) - (tmp & 0xffff)) > 1;
+        return (((tmp >> 16) - tmp) & 0xffff) > 1;
 }
 
 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
diff --git a/include/asm-x86/uv/uv_bau.h b/include/asm-x86/uv/uv_bau.h
index 91ac0dfb7588..610b6b308e93 100644
--- a/include/asm-x86/uv/uv_bau.h
+++ b/include/asm-x86/uv/uv_bau.h
@@ -40,11 +40,6 @@
 #define UV_ACTIVATION_DESCRIPTOR_SIZE   32
 #define UV_DISTRIBUTION_SIZE            256
 #define UV_SW_ACK_NPENDING              8
-#define UV_BAU_MESSAGE                  200
-/*
- * Messaging irq; see irq_64.h and include/asm-x86/hw_irq_64.h
- * To be dynamically allocated in the future
- */
 #define UV_NET_ENDPOINT_INTD            0x38
 #define UV_DESC_BASE_PNODE_SHIFT        49
 #define UV_PAYLOADQ_PNODE_SHIFT         49
diff --git a/include/asm-x86/xen/hypervisor.h b/include/asm-x86/xen/hypervisor.h
index 8e15dd28c91f..04ee0610014a 100644
--- a/include/asm-x86/xen/hypervisor.h
+++ b/include/asm-x86/xen/hypervisor.h
@@ -35,7 +35,6 @@
 
 #include <linux/types.h>
 #include <linux/kernel.h>
-#include <linux/version.h>
 
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>
diff --git a/include/crypto/hash.h b/include/crypto/hash.h
index d12498ec8a4e..ee48ef8fb2ea 100644
--- a/include/crypto/hash.h
+++ b/include/crypto/hash.h
@@ -101,6 +101,24 @@ static inline int crypto_ahash_digest(struct ahash_request *req)
         return crt->digest(req);
 }
 
+static inline int crypto_ahash_init(struct ahash_request *req)
+{
+        struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req));
+        return crt->init(req);
+}
+
+static inline int crypto_ahash_update(struct ahash_request *req)
+{
+        struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req));
+        return crt->update(req);
+}
+
+static inline int crypto_ahash_final(struct ahash_request *req)
+{
+        struct ahash_tfm *crt = crypto_ahash_crt(crypto_ahash_reqtfm(req));
+        return crt->final(req);
+}
+
 static inline void ahash_request_set_tfm(struct ahash_request *req,
                                          struct crypto_ahash *tfm)
 {
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index a26f565e8189..7d970678f940 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -250,6 +250,8 @@ unifdef-y += isdn.h
 unifdef-y += isdnif.h
 unifdef-y += isdn_divertif.h
 unifdef-y += isdn_ppp.h
+unifdef-y += ivtv.h
+unifdef-y += ivtvfb.h
 unifdef-y += joystick.h
 unifdef-y += kdev_t.h
 unifdef-y += kd.h
@@ -356,6 +358,7 @@ unifdef-y += virtio_balloon.h
 unifdef-y += virtio_console.h
 unifdef-y += virtio_pci.h
 unifdef-y += virtio_ring.h
+unifdef-y += virtio_rng.h
 unifdef-y += vt.h
 unifdef-y += wait.h
 unifdef-y += wanrouter.h
diff --git a/include/linux/agp_backend.h b/include/linux/agp_backend.h
index 972b12bcfb36..2b8df8b420fd 100644
--- a/include/linux/agp_backend.h
+++ b/include/linux/agp_backend.h
@@ -30,6 +30,8 @@
 #ifndef _AGP_BACKEND_H
 #define _AGP_BACKEND_H 1
 
+#include <linux/list.h>
+
 enum chipset_type {
         NOT_SUPPORTED,
         SUPPORTED,
@@ -78,6 +80,8 @@ struct agp_memory {
         bool is_bound;
         bool is_flushed;
         bool vmalloc_flag;
+        /* list of agp_memory mapped to the aperture */
+        struct list_head mapped_list;
 };
 
 #define AGP_NORMAL_MEMORY 0
@@ -96,6 +100,7 @@ extern struct agp_memory *agp_allocate_memory(struct agp_bridge_data *, size_t,
 extern int agp_copy_info(struct agp_bridge_data *, struct agp_kern_info *);
 extern int agp_bind_memory(struct agp_memory *, off_t);
 extern int agp_unbind_memory(struct agp_memory *);
+extern int agp_rebind_memory(void);
 extern void agp_enable(struct agp_bridge_data *, u32);
 extern struct agp_bridge_data *agp_backend_acquire(struct pci_dev *);
 extern void agp_backend_release(struct agp_bridge_data *);
diff --git a/include/linux/ata.h b/include/linux/ata.h
index 1c622e2b0504..1ce19c1ef0e9 100644
--- a/include/linux/ata.h
+++ b/include/linux/ata.h
@@ -46,18 +46,48 @@ enum {
         ATA_MAX_SECTORS_TAPE    = 65535,
 
         ATA_ID_WORDS            = 256,
+        ATA_ID_CONFIG           = 0,
+        ATA_ID_CYLS             = 1,
+        ATA_ID_HEADS            = 3,
+        ATA_ID_SECTORS          = 6,
         ATA_ID_SERNO            = 10,
+        ATA_ID_BUF_SIZE         = 21,
         ATA_ID_FW_REV           = 23,
         ATA_ID_PROD             = 27,
+        ATA_ID_MAX_MULTSECT     = 47,
+        ATA_ID_DWORD_IO         = 48,
+        ATA_ID_CAPABILITY       = 49,
         ATA_ID_OLD_PIO_MODES    = 51,
+        ATA_ID_OLD_DMA_MODES    = 52,
         ATA_ID_FIELD_VALID      = 53,
+        ATA_ID_CUR_CYLS         = 54,
+        ATA_ID_CUR_HEADS        = 55,
+        ATA_ID_CUR_SECTORS      = 56,
+        ATA_ID_MULTSECT         = 59,
+        ATA_ID_LBA_CAPACITY     = 60,
+        ATA_ID_SWDMA_MODES      = 62,
         ATA_ID_MWDMA_MODES      = 63,
         ATA_ID_PIO_MODES        = 64,
         ATA_ID_EIDE_DMA_MIN     = 65,
+        ATA_ID_EIDE_DMA_TIME    = 66,
         ATA_ID_EIDE_PIO         = 67,
         ATA_ID_EIDE_PIO_IORDY   = 68,
-        ATA_ID_UDMA_MODES       = 88,
+        ATA_ID_QUEUE_DEPTH      = 75,
         ATA_ID_MAJOR_VER        = 80,
+        ATA_ID_COMMAND_SET_1    = 82,
+        ATA_ID_COMMAND_SET_2    = 83,
+        ATA_ID_CFSSE            = 84,
+        ATA_ID_CFS_ENABLE_1     = 85,
+        ATA_ID_CFS_ENABLE_2     = 86,
+        ATA_ID_CSF_DEFAULT      = 87,
+        ATA_ID_UDMA_MODES       = 88,
+        ATA_ID_HW_CONFIG        = 93,
+        ATA_ID_SPG              = 98,
+        ATA_ID_LBA_CAPACITY_2   = 100,
+        ATA_ID_LAST_LUN         = 126,
+        ATA_ID_DLF              = 128,
+        ATA_ID_CSFO             = 129,
+        ATA_ID_CFA_POWER        = 160,
         ATA_ID_PIO4             = (1 << 1),
 
         ATA_ID_SERNO_LEN        = 20,
@@ -123,13 +153,26 @@ enum {
         ATA_BUSY                = (1 << 7),     /* BSY status bit */
         ATA_DRDY                = (1 << 6),     /* device ready */
         ATA_DF                  = (1 << 5),     /* device fault */
+        ATA_DSC                 = (1 << 4),     /* drive seek complete */
         ATA_DRQ                 = (1 << 3),     /* data request i/o */
+        ATA_CORR                = (1 << 2),     /* corrected data error */
+        ATA_IDX                 = (1 << 1),     /* index */
         ATA_ERR                 = (1 << 0),     /* have an error */
         ATA_SRST                = (1 << 2),     /* software reset */
         ATA_ICRC                = (1 << 7),     /* interface CRC error */
+        ATA_BBK                 = ATA_ICRC,     /* pre-EIDE: block marked bad */
         ATA_UNC                 = (1 << 6),     /* uncorrectable media error */
+        ATA_MC                  = (1 << 5),     /* media changed */
         ATA_IDNF                = (1 << 4),     /* ID not found */
+        ATA_MCR                 = (1 << 3),     /* media change requested */
         ATA_ABORTED             = (1 << 2),     /* command aborted */
+        ATA_TRK0NF              = (1 << 1),     /* track 0 not found */
+        ATA_AMNF                = (1 << 0),     /* address mark not found */
+        ATAPI_LFS               = 0xF0,         /* last failed sense */
+        ATAPI_EOM               = ATA_TRK0NF,   /* end of media */
+        ATAPI_ILI               = ATA_AMNF,     /* illegal length indication */
+        ATAPI_IO                = (1 << 1),
+        ATAPI_COD               = (1 << 0),
 
         /* ATA command block registers */
         ATA_REG_DATA            = 0x00,
@@ -192,6 +235,13 @@ enum {
         ATA_CMD_PMP_WRITE       = 0xE8,
         ATA_CMD_CONF_OVERLAY    = 0xB1,
         ATA_CMD_SEC_FREEZE_LOCK = 0xF5,
+        ATA_CMD_SMART           = 0xB0,
+        ATA_CMD_MEDIA_LOCK      = 0xDE,
+        ATA_CMD_MEDIA_UNLOCK    = 0xDF,
+        /* marked obsolete in the ATA/ATAPI-7 spec */
+        ATA_CMD_RESTORE         = 0x10,
+        /* EXABYTE specific */
+        ATA_EXABYTE_ENABLE_NEST = 0xF0,
 
         /* READ_LOG_EXT pages */
         ATA_LOG_SATA_NCQ        = 0x10,
@@ -232,6 +282,10 @@ enum {
         SETFEATURES_WC_ON       = 0x02, /* Enable write cache */
         SETFEATURES_WC_OFF      = 0x82, /* Disable write cache */
 
+        /* Enable/Disable Automatic Acoustic Management */
+        SETFEATURES_AAM_ON      = 0x42,
+        SETFEATURES_AAM_OFF     = 0xC2,
+
         SETFEATURES_SPINUP      = 0x07, /* Spin-up drive */
 
         SETFEATURES_SATA_ENABLE = 0x10, /* Enable use of SATA feature */
@@ -254,6 +308,15 @@ enum {
         ATA_DCO_IDENTIFY        = 0xC2,
         ATA_DCO_SET             = 0xC3,
 
+        /* feature values for SMART */
+        ATA_SMART_ENABLE        = 0xD8,
+        ATA_SMART_READ_VALUES   = 0xD0,
+        ATA_SMART_READ_THRESHOLDS = 0xD1,
+
+        /* password used in LBA Mid / LBA High for executing SMART commands */
+        ATA_SMART_LBAM_PASS     = 0x4F,
+        ATA_SMART_LBAH_PASS     = 0xC2,
+
         /* ATAPI stuff */
         ATAPI_PKT_DMA           = (1 << 0),
         ATAPI_DMADIR            = (1 << 2),     /* ATAPI data dir:
@@ -438,17 +501,17 @@ static inline int ata_is_data(u8 prot)
 /*
  * id tests
  */
-#define ata_id_is_ata(id)       (((id)[0] & (1 << 15)) == 0)
-#define ata_id_has_lba(id)      ((id)[49] & (1 << 9))
-#define ata_id_has_dma(id)      ((id)[49] & (1 << 8))
+#define ata_id_is_ata(id)       (((id)[ATA_ID_CONFIG] & (1 << 15)) == 0)
+#define ata_id_has_lba(id)      ((id)[ATA_ID_CAPABILITY] & (1 << 9))
+#define ata_id_has_dma(id)      ((id)[ATA_ID_CAPABILITY] & (1 << 8))
 #define ata_id_has_ncq(id)      ((id)[76] & (1 << 8))
-#define ata_id_queue_depth(id)  (((id)[75] & 0x1f) + 1)
-#define ata_id_removeable(id)   ((id)[0] & (1 << 7))
+#define ata_id_queue_depth(id)  (((id)[ATA_ID_QUEUE_DEPTH] & 0x1f) + 1)
+#define ata_id_removeable(id)   ((id)[ATA_ID_CONFIG] & (1 << 7))
 #define ata_id_has_atapi_AN(id) \
         ( (((id)[76] != 0x0000) && ((id)[76] != 0xffff)) && \
           ((id)[78] & (1 << 5)) )
-#define ata_id_iordy_disable(id) ((id)[49] & (1 << 10))
-#define ata_id_has_iordy(id) ((id)[49] & (1 << 11))
+#define ata_id_iordy_disable(id) ((id)[ATA_ID_CAPABILITY] & (1 << 10))
+#define ata_id_has_iordy(id) ((id)[ATA_ID_CAPABILITY] & (1 << 11))
 #define ata_id_u32(id,n)        \
         (((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
 #define ata_id_u64(id,n)        \
@@ -457,7 +520,7 @@ static inline int ata_is_data(u8 prot)
           ((u64) (id)[(n) + 1] << 16) | \
           ((u64) (id)[(n) + 0]) )
 
-#define ata_id_cdb_intr(id)     (((id)[0] & 0x60) == 0x20)
+#define ata_id_cdb_intr(id)     (((id)[ATA_ID_CONFIG] & 0x60) == 0x20)
 
 static inline bool ata_id_has_hipm(const u16 *id)
 {
@@ -482,75 +545,75 @@ static inline bool ata_id_has_dipm(const u16 *id)
 
 static inline int ata_id_has_fua(const u16 *id)
 {
-        if ((id[84] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_CFSSE] & 0xC000) != 0x4000)
                 return 0;
-        return id[84] & (1 << 6);
+        return id[ATA_ID_CFSSE] & (1 << 6);
 }
 
 static inline int ata_id_has_flush(const u16 *id)
 {
-        if ((id[83] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
                 return 0;
-        return id[83] & (1 << 12);
+        return id[ATA_ID_COMMAND_SET_2] & (1 << 12);
 }
 
 static inline int ata_id_has_flush_ext(const u16 *id)
 {
-        if ((id[83] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
                 return 0;
-        return id[83] & (1 << 13);
+        return id[ATA_ID_COMMAND_SET_2] & (1 << 13);
 }
 
 static inline int ata_id_has_lba48(const u16 *id)
 {
-        if ((id[83] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
                 return 0;
-        if (!ata_id_u64(id, 100))
+        if (!ata_id_u64(id, ATA_ID_LBA_CAPACITY_2))
                 return 0;
-        return id[83] & (1 << 10);
+        return id[ATA_ID_COMMAND_SET_2] & (1 << 10);
 }
 
 static inline int ata_id_hpa_enabled(const u16 *id)
 {
         /* Yes children, word 83 valid bits cover word 82 data */
-        if ((id[83] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
                 return 0;
         /* And 87 covers 85-87 */
-        if ((id[87] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
                 return 0;
         /* Check command sets enabled as well as supported */
-        if ((id[85] & ( 1 << 10)) == 0)
+        if ((id[ATA_ID_CFS_ENABLE_1] & (1 << 10)) == 0)
                 return 0;
-        return id[82] & (1 << 10);
+        return id[ATA_ID_COMMAND_SET_1] & (1 << 10);
 }
 
 static inline int ata_id_has_wcache(const u16 *id)
 {
         /* Yes children, word 83 valid bits cover word 82 data */
-        if ((id[83] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
                 return 0;
-        return id[82] & (1 << 5);
+        return id[ATA_ID_COMMAND_SET_1] & (1 << 5);
 }
 
 static inline int ata_id_has_pm(const u16 *id)
 {
-        if ((id[83] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
                 return 0;
-        return id[82] & (1 << 3);
+        return id[ATA_ID_COMMAND_SET_1] & (1 << 3);
 }
 
 static inline int ata_id_rahead_enabled(const u16 *id)
 {
-        if ((id[87] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
                 return 0;
-        return id[85] & (1 << 6);
+        return id[ATA_ID_CFS_ENABLE_1] & (1 << 6);
 }
 
 static inline int ata_id_wcache_enabled(const u16 *id)
 {
-        if ((id[87] & 0xC000) != 0x4000)
+        if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
                 return 0;
-        return id[85] & (1 << 5);
+        return id[ATA_ID_CFS_ENABLE_1] & (1 << 5);
 }
 
 /**
@@ -581,7 +644,7 @@ static inline unsigned int ata_id_major_version(const u16 *id)
 
 static inline int ata_id_is_sata(const u16 *id)
 {
-        return ata_id_major_version(id) >= 5 && id[93] == 0;
+        return ata_id_major_version(id) >= 5 && id[ATA_ID_HW_CONFIG] == 0;
 }
 
 static inline int ata_id_has_tpm(const u16 *id)
@@ -599,7 +662,7 @@ static inline int ata_id_has_dword_io(const u16 *id)
         /* ATA 8 reuses this flag for "trusted" computing */
         if (ata_id_major_version(id) > 7)
                 return 0;
-        if (id[48] & (1 << 0))
+        if (id[ATA_ID_DWORD_IO] & (1 << 0))
                 return 1;
         return 0;
 }
@@ -608,22 +671,22 @@ static inline int ata_id_current_chs_valid(const u16 *id)
 {
         /* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
            has not been issued to the device then the values of
-           id[54] to id[56] are vendor specific. */
-        return (id[53] & 0x01) && /* Current translation valid */
-                id[54] &&  /* cylinders in current translation */
-                id[55] &&  /* heads in current translation */
-                id[55] <= 16 &&
-                id[56];    /* sectors in current translation */
+           id[ATA_ID_CUR_CYLS] to id[ATA_ID_CUR_SECTORS] are vendor specific. */
+        return (id[ATA_ID_FIELD_VALID] & 1) && /* Current translation valid */
+                id[ATA_ID_CUR_CYLS] &&  /* cylinders in current translation */
+                id[ATA_ID_CUR_HEADS] &&  /* heads in current translation */
+                id[ATA_ID_CUR_HEADS] <= 16 &&
+                id[ATA_ID_CUR_SECTORS];    /* sectors in current translation */
 }
 
 static inline int ata_id_is_cfa(const u16 *id)
 {
-        u16 v = id[0];
-        if (v == 0x848A)        /* Standard CF */
+        if (id[ATA_ID_CONFIG] == 0x848A)        /* Standard CF */
                 return 1;
         /* Could be CF hiding as standard ATA */
-        if (ata_id_major_version(id) >= 3 &&  id[82] != 0xFFFF &&
-                        (id[82] & ( 1 << 2)))
+        if (ata_id_major_version(id) >= 3 &&
+            id[ATA_ID_COMMAND_SET_1] != 0xFFFF &&
+           (id[ATA_ID_COMMAND_SET_1] & (1 << 2)))
                 return 1;
         return 0;
 }
@@ -632,21 +695,21 @@ static inline int ata_drive_40wire(const u16 *dev_id)
 {
         if (ata_id_is_sata(dev_id))
                 return 0;       /* SATA */
-        if ((dev_id[93] & 0xE000) == 0x6000)
+        if ((dev_id[ATA_ID_HW_CONFIG] & 0xE000) == 0x6000)
                 return 0;       /* 80 wire */
         return 1;
 }
 
 static inline int ata_drive_40wire_relaxed(const u16 *dev_id)
 {
-        if ((dev_id[93] & 0x2000) == 0x2000)
+        if ((dev_id[ATA_ID_HW_CONFIG] & 0x2000) == 0x2000)
                 return 0;       /* 80 wire */
         return 1;
 }
 
 static inline int atapi_cdb_len(const u16 *dev_id)
 {
-        u16 tmp = dev_id[0] & 0x3;
+        u16 tmp = dev_id[ATA_ID_CONFIG] & 0x3;
         switch (tmp) {
         case 0:         return 12;
         case 1:         return 16;
@@ -656,7 +719,7 @@ static inline int atapi_cdb_len(const u16 *dev_id)
 
 static inline int atapi_command_packet_set(const u16 *dev_id)
 {
-        return (dev_id[0] >> 8) & 0x1f;
+        return (dev_id[ATA_ID_CONFIG] >> 8) & 0x1f;
 }
 
 static inline int atapi_id_dmadir(const u16 *dev_id)
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index 1abfe664c444..89781fd48859 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -110,6 +110,7 @@ extern int __bitmap_weight(const unsigned long *bitmap, int bits);
 
 extern int bitmap_scnprintf(char *buf, unsigned int len,
                         const unsigned long *src, int nbits);
+extern int bitmap_scnprintf_len(unsigned int nr_bits);
 extern int __bitmap_parse(const char *buf, unsigned int buflen, int is_user,
                         unsigned long *dst, int nbits);
 extern int bitmap_parse_user(const char __user *ubuf, unsigned int ulen,
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index e61f22be4d0e..44710d7e7bff 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -280,6 +280,15 @@ struct blk_queue_tag {
         atomic_t refcnt;                /* map can be shared */
 };
 
+#define BLK_SCSI_MAX_CMDS       (256)
+#define BLK_SCSI_CMD_PER_LONG   (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
+
+struct blk_cmd_filter {
+        unsigned long read_ok[BLK_SCSI_CMD_PER_LONG];
+        unsigned long write_ok[BLK_SCSI_CMD_PER_LONG];
+        struct kobject kobj;
+};
+
 struct request_queue
 {
         /*
@@ -398,6 +407,7 @@ struct request_queue
 #if defined(CONFIG_BLK_DEV_BSG)
         struct bsg_class_device bsg_dev;
 #endif
+        struct blk_cmd_filter cmd_filter;
 };
 
 #define QUEUE_FLAG_CLUSTER      0       /* cluster several segments into 1 */
@@ -807,8 +817,6 @@ extern void blk_put_queue(struct request_queue *);
 /*
  * tag stuff
  */
-#define blk_queue_tag_depth(q)          ((q)->queue_tags->busy)
-#define blk_queue_tag_queue(q)          ((q)->queue_tags->busy < (q)->queue_tags->max_depth)
 #define blk_rq_tagged(rq)               ((rq)->cmd_flags & REQ_QUEUED)
 extern int blk_queue_start_tag(struct request_queue *, struct request *);
 extern struct request *blk_queue_find_tag(struct request_queue *, int);
@@ -833,11 +841,11 @@ extern int blkdev_issue_flush(struct block_device *, sector_t *);
 /*
 * command filter functions
 */
-extern int blk_verify_command(struct file *file, unsigned char *cmd);
-extern int blk_cmd_filter_verify_command(struct blk_scsi_cmd_filter *filter,
-                                         unsigned char *cmd, mode_t *f_mode);
+extern int blk_verify_command(struct blk_cmd_filter *filter,
+                              unsigned char *cmd, int has_write_perm);
 extern int blk_register_filter(struct gendisk *disk);
 extern void blk_unregister_filter(struct gendisk *disk);
+extern void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter);
 
 #define MAX_PHYS_SEGMENTS 128
 #define MAX_HW_SEGMENTS 128
diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h
index 652470b687c9..95837bfb5256 100644
--- a/include/linux/bootmem.h
+++ b/include/linux/bootmem.h
@@ -97,10 +97,14 @@ extern void *__alloc_bootmem_low_node(pg_data_t *pgdat,
 #ifndef CONFIG_HAVE_ARCH_BOOTMEM_NODE
 #define alloc_bootmem(x) \
         __alloc_bootmem(x, SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_nopanic(x) \
+        __alloc_bootmem_nopanic(x, SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
 #define alloc_bootmem_low(x) \
         __alloc_bootmem_low(x, SMP_CACHE_BYTES, 0)
 #define alloc_bootmem_pages(x) \
         __alloc_bootmem(x, PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+#define alloc_bootmem_pages_nopanic(x) \
+        __alloc_bootmem_nopanic(x, PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
 #define alloc_bootmem_low_pages(x) \
         __alloc_bootmem_low(x, PAGE_SIZE, 0)
 #define alloc_bootmem_node(pgdat, x) \
diff --git a/include/linux/byteorder.h b/include/linux/byteorder.h
new file mode 100644
index 000000000000..29f002d73d98
--- /dev/null
+++ b/include/linux/byteorder.h
@@ -0,0 +1,372 @@
+#ifndef _LINUX_BYTEORDER_H
+#define _LINUX_BYTEORDER_H
+
+#include <linux/types.h>
+#include <linux/swab.h>
+
+#if defined(__LITTLE_ENDIAN) && defined(__BIG_ENDIAN)
+# error Fix asm/byteorder.h to define one endianness
+#endif
+
+#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
+# error Fix asm/byteorder.h to define arch endianness
+#endif
+
+#ifdef __LITTLE_ENDIAN
+# undef __LITTLE_ENDIAN
+# define __LITTLE_ENDIAN 1234
+#endif
+
+#ifdef __BIG_ENDIAN
+# undef __BIG_ENDIAN
+# define __BIG_ENDIAN 4321
+#endif
+
+#if defined(__LITTLE_ENDIAN) && !defined(__LITTLE_ENDIAN_BITFIELD)
+# define __LITTLE_ENDIAN_BITFIELD
+#endif
+
+#if defined(__BIG_ENDIAN) && !defined(__BIG_ENDIAN_BITFIELD)
+# define __BIG_ENDIAN_BITFIELD
+#endif
+
+#ifdef __LITTLE_ENDIAN
+# define __le16_to_cpu(x) ((__force __u16)(__le16)(x))
+# define __le32_to_cpu(x) ((__force __u32)(__le32)(x))
+# define __le64_to_cpu(x) ((__force __u64)(__le64)(x))
+# define __cpu_to_le16(x) ((__force __le16)(__u16)(x))
+# define __cpu_to_le32(x) ((__force __le32)(__u32)(x))
+# define __cpu_to_le64(x) ((__force __le64)(__u64)(x))
+
+# define __be16_to_cpu(x) __swab16((__force __u16)(__be16)(x))
+# define __be32_to_cpu(x) __swab32((__force __u32)(__be32)(x))
+# define __be64_to_cpu(x) __swab64((__force __u64)(__be64)(x))
+# define __cpu_to_be16(x) ((__force __be16)__swab16(x))
+# define __cpu_to_be32(x) ((__force __be32)__swab32(x))
+# define __cpu_to_be64(x) ((__force __be64)__swab64(x))
+#endif
+
+#ifdef __BIG_ENDIAN
+# define __be16_to_cpu(x) ((__force __u16)(__be16)(x))
+# define __be32_to_cpu(x) ((__force __u32)(__be32)(x))
+# define __be64_to_cpu(x) ((__force __u64)(__be64)(x))
+# define __cpu_to_be16(x) ((__force __be16)(__u16)(x))
+# define __cpu_to_be32(x) ((__force __be32)(__u32)(x))
+# define __cpu_to_be64(x) ((__force __be64)(__u64)(x))
+
+# define __le16_to_cpu(x) __swab16((__force __u16)(__le16)(x))
+# define __le32_to_cpu(x) __swab32((__force __u32)(__le32)(x))
+# define __le64_to_cpu(x) __swab64((__force __u64)(__le64)(x))
+# define __cpu_to_le16(x) ((__force __le16)__swab16(x))
+# define __cpu_to_le32(x) ((__force __le32)__swab32(x))
+# define __cpu_to_le64(x) ((__force __le64)__swab64(x))
+#endif
+
+/*
+ * These helpers could be phased out over time as the base version
+ * handles constant folding.
+ */
+#define __constant_htonl(x) __cpu_to_be32(x)
+#define __constant_ntohl(x) __be32_to_cpu(x)
+#define __constant_htons(x) __cpu_to_be16(x)
+#define __constant_ntohs(x) __be16_to_cpu(x)
+
+#define __constant_le16_to_cpu(x) __le16_to_cpu(x)
+#define __constant_le32_to_cpu(x) __le32_to_cpu(x)
+#define __constant_le64_to_cpu(x) __le64_to_cpu(x)
+#define __constant_be16_to_cpu(x) __be16_to_cpu(x)
+#define __constant_be32_to_cpu(x) __be32_to_cpu(x)
+#define __constant_be64_to_cpu(x) __be64_to_cpu(x)
+
+#define __constant_cpu_to_le16(x) __cpu_to_le16(x)
+#define __constant_cpu_to_le32(x) __cpu_to_le32(x)
+#define __constant_cpu_to_le64(x) __cpu_to_le64(x)
+#define __constant_cpu_to_be16(x) __cpu_to_be16(x)
+#define __constant_cpu_to_be32(x) __cpu_to_be32(x)
+#define __constant_cpu_to_be64(x) __cpu_to_be64(x)
+
+static inline void __le16_to_cpus(__u16 *p)
+{
+#ifdef __BIG_ENDIAN
+        __swab16s(p);
+#endif
+}
+
+static inline void __cpu_to_le16s(__u16 *p)
+{
+#ifdef __BIG_ENDIAN
+        __swab16s(p);
+#endif
+}
+
+static inline void __le32_to_cpus(__u32 *p)
+{
+#ifdef __BIG_ENDIAN
+        __swab32s(p);
+#endif
+}
+
+static inline void __cpu_to_le32s(__u32 *p)
+{
+#ifdef __BIG_ENDIAN
+        __swab32s(p);
+#endif
+}
+
+static inline void __le64_to_cpus(__u64 *p)
+{
+#ifdef __BIG_ENDIAN
+        __swab64s(p);
+#endif
+}
+
+static inline void __cpu_to_le64s(__u64 *p)
+{
+#ifdef __BIG_ENDIAN
+        __swab64s(p);
+#endif
+}
+
+static inline void __be16_to_cpus(__u16 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        __swab16s(p);
+#endif
+}
+
+static inline void __cpu_to_be16s(__u16 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        __swab16s(p);
+#endif
+}
+
+static inline void __be32_to_cpus(__u32 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        __swab32s(p);
+#endif
+}
+
+static inline void __cpu_to_be32s(__u32 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        __swab32s(p);
+#endif
+}
+
+static inline void __be64_to_cpus(__u64 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        __swab64s(p);
+#endif
+}
+
+static inline void __cpu_to_be64s(__u64 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        __swab64s(p);
+#endif
+}
+
+static inline __u16 __le16_to_cpup(const __le16 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return (__force __u16)*p;
+#else
+        return __swab16p((__force __u16 *)p);
+#endif
+}
+
+static inline __u32 __le32_to_cpup(const __le32 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return (__force __u32)*p;
+#else
+        return __swab32p((__force __u32 *)p);
+#endif
+}
+
+static inline __u64 __le64_to_cpup(const __le64 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return (__force __u64)*p;
+#else
+        return __swab64p((__force __u64 *)p);
+#endif
+}
+
+static inline __le16 __cpu_to_le16p(const __u16 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return (__force __le16)*p;
+#else
+        return (__force __le16)__swab16p(p);
+#endif
+}
+
+static inline __le32 __cpu_to_le32p(const __u32 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return (__force __le32)*p;
+#else
+        return (__force __le32)__swab32p(p);
+#endif
+}
+
+static inline __le64 __cpu_to_le64p(const __u64 *p)
+{
+#ifdef __LITTLE_ENDIAN
+        return (__force __le64)*p;
+#else
+        return (__force __le64)__swab64p(p);
+#endif
+}
+
+static inline __u16 __be16_to_cpup(const __be16 *p)
+{
+#ifdef __BIG_ENDIAN
+        return (__force __u16)*p;
+#else
+        return __swab16p((__force __u16 *)p);
+#endif
+}
+
+static inline __u32 __be32_to_cpup(const __be32 *p)
+{
+#ifdef __BIG_ENDIAN
+        return (__force __u32)*p;
+#else
+        return __swab32p((__force __u32 *)p);
+#endif
+}
+
+static inline __u64 __be64_to_cpup(const __be64 *p)
+{
+#ifdef __BIG_ENDIAN
+        return (__force __u64)*p;
+#else
+        return __swab64p((__force __u64 *)p);
+#endif
+}
+
+static inline __be16 __cpu_to_be16p(const __u16 *p)
+{
+#ifdef __BIG_ENDIAN
+        return (__force __be16)*p;
+#else
+        return (__force __be16)__swab16p(p);
+#endif
+}
+
+static inline __be32 __cpu_to_be32p(const __u32 *p)
+{
+#ifdef __BIG_ENDIAN
+        return (__force __be32)*p;
+#else
+        return (__force __be32)__swab32p(p);
+#endif
+}
+
+static inline __be64 __cpu_to_be64p(const __u64 *p)
+{
+#ifdef __BIG_ENDIAN
+        return (__force __be64)*p;
+#else
+        return (__force __be64)__swab64p(p);
+#endif
+}
+
+#ifdef __KERNEL__
+
+# define le16_to_cpu __le16_to_cpu
+# define le32_to_cpu __le32_to_cpu
+# define le64_to_cpu __le64_to_cpu
+# define be16_to_cpu __be16_to_cpu
+# define be32_to_cpu __be32_to_cpu
+# define be64_to_cpu __be64_to_cpu
+# define cpu_to_le16 __cpu_to_le16
+# define cpu_to_le32 __cpu_to_le32
+# define cpu_to_le64 __cpu_to_le64
+# define cpu_to_be16 __cpu_to_be16
+# define cpu_to_be32 __cpu_to_be32
+# define cpu_to_be64 __cpu_to_be64
+
+# define le16_to_cpup __le16_to_cpup
+# define le32_to_cpup __le32_to_cpup
+# define le64_to_cpup __le64_to_cpup
+# define be16_to_cpup __be16_to_cpup
+# define be32_to_cpup __be32_to_cpup
+# define be64_to_cpup __be64_to_cpup
+# define cpu_to_le16p __cpu_to_le16p
+# define cpu_to_le32p __cpu_to_le32p
+# define cpu_to_le64p __cpu_to_le64p
+# define cpu_to_be16p __cpu_to_be16p
+# define cpu_to_be32p __cpu_to_be32p
+# define cpu_to_be64p __cpu_to_be64p
+
+# define le16_to_cpus __le16_to_cpus
+# define le32_to_cpus __le32_to_cpus
+# define le64_to_cpus __le64_to_cpus
+# define be16_to_cpus __be16_to_cpus
+# define be32_to_cpus __be32_to_cpus
+# define be64_to_cpus __be64_to_cpus
+# define cpu_to_le16s __cpu_to_le16s
+# define cpu_to_le32s __cpu_to_le32s
+# define cpu_to_le64s __cpu_to_le64s
+# define cpu_to_be16s __cpu_to_be16s
+# define cpu_to_be32s __cpu_to_be32s
+# define cpu_to_be64s __cpu_to_be64s
+
+/*
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+# undef ntohl
+# undef ntohs
+# undef htonl
+# undef htons
+
+# define ___htonl(x) __cpu_to_be32(x)
+# define ___htons(x) __cpu_to_be16(x)
+# define ___ntohl(x) __be32_to_cpu(x)
+# define ___ntohs(x) __be16_to_cpu(x)
+
+# define htonl(x) ___htonl(x)
+# define ntohl(x) ___ntohl(x)
+# define htons(x) ___htons(x)
+# define ntohs(x) ___ntohs(x)
+
+static inline void le16_add_cpu(__le16 *var, u16 val)
+{
+        *var = cpu_to_le16(le16_to_cpup(var) + val);
+}
+
+static inline void le32_add_cpu(__le32 *var, u32 val)
+{
+        *var = cpu_to_le32(le32_to_cpup(var) + val);
+}
+
+static inline void le64_add_cpu(__le64 *var, u64 val)
+{
+        *var = cpu_to_le64(le64_to_cpup(var) + val);
+}
+
+static inline void be16_add_cpu(__be16 *var, u16 val)
+{
+        *var = cpu_to_be16(be16_to_cpup(var) + val);
+}
+
+static inline void be32_add_cpu(__be32 *var, u32 val)
+{
+        *var = cpu_to_be32(be32_to_cpup(var) + val);
+}
+
+static inline void be64_add_cpu(__be64 *var, u64 val)
+{
+        *var = cpu_to_be64(be64_to_cpup(var) + val);
+}
+
+#endif /* __KERNEL__ */
+#endif /* _LINUX_BYTEORDER_H */
diff --git a/include/linux/capability.h b/include/linux/capability.h
index 02673846d205..9d1fe30b6f6c 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -503,8 +503,19 @@ extern const kernel_cap_t __cap_init_eff_set;
 
 kernel_cap_t cap_set_effective(const kernel_cap_t pE_new);
 
-int capable(int cap);
-int __capable(struct task_struct *t, int cap);
+/**
+ * has_capability - Determine if a task has a superior capability available
+ * @t: The task in question
+ * @cap: The capability to be tested for
+ *
+ * Return true if the specified task has the given superior capability
+ * currently in effect, false if not.
+ *
+ * Note that this does not set PF_SUPERPRIV on the task.
+ */
+#define has_capability(t, cap) (security_capable((t), (cap)) == 0)
+
+extern int capable(int cap);
 
 #endif /* __KERNEL__ */
 
diff --git a/include/linux/completion.h b/include/linux/completion.h
index d2961b66d53d..02ef8835999c 100644
--- a/include/linux/completion.h
+++ b/include/linux/completion.h
@@ -49,10 +49,13 @@ extern unsigned long wait_for_completion_timeout(struct completion *x,
                                                    unsigned long timeout);
 extern unsigned long wait_for_completion_interruptible_timeout(
                         struct completion *x, unsigned long timeout);
+extern bool try_wait_for_completion(struct completion *x);
+extern bool completion_done(struct completion *x);
 
 extern void complete(struct completion *);
 extern void complete_all(struct completion *);
 
 #define INIT_COMPLETION(x)      ((x).done = 0)
 
+
 #endif
diff --git a/include/linux/cred.h b/include/linux/cred.h
new file mode 100644
index 000000000000..b69222cc1fd2
--- /dev/null
+++ b/include/linux/cred.h
@@ -0,0 +1,50 @@
+/* Credentials management
+ *
+ * Copyright (C) 2008 Red Hat, Inc. All Rights Reserved.
+ * Written by David Howells (dhowells@redhat.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public Licence
+ * as published by the Free Software Foundation; either version
+ * 2 of the Licence, or (at your option) any later version.
+ */
+
+#ifndef _LINUX_CRED_H
+#define _LINUX_CRED_H
+
+#define get_current_user()      (get_uid(current->user))
+
+#define task_uid(task)          ((task)->uid)
+#define task_gid(task)          ((task)->gid)
+#define task_euid(task)         ((task)->euid)
+#define task_egid(task)         ((task)->egid)
+
+#define current_uid()           (current->uid)
+#define current_gid()           (current->gid)
+#define current_euid()          (current->euid)
+#define current_egid()          (current->egid)
+#define current_suid()          (current->suid)
+#define current_sgid()          (current->sgid)
+#define current_fsuid()         (current->fsuid)
+#define current_fsgid()         (current->fsgid)
+#define current_cap()           (current->cap_effective)
+
+#define current_uid_gid(_uid, _gid)             \
+do {                                            \
+        *(_uid) = current->uid;                 \
+        *(_gid) = current->gid;                 \
+} while(0)
+
+#define current_euid_egid(_uid, _gid)           \
+do {                                            \
+        *(_uid) = current->euid;                \
+        *(_gid) = current->egid;                \
+} while(0)
+
+#define current_fsuid_fsgid(_uid, _gid)         \
+do {                                            \
+        *(_uid) = current->fsuid;               \
+        *(_gid) = current->fsgid;               \
+} while(0)
+
+#endif /* _LINUX_CRED_H */
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 07aa198f19ed..efba1de629ac 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -230,7 +230,7 @@ extern void d_delete(struct dentry *);
 extern struct dentry * d_alloc(struct dentry *, const struct qstr *);
 extern struct dentry * d_alloc_anon(struct inode *);
 extern struct dentry * d_splice_alias(struct inode *, struct dentry *);
-extern struct dentry * d_add_ci(struct inode *, struct dentry *, struct qstr *);
+extern struct dentry * d_add_ci(struct dentry *, struct inode *, struct qstr *);
 extern void shrink_dcache_sb(struct super_block *);
 extern void shrink_dcache_parent(struct dentry *);
 extern void shrink_dcache_for_umount(struct super_block *);
diff --git a/include/linux/device.h b/include/linux/device.h
index d24a47f80f9c..4d8372d135df 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -358,6 +358,7 @@ struct device {
 
         struct kobject kobj;
         char    bus_id[BUS_ID_SIZE];    /* position on parent bus */
+        const char              *init_name; /* initial name of the device */
         struct device_type      *type;
         unsigned                uevent_suppress:1;
 
@@ -406,7 +407,7 @@ struct device {
 /* Get the wakeup routines, which depend on struct device */
 #include <linux/pm_wakeup.h>
 
-static inline const char *dev_name(struct device *dev)
+static inline const char *dev_name(const struct device *dev)
 {
         /* will be changed into kobject_name(&dev->kobj) in the near future */
         return dev->bus_id;
@@ -518,7 +519,7 @@ extern void device_shutdown(void);
 extern void sysdev_shutdown(void);
 
 /* debugging and troubleshooting/diagnostic helpers. */
-extern const char *dev_driver_string(struct device *dev);
+extern const char *dev_driver_string(const struct device *dev);
 #define dev_printk(level, dev, format, arg...)  \
         printk(level "%s %s: " format , dev_driver_string(dev) , \
                dev_name(dev) , ## arg)
diff --git a/include/linux/exportfs.h b/include/linux/exportfs.h
index f5abd1306638..27e772cefb6a 100644
--- a/include/linux/exportfs.h
+++ b/include/linux/exportfs.h
@@ -35,6 +35,27 @@ enum fid_type {
         FILEID_INO32_GEN_PARENT = 2,
 
         /*
+         * 64 bit object ID, 64 bit root object ID,
+         * 32 bit generation number.
+         */
+        FILEID_BTRFS_WITHOUT_PARENT = 0x4d,
+
+        /*
+         * 64 bit object ID, 64 bit root object ID,
+         * 32 bit generation number,
+         * 64 bit parent object ID, 32 bit parent generation.
+         */
+        FILEID_BTRFS_WITH_PARENT = 0x4e,
+
+        /*
+         * 64 bit object ID, 64 bit root object ID,
+         * 32 bit generation number,
+         * 64 bit parent object ID, 32 bit parent generation,
+         * 64 bit parent root object ID.
+         */
+        FILEID_BTRFS_WITH_PARENT_ROOT = 0x4f,
+
+        /*
          * 32 bit block number, 16 bit partition reference,
          * 16 bit unused, 32 bit generation number.
          */
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 3b8870e32afd..531ccd5f5960 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -976,6 +976,9 @@ static inline void __fb_pad_aligned_buffer(u8 *dst, u32 d_pitch,
 
 /* drivers/video/fb_defio.c */
 extern void fb_deferred_io_init(struct fb_info *info);
+extern void fb_deferred_io_open(struct fb_info *info,
+                                struct inode *inode,
+                                struct file *file);
 extern void fb_deferred_io_cleanup(struct fb_info *info);
 extern int fb_deferred_io_fsync(struct file *file, struct dentry *dentry,
                                 int datasync);
diff --git a/include/linux/firmware-map.h b/include/linux/firmware-map.h
index acbdbcc16051..6e199c8dfacc 100644
--- a/include/linux/firmware-map.h
+++ b/include/linux/firmware-map.h
@@ -24,34 +24,8 @@
  */
 #ifdef CONFIG_FIRMWARE_MEMMAP
 
-/**
- * Adds a firmware mapping entry. This function uses kmalloc() for memory
- * allocation. Use firmware_map_add_early() if you want to use the bootmem
- * allocator.
- *
- * That function must be called before late_initcall.
- *
- * @start: Start of the memory range.
- * @end:   End of the memory range (inclusive).
- * @type:  Type of the memory range.
- *
- * Returns 0 on success, or -ENOMEM if no memory could be allocated.
- */
 int firmware_map_add(resource_size_t start, resource_size_t end,
                      const char *type);
-
-/**
- * Adds a firmware mapping entry. This function uses the bootmem allocator
- * for memory allocation. Use firmware_map_add() if you want to use kmalloc().
- *
- * That function must be called before late_initcall.
- *
- * @start: Start of the memory range.
- * @end:   End of the memory range (inclusive).
- * @type:  Type of the memory range.
- *
- * Returns 0 on success, or -ENOMEM if no memory could be allocated.
- */
 int firmware_map_add_early(resource_size_t start, resource_size_t end,
                            const char *type);
 
diff --git a/include/linux/fs_uart_pd.h b/include/linux/fs_uart_pd.h
index 809bb9ffc788..36b61ff39277 100644
--- a/include/linux/fs_uart_pd.h
+++ b/include/linux/fs_uart_pd.h
@@ -12,7 +12,6 @@
 #ifndef FS_UART_PD_H
 #define FS_UART_PD_H
 
-#include <linux/version.h>
 #include <asm/types.h>
 
 enum fs_uart_id {
diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
index f368d041e02d..bb384068272e 100644
--- a/include/linux/ftrace.h
+++ b/include/linux/ftrace.h
@@ -98,6 +98,27 @@ static inline void tracer_disable(void)
 #endif
 }
 
+/* Ftrace disable/restore without lock. Some synchronization mechanism
+ * must be used to prevent ftrace_enabled to be changed between
+ * disable/restore. */
+static inline int __ftrace_enabled_save(void)
+{
+#ifdef CONFIG_FTRACE
+        int saved_ftrace_enabled = ftrace_enabled;
+        ftrace_enabled = 0;
+        return saved_ftrace_enabled;
+#else
+        return 0;
+#endif
+}
+
+static inline void __ftrace_enabled_restore(int enabled)
+{
+#ifdef CONFIG_FTRACE
+        ftrace_enabled = enabled;
+#endif
+}
+
 #ifdef CONFIG_FRAME_POINTER
 /* TODO: need to fix this for ARM */
 # define CALLER_ADDR0 ((unsigned long)__builtin_return_address(0))
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 118216f1bd3c..be4f5e5bfe06 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -110,15 +110,6 @@ struct hd_struct {
 #define GENHD_FL_SUPPRESS_PARTITION_INFO        32
 #define GENHD_FL_FAIL                           64
 
-#define BLK_SCSI_MAX_CMDS       (256)
-#define BLK_SCSI_CMD_PER_LONG   (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
-
-struct blk_scsi_cmd_filter {
-        unsigned long read_ok[BLK_SCSI_CMD_PER_LONG];
-        unsigned long write_ok[BLK_SCSI_CMD_PER_LONG];
-        struct kobject kobj;
-};
-
 struct gendisk {
         int major;                      /* major number of driver */
         int first_minor;
@@ -128,7 +119,6 @@ struct gendisk {
         struct hd_struct **part;        /* [indexed by minor] */
         struct block_device_operations *fops;
         struct request_queue *queue;
-        struct blk_scsi_cmd_filter cmd_filter;
         void *private_data;
         sector_t capacity;
 
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index 4862398e05bf..bf34c5f4c051 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -39,7 +39,6 @@
 #define I2C_DRIVERID_SAA7111A    8      /* video input processor        */
 #define I2C_DRIVERID_SAA7185B   13      /* video encoder                */
 #define I2C_DRIVERID_SAA7110    22      /* video decoder                */
-#define I2C_DRIVERID_MGATVO     23      /* Matrox TVOut                 */
 #define I2C_DRIVERID_SAA5249    24      /* SAA5249 and compatibles      */
 #define I2C_DRIVERID_PCF8583    25      /* real time clock              */
 #define I2C_DRIVERID_SAB3036    26      /* SAB3036 tuner                */
@@ -95,7 +94,6 @@
 #define I2C_HW_B_BT848          0x010005 /* BT848 video boards */
 #define I2C_HW_B_VIA            0x010007 /* Via vt82c586b */
 #define I2C_HW_B_HYDRA          0x010008 /* Apple Hydra Mac I/O */
-#define I2C_HW_B_G400           0x010009 /* Matrox G400 */
 #define I2C_HW_B_I810           0x01000a /* Intel I810 */
 #define I2C_HW_B_VOO            0x01000b /* 3dfx Voodoo 3 / Banshee */
 #define I2C_HW_B_SCX200         0x01000e /* Nat'l Semi SCx200 I2C */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 08be0d21864c..06115128047f 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -97,7 +97,19 @@ extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client,
 
 /**
  * struct i2c_driver - represent an I2C device driver
+ * @id: Unique driver ID (optional)
  * @class: What kind of i2c device we instantiate (for detect)
+ * @attach_adapter: Callback for bus addition (for legacy drivers)
+ * @detach_adapter: Callback for bus removal (for legacy drivers)
+ * @detach_client: Callback for device removal (for legacy drivers)
+ * @probe: Callback for device binding (new-style drivers)
+ * @remove: Callback for device unbinding (new-style drivers)
+ * @shutdown: Callback for device shutdown
+ * @suspend: Callback for device suspend
+ * @resume: Callback for device resume
+ * @command: Callback for bus-wide signaling (optional)
+ * @driver: Device driver model driver
+ * @id_table: List of I2C devices supported by this driver
  * @detect: Callback for device detection
  * @address_data: The I2C addresses to probe, ignore or force (for detect)
  * @clients: List of detected clients we created (for i2c-core use only)
diff --git a/include/linux/if_tun.h b/include/linux/if_tun.h
index 4c6307ad9fdb..8529f57ba263 100644
--- a/include/linux/if_tun.h
+++ b/include/linux/if_tun.h
@@ -45,6 +45,7 @@
 #define TUNGETFEATURES _IOR('T', 207, unsigned int)
 #define TUNSETOFFLOAD  _IOW('T', 208, unsigned int)
 #define TUNSETTXFILTER _IOW('T', 209, unsigned int)
+#define TUNGETIFF      _IOR('T', 210, unsigned int)
 
 /* TUNSETIFF ifr flags */
 #define IFF_TUN         0x0001
diff --git a/include/linux/init.h b/include/linux/init.h
index 11b84e106053..93538b696e3d 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -139,6 +139,7 @@ extern initcall_t __con_initcall_start[], __con_initcall_end[];
 extern initcall_t __security_initcall_start[], __security_initcall_end[];
 
 /* Defined in init/main.c */
+extern int do_one_initcall(initcall_t fn);
 extern char __initdata boot_command_line[];
 extern char *saved_command_line;
 extern unsigned int reset_devices;
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index 22d2115458c6..8d3b7a9afd17 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -109,6 +109,7 @@ extern struct resource iomem_resource;
 extern int request_resource(struct resource *root, struct resource *new);
 extern int release_resource(struct resource *new);
 extern int insert_resource(struct resource *parent, struct resource *new);
+extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
 extern int allocate_resource(struct resource *root, struct resource *new,
                              resource_size_t size, resource_size_t min,
                              resource_size_t max, resource_size_t align,
diff --git a/include/linux/ivtv.h b/include/linux/ivtv.h
index 794b8daa9378..17ca64b5a66c 100644
--- a/include/linux/ivtv.h
+++ b/include/linux/ivtv.h
@@ -21,11 +21,7 @@
 #ifndef __LINUX_IVTV_H__
 #define __LINUX_IVTV_H__
 
-#ifdef __KERNEL__
-#include <linux/compiler.h> /* need __user */
-#else
-#define __user
-#endif
+#include <linux/compiler.h>
 #include <linux/types.h>
 
 /* ivtv knows several distinct output modes: MPEG streaming,
diff --git a/include/linux/ivtvfb.h b/include/linux/ivtvfb.h
index e980ba62ddcc..e20af47b59ad 100644
--- a/include/linux/ivtvfb.h
+++ b/include/linux/ivtvfb.h
@@ -21,11 +21,7 @@
 #ifndef __LINUX_IVTVFB_H__
 #define __LINUX_IVTVFB_H__
 
-#ifdef __KERNEL__
-#include <linux/compiler.h> /* need __user */
-#else
-#define __user
-#endif
+#include <linux/compiler.h>
 #include <linux/types.h>
 
 /* Framebuffer external API */
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index aaa998f65c7a..2651f805ba6d 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -108,6 +108,13 @@ struct completion;
 struct pt_regs;
 struct user;
 
+#ifdef CONFIG_PREEMPT_VOLUNTARY
+extern int _cond_resched(void);
+# define might_resched() _cond_resched()
+#else
+# define might_resched() do { } while (0)
+#endif
+
 /**
  * might_sleep - annotation for functions that can sleep
  *
@@ -118,13 +125,6 @@ struct user;
  * be bitten later when the calling function happens to sleep when it is not
  * supposed to.
  */
-#ifdef CONFIG_PREEMPT_VOLUNTARY
-extern int _cond_resched(void);
-# define might_resched() _cond_resched()
-#else
-# define might_resched() do { } while (0)
-#endif
-
 #ifdef CONFIG_DEBUG_SPINLOCK_SLEEP
   void __might_sleep(char *file, int line);
 # define might_sleep() \
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 32110cede64f..17f76fc05173 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -25,8 +25,8 @@
 #error KEXEC_CONTROL_MEMORY_LIMIT not defined
 #endif
 
-#ifndef KEXEC_CONTROL_CODE_SIZE
-#error KEXEC_CONTROL_CODE_SIZE not defined
+#ifndef KEXEC_CONTROL_PAGE_SIZE
+#error KEXEC_CONTROL_PAGE_SIZE not defined
 #endif
 
 #ifndef KEXEC_ARCH
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 69511f74f912..70a30651cd12 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -320,12 +320,12 @@ struct kvm_trace_rec {
                 struct {
                         __u64 cycle_u64;
                         __u32 extra_u32[KVM_TRC_EXTRA_MAX];
-                } cycle;
+                } __attribute__((packed)) cycle;
                 struct {
                         __u32 extra_u32[KVM_TRC_EXTRA_MAX];
                 } nocycle;
         } u;
-} __attribute__((packed));
+};
 
 #define KVMIO 0xAE
 
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 06b80337303b..225bfc5bd9ec 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -163,6 +163,7 @@ enum {
         ATA_DEV_NONE            = 9,    /* no device */
 
         /* struct ata_link flags */
+        ATA_LFLAG_NO_HRST       = (1 << 1), /* avoid hardreset */
         ATA_LFLAG_NO_SRST       = (1 << 2), /* avoid softreset */
         ATA_LFLAG_ASSUME_ATA    = (1 << 3), /* assume ATA class */
         ATA_LFLAG_ASSUME_SEMB   = (1 << 4), /* assume SEMB class */
@@ -646,6 +647,7 @@ struct ata_link {
 
         unsigned int            flags;          /* ATA_LFLAG_xxx */
 
+        u32                     saved_scontrol; /* SControl on probe */
         unsigned int            hw_sata_spd_limit;
         unsigned int            sata_spd_limit;
         unsigned int            sata_spd;       /* current SATA PHY speed */
@@ -1427,6 +1429,28 @@ static inline unsigned long ata_deadline(unsigned long from_jiffies,
         return from_jiffies + msecs_to_jiffies(timeout_msecs);
 }
 
+/* Don't open code these in drivers as there are traps. Firstly the range may
+   change in future hardware and specs, secondly 0xFF means 'no DMA' but is
+   > UDMA_0. Dyma ddreigiau */
+
+static inline int ata_using_mwdma(struct ata_device *adev)
+{
+        if (adev->dma_mode >= XFER_MW_DMA_0 && adev->dma_mode <= XFER_MW_DMA_4)
+                return 1;
+        return 0;
+}
+
+static inline int ata_using_udma(struct ata_device *adev)
+{
+        if (adev->dma_mode >= XFER_UDMA_0 && adev->dma_mode <= XFER_UDMA_7)
+                return 1;
+        return 0;
+}
+
+static inline int ata_dma_enabled(struct ata_device *adev)
+{
+        return (adev->dma_mode == 0xFF ? 0 : 1);
+}
 
 /**************************************************************************
  * PMP - drivers/ata/libata-pmp.c
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 2486eb4edbf1..331e5f1c2d8e 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -89,6 +89,7 @@ struct lock_class {
 
         struct lockdep_subclass_key     *key;
         unsigned int                    subclass;
+        unsigned int                    dep_gen_id;
 
         /*
          * IRQ/softirq usage tracking bits:
@@ -189,6 +190,14 @@ struct lock_chain {
         u64                             chain_key;
 };
 
+#define MAX_LOCKDEP_KEYS_BITS           13
+/*
+ * Subtract one because we offset hlock->class_idx by 1 in order
+ * to make 0 mean no class. This avoids overflowing the class_idx
+ * bitfield and hitting the BUG in hlock_class().
+ */
+#define MAX_LOCKDEP_KEYS                ((1UL << MAX_LOCKDEP_KEYS_BITS) - 1)
+
 struct held_lock {
         /*
          * One-way hash of the dependency chain up to this point. We
@@ -205,14 +214,14 @@ struct held_lock {
          * with zero), here we store the previous hash value:
          */
         u64                             prev_chain_key;
-        struct lock_class               *class;
         unsigned long                   acquire_ip;
         struct lockdep_map              *instance;
-
+        struct lockdep_map              *nest_lock;
 #ifdef CONFIG_LOCK_STAT
         u64                             waittime_stamp;
         u64                             holdtime_stamp;
 #endif
+        unsigned int                    class_idx:MAX_LOCKDEP_KEYS_BITS;
         /*
          * The lock-stack is unified in that the lock chains of interrupt
          * contexts nest ontop of process context chains, but we 'separate'
@@ -226,11 +235,11 @@ struct held_lock {
          * The following field is used to detect when we cross into an
          * interrupt context:
          */
-        int                             irq_context;
-        int                             trylock;
-        int                             read;
-        int                             check;
-        int                             hardirqs_off;
+        unsigned int irq_context:2; /* bit 0 - soft, bit 1 - hard */
+        unsigned int trylock:1;
+        unsigned int read:2;        /* see lock_acquire() comment */
+        unsigned int check:2;       /* see lock_acquire() comment */
+        unsigned int hardirqs_off:1;
 };
 
 /*
@@ -294,11 +303,15 @@ extern void lockdep_init_map(struct lockdep_map *lock, const char *name,
  *   2: full validation
  */
 extern void lock_acquire(struct lockdep_map *lock, unsigned int subclass,
-                         int trylock, int read, int check, unsigned long ip);
+                         int trylock, int read, int check,
+                         struct lockdep_map *nest_lock, unsigned long ip);
 
 extern void lock_release(struct lockdep_map *lock, int nested,
                          unsigned long ip);
 
+extern void lock_set_subclass(struct lockdep_map *lock, unsigned int subclass,
+                              unsigned long ip);
+
 # define INIT_LOCKDEP                           .lockdep_recursion = 0,
 
 #define lockdep_depth(tsk)      (debug_locks ? (tsk)->lockdep_depth : 0)
@@ -313,8 +326,9 @@ static inline void lockdep_on(void)
 {
 }
 
-# define lock_acquire(l, s, t, r, c, i)         do { } while (0)
+# define lock_acquire(l, s, t, r, c, n, i)      do { } while (0)
 # define lock_release(l, n, i)                  do { } while (0)
+# define lock_set_subclass(l, s, i)             do { } while (0)
 # define lockdep_init()                         do { } while (0)
 # define lockdep_info()                         do { } while (0)
 # define lockdep_init_map(lock, name, key, sub) do { (void)(key); } while (0)
@@ -400,9 +414,11 @@ static inline void print_irqtrace_events(struct task_struct *curr)
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 # ifdef CONFIG_PROVE_LOCKING
-#  define spin_acquire(l, s, t, i)              lock_acquire(l, s, t, 0, 2, i)
+#  define spin_acquire(l, s, t, i)              lock_acquire(l, s, t, 0, 2, NULL, i)
+#  define spin_acquire_nest(l, s, t, n, i)      lock_acquire(l, s, t, 0, 2, n, i)
 # else
-#  define spin_acquire(l, s, t, i)              lock_acquire(l, s, t, 0, 1, i)
+#  define spin_acquire(l, s, t, i)              lock_acquire(l, s, t, 0, 1, NULL, i)
+#  define spin_acquire_nest(l, s, t, n, i)      lock_acquire(l, s, t, 0, 1, NULL, i)
 # endif
 # define spin_release(l, n, i)                  lock_release(l, n, i)
 #else
@@ -412,11 +428,11 @@ static inline void print_irqtrace_events(struct task_struct *curr)
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 # ifdef CONFIG_PROVE_LOCKING
-#  define rwlock_acquire(l, s, t, i)            lock_acquire(l, s, t, 0, 2, i)
-#  define rwlock_acquire_read(l, s, t, i)       lock_acquire(l, s, t, 2, 2, i)
+#  define rwlock_acquire(l, s, t, i)            lock_acquire(l, s, t, 0, 2, NULL, i)
+#  define rwlock_acquire_read(l, s, t, i)       lock_acquire(l, s, t, 2, 2, NULL, i)
 # else
-#  define rwlock_acquire(l, s, t, i)            lock_acquire(l, s, t, 0, 1, i)
-#  define rwlock_acquire_read(l, s, t, i)       lock_acquire(l, s, t, 2, 1, i)
+#  define rwlock_acquire(l, s, t, i)            lock_acquire(l, s, t, 0, 1, NULL, i)
+#  define rwlock_acquire_read(l, s, t, i)       lock_acquire(l, s, t, 2, 1, NULL, i)
 # endif
 # define rwlock_release(l, n, i)                lock_release(l, n, i)
 #else
@@ -427,9 +443,9 @@ static inline void print_irqtrace_events(struct task_struct *curr)
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 # ifdef CONFIG_PROVE_LOCKING
-#  define mutex_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 2, i)
+#  define mutex_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 2, NULL, i)
 # else
-#  define mutex_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 1, i)
+#  define mutex_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 1, NULL, i)
 # endif
 # define mutex_release(l, n, i)                 lock_release(l, n, i)
 #else
@@ -439,11 +455,11 @@ static inline void print_irqtrace_events(struct task_struct *curr)
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 # ifdef CONFIG_PROVE_LOCKING
-#  define rwsem_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 2, i)
-#  define rwsem_acquire_read(l, s, t, i)        lock_acquire(l, s, t, 1, 2, i)
+#  define rwsem_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 2, NULL, i)
+#  define rwsem_acquire_read(l, s, t, i)        lock_acquire(l, s, t, 1, 2, NULL, i)
 # else
-#  define rwsem_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 1, i)
-#  define rwsem_acquire_read(l, s, t, i)        lock_acquire(l, s, t, 1, 1, i)
+#  define rwsem_acquire(l, s, t, i)             lock_acquire(l, s, t, 0, 1, NULL, i)
+#  define rwsem_acquire_read(l, s, t, i)        lock_acquire(l, s, t, 1, 1, NULL, i)
 # endif
 # define rwsem_release(l, n, i)                 lock_release(l, n, i)
 #else
@@ -452,4 +468,16 @@ static inline void print_irqtrace_events(struct task_struct *curr)
 # define rwsem_release(l, n, i)                 do { } while (0)
 #endif
 
+#ifdef CONFIG_DEBUG_LOCK_ALLOC
+# ifdef CONFIG_PROVE_LOCKING
+#  define lock_map_acquire(l)           lock_acquire(l, 0, 0, 0, 2, NULL, _THIS_IP_)
+# else
+#  define lock_map_acquire(l)           lock_acquire(l, 0, 0, 0, 1, NULL, _THIS_IP_)
+# endif
+# define lock_map_release(l)                    lock_release(l, 1, _THIS_IP_)
+#else
+# define lock_map_acquire(l)                    do { } while (0)
+# define lock_map_release(l)                    do { } while (0)
+#endif
+
 #endif /* __LINUX_LOCKDEP_H */
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 335288bff1b7..72a15dc26bbf 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -73,7 +73,7 @@ extern unsigned int kobjsize(const void *objp);
 #endif
 
 /*
- * vm_flags..
+ * vm_flags in vm_area_struct, see mm_types.h.
  */
 #define VM_READ         0x00000001      /* currently active flags */
 #define VM_WRITE        0x00000002
@@ -834,7 +834,6 @@ extern int mprotect_fixup(struct vm_area_struct *vma,
                           struct vm_area_struct **pprev, unsigned long start,
                           unsigned long end, unsigned long newflags);
 
-#ifdef CONFIG_HAVE_GET_USER_PAGES_FAST
 /*
  * get_user_pages_fast provides equivalent functionality to get_user_pages,
  * operating on current and current->mm (force=0 and doesn't return any vmas).
@@ -848,25 +847,6 @@ extern int mprotect_fixup(struct vm_area_struct *vma,
 int get_user_pages_fast(unsigned long start, int nr_pages, int write,
                         struct page **pages);
 
-#else
-/*
- * Should probably be moved to asm-generic, and architectures can include it if
- * they don't implement their own get_user_pages_fast.
- */
-#define get_user_pages_fast(start, nr_pages, write, pages)      \
-({                                                              \
-        struct mm_struct *mm = current->mm;                     \
-        int ret;                                                \
-                                                                \
-        down_read(&mm->mmap_sem);                               \
-        ret = get_user_pages(current, mm, start, nr_pages,      \
-                                        write, 0, pages, NULL); \
-        up_read(&mm->mmap_sem);                                 \
-                                                                \
-        ret;                                                    \
-})
-#endif
-
 /*
  * A callback you can register to apply pressure to ageable caches.
  *
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index 386edbe2cb4e..bf334138c7c1 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -113,7 +113,7 @@ struct vm_area_struct {
         struct vm_area_struct *vm_next;
 
         pgprot_t vm_page_prot;          /* Access permissions of this VMA. */
-        unsigned long vm_flags;         /* Flags, listed below. */
+        unsigned long vm_flags;         /* Flags, see mm.h. */
 
         struct rb_node vm_rb;
 
diff --git a/include/linux/net.h b/include/linux/net.h
index 4a9a30f2d68f..6dc14a240042 100644
--- a/include/linux/net.h
+++ b/include/linux/net.h
@@ -18,16 +18,9 @@
 #ifndef _LINUX_NET_H
 #define _LINUX_NET_H
 
-#include <linux/wait.h>
 #include <linux/socket.h>
-#include <linux/fcntl.h>        /* For O_CLOEXEC and O_NONBLOCK */
 #include <asm/socket.h>
 
-struct poll_table_struct;
-struct pipe_inode_info;
-struct inode;
-struct net;
-
 #define NPROTO          AF_MAX
 
 #define SYS_SOCKET      1               /* sys_socket(2)                */
@@ -62,6 +55,13 @@ typedef enum {
 #ifdef __KERNEL__
 #include <linux/stringify.h>
 #include <linux/random.h>
+#include <linux/wait.h>
+#include <linux/fcntl.h>        /* For O_CLOEXEC and O_NONBLOCK */
+
+struct poll_table_struct;
+struct pipe_inode_info;
+struct inode;
+struct net;
 
 #define SOCK_ASYNC_NOSPACE      0
 #define SOCK_ASYNC_WAITDATA     1
diff --git a/include/linux/pci-acpi.h b/include/linux/pci-acpi.h
index 3ba25065fa96..8837928fbf33 100644
--- a/include/linux/pci-acpi.h
+++ b/include/linux/pci-acpi.h
@@ -57,6 +57,15 @@ static inline acpi_status pcie_osc_support_set(u32 flags)
 {
         return __pci_osc_support_set(flags, PCI_EXPRESS_ROOT_HID_STRING);
 }
+static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
+{
+        /* Find root host bridge */
+        while (pdev->bus->self)
+                pdev = pdev->bus->self;
+
+        return acpi_get_pci_rootbridge_handle(pci_domain_nr(pdev->bus),
+                        pdev->bus->number);
+}
 #else
 #if !defined(AE_ERROR)
 typedef u32             acpi_status;
@@ -66,6 +75,8 @@ static inline acpi_status pci_osc_control_set(acpi_handle handle, u32 flags)
 {return AE_ERROR;}
 static inline acpi_status pci_osc_support_set(u32 flags) {return AE_ERROR;} 
 static inline acpi_status pcie_osc_support_set(u32 flags) {return AE_ERROR;}
+static inline acpi_handle acpi_find_root_bridge_handle(struct pci_dev *pdev)
+{ return NULL; }
 #endif
 
 #endif  /* _PCI_ACPI_H_ */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 9ec2bcce8e83..f1624b396754 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2428,6 +2428,9 @@
 #define PCI_DEVICE_ID_INTEL_ICH10_3     0x3a1a
 #define PCI_DEVICE_ID_INTEL_ICH10_4     0x3a30
 #define PCI_DEVICE_ID_INTEL_ICH10_5     0x3a60
+#define PCI_DEVICE_ID_INTEL_PCH_0       0x3b10
+#define PCI_DEVICE_ID_INTEL_PCH_1       0x3b11
+#define PCI_DEVICE_ID_INTEL_PCH_2       0x3b30
 #define PCI_DEVICE_ID_INTEL_IOAT_SNB    0x402f
 #define PCI_DEVICE_ID_INTEL_5100_16     0x65f0
 #define PCI_DEVICE_ID_INTEL_5100_21     0x65f5
diff --git a/include/linux/pid.h b/include/linux/pid.h
index 22921ac4cfd9..d7e98ff8021e 100644
--- a/include/linux/pid.h
+++ b/include/linux/pid.h
@@ -161,4 +161,13 @@ pid_t pid_vnr(struct pid *pid);
                         }                                               \
         } while (0)
 
+#define do_each_pid_thread(pid, type, task)                             \
+        do_each_pid_task(pid, type, task) {                             \
+                struct task_struct *tg___ = task;                       \
+                do {
+
+#define while_each_pid_thread(pid, type, task)                          \
+                } while_each_thread(tg___, task);                       \
+                task = tg___;                                           \
+        } while_each_pid_task(pid, type, task)
 #endif /* _LINUX_PID_H */
diff --git a/include/linux/rcuclassic.h b/include/linux/rcuclassic.h
index 8c774905dcfe..4ab843622727 100644
--- a/include/linux/rcuclassic.h
+++ b/include/linux/rcuclassic.h
@@ -117,7 +117,7 @@ extern int rcu_needs_cpu(int cpu);
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 extern struct lockdep_map rcu_lock_map;
 # define rcu_read_acquire()     \
-                        lock_acquire(&rcu_lock_map, 0, 0, 2, 1, _THIS_IP_)
+                        lock_acquire(&rcu_lock_map, 0, 0, 2, 1, NULL, _THIS_IP_)
 # define rcu_read_release()     lock_release(&rcu_lock_map, 1, _THIS_IP_)
 #else
 # define rcu_read_acquire()     do { } while (0)
diff --git a/include/linux/reboot.h b/include/linux/reboot.h
index b93b541cf111..988e55fe649b 100644
--- a/include/linux/reboot.h
+++ b/include/linux/reboot.h
@@ -59,6 +59,7 @@ extern void machine_crash_shutdown(struct pt_regs *);
  * Architecture independent implemenations of sys_reboot commands.
  */
 
+extern void kernel_restart_prepare(char *cmd);
 extern void kernel_restart(char *cmd);
 extern void kernel_halt(void);
 extern void kernel_power_off(void);
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index 69407f85e10b..fed6f5e0b411 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -102,7 +102,7 @@ int try_to_unmap(struct page *, int ignore_refs);
  * Called from mm/filemap_xip.c to unmap empty zero page
  */
 pte_t *page_check_address(struct page *, struct mm_struct *,
-                                unsigned long, spinlock_t **);
+                                unsigned long, spinlock_t **, int);
 
 /*
  * Used by swapoff to help locate where page is expected in vma.
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 5270d449ff9d..cfb0d87b99fc 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -87,6 +87,7 @@ struct sched_param {
 #include <linux/task_io_accounting.h>
 #include <linux/kobject.h>
 #include <linux/latencytop.h>
+#include <linux/cred.h>
 
 #include <asm/processor.h>
 
@@ -1551,16 +1552,10 @@ static inline int set_cpus_allowed(struct task_struct *p, cpumask_t new_mask)
 
 extern unsigned long long sched_clock(void);
 
-#ifndef CONFIG_HAVE_UNSTABLE_SCHED_CLOCK
-static inline void sched_clock_init(void)
-{
-}
-
-static inline u64 sched_clock_cpu(int cpu)
-{
-        return sched_clock();
-}
+extern void sched_clock_init(void);
+extern u64 sched_clock_cpu(int cpu);
 
+#ifndef CONFIG_HAVE_UNSTABLE_SCHED_CLOCK
 static inline void sched_clock_tick(void)
 {
 }
@@ -1572,28 +1567,11 @@ static inline void sched_clock_idle_sleep_event(void)
 static inline void sched_clock_idle_wakeup_event(u64 delta_ns)
 {
 }
-
-#ifdef CONFIG_NO_HZ
-static inline void sched_clock_tick_stop(int cpu)
-{
-}
-
-static inline void sched_clock_tick_start(int cpu)
-{
-}
-#endif
-
-#else /* CONFIG_HAVE_UNSTABLE_SCHED_CLOCK */
-extern void sched_clock_init(void);
-extern u64 sched_clock_cpu(int cpu);
+#else
 extern void sched_clock_tick(void);
 extern void sched_clock_idle_sleep_event(void);
 extern void sched_clock_idle_wakeup_event(u64 delta_ns);
-#ifdef CONFIG_NO_HZ
-extern void sched_clock_tick_stop(int cpu);
-extern void sched_clock_tick_start(int cpu);
 #endif
-#endif /* CONFIG_HAVE_UNSTABLE_SCHED_CLOCK */
 
 /*
  * For kernel-internal use: high-speed (but slightly incorrect) per-cpu
diff --git a/include/linux/security.h b/include/linux/security.h
index fd96e7f8a6f9..80c4d002864c 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -46,8 +46,8 @@ struct audit_krule;
  */
 extern int cap_capable(struct task_struct *tsk, int cap);
 extern int cap_settime(struct timespec *ts, struct timezone *tz);
-extern int cap_ptrace(struct task_struct *parent, struct task_struct *child,
-                      unsigned int mode);
+extern int cap_ptrace_may_access(struct task_struct *child, unsigned int mode);
+extern int cap_ptrace_traceme(struct task_struct *parent);
 extern int cap_capget(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
 extern int cap_capset_check(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
 extern void cap_capset_set(struct task_struct *target, kernel_cap_t *effective, kernel_cap_t *inheritable, kernel_cap_t *permitted);
@@ -1157,17 +1157,24 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
  *      @alter contains the flag indicating whether changes are to be made.
  *      Return 0 if permission is granted.
  *
- * @ptrace:
- *      Check permission before allowing the @parent process to trace the
+ * @ptrace_may_access:
+ *      Check permission before allowing the current process to trace the
  *      @child process.
  *      Security modules may also want to perform a process tracing check
  *      during an execve in the set_security or apply_creds hooks of
  *      binprm_security_ops if the process is being traced and its security
  *      attributes would be changed by the execve.
- *      @parent contains the task_struct structure for parent process.
- *      @child contains the task_struct structure for child process.
+ *      @child contains the task_struct structure for the target process.
  *      @mode contains the PTRACE_MODE flags indicating the form of access.
  *      Return 0 if permission is granted.
+ * @ptrace_traceme:
+ *      Check that the @parent process has sufficient permission to trace the
+ *      current process before allowing the current process to present itself
+ *      to the @parent process for tracing.
+ *      The parent process will still have to undergo the ptrace_may_access
+ *      checks before it is allowed to trace this one.
+ *      @parent contains the task_struct structure for debugger process.
+ *      Return 0 if permission is granted.
  * @capget:
  *      Get the @effective, @inheritable, and @permitted capability sets for
  *      the @target process.  The hook may also perform permission checking to
@@ -1287,8 +1294,8 @@ static inline void security_free_mnt_opts(struct security_mnt_opts *opts)
 struct security_operations {
         char name[SECURITY_NAME_MAX + 1];
 
-        int (*ptrace) (struct task_struct *parent, struct task_struct *child,
-                       unsigned int mode);
+        int (*ptrace_may_access) (struct task_struct *child, unsigned int mode);
+        int (*ptrace_traceme) (struct task_struct *parent);
         int (*capget) (struct task_struct *target,
                        kernel_cap_t *effective,
                        kernel_cap_t *inheritable, kernel_cap_t *permitted);
@@ -1560,8 +1567,8 @@ extern struct dentry *securityfs_create_dir(const char *name, struct dentry *par
 extern void securityfs_remove(struct dentry *dentry);
 
 /* Security operations */
-int security_ptrace(struct task_struct *parent, struct task_struct *child,
-                    unsigned int mode);
+int security_ptrace_may_access(struct task_struct *child, unsigned int mode);
+int security_ptrace_traceme(struct task_struct *parent);
 int security_capget(struct task_struct *target,
                     kernel_cap_t *effective,
                     kernel_cap_t *inheritable,
@@ -1742,11 +1749,15 @@ static inline int security_init(void)
         return 0;
 }
 
-static inline int security_ptrace(struct task_struct *parent,
-                                  struct task_struct *child,
-                                  unsigned int mode)
+static inline int security_ptrace_may_access(struct task_struct *child,
+                                             unsigned int mode)
+{
+        return cap_ptrace_may_access(child, mode);
+}
+
+static inline int security_ptrace_traceme(struct task_struct *parent)
 {
-        return cap_ptrace(parent, child, mode);
+        return cap_ptrace_traceme(parent);
 }
 
 static inline int security_capget(struct task_struct *target,
diff --git a/include/linux/seq_file.h b/include/linux/seq_file.h
index a66304a09955..a1783b229ef4 100644
--- a/include/linux/seq_file.h
+++ b/include/linux/seq_file.h
@@ -4,6 +4,8 @@
 #include <linux/types.h>
 #include <linux/string.h>
 #include <linux/mutex.h>
+#include <linux/cpumask.h>
+#include <linux/nodemask.h>
 
 struct seq_operations;
 struct file;
@@ -47,6 +49,16 @@ int seq_path(struct seq_file *, struct path *, char *);
 int seq_dentry(struct seq_file *, struct dentry *, char *);
 int seq_path_root(struct seq_file *m, struct path *path, struct path *root,
                   char *esc);
+int seq_bitmap(struct seq_file *m, unsigned long *bits, unsigned int nr_bits);
+static inline int seq_cpumask(struct seq_file *m, cpumask_t *mask)
+{
+        return seq_bitmap(m, mask->bits, NR_CPUS);
+}
+
+static inline int seq_nodemask(struct seq_file *m, nodemask_t *mask)
+{
+        return seq_bitmap(m, mask->bits, MAX_NUMNODES);
+}
 
 int single_open(struct file *, int (*)(struct seq_file *, void *), void *);
 int single_release(struct inode *, struct file *);
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index cfcc45b3bef0..909923717830 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -901,7 +901,7 @@ extern unsigned char *__pskb_pull_tail(struct sk_buff *skb, int delta);
 static inline unsigned char *__pskb_pull(struct sk_buff *skb, unsigned int len)
 {
         if (len > skb_headlen(skb) &&
-            !__pskb_pull_tail(skb, len-skb_headlen(skb)))
+            !__pskb_pull_tail(skb, len - skb_headlen(skb)))
                 return NULL;
         skb->len -= len;
         return skb->data += len;
@@ -918,7 +918,7 @@ static inline int pskb_may_pull(struct sk_buff *skb, unsigned int len)
                 return 1;
         if (unlikely(len > skb->len))
                 return 0;
-        return __pskb_pull_tail(skb, len-skb_headlen(skb)) != NULL;
+        return __pskb_pull_tail(skb, len - skb_headlen(skb)) != NULL;
 }
 
 /**
@@ -1321,7 +1321,7 @@ static inline int skb_padto(struct sk_buff *skb, unsigned int len)
         unsigned int size = skb->len;
         if (likely(size >= len))
                 return 0;
-        return skb_pad(skb, len-size);
+        return skb_pad(skb, len - size);
 }
 
 static inline int skb_add_data(struct sk_buff *skb,
@@ -1452,6 +1452,10 @@ extern int	       skb_copy_datagram_iovec(const struct sk_buff *from,
 extern int             skb_copy_and_csum_datagram_iovec(struct sk_buff *skb,
                                                         int hlen,
                                                         struct iovec *iov);
+extern int             skb_copy_datagram_from_iovec(struct sk_buff *skb,
+                                                    int offset,
+                                                    struct iovec *from,
+                                                    int len);
 extern void            skb_free_datagram(struct sock *sk, struct sk_buff *skb);
 extern int             skb_kill_datagram(struct sock *sk, struct sk_buff *skb,
                                          unsigned int flags);
diff --git a/include/linux/spinlock.h b/include/linux/spinlock.h
index 61e5610ad165..e0c0fccced46 100644
--- a/include/linux/spinlock.h
+++ b/include/linux/spinlock.h
@@ -183,8 +183,14 @@ do {								\
 
 #ifdef CONFIG_DEBUG_LOCK_ALLOC
 # define spin_lock_nested(lock, subclass) _spin_lock_nested(lock, subclass)
+# define spin_lock_nest_lock(lock, nest_lock)                           \
+         do {                                                           \
+                 typecheck(struct lockdep_map *, &(nest_lock)->dep_map);\
+                 _spin_lock_nest_lock(lock, &(nest_lock)->dep_map);     \
+         } while (0)
 #else
 # define spin_lock_nested(lock, subclass) _spin_lock(lock)
+# define spin_lock_nest_lock(lock, nest_lock) _spin_lock(lock)
 #endif
 
 #define write_lock(lock)                _write_lock(lock)
diff --git a/include/linux/spinlock_api_smp.h b/include/linux/spinlock_api_smp.h
index 8a2307ce7296..d79845d034b5 100644
--- a/include/linux/spinlock_api_smp.h
+++ b/include/linux/spinlock_api_smp.h
@@ -22,6 +22,8 @@ int in_lock_functions(unsigned long addr);
 void __lockfunc _spin_lock(spinlock_t *lock)            __acquires(lock);
 void __lockfunc _spin_lock_nested(spinlock_t *lock, int subclass)
                                                         __acquires(lock);
+void __lockfunc _spin_lock_nest_lock(spinlock_t *lock, struct lockdep_map *map)
+                                                        __acquires(lock);
 void __lockfunc _read_lock(rwlock_t *lock)              __acquires(lock);
 void __lockfunc _write_lock(rwlock_t *lock)             __acquires(lock);
 void __lockfunc _spin_lock_bh(spinlock_t *lock)         __acquires(lock);
diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h
index f1cb0ba6d715..faf1519b5adc 100644
--- a/include/linux/stop_machine.h
+++ b/include/linux/stop_machine.h
@@ -3,16 +3,13 @@
 /* "Bogolock": stop the entire machine, disable interrupts.  This is a
    very heavy lock, which is equivalent to grabbing every spinlock
    (and more).  So the "read" side to such a lock is anything which
-   diables preeempt. */
+   disables preeempt. */
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <asm/system.h>
 
 #if defined(CONFIG_STOP_MACHINE) && defined(CONFIG_SMP)
 
-/* Deprecated, but useful for transition. */
-#define ALL_CPUS ~0U
-
 /**
  * stop_machine: freeze the machine on all CPUs and run this function
  * @fn: the function to run
@@ -50,18 +47,4 @@ static inline int stop_machine(int (*fn)(void *), void *data,
         return ret;
 }
 #endif /* CONFIG_SMP */
-
-static inline int __deprecated stop_machine_run(int (*fn)(void *), void *data,
-                                                unsigned int cpu)
-{
-        /* If they don't care which cpu fn runs on, just pick one. */
-        if (cpu == NR_CPUS)
-                return stop_machine(fn, data, NULL);
-        else if (cpu == ~0U)
-                return stop_machine(fn, data, &cpu_possible_map);
-        else {
-                cpumask_t cpus = cpumask_of_cpu(cpu);
-                return stop_machine(fn, data, &cpus);
-        }
-}
 #endif /* _LINUX_STOP_MACHINE */
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index c63435095970..2ce8207686e2 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -217,11 +217,11 @@ struct platform_hibernation_ops {
 #ifdef CONFIG_HIBERNATION
 /* kernel/power/snapshot.c */
 extern void __register_nosave_region(unsigned long b, unsigned long e, int km);
-static inline void register_nosave_region(unsigned long b, unsigned long e)
+static inline void __init register_nosave_region(unsigned long b, unsigned long e)
 {
         __register_nosave_region(b, e, 0);
 }
-static inline void register_nosave_region_late(unsigned long b, unsigned long e)
+static inline void __init register_nosave_region_late(unsigned long b, unsigned long e)
 {
         __register_nosave_region(b, e, 1);
 }
diff --git a/include/linux/swab.h b/include/linux/swab.h
new file mode 100644
index 000000000000..270d5c208a89
--- /dev/null
+++ b/include/linux/swab.h
@@ -0,0 +1,309 @@
+#ifndef _LINUX_SWAB_H
+#define _LINUX_SWAB_H
+
+#include <linux/types.h>
+#include <linux/compiler.h>
+#include <asm/byteorder.h>
+
+/*
+ * casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define __const_swab16(x) ((__u16)(                             \
+        (((__u16)(x) & (__u16)0x00ffU) << 8) |                  \
+        (((__u16)(x) & (__u16)0xff00U) >> 8)))
+
+#define __const_swab32(x) ((__u32)(                             \
+        (((__u32)(x) & (__u32)0x000000ffUL) << 24) |            \
+        (((__u32)(x) & (__u32)0x0000ff00UL) <<  8) |            \
+        (((__u32)(x) & (__u32)0x00ff0000UL) >>  8) |            \
+        (((__u32)(x) & (__u32)0xff000000UL) >> 24)))
+
+#define __const_swab64(x) ((__u64)(                             \
+        (((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) |   \
+        (((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) |   \
+        (((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) |   \
+        (((__u64)(x) & (__u64)0x00000000ff000000ULL) <<  8) |   \
+        (((__u64)(x) & (__u64)0x000000ff00000000ULL) >>  8) |   \
+        (((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) |   \
+        (((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) |   \
+        (((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56)))
+
+#define __const_swahw32(x) ((__u32)(                            \
+        (((__u32)(x) & (__u32)0x0000ffffUL) << 16) |            \
+        (((__u32)(x) & (__u32)0xffff0000UL) >> 16)))
+
+#define __const_swahb32(x) ((__u32)(                            \
+        (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) |             \
+        (((__u32)(x) & (__u32)0xff00ff00UL) >> 8)))
+
+/*
+ * Implement the following as inlines, but define the interface using
+ * macros to allow constant folding when possible:
+ * ___swab16, ___swab32, ___swab64, ___swahw32, ___swahb32
+ */
+
+static inline __attribute_const__ __u16 ___swab16(__u16 val)
+{
+#ifdef __arch_swab16
+        return __arch_swab16(val);
+#elif defined(__arch_swab16p)
+        return __arch_swab16p(&val);
+#else
+        return __const_swab16(val);
+#endif
+}
+
+static inline __attribute_const__ __u32 ___swab32(__u32 val)
+{
+#ifdef __arch_swab32
+        return __arch_swab32(val);
+#elif defined(__arch_swab32p)
+        return __arch_swab32p(&val);
+#else
+        return __const_swab32(val);
+#endif
+}
+
+static inline __attribute_const__ __u64 ___swab64(__u64 val)
+{
+#ifdef __arch_swab64
+        return __arch_swab64(val);
+#elif defined(__arch_swab64p)
+        return __arch_swab64p(&val);
+#elif defined(__SWAB_64_THRU_32__)
+        __u32 h = val >> 32;
+        __u32 l = val & ((1ULL << 32) - 1);
+        return (((__u64)___swab32(l)) << 32) | ((__u64)(___swab32(h)));
+#else
+        return __const_swab64(val);
+#endif
+}
+
+static inline __attribute_const__ __u32 ___swahw32(__u32 val)
+{
+#ifdef __arch_swahw32
+        return __arch_swahw32(val);
+#elif defined(__arch_swahw32p)
+        return __arch_swahw32p(&val);
+#else
+        return __const_swahw32(val);
+#endif
+}
+
+static inline __attribute_const__ __u32 ___swahb32(__u32 val)
+{
+#ifdef __arch_swahb32
+        return __arch_swahb32(val);
+#elif defined(__arch_swahb32p)
+        return __arch_swahb32p(&val);
+#else
+        return __const_swahb32(val);
+#endif
+}
+
+/**
+ * __swab16 - return a byteswapped 16-bit value
+ * @x: value to byteswap
+ */
+#define __swab16(x)                             \
+        (__builtin_constant_p((__u16)(x)) ?     \
+        __const_swab16((x)) :                   \
+        ___swab16((x)))
+
+/**
+ * __swab32 - return a byteswapped 32-bit value
+ * @x: value to byteswap
+ */
+#define __swab32(x)                             \
+        (__builtin_constant_p((__u32)(x)) ?     \
+        __const_swab32((x)) :                   \
+        ___swab32((x)))
+
+/**
+ * __swab64 - return a byteswapped 64-bit value
+ * @x: value to byteswap
+ */
+#define __swab64(x)                             \
+        (__builtin_constant_p((__u64)(x)) ?     \
+        __const_swab64((x)) :                   \
+        ___swab64((x)))
+
+/**
+ * __swahw32 - return a word-swapped 32-bit value
+ * @x: value to wordswap
+ *
+ * __swahw32(0x12340000) is 0x00001234
+ */
+#define __swahw32(x)                            \
+        (__builtin_constant_p((__u32)(x)) ?     \
+        __const_swahw32((x)) :                  \
+        ___swahw32((x)))
+
+/**
+ * __swahb32 - return a high and low byte-swapped 32-bit value
+ * @x: value to byteswap
+ *
+ * __swahb32(0x12345678) is 0x34127856
+ */
+#define __swahb32(x)                            \
+        (__builtin_constant_p((__u32)(x)) ?     \
+        __const_swahb32((x)) :                  \
+        ___swahb32((x)))
+
+/**
+ * __swab16p - return a byteswapped 16-bit value from a pointer
+ * @p: pointer to a naturally-aligned 16-bit value
+ */
+static inline __u16 __swab16p(const __u16 *p)
+{
+#ifdef __arch_swab16p
+        return __arch_swab16p(p);
+#else
+        return __swab16(*p);
+#endif
+}
+
+/**
+ * __swab32p - return a byteswapped 32-bit value from a pointer
+ * @p: pointer to a naturally-aligned 32-bit value
+ */
+static inline __u32 __swab32p(const __u32 *p)
+{
+#ifdef __arch_swab32p
+        return __arch_swab32p(p);
+#else
+        return __swab32(*p);
+#endif
+}
+
+/**
+ * __swab64p - return a byteswapped 64-bit value from a pointer
+ * @p: pointer to a naturally-aligned 64-bit value
+ */
+static inline __u64 __swab64p(const __u64 *p)
+{
+#ifdef __arch_swab64p
+        return __arch_swab64p(p);
+#else
+        return __swab64(*p);
+#endif
+}
+
+/**
+ * __swahw32p - return a wordswapped 32-bit value from a pointer
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahw32() for details of wordswapping.
+ */
+static inline __u32 __swahw32p(const __u32 *p)
+{
+#ifdef __arch_swahw32p
+        return __arch_swahw32p(p);
+#else
+        return __swahw32(*p);
+#endif
+}
+
+/**
+ * __swahb32p - return a high and low byteswapped 32-bit value from a pointer
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahb32() for details of high/low byteswapping.
+ */
+static inline __u32 __swahb32p(const __u32 *p)
+{
+#ifdef __arch_swahb32p
+        return __arch_swahb32p(p);
+#else
+        return __swahb32(*p);
+#endif
+}
+
+/**
+ * __swab16s - byteswap a 16-bit value in-place
+ * @p: pointer to a naturally-aligned 16-bit value
+ */
+static inline void __swab16s(__u16 *p)
+{
+#ifdef __arch_swab16s
+        __arch_swab16s(p);
+#else
+        *p = __swab16p(p);
+#endif
+}
+/**
+ * __swab32s - byteswap a 32-bit value in-place
+ * @p: pointer to a naturally-aligned 32-bit value
+ */
+static inline void __swab32s(__u32 *p)
+{
+#ifdef __arch_swab32s
+        __arch_swab32s(p);
+#else
+        *p = __swab32p(p);
+#endif
+}
+
+/**
+ * __swab64s - byteswap a 64-bit value in-place
+ * @p: pointer to a naturally-aligned 64-bit value
+ */
+static inline void __swab64s(__u64 *p)
+{
+#ifdef __arch_swab64s
+        __arch_swab64s(p);
+#else
+        *p = __swab64p(p);
+#endif
+}
+
+/**
+ * __swahw32s - wordswap a 32-bit value in-place
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahw32() for details of wordswapping
+ */
+static inline void __swahw32s(__u32 *p)
+{
+#ifdef __arch_swahw32s
+        __arch_swahw32s(p);
+#else
+        *p = __swahw32p(p);
+#endif
+}
+
+/**
+ * __swahb32s - high and low byteswap a 32-bit value in-place
+ * @p: pointer to a naturally-aligned 32-bit value
+ *
+ * See __swahb32() for details of high and low byte swapping
+ */
+static inline void __swahb32s(__u32 *p)
+{
+#ifdef __arch_swahb32s
+        __arch_swahb32s(p);
+#else
+        *p = __swahb32p(p);
+#endif
+}
+
+#ifdef __KERNEL__
+# define swab16 __swab16
+# define swab32 __swab32
+# define swab64 __swab64
+# define swahw32 __swahw32
+# define swahb32 __swahb32
+# define swab16p __swab16p
+# define swab32p __swab32p
+# define swab64p __swab64p
+# define swahw32p __swahw32p
+# define swahb32p __swahb32p
+# define swab16s __swab16s
+# define swab32s __swab32s
+# define swab64s __swab64s
+# define swahw32s __swahw32s
+# define swahb32s __swahb32s
+#endif /* __KERNEL__ */
+
+#endif /* _LINUX_SWAB_H */
diff --git a/include/linux/tick.h b/include/linux/tick.h
index d3c02695dc5d..8cf8cfe2cc97 100644
--- a/include/linux/tick.h
+++ b/include/linux/tick.h
@@ -74,10 +74,13 @@ extern struct tick_device *tick_get_device(int cpu);
 extern int tick_init_highres(void);
 extern int tick_program_event(ktime_t expires, int force);
 extern void tick_setup_sched_timer(void);
+# endif
+
+# if defined CONFIG_NO_HZ || defined CONFIG_HIGH_RES_TIMERS
 extern void tick_cancel_sched_timer(int cpu);
 # else
 static inline void tick_cancel_sched_timer(int cpu) { }
-# endif /* HIGHRES */
+# endif
 
 # ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 extern struct tick_device *tick_get_broadcast_device(void);
diff --git a/include/linux/tty.h b/include/linux/tty.h
index e3579cb086e0..0cbec74ec086 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -331,6 +331,8 @@ extern int tty_write_room(struct tty_struct *tty);
 extern void tty_driver_flush_buffer(struct tty_struct *tty);
 extern void tty_throttle(struct tty_struct *tty);
 extern void tty_unthrottle(struct tty_struct *tty);
+extern int tty_do_resize(struct tty_struct *tty, struct tty_struct *real_tty,
+                                                struct winsize *ws);
 
 extern int is_current_pgrp_orphaned(void);
 extern struct pid *tty_get_pgrp(struct tty_struct *tty);
diff --git a/include/linux/tty_driver.h b/include/linux/tty_driver.h
index e1065ac0d922..16d27944c321 100644
--- a/include/linux/tty_driver.h
+++ b/include/linux/tty_driver.h
@@ -168,6 +168,18 @@
  *
  *      Optional: If not provided then the write method is called under
  *      the atomic write lock to keep it serialized with the ldisc.
+ *
+ * int (*resize)(struct tty_struct *tty, struct tty_struct *real_tty,
+ *                              unsigned int rows, unsigned int cols);
+ *
+ *      Called when a termios request is issued which changes the
+ *      requested terminal geometry.
+ *
+ *      Optional: the default action is to update the termios structure
+ *      without error. This is usually the correct behaviour. Drivers should
+ *      not force errors here if they are not resizable objects (eg a serial
+ *      line). See tty_do_resize() if you need to wrap the standard method
+ *      in your own logic - the usual case.
  */
 
 #include <linux/fs.h>
@@ -206,6 +218,8 @@ struct tty_operations {
         int (*tiocmget)(struct tty_struct *tty, struct file *file);
         int (*tiocmset)(struct tty_struct *tty, struct file *file,
                         unsigned int set, unsigned int clear);
+        int (*resize)(struct tty_struct *tty, struct tty_struct *real_tty,
+                                struct winsize *ws);
 #ifdef CONFIG_CONSOLE_POLL
         int (*poll_init)(struct tty_driver *driver, int line, char *options);
         int (*poll_get_char)(struct tty_driver *driver, int line);
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 5811c5da69f9..94ac74aba6b6 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -110,6 +110,10 @@ enum usb_interface_condition {
  * @sysfs_files_created: sysfs attributes exist
  * @needs_remote_wakeup: flag set when the driver requires remote-wakeup
  *      capability during autosuspend.
+ * @needs_altsetting0: flag set when a set-interface request for altsetting 0
+ *      has been deferred.
+ * @needs_binding: flag set when the driver should be re-probed or unbound
+ *      following a reset or suspend operation it doesn't support.
  * @dev: driver model's view of this device
  * @usb_dev: if an interface is bound to the USB major, this will point
  *      to the sysfs representation for that device.
@@ -160,6 +164,7 @@ struct usb_interface {
         unsigned is_active:1;           /* the interface is not suspended */
         unsigned sysfs_files_created:1; /* the sysfs attributes exist */
         unsigned needs_remote_wakeup:1; /* driver requires remote wakeup */
+        unsigned needs_altsetting0:1;   /* switch to altsetting 0 is pending */
         unsigned needs_binding:1;       /* needs delayed unbind/rebind */
 
         struct device dev;              /* interface specific device info */
diff --git a/include/linux/usb/musb.h b/include/linux/usb/musb.h
new file mode 100644
index 000000000000..630962c04ca4
--- /dev/null
+++ b/include/linux/usb/musb.h
@@ -0,0 +1,98 @@
+/*
+ * This is used to for host and peripheral modes of the driver for
+ * Inventra (Multidrop) Highspeed Dual-Role Controllers:  (M)HDRC.
+ *
+ * Board initialization should put one of these into dev->platform_data,
+ * probably on some platform_device named "musb_hdrc".  It encapsulates
+ * key configuration differences between boards.
+ */
+
+/* The USB role is defined by the connector used on the board, so long as
+ * standards are being followed.  (Developer boards sometimes won't.)
+ */
+enum musb_mode {
+        MUSB_UNDEFINED = 0,
+        MUSB_HOST,              /* A or Mini-A connector */
+        MUSB_PERIPHERAL,        /* B or Mini-B connector */
+        MUSB_OTG                /* Mini-AB connector */
+};
+
+struct clk;
+
+struct musb_hdrc_eps_bits {
+        const char      name[16];
+        u8              bits;
+};
+
+struct musb_hdrc_config {
+        /* MUSB configuration-specific details */
+        unsigned        multipoint:1;   /* multipoint device */
+        unsigned        dyn_fifo:1;     /* supports dynamic fifo sizing */
+        unsigned        soft_con:1;     /* soft connect required */
+        unsigned        utm_16:1;       /* utm data witdh is 16 bits */
+        unsigned        big_endian:1;   /* true if CPU uses big-endian */
+        unsigned        mult_bulk_tx:1; /* Tx ep required for multbulk pkts */
+        unsigned        mult_bulk_rx:1; /* Rx ep required for multbulk pkts */
+        unsigned        high_iso_tx:1;  /* Tx ep required for HB iso */
+        unsigned        high_iso_rx:1;  /* Rx ep required for HD iso */
+        unsigned        dma:1;          /* supports DMA */
+        unsigned        vendor_req:1;   /* vendor registers required */
+
+        u8              num_eps;        /* number of endpoints _with_ ep0 */
+        u8              dma_channels;   /* number of dma channels */
+        u8              dyn_fifo_size;  /* dynamic size in bytes */
+        u8              vendor_ctrl;    /* vendor control reg width */
+        u8              vendor_stat;    /* vendor status reg witdh */
+        u8              dma_req_chan;   /* bitmask for required dma channels */
+        u8              ram_bits;       /* ram address size */
+
+        struct musb_hdrc_eps_bits *eps_bits;
+};
+
+struct musb_hdrc_platform_data {
+        /* MUSB_HOST, MUSB_PERIPHERAL, or MUSB_OTG */
+        u8              mode;
+
+        /* for clk_get() */
+        const char      *clock;
+
+        /* (HOST or OTG) switch VBUS on/off */
+        int             (*set_vbus)(struct device *dev, int is_on);
+
+        /* (HOST or OTG) mA/2 power supplied on (default = 8mA) */
+        u8              power;
+
+        /* (PERIPHERAL) mA/2 max power consumed (default = 100mA) */
+        u8              min_power;
+
+        /* (HOST or OTG) msec/2 after VBUS on till power good */
+        u8              potpgt;
+
+        /* Power the device on or off */
+        int             (*set_power)(int state);
+
+        /* Turn device clock on or off */
+        int             (*set_clock)(struct clk *clock, int is_on);
+
+        /* MUSB configuration-specific details */
+        struct musb_hdrc_config *config;
+};
+
+
+/* TUSB 6010 support */
+
+#define TUSB6010_OSCCLK_60      16667   /* psec/clk @ 60.0 MHz */
+#define TUSB6010_REFCLK_24      41667   /* psec/clk @ 24.0 MHz XI */
+#define TUSB6010_REFCLK_19      52083   /* psec/clk @ 19.2 MHz CLKIN */
+
+#ifdef  CONFIG_ARCH_OMAP2
+
+extern int __init tusb6010_setup_interface(
+                struct musb_hdrc_platform_data *data,
+                unsigned ps_refclk, unsigned waitpin,
+                unsigned async_cs, unsigned sync_cs,
+                unsigned irq, unsigned dmachan);
+
+extern int tusb6010_platform_retime(unsigned is_refclk);
+
+#endif  /* OMAP2 */
diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h
index 09a3e6a7518f..655341d0f534 100644
--- a/include/linux/usb/serial.h
+++ b/include/linux/usb/serial.h
@@ -17,7 +17,8 @@
 #include <linux/mutex.h>
 
 #define SERIAL_TTY_MAJOR        188     /* Nice legal number now */
-#define SERIAL_TTY_MINORS       255     /* loads of devices :) */
+#define SERIAL_TTY_MINORS       254     /* loads of devices :) */
+#define SERIAL_TTY_NO_MINOR     255     /* No minor was assigned */
 
 /* The maximum number of ports one device can grab at once */
 #define MAX_NUM_PORTS           8
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index e466bd54a50e..e65a6bed4e3e 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -55,13 +55,13 @@
  */
 #ifndef __LINUX_VIDEODEV2_H
 #define __LINUX_VIDEODEV2_H
+
 #ifdef __KERNEL__
 #include <linux/time.h>     /* need struct timeval */
-#include <linux/compiler.h> /* need __user */
 #else
-#define __user
 #include <sys/time.h>
 #endif
+#include <linux/compiler.h>
 #include <linux/ioctl.h>
 #include <linux/types.h>
 
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 364789aae9f3..328eb4022727 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -4,9 +4,9 @@
 #include <linux/spinlock.h>
 #include <asm/page.h>           /* pgprot_t */
 
-struct vm_area_struct;
+struct vm_area_struct;          /* vma defining user mapping in mm_types.h */
 
-/* bits in vm_struct->flags */
+/* bits in flags of vmalloc's vm_struct below */
 #define VM_IOREMAP      0x00000001      /* ioremap() and friends */
 #define VM_ALLOC        0x00000002      /* vmalloc() */
 #define VM_MAP          0x00000004      /* vmap()ed pages */
diff --git a/include/linux/vt_kern.h b/include/linux/vt_kern.h
index 1c78d56c57e5..1cbd0a7db4e6 100644
--- a/include/linux/vt_kern.h
+++ b/include/linux/vt_kern.h
@@ -35,7 +35,6 @@ extern int fg_console, last_console, want_console;
 int vc_allocate(unsigned int console);
 int vc_cons_allocated(unsigned int console);
 int vc_resize(struct vc_data *vc, unsigned int cols, unsigned int lines);
-int vc_lock_resize(struct vc_data *vc, unsigned int cols, unsigned int lines);
 void vc_deallocate(unsigned int console);
 void reset_palette(struct vc_data *vc);
 void do_blank_screen(int entering_gfx);
diff --git a/include/net/addrconf.h b/include/net/addrconf.h
index 06b28142b3ab..c216de528b08 100644
--- a/include/net/addrconf.h
+++ b/include/net/addrconf.h
@@ -80,7 +80,8 @@ extern struct inet6_ifaddr      *ipv6_get_ifaddr(struct net *net,
                                                  struct net_device *dev,
                                                  int strict);
 
-extern int                      ipv6_dev_get_saddr(struct net_device *dev, 
+extern int                      ipv6_dev_get_saddr(struct net *net,
+                                               struct net_device *dev,
                                                const struct in6_addr *daddr,
                                                unsigned int srcprefs,
                                                struct in6_addr *saddr);
diff --git a/include/net/ip6_route.h b/include/net/ip6_route.h
index 2f8b3c06a101..5f53db7e4e57 100644
--- a/include/net/ip6_route.h
+++ b/include/net/ip6_route.h
@@ -38,11 +38,6 @@ struct route_info {
 #define RT6_LOOKUP_F_SRCPREF_COA        0x00000020
 
 
-#ifdef CONFIG_IPV6_MULTIPLE_TABLES
-extern struct rt6_info  *ip6_prohibit_entry;
-extern struct rt6_info  *ip6_blk_hole_entry;
-#endif
-
 extern void                     ip6_route_input(struct sk_buff *skb);
 
 extern struct dst_entry *       ip6_route_output(struct net *net,
@@ -112,13 +107,13 @@ struct rt6_rtnl_dump_arg
 {
         struct sk_buff *skb;
         struct netlink_callback *cb;
+        struct net *net;
 };
 
 extern int rt6_dump_route(struct rt6_info *rt, void *p_arg);
 extern void rt6_ifdown(struct net *net, struct net_device *dev);
 extern void rt6_mtu_change(struct net_device *dev, unsigned mtu);
 
-extern rwlock_t rt6_lock;
 
 /*
  *      Store a destination cache entry in a socket
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index cbb59ebed4ae..7312c3dd309f 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -140,8 +140,24 @@ struct ip_vs_seq {
 
 
 /*
- *      IPVS statistics object
+ *      IPVS statistics objects
  */
+struct ip_vs_estimator {
+        struct list_head        list;
+
+        u64                     last_inbytes;
+        u64                     last_outbytes;
+        u32                     last_conns;
+        u32                     last_inpkts;
+        u32                     last_outpkts;
+
+        u32                     cps;
+        u32                     inpps;
+        u32                     outpps;
+        u32                     inbps;
+        u32                     outbps;
+};
+
 struct ip_vs_stats
 {
         __u32                   conns;          /* connections scheduled */
@@ -156,7 +172,15 @@ struct ip_vs_stats
         __u32                   inbps;          /* current in byte rate */
         __u32                   outbps;         /* current out byte rate */
 
+        /*
+         * Don't add anything before the lock, because we use memcpy() to copy
+         * the members before the lock to struct ip_vs_stats_user in
+         * ip_vs_ctl.c.
+         */
+
         spinlock_t              lock;           /* spin lock */
+
+        struct ip_vs_estimator  est;            /* estimator */
 };
 
 struct dst_entry;
@@ -440,7 +464,7 @@ struct ip_vs_app
  */
 extern const char *ip_vs_proto_name(unsigned proto);
 extern void ip_vs_init_hash_table(struct list_head *table, int rows);
-#define IP_VS_INIT_HASH_TABLE(t) ip_vs_init_hash_table(t, sizeof(t)/sizeof(t[0]))
+#define IP_VS_INIT_HASH_TABLE(t) ip_vs_init_hash_table((t), ARRAY_SIZE((t)))
 
 #define IP_VS_APP_TYPE_FTP      1
 
@@ -620,7 +644,7 @@ extern int sysctl_ip_vs_expire_quiescent_template;
 extern int sysctl_ip_vs_sync_threshold[2];
 extern int sysctl_ip_vs_nat_icmp_send;
 extern struct ip_vs_stats ip_vs_stats;
-extern struct ctl_path net_vs_ctl_path[];
+extern const struct ctl_path net_vs_ctl_path[];
 
 extern struct ip_vs_service *
 ip_vs_service_get(__u32 fwmark, __u16 protocol, __be32 vaddr, __be16 vport);
@@ -659,7 +683,7 @@ extern void ip_vs_sync_conn(struct ip_vs_conn *cp);
 /*
  *      IPVS rate estimator prototypes (from ip_vs_est.c)
  */
-extern int ip_vs_new_estimator(struct ip_vs_stats *stats);
+extern void ip_vs_new_estimator(struct ip_vs_stats *stats);
 extern void ip_vs_kill_estimator(struct ip_vs_stats *stats);
 extern void ip_vs_zero_estimator(struct ip_vs_stats *stats);
 
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index b397e4d984c7..ff137fd7714f 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -708,10 +708,7 @@ enum ieee80211_tkip_key_type {
  *      rely on the host system for such buffering. This option is used
  *      to configure the IEEE 802.11 upper layer to buffer broadcast and
  *      multicast frames when there are power saving stations so that
- *      the driver can fetch them with ieee80211_get_buffered_bc(). Note
- *      that not setting this flag works properly only when the
- *      %IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE is also not set because
- *      otherwise the stack will not know when the DTIM beacon was sent.
+ *      the driver can fetch them with ieee80211_get_buffered_bc().
  *
  * @IEEE80211_HW_2GHZ_SHORT_SLOT_INCAPABLE:
  *      Hardware is not capable of short slot operation on the 2.4 GHz band.
@@ -1099,10 +1096,8 @@ enum ieee80211_ampdu_mlme_action {
  *      See the section "Frame filtering" for more information.
  *      This callback must be implemented and atomic.
  *
- * @set_tim: Set TIM bit. If the hardware/firmware takes care of beacon
- *      generation (that is, %IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE is set)
- *      mac80211 calls this function when a TIM bit must be set or cleared
- *      for a given AID. Must be atomic.
+ * @set_tim: Set TIM bit. mac80211 calls this function when a TIM bit
+ *      must be set or cleared for a given AID. Must be atomic.
  *
  * @set_key: See the section "Hardware crypto acceleration"
  *      This callback can sleep, and is only called between add_interface
diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h
index 6affcfaa123e..b786a5b09253 100644
--- a/include/net/pkt_sched.h
+++ b/include/net/pkt_sched.h
@@ -78,6 +78,7 @@ extern struct Qdisc *fifo_create_dflt(struct Qdisc *sch, struct Qdisc_ops *ops,
 
 extern int register_qdisc(struct Qdisc_ops *qops);
 extern int unregister_qdisc(struct Qdisc_ops *qops);
+extern void qdisc_list_del(struct Qdisc *q);
 extern struct Qdisc *qdisc_lookup(struct net_device *dev, u32 handle);
 extern struct Qdisc *qdisc_lookup_class(struct net_device *dev, u32 handle);
 extern struct qdisc_rate_table *qdisc_get_rtab(struct tc_ratespec *r,
@@ -89,7 +90,10 @@ extern void __qdisc_run(struct Qdisc *q);
 
 static inline void qdisc_run(struct Qdisc *q)
 {
-        if (!test_and_set_bit(__QDISC_STATE_RUNNING, &q->state))
+        struct netdev_queue *txq = q->dev_queue;
+
+        if (!netif_tx_queue_stopped(txq) &&
+            !test_and_set_bit(__QDISC_STATE_RUNNING, &q->state))
                 __qdisc_run(q);
 }
 
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index a7abfda3e447..e5569625d2a5 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -27,6 +27,7 @@ enum qdisc_state_t
 {
         __QDISC_STATE_RUNNING,
         __QDISC_STATE_SCHED,
+        __QDISC_STATE_DEACTIVATED,
 };
 
 struct qdisc_size_table {
@@ -60,7 +61,6 @@ struct Qdisc
         struct gnet_stats_basic bstats;
         struct gnet_stats_queue qstats;
         struct gnet_stats_rate_est      rate_est;
-        struct rcu_head         q_rcu;
         int                     (*reshape_fail)(struct sk_buff *skb,
                                         struct Qdisc *q);
 
@@ -193,6 +193,11 @@ static inline struct Qdisc *qdisc_root(struct Qdisc *qdisc)
         return qdisc->dev_queue->qdisc;
 }
 
+static inline struct Qdisc *qdisc_root_sleeping(struct Qdisc *qdisc)
+{
+        return qdisc->dev_queue->qdisc_sleeping;
+}
+
 /* The qdisc root lock is a mechanism by which to top level
  * of a qdisc tree can be locked from any qdisc node in the
  * forest.  This allows changing the configuration of some
@@ -212,6 +217,14 @@ static inline spinlock_t *qdisc_root_lock(struct Qdisc *qdisc)
         return qdisc_lock(root);
 }
 
+static inline spinlock_t *qdisc_root_sleeping_lock(struct Qdisc *qdisc)
+{
+        struct Qdisc *root = qdisc_root_sleeping(qdisc);
+
+        ASSERT_RTNL();
+        return qdisc_lock(root);
+}
+
 static inline struct net_device *qdisc_dev(struct Qdisc *qdisc)
 {
         return qdisc->dev_queue->dev;
@@ -219,12 +232,12 @@ static inline struct net_device *qdisc_dev(struct Qdisc *qdisc)
 
 static inline void sch_tree_lock(struct Qdisc *q)
 {
-        spin_lock_bh(qdisc_root_lock(q));
+        spin_lock_bh(qdisc_root_sleeping_lock(q));
 }
 
 static inline void sch_tree_unlock(struct Qdisc *q)
 {
-        spin_unlock_bh(qdisc_root_lock(q));
+        spin_unlock_bh(qdisc_root_sleeping_lock(q));
 }
 
 #define tcf_tree_lock(tp)       sch_tree_lock((tp)->q)
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index 291d56a19167..80b2e93c2936 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -6,6 +6,7 @@
 #include <linux/spinlock.h>
 #include <linux/workqueue.h>
 #include <linux/blkdev.h>
+#include <scsi/scsi.h>
 #include <asm/atomic.h>
 
 struct request_queue;
@@ -426,7 +427,7 @@ static inline int scsi_device_enclosure(struct scsi_device *sdev)
 
 static inline int scsi_device_protection(struct scsi_device *sdev)
 {
-        return sdev->inquiry[5] & (1<<0);
+        return sdev->scsi_level > SCSI_2 && sdev->inquiry[5] & (1<<0);
 }
 
 #define MODULE_ALIAS_SCSI_DEVICE(type) \
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
index 613173b5db69..920c4e9cb93d 100644
--- a/include/video/atmel_lcdc.h
+++ b/include/video/atmel_lcdc.h
@@ -41,6 +41,7 @@ struct atmel_lcdfb_info {
         struct work_struct      task;
 
         unsigned int            guard_time;
+        unsigned int            smem_len;
         struct platform_device  *pdev;
         struct clk              *bus_clk;
         struct clk              *lcdc_clk;
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 95a1f2038b1d..099ffa5e5bee 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -742,6 +742,10 @@
 #define SOFT_RESET_RB                              (1 <<  6)
 #define SOFT_RESET_HDP                             (1 <<  7)
 
+/* WAIT_UNTIL bit constants */
+#define WAIT_DMA_GUI_IDLE                          (1 << 9)
+#define WAIT_2D_IDLECLEAN                          (1 << 16)
+
 /* SURFACE_CNTL bit consants */
 #define SURF_TRANSLATION_DIS                       (1 << 8)
 #define NONSURF_AP0_SWP_16BPP                      (1 << 20)