[PATCH] Invert sense of SLB class bit

Currently, we set the class bit in kernel SLB entries, and clear it on
user SLB entries.  On POWER5, ERAT entries created in real mode have
the class bit clear.  So to avoid flushing kernel ERAT entries on each
context switch, this patch inverts our usage of the class bit, setting
it on user SLB entries and clearing it on kernel SLB entries.

Booted on POWER5 and G5.

Signed-off-by: David Gibson <dwg@au1.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>

1 files changed, 4 insertions, 2 deletions

diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index ad36bb28de29..7bc42eb087ad 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -54,8 +54,10 @@ extern char initial_stab[];
 #define SLB_VSID_C              ASM_CONST(0x0000000000000080) /* class */
 #define SLB_VSID_LS             ASM_CONST(0x0000000000000070) /* size of largepage */
  
-#define SLB_VSID_KERNEL         (SLB_VSID_KP|SLB_VSID_C)
-#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS)
+#define SLB_VSID_KERNEL         (SLB_VSID_KP)
+#define SLB_VSID_USER           (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
+
+#define SLBIE_C                 (0x08000000)
 
 /*
  * Hash table