PCI: acs p2p upsteram forwarding enabling

Note: dom0 checking in v4 has been separated out into 2/2.

This patch enables P2P upstream forwarding in ACS capable PCIe switches.
It solves two potential problems in virtualization environment where a PCIe
device is assigned to a guest domain using a HW iommu such as VT-d:

1) Unintentional failure caused by guest physical address programmed
   into the device's DMA that happens to match the memory address range
   of other downstream ports in the same PCIe switch.  This causes the PCI
   transaction to go to the matching downstream port instead of go to the
   root complex to get translated by VT-d as it should be.

2) Malicious guest software intentionally attacks another downstream
   PCIe device by programming the DMA address into the assigned device
   that matches memory address range of the downstream PCIe port.

We are in process of implementing device filtering software in KVM/XEN
management software to allow device assignment of PCIe devices behind a PCIe
switch only if it has ACS capability and with the P2P upstream forwarding bits
enabled.  This patch is intended to work for both KVM and Xen environments.

Signed-off-by: Allen Kay <allen.m.kay@intel.com>
Reviewed-by: Mathew Wilcox <willy@linux.intel.com>
Reviewed-by: Chris Wright <chris@sous-sol.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

1 files changed, 13 insertions, 0 deletions

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index dd0bed4f1cf0..d798770f08cd 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -502,6 +502,7 @@
 #define PCI_EXT_CAP_ID_VC       2
 #define PCI_EXT_CAP_ID_DSN      3
 #define PCI_EXT_CAP_ID_PWR      4
+#define PCI_EXT_CAP_ID_ACS      13
 #define PCI_EXT_CAP_ID_ARI      14
 #define PCI_EXT_CAP_ID_ATS      15
 #define PCI_EXT_CAP_ID_SRIOV    16
@@ -662,4 +663,16 @@
 #define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
 
+/* Access Control Service */
+#define PCI_ACS_CAP             0x04    /* ACS Capability Register */
+#define  PCI_ACS_SV             0x01    /* Source Validation */
+#define  PCI_ACS_TB             0x02    /* Translation Blocking */
+#define  PCI_ACS_RR             0x04    /* P2P Request Redirect */
+#define  PCI_ACS_CR             0x08    /* P2P Completion Redirect */
+#define  PCI_ACS_UF             0x10    /* Upstream Forwarding */
+#define  PCI_ACS_EC             0x20    /* P2P Egress Control */
+#define  PCI_ACS_DT             0x40    /* Direct Translated P2P */
+#define PCI_ACS_CTRL            0x06    /* ACS Control Register */
+#define PCI_ACS_EGRESS_CTL_V    0x08    /* ACS Egress Control Vector */
+
 #endif /* LINUX_PCI_REGS_H */