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authorDavide Rizzo <davide@elpa.it>2008-03-30 03:58:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-04-17 12:04:42 -0400
commitde56a2f9228477866449963c2aff9df4728ea7fb (patch)
treea68fdf3eacc411122faf4f4ec2407ff1bb955dd7 /include
parent3c7d9c81e1302c244180e62999a08ca95b175cf5 (diff)
[ARM] 4883/1: Adds some missing gpio defines for S3C2410
This is a small addition of forgotten defines to regs-gpio.h include file for the Samsung S3C2410 ARM9 SoC Signed-off-by: Davide Rizzo <davide@elpa.it> Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index 0ad75d716ded..497dd06e2c99 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -529,11 +529,13 @@
529#define S3C2410_GPD14_INP (0x00 << 28) 529#define S3C2410_GPD14_INP (0x00 << 28)
530#define S3C2410_GPD14_OUTP (0x01 << 28) 530#define S3C2410_GPD14_OUTP (0x01 << 28)
531#define S3C2410_GPD14_VD22 (0x02 << 28) 531#define S3C2410_GPD14_VD22 (0x02 << 28)
532#define S3C2410_GPD14_nSS1 (0x03 << 28)
532 533
533#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15) 534#define S3C2410_GPD15 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
534#define S3C2410_GPD15_INP (0x00 << 30) 535#define S3C2410_GPD15_INP (0x00 << 30)
535#define S3C2410_GPD15_OUTP (0x01 << 30) 536#define S3C2410_GPD15_OUTP (0x01 << 30)
536#define S3C2410_GPD15_VD23 (0x02 << 30) 537#define S3C2410_GPD15_VD23 (0x02 << 30)
538#define S3C2410_GPD15_nSS0 (0x03 << 30)
537 539
538#define S3C2410_GPD_PUPDIS(x) (1<<(x)) 540#define S3C2410_GPD_PUPDIS(x) (1<<(x))
539 541
@@ -801,12 +803,14 @@
801#define S3C2410_GPG2_INP (0x00 << 4) 803#define S3C2410_GPG2_INP (0x00 << 4)
802#define S3C2410_GPG2_OUTP (0x01 << 4) 804#define S3C2410_GPG2_OUTP (0x01 << 4)
803#define S3C2410_GPG2_EINT10 (0x02 << 4) 805#define S3C2410_GPG2_EINT10 (0x02 << 4)
806#define S3C2410_GPG2_nSS0 (0x03 << 4)
804#define S3C2400_GPG2_CDCLK (0x02 << 4) 807#define S3C2400_GPG2_CDCLK (0x02 << 4)
805 808
806#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) 809#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
807#define S3C2410_GPG3_INP (0x00 << 6) 810#define S3C2410_GPG3_INP (0x00 << 6)
808#define S3C2410_GPG3_OUTP (0x01 << 6) 811#define S3C2410_GPG3_OUTP (0x01 << 6)
809#define S3C2410_GPG3_EINT11 (0x02 << 6) 812#define S3C2410_GPG3_EINT11 (0x02 << 6)
813#define S3C2410_GPG3_nSS1 (0x03 << 6)
810#define S3C2400_GPG3_I2SSDO (0x02 << 6) 814#define S3C2400_GPG3_I2SSDO (0x02 << 6)
811#define S3C2400_GPG3_I2SSDI (0x03 << 6) 815#define S3C2400_GPG3_I2SSDI (0x03 << 6)
812 816