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authorSonic Zhang <sonic.zhang@analog.com>2008-01-27 03:32:31 -0500
committerBryan Wu <bryan.wu@analog.com>2008-01-27 03:32:31 -0500
commit971d5bc4e5c75bfc4466deaff09839cd6f918eca (patch)
tree1a3259e1c00c519e71e0f0842de3ec257781482c /include
parentb03b08ba9c7235861adf4dde712dade0bb756fe0 (diff)
[Blackfin] arch: Fix bug to Enable bf548 to Re-program Clocks while Kernel boots.
Reprogram DDR EBIU register properly for bf548. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/mach-bf548/defBF54x_base.h31
-rw-r--r--include/asm-blackfin/mach-bf548/mem_init.h61
2 files changed, 89 insertions, 3 deletions
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 319a48590c9c..08f90c21fe8a 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -1772,17 +1772,36 @@
1772#define TRP 0x3c0000 /* Pre charge-to-active command period */ 1772#define TRP 0x3c0000 /* Pre charge-to-active command period */
1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */ 1773#define TRAS 0x3c00000 /* Min Active-to-pre charge time */
1774#define TRC 0x3c000000 /* Active-to-active time */ 1774#define TRC 0x3c000000 /* Active-to-active time */
1775#define DDR_TRAS(x) ((x<<22)&TRAS) /* DDR tRAS = (1~15) cycles */
1776#define DDR_TRP(x) ((x<<18)&TRP) /* DDR tRP = (1~15) cycles */
1777#define DDR_TRC(x) ((x<<26)&TRC) /* DDR tRC = (1~15) cycles */
1778#define DDR_TRFC(x) ((x<<14)&TRFC) /* DDR tRFC = (1~15) cycles */
1779#define DDR_TREFI(x) (x&TREFI) /* DDR tRFC = (1~15) cycles */
1775 1780
1776/* Bit masks for EBIU_DDRCTL1 */ 1781/* Bit masks for EBIU_DDRCTL1 */
1777 1782
1778#define TRCD 0xf /* Active-to-Read/write delay */ 1783#define TRCD 0xf /* Active-to-Read/write delay */
1779#define MRD 0xf0 /* Mode register set to active */ 1784#define TMRD 0xf0 /* Mode register set to active */
1780#define TWR 0x300 /* Write Recovery time */ 1785#define TWR 0x300 /* Write Recovery time */
1781#define DDRDATWIDTH 0x3000 /* DDR data width */ 1786#define DDRDATWIDTH 0x3000 /* DDR data width */
1782#define EXTBANKS 0xc000 /* External banks */ 1787#define EXTBANKS 0xc000 /* External banks */
1783#define DDRDEVWIDTH 0x30000 /* DDR device width */ 1788#define DDRDEVWIDTH 0x30000 /* DDR device width */
1784#define DDRDEVSIZE 0xc0000 /* DDR device size */ 1789#define DDRDEVSIZE 0xc0000 /* DDR device size */
1785#define TWWTR 0xf0000000 /* Write-to-read delay */ 1790#define TWTR 0xf0000000 /* Write-to-read delay */
1791#define DDR_TWTR(x) ((x<<28)&TWTR) /* DDR tWTR = (1~15) cycles */
1792#define DDR_TMRD(x) ((x<<4)&TMRD) /* DDR tMRD = (1~15) cycles */
1793#define DDR_TWR(x) ((x<<8)&TWR) /* DDR tWR = (1~15) cycles */
1794#define DDR_TRCD(x) (x&TRCD) /* DDR tRCD = (1~15) cycles */
1795#define DDR_DATWIDTH 0x2000 /* DDR data width */
1796#define EXTBANK_1 0 /* 1 external bank */
1797#define EXTBANK_2 0x4000 /* 2 external banks */
1798#define DEVSZ_64 0x40000 /* DDR External Bank Size = 64MB */
1799#define DEVSZ_128 0x80000 /* DDR External Bank Size = 128MB */
1800#define DEVSZ_256 0xc0000 /* DDR External Bank Size = 256MB */
1801#define DEVSZ_512 0 /* DDR External Bank Size = 512MB */
1802#define DEVWD_4 0 /* DDR Device Width = 4 Bits */
1803#define DEVWD_8 0x10000 /* DDR Device Width = 8 Bits */
1804#define DEVWD_16 0x20000 /* DDR Device Width = 16 Bits */
1786 1805
1787/* Bit masks for EBIU_DDRCTL2 */ 1806/* Bit masks for EBIU_DDRCTL2 */
1788 1807
@@ -1790,6 +1809,10 @@
1790#define CASLATENCY 0x70 /* CAS latency */ 1809#define CASLATENCY 0x70 /* CAS latency */
1791#define DLLRESET 0x100 /* DLL Reset */ 1810#define DLLRESET 0x100 /* DLL Reset */
1792#define REGE 0x1000 /* Register mode enable */ 1811#define REGE 0x1000 /* Register mode enable */
1812#define CL_1_5 0x50 /* DDR CAS Latency = 1.5 cycles */
1813#define CL_2 0x20 /* DDR CAS Latency = 2 cycles */
1814#define CL_2_5 0x60 /* DDR CAS Latency = 2.5 cycles */
1815#define CL_3 0x30 /* DDR CAS Latency = 3 cycles */
1793 1816
1794/* Bit masks for EBIU_DDRCTL3 */ 1817/* Bit masks for EBIU_DDRCTL3 */
1795 1818
@@ -2257,6 +2280,10 @@
2257 2280
2258#define CSEL 0x30 /* Core Select */ 2281#define CSEL 0x30 /* Core Select */
2259#define SSEL 0xf /* System Select */ 2282#define SSEL 0xf /* System Select */
2283#define CSEL_DIV1 0x0000 /* CCLK = VCO / 1 */
2284#define CSEL_DIV2 0x0010 /* CCLK = VCO / 2 */
2285#define CSEL_DIV4 0x0020 /* CCLK = VCO / 4 */
2286#define CSEL_DIV8 0x0030 /* CCLK = VCO / 8 */
2260 2287
2261/* Bit masks for PLL_CTL */ 2288/* Bit masks for PLL_CTL */
2262 2289
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
index e792eb7ae6a0..befc2903d5a5 100644
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ b/include/asm-blackfin/mach-bf548/mem_init.h
@@ -28,10 +28,69 @@
28 * If not, write to the Free Software Foundation, 28 * If not, write to the Free Software Foundation,
29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 29 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 */ 30 */
31#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
31 32
32#if (CONFIG_MEM_MT46V32M16) 33#if (CONFIG_MEM_MT46V32M16_6T)
34#define DDR_SIZE DEVSZ_512
35#define DDR_WIDTH DEVWD_16
36
37#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
38#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
39#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
40#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
41#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
42
43#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
44#define DDR_tWTR DDR_TWTR(1)
45#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
46#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
47#endif
48
49#if (CONFIG_MEM_MT46V32M16_5B)
50#define DDR_SIZE DEVSZ_512
51#define DDR_WIDTH DEVWD_16
52
53#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
54#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
55#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
56#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
57#define DDR_tREFI DDR_TREFI(MIN_DDR_SCLK(7800))
58
59#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
60#define DDR_tWTR DDR_TWTR(2)
61#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
62#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
63#endif
64
65#if (CONFIG_MEM_GENERIC_BOARD)
66#define DDR_SIZE DEVSZ_512
67#define DDR_WIDTH DEVWD_16
68
69#define DDR_tRCD DDR_TRCD(3)
70#define DDR_tWTR DDR_TWTR(2)
71#define DDR_tWR DDR_TWR(2)
72#define DDR_tMRD DDR_TMRD(2)
73#define DDR_tRP DDR_TRP(3)
74#define DDR_tRAS DDR_TRAS(7)
75#define DDR_tRC DDR_TRC(10)
76#define DDR_tRFC DDR_TRFC(12)
77#define DDR_tREFI DDR_TREFI(1288)
33#endif 78#endif
34 79
80#if (CONFIG_SCLK_HZ <= 133333333)
81#define DDR_CL CL_2
82#elif (CONFIG_SCLK_HZ <= 166666666)
83#define DDR_CL CL_2_5
84#else
85#define DDR_CL CL_3
86#endif
87
88#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
89#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
90 | DDR_tMRD | DDR_tWR | DDR_tRCD)
91#define mem_DDRCTL2 DDR_CL
92
93
35#if defined CONFIG_CLKIN_HALF 94#if defined CONFIG_CLKIN_HALF
36#define CLKIN_HALF 1 95#define CLKIN_HALF 1
37#else 96#else