PCI: add latency tolerance reporting enable/disable support

Latency tolerance reporting allows devices to send messages to the root
complex indicating their latency tolerance for snooped & unsnooped
memory transactions.  Add support for enabling & disabling this
feature, along with a routine to set the max latencies a device should
send upstream.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>

2 files changed, 14 insertions, 0 deletions

diff --git a/include/linux/pci.h b/include/linux/pci.h
index 45a035cccd93..df4d69b82144 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -840,6 +840,11 @@ enum pci_obff_signal_type {
 int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
 void pci_disable_obff(struct pci_dev *dev);
 
+bool pci_ltr_supported(struct pci_dev *dev);
+int pci_enable_ltr(struct pci_dev *dev);
+void pci_disable_ltr(struct pci_dev *dev);
+int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
+
 /* For use by arch with custom probe code */
 void set_pcie_port_type(struct pci_dev *pdev);
 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index aa420261843d..e8840964aca1 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -508,6 +508,7 @@
 #define PCI_EXP_RTSTA_PENDING   0x20000 /* PME pending */
 #define PCI_EXP_DEVCAP2         36      /* Device Capabilities 2 */
 #define  PCI_EXP_DEVCAP2_ARI    0x20    /* Alternative Routing-ID */
+#define  PCI_EXP_DEVCAP2_LTR    0x800   /* Latency tolerance reporting */
 #define  PCI_EXP_OBFF_MASK      0xc0000 /* OBFF support mechanism */
 #define  PCI_EXP_OBFF_MSG       0x40000 /* New message signaling */
 #define  PCI_EXP_OBFF_WAKE      0x80000 /* Re-use WAKE# for OBFF */
@@ -515,6 +516,7 @@
 #define  PCI_EXP_DEVCTL2_ARI    0x20    /* Alternative Routing-ID */
 #define  PCI_EXP_IDO_REQ_EN     0x100   /* ID-based ordering request enable */
 #define  PCI_EXP_IDO_CMP_EN     0x200   /* ID-based ordering completion enable */
+#define  PCI_EXP_LTR_EN         0x400   /* Latency tolerance reporting */
 #define  PCI_EXP_OBFF_MSGA_EN   0x2000  /* OBFF enable with Message type A */
 #define  PCI_EXP_OBFF_MSGB_EN   0x4000  /* OBFF enable with Message type B */
 #define  PCI_EXP_OBFF_WAKE_EN   0x6000  /* OBFF using WAKE# signaling */
@@ -535,6 +537,7 @@
 #define PCI_EXT_CAP_ID_ARI      14
 #define PCI_EXT_CAP_ID_ATS      15
 #define PCI_EXT_CAP_ID_SRIOV    16
+#define PCI_EXT_CAP_ID_LTR      24
 
 /* Advanced Error Reporting */
 #define PCI_ERR_UNCOR_STATUS    4       /* Uncorrectable Error Status */
@@ -691,6 +694,12 @@
 #define  PCI_SRIOV_VFM_MO       0x2     /* Active.MigrateOut */
 #define  PCI_SRIOV_VFM_AV       0x3     /* Active.Available */
 
+#define PCI_LTR_MAX_SNOOP_LAT   0x4
+#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
+#define  PCI_LTR_VALUE_MASK     0x000003ff
+#define  PCI_LTR_SCALE_MASK     0x00001c00
+#define  PCI_LTR_SCALE_SHIFT    10
+
 /* Access Control Service */
 #define PCI_ACS_CAP             0x04    /* ACS Capability Register */
 #define  PCI_ACS_SV             0x01    /* Source Validation */