Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (21 commits)
  Blackfin Serial Driver: abstract away DLAB differences into header
  Blackfin Serial Driver: macro away the IER differences between processors
  [Blackfin] arch: remove useless IRQ_SW_INT defines
  [Blackfin] arch: protect linux/usb/musb.h include until the driver gets mainlined
  [Blackfin] arch: protect linux/usb/isp1362.h include until the driver gets mainlined
  [Blackfin] arch: add EBIU supporting for BF54x EZKIT SMSC LAN911x/LAN921x families embedded ethernet driver
  [Blackfin] arch: Set spi flash partition on bf527 as like bf548.
  [Blackfin] arch: fix bug - Remove module will not free L1 memory used
  [Blackfin] arch: fix wrong header name in comment
  [Blackfin] arch: Fix BUG - spi flash on bf527 ezkit would fail at mount
  [Blackfin] arch: add twi_lcd and twi_keypad i2c board info to bf527-ezkit
  [Blackfin] arch: Add physmap partition for BF527-EZkit
  [Blackfin] arch: fix gdb testing regression
  [Blackfin] arch: disable single stepping when delivering a signal
  [Blackfin] arch: Delete unused (copied from m68k) entries in asm-offsets.c.
  [Blackfin] arch: In the double fault handler, set up the PT_RETI slot
  [Blackfin] arch: Support for CPU_FREQ and NOHZ
  [Blackfin] arch: Functional power management support: Add CPU and platform voltage scaling support
  [Blackfin] arch: fix bug -  breaking the atomic sections code.
  [Blackfin] arch: Equalize include files: Add VR_CTL masks
  ...

15 files changed, 124 insertions, 35 deletions

diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
index 686cf83a5269..7f34cd384f12 100644
--- a/include/asm-blackfin/dpmc.h
+++ b/include/asm-blackfin/dpmc.h
@@ -1,7 +1,7 @@
 /*
  * include/asm-blackfin/dpmc.h -  Miscellaneous IOCTL commands for Dynamic Power
  *                              Management Controller Driver.
- * Copyright (C) 2004 Analog Device Inc.
+ * Copyright (C) 2004-2008 Analog Device Inc.
  *
  */
 #ifndef _BLACKFIN_DPMC_H_
@@ -65,6 +65,14 @@ void disable_wdog_timer(void);
 extern unsigned long get_cclk(void);
 extern unsigned long get_sclk(void);
 
+struct bfin_dpmc_platform_data {
+        const unsigned int *tuple_tab;
+        unsigned short tabsize;
+        unsigned short vr_settling_time; /* in us */
+};
+
+#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
+
 #endif  /* __KERNEL__ */
 
 #endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
index 562c6d3a3232..c4f721e0d00d 100644
--- a/include/asm-blackfin/entry.h
+++ b/include/asm-blackfin/entry.h
@@ -17,6 +17,11 @@
 #define PF_DTRACE_OFF   1
 #define PF_DTRACE_BIT   5
 
+/*
+ * NOTE!  The single-stepping code assumes that all interrupt handlers
+ * start by saving SYSCFG on the stack with their first instruction.
+ */
+
 /* This one is used for exceptions, emulation, and NMI.  It doesn't push
    RETI and doesn't do cli.  */
 #define SAVE_ALL_SYS            save_context_no_interrupts
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
index f0ab2736a680..26e3c8076b4e 100644
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
 #define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
 #define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
+#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
 #define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
 #define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
 
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
index fbe88dee3e2d..d016603b6615 100644
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
index 17e1548cec08..0ab4dd7494cf 100644
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -468,6 +468,8 @@
 #define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
 #define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
 #define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
+#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
 
 #define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
 #define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 832e6f6122da..5aa38e5da6b7 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -66,12 +66,13 @@ Core        Emulation               **
             DMA8/9 Interrupt        IVG13       28
             DMA10/11 Interrupt      IVG13       29
             Watchdog Timer          IVG13       30
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
+
+            Softirq                 IVG14       31
+            System Call    --
                  (lowest priority)  IVG15       32 *
  */
-#define SYS_IRQS                32
-#define NR_PERI_INTS    24
+#define SYS_IRQS        31
+#define NR_PERI_INTS    24
 
 /* The ABSTRACT IRQ definitions */
 /** the first seven of the following are fixed, the rest you change if you need to **/
@@ -96,7 +97,7 @@ Core        Emulation               **
 #define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
 #define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
 #define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
 #define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
 #define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
 #define IRQ_TMR0                23      /*Timer 0 */
@@ -108,9 +109,6 @@ Core        Emulation               **
 #define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
 #define IRQ_WATCH               30      /*Watch Dog Timer */
 
-#define IRQ_SW_INT1             31      /*Software Int 1 */
-#define IRQ_SW_INT2             32      /*Software Int 2 (reserved for SYSCALL) */
-
 #define IRQ_PF0                 33
 #define IRQ_PF1                 34
 #define IRQ_PF2                 35
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
index fd100a415b98..f79d1a0e9129 100644
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index be6f2ff77f31..2e68a8a1e730 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -34,24 +34,23 @@
 
 /*
  * Interrupt source definitions
-             Event Source    Core Event Name
-Core        Emulation               **
- Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-
-.....
-
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
-                 (lowest priority)  IVG15       32 *
+ *            Event Source    Core Event Name
+ * Core       Emulation               **
+ * Events         (highest priority)  EMU         0
+ *            Reset                   RST         1
+ *            NMI                     NMI         2
+ *            Exception               EVX         3
+ *            Reserved                --          4
+ *            Hardware Error          IVHW        5
+ *            Core Timer              IVTMR       6
+ *  .....
+ *
+ *            Softirq                 IVG14
+ *            System Call    --
+ *               (lowest priority)    IVG15
  */
 
-#define SYS_IRQS        41
+#define SYS_IRQS        39
 #define NR_PERI_INTS    32
 
 /* The ABSTRACT IRQ definitions */
@@ -95,10 +94,8 @@ Core        Emulation               **
 #define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
 #define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
 #define IRQ_MEM_DMA1        37  /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB       38  /* PF Ports F (PF15:0) Interrupt B */
+#define IRQ_PROG_INTB         38        /* PF Ports F (PF15:0) Interrupt B */
 #define IRQ_WATCH           38  /*Watch Dog Timer */
-#define IRQ_SW_INT1         40  /*Software Int 1 */
-#define IRQ_SW_INT2         41  /*Software Int 2 (reserved for SYSCALL) */
 
 #define IRQ_PPI_ERROR       42  /*PPI Error Interrupt */
 #define IRQ_CAN_ERROR       43  /*CAN Error Interrupt */
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
index 6547027cd3e6..5eb46a77d919 100644
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
@@ -54,6 +54,9 @@
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
 
+#define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
+#define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
+
 #if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
 # define CONFIG_SERIAL_BFIN_CTSRTS
 
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
index 08f90c21fe8a..e022e896cb18 100644
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h
@@ -2329,6 +2329,26 @@
 #define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
 #define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
 
+#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+
+#define GAIN_5                  0x0000  /* GAIN = 5*/
+#define GAIN_10                 0x0004  /* GAIN = 1*/
+#define GAIN_20                 0x0008  /* GAIN = 2*/
+#define GAIN_50                 0x000C  /* GAIN = 5*/
+
+#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
 /* Bit masks for NFC_CTL */
 
 #define                    WR_DLY  0xf        /* Write Strobe Delay */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
index 8a4e66d1db37..7a9628769296 100644
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -44,10 +44,15 @@
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
+#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 
+#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
+#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
+
 #ifdef CONFIG_BFIN_UART0_CTSRTS
 # define CONFIG_SERIAL_BFIN_CTSRTS
 # ifndef CONFIG_UART0_CTS_PIN
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 366c9b9a0cb7..1ab50e906fe7 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -868,6 +868,34 @@
 #define CHIPID_FAMILY          0x0FFFF000
 #define CHIPID_MANUFACTURE     0x00000FFE
 
+/* VR_CTL Masks                                                                                                                                 */
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
+#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
+#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
+#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
+
+#define GAIN                    0x000C  /* Voltage Level Gain   */
+#define GAIN_5                  0x0000  /* GAIN = 5*/
+#define GAIN_10                 0x0004  /* GAIN = 1*/
+#define GAIN_20                 0x0008  /* GAIN = 2*/
+#define GAIN_50                 0x000C  /* GAIN = 5*/
+
+#define VLEV                    0x00F0  /* Internal Voltage Level */
+#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
+#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
+#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
+#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
+#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
+#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
+#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
+#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
+#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
+#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
+#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
+
 /* PLL_DIV Masks */
 #define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
 
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 83f0383957d2..6698389c5564 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -118,12 +118,13 @@
             Supplemental interrupt 0            IVG7        69
             supplemental interrupt 1            IVG7        70
 
-            Software Interrupt 1                IVG14       71
-            Software Interrupt 2                IVG15       72 *
-                                                (lowest priority)
+            Softirq                             IVG14
+            System Call    --
+                 (lowest priority)              IVG15
+
  **********************************************************************/
 
-#define SYS_IRQS                72
+#define SYS_IRQS                71
 #define NR_PERI_INTS            64
 
 /*
@@ -237,9 +238,7 @@
 #define IRQ_RESERVED_2          (IVG_BASE + 61) /* Reserved interrupt       */
 #define IRQ_SUPPLE_0            (IVG_BASE + 62) /* Supplemental interrupt 0 */
 #define IRQ_SUPPLE_1            (IVG_BASE + 63) /* supplemental interrupt 1 */
-#define IRQ_SW_INT1             71      /* Software Interrupt 1     */
-#define IRQ_SW_INT2             72      /* Software Interrupt 2     */
-                                                /* reserved for SYSCALL */
+
 #define IRQ_PF0                 73
 #define IRQ_PF1                 74
 #define IRQ_PF2                 75
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
index fd0ebe1862b8..c0e630edfb9a 100644
--- a/include/asm-blackfin/mach-common/context.S
+++ b/include/asm-blackfin/mach-common/context.S
@@ -28,6 +28,11 @@
  */
 
 /*
+ * NOTE!  The single-stepping code assumes that all interrupt handlers
+ * start by saving SYSCFG on the stack with their first instruction.
+ */
+
+/*
  * Code to save processor context.
  *  We even save the register which are preserved by a function call
  *       - r4, r5, r6, r7, p3, p4, p5
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
index 6e5859b6ea32..ddc43ce38533 100644
--- a/include/asm-blackfin/time.h
+++ b/include/asm-blackfin/time.h
@@ -24,6 +24,8 @@
 
 #ifndef CONFIG_CPU_FREQ
 #define TIME_SCALE 1
+#define __bfin_cycles_off (0)
+#define __bfin_cycles_mod (0)
 #else
 /*
  * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
@@ -31,6 +33,8 @@
  * adjust the Core Timer Presale Register. This way we don't lose time.
  */
 #define TIME_SCALE 4
+extern unsigned long long __bfin_cycles_off;
+extern unsigned int __bfin_cycles_mod;
 #endif
 
 #endif