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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-04 10:49:37 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-04 10:49:37 -0500
commit03a2c4d76c9e99b80d74ab8a4f344e135a5ae44b (patch)
tree7fd7940a4f87dc1ace1c1bdeb1fb0d90ac3beb13 /include
parenta27341cd5fcb7cf2d2d4726e9f324009f7162c00 (diff)
parentd424b925f7092b9d95e0a8556872349abe79d9b6 (diff)
Merge branch 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (151 commits) vga_switcheroo: disable default y by new rules. drm/nouveau: fix *staging* driver build with switcheroo off. drm/radeon: fix typo in Makefile vga_switcheroo: fix build on platforms with no ACPI drm/radeon: Fix printf type warning in 64bit system. drm/radeon/kms: bump the KMS version number for square tiling support. vga_switcheroo: initial implementation (v15) drm/radeon/kms: do not disable audio engine twice Revert "drm/radeon/kms: disable HDMI audio for now on rv710/rv730" drm/radeon/kms: do not preset audio stuff and start timer when not using audio drm/radeon: r100/r200 ums: block ability for userspace app to trash 0 page and beyond drm/ttm: fix function prototype to match implementation drm/radeon: use ALIGN instead of open coding it drm/radeon/kms: initialize set_surface_reg reg for rs600 asic drm/i915: Use a dmi quirk to skip a broken SDVO TV output. drm/i915: enable/disable LVDS port at DPMS time drm/i915: check for multiple write domains in pin_and_relocate drm/i915: clean-up i915_gem_flush_gpu_write_domain drm/i915: reuse i915_gpu_idle helper drm/i915: ensure lru ordering of fence_list ... Fixed trivial conflicts in drivers/gpu/vga/Kconfig
Diffstat (limited to 'include')
-rw-r--r--include/drm/drmP.h28
-rw-r--r--include/drm/drm_buffer.h148
-rw-r--r--include/drm/drm_crtc.h2
-rw-r--r--include/drm/drm_edid.h3
-rw-r--r--include/drm/drm_pciids.h36
-rw-r--r--include/drm/nouveau_drm.h86
-rw-r--r--include/drm/radeon_drm.h1
-rw-r--r--include/drm/ttm/ttm_bo_driver.h2
-rw-r--r--include/linux/fb.h2
-rw-r--r--include/linux/vga_switcheroo.h57
10 files changed, 307 insertions, 58 deletions
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index ffac157fb5b2..4a3c4e441027 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -801,6 +801,7 @@ struct drm_driver {
801 */ 801 */
802 int (*gem_init_object) (struct drm_gem_object *obj); 802 int (*gem_init_object) (struct drm_gem_object *obj);
803 void (*gem_free_object) (struct drm_gem_object *obj); 803 void (*gem_free_object) (struct drm_gem_object *obj);
804 void (*gem_free_object_unlocked) (struct drm_gem_object *obj);
804 805
805 /* vga arb irq handler */ 806 /* vga arb irq handler */
806 void (*vgaarb_irq)(struct drm_device *dev, bool state); 807 void (*vgaarb_irq)(struct drm_device *dev, bool state);
@@ -1427,6 +1428,7 @@ extern void drm_sysfs_connector_remove(struct drm_connector *connector);
1427int drm_gem_init(struct drm_device *dev); 1428int drm_gem_init(struct drm_device *dev);
1428void drm_gem_destroy(struct drm_device *dev); 1429void drm_gem_destroy(struct drm_device *dev);
1429void drm_gem_object_free(struct kref *kref); 1430void drm_gem_object_free(struct kref *kref);
1431void drm_gem_object_free_unlocked(struct kref *kref);
1430struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev, 1432struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev,
1431 size_t size); 1433 size_t size);
1432void drm_gem_object_handle_free(struct kref *kref); 1434void drm_gem_object_handle_free(struct kref *kref);
@@ -1443,10 +1445,15 @@ drm_gem_object_reference(struct drm_gem_object *obj)
1443static inline void 1445static inline void
1444drm_gem_object_unreference(struct drm_gem_object *obj) 1446drm_gem_object_unreference(struct drm_gem_object *obj)
1445{ 1447{
1446 if (obj == NULL) 1448 if (obj != NULL)
1447 return; 1449 kref_put(&obj->refcount, drm_gem_object_free);
1450}
1448 1451
1449 kref_put(&obj->refcount, drm_gem_object_free); 1452static inline void
1453drm_gem_object_unreference_unlocked(struct drm_gem_object *obj)
1454{
1455 if (obj != NULL)
1456 kref_put(&obj->refcount, drm_gem_object_free_unlocked);
1450} 1457}
1451 1458
1452int drm_gem_handle_create(struct drm_file *file_priv, 1459int drm_gem_handle_create(struct drm_file *file_priv,
@@ -1475,6 +1482,21 @@ drm_gem_object_handle_unreference(struct drm_gem_object *obj)
1475 drm_gem_object_unreference(obj); 1482 drm_gem_object_unreference(obj);
1476} 1483}
1477 1484
1485static inline void
1486drm_gem_object_handle_unreference_unlocked(struct drm_gem_object *obj)
1487{
1488 if (obj == NULL)
1489 return;
1490
1491 /*
1492 * Must bump handle count first as this may be the last
1493 * ref, in which case the object would disappear before we
1494 * checked for a name
1495 */
1496 kref_put(&obj->handlecount, drm_gem_object_handle_free);
1497 drm_gem_object_unreference_unlocked(obj);
1498}
1499
1478struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev, 1500struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
1479 struct drm_file *filp, 1501 struct drm_file *filp,
1480 u32 handle); 1502 u32 handle);
diff --git a/include/drm/drm_buffer.h b/include/drm/drm_buffer.h
new file mode 100644
index 000000000000..322dbff3f861
--- /dev/null
+++ b/include/drm/drm_buffer.h
@@ -0,0 +1,148 @@
1/**************************************************************************
2 *
3 * Copyright 2010 Pauli Nieminen.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 *
27 **************************************************************************/
28/*
29 * Multipart buffer for coping data which is larger than the page size.
30 *
31 * Authors:
32 * Pauli Nieminen <suokkos-at-gmail-dot-com>
33 */
34
35#ifndef _DRM_BUFFER_H_
36#define _DRM_BUFFER_H_
37
38#include "drmP.h"
39
40struct drm_buffer {
41 int iterator;
42 int size;
43 char *data[];
44};
45
46
47/**
48 * Return the index of page that buffer is currently pointing at.
49 */
50static inline int drm_buffer_page(struct drm_buffer *buf)
51{
52 return buf->iterator / PAGE_SIZE;
53}
54/**
55 * Return the index of the current byte in the page
56 */
57static inline int drm_buffer_index(struct drm_buffer *buf)
58{
59 return buf->iterator & (PAGE_SIZE - 1);
60}
61/**
62 * Return number of bytes that is left to process
63 */
64static inline int drm_buffer_unprocessed(struct drm_buffer *buf)
65{
66 return buf->size - buf->iterator;
67}
68
69/**
70 * Advance the buffer iterator number of bytes that is given.
71 */
72static inline void drm_buffer_advance(struct drm_buffer *buf, int bytes)
73{
74 buf->iterator += bytes;
75}
76
77/**
78 * Allocate the drm buffer object.
79 *
80 * buf: A pointer to a pointer where the object is stored.
81 * size: The number of bytes to allocate.
82 */
83extern int drm_buffer_alloc(struct drm_buffer **buf, int size);
84
85/**
86 * Copy the user data to the begin of the buffer and reset the processing
87 * iterator.
88 *
89 * user_data: A pointer the data that is copied to the buffer.
90 * size: The Number of bytes to copy.
91 */
92extern int drm_buffer_copy_from_user(struct drm_buffer *buf,
93 void __user *user_data, int size);
94
95/**
96 * Free the drm buffer object
97 */
98extern void drm_buffer_free(struct drm_buffer *buf);
99
100/**
101 * Read an object from buffer that may be split to multiple parts. If object
102 * is not split function just returns the pointer to object in buffer. But in
103 * case of split object data is copied to given stack object that is suplied
104 * by caller.
105 *
106 * The processing location of the buffer is also advanced to the next byte
107 * after the object.
108 *
109 * objsize: The size of the objet in bytes.
110 * stack_obj: A pointer to a memory location where object can be copied.
111 */
112extern void *drm_buffer_read_object(struct drm_buffer *buf,
113 int objsize, void *stack_obj);
114
115/**
116 * Returns the pointer to the dword which is offset number of elements from the
117 * current processing location.
118 *
119 * Caller must make sure that dword is not split in the buffer. This
120 * requirement is easily met if all the sizes of objects in buffer are
121 * multiples of dword and PAGE_SIZE is multiple dword.
122 *
123 * Call to this function doesn't change the processing location.
124 *
125 * offset: The index of the dword relative to the internat iterator.
126 */
127static inline void *drm_buffer_pointer_to_dword(struct drm_buffer *buffer,
128 int offset)
129{
130 int iter = buffer->iterator + offset * 4;
131 return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
132}
133/**
134 * Returns the pointer to the dword which is offset number of elements from
135 * the current processing location.
136 *
137 * Call to this function doesn't change the processing location.
138 *
139 * offset: The index of the byte relative to the internat iterator.
140 */
141static inline void *drm_buffer_pointer_to_byte(struct drm_buffer *buffer,
142 int offset)
143{
144 int iter = buffer->iterator + offset;
145 return &buffer->data[iter / PAGE_SIZE][iter & (PAGE_SIZE - 1)];
146}
147
148#endif
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index fdf43abc36db..1347524a8e30 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -801,4 +801,6 @@ extern struct drm_display_mode *drm_gtf_mode(struct drm_device *dev,
801 bool interlaced, int margins); 801 bool interlaced, int margins);
802extern int drm_add_modes_noedid(struct drm_connector *connector, 802extern int drm_add_modes_noedid(struct drm_connector *connector,
803 int hdisplay, int vdisplay); 803 int hdisplay, int vdisplay);
804
805extern bool drm_edid_is_valid(struct edid *edid);
804#endif /* __DRM_CRTC_H__ */ 806#endif /* __DRM_CRTC_H__ */
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index d33c3e038606..b4209898f115 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -201,4 +201,7 @@ struct edid {
201 201
202#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 202#define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8))
203 203
204/* define the number of Extension EDID block */
205#define DRM_MAX_EDID_EXT_NUM 4
206
204#endif /* __DRM_EDID_H__ */ 207#endif /* __DRM_EDID_H__ */
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index e6f3b120f51a..676104b7818c 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -141,6 +141,41 @@
141 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 141 {0x1002, 0x5e4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
142 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 142 {0x1002, 0x5e4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
143 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \ 143 {0x1002, 0x5e4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x6880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x6888, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x6889, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
147 {0x1002, 0x688A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
148 {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
149 {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
150 {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
151 {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
152 {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
153 {0x1002, 0x68a0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
154 {0x1002, 0x68a1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
155 {0x1002, 0x68a8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x68a9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
158 {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
159 {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
160 {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
161 {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
162 {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
163 {0x1002, 0x68c8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
164 {0x1002, 0x68c9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
165 {0x1002, 0x68d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
166 {0x1002, 0x68d9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
167 {0x1002, 0x68da, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
168 {0x1002, 0x68de, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_NEW_MEMMAP}, \
169 {0x1002, 0x68e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
170 {0x1002, 0x68e1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
171 {0x1002, 0x68e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
172 {0x1002, 0x68e5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
173 {0x1002, 0x68e8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
174 {0x1002, 0x68e9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
175 {0x1002, 0x68f1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
176 {0x1002, 0x68f8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
177 {0x1002, 0x68f9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
178 {0x1002, 0x68fe, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CEDAR|RADEON_NEW_MEMMAP}, \
144 {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \ 179 {0x1002, 0x7100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_NEW_MEMMAP}, \
145 {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 180 {0x1002, 0x7101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
146 {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 181 {0x1002, 0x7102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R520|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -558,4 +593,5 @@
558 {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ 593 {0x8086, 0x35e8, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
559 {0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ 594 {0x8086, 0x0042, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
560 {0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \ 595 {0x8086, 0x0046, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
596 {0x8086, 0x0102, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA << 8, 0xffff00, 0}, \
561 {0, 0, 0} 597 {0, 0, 0}
diff --git a/include/drm/nouveau_drm.h b/include/drm/nouveau_drm.h
index f745948b61e4..a6a9f4af5ebd 100644
--- a/include/drm/nouveau_drm.h
+++ b/include/drm/nouveau_drm.h
@@ -25,13 +25,14 @@
25#ifndef __NOUVEAU_DRM_H__ 25#ifndef __NOUVEAU_DRM_H__
26#define __NOUVEAU_DRM_H__ 26#define __NOUVEAU_DRM_H__
27 27
28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15 28#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
29 29
30struct drm_nouveau_channel_alloc { 30struct drm_nouveau_channel_alloc {
31 uint32_t fb_ctxdma_handle; 31 uint32_t fb_ctxdma_handle;
32 uint32_t tt_ctxdma_handle; 32 uint32_t tt_ctxdma_handle;
33 33
34 int channel; 34 int channel;
35 uint32_t pushbuf_domains;
35 36
36 /* Notifier memory */ 37 /* Notifier memory */
37 uint32_t notifier_handle; 38 uint32_t notifier_handle;
@@ -109,68 +110,58 @@ struct drm_nouveau_gem_new {
109 uint32_t align; 110 uint32_t align;
110}; 111};
111 112
113#define NOUVEAU_GEM_MAX_BUFFERS 1024
114struct drm_nouveau_gem_pushbuf_bo_presumed {
115 uint32_t valid;
116 uint32_t domain;
117 uint64_t offset;
118};
119
112struct drm_nouveau_gem_pushbuf_bo { 120struct drm_nouveau_gem_pushbuf_bo {
113 uint64_t user_priv; 121 uint64_t user_priv;
114 uint32_t handle; 122 uint32_t handle;
115 uint32_t read_domains; 123 uint32_t read_domains;
116 uint32_t write_domains; 124 uint32_t write_domains;
117 uint32_t valid_domains; 125 uint32_t valid_domains;
118 uint32_t presumed_ok; 126 struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
119 uint32_t presumed_domain;
120 uint64_t presumed_offset;
121}; 127};
122 128
123#define NOUVEAU_GEM_RELOC_LOW (1 << 0) 129#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
124#define NOUVEAU_GEM_RELOC_HIGH (1 << 1) 130#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
125#define NOUVEAU_GEM_RELOC_OR (1 << 2) 131#define NOUVEAU_GEM_RELOC_OR (1 << 2)
132#define NOUVEAU_GEM_MAX_RELOCS 1024
126struct drm_nouveau_gem_pushbuf_reloc { 133struct drm_nouveau_gem_pushbuf_reloc {
134 uint32_t reloc_bo_index;
135 uint32_t reloc_bo_offset;
127 uint32_t bo_index; 136 uint32_t bo_index;
128 uint32_t reloc_index;
129 uint32_t flags; 137 uint32_t flags;
130 uint32_t data; 138 uint32_t data;
131 uint32_t vor; 139 uint32_t vor;
132 uint32_t tor; 140 uint32_t tor;
133}; 141};
134 142
135#define NOUVEAU_GEM_MAX_BUFFERS 1024 143#define NOUVEAU_GEM_MAX_PUSH 512
136#define NOUVEAU_GEM_MAX_RELOCS 1024 144struct drm_nouveau_gem_pushbuf_push {
145 uint32_t bo_index;
146 uint32_t pad;
147 uint64_t offset;
148 uint64_t length;
149};
137 150
138struct drm_nouveau_gem_pushbuf { 151struct drm_nouveau_gem_pushbuf {
139 uint32_t channel; 152 uint32_t channel;
140 uint32_t nr_dwords;
141 uint32_t nr_buffers; 153 uint32_t nr_buffers;
142 uint32_t nr_relocs;
143 uint64_t dwords;
144 uint64_t buffers; 154 uint64_t buffers;
145 uint64_t relocs;
146};
147
148struct drm_nouveau_gem_pushbuf_call {
149 uint32_t channel;
150 uint32_t handle;
151 uint32_t offset;
152 uint32_t nr_buffers;
153 uint32_t nr_relocs; 155 uint32_t nr_relocs;
154 uint32_t nr_dwords; 156 uint32_t nr_push;
155 uint64_t buffers;
156 uint64_t relocs; 157 uint64_t relocs;
158 uint64_t push;
157 uint32_t suffix0; 159 uint32_t suffix0;
158 uint32_t suffix1; 160 uint32_t suffix1;
159 /* below only accessed for CALL2 */
160 uint64_t vram_available; 161 uint64_t vram_available;
161 uint64_t gart_available; 162 uint64_t gart_available;
162}; 163};
163 164
164struct drm_nouveau_gem_pin {
165 uint32_t handle;
166 uint32_t domain;
167 uint64_t offset;
168};
169
170struct drm_nouveau_gem_unpin {
171 uint32_t handle;
172};
173
174#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001 165#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
175#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002 166#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
176#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004 167#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
@@ -183,14 +174,6 @@ struct drm_nouveau_gem_cpu_fini {
183 uint32_t handle; 174 uint32_t handle;
184}; 175};
185 176
186struct drm_nouveau_gem_tile {
187 uint32_t handle;
188 uint32_t offset;
189 uint32_t size;
190 uint32_t tile_mode;
191 uint32_t tile_flags;
192};
193
194enum nouveau_bus_type { 177enum nouveau_bus_type {
195 NV_AGP = 0, 178 NV_AGP = 0,
196 NV_PCI = 1, 179 NV_PCI = 1,
@@ -200,22 +183,17 @@ enum nouveau_bus_type {
200struct drm_nouveau_sarea { 183struct drm_nouveau_sarea {
201}; 184};
202 185
203#define DRM_NOUVEAU_CARD_INIT 0x00 186#define DRM_NOUVEAU_GETPARAM 0x00
204#define DRM_NOUVEAU_GETPARAM 0x01 187#define DRM_NOUVEAU_SETPARAM 0x01
205#define DRM_NOUVEAU_SETPARAM 0x02 188#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
206#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03 189#define DRM_NOUVEAU_CHANNEL_FREE 0x03
207#define DRM_NOUVEAU_CHANNEL_FREE 0x04 190#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
208#define DRM_NOUVEAU_GROBJ_ALLOC 0x05 191#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
209#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06 192#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
210#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
211#define DRM_NOUVEAU_GEM_NEW 0x40 193#define DRM_NOUVEAU_GEM_NEW 0x40
212#define DRM_NOUVEAU_GEM_PUSHBUF 0x41 194#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
213#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42 195#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
214#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */ 196#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
215#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */ 197#define DRM_NOUVEAU_GEM_INFO 0x44
216#define DRM_NOUVEAU_GEM_CPU_PREP 0x45
217#define DRM_NOUVEAU_GEM_CPU_FINI 0x46
218#define DRM_NOUVEAU_GEM_INFO 0x47
219#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48
220 198
221#endif /* __NOUVEAU_DRM_H__ */ 199#endif /* __NOUVEAU_DRM_H__ */
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 39537f3cf98a..81e614bf2dc3 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -808,6 +808,7 @@ struct drm_radeon_gem_create {
808#define RADEON_TILING_SWAP_32BIT 0x8 808#define RADEON_TILING_SWAP_32BIT 0x8
809#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface 809#define RADEON_TILING_SURFACE 0x10 /* this object requires a surface
810 * when mapped - i.e. front buffer */ 810 * when mapped - i.e. front buffer */
811#define RADEON_TILING_MICRO_SQUARE 0x20
811 812
812struct drm_radeon_gem_set_tiling { 813struct drm_radeon_gem_set_tiling {
813 uint32_t handle; 814 uint32_t handle;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index 4c4e0f8375b3..e3f1b4a4b601 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -908,7 +908,7 @@ extern int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo,
908 * Utility function that returns the pgprot_t that should be used for 908 * Utility function that returns the pgprot_t that should be used for
909 * setting up a PTE with the caching model indicated by @c_state. 909 * setting up a PTE with the caching model indicated by @c_state.
910 */ 910 */
911extern pgprot_t ttm_io_prot(enum ttm_caching_state c_state, pgprot_t tmp); 911extern pgprot_t ttm_io_prot(uint32_t caching_flags, pgprot_t tmp);
912 912
913#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE))) 913#if (defined(CONFIG_AGP) || (defined(CONFIG_AGP_MODULE) && defined(MODULE)))
914#define TTM_HAS_AGP 914#define TTM_HAS_AGP
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 369767bd873e..c10163b4c40e 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -543,6 +543,8 @@ struct fb_cursor_user {
543#define FB_EVENT_GET_REQ 0x0D 543#define FB_EVENT_GET_REQ 0x0D
544/* Unbind from the console if possible */ 544/* Unbind from the console if possible */
545#define FB_EVENT_FB_UNBIND 0x0E 545#define FB_EVENT_FB_UNBIND 0x0E
546/* CONSOLE-SPECIFIC: remap all consoles to new fb - for vga switcheroo */
547#define FB_EVENT_REMAP_ALL_CONSOLE 0x0F
546 548
547struct fb_event { 549struct fb_event {
548 struct fb_info *info; 550 struct fb_info *info;
diff --git a/include/linux/vga_switcheroo.h b/include/linux/vga_switcheroo.h
new file mode 100644
index 000000000000..ae9ab13b963d
--- /dev/null
+++ b/include/linux/vga_switcheroo.h
@@ -0,0 +1,57 @@
1/*
2 * Copyright (c) 2010 Red Hat Inc.
3 * Author : Dave Airlie <airlied@redhat.com>
4 *
5 * Licensed under GPLv2
6 *
7 * vga_switcheroo.h - Support for laptop with dual GPU using one set of outputs
8 */
9
10#include <linux/fb.h>
11
12enum vga_switcheroo_state {
13 VGA_SWITCHEROO_OFF,
14 VGA_SWITCHEROO_ON,
15};
16
17enum vga_switcheroo_client_id {
18 VGA_SWITCHEROO_IGD,
19 VGA_SWITCHEROO_DIS,
20 VGA_SWITCHEROO_MAX_CLIENTS,
21};
22
23struct vga_switcheroo_handler {
24 int (*switchto)(enum vga_switcheroo_client_id id);
25 int (*power_state)(enum vga_switcheroo_client_id id,
26 enum vga_switcheroo_state state);
27 int (*init)(void);
28 int (*get_client_id)(struct pci_dev *pdev);
29};
30
31
32#if defined(CONFIG_VGA_SWITCHEROO)
33void vga_switcheroo_unregister_client(struct pci_dev *dev);
34int vga_switcheroo_register_client(struct pci_dev *dev,
35 void (*set_gpu_state)(struct pci_dev *dev, enum vga_switcheroo_state),
36 bool (*can_switch)(struct pci_dev *dev));
37
38void vga_switcheroo_client_fb_set(struct pci_dev *dev,
39 struct fb_info *info);
40
41int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler);
42void vga_switcheroo_unregister_handler(void);
43
44int vga_switcheroo_process_delayed_switch(void);
45
46#else
47
48static inline void vga_switcheroo_unregister_client(struct pci_dev *dev) {}
49static inline int vga_switcheroo_register_client(struct pci_dev *dev,
50 void (*set_gpu_state)(struct pci_dev *dev, enum vga_switcheroo_state),
51 bool (*can_switch)(struct pci_dev *dev)) { return 0; }
52static inline void vga_switcheroo_client_fb_set(struct pci_dev *dev, struct fb_info *info) {}
53static inline int vga_switcheroo_register_handler(struct vga_switcheroo_handler *handler) { return 0; }
54static inline void vga_switcheroo_unregister_handler(void) {}
55static inline int vga_switcheroo_process_delayed_switch(void) { return 0; }
56
57#endif