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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-26 22:40:27 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-11-26 22:40:27 -0500
commitb5faa4b89e4d83203b1f44f143a351b518f7cda2 (patch)
tree1d195fa302af8f156b049fa548008360f16a78d5 /include
parenta039767f8d7eeb0731c4053d43c0d8caa27d69d0 (diff)
parent233b28a91caf7cff326e604c437a364eaf794106 (diff)
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cooloney/blackfin-2.6: (56 commits) Blackfin arch: fix bug when enable uart1 with uart0 disabled => no initial console Blackfin arch: split apart dump_bfin_regs and merge/remove show_regs from process.c, which was largely duplicated Blackfin arch: use common __INIT/__FINIT defines rather than setting the .section ourselves to .init.text Blackfin arch: fix bug when sending signals with the wrong PC, cause gdb get confused Blackfin arch: Ensure we printk out strings with the proper loglevel Blackfin arch: Need to specify ax with the .init.text section, Blackfin arch: Update Kconfig to latest Blackfin silicon datasheets Blackfin arch: update defconfig files Blackfin arch: Fix typo, and add ENDPROC - no functional changes Blackfin arch: convert READY to DMA_READY as it causes build errors in common sound code otherwise Blackfin arch: add defines for the on-chip L1 ROM of BF54x Blackfin arch: cplb and map header file cleanup Blackfin arch: cleanup the cplb declares Blackfin arch: fix broken on BF52x, remove silly checks on processors for L1_SCRATCH defines Blackfin arch: add support for working around anomaly 05000312 Blackfin arch: cleanup BF54x header file and add BF547 definition Blackfin arch: fix building for BF542 processors which only have 1 TWI Blackfin arch: rename _return_from_exception to _bfin_return_from_exception and export it Blackfin arch: move EXPORT_SYMBOL() to C files where the symbol is actually defined Blackfin arch: fix bug NOR Flash MTD mount fail ...
Diffstat (limited to 'include')
-rw-r--r--include/asm-blackfin/bfin-global.h5
-rw-r--r--include/asm-blackfin/cplbinit.h33
-rw-r--r--include/asm-blackfin/delay.h66
-rw-r--r--include/asm-blackfin/io.h1
-rw-r--r--include/asm-blackfin/mach-bf527/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf527/mem_map.h3
-rw-r--r--include/asm-blackfin/mach-bf533/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h4
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h3
-rw-r--r--include/asm-blackfin/mach-bf548/bf548.h34
-rw-r--r--include/asm-blackfin/mach-bf548/defBF544.h2
-rw-r--r--include/asm-blackfin/mach-bf548/defBF548.h2
-rw-r--r--include/asm-blackfin/mach-bf548/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf548/mem_map.h18
-rw-r--r--include/asm-blackfin/mach-bf561/bf561.h19
-rw-r--r--include/asm-blackfin/mach-bf561/defBF561.h15
-rw-r--r--include/asm-blackfin/mach-bf561/irq.h4
-rw-r--r--include/asm-blackfin/mach-bf561/mem_map.h7
-rw-r--r--include/asm-blackfin/mach-common/def_LPBlackfin.h8
-rw-r--r--include/asm-blackfin/page_offset.h2
-rw-r--r--include/asm-blackfin/string.h2
-rw-r--r--include/asm-blackfin/traps.h96
23 files changed, 190 insertions, 150 deletions
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
index 0212e180b90e..39bdd86871cf 100644
--- a/include/asm-blackfin/bfin-global.h
+++ b/include/asm-blackfin/bfin-global.h
@@ -50,8 +50,8 @@ extern unsigned long get_sclk(void);
50extern unsigned long sclk_to_usecs(unsigned long sclk); 50extern unsigned long sclk_to_usecs(unsigned long sclk);
51extern unsigned long usecs_to_sclk(unsigned long usecs); 51extern unsigned long usecs_to_sclk(unsigned long usecs);
52 52
53extern void dump_thread(struct pt_regs *regs, struct user *dump); 53extern void dump_bfin_process(struct pt_regs *regs);
54extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr); 54extern void dump_bfin_mem(void *retaddr);
55extern void dump_bfin_trace_buffer(void); 55extern void dump_bfin_trace_buffer(void);
56 56
57extern int init_arch_irq(void); 57extern int init_arch_irq(void);
@@ -63,6 +63,7 @@ extern void bfin_dcache_init(void);
63extern int read_iloc(void); 63extern int read_iloc(void);
64extern int bfin_console_init(void); 64extern int bfin_console_init(void);
65extern asmlinkage void lower_to_irq14(void); 65extern asmlinkage void lower_to_irq14(void);
66extern asmlinkage void bfin_return_from_exception(void);
66extern void init_exception_vectors(void); 67extern void init_exception_vectors(void);
67extern void init_dma(void); 68extern void init_dma(void);
68extern void program_IAR(void); 69extern void program_IAR(void);
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
index bec6ecdf1bdb..c4d0596e8e9f 100644
--- a/include/asm-blackfin/cplbinit.h
+++ b/include/asm-blackfin/cplbinit.h
@@ -27,6 +27,9 @@
27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 27 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28 */ 28 */
29 29
30#ifndef __ASM_CPLBINIT_H__
31#define __ASM_CPLBINIT_H__
32
30#include <asm/blackfin.h> 33#include <asm/blackfin.h>
31#include <asm/cplb.h> 34#include <asm/cplb.h>
32 35
@@ -57,8 +60,8 @@ struct cplb_tab {
57 u16 size; 60 u16 size;
58}; 61};
59 62
60extern u_long icplb_table[MAX_CPLBS+1]; 63extern u_long icplb_table[];
61extern u_long dcplb_table[MAX_CPLBS+1]; 64extern u_long dcplb_table[];
62 65
63/* Till here we are discussing about the static memory management model. 66/* Till here we are discussing about the static memory management model.
64 * However, the operating envoronments commonly define more CPLB 67 * However, the operating envoronments commonly define more CPLB
@@ -69,28 +72,16 @@ extern u_long dcplb_table[MAX_CPLBS+1];
69 * This is how Page descriptor Table is implemented in uClinux/Blackfin. 72 * This is how Page descriptor Table is implemented in uClinux/Blackfin.
70 */ 73 */
71 74
72#ifdef CONFIG_CPLB_SWITCH_TAB_L1 75extern u_long ipdt_table[];
73extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data)); 76extern u_long dpdt_table[];
74extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
75
76#ifdef CONFIG_CPLB_INFO
77extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
78extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
79#endif /* CONFIG_CPLB_INFO */
80
81#else
82
83extern u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
84extern u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
85
86#ifdef CONFIG_CPLB_INFO 77#ifdef CONFIG_CPLB_INFO
87extern u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]; 78extern u_long ipdt_swapcount_table[];
88extern u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]; 79extern u_long dpdt_swapcount_table[];
89#endif /* CONFIG_CPLB_INFO */ 80#endif
90
91#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
92 81
93extern unsigned long reserved_mem_dcache_on; 82extern unsigned long reserved_mem_dcache_on;
94extern unsigned long reserved_mem_icache_on; 83extern unsigned long reserved_mem_icache_on;
95 84
96extern void generate_cpl_tables(void); 85extern void generate_cpl_tables(void);
86
87#endif
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
index 52e7a10d7ff8..473a8113277f 100644
--- a/include/asm-blackfin/delay.h
+++ b/include/asm-blackfin/delay.h
@@ -1,29 +1,47 @@
1#ifndef _BLACKFIN_DELAY_H
2#define _BLACKFIN_DELAY_H
3
4static inline void __delay(unsigned long loops)
5{
6
7/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
8 uncomment this as soon those are implemented */
9/* 1/*
10 __asm__ __volatile__ ( "\t LSETUP (1f,1f) LC0= %0\n\t" 2 * delay.h - delay functions
11 "1:\t NOP;\n\t" 3 *
12 : :"a" (loops) 4 * Copyright (c) 2004-2007 Analog Devices Inc.
13 : "LT0","LB0","LC0"); 5 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#ifndef __ASM_DELAY_H__
10#define __ASM_DELAY_H__
14 11
15*/ 12#include <asm/mach/anomaly.h>
16 13
17 __asm__ __volatile__("[--SP] = LC0;\n\t" 14static inline void __delay(unsigned long loops)
18 "[--SP] = LT0;\n\t" 15{
19 "[--SP] = LB0;\n\t" 16 if (ANOMALY_05000312) {
20 "LSETUP (1f,1f) LC0 = %0;\n\t" 17 /* Interrupted loads to loop registers -> bad */
21 "1:\t NOP;\n\t" 18 unsigned long tmp;
22 "LB0 = [SP++];\n\t" 19 __asm__ __volatile__(
23 "LT0 = [SP++];\n\t" 20 "[--SP] = LC0;"
24 "LC0 = [SP++];\n" 21 "[--SP] = LT0;"
25 : 22 "[--SP] = LB0;"
26 :"a" (loops)); 23 "LSETUP (1f,1f) LC0 = %1;"
24 "1: NOP;"
25 /* We take advantage of the fact that LC0 is 0 at
26 * the end of the loop. Otherwise we'd need some
27 * NOPs after the CLI here.
28 */
29 "CLI %0;"
30 "LB0 = [SP++];"
31 "LT0 = [SP++];"
32 "LC0 = [SP++];"
33 "STI %0;"
34 : "=d" (tmp)
35 : "a" (loops)
36 );
37 } else
38 __asm__ __volatile__ (
39 "LSETUP(1f, 1f) LC0 = %0;"
40 "1: NOP;"
41 :
42 : "a" (loops)
43 : "LT0", "LB0", "LC0"
44 );
27} 45}
28 46
29#include <linux/param.h> /* needed for HZ */ 47#include <linux/param.h> /* needed for HZ */
@@ -41,4 +59,4 @@ static inline void udelay(unsigned long usecs)
41 __delay(usecs * loops_per_jiffy / (1000000 / HZ)); 59 __delay(usecs * loops_per_jiffy / (1000000 / HZ));
42} 60}
43 61
44#endif /* defined(_BLACKFIN_DELAY_H) */ 62#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
index d1d2e6be3b59..1601d62f39a5 100644
--- a/include/asm-blackfin/io.h
+++ b/include/asm-blackfin/io.h
@@ -122,6 +122,7 @@ extern void outsl(unsigned long port, const void *addr, unsigned long count);
122extern void insb(unsigned long port, void *addr, unsigned long count); 122extern void insb(unsigned long port, void *addr, unsigned long count);
123extern void insw(unsigned long port, void *addr, unsigned long count); 123extern void insw(unsigned long port, void *addr, unsigned long count);
124extern void insl(unsigned long port, void *addr, unsigned long count); 124extern void insl(unsigned long port, void *addr, unsigned long count);
125extern void insl_16(unsigned long port, void *addr, unsigned long count);
125 126
126extern void dma_outsb(unsigned long port, const void *addr, unsigned short count); 127extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
127extern void dma_outsw(unsigned long port, const void *addr, unsigned short count); 128extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
index 304f5bcfebe4..4e2b3f2020e5 100644
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ b/include/asm-blackfin/mach-bf527/irq.h
@@ -176,11 +176,7 @@
176 176
177#define GPIO_IRQ_BASE IRQ_PF0 177#define GPIO_IRQ_BASE IRQ_PF0
178 178
179#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
180#define NR_IRQS (IRQ_PH15+1) 179#define NR_IRQS (IRQ_PH15+1)
181#else
182#define NR_IRQS (SYS_IRQS+1)
183#endif
184 180
185#define IVG7 7 181#define IVG7 7
186#define IVG8 8 182#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
index c5aa20102b24..193082deaa4e 100644
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ b/include/asm-blackfin/mach-bf527/mem_map.h
@@ -47,6 +47,7 @@
47/* Boot ROM Memory */ 47/* Boot ROM Memory */
48 48
49#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x8000
50 51
51/* Level 1 Memory */ 52/* Level 1 Memory */
52 53
@@ -90,9 +91,7 @@
90 91
91/* Scratch Pad Memory */ 92/* Scratch Pad Memory */
92 93
93#if defined(CONFIG_BF527) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
94#define L1_SCRATCH_START 0xFFB00000 94#define L1_SCRATCH_START 0xFFB00000
95#define L1_SCRATCH_LENGTH 0x1000 95#define L1_SCRATCH_LENGTH 0x1000
96#endif
97 96
98#endif /* _MEM_MAP_527_H_ */ 97#endif /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
index 452fb825d891..832e6f6122da 100644
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -130,11 +130,7 @@ Core Emulation **
130 130
131#define GPIO_IRQ_BASE IRQ_PF0 131#define GPIO_IRQ_BASE IRQ_PF0
132 132
133#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
134#define NR_IRQS (IRQ_PF15+1) 133#define NR_IRQS (IRQ_PF15+1)
135#else
136#define NR_IRQS SYS_IRQS
137#endif
138 134
139#define IVG7 7 135#define IVG7 7
140#define IVG8 8 136#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index 94d8c4062eb7..bd30b6f3be00 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -1,4 +1,3 @@
1
2/* 1/*
3 * File: include/asm-blackfin/mach-bf533/mem_map.h 2 * File: include/asm-blackfin/mach-bf533/mem_map.h
4 * Based on: 3 * Based on:
@@ -48,6 +47,7 @@
48/* Boot ROM Memory */ 47/* Boot ROM Memory */
49 48
50#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x400
51 51
52/* Level 1 Memory */ 52/* Level 1 Memory */
53 53
@@ -160,9 +160,7 @@
160 160
161/* Scratch Pad Memory */ 161/* Scratch Pad Memory */
162 162
163#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
164#define L1_SCRATCH_START 0xFFB00000 163#define L1_SCRATCH_START 0xFFB00000
165#define L1_SCRATCH_LENGTH 0x1000 164#define L1_SCRATCH_LENGTH 0x1000
166#endif
167 165
168#endif /* _MEM_MAP_533_H_ */ 166#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 36c44bc1a917..be6f2ff77f31 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -162,11 +162,7 @@ Core Emulation **
162 162
163#define GPIO_IRQ_BASE IRQ_PF0 163#define GPIO_IRQ_BASE IRQ_PF0
164 164
165#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
166#define NR_IRQS (IRQ_PH15+1) 165#define NR_IRQS (IRQ_PH15+1)
167#else
168#define NR_IRQS (IRQ_UART1_ERROR+1)
169#endif
170 166
171#define IVG7 7 167#define IVG7 7
172#define IVG8 8 168#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 18759e38eaae..5c6726d6f3b1 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -47,6 +47,7 @@
47/* Boot ROM Memory */ 47/* Boot ROM Memory */
48 48
49#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x800
50 51
51/* Level 1 Memory */ 52/* Level 1 Memory */
52 53
@@ -167,9 +168,7 @@
167 168
168/* Scratch Pad Memory */ 169/* Scratch Pad Memory */
169 170
170#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
171#define L1_SCRATCH_START 0xFFB00000 171#define L1_SCRATCH_START 0xFFB00000
172#define L1_SCRATCH_LENGTH 0x1000 172#define L1_SCRATCH_LENGTH 0x1000
173#endif
174 173
175#endif /* _MEM_MAP_537_H_ */ 174#endif /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
index 7e6d349beb08..e748588e8930 100644
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ b/include/asm-blackfin/mach-bf548/bf548.h
@@ -106,24 +106,22 @@
106 106
107#define AMGCTLVAL (V_AMBEN | V_AMCKEN) 107#define AMGCTLVAL (V_AMBEN | V_AMCKEN)
108 108
109#ifdef CONFIG_BF542 109#if defined(CONFIG_BF542)
110#define CPU "BF542" 110# define CPU "BF542"
111#define CPUID 0x027c8000 111# define CPUID 0x027c8000
112#endif 112#elif defined(CONFIG_BF544)
113#ifdef CONFIG_BF544 113# define CPU "BF544"
114#define CPU "BF544" 114# define CPUID 0x027c8000
115#define CPUID 0x027c8000 115#elif defined(CONFIG_BF547)
116#endif 116# define CPU "BF547"
117#ifdef CONFIG_BF548 117#elif defined(CONFIG_BF548)
118#define CPU "BF548" 118# define CPU "BF548"
119#define CPUID 0x027c6000 119# define CPUID 0x027c6000
120#endif 120#elif defined(CONFIG_BF549)
121#ifdef CONFIG_BF549 121# define CPU "BF549"
122#define CPU "BF549" 122#else
123#endif 123# define CPU "UNKNOWN"
124#ifndef CPU 124# define CPUID 0x0
125#define CPU "UNKNOWN"
126#define CPUID 0x0
127#endif 125#endif
128 126
129#endif /* __MACH_BF48_H__ */ 127#endif /* __MACH_BF48_H__ */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
index 760307e34b9e..b8b9870e2697 100644
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ b/include/asm-blackfin/mach-bf548/defBF544.h
@@ -645,7 +645,7 @@
645 645
646/* Bit masks for HOST_STATUS */ 646/* Bit masks for HOST_STATUS */
647 647
648#define READY 0x1 /* DMA Ready */ 648#define DMA_READY 0x1 /* DMA Ready */
649#define FIFOFULL 0x2 /* FIFO Full */ 649#define FIFOFULL 0x2 /* FIFO Full */
650#define FIFOEMPTY 0x4 /* FIFO Empty */ 650#define FIFOEMPTY 0x4 /* FIFO Empty */
651#define COMPLETE 0x8 /* DMA Complete */ 651#define COMPLETE 0x8 /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
index 70af33c963b0..ecbca952985c 100644
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ b/include/asm-blackfin/mach-bf548/defBF548.h
@@ -1007,7 +1007,7 @@
1007 1007
1008/* Bit masks for HOST_STATUS */ 1008/* Bit masks for HOST_STATUS */
1009 1009
1010#define READY 0x1 /* DMA Ready */ 1010#define DMA_READY 0x1 /* DMA Ready */
1011#define FIFOFULL 0x2 /* FIFO Full */ 1011#define FIFOFULL 0x2 /* FIFO Full */
1012#define FIFOEMPTY 0x4 /* FIFO Empty */ 1012#define FIFOEMPTY 0x4 /* FIFO Empty */
1013#define COMPLETE 0x8 /* DMA Complete */ 1013#define COMPLETE 0x8 /* DMA Complete */
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
index 3b08cf9bd6f3..9fb7bc5399a8 100644
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ b/include/asm-blackfin/mach-bf548/irq.h
@@ -338,11 +338,7 @@ Events (highest priority) EMU 0
338 338
339#define GPIO_IRQ_BASE IRQ_PA0 339#define GPIO_IRQ_BASE IRQ_PA0
340 340
341#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
342#define NR_IRQS (IRQ_PJ15+1) 341#define NR_IRQS (IRQ_PJ15+1)
343#else
344#define NR_IRQS (SYS_IRQS+1)
345#endif
346 342
347/* For compatibility reasons with existing code */ 343/* For compatibility reasons with existing code */
348 344
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
index ec1597e31831..f99f47bc3a07 100644
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ b/include/asm-blackfin/mach-bf548/mem_map.h
@@ -47,6 +47,12 @@
47/* Boot ROM Memory */ 47/* Boot ROM Memory */
48 48
49#define BOOT_ROM_START 0xEF000000 49#define BOOT_ROM_START 0xEF000000
50#define BOOT_ROM_LENGTH 0x1000
51
52/* L1 Instruction ROM */
53
54#define L1_ROM_START 0xFFA14000
55#define L1_ROM_LENGTH 0x10000
50 56
51/* Level 1 Memory */ 57/* Level 1 Memory */
52 58
@@ -87,11 +93,19 @@
87#define BFIN_DSUPBANKS 0 93#define BFIN_DSUPBANKS 0
88#endif /*CONFIG_BFIN_DCACHE*/ 94#endif /*CONFIG_BFIN_DCACHE*/
89 95
96/* Level 2 Memory */
97#if !defined(CONFIG_BF542)
98# define L2_START 0xFEB00000
99# if defined(CONFIG_BF544)
100# define L2_LENGTH 0x10000
101# else
102# define L2_LENGTH 0x20000
103# endif
104#endif
105
90/* Scratch Pad Memory */ 106/* Scratch Pad Memory */
91 107
92#if defined(CONFIG_BF54x)
93#define L1_SCRATCH_START 0xFFB00000 108#define L1_SCRATCH_START 0xFFB00000
94#define L1_SCRATCH_LENGTH 0x1000 109#define L1_SCRATCH_LENGTH 0x1000
95#endif
96 110
97#endif/* _MEM_MAP_548_H_ */ 111#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
index 17e1d5dcef02..3ef9e5f36136 100644
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -33,25 +33,6 @@
33#define SUPPORTED_REVID 0x3 33#define SUPPORTED_REVID 0x3
34 34
35#define OFFSET_(x) ((x) & 0x0000FFFF) 35#define OFFSET_(x) ((x) & 0x0000FFFF)
36#define L1_ISRAM 0xFFA00000
37#define L1_ISRAM_END 0xFFA04000
38#define DATA_BANKA_SRAM 0xFF800000
39#define DATA_BANKA_SRAM_END 0xFF804000
40#define DATA_BANKB_SRAM 0xFF900000
41#define DATA_BANKB_SRAM_END 0xFF904000
42#define L1_DSRAMA 0xFF800000
43#define L1_DSRAMA_END 0xFF804000
44#define L1_DSRAMB 0xFF900000
45#define L1_DSRAMB_END 0xFF904000
46#define L2_SRAM 0xFEB00000
47#define L2_SRAM_END 0xFEB20000
48#define AMB_FLASH 0x20000000
49#define AMB_FLASH_END 0x21000000
50#define AMB_FLASH_LENGTH 0x01000000
51#define L1_ISRAM_LENGTH 0x4000
52#define L1_DSRAMA_LENGTH 0x4000
53#define L1_DSRAMB_LENGTH 0x4000
54#define L2_SRAM_LENGTH 0x20000
55 36
56/*some misc defines*/ 37/*some misc defines*/
57#define IMASK_IVG15 0x8000 38#define IMASK_IVG15 0x8000
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 7945e8a3a841..c3c0eb13c819 100644
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,7 @@
55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ 55/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
56#define SWRST SICA_SWRST 56#define SWRST SICA_SWRST
57#define SYSCR SICA_SYSCR 57#define SYSCR SICA_SYSCR
58#define DOUBLE_FAULT (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
58#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) 59#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
59#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) 60#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A)
60#define RESET_SOFTWARE (SWRST_OCCURRED) 61#define RESET_SOFTWARE (SWRST_OCCURRED)
@@ -877,12 +878,14 @@
877#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */ 878#define PLL_LOCKED 0x0020 /* PLL_LOCKCNT Has Been Reached */
878 879
879/* SWRST Mask */ 880/* SWRST Mask */
880#define SYSTEM_RESET 0x00000007 /* Initiates a system software reset */ 881#define SYSTEM_RESET 0x0007 /* Initiates a system software reset */
881#define SWRST_DBL_FAULT_B 0x00000800 /* SWRST Core B Double Fault */ 882#define DOUBLE_FAULT_A 0x0008 /* Core A Double Fault Causes Reset */
882#define SWRST_DBL_FAULT_A 0x00001000 /* SWRST Core A Double Fault */ 883#define DOUBLE_FAULT_B 0x0010 /* Core B Double Fault Causes Reset */
883#define SWRST_WDT_B 0x00002000 /* SWRST Watchdog B */ 884#define SWRST_DBL_FAULT_A 0x0800 /* SWRST Core A Double Fault */
884#define SWRST_WDT_A 0x00004000 /* SWRST Watchdog A */ 885#define SWRST_DBL_FAULT_B 0x1000 /* SWRST Core B Double Fault */
885#define SWRST_OCCURRED 0x00008000 /* SWRST Status */ 886#define SWRST_WDT_B 0x2000 /* SWRST Watchdog B */
887#define SWRST_WDT_A 0x4000 /* SWRST Watchdog A */
888#define SWRST_OCCURRED 0x8000 /* SWRST Status */
886 889
887/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */ 890/* ************* SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
888 891
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
index 12789927db3d..83f0383957d2 100644
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -291,11 +291,7 @@
291 291
292#define GPIO_IRQ_BASE IRQ_PF0 292#define GPIO_IRQ_BASE IRQ_PF0
293 293
294#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
295#define NR_IRQS (IRQ_PF47 + 1) 294#define NR_IRQS (IRQ_PF47 + 1)
296#else
297#define NR_IRQS SYS_IRQS
298#endif
299 295
300#define IVG7 7 296#define IVG7 7
301#define IVG8 8 297#define IVG8 8
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
index f7ac09cf2c3d..c26d8486cc4b 100644
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -19,6 +19,11 @@
19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */ 19#define ASYNC_BANK0_BASE 0x20000000 /* Async Bank 0 */
20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */ 20#define ASYNC_BANK0_SIZE 0x04000000 /* 64M */
21 21
22/* Boot ROM Memory */
23
24#define BOOT_ROM_START 0xEF000000
25#define BOOT_ROM_LENGTH 0x800
26
22/* Level 1 Memory */ 27/* Level 1 Memory */
23 28
24#ifdef CONFIG_BFIN_ICACHE 29#ifdef CONFIG_BFIN_ICACHE
@@ -67,9 +72,7 @@
67 72
68/* Scratch Pad Memory */ 73/* Scratch Pad Memory */
69 74
70#if defined(CONFIG_BF561)
71#define L1_SCRATCH_START 0xFFB00000 75#define L1_SCRATCH_START 0xFFB00000
72#define L1_SCRATCH_LENGTH 0x1000 76#define L1_SCRATCH_LENGTH 0x1000
73#endif
74 77
75#endif /* _MEM_MAP_533_H_ */ 78#endif /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
index c1d8c4a78fcf..e8967f6124f7 100644
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -46,7 +46,7 @@
46#endif 46#endif
47 47
48#define bfin_read8(addr) ({ \ 48#define bfin_read8(addr) ({ \
49 uint8_t __v; \ 49 uint32_t __v; \
50 __asm__ __volatile__( \ 50 __asm__ __volatile__( \
51 NOP_PAD_ANOMALY_05000198 \ 51 NOP_PAD_ANOMALY_05000198 \
52 "%0 = b[%1] (z);" \ 52 "%0 = b[%1] (z);" \
@@ -56,7 +56,7 @@
56 __v; }) 56 __v; })
57 57
58#define bfin_read16(addr) ({ \ 58#define bfin_read16(addr) ({ \
59 uint16_t __v; \ 59 uint32_t __v; \
60 __asm__ __volatile__( \ 60 __asm__ __volatile__( \
61 NOP_PAD_ANOMALY_05000198 \ 61 NOP_PAD_ANOMALY_05000198 \
62 "%0 = w[%1] (z);" \ 62 "%0 = w[%1] (z);" \
@@ -80,7 +80,7 @@
80 NOP_PAD_ANOMALY_05000198 \ 80 NOP_PAD_ANOMALY_05000198 \
81 "b[%0] = %1;" \ 81 "b[%0] = %1;" \
82 : \ 82 : \
83 : "a" (addr), "d" (val) \ 83 : "a" (addr), "d" ((uint8_t)(val)) \
84 : "memory" \ 84 : "memory" \
85 ) 85 )
86 86
@@ -89,7 +89,7 @@
89 NOP_PAD_ANOMALY_05000198 \ 89 NOP_PAD_ANOMALY_05000198 \
90 "w[%0] = %1;" \ 90 "w[%0] = %1;" \
91 : \ 91 : \
92 : "a" (addr), "d" (val) \ 92 : "a" (addr), "d" ((uint16_t)(val)) \
93 : "memory" \ 93 : "memory" \
94 ) 94 )
95 95
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
index 3b671d5fd70d..cbaff24b4b25 100644
--- a/include/asm-blackfin/page_offset.h
+++ b/include/asm-blackfin/page_offset.h
@@ -1,6 +1,6 @@
1 1
2/* This handles the memory map.. */ 2/* This handles the memory map.. */
3 3
4#ifdef CONFIG_BFIN 4#ifdef CONFIG_BLACKFIN
5#define PAGE_OFFSET_RAW 0x00000000 5#define PAGE_OFFSET_RAW 0x00000000
6#endif 6#endif
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
index e8ada91ab002..321f4d96e4ae 100644
--- a/include/asm-blackfin/string.h
+++ b/include/asm-blackfin/string.h
@@ -1,6 +1,8 @@
1#ifndef _BLACKFIN_STRING_H_ 1#ifndef _BLACKFIN_STRING_H_
2#define _BLACKFIN_STRING_H_ 2#define _BLACKFIN_STRING_H_
3 3
4#include <linux/types.h>
5
4#ifdef __KERNEL__ /* only set these up for kernel code */ 6#ifdef __KERNEL__ /* only set these up for kernel code */
5 7
6#define __HAVE_ARCH_STRCPY 8#define __HAVE_ARCH_STRCPY
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
index fe365b1b7ca8..ee1cbf73a9ab 100644
--- a/include/asm-blackfin/traps.h
+++ b/include/asm-blackfin/traps.h
@@ -48,28 +48,80 @@
48 48
49#ifndef __ASSEMBLY__ 49#ifndef __ASSEMBLY__
50 50
51#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n" 51#define HWC_x2(level) \
52#define HWC_x3 "External Memory Addressing Error\n" 52 "System MMR Error\n" \
53#define HWC_x12 "Performance Monitor Overflow\n" 53 level " - An error occurred due to an invalid access to an System MMR location\n" \
54#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n" 54 level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
55#define HWC_default "Reserved\n" 55 level " or a 16-bit register is accessed with a 32-bit instruction.\n"
56 56#define HWC_x3(level) \
57#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n" 57 "External Memory Addressing Error\n"
58#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n" 58#define HWC_x12(level) \
59#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n" 59 "Performance Monitor Overflow\n"
60#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n" 60#define HWC_x18(level) \
61#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n" 61 "RAISE 5 instruction\n" \
62#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n" 62 level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
63#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n" 63#define HWC_default(level) \
64#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n" 64 "Reserved\n"
65#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n" 65#define EXC_0x03(level) \
66#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n" 66 "Application stack overflow\n" \
67#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n" 67 level " - Please increase the stack size of the application using elf2flt -s option,\n" \
68#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n" 68 level " and/or reduce the stack use of the application.\n"
69#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n" 69#define EXC_0x10(level) \
70#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n" 70 "Single step\n" \
71#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n" 71 level " - When the processor is in single step mode, every instruction\n" \
72#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n" 72 level " generates an exception. Primarily used for debugging.\n"
73#define EXC_0x11(level) \
74 "Exception caused by a trace buffer full condition\n" \
75 level " - The processor takes this exception when the trace\n" \
76 level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
77#define EXC_0x21(level) \
78 "Undefined instruction\n" \
79 level " - May be used to emulate instructions that are not defined for\n" \
80 level " a particular processor implementation.\n"
81#define EXC_0x22(level) \
82 "Illegal instruction combination\n" \
83 level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
84 level " Processor Instruction Set Reference.\n"
85#define EXC_0x23(level) \
86 "Data access CPLB protection violation\n" \
87 level " - Attempted read or write to Supervisor resource,\n" \
88 level " or illegal data memory access. \n"
89#define EXC_0x24(level) \
90 "Data access misaligned address violation\n" \
91 level " - Attempted misaligned data memory or data cache access.\n"
92#define EXC_0x25(level) \
93 "Unrecoverable event\n" \
94 level " - For example, an exception generated while processing a previous exception.\n"
95#define EXC_0x26(level) \
96 "Data access CPLB miss\n" \
97 level " - Used by the MMU to signal a CPLB miss on a data access.\n"
98#define EXC_0x27(level) \
99 "Data access multiple CPLB hits\n" \
100 level " - More than one CPLB entry matches data fetch address.\n"
101#define EXC_0x28(level) \
102 "Program Sequencer Exception caused by an emulation watchpoint match\n" \
103 level " - There is a watchpoint match, and one of the EMUSW\n" \
104 level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
105#define EXC_0x2A(level) \
106 "Instruction fetch misaligned address violation\n" \
107 level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
108 level " exception, the return address provided in RETX is the destination address which is\n" \
109 level " misaligned, rather than the address of the offending instruction.\n"
110#define EXC_0x2B(level) \
111 "CPLB protection violation\n" \
112 level " - Illegal instruction fetch access (memory protection violation).\n"
113#define EXC_0x2C(level) \
114 "Instruction fetch CPLB miss\n" \
115 level " - CPLB miss on an instruction fetch.\n"
116#define EXC_0x2D(level) \
117 "Instruction fetch multiple CPLB hits\n" \
118 level " - More than one CPLB entry matches instruction fetch address.\n"
119#define EXC_0x2E(level) \
120 "Illegal use of supervisor resource\n" \
121 level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
122 level " Supervisor resources are registers and instructions that are reserved\n" \
123 level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
124 level " only instructions.\n"
73 125
74#endif /* __ASSEMBLY__ */ 126#endif /* __ASSEMBLY__ */
75#endif /* _BFIN_TRAPS_H */ 127#endif /* _BFIN_TRAPS_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 17:00:49 -0500