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authorYevgeny Petrilin <yevgenyp@mellanox.co.il>2008-10-22 13:25:29 -0400
committerRoland Dreier <rolandd@cisco.com>2008-10-22 13:25:29 -0400
commit93fc9e1bb6507dde945c2eab68c93e1066ac3691 (patch)
treeaa495ec31b7372580f9ec50acead1d170fd70aab /include
parenta3cdcbfa8fb1fccfe48d359da86e99546610c562 (diff)
mlx4_core: Support multiple pre-reserved QP regions
For ethernet support, we need to reserve QPs for the ethernet and fibre channel driver. The QPs are reserved at the end of the QP table. (This way we assure that they are aligned to their size) We need to consider these reserved ranges in bitmap creation, so we extend the mlx4 bitmap utility functions to allow reserved ranges at both the bottom and the top of the range. Signed-off-by: Yevgeny Petrilin <yevgenyp@mellanox.co.il> Signed-off-by: Roland Dreier <rolandd@cisco.com>
Diffstat (limited to 'include')
-rw-r--r--include/linux/mlx4/device.h19
1 files changed, 18 insertions, 1 deletions
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index d21e879f3c90..693f93cd29e1 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -145,6 +145,18 @@ enum {
145 MLX4_MTT_FLAG_PRESENT = 1 145 MLX4_MTT_FLAG_PRESENT = 1
146}; 146};
147 147
148enum mlx4_qp_region {
149 MLX4_QP_REGION_FW = 0,
150 MLX4_QP_REGION_ETH_ADDR,
151 MLX4_QP_REGION_FC_ADDR,
152 MLX4_QP_REGION_FC_EXCH,
153 MLX4_NUM_QP_REGION
154};
155
156enum {
157 MLX4_NUM_FEXCH = 64 * 1024,
158};
159
148static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 160static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
149{ 161{
150 return (major << 32) | (minor << 16) | subminor; 162 return (major << 32) | (minor << 16) | subminor;
@@ -169,7 +181,6 @@ struct mlx4_caps {
169 int max_rq_desc_sz; 181 int max_rq_desc_sz;
170 int max_qp_init_rdma; 182 int max_qp_init_rdma;
171 int max_qp_dest_rdma; 183 int max_qp_dest_rdma;
172 int reserved_qps;
173 int sqp_start; 184 int sqp_start;
174 int num_srqs; 185 int num_srqs;
175 int max_srq_wqes; 186 int max_srq_wqes;
@@ -201,6 +212,12 @@ struct mlx4_caps {
201 u16 stat_rate_support; 212 u16 stat_rate_support;
202 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 213 u8 port_width_cap[MLX4_MAX_PORTS + 1];
203 int max_gso_sz; 214 int max_gso_sz;
215 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
216 int reserved_qps;
217 int reserved_qps_base[MLX4_NUM_QP_REGION];
218 int log_num_macs;
219 int log_num_vlans;
220 int log_num_prios;
204}; 221};
205 222
206struct mlx4_buf_list { 223struct mlx4_buf_list {