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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-04-27 12:14:46 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-04-27 12:14:46 -0400
commit32f15dc5e6252f03aa2e04a2b140827a8297f21f (patch)
tree2898e6fd94c9e2f668dd76fb1b0290b84c6314e6 /include
parent07db59bd6b0f279c31044cba6787344f63be87ea (diff)
parent8224ca195874525533665bbcd23b6da1e575aa4d (diff)
Merge branch 'for-linus' of git://www.atmel.no/~hskinnemoen/linux/kernel/avr32
* 'for-linus' of git://www.atmel.no/~hskinnemoen/linux/kernel/avr32: (21 commits) [AVR32] Fix compile error with gcc 4.1 avr32: remove unneeded cast in atomic.h AVR32: Remove useless config option "GENERIC_BUST_SPINLOCK". [AVR32] Optimize the TLB miss handler [AVR32] Board code for ATNGW100 [AVR32] Use memcpy/memset in memcpy_{from,to}_io and memset_io [AVR32] Get rid of board_setup_fbmem() [AVR32] Reserve framebuffer memory in early_parse_fbmem() [AVR32] Simplify early handling of memory regions [AVR32] Move setup_bootmem() from mm/init.c to kernel/setup.c [AVR32] Make I/O access macros work with external devices [AVR32] Fix NMI handler [AVR32] Clean up exception handling code [AVR32] Clean up cpu identification and add features bitmap [AVR32] Clean up asm/sysreg.h [AVR32] Don't enable clocks with no users [AVR32] Put cpu in sleep 0 when idle. [AVR32] Change system timer from count-compare to Timer/Counter 0 [AVR32] Add mach-specific Kconfig [AVR32] Add nwait and tdf parameters to SMC configuration ...
Diffstat (limited to 'include')
-rw-r--r--include/asm-avr32/arch-at32ap/io.h39
-rw-r--r--include/asm-avr32/arch-at32ap/smc.h22
-rw-r--r--include/asm-avr32/arch-at32ap/time.h112
-rw-r--r--include/asm-avr32/atomic.h2
-rw-r--r--include/asm-avr32/bug.h50
-rw-r--r--include/asm-avr32/io.h326
-rw-r--r--include/asm-avr32/processor.h15
-rw-r--r--include/asm-avr32/setup.h13
-rw-r--r--include/asm-avr32/sysreg.h543
-rw-r--r--include/asm-avr32/system.h13
-rw-r--r--include/asm-avr32/thread_info.h2
-rw-r--r--include/asm-avr32/uaccess.h13
12 files changed, 659 insertions, 491 deletions
diff --git a/include/asm-avr32/arch-at32ap/io.h b/include/asm-avr32/arch-at32ap/io.h
new file mode 100644
index 000000000000..ee59e401f041
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/io.h
@@ -0,0 +1,39 @@
1#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
2#define __ASM_AVR32_ARCH_AT32AP_IO_H
3
4/* For "bizarre" halfword swapping */
5#include <linux/byteorder/swabb.h>
6
7#if defined(CONFIG_AP7000_32_BIT_SMC)
8# define __swizzle_addr_b(addr) (addr ^ 3UL)
9# define __swizzle_addr_w(addr) (addr ^ 2UL)
10# define __swizzle_addr_l(addr) (addr)
11# define ioswabb(a, x) (x)
12# define ioswabw(a, x) (x)
13# define ioswabl(a, x) (x)
14# define __mem_ioswabb(a, x) (x)
15# define __mem_ioswabw(a, x) swab16(x)
16# define __mem_ioswabl(a, x) swab32(x)
17#elif defined(CONFIG_AP7000_16_BIT_SMC)
18# define __swizzle_addr_b(addr) (addr ^ 1UL)
19# define __swizzle_addr_w(addr) (addr)
20# define __swizzle_addr_l(addr) (addr)
21# define ioswabb(a, x) (x)
22# define ioswabw(a, x) (x)
23# define ioswabl(a, x) swahw32(x)
24# define __mem_ioswabb(a, x) (x)
25# define __mem_ioswabw(a, x) swab16(x)
26# define __mem_ioswabl(a, x) swahb32(x)
27#else
28# define __swizzle_addr_b(addr) (addr)
29# define __swizzle_addr_w(addr) (addr)
30# define __swizzle_addr_l(addr) (addr)
31# define ioswabb(a, x) (x)
32# define ioswabw(a, x) swab16(x)
33# define ioswabl(a, x) swab32(x)
34# define __mem_ioswabb(a, x) (x)
35# define __mem_ioswabw(a, x) (x)
36# define __mem_ioswabl(a, x) (x)
37#endif
38
39#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
diff --git a/include/asm-avr32/arch-at32ap/smc.h b/include/asm-avr32/arch-at32ap/smc.h
index 3732b328303d..07152b7fd9c9 100644
--- a/include/asm-avr32/arch-at32ap/smc.h
+++ b/include/asm-avr32/arch-at32ap/smc.h
@@ -48,10 +48,32 @@ struct smc_config {
48 unsigned int nwe_controlled:1; 48 unsigned int nwe_controlled:1;
49 49
50 /* 50 /*
51 * 0: NWAIT is disabled
52 * 1: Reserved
53 * 2: NWAIT is frozen mode
54 * 3: NWAIT in ready mode
55 */
56 unsigned int nwait_mode:2;
57
58 /*
51 * 0: Byte select access type 59 * 0: Byte select access type
52 * 1: Byte write access type 60 * 1: Byte write access type
53 */ 61 */
54 unsigned int byte_write:1; 62 unsigned int byte_write:1;
63
64 /*
65 * Number of clock cycles before data is released after
66 * the rising edge of the read controlling signal
67 *
68 * Total cycles from SMC is tdf_cycles + 1
69 */
70 unsigned int tdf_cycles:4;
71
72 /*
73 * 0: TDF optimization disabled
74 * 1: TDF optimization enabled
75 */
76 unsigned int tdf_mode:1;
55}; 77};
56 78
57extern int smc_set_configuration(int cs, const struct smc_config *config); 79extern int smc_set_configuration(int cs, const struct smc_config *config);
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h
new file mode 100644
index 000000000000..cc8a43418a4d
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/time.h
@@ -0,0 +1,112 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
10#define _ASM_AVR32_ARCH_AT32AP_TIME_H
11
12#include <linux/platform_device.h>
13
14extern struct irqaction timer_irqaction;
15extern struct platform_device at32_systc0_device;
16extern void local_timer_interrupt(int irq, void *dev_id);
17
18#define TIMER_BCR 0x000000c0
19#define TIMER_BCR_SYNC 0
20#define TIMER_BMR 0x000000c4
21#define TIMER_BMR_TC0XC0S 0
22#define TIMER_BMR_TC1XC1S 2
23#define TIMER_BMR_TC2XC2S 4
24#define TIMER_CCR 0x00000000
25#define TIMER_CCR_CLKDIS 1
26#define TIMER_CCR_CLKEN 0
27#define TIMER_CCR_SWTRG 2
28#define TIMER_CMR 0x00000004
29#define TIMER_CMR_ABETRG 10
30#define TIMER_CMR_ACPA 16
31#define TIMER_CMR_ACPC 18
32#define TIMER_CMR_AEEVT 20
33#define TIMER_CMR_ASWTRG 22
34#define TIMER_CMR_BCPB 24
35#define TIMER_CMR_BCPC 26
36#define TIMER_CMR_BEEVT 28
37#define TIMER_CMR_BSWTRG 30
38#define TIMER_CMR_BURST 4
39#define TIMER_CMR_CLKI 3
40#define TIMER_CMR_CPCDIS 7
41#define TIMER_CMR_CPCSTOP 6
42#define TIMER_CMR_CPCTRG 14
43#define TIMER_CMR_EEVT 10
44#define TIMER_CMR_EEVTEDG 8
45#define TIMER_CMR_ENETRG 12
46#define TIMER_CMR_ETRGEDG 8
47#define TIMER_CMR_LDBDIS 7
48#define TIMER_CMR_LDBSTOP 6
49#define TIMER_CMR_LDRA 16
50#define TIMER_CMR_LDRB 18
51#define TIMER_CMR_TCCLKS 0
52#define TIMER_CMR_WAVE 15
53#define TIMER_CMR_WAVSEL 13
54#define TIMER_CV 0x00000010
55#define TIMER_CV_CV 0
56#define TIMER_IDR 0x00000028
57#define TIMER_IDR_COVFS 0
58#define TIMER_IDR_CPAS 2
59#define TIMER_IDR_CPBS 3
60#define TIMER_IDR_CPCS 4
61#define TIMER_IDR_ETRGS 7
62#define TIMER_IDR_LDRAS 5
63#define TIMER_IDR_LDRBS 6
64#define TIMER_IDR_LOVRS 1
65#define TIMER_IER 0x00000024
66#define TIMER_IER_COVFS 0
67#define TIMER_IER_CPAS 2
68#define TIMER_IER_CPBS 3
69#define TIMER_IER_CPCS 4
70#define TIMER_IER_ETRGS 7
71#define TIMER_IER_LDRAS 5
72#define TIMER_IER_LDRBS 6
73#define TIMER_IER_LOVRS 1
74#define TIMER_IMR 0x0000002c
75#define TIMER_IMR_COVFS 0
76#define TIMER_IMR_CPAS 2
77#define TIMER_IMR_CPBS 3
78#define TIMER_IMR_CPCS 4
79#define TIMER_IMR_ETRGS 7
80#define TIMER_IMR_LDRAS 5
81#define TIMER_IMR_LDRBS 6
82#define TIMER_IMR_LOVRS 1
83#define TIMER_RA 0x00000014
84#define TIMER_RA_RA 0
85#define TIMER_RB 0x00000018
86#define TIMER_RB_RB 0
87#define TIMER_RC 0x0000001c
88#define TIMER_RC_RC 0
89#define TIMER_SR 0x00000020
90#define TIMER_SR_CLKSTA 16
91#define TIMER_SR_COVFS 0
92#define TIMER_SR_CPAS 2
93#define TIMER_SR_CPBS 3
94#define TIMER_SR_CPCS 4
95#define TIMER_SR_ETRGS 7
96#define TIMER_SR_LDRAS 5
97#define TIMER_SR_LDRBS 6
98#define TIMER_SR_LOVRS 1
99#define TIMER_SR_MTIOA 17
100#define TIMER_SR_MTIOB 18
101
102/* Bit manipulation macros */
103#define TIMER_BIT(name) (1 << TIMER_##name)
104#define TIMER_BF(name,value) ((value) << TIMER_##name)
105
106/* Register access macros */
107#define timer_read(port,instance,reg) \
108 __raw_readl(port + (0x40 * instance) + TIMER_##reg)
109#define timer_write(port,instance,reg,value) \
110 __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
111
112#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
diff --git a/include/asm-avr32/atomic.h b/include/asm-avr32/atomic.h
index c40b6032c480..b9c2548a52f3 100644
--- a/include/asm-avr32/atomic.h
+++ b/include/asm-avr32/atomic.h
@@ -173,7 +173,7 @@ static inline int atomic_sub_if_positive(int i, atomic_t *v)
173} 173}
174 174
175#define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 175#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
176#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) 176#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
177 177
178#define atomic_sub(i, v) (void)atomic_sub_return(i, v) 178#define atomic_sub(i, v) (void)atomic_sub_return(i, v)
179#define atomic_add(i, v) (void)atomic_add_return(i, v) 179#define atomic_add(i, v) (void)atomic_add_return(i, v)
diff --git a/include/asm-avr32/bug.h b/include/asm-avr32/bug.h
index 521766bc9366..afdcd79a2966 100644
--- a/include/asm-avr32/bug.h
+++ b/include/asm-avr32/bug.h
@@ -18,27 +18,53 @@
18 18
19#ifdef CONFIG_DEBUG_BUGVERBOSE 19#ifdef CONFIG_DEBUG_BUGVERBOSE
20 20
21#define BUG() \ 21#define _BUG_OR_WARN(flags) \
22 do { \ 22 asm volatile( \
23 asm volatile(".hword %0\n\t" \ 23 "1: .hword %0\n" \
24 ".hword %1\n\t" \ 24 " .section __bug_table,\"a\",@progbits\n" \
25 ".long %2" \ 25 "2: .long 1b\n" \
26 : \ 26 " .long %1\n" \
27 : "n"(AVR32_BUG_OPCODE), \ 27 " .short %2\n" \
28 "i"(__LINE__), "X"(__FILE__)); \ 28 " .short %3\n" \
29 } while (0) 29 " .org 2b + %4\n" \
30 " .previous" \
31 : \
32 : "i"(AVR32_BUG_OPCODE), "i"(__FILE__), \
33 "i"(__LINE__), "i"(flags), \
34 "i"(sizeof(struct bug_entry)))
30 35
31#else 36#else
32 37
38#define _BUG_OR_WARN(flags) \
39 asm volatile( \
40 "1: .hword %0\n" \
41 " .section __bug_table,\"a\",@progbits\n" \
42 "2: .long 1b\n" \
43 " .short %1\n" \
44 " .org 2b + %2\n" \
45 " .previous" \
46 : \
47 : "i"(AVR32_BUG_OPCODE), "i"(flags), \
48 "i"(sizeof(struct bug_entry)))
49
50#endif /* CONFIG_DEBUG_BUGVERBOSE */
51
33#define BUG() \ 52#define BUG() \
34 do { \ 53 do { \
35 asm volatile(".hword %0\n\t" \ 54 _BUG_OR_WARN(0); \
36 : : "n"(AVR32_BUG_OPCODE)); \ 55 for (;;); \
37 } while (0) 56 } while (0)
38 57
39#endif /* CONFIG_DEBUG_BUGVERBOSE */ 58#define WARN_ON(condition) \
59 ({ \
60 typeof(condition) __ret_warn_on = (condition); \
61 if (unlikely(__ret_warn_on)) \
62 _BUG_OR_WARN(BUGFLAG_WARNING); \
63 unlikely(__ret_warn_on); \
64 })
40 65
41#define HAVE_ARCH_BUG 66#define HAVE_ARCH_BUG
67#define HAVE_ARCH_WARN_ON
42 68
43#endif /* CONFIG_BUG */ 69#endif /* CONFIG_BUG */
44 70
diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index c08e81048393..e30d4b3bd836 100644
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -1,13 +1,15 @@
1#ifndef __ASM_AVR32_IO_H 1#ifndef __ASM_AVR32_IO_H
2#define __ASM_AVR32_IO_H 2#define __ASM_AVR32_IO_H
3 3
4#include <linux/kernel.h>
4#include <linux/string.h> 5#include <linux/string.h>
5 6#include <linux/types.h>
6#ifdef __KERNEL__
7 7
8#include <asm/addrspace.h> 8#include <asm/addrspace.h>
9#include <asm/byteorder.h> 9#include <asm/byteorder.h>
10 10
11#include <asm/arch/io.h>
12
11/* virt_to_phys will only work when address is in P1 or P2 */ 13/* virt_to_phys will only work when address is in P1 or P2 */
12static __inline__ unsigned long virt_to_phys(volatile void *address) 14static __inline__ unsigned long virt_to_phys(volatile void *address)
13{ 15{
@@ -36,104 +38,215 @@ extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
36extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen); 38extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
37extern void __raw_readsl(const void __iomem *addr, void *data, int longlen); 39extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
38 40
39static inline void writeb(unsigned char b, volatile void __iomem *addr) 41static inline void __raw_writeb(u8 v, volatile void __iomem *addr)
40{ 42{
41 *(volatile unsigned char __force *)addr = b; 43 *(volatile u8 __force *)addr = v;
42} 44}
43static inline void writew(unsigned short b, volatile void __iomem *addr) 45static inline void __raw_writew(u16 v, volatile void __iomem *addr)
44{ 46{
45 *(volatile unsigned short __force *)addr = b; 47 *(volatile u16 __force *)addr = v;
46} 48}
47static inline void writel(unsigned int b, volatile void __iomem *addr) 49static inline void __raw_writel(u32 v, volatile void __iomem *addr)
48{ 50{
49 *(volatile unsigned int __force *)addr = b; 51 *(volatile u32 __force *)addr = v;
50} 52}
51#define __raw_writeb writeb
52#define __raw_writew writew
53#define __raw_writel writel
54 53
55static inline unsigned char readb(const volatile void __iomem *addr) 54static inline u8 __raw_readb(const volatile void __iomem *addr)
56{ 55{
57 return *(const volatile unsigned char __force *)addr; 56 return *(const volatile u8 __force *)addr;
58} 57}
59static inline unsigned short readw(const volatile void __iomem *addr) 58static inline u16 __raw_readw(const volatile void __iomem *addr)
60{ 59{
61 return *(const volatile unsigned short __force *)addr; 60 return *(const volatile u16 __force *)addr;
62} 61}
63static inline unsigned int readl(const volatile void __iomem *addr) 62static inline u32 __raw_readl(const volatile void __iomem *addr)
64{ 63{
65 return *(const volatile unsigned int __force *)addr; 64 return *(const volatile u32 __force *)addr;
65}
66
67/* Convert I/O port address to virtual address */
68#ifndef __io
69# define __io(p) ((void *)phys_to_uncached(p))
70#endif
71
72/*
73 * Not really sure about the best way to slow down I/O on
74 * AVR32. Defining it as a no-op until we have an actual test case.
75 */
76#define SLOW_DOWN_IO do { } while (0)
77
78#define __BUILD_MEMORY_SINGLE(pfx, bwl, type) \
79static inline void \
80pfx##write##bwl(type val, volatile void __iomem *addr) \
81{ \
82 volatile type *__addr; \
83 type __val; \
84 \
85 __addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
86 __val = pfx##ioswab##bwl(__addr, val); \
87 \
88 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
89 \
90 *__addr = __val; \
91} \
92 \
93static inline type pfx##read##bwl(const volatile void __iomem *addr) \
94{ \
95 volatile type *__addr; \
96 type __val; \
97 \
98 __addr = (void *)__swizzle_addr_##bwl((unsigned long)(addr)); \
99 \
100 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
101 \
102 __val = *__addr; \
103 return pfx##ioswab##bwl(__addr, __val); \
104}
105
106#define __BUILD_IOPORT_SINGLE(pfx, bwl, type, p, slow) \
107static inline void pfx##out##bwl##p(type val, unsigned long port) \
108{ \
109 volatile type *__addr; \
110 type __val; \
111 \
112 __addr = __io(__swizzle_addr_##bwl(port)); \
113 __val = pfx##ioswab##bwl(__addr, val); \
114 \
115 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
116 \
117 *__addr = __val; \
118 slow; \
119} \
120 \
121static inline type pfx##in##bwl##p(unsigned long port) \
122{ \
123 volatile type *__addr; \
124 type __val; \
125 \
126 __addr = __io(__swizzle_addr_##bwl(port)); \
127 \
128 BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long)); \
129 \
130 __val = *__addr; \
131 slow; \
132 \
133 return pfx##ioswab##bwl(__addr, __val); \
134}
135
136#define __BUILD_MEMORY_PFX(bus, bwl, type) \
137 __BUILD_MEMORY_SINGLE(bus, bwl, type)
138
139#define BUILDIO_MEM(bwl, type) \
140 __BUILD_MEMORY_PFX(, bwl, type) \
141 __BUILD_MEMORY_PFX(__mem_, bwl, type)
142
143#define __BUILD_IOPORT_PFX(bus, bwl, type) \
144 __BUILD_IOPORT_SINGLE(bus, bwl, type, ,) \
145 __BUILD_IOPORT_SINGLE(bus, bwl, type, _p, SLOW_DOWN_IO)
146
147#define BUILDIO_IOPORT(bwl, type) \
148 __BUILD_IOPORT_PFX(, bwl, type) \
149 __BUILD_IOPORT_PFX(__mem_, bwl, type)
150
151BUILDIO_MEM(b, u8)
152BUILDIO_MEM(w, u16)
153BUILDIO_MEM(l, u32)
154
155BUILDIO_IOPORT(b, u8)
156BUILDIO_IOPORT(w, u16)
157BUILDIO_IOPORT(l, u32)
158
159#define readb_relaxed readb
160#define readw_relaxed readw
161#define readl_relaxed readl
162
163#define __BUILD_MEMORY_STRING(bwl, type) \
164static inline void writes##bwl(volatile void __iomem *addr, \
165 const void *data, unsigned int count) \
166{ \
167 const type *__data = data; \
168 \
169 while (count--) \
170 __mem_write##bwl(*__data++, addr); \
171} \
172 \
173static inline void reads##bwl(const volatile void __iomem *addr, \
174 void *data, unsigned int count) \
175{ \
176 type *__data = data; \
177 \
178 while (count--) \
179 *__data++ = __mem_read##bwl(addr); \
66} 180}
67#define __raw_readb readb
68#define __raw_readw readw
69#define __raw_readl readl
70 181
71#define writesb(p, d, l) __raw_writesb((unsigned int)p, d, l) 182#define __BUILD_IOPORT_STRING(bwl, type) \
72#define writesw(p, d, l) __raw_writesw((unsigned int)p, d, l) 183static inline void outs##bwl(unsigned long port, const void *data, \
73#define writesl(p, d, l) __raw_writesl((unsigned int)p, d, l) 184 unsigned int count) \
185{ \
186 const type *__data = data; \
187 \
188 while (count--) \
189 __mem_out##bwl(*__data++, port); \
190} \
191 \
192static inline void ins##bwl(unsigned long port, void *data, \
193 unsigned int count) \
194{ \
195 type *__data = data; \
196 \
197 while (count--) \
198 *__data++ = __mem_in##bwl(port); \
199}
74 200
75#define readsb(p, d, l) __raw_readsb((unsigned int)p, d, l) 201#define BUILDSTRING(bwl, type) \
76#define readsw(p, d, l) __raw_readsw((unsigned int)p, d, l) 202 __BUILD_MEMORY_STRING(bwl, type) \
77#define readsl(p, d, l) __raw_readsl((unsigned int)p, d, l) 203 __BUILD_IOPORT_STRING(bwl, type)
78 204
205BUILDSTRING(b, u8)
206BUILDSTRING(w, u16)
207BUILDSTRING(l, u32)
79 208
80/* 209/*
81 * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be 210 * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
82 */ 211 */
83#ifndef ioread8 212#ifndef ioread8
84 213
85#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; }) 214#define ioread8(p) ((unsigned int)readb(p))
86 215
87#define ioread16(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; }) 216#define ioread16(p) ((unsigned int)readw(p))
88#define ioread16be(p) ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; }) 217#define ioread16be(p) ((unsigned int)__raw_readw(p))
89 218
90#define ioread32(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; }) 219#define ioread32(p) ((unsigned int)readl(p))
91#define ioread32be(p) ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; }) 220#define ioread32be(p) ((unsigned int)__raw_readl(p))
92 221
93#define iowrite8(v,p) __raw_writeb(v, p) 222#define iowrite8(v,p) writeb(v, p)
94 223
95#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p) 224#define iowrite16(v,p) writew(v, p)
96#define iowrite16be(v,p) __raw_writew(cpu_to_be16(v), p) 225#define iowrite16be(v,p) __raw_writew(v, p)
97 226
98#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p) 227#define iowrite32(v,p) writel(v, p)
99#define iowrite32be(v,p) __raw_writel(cpu_to_be32(v), p) 228#define iowrite32be(v,p) __raw_writel(v, p)
100 229
101#define ioread8_rep(p,d,c) __raw_readsb(p,d,c) 230#define ioread8_rep(p,d,c) readsb(p,d,c)
102#define ioread16_rep(p,d,c) __raw_readsw(p,d,c) 231#define ioread16_rep(p,d,c) readsw(p,d,c)
103#define ioread32_rep(p,d,c) __raw_readsl(p,d,c) 232#define ioread32_rep(p,d,c) readsl(p,d,c)
104 233
105#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c) 234#define iowrite8_rep(p,s,c) writesb(p,s,c)
106#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c) 235#define iowrite16_rep(p,s,c) writesw(p,s,c)
107#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c) 236#define iowrite32_rep(p,s,c) writesl(p,s,c)
108 237
109#endif 238#endif
110 239
111
112/*
113 * These two are only here because ALSA _thinks_ it needs them...
114 */
115static inline void memcpy_fromio(void * to, const volatile void __iomem *from, 240static inline void memcpy_fromio(void * to, const volatile void __iomem *from,
116 unsigned long count) 241 unsigned long count)
117{ 242{
118 char *p = to; 243 memcpy(to, (const void __force *)from, count);
119 while (count) {
120 count--;
121 *p = readb(from);
122 p++;
123 from++;
124 }
125} 244}
126 245
127static inline void memcpy_toio(volatile void __iomem *to, const void * from, 246static inline void memcpy_toio(volatile void __iomem *to, const void * from,
128 unsigned long count) 247 unsigned long count)
129{ 248{
130 const char *p = from; 249 memcpy((void __force *)to, from, count);
131 while (count) {
132 count--;
133 writeb(*p, to);
134 p++;
135 to++;
136 }
137} 250}
138 251
139static inline void memset_io(volatile void __iomem *addr, unsigned char val, 252static inline void memset_io(volatile void __iomem *addr, unsigned char val,
@@ -142,99 +255,8 @@ static inline void memset_io(volatile void __iomem *addr, unsigned char val,
142 memset((void __force *)addr, val, count); 255 memset((void __force *)addr, val, count);
143} 256}
144 257
145/*
146 * Bad read/write accesses...
147 */
148extern void __readwrite_bug(const char *fn);
149
150#define IO_SPACE_LIMIT 0xffffffff 258#define IO_SPACE_LIMIT 0xffffffff
151 259
152/* Convert I/O port address to virtual address */
153#define __io(p) ((void __iomem *)phys_to_uncached(p))
154
155/*
156 * IO port access primitives
157 * -------------------------
158 *
159 * The AVR32 doesn't have special IO access instructions; all IO is memory
160 * mapped. Note that these are defined to perform little endian accesses
161 * only. Their primary purpose is to access PCI and ISA peripherals.
162 *
163 * Note that for a big endian machine, this implies that the following
164 * big endian mode connectivity is in place.
165 *
166 * The machine specific io.h include defines __io to translate an "IO"
167 * address to a memory address.
168 *
169 * Note that we prevent GCC re-ordering or caching values in expressions
170 * by introducing sequence points into the in*() definitions. Note that
171 * __raw_* do not guarantee this behaviour.
172 *
173 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
174 */
175#define outb(v, p) __raw_writeb(v, __io(p))
176#define outw(v, p) __raw_writew(cpu_to_le16(v), __io(p))
177#define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p))
178
179#define inb(p) __raw_readb(__io(p))
180#define inw(p) le16_to_cpu(__raw_readw(__io(p)))
181#define inl(p) le32_to_cpu(__raw_readl(__io(p)))
182
183static inline void __outsb(unsigned long port, void *addr, unsigned int count)
184{
185 while (count--) {
186 outb(*(u8 *)addr, port);
187 addr++;
188 }
189}
190
191static inline void __insb(unsigned long port, void *addr, unsigned int count)
192{
193 while (count--) {
194 *(u8 *)addr = inb(port);
195 addr++;
196 }
197}
198
199static inline void __outsw(unsigned long port, void *addr, unsigned int count)
200{
201 while (count--) {
202 outw(*(u16 *)addr, port);
203 addr += 2;
204 }
205}
206
207static inline void __insw(unsigned long port, void *addr, unsigned int count)
208{
209 while (count--) {
210 *(u16 *)addr = inw(port);
211 addr += 2;
212 }
213}
214
215static inline void __outsl(unsigned long port, void *addr, unsigned int count)
216{
217 while (count--) {
218 outl(*(u32 *)addr, port);
219 addr += 4;
220 }
221}
222
223static inline void __insl(unsigned long port, void *addr, unsigned int count)
224{
225 while (count--) {
226 *(u32 *)addr = inl(port);
227 addr += 4;
228 }
229}
230
231#define outsb(port, addr, count) __outsb(port, addr, count)
232#define insb(port, addr, count) __insb(port, addr, count)
233#define outsw(port, addr, count) __outsw(port, addr, count)
234#define insw(port, addr, count) __insw(port, addr, count)
235#define outsl(port, addr, count) __outsl(port, addr, count)
236#define insl(port, addr, count) __insl(port, addr, count)
237
238extern void __iomem *__ioremap(unsigned long offset, size_t size, 260extern void __iomem *__ioremap(unsigned long offset, size_t size,
239 unsigned long flags); 261 unsigned long flags);
240extern void __iounmap(void __iomem *addr); 262extern void __iounmap(void __iomem *addr);
@@ -292,6 +314,4 @@ extern void __iounmap(void __iomem *addr);
292 */ 314 */
293#define xlate_dev_kmem_ptr(p) p 315#define xlate_dev_kmem_ptr(p) p
294 316
295#endif /* __KERNEL__ */
296
297#endif /* __ASM_AVR32_IO_H */ 317#endif /* __ASM_AVR32_IO_H */
diff --git a/include/asm-avr32/processor.h b/include/asm-avr32/processor.h
index f6913778a45f..6a64833756a6 100644
--- a/include/asm-avr32/processor.h
+++ b/include/asm-avr32/processor.h
@@ -40,6 +40,14 @@ enum tlb_config {
40 TLB_INVALID 40 TLB_INVALID
41}; 41};
42 42
43#define AVR32_FEATURE_RMW (1 << 0)
44#define AVR32_FEATURE_DSP (1 << 1)
45#define AVR32_FEATURE_SIMD (1 << 2)
46#define AVR32_FEATURE_OCD (1 << 3)
47#define AVR32_FEATURE_PCTR (1 << 4)
48#define AVR32_FEATURE_JAVA (1 << 5)
49#define AVR32_FEATURE_FPU (1 << 6)
50
43struct avr32_cpuinfo { 51struct avr32_cpuinfo {
44 struct clk *clk; 52 struct clk *clk;
45 unsigned long loops_per_jiffy; 53 unsigned long loops_per_jiffy;
@@ -48,6 +56,7 @@ struct avr32_cpuinfo {
48 unsigned short arch_revision; 56 unsigned short arch_revision;
49 unsigned short cpu_revision; 57 unsigned short cpu_revision;
50 enum tlb_config tlb_config; 58 enum tlb_config tlb_config;
59 unsigned long features;
51 60
52 struct cache_info icache; 61 struct cache_info icache;
53 struct cache_info dcache; 62 struct cache_info dcache;
@@ -125,10 +134,10 @@ extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
125#define thread_saved_pc(tsk) ((tsk)->thread.cpu_context.pc) 134#define thread_saved_pc(tsk) ((tsk)->thread.cpu_context.pc)
126 135
127struct pt_regs; 136struct pt_regs;
128void show_trace(struct task_struct *task, unsigned long *stack,
129 struct pt_regs *regs);
130
131extern unsigned long get_wchan(struct task_struct *p); 137extern unsigned long get_wchan(struct task_struct *p);
138extern void show_regs_log_lvl(struct pt_regs *regs, const char *log_lvl);
139extern void show_stack_log_lvl(struct task_struct *tsk, unsigned long sp,
140 struct pt_regs *regs, const char *log_lvl);
132 141
133#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc) 142#define KSTK_EIP(tsk) ((tsk)->thread.cpu_context.pc)
134#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp) 143#define KSTK_ESP(tsk) ((tsk)->thread.cpu_context.ksp)
diff --git a/include/asm-avr32/setup.h b/include/asm-avr32/setup.h
index 0a5224245e44..1ff1a217015d 100644
--- a/include/asm-avr32/setup.h
+++ b/include/asm-avr32/setup.h
@@ -124,19 +124,12 @@ struct tagtable {
124#define for_each_tag(t,base) \ 124#define for_each_tag(t,base) \
125 for (t = base; t->hdr.size; t = tag_next(t)) 125 for (t = base; t->hdr.size; t = tag_next(t))
126 126
127extern struct tag_mem_range *mem_phys;
128extern struct tag_mem_range *mem_reserved;
129extern struct tag_mem_range *mem_ramdisk;
130
131extern struct tag *bootloader_tags; 127extern struct tag *bootloader_tags;
132 128
133extern void setup_bootmem(void); 129extern resource_size_t fbmem_start;
134extern void setup_processor(void); 130extern resource_size_t fbmem_size;
135extern void board_setup_fbmem(unsigned long fbmem_start,
136 unsigned long fbmem_size);
137 131
138/* Chip-specific hook to enable the use of SDRAM */ 132void setup_processor(void);
139void chip_enable_sdram(void);
140 133
141#endif /* !__ASSEMBLY__ */ 134#endif /* !__ASSEMBLY__ */
142 135
diff --git a/include/asm-avr32/sysreg.h b/include/asm-avr32/sysreg.h
index f91975f330f6..c02bc8304b13 100644
--- a/include/asm-avr32/sysreg.h
+++ b/include/asm-avr32/sysreg.h
@@ -7,326 +7,281 @@
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 */ 9 */
10#ifndef __ASM_AVR32_SYSREG_H__ 10#ifndef __ASM_AVR32_SYSREG_H
11#define __ASM_AVR32_SYSREG_H__ 11#define __ASM_AVR32_SYSREG_H
12 12
13/* sysreg register offsets */ 13/* sysreg register offsets */
14#define SYSREG_SR 0x0000 14#define SYSREG_SR 0x0000
15#define SYSREG_EVBA 0x0004 15#define SYSREG_EVBA 0x0004
16#define SYSREG_ACBA 0x0008 16#define SYSREG_ACBA 0x0008
17#define SYSREG_CPUCR 0x000c 17#define SYSREG_CPUCR 0x000c
18#define SYSREG_ECR 0x0010 18#define SYSREG_ECR 0x0010
19#define SYSREG_RSR_SUP 0x0014 19#define SYSREG_RSR_SUP 0x0014
20#define SYSREG_RSR_INT0 0x0018 20#define SYSREG_RSR_INT0 0x0018
21#define SYSREG_RSR_INT1 0x001c 21#define SYSREG_RSR_INT1 0x001c
22#define SYSREG_RSR_INT2 0x0020 22#define SYSREG_RSR_INT2 0x0020
23#define SYSREG_RSR_INT3 0x0024 23#define SYSREG_RSR_INT3 0x0024
24#define SYSREG_RSR_EX 0x0028 24#define SYSREG_RSR_EX 0x0028
25#define SYSREG_RSR_NMI 0x002c 25#define SYSREG_RSR_NMI 0x002c
26#define SYSREG_RSR_DBG 0x0030 26#define SYSREG_RSR_DBG 0x0030
27#define SYSREG_RAR_SUP 0x0034 27#define SYSREG_RAR_SUP 0x0034
28#define SYSREG_RAR_INT0 0x0038 28#define SYSREG_RAR_INT0 0x0038
29#define SYSREG_RAR_INT1 0x003c 29#define SYSREG_RAR_INT1 0x003c
30#define SYSREG_RAR_INT2 0x0040 30#define SYSREG_RAR_INT2 0x0040
31#define SYSREG_RAR_INT3 0x0044 31#define SYSREG_RAR_INT3 0x0044
32#define SYSREG_RAR_EX 0x0048 32#define SYSREG_RAR_EX 0x0048
33#define SYSREG_RAR_NMI 0x004c 33#define SYSREG_RAR_NMI 0x004c
34#define SYSREG_RAR_DBG 0x0050 34#define SYSREG_RAR_DBG 0x0050
35#define SYSREG_JECR 0x0054 35#define SYSREG_JECR 0x0054
36#define SYSREG_JOSP 0x0058 36#define SYSREG_JOSP 0x0058
37#define SYSREG_JAVA_LV0 0x005c 37#define SYSREG_JAVA_LV0 0x005c
38#define SYSREG_JAVA_LV1 0x0060 38#define SYSREG_JAVA_LV1 0x0060
39#define SYSREG_JAVA_LV2 0x0064 39#define SYSREG_JAVA_LV2 0x0064
40#define SYSREG_JAVA_LV3 0x0068 40#define SYSREG_JAVA_LV3 0x0068
41#define SYSREG_JAVA_LV4 0x006c 41#define SYSREG_JAVA_LV4 0x006c
42#define SYSREG_JAVA_LV5 0x0070 42#define SYSREG_JAVA_LV5 0x0070
43#define SYSREG_JAVA_LV6 0x0074 43#define SYSREG_JAVA_LV6 0x0074
44#define SYSREG_JAVA_LV7 0x0078 44#define SYSREG_JAVA_LV7 0x0078
45#define SYSREG_JTBA 0x007c 45#define SYSREG_JTBA 0x007c
46#define SYSREG_JBCR 0x0080 46#define SYSREG_JBCR 0x0080
47#define SYSREG_CONFIG0 0x0100 47#define SYSREG_CONFIG0 0x0100
48#define SYSREG_CONFIG1 0x0104 48#define SYSREG_CONFIG1 0x0104
49#define SYSREG_COUNT 0x0108 49#define SYSREG_COUNT 0x0108
50#define SYSREG_COMPARE 0x010c 50#define SYSREG_COMPARE 0x010c
51#define SYSREG_TLBEHI 0x0110 51#define SYSREG_TLBEHI 0x0110
52#define SYSREG_TLBELO 0x0114 52#define SYSREG_TLBELO 0x0114
53#define SYSREG_PTBR 0x0118 53#define SYSREG_PTBR 0x0118
54#define SYSREG_TLBEAR 0x011c 54#define SYSREG_TLBEAR 0x011c
55#define SYSREG_MMUCR 0x0120 55#define SYSREG_MMUCR 0x0120
56#define SYSREG_TLBARLO 0x0124 56#define SYSREG_TLBARLO 0x0124
57#define SYSREG_TLBARHI 0x0128 57#define SYSREG_TLBARHI 0x0128
58#define SYSREG_PCCNT 0x012c 58#define SYSREG_PCCNT 0x012c
59#define SYSREG_PCNT0 0x0130 59#define SYSREG_PCNT0 0x0130
60#define SYSREG_PCNT1 0x0134 60#define SYSREG_PCNT1 0x0134
61#define SYSREG_PCCR 0x0138 61#define SYSREG_PCCR 0x0138
62#define SYSREG_BEAR 0x013c 62#define SYSREG_BEAR 0x013c
63#define SYSREG_SABAL 0x0300
64#define SYSREG_SABAH 0x0304
65#define SYSREG_SABD 0x0308
63 66
64/* Bitfields in SR */ 67/* Bitfields in SR */
65#define SYSREG_SR_C_OFFSET 0 68#define SYSREG_SR_C_OFFSET 0
66#define SYSREG_SR_C_SIZE 1 69#define SYSREG_SR_C_SIZE 1
67#define SYSREG_Z_OFFSET 1 70#define SYSREG_Z_OFFSET 1
68#define SYSREG_Z_SIZE 1 71#define SYSREG_Z_SIZE 1
69#define SYSREG_SR_N_OFFSET 2 72#define SYSREG_SR_N_OFFSET 2
70#define SYSREG_SR_N_SIZE 1 73#define SYSREG_SR_N_SIZE 1
71#define SYSREG_SR_V_OFFSET 3 74#define SYSREG_SR_V_OFFSET 3
72#define SYSREG_SR_V_SIZE 1 75#define SYSREG_SR_V_SIZE 1
73#define SYSREG_Q_OFFSET 4 76#define SYSREG_Q_OFFSET 4
74#define SYSREG_Q_SIZE 1 77#define SYSREG_Q_SIZE 1
75#define SYSREG_GM_OFFSET 16 78#define SYSREG_L_OFFSET 5
76#define SYSREG_GM_SIZE 1 79#define SYSREG_L_SIZE 1
77#define SYSREG_I0M_OFFSET 17 80#define SYSREG_T_OFFSET 14
78#define SYSREG_I0M_SIZE 1 81#define SYSREG_T_SIZE 1
79#define SYSREG_I1M_OFFSET 18 82#define SYSREG_SR_R_OFFSET 15
80#define SYSREG_I1M_SIZE 1 83#define SYSREG_SR_R_SIZE 1
81#define SYSREG_I2M_OFFSET 19 84#define SYSREG_GM_OFFSET 16
82#define SYSREG_I2M_SIZE 1 85#define SYSREG_GM_SIZE 1
83#define SYSREG_I3M_OFFSET 20 86#define SYSREG_I0M_OFFSET 17
84#define SYSREG_I3M_SIZE 1 87#define SYSREG_I0M_SIZE 1
85#define SYSREG_EM_OFFSET 21 88#define SYSREG_I1M_OFFSET 18
86#define SYSREG_EM_SIZE 1 89#define SYSREG_I1M_SIZE 1
87#define SYSREG_M0_OFFSET 22 90#define SYSREG_I2M_OFFSET 19
88#define SYSREG_M0_SIZE 1 91#define SYSREG_I2M_SIZE 1
89#define SYSREG_M1_OFFSET 23 92#define SYSREG_I3M_OFFSET 20
90#define SYSREG_M1_SIZE 1 93#define SYSREG_I3M_SIZE 1
91#define SYSREG_M2_OFFSET 24 94#define SYSREG_EM_OFFSET 21
92#define SYSREG_M2_SIZE 1 95#define SYSREG_EM_SIZE 1
93#define SYSREG_SR_D_OFFSET 26 96#define SYSREG_M0_OFFSET 22
94#define SYSREG_SR_D_SIZE 1 97#define SYSREG_M0_SIZE 1
95#define SYSREG_DM_OFFSET 27 98#define SYSREG_M1_OFFSET 23
96#define SYSREG_DM_SIZE 1 99#define SYSREG_M1_SIZE 1
97#define SYSREG_SR_J_OFFSET 28 100#define SYSREG_M2_OFFSET 24
98#define SYSREG_SR_J_SIZE 1 101#define SYSREG_M2_SIZE 1
99#define SYSREG_R_OFFSET 29 102#define SYSREG_SR_D_OFFSET 26
100#define SYSREG_R_SIZE 1 103#define SYSREG_SR_D_SIZE 1
101#define SYSREG_H_OFFSET 30 104#define SYSREG_DM_OFFSET 27
102#define SYSREG_H_SIZE 1 105#define SYSREG_DM_SIZE 1
103 106#define SYSREG_SR_J_OFFSET 28
104/* Bitfields in EVBA */ 107#define SYSREG_SR_J_SIZE 1
105 108#define SYSREG_H_OFFSET 29
106/* Bitfields in ACBA */ 109#define SYSREG_H_SIZE 1
107 110
108/* Bitfields in CPUCR */ 111/* Bitfields in CPUCR */
109#define SYSREG_BI_OFFSET 0 112#define SYSREG_BI_OFFSET 0
110#define SYSREG_BI_SIZE 1 113#define SYSREG_BI_SIZE 1
111#define SYSREG_BE_OFFSET 1 114#define SYSREG_BE_OFFSET 1
112#define SYSREG_BE_SIZE 1 115#define SYSREG_BE_SIZE 1
113#define SYSREG_FE_OFFSET 2 116#define SYSREG_FE_OFFSET 2
114#define SYSREG_FE_SIZE 1 117#define SYSREG_FE_SIZE 1
115#define SYSREG_RE_OFFSET 3 118#define SYSREG_RE_OFFSET 3
116#define SYSREG_RE_SIZE 1 119#define SYSREG_RE_SIZE 1
117#define SYSREG_IBE_OFFSET 4 120#define SYSREG_IBE_OFFSET 4
118#define SYSREG_IBE_SIZE 1 121#define SYSREG_IBE_SIZE 1
119#define SYSREG_IEE_OFFSET 5 122#define SYSREG_IEE_OFFSET 5
120#define SYSREG_IEE_SIZE 1 123#define SYSREG_IEE_SIZE 1
121
122/* Bitfields in ECR */
123#define SYSREG_ECR_OFFSET 0
124#define SYSREG_ECR_SIZE 32
125
126/* Bitfields in RSR_SUP */
127
128/* Bitfields in RSR_INT0 */
129
130/* Bitfields in RSR_INT1 */
131
132/* Bitfields in RSR_INT2 */
133
134/* Bitfields in RSR_INT3 */
135
136/* Bitfields in RSR_EX */
137
138/* Bitfields in RSR_NMI */
139
140/* Bitfields in RSR_DBG */
141
142/* Bitfields in RAR_SUP */
143
144/* Bitfields in RAR_INT0 */
145
146/* Bitfields in RAR_INT1 */
147
148/* Bitfields in RAR_INT2 */
149
150/* Bitfields in RAR_INT3 */
151
152/* Bitfields in RAR_EX */
153
154/* Bitfields in RAR_NMI */
155
156/* Bitfields in RAR_DBG */
157
158/* Bitfields in JECR */
159
160/* Bitfields in JOSP */
161
162/* Bitfields in JAVA_LV0 */
163
164/* Bitfields in JAVA_LV1 */
165
166/* Bitfields in JAVA_LV2 */
167
168/* Bitfields in JAVA_LV3 */
169
170/* Bitfields in JAVA_LV4 */
171
172/* Bitfields in JAVA_LV5 */
173
174/* Bitfields in JAVA_LV6 */
175
176/* Bitfields in JAVA_LV7 */
177
178/* Bitfields in JTBA */
179
180/* Bitfields in JBCR */
181 124
182/* Bitfields in CONFIG0 */ 125/* Bitfields in CONFIG0 */
183#define SYSREG_CONFIG0_D_OFFSET 1 126#define SYSREG_CONFIG0_R_OFFSET 0
184#define SYSREG_CONFIG0_D_SIZE 1 127#define SYSREG_CONFIG0_R_SIZE 1
185#define SYSREG_CONFIG0_S_OFFSET 2 128#define SYSREG_CONFIG0_D_OFFSET 1
186#define SYSREG_CONFIG0_S_SIZE 1 129#define SYSREG_CONFIG0_D_SIZE 1
187#define SYSREG_O_OFFSET 3 130#define SYSREG_CONFIG0_S_OFFSET 2
188#define SYSREG_O_SIZE 1 131#define SYSREG_CONFIG0_S_SIZE 1
189#define SYSREG_P_OFFSET 4 132#define SYSREG_CONFIG0_O_OFFSET 3
190#define SYSREG_P_SIZE 1 133#define SYSREG_CONFIG0_O_SIZE 1
191#define SYSREG_CONFIG0_J_OFFSET 5 134#define SYSREG_CONFIG0_P_OFFSET 4
192#define SYSREG_CONFIG0_J_SIZE 1 135#define SYSREG_CONFIG0_P_SIZE 1
193#define SYSREG_F_OFFSET 6 136#define SYSREG_CONFIG0_J_OFFSET 5
194#define SYSREG_F_SIZE 1 137#define SYSREG_CONFIG0_J_SIZE 1
195#define SYSREG_MMUT_OFFSET 7 138#define SYSREG_CONFIG0_F_OFFSET 6
196#define SYSREG_MMUT_SIZE 3 139#define SYSREG_CONFIG0_F_SIZE 1
197#define SYSREG_AR_OFFSET 10 140#define SYSREG_MMUT_OFFSET 7
198#define SYSREG_AR_SIZE 3 141#define SYSREG_MMUT_SIZE 3
199#define SYSREG_AT_OFFSET 13 142#define SYSREG_AR_OFFSET 10
200#define SYSREG_AT_SIZE 3 143#define SYSREG_AR_SIZE 3
201#define SYSREG_PROCESSORREVISION_OFFSET 16 144#define SYSREG_AT_OFFSET 13
202#define SYSREG_PROCESSORREVISION_SIZE 8 145#define SYSREG_AT_SIZE 3
203#define SYSREG_PROCESSORID_OFFSET 24 146#define SYSREG_PROCESSORREVISION_OFFSET 16
204#define SYSREG_PROCESSORID_SIZE 8 147#define SYSREG_PROCESSORREVISION_SIZE 8
148#define SYSREG_PROCESSORID_OFFSET 24
149#define SYSREG_PROCESSORID_SIZE 8
205 150
206/* Bitfields in CONFIG1 */ 151/* Bitfields in CONFIG1 */
207#define SYSREG_DASS_OFFSET 0 152#define SYSREG_DASS_OFFSET 0
208#define SYSREG_DASS_SIZE 3 153#define SYSREG_DASS_SIZE 3
209#define SYSREG_DLSZ_OFFSET 3 154#define SYSREG_DLSZ_OFFSET 3
210#define SYSREG_DLSZ_SIZE 3 155#define SYSREG_DLSZ_SIZE 3
211#define SYSREG_DSET_OFFSET 6 156#define SYSREG_DSET_OFFSET 6
212#define SYSREG_DSET_SIZE 4 157#define SYSREG_DSET_SIZE 4
213#define SYSREG_IASS_OFFSET 10 158#define SYSREG_IASS_OFFSET 10
214#define SYSREG_IASS_SIZE 2 159#define SYSREG_IASS_SIZE 3
215#define SYSREG_ILSZ_OFFSET 13 160#define SYSREG_ILSZ_OFFSET 13
216#define SYSREG_ILSZ_SIZE 3 161#define SYSREG_ILSZ_SIZE 3
217#define SYSREG_ISET_OFFSET 16 162#define SYSREG_ISET_OFFSET 16
218#define SYSREG_ISET_SIZE 4 163#define SYSREG_ISET_SIZE 4
219#define SYSREG_DMMUSZ_OFFSET 20 164#define SYSREG_DMMUSZ_OFFSET 20
220#define SYSREG_DMMUSZ_SIZE 6 165#define SYSREG_DMMUSZ_SIZE 6
221#define SYSREG_IMMUSZ_OFFSET 26 166#define SYSREG_IMMUSZ_OFFSET 26
222#define SYSREG_IMMUSZ_SIZE 6 167#define SYSREG_IMMUSZ_SIZE 6
223
224/* Bitfields in COUNT */
225
226/* Bitfields in COMPARE */
227 168
228/* Bitfields in TLBEHI */ 169/* Bitfields in TLBEHI */
229#define SYSREG_ASID_OFFSET 0 170#define SYSREG_ASID_OFFSET 0
230#define SYSREG_ASID_SIZE 8 171#define SYSREG_ASID_SIZE 8
231#define SYSREG_TLBEHI_I_OFFSET 8 172#define SYSREG_TLBEHI_I_OFFSET 8
232#define SYSREG_TLBEHI_I_SIZE 1 173#define SYSREG_TLBEHI_I_SIZE 1
233#define SYSREG_TLBEHI_V_OFFSET 9 174#define SYSREG_TLBEHI_V_OFFSET 9
234#define SYSREG_TLBEHI_V_SIZE 1 175#define SYSREG_TLBEHI_V_SIZE 1
235#define SYSREG_VPN_OFFSET 10 176#define SYSREG_VPN_OFFSET 10
236#define SYSREG_VPN_SIZE 22 177#define SYSREG_VPN_SIZE 22
237 178
238/* Bitfields in TLBELO */ 179/* Bitfields in TLBELO */
239#define SYSREG_W_OFFSET 0 180#define SYSREG_W_OFFSET 0
240#define SYSREG_W_SIZE 1 181#define SYSREG_W_SIZE 1
241#define SYSREG_TLBELO_D_OFFSET 1 182#define SYSREG_TLBELO_D_OFFSET 1
242#define SYSREG_TLBELO_D_SIZE 1 183#define SYSREG_TLBELO_D_SIZE 1
243#define SYSREG_SZ_OFFSET 2 184#define SYSREG_SZ_OFFSET 2
244#define SYSREG_SZ_SIZE 2 185#define SYSREG_SZ_SIZE 2
245#define SYSREG_AP_OFFSET 4 186#define SYSREG_AP_OFFSET 4
246#define SYSREG_AP_SIZE 3 187#define SYSREG_AP_SIZE 3
247#define SYSREG_B_OFFSET 7 188#define SYSREG_B_OFFSET 7
248#define SYSREG_B_SIZE 1 189#define SYSREG_B_SIZE 1
249#define SYSREG_G_OFFSET 8 190#define SYSREG_G_OFFSET 8
250#define SYSREG_G_SIZE 1 191#define SYSREG_G_SIZE 1
251#define SYSREG_TLBELO_C_OFFSET 9 192#define SYSREG_TLBELO_C_OFFSET 9
252#define SYSREG_TLBELO_C_SIZE 1 193#define SYSREG_TLBELO_C_SIZE 1
253#define SYSREG_PFN_OFFSET 10 194#define SYSREG_PFN_OFFSET 10
254#define SYSREG_PFN_SIZE 22 195#define SYSREG_PFN_SIZE 22
255
256/* Bitfields in PTBR */
257
258/* Bitfields in TLBEAR */
259 196
260/* Bitfields in MMUCR */ 197/* Bitfields in MMUCR */
261#define SYSREG_E_OFFSET 0 198#define SYSREG_E_OFFSET 0
262#define SYSREG_E_SIZE 1 199#define SYSREG_E_SIZE 1
263#define SYSREG_M_OFFSET 1 200#define SYSREG_M_OFFSET 1
264#define SYSREG_M_SIZE 1 201#define SYSREG_M_SIZE 1
265#define SYSREG_MMUCR_I_OFFSET 2 202#define SYSREG_MMUCR_I_OFFSET 2
266#define SYSREG_MMUCR_I_SIZE 1 203#define SYSREG_MMUCR_I_SIZE 1
267#define SYSREG_MMUCR_N_OFFSET 3 204#define SYSREG_MMUCR_N_OFFSET 3
268#define SYSREG_MMUCR_N_SIZE 1 205#define SYSREG_MMUCR_N_SIZE 1
269#define SYSREG_MMUCR_S_OFFSET 4 206#define SYSREG_MMUCR_S_OFFSET 4
270#define SYSREG_MMUCR_S_SIZE 1 207#define SYSREG_MMUCR_S_SIZE 1
271#define SYSREG_DLA_OFFSET 8 208#define SYSREG_DLA_OFFSET 8
272#define SYSREG_DLA_SIZE 6 209#define SYSREG_DLA_SIZE 6
273#define SYSREG_DRP_OFFSET 14 210#define SYSREG_DRP_OFFSET 14
274#define SYSREG_DRP_SIZE 6 211#define SYSREG_DRP_SIZE 6
275#define SYSREG_ILA_OFFSET 20 212#define SYSREG_ILA_OFFSET 20
276#define SYSREG_ILA_SIZE 6 213#define SYSREG_ILA_SIZE 6
277#define SYSREG_IRP_OFFSET 26 214#define SYSREG_IRP_OFFSET 26
278#define SYSREG_IRP_SIZE 6 215#define SYSREG_IRP_SIZE 6
279
280/* Bitfields in TLBARLO */
281
282/* Bitfields in TLBARHI */
283
284/* Bitfields in PCCNT */
285
286/* Bitfields in PCNT0 */
287
288/* Bitfields in PCNT1 */
289 216
290/* Bitfields in PCCR */ 217/* Bitfields in PCCR */
291 218#define SYSREG_PCCR_R_OFFSET 1
292/* Bitfields in BEAR */ 219#define SYSREG_PCCR_R_SIZE 1
220#define SYSREG_PCCR_C_OFFSET 2
221#define SYSREG_PCCR_C_SIZE 1
222#define SYSREG_PCCR_S_OFFSET 3
223#define SYSREG_PCCR_S_SIZE 1
224#define SYSREG_IEC_OFFSET 4
225#define SYSREG_IEC_SIZE 1
226#define SYSREG_IE0_OFFSET 5
227#define SYSREG_IE0_SIZE 1
228#define SYSREG_IE1_OFFSET 6
229#define SYSREG_IE1_SIZE 1
230#define SYSREG_FC_OFFSET 8
231#define SYSREG_FC_SIZE 1
232#define SYSREG_F0_OFFSET 9
233#define SYSREG_F0_SIZE 1
234#define SYSREG_F1_OFFSET 10
235#define SYSREG_F1_SIZE 1
236#define SYSREG_CONF0_OFFSET 12
237#define SYSREG_CONF0_SIZE 6
238#define SYSREG_CONF1_OFFSET 18
239#define SYSREG_CONF1_SIZE 6
293 240
294/* Constants for ECR */ 241/* Constants for ECR */
295#define ECR_UNRECOVERABLE 0 242#define ECR_UNRECOVERABLE 0
296#define ECR_TLB_MULTIPLE 1 243#define ECR_TLB_MULTIPLE 1
297#define ECR_BUS_ERROR_WRITE 2 244#define ECR_BUS_ERROR_WRITE 2
298#define ECR_BUS_ERROR_READ 3 245#define ECR_BUS_ERROR_READ 3
299#define ECR_NMI 4 246#define ECR_NMI 4
300#define ECR_ADDR_ALIGN_X 5 247#define ECR_ADDR_ALIGN_X 5
301#define ECR_PROTECTION_X 6 248#define ECR_PROTECTION_X 6
302#define ECR_DEBUG 7 249#define ECR_DEBUG 7
303#define ECR_ILLEGAL_OPCODE 8 250#define ECR_ILLEGAL_OPCODE 8
304#define ECR_UNIMPL_INSTRUCTION 9 251#define ECR_UNIMPL_INSTRUCTION 9
305#define ECR_PRIVILEGE_VIOLATION 10 252#define ECR_PRIVILEGE_VIOLATION 10
306#define ECR_FPE 11 253#define ECR_FPE 11
307#define ECR_COPROC_ABSENT 12 254#define ECR_COPROC_ABSENT 12
308#define ECR_ADDR_ALIGN_R 13 255#define ECR_ADDR_ALIGN_R 13
309#define ECR_ADDR_ALIGN_W 14 256#define ECR_ADDR_ALIGN_W 14
310#define ECR_PROTECTION_R 15 257#define ECR_PROTECTION_R 15
311#define ECR_PROTECTION_W 16 258#define ECR_PROTECTION_W 16
312#define ECR_DTLB_MODIFIED 17 259#define ECR_DTLB_MODIFIED 17
313#define ECR_TLB_MISS_X 20 260#define ECR_TLB_MISS_X 20
314#define ECR_TLB_MISS_R 24 261#define ECR_TLB_MISS_R 24
315#define ECR_TLB_MISS_W 28 262#define ECR_TLB_MISS_W 28
316 263
317/* Bit manipulation macros */ 264/* Bit manipulation macros */
318#define SYSREG_BIT(name) (1 << SYSREG_##name##_OFFSET) 265#define SYSREG_BIT(name) \
319#define SYSREG_BF(name,value) (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) << SYSREG_##name##_OFFSET) 266 (1 << SYSREG_##name##_OFFSET)
320#define SYSREG_BFEXT(name,value) (((value) >> SYSREG_##name##_OFFSET) & ((1 << SYSREG_##name##_SIZE) - 1)) 267#define SYSREG_BF(name,value) \
321#define SYSREG_BFINS(name,value,old) (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) << SYSREG_##name##_OFFSET)) | SYSREG_BF(name,value)) 268 (((value) & ((1 << SYSREG_##name##_SIZE) - 1)) \
269 << SYSREG_##name##_OFFSET)
270#define SYSREG_BFEXT(name,value)\
271 (((value) >> SYSREG_##name##_OFFSET) \
272 & ((1 << SYSREG_##name##_SIZE) - 1))
273#define SYSREG_BFINS(name,value,old) \
274 (((old) & ~(((1 << SYSREG_##name##_SIZE) - 1) \
275 << SYSREG_##name##_OFFSET)) \
276 | SYSREG_BF(name,value))
322 277
278/* Register access macros */
323#ifdef __CHECKER__ 279#ifdef __CHECKER__
324extern unsigned long __builtin_mfsr(unsigned long reg); 280extern unsigned long __builtin_mfsr(unsigned long reg);
325extern void __builtin_mtsr(unsigned long reg, unsigned long value); 281extern void __builtin_mtsr(unsigned long reg, unsigned long value);
326#endif 282#endif
327 283
328/* Register access macros */ 284#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg)
329#define sysreg_read(reg) __builtin_mfsr(SYSREG_##reg) 285#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
330#define sysreg_write(reg, value) __builtin_mtsr(SYSREG_##reg, value)
331 286
332#endif /* __ASM_AVR32_SYSREG_H__ */ 287#endif /* __ASM_AVR32_SYSREG_H */
diff --git a/include/asm-avr32/system.h b/include/asm-avr32/system.h
index ac596058697d..a8236bacc878 100644
--- a/include/asm-avr32/system.h
+++ b/include/asm-avr32/system.h
@@ -9,6 +9,7 @@
9#define __ASM_AVR32_SYSTEM_H 9#define __ASM_AVR32_SYSTEM_H
10 10
11#include <linux/compiler.h> 11#include <linux/compiler.h>
12#include <linux/linkage.h>
12#include <linux/types.h> 13#include <linux/types.h>
13 14
14#include <asm/ptrace.h> 15#include <asm/ptrace.h>
@@ -140,15 +141,9 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
140 sizeof(*(ptr)))) 141 sizeof(*(ptr))))
141 142
142struct pt_regs; 143struct pt_regs;
143extern void __die(const char *, struct pt_regs *, unsigned long, 144void NORET_TYPE die(const char *str, struct pt_regs *regs, long err);
144 const char *, const char *, unsigned long); 145void _exception(long signr, struct pt_regs *regs, int code,
145extern void __die_if_kernel(const char *, struct pt_regs *, unsigned long, 146 unsigned long addr);
146 const char *, const char *, unsigned long);
147
148#define die(msg, regs, err) \
149 __die(msg, regs, err, __FILE__ ":", __FUNCTION__, __LINE__)
150#define die_if_kernel(msg, regs, err) \
151 __die_if_kernel(msg, regs, err, __FILE__ ":", __FUNCTION__, __LINE__)
152 147
153#define arch_align_stack(x) (x) 148#define arch_align_stack(x) (x)
154 149
diff --git a/include/asm-avr32/thread_info.h b/include/asm-avr32/thread_info.h
index d1f5b35ebd54..a2e606dd4f4a 100644
--- a/include/asm-avr32/thread_info.h
+++ b/include/asm-avr32/thread_info.h
@@ -83,6 +83,7 @@ static inline struct thread_info *current_thread_info(void)
83#define TIF_SINGLE_STEP 6 /* single step after next break */ 83#define TIF_SINGLE_STEP 6 /* single step after next break */
84#define TIF_MEMDIE 7 84#define TIF_MEMDIE 7
85#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal */ 85#define TIF_RESTORE_SIGMASK 8 /* restore signal mask in do_signal */
86#define TIF_CPU_GOING_TO_SLEEP 9 /* CPU is entering sleep 0 mode */
86#define TIF_USERSPACE 31 /* true if FS sets userspace */ 87#define TIF_USERSPACE 31 /* true if FS sets userspace */
87 88
88#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE) 89#define _TIF_SYSCALL_TRACE (1 << TIF_SYSCALL_TRACE)
@@ -94,6 +95,7 @@ static inline struct thread_info *current_thread_info(void)
94#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP) 95#define _TIF_SINGLE_STEP (1 << TIF_SINGLE_STEP)
95#define _TIF_MEMDIE (1 << TIF_MEMDIE) 96#define _TIF_MEMDIE (1 << TIF_MEMDIE)
96#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK) 97#define _TIF_RESTORE_SIGMASK (1 << TIF_RESTORE_SIGMASK)
98#define _TIF_CPU_GOING_TO_SLEEP (1 << TIF_CPU_GOING_TO_SLEEP)
97 99
98/* XXX: These two masks must never span more than 16 bits! */ 100/* XXX: These two masks must never span more than 16 bits! */
99/* work to do on interrupt/exception return */ 101/* work to do on interrupt/exception return */
diff --git a/include/asm-avr32/uaccess.h b/include/asm-avr32/uaccess.h
index 74a679e9098c..ed092395215e 100644
--- a/include/asm-avr32/uaccess.h
+++ b/include/asm-avr32/uaccess.h
@@ -181,24 +181,23 @@ extern int __put_user_bad(void);
181 181
182#define __get_user_nocheck(x, ptr, size) \ 182#define __get_user_nocheck(x, ptr, size) \
183({ \ 183({ \
184 typeof(*(ptr)) __gu_val = (typeof(*(ptr)) __force)0; \ 184 unsigned long __gu_val = 0; \
185 int __gu_err = 0; \ 185 int __gu_err = 0; \
186 \ 186 \
187 switch (size) { \ 187 switch (size) { \
188 case 1: __get_user_asm("ub", __gu_val, ptr, __gu_err); break; \ 188 case 1: __get_user_asm("ub", __gu_val, ptr, __gu_err); break; \
189 case 2: __get_user_asm("uh", __gu_val, ptr, __gu_err); break; \ 189 case 2: __get_user_asm("uh", __gu_val, ptr, __gu_err); break; \
190 case 4: __get_user_asm("w", __gu_val, ptr, __gu_err); break; \ 190 case 4: __get_user_asm("w", __gu_val, ptr, __gu_err); break; \
191 case 8: __get_user_asm("d", __gu_val, ptr, __gu_err); break; \
192 default: __gu_err = __get_user_bad(); break; \ 191 default: __gu_err = __get_user_bad(); break; \
193 } \ 192 } \
194 \ 193 \
195 x = __gu_val; \ 194 x = (typeof(*(ptr)))__gu_val; \
196 __gu_err; \ 195 __gu_err; \
197}) 196})
198 197
199#define __get_user_check(x, ptr, size) \ 198#define __get_user_check(x, ptr, size) \
200({ \ 199({ \
201 typeof(*(ptr)) __gu_val = (typeof(*(ptr)) __force)0; \ 200 unsigned long __gu_val = 0; \
202 const typeof(*(ptr)) __user * __gu_addr = (ptr); \ 201 const typeof(*(ptr)) __user * __gu_addr = (ptr); \
203 int __gu_err = 0; \ 202 int __gu_err = 0; \
204 \ 203 \
@@ -216,10 +215,6 @@ extern int __put_user_bad(void);
216 __get_user_asm("w", __gu_val, __gu_addr, \ 215 __get_user_asm("w", __gu_val, __gu_addr, \
217 __gu_err); \ 216 __gu_err); \
218 break; \ 217 break; \
219 case 8: \
220 __get_user_asm("d", __gu_val, __gu_addr, \
221 __gu_err); \
222 break; \
223 default: \ 218 default: \
224 __gu_err = __get_user_bad(); \ 219 __gu_err = __get_user_bad(); \
225 break; \ 220 break; \
@@ -227,7 +222,7 @@ extern int __put_user_bad(void);
227 } else { \ 222 } else { \
228 __gu_err = -EFAULT; \ 223 __gu_err = -EFAULT; \
229 } \ 224 } \
230 x = __gu_val; \ 225 x = (typeof(*(ptr)))__gu_val; \
231 __gu_err; \ 226 __gu_err; \
232}) 227})
233 228
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 14:27:15 -0500