video: support DP controller driver

Samsung EXYNOS SoC such Exynos5 has DP controller and embedded DP
panel can be used. This patch supports DP driver based on Samsung
EXYNOS SoC chip.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>

1 files changed, 131 insertions, 0 deletions

diff --git a/include/video/exynos_dp.h b/include/video/exynos_dp.h
new file mode 100644
index 000000000000..8847a9d6dd42
--- /dev/null
+++ b/include/video/exynos_dp.h
@@ -0,0 +1,131 @@
+/*
+ * Samsung SoC DP device support
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _EXYNOS_DP_H
+#define _EXYNOS_DP_H
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 4
+
+enum link_rate_type {
+        LINK_RATE_1_62GBPS = 0x06,
+        LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+        LANE_COUNT1 = 1,
+        LANE_COUNT2 = 2,
+        LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+        START,
+        CLOCK_RECOVERY,
+        EQUALIZER_TRAINING,
+        FINISHED,
+        FAILED
+};
+
+enum voltage_swing_level {
+        VOLTAGE_LEVEL_0,
+        VOLTAGE_LEVEL_1,
+        VOLTAGE_LEVEL_2,
+        VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+        PRE_EMPHASIS_LEVEL_0,
+        PRE_EMPHASIS_LEVEL_1,
+        PRE_EMPHASIS_LEVEL_2,
+        PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+        PRBS7,
+        D10_2,
+        TRAINING_PTN1,
+        TRAINING_PTN2,
+        DP_NONE
+};
+
+enum color_space {
+        COLOR_RGB,
+        COLOR_YCBCR422,
+        COLOR_YCBCR444
+};
+
+enum color_depth {
+        COLOR_6,
+        COLOR_8,
+        COLOR_10,
+        COLOR_12
+};
+
+enum color_coefficient {
+        COLOR_YCBCR601,
+        COLOR_YCBCR709
+};
+
+enum dynamic_range {
+        VESA,
+        CEA
+};
+
+enum pll_status {
+        PLL_UNLOCKED,
+        PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+        CALCULATED_M,
+        REGISTER_M
+};
+
+enum video_timing_recognition_type {
+        VIDEO_TIMING_FROM_CAPTURE,
+        VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+        AUX_BLOCK,
+        CH0_BLOCK,
+        CH1_BLOCK,
+        CH2_BLOCK,
+        CH3_BLOCK,
+        ANALOG_TOTAL,
+        POWER_ALL
+};
+
+struct video_info {
+        char *name;
+
+        bool h_sync_polarity;
+        bool v_sync_polarity;
+        bool interlaced;
+
+        enum color_space color_space;
+        enum dynamic_range dynamic_range;
+        enum color_coefficient ycbcr_coeff;
+        enum color_depth color_depth;
+
+        enum link_rate_type link_rate;
+        enum link_lane_count_type lane_count;
+};
+
+struct exynos_dp_platdata {
+        struct video_info *video_info;
+
+        void (*phy_init)(void);
+        void (*phy_exit)(void);
+};
+
+#endif /* _EXYNOS_DP_H */