diff options
author | Randy Dunlap <randy.dunlap@oracle.com> | 2009-02-04 18:12:20 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-02-05 15:56:48 -0500 |
commit | fe86175bce50bc3d65ff09c287fed955c4da1eb3 (patch) | |
tree | 00cdc9fffe9b539dfbf901d2338c0f337d2faf2f /include/video | |
parent | cd29cf7d112aa022cfcfb257ffe3d89ffbd1d820 (diff) |
atyfb: fix CONFIG_ namespace violations
Fix namespace violations by changing non-kconfig CONFIG_ names to CNFG_*.
Fixes breakage in staging/, which adds a real CONFIG_PANEL.
Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/video')
-rw-r--r-- | include/video/aty128.h | 4 | ||||
-rw-r--r-- | include/video/mach64.h | 24 | ||||
-rw-r--r-- | include/video/radeon.h | 18 |
3 files changed, 23 insertions, 23 deletions
diff --git a/include/video/aty128.h b/include/video/aty128.h index 7079beb005e8..51ac69f05bdc 100644 --- a/include/video/aty128.h +++ b/include/video/aty128.h | |||
@@ -21,9 +21,9 @@ | |||
21 | #define I2C_CNTL_1 0x0094 | 21 | #define I2C_CNTL_1 0x0094 |
22 | #define PALETTE_INDEX 0x00b0 | 22 | #define PALETTE_INDEX 0x00b0 |
23 | #define PALETTE_DATA 0x00b4 | 23 | #define PALETTE_DATA 0x00b4 |
24 | #define CONFIG_CNTL 0x00e0 | 24 | #define CNFG_CNTL 0x00e0 |
25 | #define GEN_RESET_CNTL 0x00f0 | 25 | #define GEN_RESET_CNTL 0x00f0 |
26 | #define CONFIG_MEMSIZE 0x00f8 | 26 | #define CNFG_MEMSIZE 0x00f8 |
27 | #define MEM_CNTL 0x0140 | 27 | #define MEM_CNTL 0x0140 |
28 | #define MEM_POWER_MISC 0x015c | 28 | #define MEM_POWER_MISC 0x015c |
29 | #define AGP_BASE 0x0170 | 29 | #define AGP_BASE 0x0170 |
diff --git a/include/video/mach64.h b/include/video/mach64.h index a8332e528ec1..89e91c0cb737 100644 --- a/include/video/mach64.h +++ b/include/video/mach64.h | |||
@@ -103,7 +103,7 @@ | |||
103 | #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ | 103 | #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ |
104 | #define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ | 104 | #define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */ |
105 | 105 | ||
106 | #define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */ | 106 | #define CNFG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */ |
107 | 107 | ||
108 | /* General I/O Control */ | 108 | /* General I/O Control */ |
109 | #define GP_IO 0x0078 /* Dword offset 0_1E */ | 109 | #define GP_IO 0x0078 /* Dword offset 0_1E */ |
@@ -146,8 +146,8 @@ | |||
146 | #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ | 146 | #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */ |
147 | 147 | ||
148 | /* Configuration */ | 148 | /* Configuration */ |
149 | #define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */ | 149 | #define CNFG_STAT1 0x0094 /* Dword offset 0_25 */ |
150 | #define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */ | 150 | #define CNFG_STAT2 0x0098 /* Dword offset 0_26 */ |
151 | 151 | ||
152 | /* Bus Control */ | 152 | /* Bus Control */ |
153 | #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ | 153 | #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */ |
@@ -190,9 +190,9 @@ | |||
190 | #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ | 190 | #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */ |
191 | 191 | ||
192 | /* Configuration */ | 192 | /* Configuration */ |
193 | #define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ | 193 | #define CNFG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */ |
194 | #define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ | 194 | #define CNFG_CHIP_ID 0x00E0 /* Dword offset 0_38 */ |
195 | #define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */ | 195 | #define CNFG_STAT0 0x00E4 /* Dword offset 0_39 */ |
196 | 196 | ||
197 | /* Test and Debug */ | 197 | /* Test and Debug */ |
198 | #define CRC_SIG 0x00E8 /* Dword offset 0_3A */ | 198 | #define CRC_SIG 0x00E8 /* Dword offset 0_3A */ |
@@ -851,17 +851,17 @@ | |||
851 | #define PLL_YCLK_CNTL 0x29 | 851 | #define PLL_YCLK_CNTL 0x29 |
852 | #define PM_DYN_CLK_CNTL 0x2A | 852 | #define PM_DYN_CLK_CNTL 0x2A |
853 | 853 | ||
854 | /* CONFIG_CNTL register constants */ | 854 | /* CNFG_CNTL register constants */ |
855 | #define APERTURE_4M_ENABLE 1 | 855 | #define APERTURE_4M_ENABLE 1 |
856 | #define APERTURE_8M_ENABLE 2 | 856 | #define APERTURE_8M_ENABLE 2 |
857 | #define VGA_APERTURE_ENABLE 4 | 857 | #define VGA_APERTURE_ENABLE 4 |
858 | 858 | ||
859 | /* CONFIG_STAT0 register constants (GX, CX) */ | 859 | /* CNFG_STAT0 register constants (GX, CX) */ |
860 | #define CFG_BUS_TYPE 0x00000007 | 860 | #define CFG_BUS_TYPE 0x00000007 |
861 | #define CFG_MEM_TYPE 0x00000038 | 861 | #define CFG_MEM_TYPE 0x00000038 |
862 | #define CFG_INIT_DAC_TYPE 0x00000e00 | 862 | #define CFG_INIT_DAC_TYPE 0x00000e00 |
863 | 863 | ||
864 | /* CONFIG_STAT0 register constants (CT, ET, VT) */ | 864 | /* CNFG_STAT0 register constants (CT, ET, VT) */ |
865 | #define CFG_MEM_TYPE_xT 0x00000007 | 865 | #define CFG_MEM_TYPE_xT 0x00000007 |
866 | 866 | ||
867 | #define ISA 0 | 867 | #define ISA 0 |
@@ -942,7 +942,7 @@ | |||
942 | #define PCI_ATI_VENDOR_ID 0x1002 | 942 | #define PCI_ATI_VENDOR_ID 0x1002 |
943 | 943 | ||
944 | 944 | ||
945 | /* CONFIG_CHIP_ID register constants */ | 945 | /* CNFG_CHIP_ID register constants */ |
946 | #define CFG_CHIP_TYPE 0x0000FFFF | 946 | #define CFG_CHIP_TYPE 0x0000FFFF |
947 | #define CFG_CHIP_CLASS 0x00FF0000 | 947 | #define CFG_CHIP_CLASS 0x00FF0000 |
948 | #define CFG_CHIP_REV 0xFF000000 | 948 | #define CFG_CHIP_REV 0xFF000000 |
@@ -951,7 +951,7 @@ | |||
951 | #define CFG_CHIP_MINOR 0xC0000000 | 951 | #define CFG_CHIP_MINOR 0xC0000000 |
952 | 952 | ||
953 | 953 | ||
954 | /* Chip IDs read from CONFIG_CHIP_ID */ | 954 | /* Chip IDs read from CNFG_CHIP_ID */ |
955 | 955 | ||
956 | /* mach64GX family */ | 956 | /* mach64GX family */ |
957 | #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ | 957 | #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */ |
@@ -1254,7 +1254,7 @@ | |||
1254 | #define CRTC2_DISPLAY_DIS 0x00000400 | 1254 | #define CRTC2_DISPLAY_DIS 0x00000400 |
1255 | 1255 | ||
1256 | /* LCD register indices */ | 1256 | /* LCD register indices */ |
1257 | #define CONFIG_PANEL 0x00 | 1257 | #define CNFG_PANEL 0x00 |
1258 | #define LCD_GEN_CNTL 0x01 | 1258 | #define LCD_GEN_CNTL 0x01 |
1259 | #define DSTN_CONTROL 0x02 | 1259 | #define DSTN_CONTROL 0x02 |
1260 | #define HFB_PITCH_ADDR 0x03 | 1260 | #define HFB_PITCH_ADDR 0x03 |
diff --git a/include/video/radeon.h b/include/video/radeon.h index 1cd09cc5b169..e072b16b39ab 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h | |||
@@ -11,13 +11,13 @@ | |||
11 | #define HI_STAT 0x004C | 11 | #define HI_STAT 0x004C |
12 | #define BUS_CNTL1 0x0034 | 12 | #define BUS_CNTL1 0x0034 |
13 | #define I2C_CNTL_1 0x0094 | 13 | #define I2C_CNTL_1 0x0094 |
14 | #define CONFIG_CNTL 0x00E0 | 14 | #define CNFG_CNTL 0x00E0 |
15 | #define CONFIG_MEMSIZE 0x00F8 | 15 | #define CNFG_MEMSIZE 0x00F8 |
16 | #define CONFIG_APER_0_BASE 0x0100 | 16 | #define CNFG_APER_0_BASE 0x0100 |
17 | #define CONFIG_APER_1_BASE 0x0104 | 17 | #define CNFG_APER_1_BASE 0x0104 |
18 | #define CONFIG_APER_SIZE 0x0108 | 18 | #define CNFG_APER_SIZE 0x0108 |
19 | #define CONFIG_REG_1_BASE 0x010C | 19 | #define CNFG_REG_1_BASE 0x010C |
20 | #define CONFIG_REG_APER_SIZE 0x0110 | 20 | #define CNFG_REG_APER_SIZE 0x0110 |
21 | #define PAD_AGPINPUT_DELAY 0x0164 | 21 | #define PAD_AGPINPUT_DELAY 0x0164 |
22 | #define PAD_CTLR_STRENGTH 0x0168 | 22 | #define PAD_CTLR_STRENGTH 0x0168 |
23 | #define PAD_CTLR_UPDATE 0x016C | 23 | #define PAD_CTLR_UPDATE 0x016C |
@@ -509,7 +509,7 @@ | |||
509 | /* CLOCK_CNTL_INDEX bit constants */ | 509 | /* CLOCK_CNTL_INDEX bit constants */ |
510 | #define PLL_WR_EN 0x00000080 | 510 | #define PLL_WR_EN 0x00000080 |
511 | 511 | ||
512 | /* CONFIG_CNTL bit constants */ | 512 | /* CNFG_CNTL bit constants */ |
513 | #define CFG_VGA_RAM_EN 0x00000100 | 513 | #define CFG_VGA_RAM_EN 0x00000100 |
514 | #define CFG_ATI_REV_ID_MASK (0xf << 16) | 514 | #define CFG_ATI_REV_ID_MASK (0xf << 16) |
515 | #define CFG_ATI_REV_A11 (0 << 16) | 515 | #define CFG_ATI_REV_A11 (0 << 16) |
@@ -980,7 +980,7 @@ | |||
980 | 980 | ||
981 | /* masks */ | 981 | /* masks */ |
982 | 982 | ||
983 | #define CONFIG_MEMSIZE_MASK 0x1f000000 | 983 | #define CNFG_MEMSIZE_MASK 0x1f000000 |
984 | #define MEM_CFG_TYPE 0x40000000 | 984 | #define MEM_CFG_TYPE 0x40000000 |
985 | #define DST_OFFSET_MASK 0x003fffff | 985 | #define DST_OFFSET_MASK 0x003fffff |
986 | #define DST_PITCH_MASK 0x3fc00000 | 986 | #define DST_PITCH_MASK 0x3fc00000 |