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authorH. Peter Anvin <hpa@linux.intel.com>2014-02-25 15:05:34 -0500
committerH. Peter Anvin <hpa@linux.intel.com>2014-02-27 11:07:39 -0500
commitc5f9ee3d665a7660b296aa1e91949ae3376f0d07 (patch)
tree1312ff6f48732ff251f40a63f8147453d6d4cf8f /include/video
parent7cf6c94591bbf3dbe3bf9573a6551328ad76d885 (diff)
x86, platforms: Remove SGI Visual Workstation
The SGI Visual Workstation seems to be dead; remove support so we don't have to continue maintaining it. Cc: Andrey Panin <pazke@donpac.ru> Cc: Michael Reed <mdr@sgi.com> Link: http://lkml.kernel.org/r/530CFD6C.7040705@zytor.com Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'include/video')
-rw-r--r--include/video/sgivw.h681
1 files changed, 0 insertions, 681 deletions
diff --git a/include/video/sgivw.h b/include/video/sgivw.h
deleted file mode 100644
index f6aa5692e74b..000000000000
--- a/include/video/sgivw.h
+++ /dev/null
@@ -1,681 +0,0 @@
1/*
2 * linux/drivers/video/sgivw.h -- SGI DBE frame buffer device header
3 *
4 * Copyright (C) 1999 Silicon Graphics, Inc.
5 * Jeffrey Newquist, newquist@engr.sgi.som
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file COPYING in the main directory of this archive for
9 * more details.
10 */
11
12#ifndef __SGIVWFB_H__
13#define __SGIVWFB_H__
14
15#define DBE_GETREG(reg, dest) ((dest) = DBE_REG_BASE->reg)
16#define DBE_SETREG(reg, src) DBE_REG_BASE->reg = (src)
17#define DBE_IGETREG(reg, idx, dest) ((dest) = DBE_REG_BASE->reg[idx])
18#define DBE_ISETREG(reg, idx, src) (DBE_REG_BASE->reg[idx] = (src))
19
20#define MASK(msb, lsb) ( (((u32)1<<((msb)-(lsb)+1))-1) << (lsb) )
21#define GET(v, msb, lsb) ( ((u32)(v) & MASK(msb,lsb)) >> (lsb) )
22#define SET(v, f, msb, lsb) ( (v) = ((v)&~MASK(msb,lsb)) | (( (u32)(f)<<(lsb) ) & MASK(msb,lsb)) )
23
24#define GET_DBE_FIELD(reg, field, v) GET((v), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
25#define SET_DBE_FIELD(reg, field, v, f) SET((v), (f), DBE_##reg##_##field##_MSB, DBE_##reg##_##field##_LSB)
26
27/* NOTE: All loads/stores must be 32 bits and uncached */
28
29#define DBE_REG_PHYS 0xd0000000
30#define DBE_REG_SIZE 0x01000000
31
32struct asregs {
33 volatile u32 ctrlstat; /* 0x000000 general control */
34 volatile u32 dotclock; /* 0x000004 dot clock PLL control */
35 volatile u32 i2c; /* 0x000008 crt I2C control */
36 volatile u32 sysclk; /* 0x00000c system clock PLL control */
37 volatile u32 i2cfp; /* 0x000010 flat panel I2C control */
38 volatile u32 id; /* 0x000014 device id/chip revision */
39 volatile u32 config; /* 0x000018 power on configuration */
40 volatile u32 bist; /* 0x00001c internal bist status */
41
42 char _pad0[ 0x010000 - 0x000020 ];
43
44 volatile u32 vt_xy; /* 0x010000 current dot coords */
45 volatile u32 vt_xymax; /* 0x010004 maximum dot coords */
46 volatile u32 vt_vsync; /* 0x010008 vsync on/off */
47 volatile u32 vt_hsync; /* 0x01000c hsync on/off */
48 volatile u32 vt_vblank; /* 0x010010 vblank on/off */
49 volatile u32 vt_hblank; /* 0x010014 hblank on/off */
50 volatile u32 vt_flags; /* 0x010018 polarity of vt signals */
51 volatile u32 vt_f2rf_lock; /* 0x01001c f2rf & framelck y coord */
52 volatile u32 vt_intr01; /* 0x010020 intr 0,1 y coords */
53 volatile u32 vt_intr23; /* 0x010024 intr 2,3 y coords */
54 volatile u32 fp_hdrv; /* 0x010028 flat panel hdrv on/off */
55 volatile u32 fp_vdrv; /* 0x01002c flat panel vdrv on/off */
56 volatile u32 fp_de; /* 0x010030 flat panel de on/off */
57 volatile u32 vt_hpixen; /* 0x010034 intrnl horiz pixel on/off*/
58 volatile u32 vt_vpixen; /* 0x010038 intrnl vert pixel on/off */
59 volatile u32 vt_hcmap; /* 0x01003c cmap write (horiz) */
60 volatile u32 vt_vcmap; /* 0x010040 cmap write (vert) */
61 volatile u32 did_start_xy; /* 0x010044 eol/f did/xy reset val */
62 volatile u32 crs_start_xy; /* 0x010048 eol/f crs/xy reset val */
63 volatile u32 vc_start_xy; /* 0x01004c eol/f vc/xy reset val */
64
65 char _pad1[ 0x020000 - 0x010050 ];
66
67 volatile u32 ovr_width_tile; /* 0x020000 overlay plane ctrl 0 */
68 volatile u32 ovr_inhwctrl; /* 0x020004 overlay plane ctrl 1 */
69 volatile u32 ovr_control; /* 0x020008 overlay plane ctrl 1 */
70
71 char _pad2[ 0x030000 - 0x02000C ];
72
73 volatile u32 frm_size_tile; /* 0x030000 normal plane ctrl 0 */
74 volatile u32 frm_size_pixel; /* 0x030004 normal plane ctrl 1 */
75 volatile u32 frm_inhwctrl; /* 0x030008 normal plane ctrl 2 */
76 volatile u32 frm_control; /* 0x03000C normal plane ctrl 3 */
77
78 char _pad3[ 0x040000 - 0x030010 ];
79
80 volatile u32 did_inhwctrl; /* 0x040000 DID control */
81 volatile u32 did_control; /* 0x040004 DID shadow */
82
83 char _pad4[ 0x048000 - 0x040008 ];
84
85 volatile u32 mode_regs[32]; /* 0x048000 - 0x04807c WID table */
86
87 char _pad5[ 0x050000 - 0x048080 ];
88
89 volatile u32 cmap[6144]; /* 0x050000 - 0x055ffc color map */
90
91 char _pad6[ 0x058000 - 0x056000 ];
92
93 volatile u32 cm_fifo; /* 0x058000 color map fifo status */
94
95 char _pad7[ 0x060000 - 0x058004 ];
96
97 volatile u32 gmap[256]; /* 0x060000 - 0x0603fc gamma map */
98
99 char _pad8[ 0x068000 - 0x060400 ];
100
101 volatile u32 gmap10[1024]; /* 0x068000 - 0x068ffc gamma map */
102
103 char _pad9[ 0x070000 - 0x069000 ];
104
105 volatile u32 crs_pos; /* 0x070000 cusror control 0 */
106 volatile u32 crs_ctl; /* 0x070004 cusror control 1 */
107 volatile u32 crs_cmap[3]; /* 0x070008 - 0x070010 crs cmap */
108
109 char _pad10[ 0x078000 - 0x070014 ];
110
111 volatile u32 crs_glyph[64]; /* 0x078000 - 0x0780fc crs glyph */
112
113 char _pad11[ 0x080000 - 0x078100 ];
114
115 volatile u32 vc_0; /* 0x080000 video capture crtl 0 */
116 volatile u32 vc_1; /* 0x080004 video capture crtl 1 */
117 volatile u32 vc_2; /* 0x080008 video capture crtl 2 */
118 volatile u32 vc_3; /* 0x08000c video capture crtl 3 */
119 volatile u32 vc_4; /* 0x080010 video capture crtl 3 */
120 volatile u32 vc_5; /* 0x080014 video capture crtl 3 */
121 volatile u32 vc_6; /* 0x080018 video capture crtl 3 */
122 volatile u32 vc_7; /* 0x08001c video capture crtl 3 */
123 volatile u32 vc_8; /* 0x08000c video capture crtl 3 */
124};
125
126/* Bit mask information */
127
128#define DBE_CTRLSTAT_CHIPID_MSB 3
129#define DBE_CTRLSTAT_CHIPID_LSB 0
130#define DBE_CTRLSTAT_SENSE_N_MSB 4
131#define DBE_CTRLSTAT_SENSE_N_LSB 4
132#define DBE_CTRLSTAT_PCLKSEL_MSB 29
133#define DBE_CTRLSTAT_PCLKSEL_LSB 28
134
135#define DBE_DOTCLK_M_MSB 7
136#define DBE_DOTCLK_M_LSB 0
137#define DBE_DOTCLK_N_MSB 13
138#define DBE_DOTCLK_N_LSB 8
139#define DBE_DOTCLK_P_MSB 15
140#define DBE_DOTCLK_P_LSB 14
141#define DBE_DOTCLK_RUN_MSB 20
142#define DBE_DOTCLK_RUN_LSB 20
143
144#define DBE_VT_XY_VT_FREEZE_MSB 31
145#define DBE_VT_XY_VT_FREEZE_LSB 31
146
147#define DBE_FP_VDRV_FP_VDRV_ON_MSB 23
148#define DBE_FP_VDRV_FP_VDRV_ON_LSB 12
149#define DBE_FP_VDRV_FP_VDRV_OFF_MSB 11
150#define DBE_FP_VDRV_FP_VDRV_OFF_LSB 0
151
152#define DBE_FP_HDRV_FP_HDRV_ON_MSB 23
153#define DBE_FP_HDRV_FP_HDRV_ON_LSB 12
154#define DBE_FP_HDRV_FP_HDRV_OFF_MSB 11
155#define DBE_FP_HDRV_FP_HDRV_OFF_LSB 0
156
157#define DBE_FP_DE_FP_DE_ON_MSB 23
158#define DBE_FP_DE_FP_DE_ON_LSB 12
159#define DBE_FP_DE_FP_DE_OFF_MSB 11
160#define DBE_FP_DE_FP_DE_OFF_LSB 0
161
162#define DBE_VT_VSYNC_VT_VSYNC_ON_MSB 23
163#define DBE_VT_VSYNC_VT_VSYNC_ON_LSB 12
164#define DBE_VT_VSYNC_VT_VSYNC_OFF_MSB 11
165#define DBE_VT_VSYNC_VT_VSYNC_OFF_LSB 0
166
167#define DBE_VT_HSYNC_VT_HSYNC_ON_MSB 23
168#define DBE_VT_HSYNC_VT_HSYNC_ON_LSB 12
169#define DBE_VT_HSYNC_VT_HSYNC_OFF_MSB 11
170#define DBE_VT_HSYNC_VT_HSYNC_OFF_LSB 0
171
172#define DBE_VT_VBLANK_VT_VBLANK_ON_MSB 23
173#define DBE_VT_VBLANK_VT_VBLANK_ON_LSB 12
174#define DBE_VT_VBLANK_VT_VBLANK_OFF_MSB 11
175#define DBE_VT_VBLANK_VT_VBLANK_OFF_LSB 0
176
177#define DBE_VT_HBLANK_VT_HBLANK_ON_MSB 23
178#define DBE_VT_HBLANK_VT_HBLANK_ON_LSB 12
179#define DBE_VT_HBLANK_VT_HBLANK_OFF_MSB 11
180#define DBE_VT_HBLANK_VT_HBLANK_OFF_LSB 0
181
182#define DBE_VT_FLAGS_VDRV_INVERT_MSB 0
183#define DBE_VT_FLAGS_VDRV_INVERT_LSB 0
184#define DBE_VT_FLAGS_HDRV_INVERT_MSB 2
185#define DBE_VT_FLAGS_HDRV_INVERT_LSB 2
186
187#define DBE_VT_VCMAP_VT_VCMAP_ON_MSB 23
188#define DBE_VT_VCMAP_VT_VCMAP_ON_LSB 12
189#define DBE_VT_VCMAP_VT_VCMAP_OFF_MSB 11
190#define DBE_VT_VCMAP_VT_VCMAP_OFF_LSB 0
191
192#define DBE_VT_HCMAP_VT_HCMAP_ON_MSB 23
193#define DBE_VT_HCMAP_VT_HCMAP_ON_LSB 12
194#define DBE_VT_HCMAP_VT_HCMAP_OFF_MSB 11
195#define DBE_VT_HCMAP_VT_HCMAP_OFF_LSB 0
196
197#define DBE_VT_XYMAX_VT_MAXX_MSB 11
198#define DBE_VT_XYMAX_VT_MAXX_LSB 0
199#define DBE_VT_XYMAX_VT_MAXY_MSB 23
200#define DBE_VT_XYMAX_VT_MAXY_LSB 12
201
202#define DBE_VT_HPIXEN_VT_HPIXEN_ON_MSB 23
203#define DBE_VT_HPIXEN_VT_HPIXEN_ON_LSB 12
204#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_MSB 11
205#define DBE_VT_HPIXEN_VT_HPIXEN_OFF_LSB 0
206
207#define DBE_VT_VPIXEN_VT_VPIXEN_ON_MSB 23
208#define DBE_VT_VPIXEN_VT_VPIXEN_ON_LSB 12
209#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_MSB 11
210#define DBE_VT_VPIXEN_VT_VPIXEN_OFF_LSB 0
211
212#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_MSB 0
213#define DBE_OVR_CONTROL_OVR_DMA_ENABLE_LSB 0
214
215#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_MSB 0
216#define DBE_OVR_INHWCTRL_OVR_DMA_ENABLE_LSB 0
217
218#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_MSB 13
219#define DBE_OVR_WIDTH_TILE_OVR_FIFO_RESET_LSB 13
220
221#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_MSB 0
222#define DBE_FRM_CONTROL_FRM_DMA_ENABLE_LSB 0
223#define DBE_FRM_CONTROL_FRM_TILE_PTR_MSB 31
224#define DBE_FRM_CONTROL_FRM_TILE_PTR_LSB 9
225#define DBE_FRM_CONTROL_FRM_LINEAR_MSB 1
226#define DBE_FRM_CONTROL_FRM_LINEAR_LSB 1
227
228#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_MSB 0
229#define DBE_FRM_INHWCTRL_FRM_DMA_ENABLE_LSB 0
230
231#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_MSB 12
232#define DBE_FRM_SIZE_TILE_FRM_WIDTH_TILE_LSB 5
233#define DBE_FRM_SIZE_TILE_FRM_RHS_MSB 4
234#define DBE_FRM_SIZE_TILE_FRM_RHS_LSB 0
235#define DBE_FRM_SIZE_TILE_FRM_DEPTH_MSB 14
236#define DBE_FRM_SIZE_TILE_FRM_DEPTH_LSB 13
237#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_MSB 15
238#define DBE_FRM_SIZE_TILE_FRM_FIFO_RESET_LSB 15
239
240#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_MSB 31
241#define DBE_FRM_SIZE_PIXEL_FB_HEIGHT_PIX_LSB 16
242
243#define DBE_DID_CONTROL_DID_DMA_ENABLE_MSB 0
244#define DBE_DID_CONTROL_DID_DMA_ENABLE_LSB 0
245#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_MSB 0
246#define DBE_DID_INHWCTRL_DID_DMA_ENABLE_LSB 0
247
248#define DBE_DID_START_XY_DID_STARTY_MSB 23
249#define DBE_DID_START_XY_DID_STARTY_LSB 12
250#define DBE_DID_START_XY_DID_STARTX_MSB 11
251#define DBE_DID_START_XY_DID_STARTX_LSB 0
252
253#define DBE_CRS_START_XY_CRS_STARTY_MSB 23
254#define DBE_CRS_START_XY_CRS_STARTY_LSB 12
255#define DBE_CRS_START_XY_CRS_STARTX_MSB 11
256#define DBE_CRS_START_XY_CRS_STARTX_LSB 0
257
258#define DBE_WID_TYP_MSB 4
259#define DBE_WID_TYP_LSB 2
260#define DBE_WID_BUF_MSB 1
261#define DBE_WID_BUF_LSB 0
262
263#define DBE_VC_START_XY_VC_STARTY_MSB 23
264#define DBE_VC_START_XY_VC_STARTY_LSB 12
265#define DBE_VC_START_XY_VC_STARTX_MSB 11
266#define DBE_VC_START_XY_VC_STARTX_LSB 0
267
268/* Constants */
269
270#define DBE_FRM_DEPTH_8 0
271#define DBE_FRM_DEPTH_16 1
272#define DBE_FRM_DEPTH_32 2
273
274#define DBE_CMODE_I8 0
275#define DBE_CMODE_I12 1
276#define DBE_CMODE_RG3B2 2
277#define DBE_CMODE_RGB4 3
278#define DBE_CMODE_ARGB5 4
279#define DBE_CMODE_RGB8 5
280#define DBE_CMODE_RGBA5 6
281#define DBE_CMODE_RGB10 7
282
283#define DBE_BMODE_BOTH 3
284
285#define DBE_CRS_MAGIC 54
286
287#define DBE_CLOCK_REF_KHZ 27000
288
289/* Config Register (DBE Only) Definitions */
290
291#define DBE_CONFIG_VDAC_ENABLE 0x00000001
292#define DBE_CONFIG_VDAC_GSYNC 0x00000002
293#define DBE_CONFIG_VDAC_PBLANK 0x00000004
294#define DBE_CONFIG_FPENABLE 0x00000008
295#define DBE_CONFIG_LENDIAN 0x00000020
296#define DBE_CONFIG_TILEHIST 0x00000040
297#define DBE_CONFIG_EXT_ADDR 0x00000080
298
299#define DBE_CONFIG_FBDEV ( DBE_CONFIG_VDAC_ENABLE | \
300 DBE_CONFIG_VDAC_GSYNC | \
301 DBE_CONFIG_VDAC_PBLANK | \
302 DBE_CONFIG_LENDIAN | \
303 DBE_CONFIG_EXT_ADDR )
304
305/*
306 * Available Video Timings and Corresponding Indices
307 */
308
309typedef enum {
310 DBE_VT_640_480_60,
311
312 DBE_VT_800_600_60,
313 DBE_VT_800_600_75,
314 DBE_VT_800_600_120,
315
316 DBE_VT_1024_768_50,
317 DBE_VT_1024_768_60,
318 DBE_VT_1024_768_75,
319 DBE_VT_1024_768_85,
320 DBE_VT_1024_768_120,
321
322 DBE_VT_1280_1024_50,
323 DBE_VT_1280_1024_60,
324 DBE_VT_1280_1024_75,
325 DBE_VT_1280_1024_85,
326
327 DBE_VT_1600_1024_53,
328 DBE_VT_1600_1024_60,
329
330 DBE_VT_1600_1200_50,
331 DBE_VT_1600_1200_60,
332 DBE_VT_1600_1200_75,
333
334 DBE_VT_1920_1080_50,
335 DBE_VT_1920_1080_60,
336 DBE_VT_1920_1080_72,
337
338 DBE_VT_1920_1200_50,
339 DBE_VT_1920_1200_60,
340 DBE_VT_1920_1200_66,
341
342 DBE_VT_UNKNOWN
343} dbe_timing_t;
344
345
346
347/*
348 * Crime Video Timing Data Structure
349 */
350
351struct dbe_timing_info
352{
353 dbe_timing_t type;
354 int flags;
355 short width; /* Monitor resolution */
356 short height;
357 int fields_sec; /* fields/sec (Hz -3 dec. places */
358 int cfreq; /* pixel clock frequency (MHz -3 dec. places) */
359 short htotal; /* Horizontal total pixels */
360 short hblank_start; /* Horizontal blank start */
361 short hblank_end; /* Horizontal blank end */
362 short hsync_start; /* Horizontal sync start */
363 short hsync_end; /* Horizontal sync end */
364 short vtotal; /* Vertical total lines */
365 short vblank_start; /* Vertical blank start */
366 short vblank_end; /* Vertical blank end */
367 short vsync_start; /* Vertical sync start */
368 short vsync_end; /* Vertical sync end */
369 short pll_m; /* PLL M parameter */
370 short pll_n; /* PLL P parameter */
371 short pll_p; /* PLL N parameter */
372};
373
374/* Defines for dbe_vof_info_t flags */
375
376#define DBE_VOF_UNKNOWNMON 1
377#define DBE_VOF_STEREO 2
378#define DBE_VOF_DO_GENSYNC 4 /* enable incoming sync */
379#define DBE_VOF_SYNC_ON_GREEN 8 /* sync on green */
380#define DBE_VOF_FLATPANEL 0x1000 /* FLATPANEL Timing */
381#define DBE_VOF_MAGICKEY 0x2000 /* Backdoor key */
382
383/*
384 * DBE Timing Tables
385 */
386
387#ifdef INCLUDE_TIMING_TABLE_DATA
388struct dbe_timing_info dbeVTimings[] = {
389 {
390 DBE_VT_640_480_60,
391 /* flags, width, height, fields_sec, cfreq */
392 0, 640, 480, 59940, 25175,
393 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
394 800, 640, 800, 656, 752,
395 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
396 525, 480, 525, 490, 492,
397 /* pll_m, pll_n, pll_p */
398 15, 2, 3
399 },
400
401 {
402 DBE_VT_800_600_60,
403 /* flags, width, height, fields_sec, cfreq */
404 0, 800, 600, 60317, 40000,
405 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
406 1056, 800, 1056, 840, 968,
407 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
408 628, 600, 628, 601, 605,
409 /* pll_m, pll_n, pll_p */
410 3, 1, 1
411 },
412
413 {
414 DBE_VT_800_600_75,
415 /* flags, width, height, fields_sec, cfreq */
416 0, 800, 600, 75000, 49500,
417 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
418 1056, 800, 1056, 816, 896,
419 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
420 625, 600, 625, 601, 604,
421 /* pll_m, pll_n, pll_p */
422 11, 3, 1
423 },
424
425 {
426 DBE_VT_800_600_120,
427 /* flags, width, height, fields_sec, cfreq */
428 DBE_VOF_STEREO, 800, 600, 119800, 82978,
429 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
430 1040, 800, 1040, 856, 976,
431 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
432 666, 600, 666, 637, 643,
433 /* pll_m, pll_n, pll_p */
434 31, 5, 1
435 },
436
437 {
438 DBE_VT_1024_768_50,
439 /* flags, width, height, fields_sec, cfreq */
440 0, 1024, 768, 50000, 54163,
441 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
442 1344, 1024, 1344, 1048, 1184,
443 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
444 806, 768, 806, 771, 777,
445 /* pll_m, pll_n, pll_p */
446 4, 1, 1
447 },
448
449 {
450 DBE_VT_1024_768_60,
451 /* flags, width, height, fields_sec, cfreq */
452 0, 1024, 768, 60004, 65000,
453 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
454 1344, 1024, 1344, 1048, 1184,
455 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
456 806, 768, 806, 771, 777,
457 /* pll_m, pll_n, pll_p */
458 12, 5, 0
459 },
460
461 {
462 DBE_VT_1024_768_75,
463 /* flags, width, height, fields_sec, cfreq */
464 0, 1024, 768, 75029, 78750,
465 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
466 1312, 1024, 1312, 1040, 1136,
467 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
468 800, 768, 800, 769, 772,
469 /* pll_m, pll_n, pll_p */
470 29, 5, 1
471 },
472
473 {
474 DBE_VT_1024_768_85,
475 /* flags, width, height, fields_sec, cfreq */
476 0, 1024, 768, 84997, 94500,
477 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
478 1376, 1024, 1376, 1072, 1168,
479 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
480 808, 768, 808, 769, 772,
481 /* pll_m, pll_n, pll_p */
482 7, 2, 0
483 },
484
485 {
486 DBE_VT_1024_768_120,
487 /* flags, width, height, fields_sec, cfreq */
488 DBE_VOF_STEREO, 1024, 768, 119800, 133195,
489 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
490 1376, 1024, 1376, 1072, 1168,
491 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
492 808, 768, 808, 769, 772,
493 /* pll_m, pll_n, pll_p */
494 5, 1, 0
495 },
496
497 {
498 DBE_VT_1280_1024_50,
499 /* flags, width, height, fields_sec, cfreq */
500 0, 1280, 1024, 50000, 89460,
501 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
502 1680, 1280, 1680, 1360, 1480,
503 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
504 1065, 1024, 1065, 1027, 1030,
505 /* pll_m, pll_n, pll_p */
506 10, 3, 0
507 },
508
509 {
510 DBE_VT_1280_1024_60,
511 /* flags, width, height, fields_sec, cfreq */
512 0, 1280, 1024, 60020, 108000,
513 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
514 1688, 1280, 1688, 1328, 1440,
515 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
516 1066, 1024, 1066, 1025, 1028,
517 /* pll_m, pll_n, pll_p */
518 4, 1, 0
519 },
520
521 {
522 DBE_VT_1280_1024_75,
523 /* flags, width, height, fields_sec, cfreq */
524 0, 1280, 1024, 75025, 135000,
525 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
526 1688, 1280, 1688, 1296, 1440,
527 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
528 1066, 1024, 1066, 1025, 1028,
529 /* pll_m, pll_n, pll_p */
530 5, 1, 0
531 },
532
533 {
534 DBE_VT_1280_1024_85,
535 /* flags, width, height, fields_sec, cfreq */
536 0, 1280, 1024, 85024, 157500,
537 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
538 1728, 1280, 1728, 1344, 1504,
539 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
540 1072, 1024, 1072, 1025, 1028,
541 /* pll_m, pll_n, pll_p */
542 29, 5, 0
543 },
544
545 {
546 DBE_VT_1600_1024_53,
547 /* flags, width, height, fields_sec, cfreq */
548 DBE_VOF_FLATPANEL | DBE_VOF_MAGICKEY,
549 1600, 1024, 53000, 107447,
550 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
551 1900, 1600, 1900, 1630, 1730,
552 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
553 1067, 1024, 1067, 1027, 1030,
554 /* pll_m, pll_n, pll_p */
555 4, 1, 0
556 },
557
558 {
559 DBE_VT_1600_1024_60,
560 /* flags, width, height, fields_sec, cfreq */
561 DBE_VOF_FLATPANEL, 1600, 1024, 60000, 106913,
562 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
563 1670, 1600, 1670, 1630, 1650,
564 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
565 1067, 1024, 1067, 1027, 1030,
566 /* pll_m, pll_n, pll_p */
567 4, 1, 0
568 },
569
570 {
571 DBE_VT_1600_1200_50,
572 /* flags, width, height, fields_sec, cfreq */
573 0, 1600, 1200, 50000, 130500,
574 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
575 2088, 1600, 2088, 1644, 1764,
576 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
577 1250, 1200, 1250, 1205, 1211,
578 /* pll_m, pll_n, pll_p */
579 24, 5, 0
580 },
581
582 {
583 DBE_VT_1600_1200_60,
584 /* flags, width, height, fields_sec, cfreq */
585 0, 1600, 1200, 59940, 162000,
586 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
587 2160, 1600, 2160, 1644, 1856,
588 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
589 1250, 1200, 1250, 1201, 1204,
590 /* pll_m, pll_n, pll_p */
591 6, 1, 0
592 },
593
594 {
595 DBE_VT_1600_1200_75,
596 /* flags, width, height, fields_sec, cfreq */
597 0, 1600, 1200, 75000, 202500,
598 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
599 2160, 1600, 2160, 1644, 1856,
600 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
601 1250, 1200, 1250, 1201, 1204,
602 /* pll_m, pll_n, pll_p */
603 15, 2, 0
604 },
605
606 {
607 DBE_VT_1920_1080_50,
608 /* flags, width, height, fields_sec, cfreq */
609 0, 1920, 1080, 50000, 133200,
610 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
611 2368, 1920, 2368, 1952, 2096,
612 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
613 1125, 1080, 1125, 1083, 1086,
614 /* pll_m, pll_n, pll_p */
615 5, 1, 0
616 },
617
618 {
619 DBE_VT_1920_1080_60,
620 /* flags, width, height, fields_sec, cfreq */
621 0, 1920, 1080, 59940, 159840,
622 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
623 2368, 1920, 2368, 1952, 2096,
624 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
625 1125, 1080, 1125, 1083, 1086,
626 /* pll_m, pll_n, pll_p */
627 6, 1, 0
628 },
629
630 {
631 DBE_VT_1920_1080_72,
632 /* flags, width, height, fields_sec, cfreq */
633 0, 1920, 1080, 72000, 216023,
634 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
635 2560, 1920, 2560, 1968, 2184,
636 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
637 1172, 1080, 1172, 1083, 1086,
638 /* pll_m, pll_n, pll_p */
639 8, 1, 0
640 },
641
642 {
643 DBE_VT_1920_1200_50,
644 /* flags, width, height, fields_sec, cfreq */
645 0, 1920, 1200, 50000, 161500,
646 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
647 2584, 1920, 2584, 1984, 2240,
648 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
649 1250, 1200, 1250, 1203, 1206,
650 /* pll_m, pll_n, pll_p */
651 6, 1, 0
652 },
653
654 {
655 DBE_VT_1920_1200_60,
656 /* flags, width, height, fields_sec, cfreq */
657 0, 1920, 1200, 59940, 193800,
658 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
659 2584, 1920, 2584, 1984, 2240,
660 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
661 1250, 1200, 1250, 1203, 1206,
662 /* pll_m, pll_n, pll_p */
663 29, 4, 0
664 },
665
666 {
667 DBE_VT_1920_1200_66,
668 /* flags, width, height, fields_sec, cfreq */
669 0, 1920, 1200, 66000, 213180,
670 /* htotal, hblank_start, hblank_end, hsync_start, hsync_end */
671 2584, 1920, 2584, 1984, 2240,
672 /* vtotal, vblank_start, vblank_end, vsync_start, vsync_end */
673 1250, 1200, 1250, 1203, 1206,
674 /* pll_m, pll_n, pll_p */
675 8, 1, 0
676 }
677};
678
679#endif // INCLUDE_TIMING_TABLE_DATA
680
681#endif // ! __SGIVWFB_H__
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 21:34:30 -0500