diff options
| author | David S. Miller <davem@davemloft.net> | 2009-02-15 02:12:00 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-02-15 02:12:00 -0500 |
| commit | 5e30589521518bff36fd2638b3c3d69679c50436 (patch) | |
| tree | 6ac985658a06b0787e4354d0d16d380ea9b16a5a /include/video/radeon.h | |
| parent | ac178ef0ae9eb44fd527d87aa9b6394e05f56e1f (diff) | |
| parent | d2f8d7ee1a9b4650b4e43325b321801264f7c37a (diff) | |
Merge branch 'master' of /home/davem/src/GIT/linux-2.6/
Conflicts:
drivers/net/wireless/iwlwifi/iwl-agn.c
drivers/net/wireless/iwlwifi/iwl3945-base.c
Diffstat (limited to 'include/video/radeon.h')
| -rw-r--r-- | include/video/radeon.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/video/radeon.h b/include/video/radeon.h index 1cd09cc5b169..e072b16b39ab 100644 --- a/include/video/radeon.h +++ b/include/video/radeon.h | |||
| @@ -11,13 +11,13 @@ | |||
| 11 | #define HI_STAT 0x004C | 11 | #define HI_STAT 0x004C |
| 12 | #define BUS_CNTL1 0x0034 | 12 | #define BUS_CNTL1 0x0034 |
| 13 | #define I2C_CNTL_1 0x0094 | 13 | #define I2C_CNTL_1 0x0094 |
| 14 | #define CONFIG_CNTL 0x00E0 | 14 | #define CNFG_CNTL 0x00E0 |
| 15 | #define CONFIG_MEMSIZE 0x00F8 | 15 | #define CNFG_MEMSIZE 0x00F8 |
| 16 | #define CONFIG_APER_0_BASE 0x0100 | 16 | #define CNFG_APER_0_BASE 0x0100 |
| 17 | #define CONFIG_APER_1_BASE 0x0104 | 17 | #define CNFG_APER_1_BASE 0x0104 |
| 18 | #define CONFIG_APER_SIZE 0x0108 | 18 | #define CNFG_APER_SIZE 0x0108 |
| 19 | #define CONFIG_REG_1_BASE 0x010C | 19 | #define CNFG_REG_1_BASE 0x010C |
| 20 | #define CONFIG_REG_APER_SIZE 0x0110 | 20 | #define CNFG_REG_APER_SIZE 0x0110 |
| 21 | #define PAD_AGPINPUT_DELAY 0x0164 | 21 | #define PAD_AGPINPUT_DELAY 0x0164 |
| 22 | #define PAD_CTLR_STRENGTH 0x0168 | 22 | #define PAD_CTLR_STRENGTH 0x0168 |
| 23 | #define PAD_CTLR_UPDATE 0x016C | 23 | #define PAD_CTLR_UPDATE 0x016C |
| @@ -509,7 +509,7 @@ | |||
| 509 | /* CLOCK_CNTL_INDEX bit constants */ | 509 | /* CLOCK_CNTL_INDEX bit constants */ |
| 510 | #define PLL_WR_EN 0x00000080 | 510 | #define PLL_WR_EN 0x00000080 |
| 511 | 511 | ||
| 512 | /* CONFIG_CNTL bit constants */ | 512 | /* CNFG_CNTL bit constants */ |
| 513 | #define CFG_VGA_RAM_EN 0x00000100 | 513 | #define CFG_VGA_RAM_EN 0x00000100 |
| 514 | #define CFG_ATI_REV_ID_MASK (0xf << 16) | 514 | #define CFG_ATI_REV_ID_MASK (0xf << 16) |
| 515 | #define CFG_ATI_REV_A11 (0 << 16) | 515 | #define CFG_ATI_REV_A11 (0 << 16) |
| @@ -980,7 +980,7 @@ | |||
| 980 | 980 | ||
| 981 | /* masks */ | 981 | /* masks */ |
| 982 | 982 | ||
| 983 | #define CONFIG_MEMSIZE_MASK 0x1f000000 | 983 | #define CNFG_MEMSIZE_MASK 0x1f000000 |
| 984 | #define MEM_CFG_TYPE 0x40000000 | 984 | #define MEM_CFG_TYPE 0x40000000 |
| 985 | #define DST_OFFSET_MASK 0x003fffff | 985 | #define DST_OFFSET_MASK 0x003fffff |
| 986 | #define DST_PITCH_MASK 0x3fc00000 | 986 | #define DST_PITCH_MASK 0x3fc00000 |